From bfa9457b4c72fdf0c410042dbee6d05673c8f6af Mon Sep 17 00:00:00 2001 From: Furrtek Date: Fri, 23 Dec 2022 09:28:21 +0100 Subject: [PATCH] ESL Blaster FW V2 (PP16 support) Updated python tools to support PP16 --- hardware/esl_blaster/{FW => FW01}/.cproject | 396 +- hardware/esl_blaster/{FW => FW01}/.mxproject | 28 +- hardware/esl_blaster/{FW => FW01}/.project | 60 +- .../Device/ST/STM32F0xx/Include/stm32f070x6.h | 11270 ++++++------ .../Device/ST/STM32F0xx/Include/stm32f0xx.h | 484 +- .../ST/STM32F0xx/Include/system_stm32f0xx.h | 242 +- .../Drivers/CMSIS/Include/arm_common_tables.h | 272 +- .../Drivers/CMSIS/Include/arm_const_structs.h | 158 +- .../Drivers/CMSIS/Include/arm_math.h | 14308 ++++++++-------- .../Drivers/CMSIS/Include/cmsis_armcc.h | 1468 +- .../Drivers/CMSIS/Include/cmsis_armcc_V6.h | 3600 ++-- .../Drivers/CMSIS/Include/cmsis_gcc.h | 2746 +-- .../Drivers/CMSIS/Include/core_cm0.h | 1596 +- .../Drivers/CMSIS/Include/core_cm0plus.h | 1828 +- .../Drivers/CMSIS/Include/core_cm3.h | 3526 ++-- .../Drivers/CMSIS/Include/core_cm4.h | 3874 ++--- .../Drivers/CMSIS/Include/core_cm7.h | 5024 +++--- .../Drivers/CMSIS/Include/core_cmFunc.h | 174 +- .../Drivers/CMSIS/Include/core_cmInstr.h | 174 +- .../Drivers/CMSIS/Include/core_cmSimd.h | 192 +- .../Drivers/CMSIS/Include/core_sc000.h | 1852 +- .../Drivers/CMSIS/Include/core_sc300.h | 3490 ++-- .../Inc/Legacy/stm32_hal_legacy.h | 7066 ++++---- .../STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h | 1124 +- .../Inc/stm32f0xx_hal_cortex.h | 298 +- .../Inc/stm32f0xx_hal_def.h | 364 +- .../Inc/stm32f0xx_hal_dma.h | 1158 +- .../Inc/stm32f0xx_hal_dma_ex.h | 1654 +- .../Inc/stm32f0xx_hal_flash.h | 738 +- .../Inc/stm32f0xx_hal_flash_ex.h | 928 +- .../Inc/stm32f0xx_hal_gpio.h | 624 +- .../Inc/stm32f0xx_hal_gpio_ex.h | 1632 +- .../Inc/stm32f0xx_hal_i2c.h | 1416 +- .../Inc/stm32f0xx_hal_i2c_ex.h | 376 +- .../Inc/stm32f0xx_hal_pcd.h | 1670 +- .../Inc/stm32f0xx_hal_pcd_ex.h | 196 +- .../Inc/stm32f0xx_hal_pwr.h | 410 +- .../Inc/stm32f0xx_hal_pwr_ex.h | 950 +- .../Inc/stm32f0xx_hal_rcc.h | 3404 ++-- .../Inc/stm32f0xx_hal_rcc_ex.h | 4202 ++--- .../Inc/stm32f0xx_hal_tim.h | 3660 ++-- .../Inc/stm32f0xx_hal_tim_ex.h | 650 +- .../Inc/stm32f0xx_ll_bus.h | 1722 +- .../Inc/stm32f0xx_ll_cortex.h | 672 +- .../Inc/stm32f0xx_ll_crs.h | 1598 +- .../Inc/stm32f0xx_ll_dma.h | 4448 ++--- .../Inc/stm32f0xx_ll_exti.h | 2064 +-- .../Inc/stm32f0xx_ll_gpio.h | 1910 +-- .../Inc/stm32f0xx_ll_pwr.h | 1136 +- .../Inc/stm32f0xx_ll_rcc.h | 4514 ++--- .../Inc/stm32f0xx_ll_system.h | 3736 ++-- .../Inc/stm32f0xx_ll_utils.h | 574 +- .../STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c | 934 +- .../Src/stm32f0xx_hal_cortex.c | 714 +- .../Src/stm32f0xx_hal_dma.c | 1810 +- .../Src/stm32f0xx_hal_flash.c | 1420 +- .../Src/stm32f0xx_hal_flash_ex.c | 2000 +-- .../Src/stm32f0xx_hal_gpio.c | 1086 +- .../Src/stm32f0xx_hal_i2c.c | 9736 +++++------ .../Src/stm32f0xx_hal_i2c_ex.c | 694 +- .../Src/stm32f0xx_hal_pcd.c | 2808 +-- .../Src/stm32f0xx_hal_pcd_ex.c | 308 +- .../Src/stm32f0xx_hal_pwr.c | 940 +- .../Src/stm32f0xx_hal_pwr_ex.c | 580 +- .../Src/stm32f0xx_hal_rcc.c | 2664 +-- .../Src/stm32f0xx_hal_rcc_ex.c | 1960 +-- .../Src/stm32f0xx_hal_tim.c | 10990 ++++++------ .../Src/stm32f0xx_hal_tim_ex.c | 4024 ++--- .../Src/stm32f0xx_ll_exti.c | 476 +- .../Src/stm32f0xx_ll_gpio.c | 558 +- .../Src/stm32f0xx_ll_rcc.c | 1198 +- .../Src/stm32f0xx_ll_utils.c | 1240 +- .../esl_blaster/{FW => FW01}/ESLBlaster.ioc | 204 +- hardware/esl_blaster/{FW => FW01}/Inc/gpio.h | 114 +- hardware/esl_blaster/{FW => FW01}/Inc/main.h | 98 +- .../{FW => FW01}/Inc/stm32_assert.h | 106 +- .../{FW => FW01}/Inc/stm32f0xx_hal_conf.h | 646 +- .../{FW => FW01}/Inc/stm32f0xx_it.h | 132 +- .../esl_blaster/{FW => FW01}/Inc/usb_device.h | 210 +- .../{FW => FW01}/Inc/usbd_cdc_if.h | 260 +- .../esl_blaster/{FW => FW01}/Inc/usbd_conf.h | 350 +- .../esl_blaster/{FW => FW01}/Inc/usbd_desc.h | 102 +- .../Class/CDC/Inc/usbd_cdc.h | 358 +- .../Class/CDC/Src/usbd_cdc.c | 1850 +- .../Core/Inc/usbd_core.h | 334 +- .../Core/Inc/usbd_ctlreq.h | 226 +- .../Core/Inc/usbd_def.h | 660 +- .../Core/Inc/usbd_ioreq.h | 256 +- .../Core/Src/usbd_core.c | 1130 +- .../Core/Src/usbd_ctlreq.c | 1192 +- .../Core/Src/usbd_ioreq.c | 472 +- .../Release/ESLBlaster.bin} | Bin .../esl_blaster/FW01/Release/ESLBlaster.elf | Bin 0 -> 144920 bytes .../esl_blaster/FW01/Release/ESLBlaster.list | 6029 +++++++ .../esl_blaster/FW01/Release/ESLBlaster.map | 1472 ++ hardware/esl_blaster/FW01/Release/makefile | 75 + hardware/esl_blaster/FW01/Release/program.bat | 1 + .../esl_blaster/FW01/Release/readback.bat | 2 + .../{FW => FW01}/STM32F070F6PX_FLASH.ld | 0 hardware/esl_blaster/{FW => FW01}/Src/gpio.c | 108 +- hardware/esl_blaster/{FW => FW01}/Src/main.c | 904 +- .../{FW => FW01}/Src/stm32f0xx_hal_msp.c | 172 +- .../{FW => FW01}/Src/stm32f0xx_it.c | 318 +- .../{FW => FW01}/Src/system_stm32f0xx.c | 666 +- .../esl_blaster/{FW => FW01}/Src/usb_device.c | 202 +- .../{FW => FW01}/Src/usbd_cdc_if.c | 368 +- .../esl_blaster/{FW => FW01}/Src/usbd_conf.c | 1300 +- .../esl_blaster/{FW => FW01}/Src/usbd_desc.c | 536 +- .../Startup/startup_stm32f070f6px.s | 614 +- .../FW01/dfu-util-0.9-win64/README.txt | 26 + .../FW01/dfu-util-0.9-win64/dfu-prefix.exe | Bin 0 -> 178765 bytes .../FW01/dfu-util-0.9-win64/dfu-suffix.exe | Bin 0 -> 179276 bytes .../dfu-util-0.9-win64/dfu-util-static.exe | Bin 0 -> 799602 bytes .../FW01/dfu-util-0.9-win64/dfu-util.exe | Bin 0 -> 290852 bytes .../FW01/dfu-util-0.9-win64/libusb-1.0.dll | Bin 0 -> 638611 bytes hardware/esl_blaster/FW02/.cproject | 398 + hardware/esl_blaster/FW02/.mxproject | 14 + hardware/esl_blaster/FW02/.project | 30 + .../FW02/.settings/language.settings.xml | 52 + .../FW02/.settings/stm32cubeide.project.prefs | 4 + .../Device/ST/STM32F0xx/Include/stm32f070x6.h | 5635 ++++++ .../Device/ST/STM32F0xx/Include/stm32f0xx.h | 242 + .../ST/STM32F0xx/Include/system_stm32f0xx.h | 121 + .../Drivers/CMSIS/Include/arm_common_tables.h | 136 + .../Drivers/CMSIS/Include/arm_const_structs.h | 79 + .../FW02/Drivers/CMSIS/Include/arm_math.h | 7154 ++++++++ .../FW02/Drivers/CMSIS/Include/cmsis_armcc.h | 734 + .../Drivers/CMSIS/Include/cmsis_armcc_V6.h | 1800 ++ .../FW02/Drivers/CMSIS/Include/cmsis_gcc.h | 1373 ++ .../FW02/Drivers/CMSIS/Include/core_cm0.h | 798 + .../FW02/Drivers/CMSIS/Include/core_cm0plus.h | 914 + .../FW02/Drivers/CMSIS/Include/core_cm3.h | 1763 ++ .../FW02/Drivers/CMSIS/Include/core_cm4.h | 1937 +++ .../FW02/Drivers/CMSIS/Include/core_cm7.h | 2512 +++ .../FW02/Drivers/CMSIS/Include/core_cmFunc.h | 87 + .../FW02/Drivers/CMSIS/Include/core_cmInstr.h | 87 + .../FW02/Drivers/CMSIS/Include/core_cmSimd.h | 96 + .../FW02/Drivers/CMSIS/Include/core_sc000.h | 926 + .../FW02/Drivers/CMSIS/Include/core_sc300.h | 1745 ++ .../Inc/Legacy/stm32_hal_legacy.h | 3533 ++++ .../STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h | 562 + .../Inc/stm32f0xx_hal_cortex.h | 149 + .../Inc/stm32f0xx_hal_def.h | 182 + .../Inc/stm32f0xx_hal_dma.h | 579 + .../Inc/stm32f0xx_hal_dma_ex.h | 827 + .../Inc/stm32f0xx_hal_flash.h | 369 + .../Inc/stm32f0xx_hal_flash_ex.h | 464 + .../Inc/stm32f0xx_hal_gpio.h | 312 + .../Inc/stm32f0xx_hal_gpio_ex.h | 816 + .../Inc/stm32f0xx_hal_i2c.h | 708 + .../Inc/stm32f0xx_hal_i2c_ex.h | 188 + .../Inc/stm32f0xx_hal_pcd.h | 835 + .../Inc/stm32f0xx_hal_pcd_ex.h | 98 + .../Inc/stm32f0xx_hal_pwr.h | 205 + .../Inc/stm32f0xx_hal_pwr_ex.h | 475 + .../Inc/stm32f0xx_hal_rcc.h | 1702 ++ .../Inc/stm32f0xx_hal_rcc_ex.h | 2101 +++ .../Inc/stm32f0xx_hal_tim.h | 1830 ++ .../Inc/stm32f0xx_hal_tim_ex.h | 325 + .../Inc/stm32f0xx_ll_bus.h | 861 + .../Inc/stm32f0xx_ll_cortex.h | 336 + .../Inc/stm32f0xx_ll_crs.h | 799 + .../Inc/stm32f0xx_ll_dma.h | 2224 +++ .../Inc/stm32f0xx_ll_exti.h | 1032 ++ .../Inc/stm32f0xx_ll_gpio.h | 955 ++ .../Inc/stm32f0xx_ll_pwr.h | 568 + .../Inc/stm32f0xx_ll_rcc.h | 2257 +++ .../Inc/stm32f0xx_ll_system.h | 1868 ++ .../Inc/stm32f0xx_ll_utils.h | 287 + .../STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c | 467 + .../Src/stm32f0xx_hal_cortex.c | 357 + .../Src/stm32f0xx_hal_dma.c | 905 + .../Src/stm32f0xx_hal_flash.c | 710 + .../Src/stm32f0xx_hal_flash_ex.c | 1000 ++ .../Src/stm32f0xx_hal_gpio.c | 543 + .../Src/stm32f0xx_hal_i2c.c | 4868 ++++++ .../Src/stm32f0xx_hal_i2c_ex.c | 347 + .../Src/stm32f0xx_hal_pcd.c | 1404 ++ .../Src/stm32f0xx_hal_pcd_ex.c | 154 + .../Src/stm32f0xx_hal_pwr.c | 470 + .../Src/stm32f0xx_hal_pwr_ex.c | 290 + .../Src/stm32f0xx_hal_rcc.c | 1332 ++ .../Src/stm32f0xx_hal_rcc_ex.c | 980 ++ .../Src/stm32f0xx_hal_tim.c | 5495 ++++++ .../Src/stm32f0xx_hal_tim_ex.c | 2012 +++ .../Src/stm32f0xx_ll_exti.c | 238 + .../Src/stm32f0xx_ll_gpio.c | 279 + .../Src/stm32f0xx_ll_rcc.c | 599 + .../Src/stm32f0xx_ll_utils.c | 620 + hardware/esl_blaster/FW02/Inc/gpio.h | 57 + hardware/esl_blaster/FW02/Inc/main.h | 49 + hardware/esl_blaster/FW02/Inc/stm32_assert.h | 53 + .../esl_blaster/FW02/Inc/stm32f0xx_hal_conf.h | 323 + hardware/esl_blaster/FW02/Inc/stm32f0xx_it.h | 66 + hardware/esl_blaster/FW02/Inc/usb_device.h | 105 + hardware/esl_blaster/FW02/Inc/usbd_cdc_if.h | 130 + hardware/esl_blaster/FW02/Inc/usbd_conf.h | 175 + hardware/esl_blaster/FW02/Inc/usbd_desc.h | 51 + .../Class/CDC/Inc/usbd_cdc.h | 179 + .../Class/CDC/Src/usbd_cdc.c | 925 + .../Core/Inc/usbd_core.h | 167 + .../Core/Inc/usbd_ctlreq.h | 113 + .../Core/Inc/usbd_def.h | 330 + .../Core/Inc/usbd_ioreq.h | 128 + .../Core/Src/usbd_core.c | 565 + .../Core/Src/usbd_ctlreq.c | 596 + .../Core/Src/usbd_ioreq.c | 236 + .../esl_blaster/FW02/Release/ESLBlaster02.bin | Bin 0 -> 13460 bytes .../esl_blaster/FW02/Release/ESLBlaster02.elf | Bin 0 -> 145080 bytes .../FW02/Release/ESLBlaster02.list | 6098 +++++++ .../esl_blaster/FW02/Release/ESLBlaster02.map | 1489 ++ hardware/esl_blaster/FW02/Release/makefile | 103 + hardware/esl_blaster/FW02/Release/program.bat | 1 + .../esl_blaster/FW02/STM32F070F6PX_FLASH.ld | 206 + hardware/esl_blaster/FW02/Src/gpio.c | 54 + hardware/esl_blaster/FW02/Src/main.c | 523 + .../esl_blaster/FW02/Src/stm32f0xx_hal_msp.c | 86 + hardware/esl_blaster/FW02/Src/stm32f0xx_it.c | 159 + .../esl_blaster/FW02/Src/system_stm32f0xx.c | 333 + hardware/esl_blaster/FW02/Src/usb_device.c | 101 + hardware/esl_blaster/FW02/Src/usbd_cdc_if.c | 184 + hardware/esl_blaster/FW02/Src/usbd_conf.c | 650 + hardware/esl_blaster/FW02/Src/usbd_desc.c | 268 + .../FW02/Startup/startup_stm32f070f6px.s | 307 + .../FW02/dfu-util-0.9-win64/README.txt | 26 + .../FW02/dfu-util-0.9-win64/dfu-prefix.exe | Bin 0 -> 178765 bytes .../FW02/dfu-util-0.9-win64/dfu-suffix.exe | Bin 0 -> 179276 bytes .../dfu-util-0.9-win64/dfu-util-static.exe | Bin 0 -> 799602 bytes .../FW02/dfu-util-0.9-win64/dfu-util.exe | Bin 0 -> 290852 bytes .../FW02/dfu-util-0.9-win64/libusb-1.0.dll | Bin 0 -> 638611 bytes hardware/esl_blaster/README.md | 7 +- tools_python/img2dm.py | 27 +- tools_python/pr.py | 12 +- tools_python/rawcmd.py | 15 +- 234 files changed, 187474 insertions(+), 85866 deletions(-) rename hardware/esl_blaster/{FW => FW01}/.cproject (99%) rename hardware/esl_blaster/{FW => FW01}/.mxproject (99%) rename hardware/esl_blaster/{FW => FW01}/.project (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/arm_common_tables.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/arm_const_structs.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/arm_math.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/cmsis_armcc.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/cmsis_armcc_V6.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/cmsis_gcc.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cm0.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cm0plus.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cm3.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cm4.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cm7.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cmFunc.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cmInstr.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_cmSimd.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_sc000.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/CMSIS/Include/core_sc300.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h (98%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c (97%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c (96%) rename hardware/esl_blaster/{FW => FW01}/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c (97%) rename hardware/esl_blaster/{FW => FW01}/ESLBlaster.ioc (97%) rename hardware/esl_blaster/{FW => FW01}/Inc/gpio.h (96%) rename hardware/esl_blaster/{FW => FW01}/Inc/main.h (96%) rename hardware/esl_blaster/{FW => FW01}/Inc/stm32_assert.h (97%) rename hardware/esl_blaster/{FW => FW01}/Inc/stm32f0xx_hal_conf.h (97%) rename hardware/esl_blaster/{FW => FW01}/Inc/stm32f0xx_it.h (96%) rename hardware/esl_blaster/{FW => FW01}/Inc/usb_device.h (95%) rename hardware/esl_blaster/{FW => FW01}/Inc/usbd_cdc_if.h (95%) rename hardware/esl_blaster/{FW => FW01}/Inc/usbd_conf.h (95%) rename hardware/esl_blaster/{FW => FW01}/Inc/usbd_desc.h (96%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h (96%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c (96%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h (97%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h (95%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h (97%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h (95%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c (95%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c (96%) rename hardware/esl_blaster/{FW => FW01}/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c (95%) rename hardware/esl_blaster/{FW/ESLBlasterB0.bin => FW01/Release/ESLBlaster.bin} (100%) create mode 100644 hardware/esl_blaster/FW01/Release/ESLBlaster.elf create mode 100644 hardware/esl_blaster/FW01/Release/ESLBlaster.list create mode 100644 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hardware/esl_blaster/FW01/dfu-util-0.9-win64/README.txt create mode 100644 hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-prefix.exe create mode 100644 hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-suffix.exe create mode 100644 hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util-static.exe create mode 100644 hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util.exe create mode 100644 hardware/esl_blaster/FW01/dfu-util-0.9-win64/libusb-1.0.dll create mode 100644 hardware/esl_blaster/FW02/.cproject create mode 100644 hardware/esl_blaster/FW02/.mxproject create mode 100644 hardware/esl_blaster/FW02/.project create mode 100644 hardware/esl_blaster/FW02/.settings/language.settings.xml create mode 100644 hardware/esl_blaster/FW02/.settings/stm32cubeide.project.prefs create mode 100644 hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h create mode 100644 hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h create mode 100644 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hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c create mode 100644 hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c create mode 100644 hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c create mode 100644 hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c create mode 100644 hardware/esl_blaster/FW02/Inc/gpio.h create mode 100644 hardware/esl_blaster/FW02/Inc/main.h create mode 100644 hardware/esl_blaster/FW02/Inc/stm32_assert.h create mode 100644 hardware/esl_blaster/FW02/Inc/stm32f0xx_hal_conf.h create mode 100644 hardware/esl_blaster/FW02/Inc/stm32f0xx_it.h create mode 100644 hardware/esl_blaster/FW02/Inc/usb_device.h create mode 100644 hardware/esl_blaster/FW02/Inc/usbd_cdc_if.h create mode 100644 hardware/esl_blaster/FW02/Inc/usbd_conf.h create mode 100644 hardware/esl_blaster/FW02/Inc/usbd_desc.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c create mode 100644 hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c create mode 100644 hardware/esl_blaster/FW02/Release/ESLBlaster02.bin create mode 100644 hardware/esl_blaster/FW02/Release/ESLBlaster02.elf create mode 100644 hardware/esl_blaster/FW02/Release/ESLBlaster02.list create mode 100644 hardware/esl_blaster/FW02/Release/ESLBlaster02.map create mode 100644 hardware/esl_blaster/FW02/Release/makefile create mode 100644 hardware/esl_blaster/FW02/Release/program.bat create mode 100644 hardware/esl_blaster/FW02/STM32F070F6PX_FLASH.ld create mode 100644 hardware/esl_blaster/FW02/Src/gpio.c create mode 100644 hardware/esl_blaster/FW02/Src/main.c create mode 100644 hardware/esl_blaster/FW02/Src/stm32f0xx_hal_msp.c create mode 100644 hardware/esl_blaster/FW02/Src/stm32f0xx_it.c create mode 100644 hardware/esl_blaster/FW02/Src/system_stm32f0xx.c create mode 100644 hardware/esl_blaster/FW02/Src/usb_device.c create mode 100644 hardware/esl_blaster/FW02/Src/usbd_cdc_if.c create mode 100644 hardware/esl_blaster/FW02/Src/usbd_conf.c create mode 100644 hardware/esl_blaster/FW02/Src/usbd_desc.c create mode 100644 hardware/esl_blaster/FW02/Startup/startup_stm32f070f6px.s create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/README.txt create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-prefix.exe create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-suffix.exe create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util-static.exe create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util.exe create mode 100644 hardware/esl_blaster/FW02/dfu-util-0.9-win64/libusb-1.0.dll diff --git a/hardware/esl_blaster/FW/.cproject b/hardware/esl_blaster/FW01/.cproject similarity index 99% rename from hardware/esl_blaster/FW/.cproject rename to hardware/esl_blaster/FW01/.cproject index 220e294..f05bad4 100644 --- a/hardware/esl_blaster/FW/.cproject +++ b/hardware/esl_blaster/FW01/.cproject @@ -1,198 +1,198 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/esl_blaster/FW/.mxproject b/hardware/esl_blaster/FW01/.mxproject similarity index 99% rename from hardware/esl_blaster/FW/.mxproject rename to hardware/esl_blaster/FW01/.mxproject index 4653050..107bdc7 100644 --- a/hardware/esl_blaster/FW/.mxproject +++ b/hardware/esl_blaster/FW01/.mxproject @@ -1,14 +1,14 @@ -[PreviousGenFiles] -HeaderPath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Inc -HeaderFiles=gpio.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f0xx_it.h;stm32_assert.h;stm32f0xx_hal_conf.h;main.h; -SourcePath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Src -SourceFiles=gpio.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f0xx_it.c;stm32f0xx_hal_msp.c;main.c; - -[PreviousLibFiles] -LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; - -[PreviousUsedCubeIDEFiles] -SourceFiles=Src\main.c;Src\gpio.c;Src\usb_device.c;Src\usbd_conf.c;Src\usbd_desc.c;Src\usbd_cdc_if.c;Src\stm32f0xx_it.c;Src\stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;null;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; -HeaderPath=Drivers\STM32F0xx_HAL_Driver\Inc;Drivers\STM32F0xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F0xx\Include;Drivers\CMSIS\Include;Inc; -CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F070x6; - +[PreviousGenFiles] +HeaderPath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Inc +HeaderFiles=gpio.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f0xx_it.h;stm32_assert.h;stm32f0xx_hal_conf.h;main.h; +SourcePath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Src +SourceFiles=gpio.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f0xx_it.c;stm32f0xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Src\main.c;Src\gpio.c;Src\usb_device.c;Src\usbd_conf.c;Src\usbd_desc.c;Src\usbd_cdc_if.c;Src\stm32f0xx_it.c;Src\stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;null;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; +HeaderPath=Drivers\STM32F0xx_HAL_Driver\Inc;Drivers\STM32F0xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F0xx\Include;Drivers\CMSIS\Include;Inc; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F070x6; + diff --git a/hardware/esl_blaster/FW/.project b/hardware/esl_blaster/FW01/.project similarity index 97% rename from hardware/esl_blaster/FW/.project rename to hardware/esl_blaster/FW01/.project index aecc414..ce23dcb 100644 --- a/hardware/esl_blaster/FW/.project +++ b/hardware/esl_blaster/FW01/.project @@ -1,30 +1,30 @@ - - - ESLBlaster - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - com.st.stm32cube.ide.mcu.MCUProjectNature - org.eclipse.cdt.core.cnature - com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature - com.st.stm32cube.ide.mcu.MCUCubeProjectNature - com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - + + + ESLBlaster + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h index 7692d25..630a1e0 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h @@ -1,5635 +1,5635 @@ -/** - ****************************************************************************** - * @file stm32f070x6.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F0xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f070x6 - * @{ - */ - -#ifndef __STM32F070x6_H -#define __STM32F070x6_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0 Processor and Core Peripherals - */ -#define __CM0_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ -#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F0xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** STM32F0 specific Interrupt Numbers ******************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ - FLASH_IRQn = 3, /*!< FLASH global Interrupt */ - RCC_IRQn = 4, /*!< RCC global Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ - ADC1_IRQn = 12, /*!< ADC1 Interrupt */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ - USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - USART2_IRQn = 28, /*!< USART2 global Interrupt */ - USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_stm32f0xx.h" /* STM32F0xx System Header */ -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f070x6 + * @{ + */ + +#ifndef __STM32F070x6_H +#define __STM32F070x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx - * @{ - */ - -#ifndef __STM32F0xx_H -#define __STM32F0xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F0) -#define STM32F0 -#endif /* STM32F0 */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ - !defined (STM32F031x6) && !defined (STM32F038xx) && \ - !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ - !defined (STM32F051x8) && !defined (STM32F058xx) && \ - !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ - !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) - /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ - /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ - /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ - /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ - /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ - /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ - /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ - /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ - /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V2.3.3 - */ -#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ - |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ - |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ - |(__STM32F0_DEVICE_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F030x6) - #include "stm32f030x6.h" -#elif defined(STM32F030x8) - #include "stm32f030x8.h" -#elif defined(STM32F031x6) - #include "stm32f031x6.h" -#elif defined(STM32F038xx) - #include "stm32f038xx.h" -#elif defined(STM32F042x6) - #include "stm32f042x6.h" -#elif defined(STM32F048xx) - #include "stm32f048xx.h" -#elif defined(STM32F051x8) - #include "stm32f051x8.h" -#elif defined(STM32F058xx) - #include "stm32f058xx.h" -#elif defined(STM32F070x6) - #include "stm32f070x6.h" -#elif defined(STM32F070xB) - #include "stm32f070xb.h" -#elif defined(STM32F071xB) - #include "stm32f071xb.h" -#elif defined(STM32F072xB) - #include "stm32f072xb.h" -#elif defined(STM32F078xx) - #include "stm32f078xx.h" -#elif defined(STM32F091xC) - #include "stm32f091xc.h" -#elif defined(STM32F098xx) - #include "stm32f098xx.h" -#elif defined(STM32F030xC) - #include "stm32f030xc.h" -#else - #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f0xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F0xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32F0xx device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.3 + */ +#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F0_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h index 4daf83e..56c908a 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h @@ -1,121 +1,121 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F0XX_H -#define __SYSTEM_STM32F0XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F0xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F0xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 3) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) by calling HAL API function HAL_RCC_ClockConfig() - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F0XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_common_tables.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_common_tables.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_common_tables.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_common_tables.h index d5d7241..8742a56 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_common_tables.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_common_tables.h @@ -1,136 +1,136 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_const_structs.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_const_structs.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_const_structs.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_const_structs.h index 54595f5..726d06e 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_const_structs.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_const_structs.h @@ -1,79 +1,79 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_math.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_math.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_math.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_math.h index 580cbbd..d33f8a9 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/arm_math.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/arm_math.h @@ -1,7154 +1,7154 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc.h index f2bb66a..74c49c6 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc.h @@ -1,734 +1,734 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc_V6.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc_V6.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc_V6.h index d714e9b..cd13240 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_armcc_V6.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_armcc_V6.h @@ -1,1800 +1,1800 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_gcc.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_gcc.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_gcc.h index d868f2e..bb89fbb 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/cmsis_gcc.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/cmsis_gcc.h @@ -1,1373 +1,1373 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0.h index fdee521..711dad5 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0.h @@ -1,798 +1,798 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0plus.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0plus.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0plus.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0plus.h index 7614450..b04aa39 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm0plus.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm0plus.h @@ -1,914 +1,914 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm3.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm3.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm3.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm3.h index 34ed84c..b4ac4c7 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm3.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm3.h @@ -1,1763 +1,1763 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm4.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm4.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm4.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm4.h index 01cb73b..dc840eb 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm4.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm4.h @@ -1,1937 +1,1937 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm7.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm7.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm7.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm7.h index 20963c1..3b7530a 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cm7.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cm7.h @@ -1,2512 +1,2512 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmFunc.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmFunc.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmFunc.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmFunc.h index ca319a5..652a48a 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmFunc.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmFunc.h @@ -1,87 +1,87 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmInstr.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmInstr.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmInstr.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmInstr.h index a0a5064..f474b0e 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmInstr.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmInstr.h @@ -1,87 +1,87 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmSimd.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmSimd.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmSimd.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmSimd.h index 4d76bf9..66bf5c2 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_cmSimd.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_cmSimd.h @@ -1,96 +1,96 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc000.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc000.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc000.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc000.h index ea16bf3..514dbd8 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc000.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc000.h @@ -1,926 +1,926 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc300.h b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc300.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc300.h rename to hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc300.h index 820cef4..8bd18aa 100644 --- a/hardware/esl_blaster/FW/Drivers/CMSIS/Include/core_sc300.h +++ b/hardware/esl_blaster/FW01/Drivers/CMSIS/Include/core_sc300.h @@ -1,1745 +1,1745 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 861e121..f605e57 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -1,3533 +1,3533 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_HAL_LEGACY -#define STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 - -#if defined(STM32H7) -#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT -#endif /* STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) -#endif - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) -#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID -#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID -#endif - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - -#if defined(STM32L4) - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#endif /* STM32L4 */ - -#if defined(STM32H7) - -#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - -#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX -#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 -#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else -#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE -#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE -#endif -#if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#endif - -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) -#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE -#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE -#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET -#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -#if defined(STM32G4) - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster -#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD -#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD -#endif /* STM32G4 */ -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32H7) -#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 -#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 -#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 -#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 -#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 -#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE - -#if defined(STM32G4) -#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig -#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable -#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable -#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset -#endif /* STM32G4 */ -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -#if defined(STM32L1) || defined(STM32L4) -#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID -#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID -#endif - - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS - -#if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP - - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP -#endif - -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -#if defined(STM32H7) - - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP - - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP - - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -#if defined(STM32L0) -#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO -#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO -#endif - -#if defined(STM32F3) -#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE -#endif - -#if defined(STM32H7) -#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 -#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 -#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 -#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 -#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 -#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 -#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 -#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 -#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 -#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 -#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 -#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 -#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 -#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 -#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 -#endif - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) -#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT -#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT -#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT -#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA -#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA -#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA -#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ - -#if defined(STM32F4) -#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT -#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT -#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT -#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT -#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA -#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA -#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA -#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA -#endif /* STM32F4 */ - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) -#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro -#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT -#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback -#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent -#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT -#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 -#else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#endif /* STM32H7 */ -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -#if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET - -#if defined(STM32H7) -#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE -#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE - -#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ -#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ - - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED -#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED -#endif - -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET - -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32L1) -#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#endif /* STM32L1 */ - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop -#endif -/** - * @} - */ - -/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32L4) -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h index 8bf0e6c..e9747ee 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h @@ -1,562 +1,562 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_H -#define __STM32F0xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_conf.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup HAL_Private_Macros - * @{ - */ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F070xB) || defined(STM32F030x6) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#else -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#endif -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ -#if defined(STM32F091xC) || defined(STM32F098xx) -#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** @defgroup HAL_Pin_remapping HAL Pin remapping - * @{ - */ -#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). - 0: No remap (pin pair PA9/10 mapped on the pins) - 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ - -/** - * @} - */ -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection - * @note Applicable on STM32F09x - * @{ - */ -#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ -#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ -#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ - -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx */ - - -/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO - * @{ - */ - -/** @brief Fast-mode Plus driving capability on a specific GPIO - */ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F070xB) || defined(STM32F030x6) -#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ -#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ -#endif -#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ -#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ -#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ -#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ - -/** - * @} - */ - - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper - * @brief ISR Wrapper - * @note applicable on STM32F09x - * @{ - */ -#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */ - -#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ -#if defined(STM32F091xC) -#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ -#endif -#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ -#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ -#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ -#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ -#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ -#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ -#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ -#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ -#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ -#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ -#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ -#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ -#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ -#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ -#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ -#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ -#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ -#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ -#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ -#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ -#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ -#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ -#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ -#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ -#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ -#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ -#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ -#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ -#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ -#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ -#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ -#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ -#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ -#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ -#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ -#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ -#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ -#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ -#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ -#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ -#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ -#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ -#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ -#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ -#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ -#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ -#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ -#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ -#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ -#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ -#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ -#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ -#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ -#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ -#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ -#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ -#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ -#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ -#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ -#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ -#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ -#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ -#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ -#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ -#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ -#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ -#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ -#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals - * @brief Freeze/Unfreeze Peripherals in Debug mode - * @{ - */ - -#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) -#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) -#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ - -#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) -#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ - -/** - * @} - */ - -/** @defgroup Memory_Mapping_Selection Memory Mapping Selection - * @{ - */ -#if defined(SYSCFG_CFGR1_MEM_MODE) -/** @brief Main Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) -#endif /* SYSCFG_CFGR1_MEM_MODE */ - -#if defined(SYSCFG_CFGR1_MEM_MODE_0) -/** @brief System Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ - SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ - }while(0) -#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ - -#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) -/** @brief Embedded SRAM mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ - SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ - }while(0) -#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ -/** - * @} - */ - - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** @defgroup HAL_Pin_remap HAL Pin remap - * @brief Pin remapping enable/disable macros - * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping - * @{ - */ -#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ - SYSCFG->CFGR1 |= (__PIN_REMAP__); \ - }while(0) -#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ - SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -/** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. - * That you can find above these macros. - */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) -#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable - * @{ - */ -/** @brief SYSCFG Break Lockup lock - * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ - -#if defined(SYSCFG_CFGR2_PVD_LOCK) -/** @defgroup PVD_Lock_Enable PVD Lock - * @{ - */ -/** @brief SYSCFG Break PVD lock - * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_PVD_LOCK */ - -#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) -/** @defgroup SRAM_Parity_Lock SRAM Parity Lock - * @{ - */ -/** @brief SYSCFG Break SRAM PARITY lock - * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ - -#if defined(SYSCFG_CFGR2_SRAM_PEF) -/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM - * @brief Parity check on RAM disable macro - * @note Disabling the parity check on RAM locks the configuration bit. - * To re-enable the parity check on RAM perform a system reset. - * @{ - */ -#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_SRAM_PEF */ - - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check - * @brief ISR wrapper check - * @note This feature is applicable on STM32F09x - * @note Allow to determine interrupt source per line. - * @{ - */ -#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) -/** - * @} - */ -#endif /* (STM32F091xC) || defined (STM32F098xx)*/ - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection - * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register - * @note This feature is applicable on STM32F09x - * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL - * @{ - */ -#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ - SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ - SYSCFG->CFGR1 |= (__SOURCE__); \ - }while(0) - -#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) -/** - * @} - */ -#endif /* (STM32F091xC) || defined (STM32F098xx)*/ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_H +#define __STM32F0xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_conf.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Macros + * @{ + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#else +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#endif +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remapping HAL Pin remapping + * @{ + */ +#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). + 0: No remap (pin pair PA9/10 mapped on the pins) + 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ + +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection + * @note Applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ +#endif +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ + +/** + * @} + */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @note applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */ + +#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ +#if defined(STM32F091xC) +#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ +#endif +#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ +#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ +#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ +#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ +#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ +#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ +#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ +#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ +#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ +#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ +#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ +#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ +#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ +#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ +#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ +#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ +#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ +#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ +#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ +#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ +#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ +#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ +#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ +#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ +#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ +#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ +#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ +#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ +#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ +#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ +#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ +#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ +#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ +#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ + +#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup Memory_Mapping_Selection Memory Mapping Selection + * @{ + */ +#if defined(SYSCFG_CFGR1_MEM_MODE) +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#endif /* SYSCFG_CFGR1_MEM_MODE */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ +/** + * @} + */ + + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remap HAL Pin remap + * @brief Pin remapping enable/disable macros + * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping + * @{ + */ +#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 |= (__PIN_REMAP__); \ + }while(0) +#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * That you can find above these macros. + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ + +#if defined(SYSCFG_CFGR2_PVD_LOCK) +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_PVD_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +/** @defgroup SRAM_Parity_Lock SRAM Parity Lock + * @{ + */ +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PEF) +/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM + * @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + * @{ + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PEF */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check + * @brief ISR wrapper check + * @note This feature is applicable on STM32F09x + * @note Allow to determine interrupt source per line. + * @{ + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection + * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register + * @note This feature is applicable on STM32F09x + * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @{ + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ + SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ + SYSCFG->CFGR1 |= (__SOURCE__); \ + }while(0) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); +uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h index f1f3de8..ebea4ea 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h @@ -1,149 +1,149 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CORTEX_H -#define __STM32F0xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) -#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ -/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions *******************************/ -void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * @{ - */ - -/* Peripheral Control functions *************************************************/ -uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CORTEX_H +#define __STM32F0xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ +/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *******************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h index 306d23f..a65b44e 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h @@ -1,182 +1,182 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DEF -#define __STM32F0xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" -#if defined(USE_HAL_LEGACY) - #include "Legacy/stm32_hal_legacy.h" -#endif -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) - #error " USE_RTOS should be 0 in the current HAL release " -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F0xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DEF +#define __STM32F0xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#if defined(USE_HAL_LEGACY) + #include "Legacy/stm32_hal_legacy.h" +#endif +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ + (__DMA_HANDLE_).Parent = (__HANDLE__); \ + } while(0) + +#define UNUSED(x) ((void)(x)) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h index f6f5b2c..6a9fb70 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h @@ -1,579 +1,579 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DMA_H -#define __STM32F0xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ - -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ -} DMA_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ -#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ - -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ - -#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ -#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ -#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ -#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ -#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ -#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ -#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ -#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ -#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ -#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ -#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ -#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ -#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ -#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ -#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ -#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ -#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ -#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ -#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ -#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ -#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ -#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ -#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ -#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ -#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ -#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ -#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ -#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ - -/** - * @} - */ - -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @defgroup HAL_DMA_remapping HAL DMA remapping - * Elements values convention: 0xYYYYYYYY - * - YYYYYYYY : Position in the SYSCFG register CFGR1 - * @{ - */ -#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap - 0: No remap (ADC DMA requests mapped on DMA channel 1 - 1: Remap (ADC DMA requests mapped on DMA channel 2 */ -#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap - 0: No remap (USART1_TX DMA request mapped on DMA channel 2 - 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ -#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap - 0: No remap (USART1_RX DMA request mapped on DMA channel 3 - 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ -#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap - 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) - 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ -#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap - 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ -#if defined (STM32F070xB) -#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. - 0: Disabled, need to remap before use - 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ - -#endif - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) - 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ -#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) - 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ -#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) - 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) - 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) - 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ -#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) - 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ -#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) - 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ -#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) - 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ -#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) - 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ -#endif - -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_DMA_RMP */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state - * @param __HANDLE__ DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) - - -/* Interrupt & Flag management */ - -/** - * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. - * @param __HANDLE__ DMA handle - * - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @brief DMA remapping enable/disable macros - * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping - */ -#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ - SYSCFG->CFGR1 |= (__DMA_REMAP__); \ - }while(0) -#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ - SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ - }while(0) -#endif /* SYSCFG_CFGR1_DMA_RMP */ - -/** - * @} - */ - -/* Include DMA HAL Extension module */ -#include "stm32f0xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* Input and Output operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Macros - * @{ - */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) - -#if defined(SYSCFG_CFGR1_DMA_RMP) - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ - ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ - ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ - ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ - ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ - ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ - ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ - ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) -#elif defined (STM32F070xB) -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ - ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) -#else -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) -#endif - -#endif /* SYSCFG_CFGR1_DMA_RMP */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_H +#define __STM32F0xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ +} DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ +#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ +#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ +#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ +#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ +#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ +#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ +#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ +#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ +#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ +#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ +#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ +#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ +#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ +#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ +#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ +#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ +#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ +#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ +#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ +#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ +#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ +#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ +#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ +#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ +#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ +#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ +#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ + +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ +#if defined (STM32F070xB) +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. + 0: Disabled, need to remap before use + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ + +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif + +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_DMA_RMP */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping + */ +#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +#endif /* SYSCFG_CFGR1_DMA_RMP */ + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* Input and Output operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#if defined(SYSCFG_CFGR1_DMA_RMP) + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ + ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ + ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ + ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) +#elif defined (STM32F070xB) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#else +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#endif + +#endif /* SYSCFG_CFGR1_DMA_RMP */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h index d6395df..03217b1 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h @@ -1,827 +1,827 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DMA_EX_H -#define __STM32F0xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants - * @{ - */ -#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#if !defined(STM32F030xC) -#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#endif /* !defined(STM32F030xC) */ - -/****************** DMA1 remap bit field definition********************/ -/* DMA1 - Channel 1 */ -#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ -#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ -#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 2 */ -#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ -#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 3 */ -#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ -#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 4 */ -#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 5 */ -#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ -#endif /* !defined(STM32F030xC) */ - -#if !defined(STM32F030xC) -/* DMA1 - Channel 6 */ -#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ -/* DMA1 - Channel 7 */ -#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ - -/****************** DMA2 remap bit field definition********************/ -/* DMA2 - Channel 1 */ -#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ -/* DMA2 - Channel 2 */ -#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ -/* DMA2 - Channel 3 */ -#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ -#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ -#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ -/* DMA2 - Channel 4 */ -#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ -#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ -#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ -/* DMA2 - Channel 5 */ -#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ -#endif /* !defined(STM32F030xC) */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) - -#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ - ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ - ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ - ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ - ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030xC) -#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) -#endif /* STM32F030xC */ - -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros - * @{ - */ -/* Interrupt & Flag management */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - DMA_FLAG_GL7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#elif defined(STM32F091xC) || defined(STM32F098xx) -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ - DMA_FLAG_GL5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ - (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ - (DMA1->IFCR = (__FLAG__))) - -#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - DMA_FLAG_GL5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_5 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_5 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#endif - - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __HAL_DMA1_REMAP(__REQUEST__) \ - do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ - DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ - DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ - }while(0) - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define __HAL_DMA2_REMAP(__REQUEST__) \ - do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ - DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ - DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ - }while(0) -#endif /* STM32F091xC || STM32F098xx */ - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_DMA_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_EX_H +#define __STM32F0xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ +#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#if !defined(STM32F030xC) +#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#endif /* !defined(STM32F030xC) */ + +/****************** DMA1 remap bit field definition********************/ +/* DMA1 - Channel 1 */ +#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ +#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ +#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 2 */ +#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ +#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 3 */ +#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 4 */ +#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 5 */ +#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if !defined(STM32F030xC) +/* DMA1 - Channel 6 */ +#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ +/* DMA1 - Channel 7 */ +#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ + +/****************** DMA2 remap bit field definition********************/ +/* DMA2 - Channel 1 */ +#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ +/* DMA2 - Channel 2 */ +#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ +/* DMA2 - Channel 3 */ +#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ +#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ +#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ +/* DMA2 - Channel 4 */ +#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ +#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ +#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ +/* DMA2 - Channel 5 */ +#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) + +#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) +#endif /* STM32F030xC */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros + * @{ + */ +/* Interrupt & Flag management */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#elif defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif + + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define __HAL_DMA1_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ + DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_DMA2_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ + DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) +#endif /* STM32F091xC || STM32F098xx */ + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h index f41a41b..f2ee248 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h @@ -1,369 +1,369 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_FLASH_H -#define __STM32F0xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ -/** - * @} - */ - -/** @addtogroup FLASH_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) - -#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ - ((__LATENCY__) == FLASH_LATENCY_1)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_PAGEERASE = 1U, - FLASH_PROC_MASSERASE = 2U, - FLASH_PROC_PROGRAMHALFWORD = 3U, - FLASH_PROC_PROGRAMWORD = 4U, - FLASH_PROC_PROGRAMDOUBLEWORD = 5U -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ - - __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ - - __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ - - HAL_LockTypeDef Lock; /*!< FLASH locking object */ - - __IO uint32_t ErrorCode; /*!< FLASH error code - This parameter can be a value of @ref FLASH_Error_Codes */ -} FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Codes FLASH Error Codes - * @{ - */ - -#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ -#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ -#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ - -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) - - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @} - */ - -/** @defgroup FLASH_Prefetch FLASH Prefetch - * @brief macros to handle FLASH Prefetch buffer - * @{ - */ -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_BSY FLASH Busy flag - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32f0xx_hal_flash_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); - -/* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -uint32_t HAL_FLASH_GetError(void); - -/** - * @} - */ - -/** - * @} - */ - -/* Private function -------------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_H +#define __STM32F0xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f0xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h index d382a9d..0d127e3 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h @@ -1,464 +1,464 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of Flash HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_FLASH_EX_H -#define __STM32F0xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/** @addtogroup FLASHEx_Private_Macros - * @{ - */ -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) - -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1))/*||\ - ((LEVEL) == OB_RDP_LEVEL_2))*/ - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) - -#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) - -#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) - -#if defined(FLASH_OBR_BOOT_SEL) -#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) -#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) -#endif /* FLASH_OBR_BOOT_SEL */ - - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) - -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ - - uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. - This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Options bytes program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_OB_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_OB_WRP_State */ - - uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected - This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ - - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: - IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, - @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and - @ref FLASHEx_OB_RAM_Parity_Check_Enable */ - - uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed - This parameter can be a value of @ref FLASHEx_OB_Data_Address */ - - uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ -} FLASH_OBProgramInitTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Page_Size FLASHEx Page Size - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ - || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) -#define FLASH_PAGE_SIZE 0x400U -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define FLASH_PAGE_SIZE 0x800U -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ -/** - * @} - */ - -/** @defgroup FLASHEx_Type_Erase FLASH Type Erase - * @{ - */ -#define FLASH_TYPEERASE_PAGES (0x00U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_EX_H +#define __STM32F0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1))/*||\ + ((LEVEL) == OB_RDP_LEVEL_2))*/ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) + +#if defined(FLASH_OBR_BOOT_SEL) +#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) +#endif /* FLASH_OBR_BOOT_SEL */ + + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and + @ref FLASHEx_OB_RAM_Parity_Check_Enable */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size FLASHEx Page Size + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ + || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES (0x00U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_GPIO_H -#define __STM32F0xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0U, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ - -#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ -/** - * @} - */ - - /** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) - -#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ - ((__MODE__) == GPIO_MODE_AF_PP) ||\ - ((__MODE__) == GPIO_MODE_AF_OD) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING) ||\ - ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ - ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_ANALOG)) - -#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) - -#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ - ((__PULL__) == GPIO_PULLUP) || \ - ((__PULL__) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Include GPIO HAL Extended module */ -#include "stm32f0xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_H +#define __STM32F0xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32f0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h index 22b94ef..82169b4 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h @@ -1,816 +1,816 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_GPIO_EX_H -#define __STM32F0xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -#if defined (STM32F030x6) -/*------------------------- STM32F030x6---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030x6 */ - -/*---------------------------------- STM32F030x8 -------------------------------------------*/ -#if defined (STM32F030x8) -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030x8 */ - -#if defined (STM32F031x6) || defined (STM32F038xx) -/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F031x6 || STM32F038xx */ - -#if defined (STM32F051x8) || defined (STM32F058xx) -/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F051x8/STM32F058xx */ - -#if defined (STM32F071xB) -/*--------------------------- STM32F071xB ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F071xB */ - - -#if defined(STM32F091xC) || defined(STM32F098xx) -/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ -#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */ -#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ -#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */ -#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */ -#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */ -#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ -#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ -#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */ -#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030xC) -/*--------------------------- STM32F030xC ----------------------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ -#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030xC */ - -#if defined (STM32F072xB) || defined (STM32F078xx) -/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ -#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F072xB || STM32F078xx */ - -#if defined (STM32F070xB) -/*---------------------------------- STM32F070xB ---------------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F070xB */ - -#if defined (STM32F042x6) || defined (STM32F048xx) -/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined (STM32F070x6) -/*--------------------------------------- STM32F070x6 ----------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F070x6 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros - * @{ - */ - -/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index -* @{ - */ -#if defined(GPIOD) && defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) -#endif - -#if defined(GPIOD) && !defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U : 5U) -#endif - -#if !defined(GPIOD) && defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) -#endif - -#if !defined(GPIOD) && !defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 5U) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_EX_H +#define __STM32F0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined (STM32F030x6) +/*------------------------- STM32F030x6---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x6 */ + +/*---------------------------------- STM32F030x8 -------------------------------------------*/ +#if defined (STM32F030x8) +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x8 */ + +#if defined (STM32F031x6) || defined (STM32F038xx) +/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F031x6 || STM32F038xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) +/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F051x8/STM32F058xx */ + +#if defined (STM32F071xB) +/*--------------------------- STM32F071xB ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F071xB */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */ +#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */ +#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */ +#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ +#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */ +#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +/*--------------------------- STM32F030xC ----------------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030xC */ + +#if defined (STM32F072xB) || defined (STM32F078xx) +/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined (STM32F070xB) +/*---------------------------------- STM32F070xB ---------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070xB */ + +#if defined (STM32F042x6) || defined (STM32F048xx) +/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined (STM32F070x6) +/*--------------------------------------- STM32F070x6 ----------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070x6 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index +* @{ + */ +#if defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif + +#if !defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if !defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 5U) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h index 7970425..dfdbdec 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h @@ -1,708 +1,708 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_I2C_H -#define __STM32F0xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -} I2C_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32f0xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32f0xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_H +#define __STM32F0xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 IP initilisation status\n + * 0 : Reset (IP not initialized)\n + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (IP in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (IP busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ +} I2C_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP I2C_CR2_STOP +#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE I2C_CR2_START +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f0xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h index 815213a..69bc8fb 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h @@ -1,188 +1,188 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_I2C_EX_H -#define __STM32F0xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) -#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ -#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ -#else -#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ -#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ -#endif -#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ -#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ -#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ -#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ -#else -#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ -#endif -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ -#else -#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -#if defined(I2C_CR1_WUPEN) -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); -#endif -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ - ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_EX_H +#define __STM32F0xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#else +#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ +#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ +#endif +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if defined(I2C_CR1_WUPEN) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +#endif +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h index 1716387..974827c 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h @@ -1,835 +1,835 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pcd.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PCD_H -#define __STM32F0xx_HAL_PCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - -/** - * @brief PCD State structure definition - */ -typedef enum -{ - HAL_PCD_STATE_RESET = 0x00U, - HAL_PCD_STATE_READY = 0x01U, - HAL_PCD_STATE_ERROR = 0x02U, - HAL_PCD_STATE_BUSY = 0x03U, - HAL_PCD_STATE_TIMEOUT = 0x04U -} PCD_StateTypeDef; - -/** - * @brief PCD double buffered endpoint direction - */ -typedef enum -{ - PCD_EP_DBUF_OUT, - PCD_EP_DBUF_IN, - PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; - -/** - * @brief PCD endpoint buffer number - */ -typedef enum -{ - PCD_EP_NOBUF, - PCD_EP_BUF0, - PCD_EP_BUF1 -}PCD_EP_BUF_NUM; - -/** - * @brief PCD Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Core_Speed */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref PCD_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode - This parameter can be set to ENABLE or DISABLE */ - - uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - -}PCD_InitTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref PCD_EP_Type */ - - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -}PCD_EPTypeDef; - -typedef USB_TypeDef PCD_TypeDef; - -/** - * @brief PCD Handle Structure definition - */ -typedef struct -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - void *pData; /*!< Pointer to upper stack Handler */ - -} PCD_HandleTypeDef; - -/** - * @} - */ - -/* Include PCD HAL Extension module */ -#include "stm32f0xx_hal_pcd_ex.h" - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup PCD_Core_Speed PCD Core Speed - * @{ - */ -#define PCD_SPEED_HIGH 0 /* Not Supported */ -#define PCD_SPEED_FULL 2 -/** - * @} - */ - - /** @defgroup PCD_Core_PHY PCD Core PHY - * @{ - */ -#define PCD_PHY_EMBEDDED 2 -/** - * @} - */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt - * @{ - */ -#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ -/** - * @} - */ - -/** @defgroup PCD_EP0_MPS PCD EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 -/** - * @} - */ - -/** @defgroup PCD_EP_Type PCD EP Type - * @{ - */ -#define PCD_EP_TYPE_CTRL 0 -#define PCD_EP_TYPE_ISOC 1 -#define PCD_EP_TYPE_BULK 2 -#define PCD_EP_TYPE_INTR 3 -/** - * @} - */ - -/** @defgroup PCD_ENDP PCD ENDP - * @{ - */ -#define PCD_ENDP0 ((uint8_t)0U) -#define PCD_ENDP1 ((uint8_t)1U) -#define PCD_ENDP2 ((uint8_t)2U) -#define PCD_ENDP3 ((uint8_t)3U) -#define PCD_ENDP4 ((uint8_t)4U) -#define PCD_ENDP5 ((uint8_t)5U) -#define PCD_ENDP6 ((uint8_t)6U) -#define PCD_ENDP7 ((uint8_t)7U) -/** - * @} - */ - -/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind - * @{ - */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup PCD_Private_Macros PCD Private Macros - * @{ - */ - -/* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) - -/* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) - - - -/** - * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wType Endpoint Type. - * @retval None - */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - (((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX))) - -/** - * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval Endpoint Type - */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) - - -/** - * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bDir Direction - * @retval None - */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} - -/** - * @brief gets direction of the double buffered endpoint - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval EP_DBUF_OUT, EP_DBUF_IN, - * EP_DBUF_ERR if the endpoint counter not yet programmed. - */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ - \ - _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0U)\ - { \ - _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ - { \ - _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\ - } /* PCD_SET_EP_TX_STATUS */ - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ - \ - _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0U) \ - { \ - _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ - { \ - _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ - -/** - * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wStaterx new state. - * @param wStatetx new state. - * @retval None - */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ - -/** - * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] - * /STAT_RX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval status - */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT) - -/** - * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) -#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) - -/** - * @brief checks stall condition in an endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval TRUE = endpoint in stall condition. - */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) - -/** - * @brief set & clear EP_KIND bit. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))) - -/** - * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx),(bEpNum));\ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\ - {\ - PCD_TX_DTOG((USBx),(bEpNum));\ - } - -/** - * @brief Sets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bAddr Address. - * @retval None - */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr)) - -/** - * @brief Gets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) - -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U))))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U))))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U))))) - -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U))))) - -/** - * @brief sets address of the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wAddr address to be set (must be word aligned). - * @retval None - */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) - -/** - * @brief Gets address of the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval address of the buffer. - */ -#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg Register - * @param wCount Counter. - * @param wNBlocks no. of Blocks. - * @retval None - */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5U;\ - if(((wCount) & 0x1fU) == 0U)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \ - }/* PCD_CALC_BLK32 */ - - -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1U;\ - if(((wCount) & 0x1U) != 0U)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10U);\ - }/* PCD_CALC_BLK2 */ - - -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62U) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ - - -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\ - } - -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wCount Counter value. - * @retval None - */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \ - PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ - } - -/** - * @brief gets counter of the tx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval Counter value - */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) - -/** - * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wBuf0Addr buffer 0 address. - * @retval Counter value - */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr))) - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wBuf0Addr buffer 0 address. - * @param wBuf1Addr buffer 1 address. - * @retval None - */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bDir endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount Counter value - * @retval None - */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - { \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf0Count*/ - -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ - -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \ - } /* PCD_SET_EP_DBUF_CNT */ - -/** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ - */ -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PCD_H +#define __STM32F0xx_HAL_PCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U +} PCD_StateTypeDef; + +/** + * @brief PCD double buffered endpoint direction + */ +typedef enum +{ + PCD_EP_DBUF_OUT, + PCD_EP_DBUF_IN, + PCD_EP_DBUF_ERR, +}PCD_EP_DBUF_DIR; + +/** + * @brief PCD endpoint buffer number + */ +typedef enum +{ + PCD_EP_NOBUF, + PCD_EP_BUF0, + PCD_EP_BUF1 +}PCD_EP_BUF_NUM; + +/** + * @brief PCD Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref PCD_EP0_MPS */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode + This parameter can be set to ENABLE or DISABLE */ + + uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + +}PCD_InitTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref PCD_EP_Type */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +}PCD_EPTypeDef; + +typedef USB_TypeDef PCD_TypeDef; + +/** + * @brief PCD Handle Structure definition + */ +typedef struct +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + void *pData; /*!< Pointer to upper stack Handler */ + +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extension module */ +#include "stm32f0xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Core_Speed PCD Core Speed + * @{ + */ +#define PCD_SPEED_HIGH 0 /* Not Supported */ +#define PCD_SPEED_FULL 2 +/** + * @} + */ + + /** @defgroup PCD_Core_PHY PCD Core PHY + * @{ + */ +#define PCD_PHY_EMBEDDED 2 +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) + +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +/** + * @} + */ + +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define PCD_EP0MPS_64 DEP0CTL_MPS_64 +#define PCD_EP0MPS_32 DEP0CTL_MPS_32 +#define PCD_EP0MPS_16 DEP0CTL_MPS_16 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_EP_Type PCD EP Type + * @{ + */ +#define PCD_EP_TYPE_CTRL 0 +#define PCD_EP_TYPE_ISOC 1 +#define PCD_EP_TYPE_BULK 2 +#define PCD_EP_TYPE_INTR 3 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 ((uint8_t)0U) +#define PCD_ENDP1 ((uint8_t)1U) +#define PCD_ENDP2 ((uint8_t)2U) +#define PCD_ENDP3 ((uint8_t)3U) +#define PCD_ENDP4 ((uint8_t)4U) +#define PCD_ENDP5 ((uint8_t)5U) +#define PCD_ENDP6 ((uint8_t)6U) +#define PCD_ENDP7 ((uint8_t)7U) +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) + + + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + (((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) + + +/** + * @brief free buffer used from the application realizing it to the line + toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir Direction + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ +{\ + if ((bDir) == PCD_EP_DBUF_OUT)\ + { /* OUT double buffered endpoint */\ + PCD_TX_DTOG((USBx), (bEpNum));\ + }\ + else if ((bDir) == PCD_EP_DBUF_IN)\ + { /* IN double buffered endpoint */\ + PCD_RX_DTOG((USBx), (bEpNum));\ + }\ +} + +/** + * @brief gets direction of the double buffered endpoint + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval EP_DBUF_OUT, EP_DBUF_IN, + * EP_DBUF_ERR if the endpoint counter not yet programmed. + */ +#define PCD_GET_DB_DIR(USBx, bEpNum)\ +{\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\ + return(PCD_EP_DBUF_OUT);\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\ + return(PCD_EP_DBUF_IN);\ + else\ + return(PCD_EP_DBUF_ERR);\ +} + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ + \ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wState))!= 0U)\ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\ + } /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ + register uint32_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ + } /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ + == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ + == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK)))) +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))) + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) +#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ + { \ + PCD_RX_DTOG((USBx),(bEpNum));\ + } +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\ + {\ + PCD_TX_DTOG((USBx),(bEpNum));\ + } + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ + USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr)) + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U))))) + +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U))))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param dwReg Register + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 5U;\ + if(((wCount) & 0x1fU) == 0U)\ + { \ + (wNBlocks)--;\ + } \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \ + }/* PCD_CALC_BLK32 */ + + +#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 1U;\ + if(((wCount) & 0x1U) != 0U)\ + { \ + (wNBlocks)++;\ + } \ + *pdwReg = (uint16_t)((wNBlocks) << 10U);\ + }/* PCD_CALC_BLK2 */ + + +#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ + uint16_t wNBlocks;\ + if((wCount) > 62U) \ + { \ + PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \ + } \ + else \ + { \ + PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \ + } \ + }/* PCD_SET_EP_CNT_RX_REG */ + + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\ + } + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) +#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \ + PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ + } + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr))) + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @param wBuf1Addr buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ + } /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \ + else if((bDir) == PCD_EP_DBUF_IN)\ + { \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ + } /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + {/* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \ + } \ + else if((bDir) == PCD_EP_DBUF_IN)\ + {/* IN endpoint */ \ + *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ + } /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + } /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +/** @defgroup PCD_Instance_definition PCD Instance definition + * @{ + */ +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h index cd84af2..35a70b6 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h @@ -1,98 +1,98 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pcd_ex.h - * @author MCD Application Team - * @brief Header file of PCD HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PCD_EX_H -#define __STM32F0xx_HAL_PCD_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Internal macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ -/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PCD_EX_H +#define __STM32F0xx_HAL_PCD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Internal macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h index 8f1f7dd..ce9b7dd 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h @@ -1,205 +1,205 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PWR_H -#define __STM32F0xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON (0x00000000U) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * Warning: this Flag is not available on STM32F030x8 products - * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference - * voltage VREFINT is ready. - * Warning: this Flag is not available on STM32F030x8 products - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) - - -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32f0xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions **********************************************/ -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_H +#define __STM32F0xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * Warning: this Flag is not available on STM32F030x8 products + * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference + * voltage VREFINT is ready. + * Warning: this Flag is not available on STM32F030x8 products + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h index dab4f98..ef74a81 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h @@ -1,475 +1,475 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PWR_EX_H -#define __STM32F0xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Types PWREx Exported Types - * @{ - */ - -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level - This parameter can be a value of @ref PWREx_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWREx_PVD_Mode */ -}PWR_PVDTypeDef; - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ - - -/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins - * @{ - */ -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) -#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7) || \ - ((PIN) == PWR_WAKEUP_PIN8)) - -#elif defined(STM32F030xC) || defined (STM32F070xB) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7)) - -#elif defined(STM32F042x6) || defined (STM32F048xx) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7)) - -#else -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) - - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2)) - -#endif - -/** - * @} - */ - -/** @defgroup PWREx_EXTI_Line PWREx EXTI Line - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) - -#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) ||*/ -/** - * @} - */ - -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -/** - * @} - */ - -/** @defgroup PWREx_PVD_Mode PWREx PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -/** - * @} - */ -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -/** @defgroup PWREx_Flag PWREx Flag - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#else -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Macros PWREx Exported Macros - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -/** - * @brief Enable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - -/** - * @brief PVD EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - -/** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD EXTI flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -/** - * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ - do{ \ - EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ - EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ - } while(0) - -/** - * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) - -/** - * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. - * @retval EXTI VDDIO2 Monitor Line Status. - */ -#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Clear the VDDIO2 Monitor EXTI flag. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) - - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ -/* I/O operation functions ***************************************************/ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWREx_Vddio2Monitor_IRQHandler(void); -void HAL_PWREx_Vddio2MonitorCallback(void); -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/* Peripheral Control functions **********************************************/ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWREx_EnableVddio2Monitor(void); -void HAL_PWREx_DisableVddio2Monitor(void); -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_EX_H +#define __STM32F0xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + This parameter can be a value of @ref PWREx_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVD_Mode */ +}PWR_PVDTypeDef; + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) +#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7) || \ + ((PIN) == PWR_WAKEUP_PIN8)) + +#elif defined(STM32F030xC) || defined (STM32F070xB) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#elif defined(STM32F042x6) || defined (STM32F048xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#else +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) + + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) + +#endif + +/** + * @} + */ + +/** @defgroup PWREx_EXTI_Line PWREx EXTI Line + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + +#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ +/** + * @} + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/** + * @} + */ + +/** @defgroup PWREx_PVD_Mode PWREx PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +/** + * @} + */ +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +/** @defgroup PWREx_Flag PWREx Flag + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#else +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWREx Exported Macros + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ + do{ \ + EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + } while(0) + +/** + * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) + +/** + * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. + * @retval EXTI VDDIO2 Monitor Line Status. + */ +#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Clear the VDDIO2 Monitor EXTI flag. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) + + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +/* I/O operation functions ***************************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_Vddio2Monitor_IRQHandler(void); +void HAL_PWREx_Vddio2MonitorCallback(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/* Peripheral Control functions **********************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_EnableVddio2Monitor(void); +void HAL_PWREx_DisableVddio2Monitor(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h similarity index 98% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h index ce9bda5..c9cf5a6 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h @@ -1,1702 +1,1702 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_RCC_H -#define __STM32F0xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ - -/* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ -/* LSE state change timeout */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#if defined(RCC_HSI48_SUPPORT) -#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_Register_Offset Register offsets - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x04 -#define RCC_CIR_OFFSET 0x08 -#define RCC_BDCR_OFFSET 0x20 -#define RCC_CSR_OFFSET 0x24 - -/** - * @} - */ - - -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) - -/* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1U) -#define CR2_REG_INDEX ((uint8_t)2U) -#define BDCR_REG_INDEX ((uint8_t)3U) -#define CSR_REG_INDEX ((uint8_t)4U) - -/* Bits position in in the CFGR register */ -#define RCC_CFGR_PLLMUL_BITNUMBER 18U -#define RCC_CFGR_HPRE_BITNUMBER 4U -#define RCC_CFGR_PPRE_BITNUMBER 8U -/* Flags in the CFGR2 register */ -#define RCC_CFGR2_PREDIV_BITNUMBER 0 -/* Flags in the CR register */ -#define RCC_CR_HSIRDY_BitNumber 1 -#define RCC_CR_HSERDY_BitNumber 17 -#define RCC_CR_PLLRDY_BitNumber 25 -/* Flags in the CR2 register */ -#define RCC_CR2_HSI14RDY_BitNumber 1 -#define RCC_CR2_HSI48RDY_BitNumber 16 -/* Flags in the BDCR register */ -#define RCC_BDCR_LSERDY_BitNumber 1 -/* Flags in the CSR register */ -#define RCC_CSR_LSIRDY_BitNumber 1 -#define RCC_CSR_V18PWRRSTF_BitNumber 23 -#define RCC_CSR_RMVF_BitNumber 24 -#define RCC_CSR_OBLRSTF_BitNumber 25 -#define RCC_CSR_PINRSTF_BitNumber 26 -#define RCC_CSR_PORRSTF_BitNumber 27 -#define RCC_CSR_SFTRSTF_BitNumber 28 -#define RCC_CSR_IWDGRSTF_BitNumber 29 -#define RCC_CSR_WWDGRSTF_BitNumber 30 -#define RCC_CSR_LPWRRSTF_BitNumber 31 -/* Flags in the HSITRIM register */ -#define RCC_CR_HSITRIM_BitNumber 3 -#define RCC_HSI14TRIM_BIT_NUMBER 3 -#define RCC_FLAG_MASK ((uint8_t)0x1FU) - -/** - * @} - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) -#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ - ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ - ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ - ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ - ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ - ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ - ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ - ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) - -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ - ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ - ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ - ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ - ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ - ((__MUL__) == RCC_PLL_MUL16)) -#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) -#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< PLLState: The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ - - uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ - -} RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ - - uint32_t HSI14State; /*!< The new state of the HSI14. - This parameter can be a value of @ref RCC_HSI14_Config */ - - uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - -#if defined(RCC_HSI48_SUPPORT) - uint32_t HSI48State; /*!< The new state of the HSI48. - This parameter can be a value of @ref RCC_HSI48_Config */ - -#endif /* RCC_HSI48_SUPPORT */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -} RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_Clock_Source */ - -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ - -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE (0x00000000U) -#define RCC_OSCILLATORTYPE_HSE (0x00000001U) -#define RCC_OSCILLATORTYPE_HSI (0x00000002U) -#define RCC_OSCILLATORTYPE_LSE (0x00000004U) -#define RCC_OSCILLATORTYPE_LSI (0x00000008U) -#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) -#if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ - -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_HSI14_Config RCC HSI14 Config - * @{ - */ -#define RCC_HSI14_OFF (0x00000000U) -#define RCC_HSI14_ON RCC_CR2_HSI14ON -#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) - -#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ - -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00U) -#define RCC_HSI48_ON ((uint8_t)0x01U) - -/** - * @} - */ -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ -#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor - * @{ - */ -#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 -#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 -#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 -#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 -#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 -#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 -#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 -#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 -#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 -#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 -#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 - -/** - * @} - */ - -/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor - * @{ - */ - -#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 -#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 -#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 -#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 -#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 -#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 -#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 -#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 -#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 -#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 -#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 -#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 -#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 -#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 -#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 -#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 - -/** - * @} - */ - - -/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK -#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK -#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE -#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI - -/** - * @} - */ - -/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK - -/** - * @} - */ -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 (0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ - -/** - * @} - */ - -/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK -#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK -#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE -#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL -#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 - -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ -#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ -#if defined(RCC_CIR_HSI48RDYF) -#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ -#endif -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: CR2 register - * - 011: BDCR register - * - 0100: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) -/* Flags in the CR2 register */ -#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) -#if defined(RCC_CSR_V18PWRRSTF) -#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) -#endif -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable - * @brief Enable or disable the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) -#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) -#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) -#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) -#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) -#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) -#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) -/** - * @} - */ - - -/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) -#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) -#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) - -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) -#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) -#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) -/** - * @} - */ -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) -#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) - -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) - -/** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) - -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON turn ON the HSE oscillator - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - }while(0U) - -/** - * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. - * @note Predivision factor can not be changed if PLL is used as system clock - * In this case, you have to select another source of the system clock, disable the PLL and - * then change the HSE predivision factor. - * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. - * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. - */ -#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if ((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - else if ((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration - * @{ - */ - -/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). - * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software - * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be - * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. - * clock cycles. - */ -#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) - -/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). - * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI14 can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI14. - * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) - -/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. - */ -#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) - -/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. - */ -#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) - -/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI14 RC. - * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_HSI14CALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ - MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) -/** - * @} - */ - -/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config - * @{ - */ - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * @param __USART1CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) - -/** @brief Macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) - -/** - * @} - */ - -/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config - * @{ - */ - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to disable the main PLL. - * @note The main PLL can not be disabled if it is used as system clock source - */ -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. - * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock - * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ - do { \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ - } while(0U) - - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) - -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - @if STM32F042x6 - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F048xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F071xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F072xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F078xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F091xC - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F098xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F030x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F030xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F031x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F038xx - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F070x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F070xB - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 - * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 - * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 - */ -#else -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source - */ -#endif -#if defined(RCC_CFGR_MCOPRE) -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) -#else - -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) - -#endif - -/** - * @} - */ - - /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macro to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, - * the RTC cannot be used in STOP and STANDBY modes. - * @note The system must always be configured so as to get a PCLK frequency greater than or - * equal to the RTCCLK frequency for a proper operation of the RTC. - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** @brief Macro to enable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** @brief Macro to disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** @brief Macro to force the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** @brief Macros to release the Backup domain reset. - */ -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. - * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready - @if STM32F038xx - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F042x6 - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F048xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F058xx - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F071xB - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F072xB - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F078xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F091xC - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F098xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @endif - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. - * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset - * @arg @ref RCC_FLAG_PINRST Pin reset. - * @arg @ref RCC_FLAG_PORRST POR/PDR reset. - * @arg @ref RCC_FLAG_SFTRST Software reset. - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. - * @arg @ref RCC_FLAG_LPWRRST Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ - (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ - (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ - RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32f0xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_H +#define __STM32F0xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 + +/** + * @} + */ + + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1U) +#define CR2_REG_INDEX ((uint8_t)2U) +#define BDCR_REG_INDEX ((uint8_t)3U) +#define CSR_REG_INDEX ((uint8_t)4U) + +/* Bits position in in the CFGR register */ +#define RCC_CFGR_PLLMUL_BITNUMBER 18U +#define RCC_CFGR_HPRE_BITNUMBER 4U +#define RCC_CFGR_PPRE_BITNUMBER 8U +/* Flags in the CFGR2 register */ +#define RCC_CFGR2_PREDIV_BITNUMBER 0 +/* Flags in the CR register */ +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 +/* Flags in the CR2 register */ +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 +/* Flags in the BDCR register */ +#define RCC_BDCR_LSERDY_BitNumber 1 +/* Flags in the CSR register */ +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 +/* Flags in the HSITRIM register */ +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_HSI14TRIM_BIT_NUMBER 3 +#define RCC_FLAG_MASK ((uint8_t)0x1FU) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ + ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ + ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ + ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ + ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ + ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ + ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ + ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t HSI14State; /*!< The new state of the HSI14. + This parameter can be a value of @ref RCC_HSI14_Config */ + + uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_HSI48_SUPPORT) + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_HSI48_SUPPORT */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) +#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ +#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Config RCC HSI14 Config + * @{ + */ +#define RCC_HSI14_OFF (0x00000000U) +#define RCC_HSI14_ON RCC_CR2_HSI14ON +#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) + +#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00U) +#define RCC_HSI48_ON ((uint8_t)0x01U) + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ +#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 +#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 + +/** + * @} + */ + +/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor + * @{ + */ + +#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +/** + * @} + */ + + +/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK + +/** + * @} + */ +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL +#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_CIR_HSI48RDYF) +#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ +#endif +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: CR2 register + * - 011: BDCR register + * - 0100: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) +/* Flags in the CR2 register */ +#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) +#if defined(RCC_CSR_V18PWRRSTF) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) +#endif +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + + +/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) +/** + * @} + */ +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration + * @{ + */ + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). + * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software + * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be + * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. + * clock cycles. + */ +#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI14 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI14 RC. + * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSI14CALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) +/** + * @} + */ + +/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) + +/** + * @} + */ + +/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ + } while(0U) + + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif +#if defined(RCC_CFGR_MCOPRE) +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#else + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + +#endif + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, + * the RTC cannot be used in STOP and STANDBY modes. + * @note The system must always be configured so as to get a PCLK frequency greater than or + * equal to the RTCCLK frequency for a proper operation of the RTC. + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready + @if STM32F038xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F042x6 + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F048xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F058xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F071xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F072xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F078xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F091xC + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F098xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ + (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h index 4804e6e..e86d950 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h @@ -1,2101 +1,2101 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_RCC_EX_H -#define __STM32F0xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) - -#else - -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#endif /* RCC_HSI48_SUPPORT */ - -#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14)) - -#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI48)) - -#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14)) - -#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Constants - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) - -/** @addtogroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV - -/** - * @} - */ - -/** @addtogroup RCC_Interrupt - * @{ - */ -#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -/** - * @} - */ - -/** @addtogroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) -/** - * @} - */ - -/** @addtogroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 -/** - * @} - */ - -/** @addtogroup RCC_System_Clock_Source_Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 -/** - * @} - */ - -#else -/** @addtogroup RCC_PLL_Clock_Source - * @{ - */ - -#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#else -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 -#endif - -/** - * @} - */ - -#endif /* RCC_HSI48_SUPPORT */ - -/** @addtogroup RCC_MCO_Clock_Source - * @{ - */ - -#if defined(RCC_CFGR_PLLNODIV) - -#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) - -#endif /* RCC_CFGR_PLLNODIV */ - -#if defined(RCC_CFGR_MCO_HSI48) - -#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 - -#endif /* SRCC_CFGR_MCO_HSI48 */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Private Constants -------------------------------------------------------------*/ -#if defined(CRS) -/** @addtogroup RCCEx_Private_Constants - * @{ - */ - -/* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) - -/* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) - -/** - * @} - */ -#endif /* CRS */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC)) -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_USB)) -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC)) -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) -#endif /* STM32F072xB || STM32F078xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) - -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLL)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLL)) - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) -#endif /* STM32F091xC || STM32F098xx */ - - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(RCC_CFGR_MCOPRE) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ - ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ - ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) -#else - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) - -#endif /* RCC_CFGR_MCOPRE */ - -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) - -#if defined(CRS) - -#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) -#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) -#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) -#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) -#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) -#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) -#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ - ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) -#endif /* CRS */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC extended clocks structure definition - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F072xB || STM32F078xx */ - - -#if defined(STM32F091xC) || defined(STM32F098xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -/** - * @brief RCC_CRS Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. - This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ - - uint32_t Source; /*!< Specifies the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ - - uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ - - uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. - It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) - This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ - - uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. - This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ - - uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ - -}RCC_CRSInitTypeDef; - -/** - * @brief RCC_CRS Synchronization structure definition - */ -typedef struct -{ - uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFFU */ - - uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3FU */ - - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter - value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFFU */ - - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. - It shows whether the actual frequency is below or above the target. - This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ - -}RCC_CRSSynchroInfoTypeDef; - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F072xB || STM32F078xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USART3 (0x00040000U) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) - -/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source - * @{ - */ -#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ -#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source - * @{ - */ -#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ -#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ - -/** - * @} - */ - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK -#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK -#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE -#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI - -/** - * @} - */ - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK -#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK -#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE -#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI - -/** - * @} - */ - -#endif /* STM32F091xC || STM32F098xx */ - - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source - * @{ - */ -#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 -#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) - -#define RCC_MCODIV_1 (0x00000000U) -#define RCC_MCODIV_2 (0x10000000U) -#define RCC_MCODIV_4 (0x20000000U) -#define RCC_MCODIV_8 (0x30000000U) -#define RCC_MCODIV_16 (0x40000000U) -#define RCC_MCODIV_32 (0x50000000U) -#define RCC_MCODIV_64 (0x60000000U) -#define RCC_MCODIV_128 (0x70000000U) - -#else - -#define RCC_MCODIV_1 (0x00000000U) - -#endif /* RCC_CFGR_MCOPRE */ - -/** - * @} - */ - -/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration - * @{ - */ - -#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Status RCCEx CRS Status - * @{ - */ -#define RCC_CRS_NONE (0x00000000U) -#define RCC_CRS_TIMEOUT (0x00000001U) -#define RCC_CRS_SYNCOK (0x00000002U) -#define RCC_CRS_SYNCWARN (0x00000004U) -#define RCC_CRS_SYNCERR (0x00000008U) -#define RCC_CRS_SYNCMISS (0x00000010U) -#define RCC_CRS_TRIMOVF (0x00000020U) - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source - * @{ - */ -#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider - * @{ - */ -#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ -#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity - * @{ - */ -#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value - * @{ - */ -#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value - * @{ - */ -#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye - * @{ - */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction - * @{ - */ -#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources - * @{ - */ -#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ -#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ -#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ -#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags - * @{ - */ -#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ -#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ -#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ -#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ -#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ -#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) -#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases peripheral reset. - * @{ - */ - -/** @brief Force or release AHB peripheral reset. - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) - -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) - -#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -/** @brief Force or release APB1 peripheral reset. - */ -#if defined(STM32F030x8) \ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) - -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) - -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - -#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) - -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) - -#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) - -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) - -#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) - -#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - - -/** @brief Force or release APB2 peripheral reset. - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) - -#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) - -#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) -#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) - -#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) -#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -/** @brief AHB Peripheral Clock Enable Disable Status - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) -#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx */ - -/** @brief APB1 Peripheral Clock Enable Disable Status - */ -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) -#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) -#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** @brief APB1 Peripheral Clock Enable Disable Status - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) -#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) -#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) -#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - - -/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable - * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI48 can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI14. - * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software - * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be - * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. - * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator - * clock cycles. - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) - -#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) -#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) - -/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_HSI48_ON HSI48 enabled - * @arg @ref RCC_HSI48_OFF HSI48 disabled - */ -#define __HAL_RCC_GET_HSI48_STATE() \ - (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) - -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config - * @{ - */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F070x6) || defined(STM32F070xB) - -/** @brief Macro to configure the USB clock (USBCLK). - * @param __USBCLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: -@if STM32F070xB -@elseif STM32F070x6 -@else - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock -@endif - * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock - */ -#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) - -/** @brief Macro to get the USB clock source. - * @retval The clock source can be one of the following values: -@if STM32F070xB -@elseif STM32F070x6 -@else - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock -@endif - * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock - */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F072xB || STM32F078xx || */ - /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @brief Macro to configure the CEC clock. - * @param __CECCLKSOURCE__ specifies the CEC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock - * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock - */ -#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) - -/** @brief Macro to get the HDMI CEC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock - * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock - */ -#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined(STM32F098xx) */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) -/** @brief Macro to configure the USART2 clock (USART2CLK). - * @param __USART2CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) - -/** @brief Macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ - -#if defined(STM32F091xC) || defined(STM32F098xx) -/** @brief Macro to configure the USART3 clock (USART3CLK). - * @param __USART3CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) - -/** @brief Macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) - -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. - * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. - * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ - RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag - * @{ - */ -/* Interrupt & Flag management */ - -/** - * @brief Enable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) - -/** - * @brief Disable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) - -/** @brief Check whether the CRS interrupt has occurred or not. - * @param __INTERRUPT__ specifies the CRS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** @brief Clear the CRS interrupt pending bits - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt - * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt - * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt - */ -#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0U) - -/** - * @brief Check whether the specified CRS flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @retval The new state of _FLAG_ (TRUE or FALSE). - */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the CRS specified FLAG. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR - * @retval None - */ -#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0U) - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ -/** - * @brief Enable the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Disable the oscillator clock for frequency error counter. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Enable the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Disable the automatic hardware adjustement of TRIM bits. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to - * reach the expected synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval None - */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ - -#if defined(CRS) - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ - -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -void HAL_RCCEx_CRS_IRQHandler(void); -void HAL_RCCEx_CRS_SyncOkCallback(void); -void HAL_RCCEx_CRS_SyncWarnCallback(void); -void HAL_RCCEx_CRS_ExpectedSyncCallback(void); -void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_EX_H +#define __STM32F0xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#else + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV + +/** + * @} + */ + +/** @addtogroup RCC_Interrupt + * @{ + */ +#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source_Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 +/** + * @} + */ + +#else +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ + +#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#else +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 +#endif + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @addtogroup RCC_MCO_Clock_Source + * @{ + */ + +#if defined(RCC_CFGR_PLLNODIV) + +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#endif /* RCC_CFGR_PLLNODIV */ + +#if defined(RCC_CFGR_MCO_HSI48) + +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 + +#endif /* SRCC_CFGR_MCO_HSI48 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Private Constants -------------------------------------------------------------*/ +#if defined(CRS) +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(RCC_CFGR_MCOPRE) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ + ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) +#else + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) + +#endif /* RCC_CFGR_MCOPRE */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) +#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) +#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) +#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ + ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +#endif /* CRS */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F072xB || STM32F078xx */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +}RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3FU */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +}RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USART3 (0x00040000U) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK +#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE +#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI + +/** + * @} + */ + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK +#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE +#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI + +/** + * @} + */ + +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 +#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) + +#define RCC_MCODIV_1 (0x00000000U) +#define RCC_MCODIV_2 (0x10000000U) +#define RCC_MCODIV_4 (0x20000000U) +#define RCC_MCODIV_8 (0x30000000U) +#define RCC_MCODIV_16 (0x40000000U) +#define RCC_MCODIV_32 (0x50000000U) +#define RCC_MCODIV_64 (0x60000000U) +#define RCC_MCODIV_128 (0x70000000U) + +#else + +#define RCC_MCODIV_1 (0x00000000U) + +#endif /* RCC_CFGR_MCOPRE */ + +/** + * @} + */ + +/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration + * @{ + */ + +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE (0x00000000U) +#define RCC_CRS_TIMEOUT (0x00000001U) +#define RCC_CRS_SYNCOK (0x00000002U) +#define RCC_CRS_SYNCWARN (0x00000004U) +#define RCC_CRS_SYNCERR (0x00000008U) +#define RCC_CRS_SYNCMISS (0x00000010U) +#define RCC_CRS_TRIMOVF (0x00000020U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) +#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases peripheral reset. + * @{ + */ + +/** @brief Force or release AHB peripheral reset. + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) + +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @brief Force or release APB1 peripheral reset. + */ +#if defined(STM32F030x8) \ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) + +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) + +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) + +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) + +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) + +#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + + +/** @brief Force or release APB2 peripheral reset. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) + +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) + +#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** @brief AHB Peripheral Clock Enable Disable Status + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) +#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) +#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) +#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable + * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI48 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software + * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be + * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. + * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator + * clock cycles. + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) + +/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSI48_ON HSI48 enabled + * @arg @ref RCC_HSI48_OFF HSI48 disabled + */ +#define __HAL_RCC_GET_HSI48_STATE() \ + (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) + +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F070x6) || defined(STM32F070xB) + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx || */ + /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @brief Macro to configure the CEC clock. + * @param __CECCLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) + +/** @brief Macro to get the HDMI CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined(STM32F098xx) */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ + RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag + * @{ + */ +/* Interrupt & Flag management */ + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0U) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustement of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Disable the automatic hardware adjustement of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h index c1149b4..410138a 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h @@ -1,1830 +1,1830 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_TIM_H -#define __STM32F0xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief TIM Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref TIM_DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP (0x0000U) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 (0x0000U) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes - * @{ - */ -#define TIM_OCMODE_TIMING (0x0000U) -#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE (0x0000U) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH (0x0000U) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH (0x0000U) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 (0x0000U) -#define TIM_CHANNEL_2 (0x0004U) -#define TIM_CHANNEL_3 (0x0008U) -#define TIM_CHANNEL_4 (0x000CU) -#define TIM_CHANNEL_ALL (0x0018U) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE (0x0000U) - -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 (0x0000U) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF (0x0000U) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable - * @{ - */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW (0x0000U) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) -/** - * @} - */ -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET (0x0000U) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave Mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE (0x0000U) -#define TIM_SLAVEMODE_RESET (0x0004U) -#define TIM_SLAVEMODE_GATED (0x0005U) -#define TIM_SLAVEMODE_TRIGGER (0x0006U) -#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) -#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 (0x0000U) -#define TIM_TS_ITR1 (0x0010U) -#define TIM_TS_ITR2 (0x0020U) -#define TIM_TS_ITR3 (0x0030U) -#define TIM_TS_TI1F_ED (0x0040U) -#define TIM_TS_TI1FP1 (0x0050U) -#define TIM_TS_TI2FP2 (0x0060U) -#define TIM_TS_ETRF (0x0070U) -#define TIM_TS_NONE (0xFFFFU) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 (0x0000U) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) -/** - * @} - */ - -/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE (0x0001U) -#define TIM_CCx_DISABLE (0x0000U) -#define TIM_CCxN_ENABLE (0x0004U) -#define TIM_CCxN_DISABLE (0x0000U) -/** - * @} - */ - -/** - * @} - */ - -/* Private Constants -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ - -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) - -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ - ((STATE) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3)) - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) - -#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_TRIGGER) || \ - ((FLAG) == TIM_FLAG_BREAK) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ - ((STATE) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ - ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ - ((BASE) == TIM_DMABASE_CR2) || \ - ((BASE) == TIM_DMABASE_SMCR) || \ - ((BASE) == TIM_DMABASE_DIER) || \ - ((BASE) == TIM_DMABASE_SR) || \ - ((BASE) == TIM_DMABASE_EGR) || \ - ((BASE) == TIM_DMABASE_CCMR1) || \ - ((BASE) == TIM_DMABASE_CCMR2) || \ - ((BASE) == TIM_DMABASE_CCER) || \ - ((BASE) == TIM_DMABASE_CNT) || \ - ((BASE) == TIM_DMABASE_PSC) || \ - ((BASE) == TIM_DMABASE_ARR) || \ - ((BASE) == TIM_DMABASE_RCR) || \ - ((BASE) == TIM_DMABASE_CCR1) || \ - ((BASE) == TIM_DMABASE_CCR2) || \ - ((BASE) == TIM_DMABASE_CCR3) || \ - ((BASE) == TIM_DMABASE_CCR4) || \ - ((BASE) == TIM_DMABASE_BDTR) || \ - ((BASE) == TIM_DMABASE_DCR) || \ - ((BASE) == TIM_DMABASE_OR)) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -/** @brief Set TIM IC prescaler - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @param __ICPSC__ specifies the prescaler value. - * @retval None - */ -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -/** @brief Reset TIM IC prescaler - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @retval None - */ -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - - -/** @brief Set TIM IC polarity - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @param __POLARITY__ specifies TIM Channel Polarity - * @retval None - */ -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) - -/** @brief Reset TIM IC polarity - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @retval None - */ -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -/** - * @} - */ - -/* Private Functions --------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state - * @param __HANDLE__ TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) -/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/* The Main Output Enable of a timer instance is disabled unconditionally */ -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled uncondiotionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** - * @brief Enables the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** - * @brief Enables the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** - * @brief Disables the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** - * @brief Checks whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clears the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Clear the TIM interrupt pending bits - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Sets the TIM active prescaler register value on update event. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the active prescaler register new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Sets the TIM Capture Compare Register value on runtime without - * calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) - -/** - * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) - -/** - * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Sets the TIM Autoreload Register value on runtime without calling - * another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Sets the TIM Clock Division value on runtime without calling - * another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Sets the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) - -/** - * @brief Resets the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) - - -/** - * @brief Sets the TIM Input Capture prescaler on runtime without calling - * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * (+) Counter overflow/underflow - * (+) Setting the UG bit - * (+) Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - -/** - * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ - -/* Include TIM HAL Extension module */ -#include "stm32f0xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 - * @{ - */ -/* Timer PWM functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions ***********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions ***************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 - * @{ - */ -/* Timer Encoder functions *****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 - * @{ - */ -/* Interrupt Handler functions **********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group9 - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group10 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** - * @} - */ - -/* Private Functions --------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_H +#define __STM32F0xx_HAL_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + + +/** + * @brief TIM Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter can be a value of @ref TIM_ClearInput_Prescaler */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct { + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +}TIM_SlaveConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +}HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +typedef struct +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref TIM_DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +}TIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP (0x0000U) +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 (0x0000U) +#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) +#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes + * @{ + */ +#define TIM_OCMODE_TIMING (0x0000U) +#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE (0x0000U) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH (0x0000U) +#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH (0x0000U) +#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) +#define TIM_OCIDLESTATE_RESET (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) +#define TIM_OCNIDLESTATE_RESET (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 (0x0000U) +#define TIM_CHANNEL_2 (0x0004U) +#define TIM_CHANNEL_3 (0x0008U) +#define TIM_CHANNEL_4 (0x000CU) +#define TIM_CHANNEL_ALL (0x0018U) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) +#define TIM_OPMODE_REPETITIVE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE (TIM_DIER_UIE) +#define TIM_IT_CC1 (TIM_DIER_CC1IE) +#define TIM_IT_CC2 (TIM_DIER_CC2IE) +#define TIM_IT_CC3 (TIM_DIER_CC3IE) +#define TIM_IT_CC4 (TIM_DIER_CC4IE) +#define TIM_IT_COM (TIM_DIER_COMIE) +#define TIM_IT_TRIGGER (TIM_DIER_TIE) +#define TIM_IT_BREAK (TIM_DIER_BIE) +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) +#define TIM_COMMUTATION_SOFTWARE (0x0000U) + +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE (TIM_DIER_UDE) +#define TIM_DMA_CC1 (TIM_DIER_CC1DE) +#define TIM_DMA_CC2 (TIM_DIER_CC2DE) +#define TIM_DMA_CC3 (TIM_DIER_CC3DE) +#define TIM_DMA_CC4 (TIM_DIER_CC4DE) +#define TIM_DMA_COM (TIM_DIER_COMDE) +#define TIM_DMA_TRIGGER (TIM_DIER_TDE) +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE (TIM_SR_UIF) +#define TIM_FLAG_CC1 (TIM_SR_CC1IF) +#define TIM_FLAG_CC2 (TIM_SR_CC2IF) +#define TIM_FLAG_CC3 (TIM_SR_CC3IF) +#define TIM_FLAG_CC4 (TIM_SR_CC4IF) +#define TIM_FLAG_COM (TIM_SR_COMIF) +#define TIM_FLAG_TRIGGER (TIM_SR_TIF) +#define TIM_FLAG_BREAK (TIM_SR_BIF) +#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) +#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) +#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) +#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 (0x0000U) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) +#define TIM_OSSR_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) +#define TIM_OSSI_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF (0x0000U) +#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) +#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) +#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable + * @{ + */ +#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) +#define TIM_BREAK_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW (0x0000U) +#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) +/** + * @} + */ +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) +#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET (0x0000U) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave Mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE (0x0000U) +#define TIM_SLAVEMODE_RESET (0x0004U) +#define TIM_SLAVEMODE_GATED (0x0005U) +#define TIM_SLAVEMODE_TRIGGER (0x0006U) +#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) +#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 (0x0000U) +#define TIM_TS_ITR1 (0x0010U) +#define TIM_TS_ITR2 (0x0020U) +#define TIM_TS_ITR3 (0x0030U) +#define TIM_TS_TI1F_ED (0x0040U) +#define TIM_TS_TI1FP1 (0x0050U) +#define TIM_TS_TI2FP2 (0x0060U) +#define TIM_TS_ETRF (0x0070U) +#define TIM_TS_NONE (0xFFFFU) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 (0x0000U) +#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 (0x00000000) +#define TIM_DMABASE_CR2 (0x00000001) +#define TIM_DMABASE_SMCR (0x00000002) +#define TIM_DMABASE_DIER (0x00000003) +#define TIM_DMABASE_SR (0x00000004) +#define TIM_DMABASE_EGR (0x00000005) +#define TIM_DMABASE_CCMR1 (0x00000006) +#define TIM_DMABASE_CCMR2 (0x00000007) +#define TIM_DMABASE_CCER (0x00000008) +#define TIM_DMABASE_CNT (0x00000009) +#define TIM_DMABASE_PSC (0x0000000A) +#define TIM_DMABASE_ARR (0x0000000B) +#define TIM_DMABASE_RCR (0x0000000C) +#define TIM_DMABASE_CCR1 (0x0000000D) +#define TIM_DMABASE_CCR2 (0x0000000E) +#define TIM_DMABASE_CCR3 (0x0000000F) +#define TIM_DMABASE_CCR4 (0x00000010) +#define TIM_DMABASE_BDTR (0x00000011) +#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_OR (0x00000013) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +/** + * @} + */ + +/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE (0x0001U) +#define TIM_CCx_DISABLE (0x0000U) +#define TIM_CCxN_ENABLE (0x0004U) +#define TIM_CCxN_DISABLE (0x0000U) +/** + * @} + */ + +/** + * @} + */ + +/* Private Constants -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ + +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ + ((STATE) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) + +#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_TRIGGER) || \ + ((FLAG) == TIM_FLAG_BREAK) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ + ((STATE) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ + ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ + ((BASE) == TIM_DMABASE_CR2) || \ + ((BASE) == TIM_DMABASE_SMCR) || \ + ((BASE) == TIM_DMABASE_DIER) || \ + ((BASE) == TIM_DMABASE_SR) || \ + ((BASE) == TIM_DMABASE_EGR) || \ + ((BASE) == TIM_DMABASE_CCMR1) || \ + ((BASE) == TIM_DMABASE_CCMR2) || \ + ((BASE) == TIM_DMABASE_CCER) || \ + ((BASE) == TIM_DMABASE_CNT) || \ + ((BASE) == TIM_DMABASE_PSC) || \ + ((BASE) == TIM_DMABASE_ARR) || \ + ((BASE) == TIM_DMABASE_RCR) || \ + ((BASE) == TIM_DMABASE_CCR1) || \ + ((BASE) == TIM_DMABASE_CCR2) || \ + ((BASE) == TIM_DMABASE_CCR3) || \ + ((BASE) == TIM_DMABASE_CCR4) || \ + ((BASE) == TIM_DMABASE_BDTR) || \ + ((BASE) == TIM_DMABASE_DCR) || \ + ((BASE) == TIM_DMABASE_OR)) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __ICPSC__ specifies the prescaler value. + * @retval None + */ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @retval None + */ +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + + +/** @brief Set TIM IC polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __POLARITY__ specifies TIM Channel Polarity + * @retval None + */ +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) + +/** @brief Reset TIM IC polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @retval None + */ +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state + * @param __HANDLE__ TIM handle. + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) +/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/* The Main Output Enable of a timer instance is disabled unconditionally */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled uncondiotionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** + * @brief Enables the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** + * @brief Enables the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disables the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Checks whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Checks whether the specified TIM interrupt has occurred or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Clear the TIM interrupt pending bits + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Sets the TIM active prescaler register value on update event. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the active prescaler register new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Sets the TIM Capture Compare Register value on runtime without + * calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) + +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) + +/** + * @brief Sets the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Sets the TIM Autoreload Register value on runtime without calling + * another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Sets the TIM Clock Division value on runtime without calling + * another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) + + +/** + * @brief Sets the TIM Input Capture prescaler on runtime without calling + * another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * (+) Counter overflow/underflow + * (+) Setting the UG bit + * (+) Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + +/** + * @brief Sets the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ + +/* Include TIM HAL Extension module */ +#include "stm32f0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @{ + */ +/* Timer PWM functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions ***********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions ***************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 + * @{ + */ +/* Timer Encoder functions *****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group9 + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h index 77125de..a504794 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h @@ -1,325 +1,325 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_TIM_EX_H -#define __STM32F0xx_HAL_TIM_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIMEx Exported Types - * @{ - */ - - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; - -/** - * @brief TIM Break and Dead time configuration Structure definition - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIMEx Remap - * @{ - */ - -#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ -#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ -#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ -#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ -/** - * @} - */ - -/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE (0x00000000U) -#define TIM_CLEARINPUTSOURCE_ETR (0x00000001U) -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U) -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined (STM32F098xx) */ -/** - * @} - */ - -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ - ((TIM_REMAP) == TIM_TIM14_RTC) ||\ - ((TIM_REMAP) == TIM_TIM14_HSE) ||\ - ((TIM_REMAP) == TIM_TIM14_MCO)) - -#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ - -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR)) -#else -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined (STM32F098xx) */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 - * @{ - */ -/* Extension Callback *********************************************************/ -void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 - * @{ - */ -/* Extension Peripheral State functions **************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_EX_H +#define __STM32F0xx_HAL_TIM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIMEx Exported Types + * @{ + */ + + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct { + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +}TIM_MasterConfigTypeDef; + +/** + * @brief TIM Break and Dead time configuration Structure definition + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIMEx Remap + * @{ + */ + +#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ +#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ +/** + * @} + */ + +/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE (0x00000000U) +#define TIM_CLEARINPUTSOURCE_ETR (0x00000001U) +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ + ((TIM_REMAP) == TIM_TIM14_RTC) ||\ + ((TIM_REMAP) == TIM_TIM14_HSE) ||\ + ((TIM_REMAP) == TIM_TIM14_MCO)) + +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 + * @{ + */ +/* Extension Callback *********************************************************/ +void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 + * @{ + */ +/* Extension Peripheral State functions **************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +* @{ +*/ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +/** +* @} +*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h index 2aa2bb6..4059159 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h @@ -1,861 +1,861 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_BUS_H -#define __STM32F0xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN -#if defined(DMA2) -#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN -#endif /*DMA2*/ -#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN -#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN -#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN -#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN -#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN -#if defined(GPIOD) -#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN -#endif /*GPIOD*/ -#if defined(GPIOE) -#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN -#endif /*GPIOE*/ -#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN -#if defined(TSC) -#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN -#endif /*TSC*/ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#if defined(TIM2) -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN -#endif /*TIM2*/ -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN -#if defined(TIM6) -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN -#endif /*TIM6*/ -#if defined(TIM7) -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN -#endif /*TIM7*/ -#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN -#if defined(SPI2) -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN -#endif /*SPI2*/ -#if defined(USART2) -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN -#endif /* USART2 */ -#if defined(USART3) -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN -#endif /* USART3 */ -#if defined(USART4) -#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN -#endif /* USART4 */ -#if defined(USART5) -#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN -#endif /* USART5 */ -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN -#if defined(I2C2) -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN -#endif /*I2C2*/ -#if defined(USB) -#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN -#endif /* USB */ -#if defined(CAN) -#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN -#endif /*CAN*/ -#if defined(CRS) -#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN -#endif /*CRS*/ -#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN -#if defined(DAC) -#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN -#endif /*DAC*/ -#if defined(CEC) -#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN -#endif /*CEC*/ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH - * @{ - */ -#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN -#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN -#if defined(USART8) -#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN -#endif /*USART8*/ -#if defined(USART7) -#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN -#endif /*USART7*/ -#if defined(USART6) -#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN -#endif /*USART6*/ -#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN -#if defined(TIM15) -#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN -#endif /*TIM15*/ -#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN -#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN -#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n - * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n - * AHBENR TSCEN LL_AHB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHBENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n - * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n - * AHBENR TSCEN LL_AHB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n - * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n - * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CECEN LL_APB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n - * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n - * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CECEN LL_APB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset (available in register 1). - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset (available in register 1). - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset (available in register 2). - * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n - * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset (available in register 2). - * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_BUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_BUS_H +#define __STM32F0xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN +#endif /*GPIOD*/ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN +#endif /*GPIOE*/ +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN +#if defined(TSC) +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN +#endif /*TSC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /*TIM2*/ +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(USART2) +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#endif /* USART2 */ +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN +#endif /* USART4 */ +#if defined(USART5) +#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN +#endif /* USART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /* USB */ +#if defined(CAN) +#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN +#endif /*CAN*/ +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN +#endif /*CRS*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /*DAC*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(USART8) +#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN +#endif /*USART8*/ +#if defined(USART7) +#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN +#endif /*USART7*/ +#if defined(USART6) +#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /*USART6*/ +#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(TIM15) +#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /*TIM15*/ +#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h index 2ae1b8f..4044db1 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h @@ -1,336 +1,336 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick - functions - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) API to access to MCU info (CPUID register) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_CORTEX_H -#define __STM32F0xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Architecture number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture - * @retval Value should be equal to 0xC for Cortex-M0 devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC20 for Cortex-M0 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_CORTEX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CORTEX_H +#define __STM32F0xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC20 for Cortex-M0 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h index 93358ce..4f154c1 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h @@ -1,799 +1,799 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_crs.h - * @author MCD Application Team - * @brief Header file of CRS LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_CRS_H -#define __STM32F0xx_LL_CRS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(CRS) - -/** @defgroup CRS_LL CRS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants - * @{ - */ - -/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_CRS_ReadReg function - * @{ - */ -#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF -#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF -#define LL_CRS_ISR_ERRF CRS_ISR_ERRF -#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF -#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR -#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS -#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF -/** - * @} - */ - -/** @defgroup CRS_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions - * @{ - */ -#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE -#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE -#define LL_CRS_CR_ERRIE CRS_CR_ERRIE -#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider - * @{ - */ -#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ -#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source - * @{ - */ -#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ -#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity - * @{ - */ -#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ -#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction - * @{ - */ -#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ -#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values - * @{ - */ -/** - * @brief Reset value of the RELOAD field - * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz - * and a synchronization signal frequency of 1 kHz (SOF signal from USB) - */ -#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) - -/** - * @brief Reset value of Frequency error limit. - */ -#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) - -/** - * @brief Reset value of the HSI48 Calibration field - * @note The default value is 32, which corresponds to the middle of the trimming interval. - * The trimming step is around 67 kHz between two consecutive TRIM steps. - * A higher TRIM value corresponds to a higher output frequency - */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros - * @{ - */ - -/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload - * @{ - */ - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between - * the target frequency and the frequency of the synchronization source after - * prescaling. It is then decreased by one in order to reach the expected - * synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval Reload value (in Hz) - */ -#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions - * @{ - */ - -/** @defgroup CRS_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable Frequency error counter - * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified - * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) -{ - SET_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Disable Frequency error counter - * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Check if Frequency error counter is enabled or not - * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); -} - -/** - * @brief Enable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) -{ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Disable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Check if Automatic trimming is enabled or not - * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); -} - -/** - * @brief Set HSI48 oscillator smooth trimming - * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only - * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 63 - * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); -} - -/** - * @brief Get HSI48 oscillator smooth trimming - * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 63 - */ -__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) -{ - return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); -} - -/** - * @brief Set counter reload value - * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter - * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF - * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT - * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); -} - -/** - * @brief Get counter reload value - * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter - * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); -} - -/** - * @brief Set frequency error limit - * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit - * @param Value a number between Min_Data = 0 and Max_Data = 255 - * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); -} - -/** - * @brief Get frequency error limit - * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit - * @retval A number between Min_Data = 0 and Max_Data = 255 - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); -} - -/** - * @brief Set division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider - * @param Divider This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); -} - -/** - * @brief Get division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); -} - -/** - * @brief Set SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); -} - -/** - * @brief Get SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); -} - -/** - * @brief Set input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); -} - -/** - * @brief Get input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); -} - -/** - * @brief Configure CRS for the synchronization - * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n - * CFGR RELOAD LL_CRS_ConfigSynchronization\n - * CFGR FELIM LL_CRS_ConfigSynchronization\n - * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n - * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n - * CFGR SYNCPOL LL_CRS_ConfigSynchronization - * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 - * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF - * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 - * @param Settings This parameter can be a combination of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 - * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB - * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); - MODIFY_REG(CRS->CFGR, - CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, - ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_CRS_Management CRS_Management - * @{ - */ - -/** - * @brief Generate software SYNC event - * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Get the frequency error direction latched in the time of the last - * SYNC event - * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP - * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** - * @brief Get the frequency error counter value latched in the time of the last SYNC event - * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture - * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if SYNC event OK signal occurred or not - * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); -} - -/** - * @brief Check if SYNC warning signal occurred or not - * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); -} - -/** - * @brief Check if Synchronization or trimming error signal occurred or not - * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); -} - -/** - * @brief Check if Expected SYNC signal occurred or not - * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); -} - -/** - * @brief Check if SYNC error signal occurred or not - * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); -} - -/** - * @brief Check if SYNC missed error signal occurred or not - * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); -} - -/** - * @brief Check if Trimming overflow or underflow occurred or not - * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); -} - -/** - * @brief Clear the SYNC event OK flag - * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); -} - -/** - * @brief Clear the SYNC warning flag - * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); -} - -/** - * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also - * the ERR flag - * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); -} - -/** - * @brief Clear Expected SYNC flag - * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Disable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Check if SYNC event OK interrupt is enabled or not - * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); -} - -/** - * @brief Enable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Disable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Check if SYNC warning interrupt is enabled or not - * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); -} - -/** - * @brief Enable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) -{ - SET_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Disable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Check if Synchronization or trimming error interrupt is enabled or not - * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); -} - -/** - * @brief Enable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Disable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Check if Expected SYNC interrupt is enabled or not - * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_CRS_DeInit(void); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(CRS) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_CRS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CRS_H +#define __STM32F0xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. + * A higher TRIM value corresponds to a higher output frequency + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CRS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h index 4c60438..9d9eb97 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h @@ -1,2224 +1,2224 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_DMA_H -#define __STM32F0xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ -static const uint8_t CHANNEL_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), -#if defined(DMA1_Channel6) - (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), -#endif /*DMA1_Channel6*/ -#if defined(DMA1_Channel7) - (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) -#endif /*DMA1_Channel7*/ -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Constants DMA Private Constants - * @{ - */ -/* Define used to get CSELR register offset */ -#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) - -/* Defines used for the bit position in the register and perform offsets */ -#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_Private_Macros DMA Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note: The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Channel - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - - uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMA_LL_EC_REQUEST - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ -#endif - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ -/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_DMA_WriteReg function - * @{ - */ -#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ -#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ -#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ -#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ -#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ -#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ -#if defined(DMA1_Channel6) -#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ -#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ -#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ -#endif -/** - * @} - */ - -/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_DMA_ReadReg function - * @{ - */ -#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ -#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ -#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ -#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ -#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ -#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ -#if defined(DMA1_Channel6) -#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ -#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ -#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ -#endif -/** - * @} - */ - -/** @defgroup DMA_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions - * @{ - */ -#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ -#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ -#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ -#if defined(DMA1_Channel6) -#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ -#endif -#if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ -#endif /*USE_FULL_LL_DRIVER*/ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE Transfer mode - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode - * @{ - */ -#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY Memory increment mode - * @{ - */ -#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) -/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request - * @{ - */ -#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ -#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ -#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ -#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ -#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ -#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ -#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ -#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ -#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ -/** - * @} - */ -#endif - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely - * @{ - */ -/** - * @brief Convert DMAx_Channely into DMAx - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval DMAx - */ -#if defined(DMA2) -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) -#else -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) -#endif - -/** - * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval LL_DMA_CHANNEL_y - */ -#if defined (DMA2) -#if defined (DMA2_Channel6) && defined (DMA2_Channel7) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#else -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#endif -#else -#if defined (DMA1_Channel6) && defined (DMA1_Channel7) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#elif defined (DMA1_Channel6) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - LL_DMA_CHANNEL_6) -#else -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - LL_DMA_CHANNEL_5) -#endif /* DMA1_Channel6 && DMA1_Channel7 */ -#endif - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely - * @param __DMA_INSTANCE__ DMAx - * @param __CHANNEL__ LL_DMA_CHANNEL_y - * @retval DMAx_Channely - */ -#if defined (DMA2) -#if defined (DMA2_Channel6) && defined (DMA2_Channel7) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ - DMA2_Channel7) -#else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#endif -#else -#if defined (DMA1_Channel6) && defined (DMA1_Channel7) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#elif defined (DMA1_Channel6) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - DMA1_Channel6) -#else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - DMA1_Channel5) -#endif /* DMA1_Channel6 && DMA1_Channel7 */ -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA channel. - * @rmtoll CCR EN LL_DMA_EnableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Disable DMA channel. - * @rmtoll CCR EN LL_DMA_DisableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Check if DMA channel is enabled or disabled. - * @rmtoll CCR EN LL_DMA_IsEnabledChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); -} - -/** - * @brief Configure all parameters link to DMA transfer. - * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n - * CCR MEM2MEM LL_DMA_ConfigTransfer\n - * CCR CIRC LL_DMA_ConfigTransfer\n - * CCR PINC LL_DMA_ConfigTransfer\n - * CCR MINC LL_DMA_ConfigTransfer\n - * CCR PSIZE LL_DMA_ConfigTransfer\n - * CCR MSIZE LL_DMA_ConfigTransfer\n - * CCR PL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); -} - -/** - * @brief Set DMA mode circular or normal. - * @note The circular buffer mode cannot be used if the memory-to-memory - * data transfer is configured on the selected Channel. - * @rmtoll CCR CIRC LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, - Mode); -} - -/** - * @brief Get DMA mode circular or normal. - * @rmtoll CCR CIRC LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_CIRC)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, - PeriphOrM2MSrcIncMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, - MemoryOrM2MDstIncMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, - PeriphOrM2MSrcDataSize); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CCR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, - MemoryOrM2MDstDataSize); -} - -/** - * @brief Get Memory size. - * @rmtoll CCR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MSIZE)); -} - -/** - * @brief Set Channel priority level. - * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, - Priority); -} - -/** - * @brief Get Channel priority level. - * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @note This action has no effect if - * channel is enabled. - * @rmtoll CNDTR NDT LL_DMA_SetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @note Once the channel is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @rmtoll CNDTR NDT LL_DMA_GetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT)); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). - * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n - * CMAR MA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, - uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); -} - -/** - * @brief Get Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CMAR MA LL_DMA_GetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @brief Get Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CPAR PA LL_DMA_GetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Get the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Get the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) -/** - * @brief Set DMA request for DMA instance on Channel x. - * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. - * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n - * CSELR C2S LL_DMA_SetPeriphRequest\n - * CSELR C3S LL_DMA_SetPeriphRequest\n - * CSELR C4S LL_DMA_SetPeriphRequest\n - * CSELR C5S LL_DMA_SetPeriphRequest\n - * CSELR C6S LL_DMA_SetPeriphRequest\n - * CSELR C7S LL_DMA_SetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphRequest This parameter can be one of the following values: - * @arg @ref LL_DMA_REQUEST_0 - * @arg @ref LL_DMA_REQUEST_1 - * @arg @ref LL_DMA_REQUEST_2 - * @arg @ref LL_DMA_REQUEST_3 - * @arg @ref LL_DMA_REQUEST_4 - * @arg @ref LL_DMA_REQUEST_5 - * @arg @ref LL_DMA_REQUEST_6 - * @arg @ref LL_DMA_REQUEST_7 - * @arg @ref LL_DMA_REQUEST_8 - * @arg @ref LL_DMA_REQUEST_9 - * @arg @ref LL_DMA_REQUEST_10 - * @arg @ref LL_DMA_REQUEST_11 - * @arg @ref LL_DMA_REQUEST_12 - * @arg @ref LL_DMA_REQUEST_13 - * @arg @ref LL_DMA_REQUEST_14 - * @arg @ref LL_DMA_REQUEST_15 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) -{ - MODIFY_REG(DMAx->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); -} - -/** - * @brief Get DMA request for DMA instance on Channel x. - * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n - * CSELR C2S LL_DMA_GetPeriphRequest\n - * CSELR C3S LL_DMA_GetPeriphRequest\n - * CSELR C4S LL_DMA_GetPeriphRequest\n - * CSELR C5S LL_DMA_GetPeriphRequest\n - * CSELR C6S LL_DMA_GetPeriphRequest\n - * CSELR C7S LL_DMA_GetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_REQUEST_0 - * @arg @ref LL_DMA_REQUEST_1 - * @arg @ref LL_DMA_REQUEST_2 - * @arg @ref LL_DMA_REQUEST_3 - * @arg @ref LL_DMA_REQUEST_4 - * @arg @ref LL_DMA_REQUEST_5 - * @arg @ref LL_DMA_REQUEST_6 - * @arg @ref LL_DMA_REQUEST_7 - * @arg @ref LL_DMA_REQUEST_8 - * @arg @ref LL_DMA_REQUEST_9 - * @arg @ref LL_DMA_REQUEST_10 - * @arg @ref LL_DMA_REQUEST_11 - * @arg @ref LL_DMA_REQUEST_12 - * @arg @ref LL_DMA_REQUEST_13 - * @arg @ref LL_DMA_REQUEST_14 - * @arg @ref LL_DMA_REQUEST_15 - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(DMAx->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); -} -#endif - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Channel 1 global interrupt flag. - * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); -} - -/** - * @brief Get Channel 2 global interrupt flag. - * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); -} - -/** - * @brief Get Channel 3 global interrupt flag. - * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); -} - -/** - * @brief Get Channel 4 global interrupt flag. - * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); -} - -/** - * @brief Get Channel 5 global interrupt flag. - * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 global interrupt flag. - * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 global interrupt flag. - * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); -} -#endif - -/** - * @brief Get Channel 1 transfer complete flag. - * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); -} - -/** - * @brief Get Channel 2 transfer complete flag. - * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); -} - -/** - * @brief Get Channel 3 transfer complete flag. - * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); -} - -/** - * @brief Get Channel 4 transfer complete flag. - * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); -} - -/** - * @brief Get Channel 5 transfer complete flag. - * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 transfer complete flag. - * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 transfer complete flag. - * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); -} -#endif - -/** - * @brief Get Channel 1 half transfer flag. - * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); -} - -/** - * @brief Get Channel 2 half transfer flag. - * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); -} - -/** - * @brief Get Channel 3 half transfer flag. - * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); -} - -/** - * @brief Get Channel 4 half transfer flag. - * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); -} - -/** - * @brief Get Channel 5 half transfer flag. - * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 half transfer flag. - * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 half transfer flag. - * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); -} -#endif - -/** - * @brief Get Channel 1 transfer error flag. - * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); -} - -/** - * @brief Get Channel 2 transfer error flag. - * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); -} - -/** - * @brief Get Channel 3 transfer error flag. - * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); -} - -/** - * @brief Get Channel 4 transfer error flag. - * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); -} - -/** - * @brief Get Channel 5 transfer error flag. - * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 transfer error flag. - * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 transfer error flag. - * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); -} -#endif - -/** - * @brief Clear Channel 1 global interrupt flag. - * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); -} - -/** - * @brief Clear Channel 2 global interrupt flag. - * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); -} - -/** - * @brief Clear Channel 3 global interrupt flag. - * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); -} - -/** - * @brief Clear Channel 4 global interrupt flag. - * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); -} - -/** - * @brief Clear Channel 5 global interrupt flag. - * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 global interrupt flag. - * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 global interrupt flag. - * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); -} -#endif - -/** - * @brief Clear Channel 1 transfer complete flag. - * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); -} - -/** - * @brief Clear Channel 2 transfer complete flag. - * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); -} - -/** - * @brief Clear Channel 3 transfer complete flag. - * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); -} - -/** - * @brief Clear Channel 4 transfer complete flag. - * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); -} - -/** - * @brief Clear Channel 5 transfer complete flag. - * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 transfer complete flag. - * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 transfer complete flag. - * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); -} -#endif - -/** - * @brief Clear Channel 1 half transfer flag. - * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); -} - -/** - * @brief Clear Channel 2 half transfer flag. - * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); -} - -/** - * @brief Clear Channel 3 half transfer flag. - * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); -} - -/** - * @brief Clear Channel 4 half transfer flag. - * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); -} - -/** - * @brief Clear Channel 5 half transfer flag. - * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 half transfer flag. - * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 half transfer flag. - * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); -} -#endif - -/** - * @brief Clear Channel 1 transfer error flag. - * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); -} - -/** - * @brief Clear Channel 2 transfer error flag. - * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); -} - -/** - * @brief Clear Channel 3 transfer error flag. - * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); -} - -/** - * @brief Clear Channel 4 transfer error flag. - * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); -} - -/** - * @brief Clear Channel 5 transfer error flag. - * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 transfer error flag. - * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 transfer error flag. - * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); -} -#endif - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Check if Transfer complete Interrupt is enabled. - * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); -} - -/** - * @brief Check if Half transfer Interrupt is enabled. - * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); -} - -/** - * @brief Check if Transfer error Interrupt is enabled. - * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_DMA_H +#define __STM32F0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /*DMA1_Channel6*/ +#if defined(DMA1_Channel7) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +#endif /*DMA1_Channel7*/ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/* Define used to get CSELR register offset */ +#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + +/* Defines used for the bit position in the register and perform offsets */ +#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMA_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ +/** + * @} + */ +#endif + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + LL_DMA_CHANNEL_6) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + DMA1_Channel6) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** + * @brief Set DMA request for DMA instance on Channel x. + * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. + * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n + * CSELR C2S LL_DMA_SetPeriphRequest\n + * CSELR C3S LL_DMA_SetPeriphRequest\n + * CSELR C4S LL_DMA_SetPeriphRequest\n + * CSELR C5S LL_DMA_SetPeriphRequest\n + * CSELR C6S LL_DMA_SetPeriphRequest\n + * CSELR C7S LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) +{ + MODIFY_REG(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); +} + +/** + * @brief Get DMA request for DMA instance on Channel x. + * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n + * CSELR C2S LL_DMA_GetPeriphRequest\n + * CSELR C3S LL_DMA_GetPeriphRequest\n + * CSELR C4S LL_DMA_GetPeriphRequest\n + * CSELR C5S LL_DMA_GetPeriphRequest\n + * CSELR C6S LL_DMA_GetPeriphRequest\n + * CSELR C7S LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} +#endif + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} +#endif + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h index 7ef46fa..647409c 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h @@ -1,1032 +1,1032 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_EXTI_H -#define __STM32F0xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#if defined(EXTI_IMR_IM16) -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#endif -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#endif -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#if defined(EXTI_IMR_IM20) -#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ -#endif -#if defined(EXTI_IMR_IM21) -#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ -#endif -#if defined(EXTI_IMR_IM22) -#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ -#endif -#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ -#if defined(EXTI_IMR_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ -#endif -#if defined(EXTI_IMR_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ -#endif -#if defined(EXTI_IMR_IM26) -#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ -#endif -#if defined(EXTI_IMR_IM27) -#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ -#endif -#if defined(EXTI_IMR_IM28) -#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ -#endif -#if defined(EXTI_IMR_IM29) -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ -#endif -#if defined(EXTI_IMR_IM30) -#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ -#endif -#if defined(EXTI_IMR_IM31) -#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ -#endif -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ - - -#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); - -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - - -/** - * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); -} - - -/** - * @brief Clear ExtLine Flags for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_EXTI_H +#define __STM32F0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h index 84c3fb5..2782b06 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h @@ -1,955 +1,955 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_GPIO_H -#define __STM32F0xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) - -/** @defgroup GPIO_LL GPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ - GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ - GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ - GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ - GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ - GPIO_BSRR_BS_15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ -/** - * @} - */ -#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW -#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM -#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), - ((((Pin * Pin) * Pin) * Pin) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * - (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); -} - - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) -{ - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BRR, PinMask); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_GPIO_H +#define __STM32F0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h index 02a4bf4..3a6449d 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h @@ -1,568 +1,568 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_PWR_H -#define __STM32F0xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ -#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ -#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#if defined(PWR_PVD_SUPPORT) -#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#endif /* PWR_PVD_SUPPORT */ -#if defined(PWR_CSR_VREFINTRDYF) -#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ -#endif /* PWR_CSR_VREFINTRDYF */ -#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ -#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ -#endif /* PWR_CSR_EWUP3 */ -#if defined(PWR_CSR_EWUP4) -#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ -#endif /* PWR_CSR_EWUP4 */ -#if defined(PWR_CSR_EWUP5) -#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ -#endif /* PWR_CSR_EWUP5 */ -#if defined(PWR_CSR_EWUP6) -#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ -#endif /* PWR_CSR_EWUP6 */ -#if defined(PWR_CSR_EWUP7) -#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ -#endif /* PWR_CSR_EWUP7 */ -#if defined(PWR_CSR_EWUP8) -#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ -#endif /* PWR_CSR_EWUP8 */ -/** - * @} - */ - - -/** @defgroup PWR_LL_EC_MODE_PWR Mode Power - * @{ - */ -#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ -/** - * @} - */ - -#if defined(PWR_CR_LPDS) -/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode - * @{ - */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ -/** - * @} - */ -#endif /* PWR_CR_LPDS */ - -#if defined(PWR_PVD_SUPPORT) -/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level - * @{ - */ -#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ -#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ -#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ -#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ -#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ -#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ -#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ -#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ -/** - * @} - */ -#endif /* PWR_PVD_SUPPORT */ -/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins - * @{ - */ -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ -#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ -#endif /* PWR_CSR_EWUP3 */ -#if defined(PWR_CSR_EWUP4) -#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ -#endif /* PWR_CSR_EWUP4 */ -#if defined(PWR_CSR_EWUP5) -#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ -#endif /* PWR_CSR_EWUP5 */ -#if defined(PWR_CSR_EWUP6) -#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ -#endif /* PWR_CSR_EWUP6 */ -#if defined(PWR_CSR_EWUP7) -#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ -#endif /* PWR_CSR_EWUP7 */ -#if defined(PWR_CSR_EWUP8) -#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ -#endif /* PWR_CSR_EWUP8 */ -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable access to the backup domain - * @rmtoll CR DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Disable access to the backup domain - * @rmtoll CR DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Check if the backup domain is enabled - * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); -} - -#if defined(PWR_CR_LPDS) -/** - * @brief Set voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_SetRegulModeDS - * @param RegulMode This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) -{ - MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); -} - -/** - * @brief Get voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_GetRegulModeDS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); -} -#endif /* PWR_CR_LPDS */ - -/** - * @brief Set Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPDS LL_PWR_SetPowerMode - * @param PDMode This parameter can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) -{ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); -} - -/** - * @brief Get Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPDS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); -} - -#if defined(PWR_PVD_SUPPORT) -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector - * @rmtoll CR PLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); -} - -/** - * @brief Get the voltage threshold detection - * @rmtoll CR PLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); -} - -/** - * @brief Enable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Disable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Check if Power Voltage Detector is enabled - * @rmtoll CR PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); -} -#endif /* PWR_PVD_SUPPORT */ - -/** - * @brief Enable the WakeUp PINx functionality - * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Disable the WakeUp PINx functionality - * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Check if the WakeUp PINx functionality is enabled - * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); -} - - -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Wake-up Flag - * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); -} - -/** - * @brief Get Standby Flag - * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); -} - -#if defined(PWR_PVD_SUPPORT) -/** - * @brief Indicate whether VDD voltage is below the selected PVD threshold - * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); -} -#endif /* PWR_PVD_SUPPORT */ - -#if defined(PWR_CSR_VREFINTRDYF) -/** - * @brief Get Internal Reference VrefInt Flag - * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); -} -#endif /* PWR_CSR_VREFINTRDYF */ -/** - * @brief Clear Standby Flag - * @rmtoll CR CSBF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - SET_BIT(PWR->CR, PWR_CR_CSBF); -} - -/** - * @brief Clear Wake-up Flags - * @rmtoll CR CWUF LL_PWR_ClearFlag_WU - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) -{ - SET_BIT(PWR->CR, PWR_CR_CWUF); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_PWR_H +#define __STM32F0xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h index 93f2327..50bba6b 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h @@ -1,2257 +1,2257 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_RCC_H -#define __STM32F0xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Constants RCC Private Constants - * @{ - */ -/* Defines used for the bit position in the register and perform offsets*/ -#define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ -#define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ -#define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ -#define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ -#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ -#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ -#if defined(RCC_HSI48_SUPPORT) - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ -#endif /* HSI48_VALUE */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ -#endif /* RCC_HSI48_SUPPORT */ -#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#endif /* RCC_HSI48_SUPPORT */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -#if defined(RCC_CSR_V18PWRRSTF) -#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ -#endif /* RCC_CSR_V18PWRRSTF */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability - * @{ - */ -#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -#if defined(RCC_CFGR_SW_HSI48) -#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ -#endif /* RCC_CFGR_SW_HSI48 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -#if defined(RCC_CFGR_SWS_HSI48) -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ -#endif /* RCC_CFGR_SWS_HSI48 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ -#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ -#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ -#if defined(RCC_CFGR_MCOSEL_HSI48) -#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ -#endif /* RCC_CFGR_MCOSEL_HSI48 */ -#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ -#if defined(RCC_CFGR_PLLNODIV) -#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ -#endif /* RCC_CFGR_PLLNODIV */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ -#if defined(RCC_CFGR_MCOPRE) -#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ -#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ -#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ -#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ -#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ -#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ -#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ -#endif /* RCC_CFGR_MCOPRE */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ -#if defined(RCC_CFGR3_USART2SW) -#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) -#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ -#endif /* RCC_CFGR3_USART3SW */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ -/** - * @} - */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ -#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ -/** - * @} - */ - -#endif /* CEC */ - -#if defined(USB) -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#if defined(RCC_CFGR3_USBSW_HSI48) -#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ -#else -#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ -#endif /*RCC_CFGR3_USBSW_HSI48*/ -#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ -/** - * @} - */ - -#endif /* USB */ - -/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ -#if defined(RCC_CFGR3_USART2SW) -#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) -#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ -#endif /* RCC_CFGR3_USART3SW */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ -/** - * @} - */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ -/** - * @} - */ -#endif /* CEC */ - -#if defined(USB) -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ -/** - * @} - */ -#endif /* USB */ - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor - * @{ - */ -#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ -#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ -#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ -#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ -#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ -#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ -#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ -#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ -#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ -#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ -#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ -#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ -#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ -#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ -#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE - * @{ - */ -#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ -#if defined(RCC_CFGR_SW_HSI48) -#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ -#endif /* RCC_CFGR_SW_HSI48 */ -#else -#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor - * @{ - */ -#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ -#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ -#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ -#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ -#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ -#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ -#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ -#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ -#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ -#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ -#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ -#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ -#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ -#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ -#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ -#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() - * , @ref LL_RCC_PLL_GetPrediv()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) - * @param __PLLMUL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @param __PLLPREDIV__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ - (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) - -#else -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) - * @param __PLLMUL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ - ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -/** - * @brief Helper macro to calculate the HCLK frequency - * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler - * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) - * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler - * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Disable the Clock Security System. - * @note Cannot be disabled in HSE is ready (only by hardware) - * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 16, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value between Min_Data = 0x00 and Max_Data = 0x1F - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); -} - -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_LL_EF_HSI48 HSI48 - * @{ - */ - -/** - * @brief Enable HSI48 - * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Enable(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); -} - -/** - * @brief Disable HSI48 - * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Disable(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); -} - -/** - * @brief Check if HSI48 oscillator Ready - * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) -{ - return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); -} - -/** - * @brief Get HSI48 Calibration value - * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); -} - -/** - * @} - */ - -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_LL_EF_HSI14 HSI14 - * @{ - */ - -/** - * @brief Enable HSI14 - * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_Enable(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); -} - -/** - * @brief Disable HSI14 - * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_Disable(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); -} - -/** - * @brief Check if HSI14 oscillator Ready - * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) -{ - return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); -} - -/** - * @brief ADC interface can turn on the HSI14 oscillator - * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); -} - -/** - * @brief ADC interface can not turn on the HSI14 oscillator - * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); -} - -/** - * @brief Set HSI14 Calibration trimming - * @note user-programmable trimming value that is added to the HSI14CAL - * @note Default value is 16, which, when added to the HSI14CAL value, - * should trim the HSI14 to 14 MHz +/- 1 % - * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming - * @param Value between Min_Data = 0x00 and Max_Data = 0xFF - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); -} - -/** - * @brief Get HSI14 Calibration value - * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of - * HSI14TRIM and the factory trim value - * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); -} - -/** - * @brief Get HSI14 Calibration trimming - * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Set LSE oscillator drive capability - * @note The oscillator is in Xtal mode when it is not in bypass mode. - * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability - * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); -} - -/** - * @brief Get LSE oscillator drive capability - * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); -} - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n - * CFGR MCOPRE LL_RCC_ConfigMCO\n - * CFGR PLLNODIV LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_HSI14 - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_LSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 - * - * (*) value not defined in all devices - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 (*) - * @arg @ref LL_RCC_MCO1_DIV_4 (*) - * @arg @ref LL_RCC_MCO1_DIV_8 (*) - * @arg @ref LL_RCC_MCO1_DIV_16 (*) - * @arg @ref LL_RCC_MCO1_DIV_32 (*) - * @arg @ref LL_RCC_MCO1_DIV_64 (*) - * @arg @ref LL_RCC_MCO1_DIV_128 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ -#if defined(RCC_CFGR_MCOPRE) -#if defined(RCC_CFGR_PLLNODIV) - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); -#else - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); -#endif /* RCC_CFGR_PLLNODIV */ -#else - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); -#endif /* RCC_CFGR_MCOPRE */ -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -/** - * @brief Configure USARTx clock source - * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n - * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n - * CFGR3 USART3SW LL_RCC_SetUSARTClockSource - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) -{ - MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); -} - -/** - * @brief Configure I2Cx clock source - * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); -} - -#if defined(CEC) -/** - * @brief Configure CEC clock source - * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource - * @param CECxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); -} -#endif /* CEC */ - -#if defined(USB) -/** - * @brief Configure USB clock source - * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); -} -#endif /* USB */ - -/** - * @brief Get USARTx clock source - * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n - * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n - * CFGR3 USART3SW LL_RCC_GetUSARTClockSource - * @param USARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); -} - -/** - * @brief Get I2Cx clock source - * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource - * @param I2Cx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); -} - -#if defined(CEC) -/** - * @brief Get CEC clock source - * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource - * @param CECx This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); -} -#endif /* CEC */ - -#if defined(USB) -/** - * @brief Get USBx clock source - * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); -} -#endif /* USB */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed any more unless - * the Backup domain is reset. The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); -} - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -/** - * @brief Configure PLL used for SYSCLK Domain - * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - * @param PLLMul This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @param PLLDiv This parameter can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); -} - -#else - -/** - * @brief Configure PLL used for SYSCLK Domain - * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 - * @param PLLMul This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); -} -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI (*) - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); -} - -/** - * @brief Get PLL multiplication Factor - * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); -} - -/** - * @brief Get PREDIV division factor for the main PLL - * @note They can be written only when the PLL is disabled - * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); -} - -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); -} - -/** - * @brief Clear HSI14 ready interrupt flag - * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Clear HSI48 ready interrupt flag - * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_CSSC); -} - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); -} - -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); -} - -/** - * @brief Check if HSI14 ready interrupt occurred or not - * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Check if HSI48 ready interrupt occurred or not - * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); -} - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); -} - -/** - * @brief Check if RCC flag is set or not. - * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); -} - -/** - * @brief Check if RCC flag POR/PDR reset is set or not. - * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); -} - -#if defined(RCC_CSR_V18PWRRSTF) -/** - * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. - * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); -} -#endif /* RCC_CSR_V18PWRRSTF */ - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Enable HSI14 ready interrupt - * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Enable HSI48 ready interrupt - * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Disable HSI14 ready interrupt - * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Disable HSI48 ready interrupt - * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); -} - -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); -} - -/** - * @brief Checks if HSI14 ready interrupt source is enabled or disabled. - * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Checks if HSI48 ready interrupt source is enabled or disabled. - * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); -#if defined(USB_OTG_FS) || defined(USB) -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#endif /* USB_OTG_FS || USB */ -#if defined(CEC) -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); -#endif /* CEC */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RCC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_RCC_H +#define __STM32F0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used for the bit position in the register and perform offsets*/ +#define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ +#define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#if defined(RCC_CSR_V18PWRRSTF) +#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ +#endif /* RCC_CSR_V18PWRRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ +#endif /* RCC_CFGR_SW_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#if defined(RCC_CFGR_SWS_HSI48) +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ +#endif /* RCC_CFGR_SWS_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#if defined(RCC_CFGR_MCOSEL_HSI48) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ +#endif /* RCC_CFGR_MCOSEL_HSI48 */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_PLLNODIV) +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ +#endif /* RCC_CFGR_PLLNODIV */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ +#if defined(RCC_CFGR_MCOPRE) +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ +#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ +#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ +#endif /* RCC_CFGR_MCOPRE */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ +/** + * @} + */ + +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_CFGR3_USBSW_HSI48) +#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ +#endif /*RCC_CFGR3_USBSW_HSI48*/ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ +/** + * @} + */ + +#endif /* USB */ + +/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* USB */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ +#endif /* RCC_CFGR_SW_HSI48 */ +#else +#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + * , @ref LL_RCC_PLL_GetPrediv()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param __PLLPREDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disable the Clock Security System. + * @note Cannot be disabled in HSE is ready (only by hardware) + * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); +} + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_HSI14 HSI14 + * @{ + */ + +/** + * @brief Enable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Disable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Check if HSI14 oscillator Ready + * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); +} + +/** + * @brief ADC interface can turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief ADC interface can not turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief Set HSI14 Calibration trimming + * @note user-programmable trimming value that is added to the HSI14CAL + * @note Default value is 16, which, when added to the HSI14CAL value, + * should trim the HSI14 to 14 MHz +/- 1 % + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration value + * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + * HSI14TRIM and the factory trim value + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration trimming + * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO\n + * CFGR PLLNODIV LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_HSI14 + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * + * (*) value not defined in all devices + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 (*) + * @arg @ref LL_RCC_MCO1_DIV_4 (*) + * @arg @ref LL_RCC_MCO1_DIV_8 (*) + * @arg @ref LL_RCC_MCO1_DIV_16 (*) + * @arg @ref LL_RCC_MCO1_DIV_32 (*) + * @arg @ref LL_RCC_MCO1_DIV_64 (*) + * @arg @ref LL_RCC_MCO1_DIV_128 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ +#if defined(RCC_CFGR_MCOPRE) +#if defined(RCC_CFGR_PLLNODIV) + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +#endif /* RCC_CFGR_PLLNODIV */ +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +#endif /* RCC_CFGR_MCOPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); +} + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); +} +#endif /* USB */ + +/** + * @brief Get USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); +} + +#if defined(CEC) +/** + * @brief Get CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); +} +#endif /* USB */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); +} + +#else + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); +} +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get PREDIV division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear HSI14 ready interrupt flag + * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if HSI14 ready interrupt occurred or not + * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_V18PWRRSTF) +/** + * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. + * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); +} +#endif /* RCC_CSR_V18PWRRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Enable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @brief Checks if HSI14 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h index 7eecd25..65af161 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h @@ -1,1868 +1,1868 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_SYSTEM_H -#define __STM32F0xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap -* @{ -*/ -#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ -/** - * @} - */ - -#if defined(SYSCFG_CFGR1_IR_MOD) -/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation - * @{ - */ -#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */ -#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */ -#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_IR_MOD */ - -#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap - * @{ - */ -#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) -#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */ -#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */ -#endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) -#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */ -#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */ -#endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART2_DMA_RMP) -#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */ -#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -#endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART3_DMA_RMP) -#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */ -#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ -/** - * @} - */ -#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ - -#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap - * @{ - */ -#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */ -#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -/** - * @} - */ - -#endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ - -#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap - * @{ - */ -#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */ -#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */ -/** - * @} - */ - -#endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ - -#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap - * @{ - */ -#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */ -#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap - * @{ - */ -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) -#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) -#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */ -#else -#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ -#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) -#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) -#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */ -#else -#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ -#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ -#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ -#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) -#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */ -#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ -#endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) -#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */ -#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ -#endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) -#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */ -#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */ -#endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ - -/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS - * @{ - */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */ -#endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) -#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) -#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT - * @{ - */ -#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ -#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ -#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ -#if defined(GPIOD_BASE) -#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ -#endif /*GPIOD_BASE*/ -#if defined(GPIOE_BASE) -#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ -#endif /*GPIOE_BASE*/ -#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE - * @{ - */ -#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK - * @{ - */ -#if defined(SYSCFG_CFGR2_PVD_LOCK) -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection - with TIM1/15/16U/17 Break Input and also - the PVDE and PLS bits of the Power Control Interface */ -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal - with Break Input of TIM1/15/16/17 */ -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of - CortexM0 with Break Input of TIM1/15/16/17 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ -#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ -#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ -#endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ -#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ - -/** - * @brief Set memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory - * @param Memory This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); -} - -/** - * @brief Get memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); -} - -#if defined(SYSCFG_CFGR1_IR_MOD) -/** - * @brief Set IR Modulation Envelope signal source. - * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_IR_MOD_TIM16 - * @arg @ref LL_SYSCFG_IR_MOD_USART1 - * @arg @ref LL_SYSCFG_IR_MOD_USART4 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); -} - -/** - * @brief Get IR Modulation Envelope signal source. - * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_IR_MOD_TIM16 - * @arg @ref LL_SYSCFG_IR_MOD_USART1 - * @arg @ref LL_SYSCFG_IR_MOD_USART4 - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); -} -#endif /* SYSCFG_CFGR1_IR_MOD */ - -#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) -/** - * @brief Set DMA request remapping bits for USART - * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) - * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) - * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) - * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) - * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) - * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) - * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) - * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); -} -#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) -/** - * @brief Set DMA request remapping bits for SPI - * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 - * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) -/** - * @brief Set DMA request remapping bits for I2C - * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 - * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) -/** - * @brief Set DMA request remapping bits for ADC - * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 - * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) -/** - * @brief Set DMA request remapping bits for TIM - * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) - * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) - * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) - * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) - * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) - * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) - * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); -} -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** - * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either - * PA9/10 or PA11/12 pin pair on small pin-count packages) - * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); -} - -/** - * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either - * PA9/10 or PA11/12 pin pair on small pin-count packages) - * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); -} -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Configure source input for the EXTI external interrupt. - * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource - * @param Port This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD (*) - * @arg @ref LL_SYSCFG_EXTI_PORTE (*) - * @arg @ref LL_SYSCFG_EXTI_PORTF - * - * (*) value not defined in all devices - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) -{ - MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16)); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD (*) - * @arg @ref LL_SYSCFG_EXTI_PORTE (*) - * @arg @ref LL_SYSCFG_EXTI_PORTF - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) -{ - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16)); -} - -#if defined(SYSCFG_ITLINE0_SR_EWDG) -/** - * @brief Check if Window watchdog interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); -} -#endif /* SYSCFG_ITLINE0_SR_EWDG */ - -#if defined(SYSCFG_ITLINE1_SR_PVDOUT) -/** - * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). - * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); -} -#endif /* SYSCFG_ITLINE1_SR_PVDOUT */ - -#if defined(SYSCFG_ITLINE1_SR_VDDIO2) -/** - * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). - * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); -} -#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) -/** - * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) -/** - * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) -/** - * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ - -#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) -/** - * @brief Check if Flash interface interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)); -} -#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ - -#if defined(SYSCFG_ITLINE4_SR_CRS) -/** - * @brief Check if Clock recovery system interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); -} -#endif /* SYSCFG_ITLINE4_SR_CRS */ - -#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) -/** - * @brief Check if Reset and clock control interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)); -} -#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ - -#if defined(SYSCFG_ITLINE5_SR_EXTI0) -/** - * @brief Check if EXTI line 0 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); -} -#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ - -#if defined(SYSCFG_ITLINE5_SR_EXTI1) -/** - * @brief Check if EXTI line 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); -} -#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ - -#if defined(SYSCFG_ITLINE6_SR_EXTI2) -/** - * @brief Check if EXTI line 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); -} -#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ - -#if defined(SYSCFG_ITLINE6_SR_EXTI3) -/** - * @brief Check if EXTI line 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); -} -#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI4) -/** - * @brief Check if EXTI line 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI5) -/** - * @brief Check if EXTI line 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI6) -/** - * @brief Check if EXTI line 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI7) -/** - * @brief Check if EXTI line 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI8) -/** - * @brief Check if EXTI line 8 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI9) -/** - * @brief Check if EXTI line 9 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI10) -/** - * @brief Check if EXTI line 10 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI11) -/** - * @brief Check if EXTI line 11 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI12) -/** - * @brief Check if EXTI line 12 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI13) -/** - * @brief Check if EXTI line 13 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI14) -/** - * @brief Check if EXTI line 14 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI15) -/** - * @brief Check if EXTI line 15 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ - -#if defined(SYSCFG_ITLINE8_SR_TSC_EOA) -/** - * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA)); -} -#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ - -#if defined(SYSCFG_ITLINE8_SR_TSC_MCE) -/** - * @brief Check if Touch sensing controller max counterror interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE)); -} -#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ - -#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) -/** - * @brief Check if DMA1 channel 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)); -} -#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) -/** - * @brief Check if DMA1 channel 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) -/** - * @brief Check if DMA1 channel 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) -/** - * @brief Check if DMA2 channel 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) -/** - * @brief Check if DMA2 channel 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) -/** - * @brief Check if DMA1 channel 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) -/** - * @brief Check if DMA1 channel 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) -/** - * @brief Check if DMA1 channel 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) -/** - * @brief Check if DMA1 channel 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) -/** - * @brief Check if DMA2 channel 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) -/** - * @brief Check if DMA2 channel 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) -/** - * @brief Check if DMA2 channel 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ - -#if defined(SYSCFG_ITLINE12_SR_ADC) -/** - * @brief Check if ADC interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); -} -#endif /* SYSCFG_ITLINE12_SR_ADC */ - -#if defined(SYSCFG_ITLINE12_SR_COMP1) -/** - * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). - * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)); -} -#endif /* SYSCFG_ITLINE12_SR_COMP1 */ - -#if defined(SYSCFG_ITLINE12_SR_COMP2) -/** - * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). - * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)); -} -#endif /* SYSCFG_ITLINE12_SR_COMP2 */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) -/** - * @brief Check if Timer 1 break interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) -/** - * @brief Check if Timer 1 update interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) -/** - * @brief Check if Timer 1 trigger interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) -/** - * @brief Check if Timer 1 commutation interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ - -#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) -/** - * @brief Check if Timer 1 capture compare interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)); -} -#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ - -#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) -/** - * @brief Check if Timer 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)); -} -#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ - -#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) -/** - * @brief Check if Timer 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)); -} -#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ - -#if defined(SYSCFG_ITLINE17_SR_DAC) -/** - * @brief Check if DAC underrun interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); -} -#endif /* SYSCFG_ITLINE17_SR_DAC */ - -#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) -/** - * @brief Check if Timer 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)); -} -#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ - -#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) -/** - * @brief Check if Timer 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)); -} -#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ - -#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) -/** - * @brief Check if Timer 14 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)); -} -#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ - -#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) -/** - * @brief Check if Timer 15 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)); -} -#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ - -#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) -/** - * @brief Check if Timer 16 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)); -} -#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ - -#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) -/** - * @brief Check if Timer 17 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)); -} -#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ - -#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) -/** - * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. - * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)); -} -#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ - -#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) -/** - * @brief Check if I2C2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)); -} -#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ - -#if defined(SYSCFG_ITLINE25_SR_SPI1) -/** - * @brief Check if SPI1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); -} -#endif /* SYSCFG_ITLINE25_SR_SPI1 */ - -#if defined(SYSCFG_ITLINE26_SR_SPI2) -/** - * @brief Check if SPI2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); -} -#endif /* SYSCFG_ITLINE26_SR_SPI2 */ - -#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) -/** - * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. - * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)); -} -#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ - -#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) -/** - * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. - * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)); -} -#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) -/** - * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. - * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) -/** - * @brief Check if USART4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART5_GLB) -/** - * @brief Check if USART5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART6_GLB) -/** - * @brief Check if USART6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART7_GLB) -/** - * @brief Check if USART7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART8_GLB) -/** - * @brief Check if USART8 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ - -#if defined(SYSCFG_ITLINE30_SR_CAN) -/** - * @brief Check if CAN interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); -} -#endif /* SYSCFG_ITLINE30_SR_CAN */ - -#if defined(SYSCFG_ITLINE30_SR_CEC) -/** - * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. - * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); -} -#endif /* SYSCFG_ITLINE30_SR_CEC */ - -/** - * @brief Set connections to TIMx Break inputs - * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs - * @param Break This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) -{ -#if defined(SYSCFG_CFGR2_PVD_LOCK) - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); -#else - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -} - -/** - * @brief Get connections to TIMx Break inputs - * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ -#if defined(SYSCFG_CFGR2_PVD_LOCK) - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, - SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)); -#else - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)); -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -} - -/** - * @brief Check if SRAM parity error detected - * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) -{ - return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); -} - -/** - * @brief Clear SRAM parity error flag - * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) -{ - SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); -} - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @note For STM32F03x devices, the device ID is 0x444 - * @note For STM32F04x devices, the device ID is 0x445. - * @note For STM32F05x devices, the device ID is 0x440 - * @note For STM32F07x devices, the device ID is 0x448 - * @note For STM32F09x devices, the device ID is 0x442 - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - For example, it is read as 0x1000 for Revision 1.0. - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Freeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB2FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB2FZ, Periphs); -} -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Disable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Check if Prefetch buffer is enabled - * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); -} - - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_SYSTEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_SYSTEM_H +#define __STM32F0xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + * @{ + */ +#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap + * @{ + */ +#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) +#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */ +#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */ +#endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) +#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */ +#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */ +#endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART2_DMA_RMP) +#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */ +#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART3_DMA_RMP) +#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap + * @{ + */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ + +#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap + * @{ + */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap + * @{ + */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap + * @{ + */ +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */ +#else +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ +#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */ +#else +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ +#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) +#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */ +#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) +#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */ +#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) +#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#if defined(GPIOE_BASE) +#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ +#endif /*GPIOE_BASE*/ +#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CFGR2_PVD_LOCK) +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection + with TIM1/15/16U/17 Break Input and also + the PVDE and PLS bits of the Power Control Interface */ +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal + with Break Input of TIM1/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of + CortexM0 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ +#endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ +#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** + * @brief Set IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); +} + +/** + * @brief Get IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); +} +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for USART + * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) +/** + * @brief Set DMA request remapping bits for SPI + * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) +/** + * @brief Set DMA request remapping bits for I2C + * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** + * @brief Set DMA request remapping bits for ADC + * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for TIM + * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** + * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} + +/** + * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16)); +} + +#if defined(SYSCFG_ITLINE0_SR_EWDG) +/** + * @brief Check if Window watchdog interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); +} +#endif /* SYSCFG_ITLINE0_SR_EWDG */ + +#if defined(SYSCFG_ITLINE1_SR_PVDOUT) +/** + * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). + * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); +} +#endif /* SYSCFG_ITLINE1_SR_PVDOUT */ + +#if defined(SYSCFG_ITLINE1_SR_VDDIO2) +/** + * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). + * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); +} +#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) +/** + * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) +/** + * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) +/** + * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ + +#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) +/** + * @brief Check if Flash interface interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)); +} +#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + +#if defined(SYSCFG_ITLINE4_SR_CRS) +/** + * @brief Check if Clock recovery system interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); +} +#endif /* SYSCFG_ITLINE4_SR_CRS */ + +#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) +/** + * @brief Check if Reset and clock control interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)); +} +#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI0) +/** + * @brief Check if EXTI line 0 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI1) +/** + * @brief Check if EXTI line 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI2) +/** + * @brief Check if EXTI line 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI3) +/** + * @brief Check if EXTI line 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI4) +/** + * @brief Check if EXTI line 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI5) +/** + * @brief Check if EXTI line 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI6) +/** + * @brief Check if EXTI line 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI7) +/** + * @brief Check if EXTI line 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI8) +/** + * @brief Check if EXTI line 8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI9) +/** + * @brief Check if EXTI line 9 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI10) +/** + * @brief Check if EXTI line 10 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI11) +/** + * @brief Check if EXTI line 11 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI12) +/** + * @brief Check if EXTI line 12 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI13) +/** + * @brief Check if EXTI line 13 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI14) +/** + * @brief Check if EXTI line 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI15) +/** + * @brief Check if EXTI line 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_EOA) +/** + * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_MCE) +/** + * @brief Check if Touch sensing controller max counterror interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ + +#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +/** + * @brief Check if DMA1 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)); +} +#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +/** + * @brief Check if DMA1 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +/** + * @brief Check if DMA1 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) +/** + * @brief Check if DMA2 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) +/** + * @brief Check if DMA2 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +/** + * @brief Check if DMA1 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +/** + * @brief Check if DMA1 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +/** + * @brief Check if DMA1 channel 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +/** + * @brief Check if DMA1 channel 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) +/** + * @brief Check if DMA2 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) +/** + * @brief Check if DMA2 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) +/** + * @brief Check if DMA2 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ + +#if defined(SYSCFG_ITLINE12_SR_ADC) +/** + * @brief Check if ADC interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); +} +#endif /* SYSCFG_ITLINE12_SR_ADC */ + +#if defined(SYSCFG_ITLINE12_SR_COMP1) +/** + * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). + * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP1 */ + +#if defined(SYSCFG_ITLINE12_SR_COMP2) +/** + * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). + * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP2 */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +/** + * @brief Check if Timer 1 break interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +/** + * @brief Check if Timer 1 update interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +/** + * @brief Check if Timer 1 trigger interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +/** + * @brief Check if Timer 1 commutation interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ + +#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +/** + * @brief Check if Timer 1 capture compare interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)); +} +#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + +#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) +/** + * @brief Check if Timer 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)); +} +#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ + +#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +/** + * @brief Check if Timer 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)); +} +#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ + +#if defined(SYSCFG_ITLINE17_SR_DAC) +/** + * @brief Check if DAC underrun interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); +} +#endif /* SYSCFG_ITLINE17_SR_DAC */ + +#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) +/** + * @brief Check if Timer 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)); +} +#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ + +#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) +/** + * @brief Check if Timer 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)); +} +#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ + +#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +/** + * @brief Check if Timer 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)); +} +#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ + +#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +/** + * @brief Check if Timer 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)); +} +#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ + +#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +/** + * @brief Check if Timer 16 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)); +} +#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ + +#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +/** + * @brief Check if Timer 17 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)); +} +#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ + +#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +/** + * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. + * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)); +} +#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ + +#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +/** + * @brief Check if I2C2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)); +} +#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ + +#if defined(SYSCFG_ITLINE25_SR_SPI1) +/** + * @brief Check if SPI1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); +} +#endif /* SYSCFG_ITLINE25_SR_SPI1 */ + +#if defined(SYSCFG_ITLINE26_SR_SPI2) +/** + * @brief Check if SPI2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); +} +#endif /* SYSCFG_ITLINE26_SR_SPI2 */ + +#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +/** + * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. + * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)); +} +#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ + +#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +/** + * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)); +} +#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +/** + * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. + * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +/** + * @brief Check if USART4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART5_GLB) +/** + * @brief Check if USART5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART6_GLB) +/** + * @brief Check if USART6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART7_GLB) +/** + * @brief Check if USART7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART8_GLB) +/** + * @brief Check if USART8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ + +#if defined(SYSCFG_ITLINE30_SR_CAN) +/** + * @brief Check if CAN interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); +} +#endif /* SYSCFG_ITLINE30_SR_CAN */ + +#if defined(SYSCFG_ITLINE30_SR_CEC) +/** + * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. + * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); +} +#endif /* SYSCFG_ITLINE30_SR_CEC */ + +/** + * @brief Set connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); +#else + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Get connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, + SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Check if SRAM parity error detected + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); +} + +/** + * @brief Clear SRAM parity error flag + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F03x devices, the device ID is 0x444 + * @note For STM32F04x devices, the device ID is 0x445. + * @note For STM32F05x devices, the device ID is 0x440 + * @note For STM32F07x devices, the device ID is 0x448 + * @note For STM32F09x devices, the device ID is 0x442 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as 0x1000 for Revision 1.0. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h index a137017..ca5ed3e 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h @@ -1,287 +1,287 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_UTILS_H -#define __STM32F0xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLL_MUL - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. - This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -#else - uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. - This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); -} - - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#if defined(RCC_CFGR_SW_HSI48) -ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#endif /*RCC_CFGR_SW_HSI48*/ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_UTILS_H +#define __STM32F0xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#else + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#if defined(RCC_CFGR_SW_HSI48) +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#endif /*RCC_CFGR_SW_HSI48*/ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c index cec77d9..56e21e8 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c @@ -1,467 +1,467 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs categories: - (+) HAL Initialization and de-initialization functions - (+) HAL Control functions - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @brief STM32F0xx HAL Driver version number V1.7.1 - */ -#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32F0xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\ - |(__STM32F0xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK (0x00000FFFU) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -__IO uint32_t uwTick; -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak - to make override possible in case of other implementations in user file. - -@endverbatim - * @{ - */ - -/** - * @brief This function configures the Flash prefetch, - * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before - * the clock configuration - * @note The time base configuration is based on HSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation,Systick is used as source of time base. - * The tick variable is incremented each 1ms in its ISR. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the source - * of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB_FORCE_RESET(); - __HAL_RCC_AHB_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __Weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during Sleep mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note ThiS function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(__IO uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait++; - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) - -{ - /* Disable SysTick Interrupt */ - CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief This method returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F0xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Returns first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Returns second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Returns third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) HAL Initialization and de-initialization functions + (+) HAL Control functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F0xx HAL Driver version number V1.7.1 + */ +#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F0xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK (0x00000FFFU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +__IO uint32_t uwTick; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on HSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick++; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(__IO uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait++; + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c index 5d27d0b..fba72d3 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c @@ -1,357 +1,357 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M0 exceptions are managed by CMSIS functions. - (#) Enable and Configure the priority of the selected IRQ Channels. - The priority can be 0..3. - - -@- Lower priority values gives higher priority. - -@- Priority Order: - (#@) Lowest priority. - (#@) Lowest hardware priority (IRQn position). - - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - -@- Negative value of IRQn_Type are not allowed. - - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x03). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined - inside the stm32f0xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn External interrupt number . - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) - * @param PreemptPriority The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 3. - * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. - * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because - * no subpriority supported in Cortex M0 based products. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - NVIC_SetPriority(IRQn,PreemptPriority); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. - - -@endverbatim - * @{ - */ - - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) -{ - /* Get priority for Cortex-M system or device specific interrupts */ - return NVIC_GetPriority(IRQn); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32f0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0 based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK) functionalities. + + +@endverbatim + * @{ + */ + + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c index 5c98f40..9bd69a0 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c @@ -1,905 +1,905 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to Reference manual for connection between peripherals - and DMA requests . - - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, - using HAL_DMA_Init() function. - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - - /* Check the DMA handle allocation */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - /* Initialize DmaBaseAddress and ChannelIndex parameters used - by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - DMA_CalcBaseAndBitshift(hdma); - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - /* Check the DMA handle allocation */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0U; - - /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0U; - - /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0U; - - /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0U; - -/* Get DMA Base Address */ - DMA_CalcBaseAndBitshift(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - hdma->Instance->CCR |= DMA_CCR_EN; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete, & transfer error interrupts */ - /* Half transfer interrupt is optional: enable it only if associated callback is available */ - if(NULL != hdma->XferHalfCpltCallback ) - { - hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - } - else - { - hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); - hdma->Instance->CCR &= ~DMA_IT_HT; - } - - /* Enable the Peripheral */ - hdma->Instance->CCR |= DMA_CCR_EN; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - /* Disable DMA IT */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Disable the channel */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Abort the DMA Transfer in Interrupt mode. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - - /* Disable DMA IT */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Disable the channel */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel Specifies the DMA level complete. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0U; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) - { - if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the half transfer interrupt */ - hdma->Instance->CCR &= ~DMA_IT_HT; - } - - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - - /* DMA peripheral state is not updated in Half Transfer */ - /* State is updated only in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the transfer complete & transfer error interrupts */ - /* if the DMA mode is not CIRCULAR */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management ***************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Then, disable all DMA interrupts */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback pointer to private callback function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Set the DMA Transfer parameters. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -/** - * @brief set the DMA base address and channel index depending on DMA instance - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) -{ -#if defined (DMA2) - /* calculation of the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA2; - } -#else - /* calculation of the channel index */ - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; -#endif -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialize DmaBaseAddress and ChannelIndex parameters used + by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +/* Get DMA Base Address */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete, & transfer error interrupts */ + /* Half transfer interrupt is optional: enable it only if associated callback is available */ + if(NULL != hdma->XferHalfCpltCallback ) + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + } + else + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Abort the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + { + if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + + /* DMA peripheral state is not updated in Half Transfer */ + /* State is updated only in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete & transfer error interrupts */ + /* if the DMA mode is not CIRCULAR */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management ***************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Then, disable all DMA interrupts */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameters. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief set the DMA base address and channel index depending on DMA instance + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c index 42f3f50..514fafe 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c @@ -1,710 +1,710 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) Option Bytes programming - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F0xx devices. - - (#) FLASH Memory I/O Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase page, erase all pages - (++) Program functions: half word, word and doubleword - (#) FLASH Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Lock and Unlock the Option Bytes - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - (++) Erase Option Bytes - (++) Program the data Option Bytes - (++) Get the Write protection. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group - includes all needed functions to: - (++) Handle FLASH interrupts - (++) Wait for last FLASH operation according to its status - (++) Get error flag status - - [..] In addition to these function, this driver includes a set of macros allowing - to handle the following operations: - - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro ---------------------------- ---------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_SetErrorCode(void); -extern void FLASH_PageErase(uint32_t PageAddress); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Program halfword, word or double word at a specified address - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @note FLASH should be previously erased before new programmation (only exception to this - * is when 0x0000 is programmed) - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint8_t index = 0U; - uint8_t nbiterations = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - /* Program halfword (16-bit) at a specified address. */ - nbiterations = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /* Program word (32-bit = 2*16-bit) at a specified address. */ - nbiterations = 2U; - } - else - { - /* Program double word (64-bit = 4*16-bit) at a specified address. */ - nbiterations = 4U; - } - - for (index = 0U; index < nbiterations; index++) - { - FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programation procedure */ - if (status != HAL_OK) - { - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program halfword, word or double word at a specified address with interrupt enabled. - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - pFlash.Address = Address; - pFlash.Data = Data; - - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; - /* Program halfword (16-bit) at a specified address. */ - pFlash.DataRemaining = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; - /* Program word (32-bit : 2*16-bit) at a specified address. */ - pFlash.DataRemaining = 2U; - } - else - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; - /* Program double word (64-bit : 4*16-bit) at a specified address. */ - pFlash.DataRemaining = 4U; - } - - /* Program halfword (16-bit) at a specified address. */ - FLASH_Program_HalfWord(Address, (uint16_t)Data); - - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t addresstmp = 0U; - - /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - /* Return the faulty address */ - addresstmp = pFlash.Address; - /* Reset address */ - pFlash.Address = 0xFFFFFFFFU; - - /* Save the Error code */ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(addresstmp); - - /* Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - /* Process can continue only if no error detected */ - if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still pages to erase */ - if(pFlash.DataRemaining != 0U) - { - addresstmp = pFlash.Address; - /*Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - - /*Increment sector number*/ - addresstmp = pFlash.Address + FLASH_PAGE_SIZE; - pFlash.Address = addresstmp; - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - FLASH_PageErase(addresstmp); - } - else - { - /* No more pages to Erase, user callback can be called. */ - /* Reset Sector and stop Erase pages procedure */ - pFlash.Address = addresstmp = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - } - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /* Operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - - /* MassErase ended. Return the selected bank */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); - - /* Stop Mass Erase procedure*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - else - { - /* Nb of 16-bit data to program can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0U) - { - /* Increment address to 16-bit */ - pFlash.Address += 2; - addresstmp = pFlash.Address; - - /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16U); - - /* Operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); - } - else - { - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); - } - else - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); - } - - /* Reset Address and stop Program procedure */ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - } - } - - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Operation is completed, disable the PG, PER and MER Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - - /* Disable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which returned an error - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @note This function will reset automatically the MCU. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions - * @brief Peripheral errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode The returned value can be: - * @ref FLASH_Error_Codes - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @param Address specify the address to be programmed. - * @param Data specify the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Proceed to program the new data */ - SET_BIT(FLASH->CR, FLASH_CR_PG); - - /* Write data in the address */ - *(__IO uint16_t*)Address = Data; -} - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - uint32_t flags = 0U; - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - flags |= FLASH_FLAG_WRPERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - flags |= FLASH_FLAG_PGERR; - } - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(flags); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F0xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programmation (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0U; + uint8_t nbiterations = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + /* In case of error, stop programation procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + flags |= FLASH_FLAG_PGERR; + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c index 4ee0bc0..bb6143d 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c @@ -1,1000 +1,1000 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + Extended Initialization/de-initialization functions - * + Extended I/O operation functions - * + Extended Peripheral Control functions - * - @verbatim - ============================================================================== - ##### Flash peripheral extended features ##### - ============================================================================== - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F0xxx devices. It includes - - (++) Set/Reset the write protection - (++) Program the user Option Bytes - (++) Get the Read protection Level - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @addtogroup FLASH - * @{ - */ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants - * @{ - */ -#define FLASH_POSITION_IWDGSW_BIT 8U -#define FLASH_POSITION_OB_USERDATA0_BIT 16U -#define FLASH_POSITION_OB_USERDATA1_BIT 24U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -/* Erase operations */ -static void FLASH_MassErase(void); -void FLASH_PageErase(uint32_t PageAddress); - -/* Option bytes control */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); -static uint32_t FLASH_OB_GetWRP(void); -static uint32_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetUser(void); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions - * @brief FLASH Memory Erasing functions - * -@verbatim - ============================================================================== - ##### FLASH Erasing Programming functions ##### - ============================================================================== - - [..] The FLASH Memory Erasing functions, includes the following functions: - (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback - is called with parameter 0xFFFFFFFF - - [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - -@endverbatim - * @{ - */ - - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError pointer to variable that - * contains the configuration information on faulty page in case of error - * (0xFFFFFFFF means that all the pages have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t address = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass Erase requested for Bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Mass erase to be done*/ - FLASH_MassErase(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - } - } - else - { - /* Page Erase is requested */ - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - /* Page Erase requested on address located on bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - /* Erase page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); - address += FLASH_PAGE_SIZE) - { - FLASH_PageErase(address); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; - } - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* If procedure already ongoing, reject the next one */ - if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - FLASH_MassErase(); - } - else - { - /* Erase by page to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - pFlash.DataRemaining = pEraseInit->NbPages; - pFlash.Address = pEraseInit->PageAddress; - - /*Erase 1st page and wait for IT*/ - FLASH_PageErase(pEraseInit->PageAddress); - } - - return status; -} - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - option bytes operations. - -@endverbatim - * @{ - */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) -{ - uint8_t rdptmp = OB_RDP_LEVEL_0; - HAL_StatusTypeDef status = HAL_ERROR; - - /* Get the actual read protection Option Byte value */ - rdptmp = FLASH_OB_GetRDP(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Restore the last read protection Option Byte value */ - status = FLASH_OB_RDP_LevelConfig(rdptmp); - } - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Program option bytes - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /* Enable of Write protection on the selected page */ - status = FLASH_OB_EnableWRP(pOBInit->WRPPage); - } - else - { - /* Disable of Write protection on the selected page */ - status = FLASH_OB_DisableWRP(pOBInit->WRPPage); - } - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* USER configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* DATA configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) - { - status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; - - /*Get WRP*/ - pOBInit->WRPPage = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); -} - -/** - * @brief Get the Option byte user data - * @param DATAAdress Address of the option byte DATA - * This parameter can be one of the following values: - * @arg @ref OB_DATA_ADDRESS_DATA0 - * @arg @ref OB_DATA_ADDRESS_DATA1 - * @retval Value programmed in USER data - */ -uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) -{ - uint32_t value = 0U; - - if (DATAAdress == OB_DATA_ADDRESS_DATA0) - { - /* Get value programmed in OB USER Data0 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; - } - else - { - /* Get value programmed in OB USER Data1 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; - } - - return value; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ - -/** - * @brief Full erase of FLASH memory Bank - * - * @retval None - */ -static void FLASH_MassErase(void) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Only bank1 will be erased*/ - SET_BIT(FLASH->CR, FLASH_CR_MER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Enable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write protected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; -#if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; -#endif /* OB_WRP1_WRP1 */ -#if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; -#endif /* OB_WRP2_WRP2 */ -#if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; -#endif /* OB_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be protected ******/ - WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES48TO63MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES48TO63MASK */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - /* Enable write protection */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 &= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP0_WRP0 */ - -#if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 &= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP1_WRP1 */ - -#if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 &= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP2_WRP2 */ - -#if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 &= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Disable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write unprotected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; -#if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; -#endif /* OB_WRP1_WRP1 */ -#if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; -#endif /* OB_WRP2_WRP2 */ -#if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; -#endif /* OB_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be unprotected ******/ - WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES48TO63MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES48TO63MASK */ - - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 |= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP0_WRP0 */ - -#if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 |= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP1_WRP1 */ - -#if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 |= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP2_WRP2 */ - -#if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 |= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - return status; -} - -/** - * @brief Set the read protection level. - * @param ReadProtectLevel specifies the read protection level. - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Full chip protection - * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - - WRITE_REG(OB->RDP, ReadProtectLevel); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte. - * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), - * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). - * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); - assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); - assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); - assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); - assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); - assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); -#if defined(FLASH_OBR_BOOT_SEL) - assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); - assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); -#endif /* FLASH_OBR_BOOT_SEL */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(FLASH_OBR_BOOT_SEL) - OB->USER = UserConfig; -#else - OB->USER = (UserConfig | 0x88U); -#endif - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param Address specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data specifies the data to be programmed. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enables the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval The FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(READ_REG(FLASH->WRPR)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FLASH RDP level - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Full chip protection - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - uint32_t tmp_reg; - - /* Read RDP level bits */ - tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); - - if (tmp_reg == 0U) - { - return OB_RDP_LEVEL_0; - } - else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2) - { - return OB_RDP_LEVEL_2; - } - else - { - return OB_RDP_LEVEL_1; - } -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), - * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). - * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Erase the specified FLASH memory page - * @param PageAddress FLASH page to erase - * The value of this parameter depend on device used within the same series - * - * @retval None - */ -void FLASH_PageErase(uint32_t PageAddress) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Proceed to erase the page */ - SET_BIT(FLASH->CR, FLASH_CR_PER); - WRITE_REG(FLASH->AR, PageAddress); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F0xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT 8U +#define FLASH_POSITION_OB_USERDATA0_BIT 16U +#define FLASH_POSITION_OB_USERDATA1_BIT 24U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(void); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0U; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); +#if defined(FLASH_OBR_BOOT_SEL) + assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); + assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); +#endif /* FLASH_OBR_BOOT_SEL */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_OBR_BOOT_SEL) + OB->USER = UserConfig; +#else + OB->USER = (UserConfig | 0x88U); +#endif + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t tmp_reg; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); + + if (tmp_reg == 0U) + { + return OB_RDP_LEVEL_0; + } + else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2) + { + return OB_RDP_LEVEL_2; + } + else + { + return OB_RDP_LEVEL_1; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c index 97a64d1..2890fcc 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c @@ -1,543 +1,543 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (++) Input mode - (++) Analog mode - (++) Output mode - (++) Alternate function mode - (++) External interrupt/event lines - - (+) During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - (+) The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - (+) All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - (+) The external interrupt/event controller consists of up to 28 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also - recommended to use it to unconfigure pin which was used as an external interrupt - or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG - registers. - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PF0 and PF1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup GPIO_Private_Defines GPIO Private Defines - * @{ - */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - -#define GPIO_NUMBER (16U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t temp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - - if(iocurrent) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U)); - SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - SET_BIT(temp, GPIO_Init->Speed << (position * 2U)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U)); - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - SET_BIT(temp, iocurrent); - } - EXTI->IMR = temp; - - temp = EXTI->EMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - SET_BIT(temp, iocurrent); - } - EXTI->EMR = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->FTSR = temp; - } - } - - position++; - } -} - -/** - * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t tmp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1U << position); - - if (iocurrent) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floting Mode */ - CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U)); - - /* Configure the default Alternate Function in current IO */ - CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - - /* Configure the default value for IO Speed */ - CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - - /* Configure the default value IO Output Type */ - CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; - - /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U)); - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2U]; - tmp &= ((0x0FU) << (4U * (position & 0x03U))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) - { - tmp = (0x0FU) << (4U * (position & 0x03U)); - CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp); - - /* Clear EXTI line configuration */ - CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); - } - } - - position++; - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; - } - -/** - * @brief Set or clear the selected data port bit. - * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } -} - -/** - * @brief Toggle the specified GPIO pin. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the pin to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** -* @brief Locks GPIO Pins configuration registers. -* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, -* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. -* @note The configuration of the locked GPIO pins can no longer be modified -* until the next reset. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bits to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). -* @retval None -*/ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - SET_BIT(tmp, GPIO_Pin); - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handle EXTI interrupt request. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callback. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also + recommended to use it to unconfigure pin which was used as an external interrupt + or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG + registers. + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) + +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != RESET) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + + if(iocurrent) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U)); + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + SET_BIT(temp, GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(temp, iocurrent); + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(temp, iocurrent); + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->FTSR = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != RESET) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1U << position); + + if (iocurrent) + { + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + + /* Configure the default value for IO Speed */ + CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U)); + + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= ((0x0FU) << (4U * (position & 0x03U))); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + tmp = (0x0FU) << (4U * (position & 0x03U)); + CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; + } + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bits to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c index 1319f11..c64e0f0 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c @@ -1,4868 +1,4868 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode IO sequential operation *** - ============================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) - -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private functions to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - __IO uint32_t I2C_Trials = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - } - while (I2C_Trials < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If size > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, hi2c->ErrorCode); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** -* @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - } - - /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if ((ITFlags & I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) - { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Rx Complete callback */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Tx Complete callback */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* If state is an abort treatment on goind, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - } - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Wait until STOP Flag is reset */ - /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) + +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ + ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ + ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private functions to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private functions to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; + } + + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + __IO uint32_t I2C_Trials = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials++ == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If size > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Call the Error Callback in case of Error detected */ + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, hi2c->ErrorCode); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + } + + /* Check if STOPF is set */ + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress = 0U; + uint32_t xfermode = 0U; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection = 0U; + uint16_t slaveaddrcode = 0U; + uint16_t ownadd1code = 0U; + uint16_t ownadd2code = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if ((ITFlags & I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + { + hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Store Last receive data if any */ + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Rx Complete callback */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Tx Complete callback */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Get the CR2 register value */ + tmpreg = hi2c->Instance->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + + /* update CR2 register */ + hi2c->Instance->CR2 = tmpreg; +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c index 3e139be..6c24c54 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c @@ -1,347 +1,347 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32F0xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter and Wake Up Feature - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of I2C Wake Up Mode using the functions : - (++) HAL_I2CEx_EnableWakeUp() - (++) HAL_I2CEx_DisableWakeUp() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisableFastModePlus() - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Wake Up Feature - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#if defined(I2C_CR1_WUPEN) - -/** - * @brief Enable I2C wakeup from stop mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 |= I2C_CR1_WUPEN; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable I2C wakeup from stop mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F0xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#if defined(I2C_CR1_WUPEN) + +/** + * @brief Enable I2C wakeup from stop mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from stop mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c index cc61edf..a802483 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c @@ -1,1404 +1,1404 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pcd.c - * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_CLK_ENABLE); - - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable HCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PCD_Private_Define PCD Private Define - * @{ - */ -#define BTABLE_ADDRESS (0x000) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ - uint32_t i = 0U; - - uint32_t wInterrupt_Mask = 0U; - - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - if(hpcd->State == HAL_PCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hpcd->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Init endpoints structures */ - for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1U; - hpcd->IN_ep[i].num = i; - /* Control until ep is actvated */ - hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0U; - hpcd->IN_ep[i].xfer_buff = 0U; - hpcd->IN_ep[i].xfer_len = 0U; - } - - for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) - { - hpcd->OUT_ep[i].is_in = 0U; - hpcd->OUT_ep[i].num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0U; - hpcd->OUT_ep[i].xfer_buff = 0U; - hpcd->OUT_ep[i].xfer_len = 0U; - } - - /* Init Device */ - /*CNTR_FRES = 1*/ - hpcd->Instance->CNTR = USB_CNTR_FRES; - - /*CNTR_FRES = 0*/ - hpcd->Instance->CNTR = 0; - - /*Clear pending interrupts*/ - hpcd->Instance->ISTR = 0; - - /*Set Btable Adress*/ - hpcd->Instance->BTABLE = BTABLE_ADDRESS; - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - hpcd->USB_Address = 0U; - hpcd->State= HAL_PCD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - HAL_PCD_Stop(hpcd); - - /* DeInit the low level hardware */ - HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - hpcd->Instance->BCDR |= USB_BCDR_DPPU; - - return HAL_OK; -} - -/** - * @brief Stop the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* disable all interrupts and force USB reset */ - hpcd->Instance->CNTR = USB_CNTR_FRES; - - /* clear interrupt status register */ - hpcd->Instance->ISTR = 0; - - /* switch-off device */ - hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief This function handles PCD interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0U; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0U); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { - - hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE)); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - HAL_PCD_SOFCallback(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - } -} - -/** - * @brief Data out stage callbacks - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callbacks - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callbacks - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callbacks - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callbacks - * @param hpcd PCD handle - * @retval None - */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - hpcd->Instance->BCDR |= USB_BCDR_DPPU; - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Disconnect the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* Disable DP Pull-Down bit*/ - hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address - * @param hpcd PCD handle - * @param address new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - - if(address == 0U) - { - /* set device address and enable function */ - hpcd->Instance->DADDR = USB_DADDR_EF; - } - else /* USB Address will be applied later */ - { - hpcd->USB_Address = address; - } - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -/** - * @brief Open and configure an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param ep_mps endpoint max packert size - * @param ep_type endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; - } - ep->num = ep_addr & 0x7FU; - - ep->is_in = (0x80U & ep_addr) != 0U; - ep->maxpacket = ep_mps; - ep->type = ep_type; - - __HAL_LOCK(hpcd); - - /* initialize Endpoint */ - switch (ep->type) - { - case PCD_EP_TYPE_CTRL: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); - break; - case PCD_EP_TYPE_BULK: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); - break; - case PCD_EP_TYPE_INTR: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); - break; - case PCD_EP_TYPE_ISOC: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); - break; - default: - break; - } - - PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); - - if (ep->doublebuffer == 0U) - { - if (ep->is_in) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) - } - else - { - /*Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket) - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - } - } - /*Double Buffer*/ - else - { - /*Set the endpoint as double buffered*/ - PCD_SET_EP_DBUF(hpcd->Instance, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1) - - if (ep->is_in==0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(hpcd->Instance, ep->num); - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - PCD_RX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) - } - } - - __HAL_UNLOCK(hpcd); - return ret; -} - - -/** - * @brief Deactivate an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; - } - ep->num = ep_addr & 0x7FU; - - ep->is_in = (0x80U & ep_addr) != 0U; - - __HAL_LOCK(hpcd); - - if (ep->doublebuffer == 0U) - { - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) - } - else - { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) - } - } - /*Double Buffer*/ - else - { - if (ep->is_in==0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(hpcd->Instance, ep->num); - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - PCD_RX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) - } - } - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the reception buffer - * @param len amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - - PCD_EPTypeDef *ep; - - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0U; - ep->is_in = 0U; - ep->num = ep_addr & 0x7FU; - - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0U; - } - - /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) - { - /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len) - } - else - { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len) - } - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - - return HAL_OK; -} - -/** - * @brief Get Received Data Size - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval Data Size - */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count; -} -/** - * @brief Send an amount of data - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the transmission buffer - * @param len amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - uint16_t pmabuffer = 0U; - - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0U; - ep->is_in = 1U; - ep->num = ep_addr & 0x7FU; - - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0U; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0U) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); - PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); - } - else - { - /*Write the data to the USB endpoint*/ - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) - { - /*Set the Double buffer counter for pmabuffer1*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) - pmabuffer = ep->pmaaddr1; - } - else - { - /*Set the Double buffer counter for pmabuffer0*/ - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len) - pmabuffer = ep->pmaaddr0; - } - - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) - } - - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - __HAL_LOCK(hpcd); - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7FU; - ep->is_in = ((ep_addr & 0x80U) == 0x80U); - - if (ep->num == 0U) - { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) - } - else - { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL) - } - else - { - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL) - } - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0U; - ep->num = ep_addr & 0x7FU; - ep->is_in = ((ep_addr & 0x80U) == 0x80U); - - __HAL_LOCK(hpcd); - - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) - } - else - { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return HAL_OK; -} - -/** - * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling -* @param hpcd PCD handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - if (hpcd->Init.lpm_enable ==1) - { - /* Apply L1 Resume */ - hpcd->Instance->CNTR |= USB_CNTR_L1RESUME; - } - else - { - /* Apply L2 Resume */ - hpcd->Instance->CNTR |= USB_CNTR_RESUME; - } - - return (HAL_OK); -} - -/** -* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling -* @param hpcd PCD handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - if (hpcd->Init.lpm_enable ==1) - { - /* Release L1 Resume */ - hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_L1RESUME)); - } - else - { - /* Release L2 Resume */ - hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_RESUME)) ; - } - - return (HAL_OK); -} -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD state - * @param hpcd PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup PCD_Private_Functions - * @{ - */ -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; - uint32_t i; - uint16_t temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); - - for (i = n; i != 0; i--) - { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ; - *pdwVal++ = temp2; - pbUsrBuf++; - } -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf = pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (uint32_t)wNBytes >> 1U; - uint32_t i; - uint16_t *pdwVal; - uint32_t temp; - pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); - - for (i = n; i != 0U; i--) - { - temp = *pdwVal++; - *pbUsrBuf++ = ((temp >> 0) & 0xFF); - *pbUsrBuf++ = ((temp >> 8) & 0xFF); - } - - if (wNBytes % 2) - { - temp = *pdwVal++; - *pbUsrBuf++ = ((temp >> 0) & 0xFF); - } -} - -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep; - uint16_t count=0U; - uint8_t EPindex; - __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0U; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) - { - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (EPindex == 0U) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0U) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0U); - - - if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0U; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0U) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0U) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0U) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0U); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket) - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID) - } - } - } - else - { - - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0U) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); - ep = &hpcd->OUT_ep[EPindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0U) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0U) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0U) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0U) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT) - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0U) - { - ep = &hpcd->IN_ep[EPindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0U) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0U) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0U) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } - } - } - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE); + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable HCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PCD_Private_Define PCD Private Define + * @{ + */ +#define BTABLE_ADDRESS (0x000) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and create the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + uint32_t i = 0U; + + uint32_t wInterrupt_Mask = 0U; + + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + /* Control until ep is actvated */ + hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + /*CNTR_FRES = 1*/ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /*CNTR_FRES = 0*/ + hpcd->Instance->CNTR = 0; + + /*Clear pending interrupts*/ + hpcd->Instance->ISTR = 0; + + /*Set Btable Adress*/ + hpcd->Instance->BTABLE = BTABLE_ADDRESS; + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + hpcd->USB_Address = 0U; + hpcd->State= HAL_PCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + HAL_PCD_Stop(hpcd); + + /* DeInit the low level hardware */ + HAL_PCD_MspDeInit(hpcd); + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* disable all interrupts and force USB reset */ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /* clear interrupt status register */ + hpcd->Instance->ISTR = 0; + + /* switch-off device */ + hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wInterrupt_Mask = 0U; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + HAL_PCD_ResetCallback(hpcd); + HAL_PCD_SetAddress(hpcd, 0U); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + { + + hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE)); + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + HAL_PCD_ResumeCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) + { + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + { + HAL_PCD_SuspendCallback(hpcd); + } + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + HAL_PCD_SOFCallback(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} + +/** + * @brief Data out stage callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Disable DP Pull-Down bit*/ + hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + + if(address == 0U) + { + /* set device address and enable function */ + hpcd->Instance->DADDR = USB_DADDR_EF; + } + else /* USB Address will be applied later */ + { + hpcd->USB_Address = address; + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packert size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + } + ep->num = ep_addr & 0x7FU; + + ep->is_in = (0x80U & ep_addr) != 0U; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + __HAL_LOCK(hpcd); + + /* initialize Endpoint */ + switch (ep->type) + { + case PCD_EP_TYPE_CTRL: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); + break; + case PCD_EP_TYPE_BULK: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); + break; + case PCD_EP_TYPE_INTR: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); + break; + case PCD_EP_TYPE_ISOC: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); + break; + default: + break; + } + + PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + /* Configure NAK status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket) + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + } + } + /*Double Buffer*/ + else + { + /*Set the endpoint as double buffered*/ + PCD_SET_EP_DBUF(hpcd->Instance, ep->num); + /*Set buffer address for double buffered mode*/ + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1) + + if (ep->is_in==0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + + __HAL_UNLOCK(hpcd); + return ret; +} + + +/** + * @brief Deactivate an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + } + ep->num = ep_addr & 0x7FU; + + ep->is_in = (0x80U & ep_addr) != 0U; + + __HAL_LOCK(hpcd); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + /*Double Buffer*/ + else + { + if (ep->is_in==0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0x7FU; + + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0U; + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0) + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len) + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len) + } + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + uint16_t pmabuffer = 0U; + + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0x7FU; + + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0U; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); + PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Write the data to the USB endpoint*/ + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) + { + /*Set the Double buffer counter for pmabuffer1*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) + pmabuffer = ep->pmaaddr1; + } + else + { + /*Set the Double buffer counter for pmabuffer0*/ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len) + pmabuffer = ep->pmaaddr0; + } + + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) + } + + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + __HAL_LOCK(hpcd); + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 1; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); + + if (ep->num == 0U) + { + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) + } + else + { + if (ep->is_in) + { + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL) + } + else + { + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL) + } + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 0U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); + + __HAL_LOCK(hpcd); + + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return HAL_OK; +} + +/** + * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling +* @param hpcd PCD handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + if (hpcd->Init.lpm_enable ==1) + { + /* Apply L1 Resume */ + hpcd->Instance->CNTR |= USB_CNTR_L1RESUME; + } + else + { + /* Apply L2 Resume */ + hpcd->Instance->CNTR |= USB_CNTR_RESUME; + } + + return (HAL_OK); +} + +/** +* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling +* @param hpcd PCD handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + if (hpcd->Init.lpm_enable ==1) + { + /* Release L1 Resume */ + hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_L1RESUME)); + } + else + { + /* Release L2 Resume */ + hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_RESUME)) ; + } + + return (HAL_OK); +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD state + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PCD_Private_Functions + * @{ + */ +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; + uint32_t i; + uint16_t temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ; + *pdwVal++ = temp2; + pbUsrBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf = pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1U; + uint32_t i; + uint16_t *pdwVal; + uint32_t temp; + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + + for (i = n; i != 0U; i--) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + *pbUsrBuf++ = ((temp >> 8) & 0xFF); + } + + if (wNBytes % 2) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + } +} + +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count=0U; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0U; + + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0U); + + + if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0U); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket) + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID) + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0U) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT) + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0U) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0U) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c index 77207fa..b00d2f8 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c @@ -1,154 +1,154 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pcd_ex.c - * @author MCD Application Team - * @brief Extended PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Configuration of the PMA for EP - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update PMA configuration - -@endverbatim - * @{ - */ - -/** - * @brief Configure PMA for EP - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param ep_kind endpoint Kind - * @arg USB_SNG_BUF: Single Buffer used - * @arg USB_DBL_BUF: Double Buffer used - * @param pmaadress EP address in The PMA: In case of single buffer endpoint - * this parameter is 16-bit value providing the address - * in PMA allocated to endpoint. - * In case of double buffer endpoint this parameter - * is a 32-bit value providing the endpoint buffer 0 address - * in the LSB part of 32-bit value and endpoint buffer 1 address - * in the MSB part of 32-bit value. - * @retval : status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) - -{ - PCD_EPTypeDef *ep; - - /* initialize ep structure*/ - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - { - /*Single Buffer*/ - ep->doublebuffer = 0U; - /*Configure the PMA*/ - ep->pmaadress = (uint16_t)pmaadress; - } - else /*USB_DBL_BUF*/ - { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1U; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFFU; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; - } - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief Extended PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Configuration of the PMA for EP + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update PMA configuration + +@endverbatim + * @{ + */ + +/** + * @brief Configure PMA for EP + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * @arg USB_SNG_BUF: Single Buffer used + * @arg USB_DBL_BUF: Double Buffer used + * @param pmaadress EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval : status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) + +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /*Single Buffer*/ + ep->doublebuffer = 0U; + /*Configure the PMA*/ + ep->pmaadress = (uint16_t)pmaadress; + } + else /*USB_DBL_BUF*/ + { + /*Double Buffer Endpoint*/ + ep->doublebuffer = 1U; + /*Configure the PMA*/ + ep->pmaaddr0 = pmaadress & 0xFFFFU; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; + } + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c index 98e94da..4eef3d0 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c @@ -1,470 +1,470 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization function - * + Peripheral Control function - * - @verbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers when present). - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - PWR->CR |= (uint32_t)PWR_CR_DBP; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers when present). - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - PWR->CR &= ~((uint32_t)PWR_CR_DBP); -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. - (++)WakeUp Pin 1 on PA.00. - (++)WakeUp Pin 2 on PC.13. - (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) - (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) - (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) - (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) - (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) - (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction - (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, - when programmed in wakeup mode (the peripheral must be - programmed in wakeup mode and the corresponding interrupt vector - must be enabled in the NVIC) - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. - The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers and Standby circuitry. - The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - - (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: - (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) - to be sensitive to to the selected edges (falling, rising or falling - and rising) (Interrupt or Event modes) using the EXTI_Init() function. - (+++) Configure the comparator to generate the event. -@endverbatim - * @{ - */ - -/** - * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. - * This parameter can be value of : - * @ref PWREx_WakeUp_Pins - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Enable the EWUPx pin */ - SET_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. - * This parameter can be values of : - * @ref PWREx_WakeUp_Pins - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Disable the EWUPx pin */ - CLEAR_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator Specifies the regulator state in SLEEP mode. - * On STM32F0 devices, this parameter is a dummy value and it is ignored - * as regulator can't be modified in this mode. Parameter is kept for platform - * compatibility. - * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator Specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON - * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - - /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); - - /* Set LPDS bit according to Regulator value */ - tmpreg |= Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC alternate function pins if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - WKUP pins if enabled. - * STM32F0x8 devices, the Stop mode is available, but it is - * aningless to distinguish between voltage regulator in Low power - * mode and voltage regulator in Run mode because the regulator - * not used and the core is supplied directly from an external source. - * Consequently, the Standby mode is not available on those devices. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= (uint32_t)PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - - -/** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization function + * + Peripheral Control function + * + @verbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + PWR->CR |= (uint32_t)PWR_CR_DBP; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. + (++)WakeUp Pin 1 on PA.00. + (++)WakeUp Pin 2 on PC.13. + (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) + (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) + (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) + (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + when programmed in wakeup mode (the peripheral must be + programmed in wakeup mode and the corresponding interrupt vector + must be enabled in the NVIC) + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. + The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers and Standby circuitry. + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. +@endverbatim + * @{ + */ + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be value of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be values of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator Specifies the regulator state in SLEEP mode. + * On STM32F0 devices, this parameter is a dummy value and it is ignored + * as regulator can't be modified in this mode. Parameter is kept for platform + * compatibility. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC alternate function pins if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pins if enabled. + * STM32F0x8 devices, the Stop mode is available, but it is + * aningless to distinguish between voltage regulator in Low power + * mode and voltage regulator in Run mode because the regulator + * not used and the core is supplied directly from an external source. + * Consequently, the Standby mode is not available on those devices. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= (uint32_t)PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c index 25174c6..d83817d 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c @@ -1,290 +1,290 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWREx HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup PWREx_Private_Constants PWREx Private Constants - * @{ - */ -#define PVD_MODE_IT (0x00010000U) -#define PVD_MODE_EVT (0x00020000U) -#define PVD_RISING_EDGE (0x00000001U) -#define PVD_FALLING_EDGE (0x00000002U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions - * @brief Extended Peripheral Control functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. - (+) The PVD is stopped in Standby mode. - -@- PVD is not available on STM32F030x4/x6/x8 - - *** VDDIO2 Monitor Configuration *** - ==================================== - [..] - (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it - to VREFInt Voltage - (+) This monitor is internally connected to the EXTI line31 - and can generate an interrupt if enabled. This is done through - HAL_PWREx_EnableVddio2Monitor() function. - -@- VDDIO2 is available on STM32F07x/09x/04x - -@endverbatim - * @{ - */ - -#if defined (STM32F031x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F091xC) || \ - defined (STM32F042x6) || defined (STM32F072xB) -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - PWR->CR |= (uint32_t)PWR_CR_PVDE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - PWR->CR &= ~((uint32_t)PWR_CR_PVDE); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F091xC) || */ - /* defined (STM32F042x6) || defined (STM32F072xB) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -/** - * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. - * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, - an interrupt is generated Irq line 1. - NVIS has to be enable by user. - * @retval None - */ -void HAL_PWREx_EnableVddio2Monitor(void) -{ - __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); -} - -/** - * @brief Disable the Vddio2 Monitor. - * @retval None - */ -void HAL_PWREx_DisableVddio2Monitor(void) -{ - __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); - -} - -/** - * @brief This function handles the PWR Vddio2 monitor interrupt request. - * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). - * @retval None - */ -void HAL_PWREx_Vddio2Monitor_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) - { - /* PWR Vddio2 monitor interrupt user callback */ - HAL_PWREx_Vddio2MonitorCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR Vddio2 Monitor interrupt callback - * @retval None - */ -__weak void HAL_PWREx_Vddio2MonitorCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file - */ -} - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWREx HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @brief Extended Peripheral Control functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. + (+) The PVD is stopped in Standby mode. + -@- PVD is not available on STM32F030x4/x6/x8 + + *** VDDIO2 Monitor Configuration *** + ==================================== + [..] + (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it + to VREFInt Voltage + (+) This monitor is internally connected to the EXTI line31 + and can generate an interrupt if enabled. This is done through + HAL_PWREx_EnableVddio2Monitor() function. + -@- VDDIO2 is available on STM32F07x/09x/04x + +@endverbatim + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F091xC) || \ + defined (STM32F042x6) || defined (STM32F072xB) +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + PWR->CR |= (uint32_t)PWR_CR_PVDE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_PVDE); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F091xC) || */ + /* defined (STM32F042x6) || defined (STM32F072xB) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. + * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, + an interrupt is generated Irq line 1. + NVIS has to be enable by user. + * @retval None + */ +void HAL_PWREx_EnableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); +} + +/** + * @brief Disable the Vddio2 Monitor. + * @retval None + */ +void HAL_PWREx_DisableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); + +} + +/** + * @brief This function handles the PWR Vddio2 monitor interrupt request. + * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWREx_Vddio2Monitor_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) + { + /* PWR Vddio2 monitor interrupt user callback */ + HAL_PWREx_Vddio2MonitorCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR Vddio2 Monitor interrupt callback + * @retval None + */ +__weak void HAL_PWREx_Vddio2MonitorCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c index 1293139..619a481 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c @@ -1,1332 +1,1332 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, - and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; - all peripherals mapped on these buses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB buses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC -* @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, - AHB and APB1). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - The HSI clock can be used also to clock the USART and I2C peripherals. - - (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock - the ADC peripheral. - - (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: - (++) The first output is used to generate the high speed system clock (up to 48 MHz) - (++) The second output is used to generate the clock for the USB FS (48 MHz) - (++) The third output may be used to generate the clock for the TIM, I2C and USART - peripherals (up to 48 MHz) - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M0 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL - clock (divided by 2) output on pin (such as PA8 pin). - - [..] System, AHB and APB buses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: - (++) The FLASH program/erase clock which is always HSI 8MHz clock. - (++) The USB 48 MHz clock which is derived from the PLL VCO clock. - (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. - (++) The I2C clock which can be derived as well from HSI 8MHz clock. - (++) The ADC clock which is derived from PLL output. - (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC - (HSE divided by a programmable prescaler). The System clock (SYSCLK) - frequency must be higher or equal to the RTC clock frequency. - (++) IWDG clock which is always the LSI clock. - - (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. - - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - @endverbatim - * @{ - */ - -/* - Additional consideration on the SYSCLK based on Latency settings: - +-----------------------------------------------+ - | Latency | SYSCLK clock frequency (MHz) | - |---------------|-------------------------------| - |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - |---------------|-------------------------------| - |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - +-----------------------------------------------+ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB, APB1 prescaler set to 1. - * - CSS and MCO1 OFF - * - All interrupts disabled - * @note This function does not modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); - - /* Reset HSEON, CSSON, PLLON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset CFGR2 register */ - CLEAR_REG(RCC->CFGR2); - - /* Reset CFGR3 register */ - CLEAR_REG(RCC->CFGR3); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*----------------------------- HSI14 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); - - /* Check the HSI14 State */ - if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) - { - /* Enable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_ENABLE(); - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - -#if defined(RCC_HSI48_SUPPORT) - /*----------------------------- HSI48 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - - /* When the HSI48 is used as system clock it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) - { - return HAL_ERROR; - } - } - else - { - /* Check the HSI48 State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } -#endif /* RCC_HSI48_SUPPORT */ - - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, predivider and multiplication factor. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PREDIV, - RCC_OscInitStruct->PLL.PLLMUL); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * start-up from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(RCC_CFGR_SWS_HSI48) - /* HSI48 is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - /* Check the HSI48 ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - return HAL_ERROR; - } - } -#endif /* RCC_CFGR_SWS_HSI48 */ - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#if defined(RCC_CFGR_SWS_HSI48) - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#endif /* RCC_CFGR_SWS_HSI48 */ - else - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - - @endverbatim - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - @if STM32F042x6 - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F048xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F071xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F072xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F078xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F091xC - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F098xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F030x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F030xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F031x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F038xx - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F070x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F070xB - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock - * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock - * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock - * @retval None - */ -#else -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @retval None - */ -#endif -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio; - - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* Configure the MCO1 pin in alternate function mode */ - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_FREQ_HIGH; - gpio.Pull = GPIO_NOPULL; - gpio.Pin = MCO1_PIN; - gpio.Alternate = GPIO_AF0_MCO; - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - - /* Configure the MCO clock source */ - __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) - * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based - * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the - * PLL factor. - * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, - 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; - const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, - 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; - - uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - uint32_t sysclockfreq = 0U; - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ - { - pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; - if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ - pllclk = (HSE_VALUE / prediv) * pllmul; - } -#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) - else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) - { - /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ - pllclk = (HSI48_VALUE / prediv) * pllmul; - } -#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ - else - { -#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) - /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ - pllclk = (HSI_VALUE / prediv) * pllmul; -#else - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul); -#endif - } - sysclockfreq = pllclk; - break; - } -#if defined(RCC_CFGR_SWS_HSI48) - case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ - { - sysclockfreq = HSI48_VALUE; - break; - } -#endif /* RCC_CFGR_SWS_HSI48 */ - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - default: /* HSI used as system clock */ - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; -#if defined(RCC_HSI48_SUPPORT) - RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; -#endif /* RCC_HSI48_SUPPORT */ - - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the HSI14 configuration -----------------------------------------------*/ - if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) - { - RCC_OscInitStruct->HSI14State = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); - -#if defined(RCC_HSI48_SUPPORT) - /* Get the HSI48 configuration if any-----------------------------------------*/ - RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); - RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * contains the current clock configuration. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, + AHB and APB1). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + The HSI clock can be used also to clock the USART and I2C peripherals. + + (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock + the ADC peripheral. + + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 48 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the TIM, I2C and USART + peripherals (up to 48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. + + (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + + /* Reset CFGR3 register */ + CLEAR_REG(RCC->CFGR3); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(RCC_HSI48_SUPPORT) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Check the HSI48 State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } +#endif /* RCC_HSI48_SUPPORT */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(RCC_CFGR_SWS_HSI48) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* RCC_CFGR_SWS_HSI48 */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(RCC_CFGR_SWS_HSI48) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* RCC_CFGR_SWS_HSI48 */ + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @retval None + */ +#else +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +#endif +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based + * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the + * PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE / prediv) * pllmul; + } +#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (HSI48_VALUE / prediv) * pllmul; + } +#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ + else + { +#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (HSI_VALUE / prediv) * pllmul; +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul); +#endif + } + sysclockfreq = pllclk; + break; + } +#if defined(RCC_CFGR_SWS_HSI48) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + { + sysclockfreq = HSI48_VALUE; + break; + } +#endif /* RCC_CFGR_SWS_HSI48 */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif /* RCC_HSI48_SUPPORT */ + + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI14 configuration -----------------------------------------------*/ + if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) + { + RCC_OscInitStruct->HSI14State = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration if any-----------------------------------------*/ + RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c index d1d1137..a5699bf 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c @@ -1,980 +1,980 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * + Extended Clock Recovery System Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/** @defgroup RCCEx RCCEx - * @brief RCC Extension HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#if defined(CRS) -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -/* Bit position in register */ -#define CRS_CFGR_FELIM_BITNUMBER 16 -#define CRS_CR_TRIM_BITNUMBER 8 -#define CRS_ISR_FECAP_BITNUMBER 16 -/** - * @} - */ -#endif /* CRS */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks - * (USART, RTC, I2C, CEC and USB). - * - * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t temp_reg = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*---------------------------- RTC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - FlagStatus pwrclkchanged = RESET; - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = temp_reg; - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*------------------------------- USART1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - /*----------------------------- USART2 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - /*----------------------------- USART3 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } -#endif /* STM32F091xC || STM32F098xx */ - - /*------------------------------ I2C1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) - /*------------------------------ USB Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - { - /* Check the parameters */ - assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); - - /* Configure the USB clock source */ - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - /*------------------------------ CEC clock Configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - { - /* Check the parameters */ - assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - - /* Configure the CEC clock source */ - __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - } -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - - return HAL_OK; -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals clocks - * (USART, RTC, I2C, CEC and USB). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - /* Set all possible values for the extended clock type parameter------------*/ - /* Common part first */ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; - /* Get the RTC configuration --------------------------------------------*/ - PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); - /* Get the USART1 clock configuration --------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - /* Get the I2C1 clock source -----------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; - /* Get the USART2 clock source ---------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; - /* Get the USART3 clock source ---------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; - /* Get the USB clock source ---------------------------------------------*/ - PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; - /* Get the CEC clock source ------------------------------------------------*/ - PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -} - -/** - * @brief Returns the peripheral clock frequency - * @note Returns 0 if peripheral clock is unknown - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - @if STM32F042x6 - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F048xx - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F051x8 - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F058xx - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F070x6 - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F070xB - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F071xB - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F072xB - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F078xx - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F091xC - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F098xx - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - * @retval Frequency in Hz (0: means that no available frequency for the peripheral) - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* frequency == 0 : means that no available frequency for the peripheral */ - uint32_t frequency = 0U; - - uint32_t srcclk = 0U; -#if defined(USB) - uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; -#endif /* USB */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - switch (PeriphClk) - { - case RCC_PERIPHCLK_RTC: - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - break; - } - case RCC_PERIPHCLK_USART1: - { - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - /* Check if USART1 clock selection is PCLK1 */ - if (srcclk == RCC_USART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART1 clock selection is HSI */ - else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART1 clock selection is SYSCLK */ - else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART1 clock selection is LSE */ - else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#if defined(RCC_CFGR3_USART2SW) - case RCC_PERIPHCLK_USART2: - { - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - /* Check if USART2 clock selection is PCLK1 */ - if (srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART2 clock selection is HSI */ - else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART2 clock selection is SYSCLK */ - else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART2 clock selection is LSE */ - else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) - case RCC_PERIPHCLK_USART3: - { - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - /* Check if USART3 clock selection is PCLK1 */ - if (srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART3 clock selection is HSI */ - else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART3 clock selection is SYSCLK */ - else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART3 clock selection is LSE */ - else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* RCC_CFGR3_USART3SW */ - case RCC_PERIPHCLK_I2C1: - { - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Check if HSI is ready and if I2C1 clock selection is HSI */ - if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if I2C1 clock selection is SYSCLK */ - else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - break; - } -#if defined(USB) - case RCC_PERIPHCLK_USB: - { - /* Get the current USB source */ - srcclk = __HAL_RCC_GET_USB_SOURCE(); - - /* Check if PLL is ready and if USB clock selection is PLL */ - if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) - { - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ - frequency = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(RCC_CR2_HSI48ON) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ - frequency = (HSI48_VALUE / predivfactor) * pllmull; - } -#endif /* RCC_CR2_HSI48ON */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) - /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ - frequency = (HSI_VALUE / predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ - frequency = (HSI_VALUE >> 1U) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ - } - } -#if defined(RCC_CR2_HSI48ON) - /* Check if HSI48 is ready and if USB clock selection is HSI48 */ - else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) - { - frequency = HSI48_VALUE; - } -#endif /* RCC_CR2_HSI48ON */ - break; - } -#endif /* USB */ -#if defined(CEC) - case RCC_PERIPHCLK_CEC: - { - /* Get the current CEC source */ - srcclk = __HAL_RCC_GET_CEC_SOURCE(); - - /* Check if HSI is ready and if CEC clock selection is HSI */ - if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if LSE is ready and if CEC clock selection is LSE */ - else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* CEC */ - default: - { - break; - } - } - return(frequency); -} - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * -@verbatim - =============================================================================== - ##### Extended Clock Recovery System Control functions ##### - =============================================================================== - [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: - - (#) In System clock config, HSI48 needs to be enabled - - (#) Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions as follows: - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and synchronization frequencies values - (##) Call function @ref HAL_RCCEx_CRSConfig which - (+++) Reset CRS registers to their default values. - (+++) Configure CRS registers with synchronization configuration - (+++) Enable automatic calibration and frequency error counter feature - Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the - periodic USB SOF will not be generated by the host. No SYNC signal will therefore be - provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock - precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs - should be used as SYNC signal. - - (##) A polling function is provided to wait for complete synchronization - (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - @ref HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go - through CRS Handler (RCC_IRQn/RCC_IRQHandler) - (++) Call function @ref HAL_RCCEx_CRSConfig() - (++) Enable RCC_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from - HAL_RCCEx_CRS_IRQHandler(): - (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() - (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() - (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) @ref HAL_RCCEx_CRS_ErrorCallback() - - (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) - -@endverbatim - * @{ - */ - -/** - * @brief Start automatic synchronization for polling mode - * @param pInit Pointer on RCC_CRSInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) -{ - uint32_t value = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); - assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); - assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); - assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); - assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); - assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - - /* CONFIGURATION */ - - /* Before configuration, reset CRS registers to their default values*/ - __HAL_RCC_CRS_FORCE_RESET(); - __HAL_RCC_CRS_RELEASE_RESET(); - - /* Set the SYNCDIV[2:0] bits according to Prescaler value */ - /* Set the SYNCSRC[1:0] bits according to Source value */ - /* Set the SYNCSPOL bit according to Polarity value */ - value = (pInit->Prescaler | pInit->Source | pInit->Polarity); - /* Set the RELOAD[15:0] bits according to ReloadValue value */ - value |= pInit->ReloadValue; - /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); - WRITE_REG(CRS->CFGR, value); - - /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); - - /* START AUTOMATIC SYNCHRONIZATION*/ - - /* Enable Automatic trimming & Frequency error counter */ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); -} - -/** - * @brief Generate the software synchronization event - * @retval None - */ -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Return synchronization info - * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) -{ - /* Check the parameter */ - assert_param(pSynchroInfo != NULL); - - /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - - /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); - - /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); - - /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** -* @brief Wait for CRS Synchronization status. -* @param Timeout Duration of the timeout -* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization -* frequency. -* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. -* @retval Combination of Synchronization status -* This parameter can be a combination of the following values: -* @arg @ref RCC_CRS_TIMEOUT -* @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARN -* @arg @ref RCC_CRS_SYNCERR -* @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOVF -*/ -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) -{ - uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for CRS flag or timeout detection */ - do - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - crsstatus = RCC_CRS_TIMEOUT; - } - } - /* Check CRS SYNCOK flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) - { - /* CRS SYNC event OK */ - crsstatus |= RCC_CRS_SYNCOK; - - /* Clear CRS SYNC event OK bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); - } - - /* Check CRS SYNCWARN flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) - { - /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARN; - - /* Clear CRS SYNCWARN bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); - } - - /* Check CRS TRIM overflow flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOVF; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); - } - - /* Check CRS Error flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_SYNCERR; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); - } - - /* Check CRS SYNC Missed flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) - { - /* CRS SYNC Missed */ - crsstatus |= RCC_CRS_SYNCMISS; - - /* Clear CRS SYNC Missed bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); - } - - /* Check CRS Expected SYNC flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) - { - /* frequency error counter reached a zero value */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); - } - } while(RCC_CRS_NONE == crsstatus); - - return crsstatus; -} - -/** - * @brief Handle the Clock Recovery System interrupt request. - * @retval None - */ -void HAL_RCCEx_CRS_IRQHandler(void) -{ - uint32_t crserror = RCC_CRS_NONE; - /* Get current IT flags and IT sources values */ - uint32_t itflags = READ_REG(CRS->ISR); - uint32_t itsources = READ_REG(CRS->CR); - - /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) - { - /* Clear CRS SYNC event OK flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); - - /* user callback */ - HAL_RCCEx_CRS_SyncOkCallback(); - } - /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) - { - /* Clear CRS SYNCWARN flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); - - /* user callback */ - HAL_RCCEx_CRS_SyncWarnCallback(); - } - /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) - { - /* frequency error counter reached a zero value */ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); - - /* user callback */ - HAL_RCCEx_CRS_ExpectedSyncCallback(); - } - /* Check CRS Error flags */ - else - { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) - { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) - { - crserror |= RCC_CRS_SYNCERR; - } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) - { - crserror |= RCC_CRS_SYNCMISS; - } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) - { - crserror |= RCC_CRS_TRIMOVF; - } - - /* Clear CRS Error flags */ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - - /* user error callback */ - HAL_RCCEx_CRS_ErrorCallback(crserror); - } - } -} - -/** - * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncOkCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - * @retval none - */ -__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Error); - - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(CRS) +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/* Bit position in register */ +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t temp_reg = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART3 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* STM32F091xC || STM32F098xx */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + /* Common part first */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + /* Get the RTC configuration --------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USART1 clock configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + /* Get the USB clock source ---------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + @if STM32F042x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F048xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F051x8 + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F058xx + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F070x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F070xB + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F071xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F072xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F078xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F091xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F098xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* frequency == 0 : means that no available frequency for the peripheral */ + uint32_t frequency = 0U; + + uint32_t srcclk = 0U; +#if defined(USB) + uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; +#endif /* USB */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 32U; + } + break; + } + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + /* Check if USART1 clock selection is PCLK1 */ + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART1 clock selection is HSI */ + else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART1 clock selection is SYSCLK */ + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART1 clock selection is LSE */ + else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#if defined(RCC_CFGR3_USART2SW) + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + /* Check if USART2 clock selection is PCLK1 */ + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART2 clock selection is HSI */ + else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART2 clock selection is SYSCLK */ + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART2 clock selection is LSE */ + else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + case RCC_PERIPHCLK_USART3: + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + /* Check if USART3 clock selection is PCLK1 */ + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART3 clock selection is HSI */ + else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART3 clock selection is SYSCLK */ + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART3 clock selection is LSE */ + else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART3SW */ + case RCC_PERIPHCLK_I2C1: + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Check if HSI is ready and if I2C1 clock selection is HSI */ + if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C1 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#if defined(USB) + case RCC_PERIPHCLK_USB: + { + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + /* Check if PLL is ready and if USB clock selection is PLL */ + if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ + frequency = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(RCC_CR2_HSI48ON) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ + frequency = (HSI48_VALUE / predivfactor) * pllmull; + } +#endif /* RCC_CR2_HSI48ON */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) + /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ + frequency = (HSI_VALUE / predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ + frequency = (HSI_VALUE >> 1U) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ + } + } +#if defined(RCC_CR2_HSI48ON) + /* Check if HSI48 is ready and if USB clock selection is HSI48 */ + else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) + { + frequency = HSI48_VALUE; + } +#endif /* RCC_CR2_HSI48ON */ + break; + } +#endif /* USB */ +#if defined(CEC) + case RCC_PERIPHCLK_CEC: + { + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + /* Check if HSI is ready and if CEC clock selection is HSI */ + if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if LSE is ready and if CEC clock selection is LSE */ + else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* CEC */ + default: + { + break; + } + } + return(frequency); +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function @ref HAL_RCCEx_CRSConfig which + (+++) Reset CRS registers to their default values. + (+++) Configure CRS registers with synchronization configuration + (+++) Enable automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + @ref HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (RCC_IRQn/RCC_IRQHandler) + (++) Call function @ref HAL_RCCEx_CRSConfig() + (++) Enable RCC_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() + (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() + (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the timeout +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart = 0U; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while(RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + { + if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + { + crserror |= RCC_CRS_SYNCERR; + } + if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + { + crserror |= RCC_CRS_SYNCMISS; + } + if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c index 545012b..459f362 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c @@ -1,5495 +1,5495 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TIM_Private_Functions TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM OnePulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } - /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - __HAL_LOCK(htim); - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ -return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0U ) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ -return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0U ) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0U; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1 : TIM Channel 1 selected - * @arg TIM_CHANNEL_2 : TIM Channel 2 selected - * @arg TIM_CHANNEL_3 : TIM Channel 3 selected - * @arg TIM_CHANNEL_4 : TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base state - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC state - * @param htim TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM state - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture state - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode state - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode state - * @param htim TIM Encoder handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIM_Private_Functions TIM_Private_Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx TIM periheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0U; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0 : Internal Trigger 0 - * @arg TIM_TS_ITR1 : Internal Trigger 1 - * @arg TIM_TS_ITR2 : Internal Trigger 2 - * @arg TIM_TS_ITR3 : Internal Trigger 3 - * @arg TIM_TS_TI1F_ED : TI1 Edge Detector - * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 - * @arg TIM_TS_ETRF : External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) -{ - uint32_t tmpsmcr = 0U; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0U; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1 : TIM Channel 1 - * @arg TIM_CHANNEL_2 : TIM Channel 2 - * @arg TIM_CHANNEL_3 : TIM Channel 3 - * @arg TIM_CHANNEL_4 : TIM Channel 4 - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + Time Base Initialization + * + Time Base Start + * + Time Base Start Interruption + * + Time Base Start DMA + * + Time Output Compare/PWM Initialization + * + Time Output Compare/PWM Channel Configuration + * + Time Output Compare/PWM Start + * + Time Output Compare/PWM Start Interruption + * + Time Output Compare/PWM Start DMA + * + Time Input Capture Initialization + * + Time Input Capture Channel Configuration + * + Time Input Capture Start + * + Time Input Capture Start Interruption + * + Time Input Capture Start DMA + * + Time One Pulse Initialization + * + Time One Pulse Channel Configuration + * + Time One Pulse Start + * + Time Encoder Interface Initialization + * + Time Encoder Interface Start + * + Time Encoder Interface Start Interruption + * + Time Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + Time OCRef clear configuration + * + Time External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions + * +@verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions + * +@verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM OPWM. + (+) De-initialize the TIM PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions + * +@verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions + * +@verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions + * +@verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +{ + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Reset the SMS bits */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_ALL: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + HAL_TIM_PeriodElapsedCallback(htim); + } + } + /* TIM Break input event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + HAL_TIMEx_BreakCallback(htim); + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + HAL_TIM_TriggerCallback(htim); + } + } + /* TIM commutation event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + HAL_TIMEx_CommutationCallback(htim); + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + __HAL_LOCK(htim); + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if(OutputChannel != InputChannel) + { + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; + } + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0U ) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0U ) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + uint32_t tmpsmcr = 0U; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Reset the SMS and TS Bits */ + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + } + break; + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + } + break; + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + } + break; + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + } + break; + case TIM_CLOCKSOURCE_ITR0: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); + } + break; + case TIM_CLOCKSOURCE_ITR1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); + } + break; + case TIM_CLOCKSOURCE_ITR2: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); + } + break; + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) + { + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1 : TIM Channel 1 selected + * @arg TIM_CHANNEL_2 : TIM Channel 2 selected + * @arg TIM_CHANNEL_3 : TIM Channel 3 selected + * @arg TIM_CHANNEL_4 : TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) Timer Period elapsed callback + (+) Timer Output Compare callback + (+) Timer Input capture callback + (+) Timer Trigger callback + (+) Timer Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ + +} +/** + * @brief Output Compare callback in non blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} +/** + * @brief Input Capture callback in non blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base state + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC state + * @param htim TIM Ouput Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM state + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture state + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode state + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode state + * @param htim TIM Encoder handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_ErrorCallback(htim); +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_PWM_PulseFinishedCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_IC_CaptureCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_PeriodElapsedCallback(htim); +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_TriggerCallback(htim); +} + +/** + * @brief Time Base configuration + * @param TIMx TIM periheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1 = 0U; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = (uint32_t)Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0 : Internal Trigger 0 + * @arg TIM_TS_ITR1 : Internal Trigger 1 + * @arg TIM_TS_ITR2 : Internal Trigger 2 + * @arg TIM_TS_ITR3 : Internal Trigger 3 + * @arg TIM_TS_TI1F_ED : TI1 Edge Detector + * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 + * @arg TIM_TS_ETRF : External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +{ + uint32_t tmpsmcr = 0U; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0U; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1 : TIM Channel 1 + * @arg TIM_CHANNEL_2 : TIM Channel 2 + * @arg TIM_CHANNEL_3 : TIM Channel 3 + * @arg TIM_CHANNEL_4 : TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << Channel); +} + + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c index 729fd89..9bf2c75 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c @@ -1,2012 +1,2012 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal bread and dead time configuration - * + Time Master and Slave synchronization configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Complementary Output Compare : HAL_TIM_OC_MspInit() - (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() - (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions - * @{ - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complemetary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ -/** - * @brief Configure the TIM commutation event sequence. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation Interrupt Request */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the MMS Bits */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - htim->Instance->SMCR &= ~TIM_SMCR_MSM; - /* Set or Reset the MSM Bit */ - htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM14 Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * This parameter can be one of the following values: - * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO - * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock - * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 - * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions - * @brief Extension Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions - * @brief Extension Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface state - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIMEx_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp = 0U; - - tmp = TIM_CCER_CC1NE << Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal bread and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Complementary Output Compare : HAL_TIM_OC_MspInit() + (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() + (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: +{ + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complemetary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) + { + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; + } + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ +/** + * @brief Configure the TIM commutation event sequence. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation Interrupt Request */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the MMS Bits */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + htim->Instance->SMCR &= ~TIM_SMCR_MSM; + /* Set or Reset the MSM Bit */ + htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM14 Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock + * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @retval None + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + uint32_t tmpsmcr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions + * @brief Extension Callbacks functions + * +@verbatim + ============================================================================== + ##### Extension Callbacks functions ##### + ============================================================================== + [..] + This section provides Extension TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_CommutationCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIMEx_CommutationCallback(htim); +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions + * @brief Extension Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extension Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface state + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIMEx_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp = 0U; + + tmp = TIM_CCER_CC1NE << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << Channel); +} + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c index 6b943be..d9e4253 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c @@ -1,238 +1,238 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_exti.c - * @author MCD Application Team - * @brief EXTI LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_exti.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Private_Macros - * @{ - */ - -#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) - -#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) - - -#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the EXTI registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_DeInit(void) -{ - /* Interrupt mask register set to default reset values */ -#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) - LL_EXTI_WriteReg(IMR, 0x0FF40000U); -#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) - LL_EXTI_WriteReg(IMR, 0x7FF40000U); -#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - LL_EXTI_WriteReg(IMR, 0x0F940000U); -#else - LL_EXTI_WriteReg(IMR, 0x7F840000U); -#endif - /* Event mask register set to default reset values */ - LL_EXTI_WriteReg(EMR, 0x00000000U); - /* Rising Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(RTSR, 0x00000000U); - /* Falling Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(FTSR, 0x00000000U); - /* Software interrupt event register set to default reset values */ - LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register clear */ - LL_EXTI_WriteReg(PR, 0x007BFFFFU); - - return SUCCESS; -} - -/** - * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. - * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - ErrorStatus status = SUCCESS; - /* Check the parameters */ - assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); - assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); - - /* ENABLE LineCommand */ - if (EXTI_InitStruct->LineCommand != DISABLE) - { - assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); - - /* Configure EXTI Lines in range from 0 to 31 */ - if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) - { - switch (EXTI_InitStruct->Mode) - { - case LL_EXTI_MODE_IT: - /* First Disable Event on provided Lines */ - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable IT on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_EVENT: - /* First Disable IT on provided Lines */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Event on provided Lines */ - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_IT_EVENT: - /* Directly Enable IT & Event on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) - { - switch (EXTI_InitStruct->Trigger) - { - case LL_EXTI_TRIGGER_RISING: - /* First Disable Falling Trigger on provided Lines */ - LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Rising Trigger on provided Lines */ - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_FALLING: - /* First Disable Rising Trigger on provided Lines */ - LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Falling Trigger on provided Lines */ - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_RISING_FALLING: - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - } - } - } - /* DISABLE LineCommand */ - else - { - /* De-configure EXTI Lines in range from 0 to 31 */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - } - return status; -} - -/** - * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. - * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval None - */ -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; - EXTI_InitStruct->LineCommand = DISABLE; - EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; - EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (EXTI) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ +#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) + LL_EXTI_WriteReg(IMR, 0x0FF40000U); +#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) + LL_EXTI_WriteReg(IMR, 0x7FF40000U); +#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + LL_EXTI_WriteReg(IMR, 0x0F940000U); +#else + LL_EXTI_WriteReg(IMR, 0x7F840000U); +#endif + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register clear */ + LL_EXTI_WriteReg(PR, 0x007BFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c index b1a6bdb..3fae50c 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c @@ -1,279 +1,279 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_gpio.c - * @author MCD Application Team - * @brief GPIO LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_gpio.h" -#include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) - -/** @addtogroup GPIO_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) - -#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ - ((__VALUE__) == LL_GPIO_MODE_ANALOG)) - -#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ - ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) - -#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ - ((__VALUE__) == LL_GPIO_PULL_UP) ||\ - ((__VALUE__) == LL_GPIO_PULL_DOWN)) - -#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ - ((__VALUE__) == LL_GPIO_AF_1 ) ||\ - ((__VALUE__) == LL_GPIO_AF_2 ) ||\ - ((__VALUE__) == LL_GPIO_AF_3 ) ||\ - ((__VALUE__) == LL_GPIO_AF_4 ) ||\ - ((__VALUE__) == LL_GPIO_AF_5 ) ||\ - ((__VALUE__) == LL_GPIO_AF_6 ) ||\ - ((__VALUE__) == LL_GPIO_AF_7 )) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize GPIO registers (Registers restored to their default values). - * @param GPIOx GPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: Wrong GPIO Port - */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force and Release reset on clock of GPIOx Port */ - if (GPIOx == GPIOA) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); - } - else if (GPIOx == GPIOB) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); - } - else if (GPIOx == GPIOC) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); - } -#if defined(GPIOD) - else if (GPIOx == GPIOD) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); - } -#endif /* GPIOD */ -#if defined(GPIOE) - else if (GPIOx == GPIOE) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); - } -#endif /* GPIOE */ -#if defined(GPIOF) - else if (GPIOx == GPIOF) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); - } -#endif /* GPIOF */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. - * @param GPIOx GPIO Port - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * that contains the configuration information for the specified GPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t pinpos = 0x00000000U; - uint32_t currentpin = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - /* pinpos = 0; useless as already done in default initialization */ - - /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) - { - /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); - - if (currentpin) - { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Speed mode parameters */ - assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); - - /* Speed mode configuration */ - LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); - } - - /* Pull-up Pull down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - - if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) - { - /* Check Alternate parameter */ - assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - - /* Speed mode configuration */ - if (currentpin < LL_GPIO_PIN_8) - { - LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - else - { - LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - } - } - pinpos++; - } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; - GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct->Alternate = LL_GPIO_AF_0; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_gpio.h" +#include "stm32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + } +#endif /* GPIOF */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos = 0x00000000U; + uint32_t currentpin = 0x00000000U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + /* pinpos = 0; useless as already done in default initialization */ + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + + if (currentpin) + { + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + } + pinpos++; + } + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c similarity index 96% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c index fc2fe50..6a244fd 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c @@ -1,599 +1,599 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_rcc.c - * @author MCD Application Team - * @brief RCC LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_rcc.h" -#ifdef USE_FULL_ASSERT - #include "stm32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_LL_Private_Macros - * @{ - */ -#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) -#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) -#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) -#else -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) -#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ - -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) - -#if defined(USB) -#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) -#endif /* USB */ - -#if defined(CEC) -#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) -#endif /* CEC */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_LL_Private_Functions RCC Private functions - * @{ - */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_LL_EF_Init - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB and APB1 prescaler set to 1. - * - CSS, MCO OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RCC registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_RCC_DeInit(void) -{ - uint32_t vl_mask = 0U; - - /* Set HSION bit */ - LL_RCC_HSI_Enable(); - - /* Set HSITRIM bits to the reset value*/ - LL_RCC_HSI_SetCalibTrimming(0x10U); - - /* Reset SW, HPRE, PPRE and MCOSEL bits */ - vl_mask = 0xFFFFFFFFU; - CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); - LL_RCC_WriteReg(CFGR, vl_mask); - - /* Reset HSEON, CSSON, PLLON bits */ - vl_mask = 0xFFFFFFFFU; - CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); - LL_RCC_WriteReg(CR, vl_mask); - - /* Reset HSEBYP bit */ - LL_RCC_HSE_DisableBypass(); - - /* Reset CFGR register */ - LL_RCC_WriteReg(CFGR, 0x00000000U); - -#if defined(RCC_HSI48_SUPPORT) - /* Reset CR2 register */ - LL_RCC_WriteReg(CR2, 0x00000000U); - - /* Disable HSI48 */ - LL_RCC_HSI48_Disable(); - -#endif /*RCC_HSI48_SUPPORT*/ - /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ - LL_RCC_HSI14_SetCalibTrimming(0x10U); - LL_RCC_HSI14_Disable(); - LL_RCC_HSI14_EnableADCControl(); - - /* Reset CFGR2 register */ - LL_RCC_WriteReg(CFGR2, 0x00000000U); - - /* Reset CFGR3 register */ - LL_RCC_WriteReg(CFGR3, 0x00000000U); - - /* Clear pending flags */ -#if defined(RCC_HSI48_SUPPORT) - vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); -#else - vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); -#endif /* RCC_HSI48_SUPPORT */ - SET_BIT(RCC->CIR, vl_mask); - - /* Disable all interrupts */ - LL_RCC_WriteReg(CIR, 0x00000000U); - - return SUCCESS; -} - -/** - * @} - */ - -/** @addtogroup RCC_LL_EF_Get_Freq - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * and different peripheral clocks available on the device. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) - * @note If SYSCLK source is PLL, function returns values based on - * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. - * @note (**) HSI_VALUE is a defined constant but the real value may vary - * depending on the variations in voltage and temperature. - * @note (***) HSE_VALUE is a defined constant, user has to ensure that - * HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * @note The result of this function could be incorrect when using fractional - * value for HSE crystal. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * @{ - */ - -/** - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function - * must be called to update structure fields. Otherwise, any - * configuration based on this function will be incorrect. - * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies - * @retval None - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) -{ - /* Get SYSCLK frequency */ - RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); - - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); - - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); -} - -/** - * @brief Return USARTx clock frequency - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval USART clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready - */ -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) -{ - uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); -#if defined(RCC_CFGR3_USART1SW) - if (USARTxSource == LL_RCC_USART1_CLKSOURCE) - { - /* USART1CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#endif /* RCC_CFGR3_USART1SW */ - -#if defined(RCC_CFGR3_USART2SW) - if (USARTxSource == LL_RCC_USART2_CLKSOURCE) - { - /* USART2CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#endif /* RCC_CFGR3_USART2SW */ - -#if defined(RCC_CFGR3_USART3SW) - if (USARTxSource == LL_RCC_USART3_CLKSOURCE) - { - /* USART3CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - -#endif /* RCC_CFGR3_USART3SW */ - return usart_frequency; -} - -/** - * @brief Return I2Cx clock frequency - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @retval I2C clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready - */ -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) -{ - uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); - - /* I2C1 CLK clock frequency */ - if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) - { - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - default: - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - } - } - - return i2c_frequency; -} - -#if defined(USB) -/** - * @brief Return USBx clock frequency - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval USB clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected - */ -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) -{ - uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); - - /* USBCLK clock frequency */ - switch (LL_RCC_GetUSBClockSource(USBxSource)) - { - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady()) - { - usb_frequency = RCC_PLL_GetFreqDomain_SYS(); - } - break; - -#if defined(RCC_CFGR3_USBSW_HSI48) - case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ - default: - if (LL_RCC_HSI48_IsReady()) - { - usb_frequency = HSI48_VALUE; - } - break; -#else - case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ - default: - usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; -#endif /* RCC_CFGR3_USBSW_HSI48 */ - } - - return usb_frequency; -} -#endif /* USB */ - -#if defined(CEC) -/** - * @brief Return CECx clock frequency - * @param CECxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval CEC clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready - */ -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) -{ - uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); - - /* CECCLK clock frequency */ - switch (LL_RCC_GetCECClockSource(CECxSource)) - { - case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ - if (LL_RCC_HSI_IsReady()) - { - cec_frequency = HSI_VALUE / 244U; - } - break; - - case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ - default: - if (LL_RCC_LSE_IsReady()) - { - cec_frequency = LSE_VALUE; - } - break; - } - - return cec_frequency; -} -#endif /* CEC */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCC_LL_Private_Functions - * @{ - */ - -/** - * @brief Return SYSTEM clock frequency - * @retval SYSTEM clock frequency (in Hz) - */ -uint32_t RCC_GetSystemClockFreq(void) -{ - uint32_t frequency = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (LL_RCC_GetSysClkSource()) - { - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - frequency = HSI_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - frequency = HSE_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ - frequency = RCC_PLL_GetFreqDomain_SYS(); - break; - -#if defined(RCC_HSI48_SUPPORT) - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ - frequency = HSI48_VALUE; - break; -#endif /* RCC_HSI48_SUPPORT */ - - default: - frequency = HSI_VALUE; - break; - } - - return frequency; -} - -/** - * @brief Return HCLK clock frequency - * @param SYSCLK_Frequency SYSCLK clock frequency - * @retval HCLK clock frequency (in Hz) - */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) -{ - /* HCLK clock frequency */ - return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); -} - -/** - * @brief Return PCLK1 clock frequency - * @param HCLK_Frequency HCLK clock frequency - * @retval PCLK1 clock frequency (in Hz) - */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) -{ - /* PCLK1 clock frequency */ - return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); -} -/** - * @brief Return PLL clock frequency used for system domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ - - /* Get PLL source */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE; -#else - case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE / 2U; -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - break; - -#if defined(RCC_HSI48_SUPPORT) - case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ - pllinputfreq = HSI48_VALUE; - break; -#endif /* RCC_HSI48_SUPPORT */ - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllinputfreq = HSI_VALUE; -#else - pllinputfreq = HSI_VALUE / 2U; -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - break; - } -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); -#else - return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) +#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) + +#if defined(USB) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB */ + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + uint32_t vl_mask = 0U; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x10U); + + /* Reset SW, HPRE, PPRE and MCOSEL bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); + LL_RCC_WriteReg(CFGR, vl_mask); + + /* Reset HSEON, CSSON, PLLON bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); + LL_RCC_WriteReg(CR, vl_mask); + + /* Reset HSEBYP bit */ + LL_RCC_HSE_DisableBypass(); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + +#if defined(RCC_HSI48_SUPPORT) + /* Reset CR2 register */ + LL_RCC_WriteReg(CR2, 0x00000000U); + + /* Disable HSI48 */ + LL_RCC_HSI48_Disable(); + +#endif /*RCC_HSI48_SUPPORT*/ + /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ + LL_RCC_HSI14_SetCalibTrimming(0x10U); + LL_RCC_HSI14_Disable(); + LL_RCC_HSI14_EnableADCControl(); + + /* Reset CFGR2 register */ + LL_RCC_WriteReg(CFGR2, 0x00000000U); + + /* Reset CFGR3 register */ + LL_RCC_WriteReg(CFGR3, 0x00000000U); + + /* Clear pending flags */ +#if defined(RCC_HSI48_SUPPORT) + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); +#else + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); +#endif /* RCC_HSI48_SUPPORT */ + SET_BIT(RCC->CIR, vl_mask); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIR, 0x00000000U); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a defined constant but the real value may vary + * depending on the variations in voltage and temperature. + * @note (***) HSE_VALUE is a defined constant, user has to ensure that + * HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval USART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); +#if defined(RCC_CFGR3_USART1SW) + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART1SW */ + +#if defined(RCC_CFGR3_USART2SW) + if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) + if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + +#endif /* RCC_CFGR3_USART3SW */ + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + /* I2C1 CLK clock frequency */ + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + } + } + + return i2c_frequency; +} + +#if defined(USB) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + +#if defined(RCC_CFGR3_USBSW_HSI48) + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + default: + if (LL_RCC_HSI48_IsReady()) + { + usb_frequency = HSI48_VALUE; + } + break; +#else + case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ + default: + usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; +#endif /* RCC_CFGR3_USBSW_HSI48 */ + } + + return usb_frequency; +} +#endif /* USB */ + +#if defined(CEC) +/** + * @brief Return CECx clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ + if (LL_RCC_HSI_IsReady()) + { + cec_frequency = HSI_VALUE / 244U; + } + break; + + case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ + default: + if (LL_RCC_LSE_IsReady()) + { + cec_frequency = LSE_VALUE; + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + frequency = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; +#else + case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ + pllinputfreq = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllinputfreq = HSI_VALUE; +#else + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + } +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); +#else + return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c similarity index 97% rename from hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c rename to hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c index c48809e..836204a 100644 --- a/hardware/esl_blaster/FW/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c +++ b/hardware/esl_blaster/FW01/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c @@ -1,620 +1,620 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_utils.c - * @author MCD Application Team - * @brief UTILS LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_rcc.h" -#include "stm32f0xx_ll_utils.h" -#include "stm32f0xx_ll_system.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @addtogroup UTILS_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Constants - * @{ - */ - -/* Defines used for PLL range */ -#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ -#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ - -/* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ - -/* Defines used for FLASH latency according to SYSCLK Frequency */ -#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Macros - * @{ - */ -#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) - -#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) - -#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_16)) - -#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) - -#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)) - - -#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) - -#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Functions UTILS Private functions - * @{ - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); -#endif /* FLASH_ACR_LATENCY */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -static ErrorStatus UTILS_PLL_IsBusy(void); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UTILS_LL_EF_DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on SysTick counter flag - * @note When a RTOS is used, it is recommended to avoid using blocking delay - * and use rather osDelay service. - * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which - * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -void LL_mDelay(uint32_t Delay) -{ - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - - /* Add a period to guaranty minimum wait */ - if (Delay < LL_MAX_DELAY) - { - Delay++; - } - - while (Delay) - { - if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - { - Delay--; - } - } -} - -/** - * @} - */ - -/** @addtogroup UTILS_EF_SYSTEM - * @brief System Configuration functions - * - @verbatim - =============================================================================== - ##### System Configuration functions ##### - =============================================================================== - [..] - System, AHB and APB buses clocks configuration - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. - @endverbatim - @internal - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: - (++) +-----------------------------------------------+ - (++) | Latency | SYSCLK clock frequency (MHz) | - (++) |---------------|-------------------------------| - (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - (++) |---------------|-------------------------------| - (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - (++) +-----------------------------------------------+ - @endinternal - * @{ - */ - -/** - * @brief This function sets directly SystemCoreClock CMSIS variable. - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; -} - -/** - * @brief This function configures system clock with HSI as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) - * - PREDIV: Set to 2 for few devices - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @note FLASH latency can be modified through this function. - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - /* Check PREDIV value */ - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); -#else - /* Force PREDIV value to 2 */ - UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI if not enabled */ - if (LL_RCC_HSI_IsReady() != 1U) - { - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - { - /* Wait for HSI ready */ - } - } - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -#if defined(RCC_CFGR_SW_HSI48) -/** - * @brief This function configures system clock with HSI48 as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check PREDIV value */ - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI48 if not enabled */ - if (LL_RCC_HSI48_IsReady() != 1U) - { - LL_RCC_HSI48_Enable(); - while (LL_RCC_HSI48_IsReady() != 1U) - { - /* Wait for HSI48 ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -#endif /*RCC_CFGR_SW_HSI48*/ -/** - * @brief This function configures system clock with HSE as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @note FLASH latency can be modified through this function. - * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 - * @param HSEBypass This parameter can be one of the following values: - * @arg @ref LL_UTILS_HSEBYPASS_ON - * @arg @ref LL_UTILS_HSEBYPASS_OFF - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check PREDIV value */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); -#else - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); - - /* Enable HSE if not enabled */ - if (LL_RCC_HSE_IsReady() != 1U) - { - /* Check if need to enable HSE bypass feature or not */ - if (HSEBypass == LL_UTILS_HSEBYPASS_ON) - { - LL_RCC_HSE_EnableBypass(); - } - else - { - LL_RCC_HSE_DisableBypass(); - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - while (LL_RCC_HSE_IsReady() != 1U) - { - /* Wait for HSE ready */ - } - } - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param Frequency SYSCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if (Frequency == 0U) - { - status = ERROR; - } - else - { - if (Frequency > UTILS_LATENCY1_FREQ) - { - /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} -#endif /* FLASH_ACR_LATENCY */ - -/** - * @brief Function to check that PLL can be modified - * @param PLL_InputFrequency PLL input frequency (in Hz) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @retval PLL output frequency (in Hz) - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) -{ - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); - - /* Check different PLL parameters according to RM */ - /* The application software must set correctly the PLL multiplication factor to - be in the range 16-48MHz */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); - - return pllfreq; -} - -/** - * @brief Function to check that PLL can be modified - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - ErrorStatus status = SUCCESS; - - /* Check if PLL is busy*/ - if (LL_RCC_PLL_IsReady() != 0U) - { - /* PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief Function to enable PLL and switch system clock to PLL - * @param SYSCLK_Frequency SYSCLK frequency - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t sysclk_frequency_current = 0U; - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - - /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); - - /* Increasing the number of wait states because of higher CPU frequency */ - if (sysclk_frequency_current < SYSCLK_Frequency) - { - /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - } - - /* Update system clock configuration */ - if (status == SUCCESS) - { - /* Enable PLL */ - LL_RCC_PLL_Enable(); - while (LL_RCC_PLL_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1 & APB2 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (sysclk_frequency_current > SYSCLK_Frequency) - { - /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - } - - /* Update SystemCoreClock variable */ - if (status == SUCCESS) - { - LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_system.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ + +/* Defines used for PLL range */ +#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to SYSCLK Frequency */ +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_16)) + +#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)) + + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. + @endverbatim + @internal + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + (++) +-----------------------------------------------+ + (++) | Latency | SYSCLK clock frequency (MHz) | + (++) |---------------|-------------------------------| + (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + (++) |---------------|-------------------------------| + (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + (++) +-----------------------------------------------+ + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + * - PREDIV: Set to 2 for few devices + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + /* Force PREDIV value to 2 */ + UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#if defined(RCC_CFGR_SW_HSI48) +/** + * @brief This function configures system clock with HSI48 as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI48 if not enabled */ + if (LL_RCC_HSI48_IsReady() != 1U) + { + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1U) + { + /* Wait for HSI48 ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#endif /*RCC_CFGR_SW_HSI48*/ +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency SYSCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + { + status = ERROR; + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} +#endif /* FLASH_ACR_LATENCY */ + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + + /* Check different PLL parameters according to RM */ + /* The application software must set correctly the PLL multiplication factor to + be in the range 16-48MHz */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t sysclk_frequency_current = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + + /* Calculate current SYSCLK frequency */ + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (sysclk_frequency_current < SYSCLK_Frequency) + { + /* Set FLASH latency to highest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (sysclk_frequency_current > SYSCLK_Frequency) + { + /* Set FLASH latency to lowest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/ESLBlaster.ioc b/hardware/esl_blaster/FW01/ESLBlaster.ioc similarity index 97% rename from hardware/esl_blaster/FW/ESLBlaster.ioc rename to hardware/esl_blaster/FW01/ESLBlaster.ioc index cf880af..92efad8 100644 --- a/hardware/esl_blaster/FW/ESLBlaster.ioc +++ b/hardware/esl_blaster/FW01/ESLBlaster.ioc @@ -1,102 +1,102 @@ -#MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32F0 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IP3=USB -Mcu.IP4=USB_DEVICE -Mcu.IPNb=5 -Mcu.Name=STM32F070F6Px -Mcu.Package=TSSOP20 -Mcu.Pin0=PF0-OSC_IN -Mcu.Pin1=PF1-OSC_OUT -Mcu.Pin2=PA11 -Mcu.Pin3=PA12 -Mcu.Pin4=VP_SYS_VS_PINREMAP -Mcu.Pin5=VP_SYS_VS_Systick -Mcu.Pin6=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS -Mcu.PinsNb=7 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32F070F6Px -MxCube.Version=5.2.0 -MxDb.Version=DB.5.0.20 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.USB_IRQn=true\:0\:0\:false\:false\:true\:false\:true -PA11.Mode=Device -PA11.Signal=USB_DM -PA12.Mode=Device -PA12.Signal=USB_DP -PCC.Checker=false -PCC.Line=STM32F0x0 Value Line -PCC.MCU=STM32F070F6Px -PCC.PartNumber=STM32F070F6Px -PCC.Seq0=0 -PCC.Series=STM32F0 -PCC.Temperature=25 -PCC.Vdd=3.6 -PF0-OSC_IN.Mode=HSE-External-Oscillator -PF0-OSC_IN.Signal=RCC_OSC_IN -PF1-OSC_OUT.Mode=HSE-External-Oscillator -PF1-OSC_OUT.Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=true -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F070F6Px -ProjectManager.FirmwarePackage=STM32Cube FW_F0 V1.10.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x180 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain=STM32CubeIDE -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=ESLBlaster.ioc -ProjectManager.ProjectName=ESLBlaster -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=STM32CubeIDE -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true -RCC.AHBFreq_Value=48000000 -RCC.APB1Freq_Value=48000000 -RCC.APB1TimFreq_Value=48000000 -RCC.FCLKCortexFreq_Value=48000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=48000000 -RCC.HSE_VALUE=4000000 -RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,PLLCLKFreq_Value,PLLMUL,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USART1Freq_Value,USBOutputFreqValue,VCOOutput2Freq_Value -RCC.PLLCLKFreq_Value=48000000 -RCC.PLLMUL=RCC_PLL_MUL12 -RCC.SYSCLKFreq_VALUE=48000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.TimSysFreq_Value=48000000 -RCC.USART1Freq_Value=48000000 -RCC.USBOutputFreqValue=48000000 -RCC.VCOOutput2Freq_Value=4000000 -USB_DEVICE.CLASS_NAME_FS=CDC -USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS -USB_DEVICE.VirtualMode=Cdc -USB_DEVICE.VirtualModeFS=Cdc_FS -VP_SYS_VS_PINREMAP.Mode=PINREMAP -VP_SYS_VS_PINREMAP.Signal=SYS_VS_PINREMAP -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS -board=custom +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32F0 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IP3=USB +Mcu.IP4=USB_DEVICE +Mcu.IPNb=5 +Mcu.Name=STM32F070F6Px +Mcu.Package=TSSOP20 +Mcu.Pin0=PF0-OSC_IN +Mcu.Pin1=PF1-OSC_OUT +Mcu.Pin2=PA11 +Mcu.Pin3=PA12 +Mcu.Pin4=VP_SYS_VS_PINREMAP +Mcu.Pin5=VP_SYS_VS_Systick +Mcu.Pin6=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS +Mcu.PinsNb=7 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F070F6Px +MxCube.Version=5.2.0 +MxDb.Version=DB.5.0.20 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.USB_IRQn=true\:0\:0\:false\:false\:true\:false\:true +PA11.Mode=Device +PA11.Signal=USB_DM +PA12.Mode=Device +PA12.Signal=USB_DP +PCC.Checker=false +PCC.Line=STM32F0x0 Value Line +PCC.MCU=STM32F070F6Px +PCC.PartNumber=STM32F070F6Px +PCC.Seq0=0 +PCC.Series=STM32F0 +PCC.Temperature=25 +PCC.Vdd=3.6 +PF0-OSC_IN.Mode=HSE-External-Oscillator +PF0-OSC_IN.Signal=RCC_OSC_IN +PF1-OSC_OUT.Mode=HSE-External-Oscillator +PF1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F070F6Px +ProjectManager.FirmwarePackage=STM32Cube FW_F0 V1.10.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x180 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain=STM32CubeIDE +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=ESLBlaster.ioc +ProjectManager.ProjectName=ESLBlaster +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true +RCC.AHBFreq_Value=48000000 +RCC.APB1Freq_Value=48000000 +RCC.APB1TimFreq_Value=48000000 +RCC.FCLKCortexFreq_Value=48000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=48000000 +RCC.HSE_VALUE=4000000 +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,PLLCLKFreq_Value,PLLMUL,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USART1Freq_Value,USBOutputFreqValue,VCOOutput2Freq_Value +RCC.PLLCLKFreq_Value=48000000 +RCC.PLLMUL=RCC_PLL_MUL12 +RCC.SYSCLKFreq_VALUE=48000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TimSysFreq_Value=48000000 +RCC.USART1Freq_Value=48000000 +RCC.USBOutputFreqValue=48000000 +RCC.VCOOutput2Freq_Value=4000000 +USB_DEVICE.CLASS_NAME_FS=CDC +USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS +USB_DEVICE.VirtualMode=Cdc +USB_DEVICE.VirtualModeFS=Cdc_FS +VP_SYS_VS_PINREMAP.Mode=PINREMAP +VP_SYS_VS_PINREMAP.Signal=SYS_VS_PINREMAP +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS +VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS +board=custom diff --git a/hardware/esl_blaster/FW/Inc/gpio.h b/hardware/esl_blaster/FW01/Inc/gpio.h similarity index 96% rename from hardware/esl_blaster/FW/Inc/gpio.h rename to hardware/esl_blaster/FW01/Inc/gpio.h index d3c4629..a5a8577 100644 --- a/hardware/esl_blaster/FW/Inc/gpio.h +++ b/hardware/esl_blaster/FW01/Inc/gpio.h @@ -1,57 +1,57 @@ -/** - ****************************************************************************** - * File Name : gpio.h - * Description : This file contains all the functions prototypes for - * the gpio - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __gpio_H -#define __gpio_H -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -void MX_GPIO_Init(void); - -/* USER CODE BEGIN Prototypes */ - -/* USER CODE END Prototypes */ - -#ifdef __cplusplus -} -#endif -#endif /*__ pinoutConfig_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * File Name : gpio.h + * Description : This file contains all the functions prototypes for + * the gpio + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __gpio_H +#define __gpio_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ pinoutConfig_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/main.h b/hardware/esl_blaster/FW01/Inc/main.h similarity index 96% rename from hardware/esl_blaster/FW/Inc/main.h rename to hardware/esl_blaster/FW01/Inc/main.h index 9ee7a59..f30c871 100644 --- a/hardware/esl_blaster/FW/Inc/main.h +++ b/hardware/esl_blaster/FW01/Inc/main.h @@ -1,49 +1,49 @@ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#ifndef __MAIN_H -#define __MAIN_H - -#include "stm32f0xx_hal.h" -#include "stm32f0xx_ll_crs.h" -#include "stm32f0xx_ll_rcc.h" -#include "stm32f0xx_ll_bus.h" -#include "stm32f0xx_ll_system.h" -#include "stm32f0xx_ll_exti.h" -#include "stm32f0xx_ll_cortex.h" -#include "stm32f0xx_ll_utils.h" -#include "stm32f0xx_ll_pwr.h" -#include "stm32f0xx_ll_dma.h" -#include "stm32f0xx_ll_gpio.h" - -#define FIFO_SIZE 256 // Must be 2^N - -#define FIFO_INCR(x) (((x)+1)&((FIFO_SIZE)-1)) - -typedef struct FIFO { - uint32_t head; - uint32_t tail; - uint8_t data[FIFO_SIZE]; -} FIFO; - -extern volatile FIFO RX_FIFO; - -void Error_Handler(void); - -#endif +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#ifndef __MAIN_H +#define __MAIN_H + +#include "stm32f0xx_hal.h" +#include "stm32f0xx_ll_crs.h" +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_bus.h" +#include "stm32f0xx_ll_system.h" +#include "stm32f0xx_ll_exti.h" +#include "stm32f0xx_ll_cortex.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_pwr.h" +#include "stm32f0xx_ll_dma.h" +#include "stm32f0xx_ll_gpio.h" + +#define FIFO_SIZE 256 // Must be 2^N + +#define FIFO_INCR(x) (((x)+1)&((FIFO_SIZE)-1)) + +typedef struct FIFO { + uint32_t head; + uint32_t tail; + uint8_t data[FIFO_SIZE]; +} FIFO; + +extern volatile FIFO RX_FIFO; + +void Error_Handler(void); + +#endif diff --git a/hardware/esl_blaster/FW/Inc/stm32_assert.h b/hardware/esl_blaster/FW01/Inc/stm32_assert.h similarity index 97% rename from hardware/esl_blaster/FW/Inc/stm32_assert.h rename to hardware/esl_blaster/FW01/Inc/stm32_assert.h index c78c531..47016da 100644 --- a/hardware/esl_blaster/FW/Inc/stm32_assert.h +++ b/hardware/esl_blaster/FW01/Inc/stm32_assert.h @@ -1,53 +1,53 @@ -/** - ****************************************************************************** - * @file stm32_assert.h - * @brief STM32 assert file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_ASSERT_H -#define __STM32_ASSERT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Includes ------------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(char* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_ASSERT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/stm32f0xx_hal_conf.h b/hardware/esl_blaster/FW01/Inc/stm32f0xx_hal_conf.h similarity index 97% rename from hardware/esl_blaster/FW/Inc/stm32f0xx_hal_conf.h rename to hardware/esl_blaster/FW01/Inc/stm32f0xx_hal_conf.h index b7e58e4..e53753b 100644 --- a/hardware/esl_blaster/FW/Inc/stm32f0xx_hal_conf.h +++ b/hardware/esl_blaster/FW01/Inc/stm32f0xx_hal_conf.h @@ -1,323 +1,323 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CONF_H -#define __STM32F0xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_UART_MODULE_ENABLED */ -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/*#define HAL_EXTI_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)4000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator for ADC (HSI14) value. - */ -#if !defined (HSI14_VALUE) -#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -/** - * @brief Internal High Speed oscillator for USB (HSI48) value. - */ -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)40000) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSI) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ - /* Warning: Must be set to higher priority for HAL_Delay() */ - /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f0xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f0xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f0xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f0xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f0xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f0xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f0xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f0xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32f0xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f0xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f0xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f0xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f0xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f0xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f0xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f0xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f0xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f0xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f0xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f0xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f0xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f0xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f0xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32f0xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f0xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f0xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f0xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(char* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f0xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CONF_H +#define __STM32F0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)4000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator for ADC (HSI14) value. + */ +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSI) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f0xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/stm32f0xx_it.h b/hardware/esl_blaster/FW01/Inc/stm32f0xx_it.h similarity index 96% rename from hardware/esl_blaster/FW/Inc/stm32f0xx_it.h rename to hardware/esl_blaster/FW01/Inc/stm32f0xx_it.h index 0edecec..38076f1 100644 --- a/hardware/esl_blaster/FW/Inc/stm32f0xx_it.h +++ b/hardware/esl_blaster/FW01/Inc/stm32f0xx_it.h @@ -1,66 +1,66 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f0xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_IT_H -#define __STM32F0xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void SVC_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void USB_IRQHandler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_IT_H +#define __STM32F0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USB_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/usb_device.h b/hardware/esl_blaster/FW01/Inc/usb_device.h similarity index 95% rename from hardware/esl_blaster/FW/Inc/usb_device.h rename to hardware/esl_blaster/FW01/Inc/usb_device.h index 1d85703..f255f88 100644 --- a/hardware/esl_blaster/FW/Inc/usb_device.h +++ b/hardware/esl_blaster/FW01/Inc/usb_device.h @@ -1,105 +1,105 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usb_device.h - * @version : v2.0_Cube - * @brief : Header for usb_device.c file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEVICE__H__ -#define __USB_DEVICE__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" -#include "stm32f0xx_hal.h" -#include "usbd_def.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @{ - */ - -/** @defgroup USBD_DEVICE USBD_DEVICE - * @brief Device file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables - * @brief Public variables. - * @{ - */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* - * -- Insert your variables declaration here -- - */ -/* USER CODE BEGIN VARIABLES */ - -/* USER CODE END VARIABLES */ -/** - * @} - */ - -/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/** USB Device initialization function. */ -void MX_USB_DEVICE_Init(void); - -/* - * -- Insert functions declaration here -- - */ -/* USER CODE BEGIN FD */ - -/* USER CODE END FD */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_DEVICE__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.h + * @version : v2.0_Cube + * @brief : Header for usb_device.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEVICE__H__ +#define __USB_DEVICE__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_DEVICE USBD_DEVICE + * @brief Device file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables + * @brief Public variables. + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ +/** + * @} + */ + +/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/** USB Device initialization function. */ +void MX_USB_DEVICE_Init(void); + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEVICE__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/usbd_cdc_if.h b/hardware/esl_blaster/FW01/Inc/usbd_cdc_if.h similarity index 95% rename from hardware/esl_blaster/FW/Inc/usbd_cdc_if.h rename to hardware/esl_blaster/FW01/Inc/usbd_cdc_if.h index 5299c47..0a9b7c1 100644 --- a/hardware/esl_blaster/FW/Inc/usbd_cdc_if.h +++ b/hardware/esl_blaster/FW01/Inc/usbd_cdc_if.h @@ -1,130 +1,130 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usbd_cdc_if.h - * @version : v2.0_Cube - * @brief : Header for usbd_cdc_if.c file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_H__ -#define __USBD_CDC_IF_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @brief For Usb device. - * @{ - */ - -/** @defgroup USBD_CDC_IF USBD_CDC_IF - * @brief Usb VCP device module - * @{ - */ - -/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines - * @brief Defines. - * @{ - */ -/* USER CODE BEGIN EXPORTED_DEFINES */ - -/* USER CODE END EXPORTED_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types - * @brief Types. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_TYPES */ - -/* USER CODE END EXPORTED_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_MACRO */ - -/* USER CODE END EXPORTED_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** CDC Interface callback. */ -extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype - * @brief Public functions declaration. - * @{ - */ - -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -/* USER CODE BEGIN EXPORTED_FUNCTIONS */ - -/* USER CODE END EXPORTED_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CDC_IF_H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_cdc_if.h + * @version : v2.0_Cube + * @brief : Header for usbd_cdc_if.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_H__ +#define __USBD_CDC_IF_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief For Usb device. + * @{ + */ + +/** @defgroup USBD_CDC_IF USBD_CDC_IF + * @brief Usb VCP device module + * @{ + */ + +/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines + * @brief Defines. + * @{ + */ +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** CDC Interface callback. */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CDC_IF_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/usbd_conf.h b/hardware/esl_blaster/FW01/Inc/usbd_conf.h similarity index 95% rename from hardware/esl_blaster/FW/Inc/usbd_conf.h rename to hardware/esl_blaster/FW01/Inc/usbd_conf.h index 3a330b1..0e2b921 100644 --- a/hardware/esl_blaster/FW/Inc/usbd_conf.h +++ b/hardware/esl_blaster/FW01/Inc/usbd_conf.h @@ -1,175 +1,175 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usbd_conf.h - * @version : v2.0_Cube - * @brief : Header for usbd_conf.c file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include -#include "main.h" -#include "stm32f0xx.h" -#include "stm32f0xx_hal.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @{ - */ - -/** @defgroup USBD_CONF USBD_CONF - * @brief Configuration file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines - * @brief Defines for configuration of the Usb device. - * @{ - */ - -/*---------- -----------*/ -#define USBD_MAX_NUM_INTERFACES 1 -/*---------- -----------*/ -#define USBD_MAX_NUM_CONFIGURATION 1 -/*---------- -----------*/ -#define USBD_MAX_STR_DESC_SIZ 512 -/*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 -/*---------- -----------*/ -#define USBD_DEBUG_LEVEL 0 -/*---------- -----------*/ -#define USBD_SELF_POWERED 1 -/*---------- -----------*/ -#define MAX_STATIC_ALLOC_SIZE 512 - -/****************************************/ -/* #define for FS and HS identification */ -#define DEVICE_FS 0 - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* Memory management macros */ - -/** Alias for memory allocation. */ -#define USBD_malloc (uint32_t *)USBD_static_malloc - -/** Alias for memory release. */ -#define USBD_free USBD_static_free - -/** Alias for memory set. */ -#define USBD_memset /* Not used */ - -/** Alias for memory copy. */ -#define USBD_memcpy /* Not used */ - -/** Alias for delay. */ -#define USBD_Delay HAL_Delay - -/* DEBUG macros */ - -#if (USBD_DEBUG_LEVEL > 0) -#define USBD_UsrLog(...) printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_UsrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 1) - -#define USBD_ErrLog(...) printf("ERROR: ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_ErrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 2) -#define USBD_DbgLog(...) printf("DEBUG : ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_DbgLog(...) -#endif - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types - * @brief Types. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/* Exported functions -------------------------------------------------------*/ -void *USBD_static_malloc(uint32_t size); -void USBD_static_free(void *p); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CONF__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.h + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "main.h" +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_CONF USBD_CONF + * @brief Configuration file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines + * @brief Defines for configuration of the Usb device. + * @{ + */ + +/*---------- -----------*/ +#define USBD_MAX_NUM_INTERFACES 1 +/*---------- -----------*/ +#define USBD_MAX_NUM_CONFIGURATION 1 +/*---------- -----------*/ +#define USBD_MAX_STR_DESC_SIZ 512 +/*---------- -----------*/ +#define USBD_SUPPORT_USER_STRING 0 +/*---------- -----------*/ +#define USBD_DEBUG_LEVEL 0 +/*---------- -----------*/ +#define USBD_SELF_POWERED 1 +/*---------- -----------*/ +#define MAX_STATIC_ALLOC_SIZE 512 + +/****************************************/ +/* #define for FS and HS identification */ +#define DEVICE_FS 0 + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* Memory management macros */ + +/** Alias for memory allocation. */ +#define USBD_malloc (uint32_t *)USBD_static_malloc + +/** Alias for memory release. */ +#define USBD_free USBD_static_free + +/** Alias for memory set. */ +#define USBD_memset /* Not used */ + +/** Alias for memory copy. */ +#define USBD_memcpy /* Not used */ + +/** Alias for delay. */ +#define USBD_Delay HAL_Delay + +/* DEBUG macros */ + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types + * @brief Types. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ +void *USBD_static_malloc(uint32_t size); +void USBD_static_free(void *p); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CONF__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Inc/usbd_desc.h b/hardware/esl_blaster/FW01/Inc/usbd_desc.h similarity index 96% rename from hardware/esl_blaster/FW/Inc/usbd_desc.h rename to hardware/esl_blaster/FW01/Inc/usbd_desc.h index 28f5e7a..c1ca14e 100644 --- a/hardware/esl_blaster/FW/Inc/usbd_desc.h +++ b/hardware/esl_blaster/FW01/Inc/usbd_desc.h @@ -1,51 +1,51 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usbd_desc.c - * @version : v2.0_Cube - * @brief : Header for usbd_conf.c file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DESC__C__ -#define __USBD_DESC__C__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants - * @brief Constants. - * @{ - */ -#define DEVICE_ID1 (UID_BASE) -#define DEVICE_ID2 (UID_BASE + 0x4) -#define DEVICE_ID3 (UID_BASE + 0x8) - -#define USB_SIZ_STRING_SERIAL 0x1A // 10 Unicode chars - -/** Descriptor for the Usb device. */ -extern USBD_DescriptorsTypeDef FS_Desc; - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DESC__C__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC__C__ +#define __USBD_DESC__C__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants + * @brief Constants. + * @{ + */ +#define DEVICE_ID1 (UID_BASE) +#define DEVICE_ID2 (UID_BASE + 0x4) +#define DEVICE_ID3 (UID_BASE + 0x8) + +#define USB_SIZ_STRING_SERIAL 0x1A // 10 Unicode chars + +/** Descriptor for the Usb device. */ +extern USBD_DescriptorsTypeDef FS_Desc; + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DESC__C__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h similarity index 96% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index 31397d2..d937b2e 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -1,179 +1,179 @@ -/** - ****************************************************************************** - * @file usbd_cdc.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief header file for the usbd_cdc.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CDC_H -#define __USB_CDC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for usbd_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define CDC_IN_EP 0x81 /* EP1 for data IN */ -#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ -#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ - -/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ -#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ -#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ - -#define USB_CDC_CONFIG_DESC_SIZ 67 -#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE -#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE - -#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE -#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - -/** - * @} - */ -typedef struct -{ - uint32_t bitrate; - uint8_t format; - uint8_t paritytype; - uint8_t datatype; -}USBD_CDC_LineCodingTypeDef; - -typedef struct _USBD_CDC_Itf -{ - int8_t (* Init) (void); - int8_t (* DeInit) (void); - int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); - -}USBD_CDC_ItfTypeDef; - - -typedef struct -{ - uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ - uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; -} -USBD_CDC_HandleTypeDef; - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_ClassTypeDef USBD_CDC; -#define USBD_CDC_CLASS &USBD_CDC -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops); - -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length); - -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); - -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); - -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_CDC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief header file for the usbd_cdc.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for usbd_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#define CDC_IN_EP 0x81 /* EP1 for data IN */ +#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ +#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ + +#define USB_CDC_CONFIG_DESC_SIZ 67 +#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE +#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE + +#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE +#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ +typedef struct +{ + uint32_t bitrate; + uint8_t format; + uint8_t paritytype; + uint8_t datatype; +}USBD_CDC_LineCodingTypeDef; + +typedef struct _USBD_CDC_Itf +{ + int8_t (* Init) (void); + int8_t (* DeInit) (void); + int8_t (* Control) (uint8_t, uint8_t * , uint16_t); + int8_t (* Receive) (uint8_t *, uint32_t *); + +}USBD_CDC_ItfTypeDef; + + +typedef struct +{ + uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; +} +USBD_CDC_HandleTypeDef; + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); + +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length); + +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff); + +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c similarity index 96% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 06b3fc8..b2ca5f1 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -1,925 +1,925 @@ -/** - ****************************************************************************** - * @file usbd_cdc.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" -#include "usbd_desc.h" -#include "usbd_ctlreq.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_CDC - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_CDC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); - -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Variables - * @{ - */ - - -/* CDC interface class callbacks structure */ -USBD_ClassTypeDef USBD_CDC = -{ - USBD_CDC_Init, - USBD_CDC_DeInit, - USBD_CDC_Setup, - NULL, /* EP0_TxSent, */ - USBD_CDC_EP0_RxReady, - USBD_CDC_DataIn, - USBD_CDC_DataOut, - NULL, - NULL, - NULL, - USBD_CDC_GetHSCfgDesc, - USBD_CDC_GetFSCfgDesc, - USBD_CDC_GetOtherSpeedCfgDesc, - USBD_CDC_GetDeviceQualifierDescriptor, -}; - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Functions - * @{ - */ - -/** - * @brief USBD_CDC_Init - * Initialize the CDC interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - USBD_CDC_HandleTypeDef *hcdc; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_OUT_PACKET_SIZE); - - } - else - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - /* Open Command IN EP */ - USBD_LL_OpenEP(pdev, - CDC_CMD_EP, - USBD_EP_TYPE_INTR, - CDC_CMD_PACKET_SIZE); - - - pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); - - if(pdev->pClassData == NULL) - { - ret = 1; - } - else - { - hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Init physical Interface components */ - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - - /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - - - } - return ret; -} - -/** - * @brief USBD_CDC_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - - /* Open EP IN */ - USBD_LL_CloseEP(pdev, - CDC_IN_EP); - - /* Open EP OUT */ - USBD_LL_CloseEP(pdev, - CDC_OUT_EP); - - /* Open Command IN EP */ - USBD_LL_CloseEP(pdev, - CDC_CMD_EP); - - - /* DeInit physical Interface components */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; - } - - return ret; -} - -/** - * @brief USBD_CDC_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - static uint8_t ifalt = 0; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - if (req->wLength) - { - if (req->bmRequest & 0x80) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)hcdc->data, - req->wLength); - USBD_CtlSendData (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - else - { - hcdc->CmdOpCode = req->bRequest; - hcdc->CmdLength = req->wLength; - - USBD_CtlPrepareRx (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - - } - else - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t*)req, - 0); - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &ifalt, - 1); - break; - - case USB_REQ_SET_INTERFACE : - break; - } - - default: - break; - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - - hcdc->TxState = 0; - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - - - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, - (uint8_t *)hcdc->data, - hcdc->CmdLength); - hcdc->CmdOpCode = 0xFF; - - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_GetFSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; -} - -/** - * @brief USBD_CDC_GetHSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; -} - -/** - * @brief USBD_CDC_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; -} - -/** -* @brief DeviceQualifierDescriptor -* return Device Qualifier descriptor -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) -{ - *length = sizeof (USBD_CDC_DeviceQualifierDesc); - return USBD_CDC_DeviceQualifierDesc; -} - -/** -* @brief USBD_CDC_RegisterInterface - * @param pdev: device instance - * @param fops: CD Interface callback - * @retval status - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops) -{ - uint8_t ret = USBD_FAIL; - - if(fops != NULL) - { - pdev->pUserData= fops; - ret = USBD_OK; - } - - return ret; -} - -/** - * @brief USBD_CDC_SetTxBuffer - * @param pdev: device instance - * @param pbuff: Tx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; - - return USBD_OK; -} - - -/** - * @brief USBD_CDC_SetRxBuffer - * @param pdev: device instance - * @param pbuff: Rx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->RxBuffer = pbuff; - - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - if(hcdc->TxState == 0) - { - /* Tx Transfer in progress */ - hcdc->TxState = 1; - - /* Transmit next packet */ - USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - - return USBD_OK; - } - else - { - return USBD_BUSY; - } - } - else - { - return USBD_FAIL; - } -} - - -/** - * @brief USBD_CDC_ReceivePacket - * prepare OUT Endpoint for reception - * @param pdev: device instance - * @retval status - */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Suspend or Resume USB Out process */ - if(pdev->pClassData != NULL) - { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_cdc.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" +#include "usbd_desc.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ + + +/* CDC interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_GetHSCfgDesc, + USBD_CDC_GetFSCfgDesc, + USBD_CDC_GetOtherSpeedCfgDesc, + USBD_CDC_GetDeviceQualifierDescriptor, +}; + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_Init + * Initialize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + USBD_CDC_HandleTypeDef *hcdc; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); + + } + else + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + /* Open Command IN EP */ + USBD_LL_OpenEP(pdev, + CDC_CMD_EP, + USBD_EP_TYPE_INTR, + CDC_CMD_PACKET_SIZE); + + + pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); + + if(pdev->pClassData == NULL) + { + ret = 1; + } + else + { + hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init Xfer states */ + hcdc->TxState =0; + hcdc->RxState =0; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + + + } + return ret; +} + +/** + * @brief USBD_CDC_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + + /* Open EP IN */ + USBD_LL_CloseEP(pdev, + CDC_IN_EP); + + /* Open EP OUT */ + USBD_LL_CloseEP(pdev, + CDC_OUT_EP); + + /* Open Command IN EP */ + USBD_LL_CloseEP(pdev, + CDC_CMD_EP); + + + /* DeInit physical Interface components */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return ret; +} + +/** + * @brief USBD_CDC_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + static uint8_t ifalt = 0; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength) + { + if (req->bmRequest & 0x80) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + USBD_CtlSendData (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = req->wLength; + + USBD_CtlPrepareRx (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t*)req, + 0); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + &ifalt, + 1); + break; + + case USB_REQ_SET_INTERFACE : + break; + } + + default: + break; + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if(pdev->pClassData != NULL) + { + + hcdc->TxState = 0; + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + + + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + (uint8_t *)hcdc->data, + hcdc->CmdLength); + hcdc->CmdOpCode = 0xFF; + + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; +} + +/** + * @brief USBD_CDC_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; +} + +/** + * @brief USBD_CDC_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; +} + +/** +* @brief DeviceQualifierDescriptor +* return Device Qualifier descriptor +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) +{ + *length = sizeof (USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; +} + +/** +* @brief USBD_CDC_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + uint8_t ret = USBD_FAIL; + + if(fops != NULL) + { + pdev->pUserData= fops; + ret = USBD_OK; + } + + return ret; +} + +/** + * @brief USBD_CDC_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return USBD_OK; +} + + +/** + * @brief USBD_CDC_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return USBD_OK; +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if(pdev->pClassData != NULL) + { + if(hcdc->TxState == 0) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1; + + /* Transmit next packet */ + USBD_LL_Transmit(pdev, + CDC_IN_EP, + hcdc->TxBuffer, + hcdc->TxLength); + + return USBD_OK; + } + else + { + return USBD_BUSY; + } + } + else + { + return USBD_FAIL; + } +} + + +/** + * @brief USBD_CDC_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Suspend or Resume USB Out process */ + if(pdev->pClassData != NULL) + { + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h similarity index 97% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h index 6550cd7..013a5c1 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -1,167 +1,167 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for usbd_core.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" -#include "usbd_def.h" -#include "usbd_ioreq.h" -#include "usbd_ctlreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ -#define USBD_SOF USBD_LL_SOF -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); - -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); - -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); - -/* USBD Low Level Driver */ -USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps); - -USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); -USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -void USBD_LL_Delay (uint32_t Delay); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for usbd_core.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "usbd_def.h" +#include "usbd_ioreq.h" +#include "usbd_ctlreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +#define USBD_SOF USBD_LL_SOF +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); + +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); + +/* USBD Low Level Driver */ +USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); +USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +void USBD_LL_Delay (uint32_t Delay); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h similarity index 95% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h index 66380fd..bf88252 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -1,113 +1,113 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_REQUEST_H -#define __USB_REQUEST_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_req.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - - -void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - -void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); - -void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_REQUEST_H */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_REQUEST_H +#define __USB_REQUEST_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_req.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + + +void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + +void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); + +void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_REQUEST_H */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h similarity index 97% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index 969e324..8fbe81e 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -1,330 +1,330 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief General defines for the usb device library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 -#define USB_LEN_LANGID_STR_DESC 0x04 -#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_BOS 0x0F - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -#define USB_DEVICE_CAPABITY_TYPE 0x10 - -#define USB_HS_MAX_PACKET_SIZE 512 -#define USB_FS_MAX_PACKET_SIZE 64 -#define USB_MAX_EP0_SIZE 64 - -/* Device Status */ -#define USBD_STATE_DEFAULT 1 -#define USBD_STATE_ADDRESSED 2 -#define USBD_STATE_CONFIGURED 3 -#define USBD_STATE_SUSPENDED 4 - - -/* EP0 State */ -#define USBD_EP0_IDLE 0 -#define USBD_EP0_SETUP 1 -#define USBD_EP0_DATA_IN 2 -#define USBD_EP0_DATA_OUT 3 -#define USBD_EP0_STATUS_IN 4 -#define USBD_EP0_STATUS_OUT 5 -#define USBD_EP0_STALL 6 - -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 - - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ - -typedef struct usb_setup_req -{ - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -}USBD_SetupReqTypedef; - -struct _USBD_HandleTypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); - uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); - uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); - uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - - uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); - uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); -#if (USBD_SUPPORT_USER_STRING == 1) - uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); -#endif - -} USBD_ClassTypeDef; - -/* Following USB Device Speed */ -typedef enum -{ - USBD_SPEED_HIGH = 0, - USBD_SPEED_FULL = 1, - USBD_SPEED_LOW = 2, -}USBD_SpeedTypeDef; - -/* Following USB Device status */ -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_StatusTypeDef; - -/* USB Device descriptors structure */ -typedef struct -{ - uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#if (USBD_LPM_ENABLED == 1) - uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#endif -} USBD_DescriptorsTypeDef; - -/* USB Device handle structure */ -typedef struct -{ - uint32_t status; - uint32_t total_length; - uint32_t rem_length; - uint32_t maxpacket; -} USBD_EndpointTypeDef; - -/* USB Device handle structure */ -typedef struct _USBD_HandleTypeDef -{ - uint8_t id; - uint32_t dev_config; - uint32_t dev_default_config; - uint32_t dev_config_status; - USBD_SpeedTypeDef dev_speed; - USBD_EndpointTypeDef ep_in[15]; - USBD_EndpointTypeDef ep_out[15]; - uint32_t ep0_state; - uint32_t ep0_data_len; - uint8_t dev_state; - uint8_t dev_old_state; - uint8_t dev_address; - uint8_t dev_connection_status; - uint8_t dev_test_mode; - uint32_t dev_remote_wakeup; - - USBD_SetupReqTypedef request; - USBD_DescriptorsTypeDef *pDesc; - USBD_ClassTypeDef *pClass; - void *pClassData; - void *pUserData; - void *pData; -} USBD_HandleTypeDef; - -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ - -#if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN -#else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ -#endif /* __GNUC__ */ - - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief General defines for the usb device library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0 +#endif + + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_OTG_DESC 0x03 +#define USB_LEN_LANGID_STR_DESC 0x04 +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 +#define USB_DESC_TYPE_BOS 0x0F + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +#define USB_DEVICE_CAPABITY_TYPE 0x10 + +#define USB_HS_MAX_PACKET_SIZE 512 +#define USB_FS_MAX_PACKET_SIZE 64 +#define USB_MAX_EP0_SIZE 64 + +/* Device Status */ +#define USBD_STATE_DEFAULT 1 +#define USBD_STATE_ADDRESSED 2 +#define USBD_STATE_CONFIGURED 3 +#define USBD_STATE_SUSPENDED 4 + + +/* EP0 State */ +#define USBD_EP0_IDLE 0 +#define USBD_EP0_SETUP 1 +#define USBD_EP0_DATA_IN 2 +#define USBD_EP0_DATA_OUT 3 +#define USBD_EP0_STATUS_IN 4 +#define USBD_EP0_STATUS_OUT 5 +#define USBD_EP0_STALL 6 + +#define USBD_EP_TYPE_CTRL 0 +#define USBD_EP_TYPE_ISOC 1 +#define USBD_EP_TYPE_BULK 2 +#define USBD_EP_TYPE_INTR 3 + + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ + +typedef struct usb_setup_req +{ + + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +}USBD_SetupReqTypedef; + +struct _USBD_HandleTypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); + uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); + uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); + uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + + uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); +#if (USBD_SUPPORT_USER_STRING == 1) + uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); +#endif + +} USBD_ClassTypeDef; + +/* Following USB Device Speed */ +typedef enum +{ + USBD_SPEED_HIGH = 0, + USBD_SPEED_FULL = 1, + USBD_SPEED_LOW = 2, +}USBD_SpeedTypeDef; + +/* Following USB Device status */ +typedef enum { + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_StatusTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); +#if (USBD_LPM_ENABLED == 1) + uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); +#endif +} USBD_DescriptorsTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; +} USBD_EndpointTypeDef; + +/* USB Device handle structure */ +typedef struct _USBD_HandleTypeDef +{ + uint8_t id; + uint32_t dev_config; + uint32_t dev_default_config; + uint32_t dev_config_status; + USBD_SpeedTypeDef dev_speed; + USBD_EndpointTypeDef ep_in[15]; + USBD_EndpointTypeDef ep_out[15]; + uint32_t ep0_state; + uint32_t ep0_data_len; + uint8_t dev_state; + uint8_t dev_old_state; + uint8_t dev_address; + uint8_t dev_connection_status; + uint8_t dev_test_mode; + uint32_t dev_remote_wakeup; + + USBD_SetupReqTypedef request; + USBD_DescriptorsTypeDef *pDesc; + USBD_ClassTypeDef *pClass; + void *pClassData; + void *pUserData; + void *pData; +} USBD_HandleTypeDef; + +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) +#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN +#else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ +#endif /* __GNUC__ */ + + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h similarity index 95% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h index dbf8ca1..b476307 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -1,128 +1,128 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_IOREQ_H -#define __USBD_IOREQ_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *buf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); - -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , - uint8_t epnum); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_IOREQ_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_IOREQ_H +#define __USBD_IOREQ_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *buf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); + +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , + uint8_t epnum); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_IOREQ_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c similarity index 95% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c index 86fc2de..0158829 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -1,565 +1,565 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initializes the device stack and load the class driver -* @param pdev: device instance -* @param pdesc: Descriptor structure address -* @param id: Low level core index -* @retval None -*/ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) -{ - /* Check whether the USB Host handle is valid */ - if(pdev == NULL) - { - USBD_ErrLog("Invalid Device handle"); - return USBD_FAIL; - } - - /* Unlink previous class*/ - if(pdev->pClass != NULL) - { - pdev->pClass = NULL; - } - - /* Assign USBD Descriptors */ - if(pdesc != NULL) - { - pdev->pDesc = pdesc; - } - - /* Set Device initial State */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->id = id; - /* Initialize low level driver */ - USBD_LL_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_DeInit -* Re-Initialize th device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) -{ - /* Set Default State */ - pdev->dev_state = USBD_STATE_DEFAULT; - - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - /* Initialize low level driver */ - USBD_LL_DeInit(pdev); - - return USBD_OK; -} - - -/** - * @brief USBD_RegisterClass - * Link class driver to Device Core. - * @param pDevice : Device Handle - * @param pclass: Class handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) -{ - USBD_StatusTypeDef status = USBD_OK; - if(pclass != 0) - { - /* link the class to the USB Device handle */ - pdev->pClass = pclass; - status = USBD_OK; - } - else - { - USBD_ErrLog("Invalid Class handle"); - status = USBD_FAIL; - } - - return status; -} - -/** - * @brief USBD_Start - * Start the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) -{ - - /* Start the low level driver */ - USBD_LL_Start(pdev); - - return USBD_OK; -} - -/** - * @brief USBD_Stop - * Stop the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - - -/** -* @brief USBD_SetClassConfig -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - USBD_StatusTypeDef ret = USBD_FAIL; - - if(pdev->pClass != NULL) - { - /* Set configuration and Start the Class*/ - if(pdev->pClass->Init(pdev, cfgidx) == 0) - { - ret = USBD_OK; - } - } - return ret; -} - -/** -* @brief USBD_ClrClassConfig -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_StatusTypeDef -*/ -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - /* Clear configuration and De-initialize the Class process*/ - pdev->pClass->DeInit(pdev, cfgidx); - return USBD_OK; -} - - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) -{ - - USBD_ParseSetupRequest(&pdev->request, psetup); - - pdev->ep0_state = USBD_EP0_SETUP; - pdev->ep0_data_len = pdev->request.wLength; - - switch (pdev->request.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &pdev->request); - break; - - default: - USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data OUT stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_out[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_OUT) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueRx (pdev, - pdata, - MIN(pep->rem_length ,pep->maxpacket)); - } - else - { - if((pdev->pClass->EP0_RxReady != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->pClass->DataOut != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_in[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_IN) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueSendData (pdev, - pdata, - pep->rem_length); - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((pep->total_length % pep->maxpacket == 0) && - (pep->total_length >= pep->maxpacket) && - (pep->total_length < pdev->ep0_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - pdev->ep0_data_len = 0; - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { - if((pdev->pClass->EP0_TxSent != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev_test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev_test_mode = 0; - } - } - else if((pdev->pClass->DataIn != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataIn(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) -{ - /* Open EP0 OUT */ - USBD_LL_OpenEP(pdev, - 0x00, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - - /* Open EP0 IN */ - USBD_LL_OpenEP(pdev, - 0x80, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - /* Upon Reset call user call back */ - pdev->dev_state = USBD_STATE_DEFAULT; - - if (pdev->pClassData) - pdev->pClass->DeInit(pdev, pdev->dev_config); - - - return USBD_OK; -} - - - - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) -{ - pdev->dev_speed = speed; - return USBD_OK; -} - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) -{ - pdev->dev_old_state = pdev->dev_state; - pdev->dev_state = USBD_STATE_SUSPENDED; - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) -{ - pdev->dev_state = pdev->dev_old_state; - return USBD_OK; -} - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) -{ - if(pdev->dev_state == USBD_STATE_CONFIGURED) - { - if(pdev->pClass->SOF != NULL) - { - pdev->pClass->SOF(pdev); - } - } - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->pClass->DeInit(pdev, pdev->dev_config); - - return USBD_OK; -} -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initializes the device stack and load the class driver +* @param pdev: device instance +* @param pdesc: Descriptor structure address +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + /* Check whether the USB Host handle is valid */ + if(pdev == NULL) + { + USBD_ErrLog("Invalid Device handle"); + return USBD_FAIL; + } + + /* Unlink previous class*/ + if(pdev->pClass != NULL) + { + pdev->pClass = NULL; + } + + /* Assign USBD Descriptors */ + if(pdesc != NULL) + { + pdev->pDesc = pdesc; + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->id = id; + /* Initialize low level driver */ + USBD_LL_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_DeInit +* Re-Initialize th device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) +{ + /* Set Default State */ + pdev->dev_state = USBD_STATE_DEFAULT; + + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + /* Initialize low level driver */ + USBD_LL_DeInit(pdev); + + return USBD_OK; +} + + +/** + * @brief USBD_RegisterClass + * Link class driver to Device Core. + * @param pDevice : Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + USBD_StatusTypeDef status = USBD_OK; + if(pclass != 0) + { + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + status = USBD_OK; + } + else + { + USBD_ErrLog("Invalid Class handle"); + status = USBD_FAIL; + } + + return status; +} + +/** + * @brief USBD_Start + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) +{ + + /* Start the low level driver */ + USBD_LL_Start(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_Stop + * Stop the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + + +/** +* @brief USBD_SetClassConfig +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_FAIL; + + if(pdev->pClass != NULL) + { + /* Set configuration and Start the Class*/ + if(pdev->pClass->Init(pdev, cfgidx) == 0) + { + ret = USBD_OK; + } + } + return ret; +} + +/** +* @brief USBD_ClrClassConfig +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Clear configuration and De-initialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + return USBD_OK; +} + + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + + USBD_ParseSetupRequest(&pdev->request, psetup); + + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data OUT stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_out[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_OUT) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueRx (pdev, + pdata, + MIN(pep->rem_length ,pep->maxpacket)); + } + else + { + if((pdev->pClass->EP0_RxReady != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + } + else if((pdev->pClass->DataOut != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataOut(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_in[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_IN) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueSendData (pdev, + pdata, + pep->rem_length); + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + NULL, + 0); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((pep->total_length % pep->maxpacket == 0) && + (pep->total_length >= pep->maxpacket) && + (pep->total_length < pdev->ep0_data_len )) + { + + USBD_CtlContinueSendData(pdev , NULL, 0); + pdev->ep0_data_len = 0; + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + NULL, + 0); + } + else + { + if((pdev->pClass->EP0_TxSent != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_TxSent(pdev); + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev_test_mode == 1) + { + USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0; + } + } + else if((pdev->pClass->DataIn != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataIn(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, + 0x00, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, + 0x80, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + + if (pdev->pClassData) + pdev->pClass->DeInit(pdev, pdev->dev_config); + + + return USBD_OK; +} + + + + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + return USBD_OK; +} + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + pdev->dev_state = pdev->dev_old_state; + return USBD_OK; +} + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + if(pdev->dev_state == USBD_STATE_CONFIGURED) + { + if(pdev->pClass->SOF != NULL) + { + pdev->pClass->SOF(pdev); + } + } + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->pClass->DeInit(pdev, pdev->dev_config); + + return USBD_OK; +} +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c similarity index 96% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c index b00c129..3498604 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -1,596 +1,596 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ctlreq.h" -#include "usbd_ioreq.h" - -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetAddress(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetStatus(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_StatusTypeDef ret = USBD_OK; - - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev, req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev, req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev, req); - break; - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev, req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev, req); - break; - - default: - USBD_CtlError(pdev, req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_StatusTypeDef ret = USBD_OK; - - switch (pdev->dev_state) { - case USBD_STATE_CONFIGURED: - if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) { - pdev->pClass->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - USBD_CtlSendStatus(pdev); - } else { - USBD_CtlError(pdev, req); - } - break; - - default: - USBD_CtlError(pdev, req); - - break; - } - return USBD_OK; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - - uint8_t ep_addr; - USBD_StatusTypeDef ret = USBD_OK; - USBD_EndpointTypeDef *pep; - ep_addr = LOBYTE(req->wIndex); - - /* Check if it is a class request */ - if ((req->bmRequest & 0x60) == 0x20) - { - pdev->pClass->Setup (pdev, req); - - return USBD_OK; - } - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - - } - } - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_ClearStallEP(pdev , ep_addr); - pdev->pClass->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ - &pdev->ep_out[ep_addr & 0x7F]; - if(USBD_LL_IsStallEP(pdev, ep_addr)) - { - pep->status = 0x0001; - } - else - { - pep->status = 0x0000; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&pep->status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) { - uint16_t len; - uint8_t *pbuf; - - switch (req->wValue >> 8) - { -#if (USBD_LPM_ENABLED == 1) - case USB_DESC_TYPE_BOS: - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - break; -#endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - break; - - case USB_DESC_TYPE_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - else - { - pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - break; - - default: -#if (USBD_SUPPORT_USER_STRING == 1) - pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlError(pdev , req); - } else { - pdev->dev_address = dev_addr; - USBD_LL_SetUSBAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - pdev->dev_state = USBD_STATE_ADDRESSED; - else - pdev->dev_state = USBD_STATE_DEFAULT; - } - } else { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if (cfgidx) - { - pdev->dev_config = cfgidx; - pdev->dev_state = USBD_STATE_CONFIGURED; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USBD_STATE_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - pdev->dev_config = cfgidx; - USBD_ClrClassConfig(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev_config) - { - /* Clear old configuration */ - USBD_ClrClassConfig(pdev , pdev->dev_config); - - /* set new configuration */ - pdev->dev_config = cfgidx; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - if (req->wLength != 1) { - USBD_CtlError(pdev , req); - } else { - switch (pdev->dev_state ) { - case USBD_STATE_ADDRESSED: - pdev->dev_default_config = 0; - USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_default_config, 1); - break; - - case USBD_STATE_CONFIGURED: - USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_config, 1); - break; - - default: - USBD_CtlError(pdev , req); - - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - switch (pdev->dev_state) { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - - #if ( USBD_SELF_POWERED == 1) - pdev->dev_config_status = USB_CONFIG_SELF_POWERED; - #else - pdev->dev_config_status = 0; - #endif - - if (pdev->dev_remote_wakeup) - pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - - USBD_CtlSendData (pdev, (uint8_t *)& pdev->dev_config_status, 2); - break; - - default: - USBD_CtlError(pdev, req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { - pdev->dev_remote_wakeup = 1; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - switch (pdev->dev_state) { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { - pdev->dev_remote_wakeup = 0; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { - req->bmRequest = *(uint8_t *) (pdata); - req->bRequest = *(uint8_t *) (pdata + 1); - req->wValue = SWAPBYTE (pdata + 2); - req->wIndex = SWAPBYTE (pdata + 4); - req->wLength = SWAPBYTE (pdata + 6); -} - -void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_LL_StallEP(pdev , 0x80); - USBD_LL_StallEP(pdev , 0); -} +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ctlreq.h" +#include "usbd_ioreq.h" + +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetAddress(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetStatus(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor (pdev, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (pdev, req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (pdev, req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (pdev, req); + break; + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (pdev, req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (pdev, req); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; + + switch (pdev->dev_state) { + case USBD_STATE_CONFIGURED: + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) { + pdev->pClass->Setup (pdev, req); + + if((req->wLength == 0)&& (ret == USBD_OK)) + USBD_CtlSendStatus(pdev); + } else { + USBD_CtlError(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + + break; + } + return USBD_OK; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) +{ + + uint8_t ep_addr; + USBD_StatusTypeDef ret = USBD_OK; + USBD_EndpointTypeDef *pep; + ep_addr = LOBYTE(req->wIndex); + + /* Check if it is a class request */ + if ((req->bmRequest & 0x60) == 0x20) + { + pdev->pClass->Setup (pdev, req); + + return USBD_OK; + } + + switch (req->bRequest) + { + + case USB_REQ_SET_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + + } + } + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_ClearStallEP(pdev , ep_addr); + pdev->pClass->Setup (pdev, req); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ + &pdev->ep_out[ep_addr & 0x7F]; + if(USBD_LL_IsStallEP(pdev, ep_addr)) + { + pep->status = 0x0001; + } + else + { + pep->status = 0x0000; + } + + USBD_CtlSendData (pdev, + (uint8_t *)&pep->status, + 2); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + default: + break; + } + return ret; +} +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) { + uint16_t len; + uint8_t *pbuf; + + switch (req->wValue >> 8) + { +#if (USBD_LPM_ENABLED == 1) + case USB_DESC_TYPE_BOS: + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + break; + + default: +#if (USBD_SUPPORT_USER_STRING == 1) + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); + break; +#else + USBD_CtlError(pdev , req); + return; +#endif + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + default: + USBD_CtlError(pdev , req); + return; + } + + if((len != 0)&& (req->wLength != 0)) + { + + len = MIN(len , req->wLength); + + USBD_CtlSendData (pdev, + pbuf, + len); + } + +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (pdev->dev_state == USBD_STATE_CONFIGURED) { + USBD_CtlError(pdev , req); + } else { + pdev->dev_address = dev_addr; + USBD_LL_SetUSBAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0) + pdev->dev_state = USBD_STATE_ADDRESSED; + else + pdev->dev_state = USBD_STATE_DEFAULT; + } + } else { + USBD_CtlError(pdev , req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if (cfgidx) + { + pdev->dev_config = cfgidx; + pdev->dev_state = USBD_STATE_CONFIGURED; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + USBD_ClrClassConfig(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + USBD_ClrClassConfig(pdev , pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + if (req->wLength != 1) { + USBD_CtlError(pdev , req); + } else { + switch (pdev->dev_state ) { + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0; + USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_default_config, 1); + break; + + case USBD_STATE_CONFIGURED: + USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_config, 1); + break; + + default: + USBD_CtlError(pdev , req); + + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + switch (pdev->dev_state) { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + #if ( USBD_SELF_POWERED == 1) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + #else + pdev->dev_config_status = 0; + #endif + + if (pdev->dev_remote_wakeup) + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + + USBD_CtlSendData (pdev, (uint8_t *)& pdev->dev_config_status, 2); + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev_remote_wakeup = 1; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + switch (pdev->dev_state) { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev_remote_wakeup = 0; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { + req->bmRequest = *(uint8_t *) (pdata); + req->bRequest = *(uint8_t *) (pdata + 1); + req->wValue = SWAPBYTE (pdata + 2); + req->wIndex = SWAPBYTE (pdata + 4); + req->wLength = SWAPBYTE (pdata + 6); +} + +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_LL_StallEP(pdev , 0x80); + USBD_LL_StallEP(pdev , 0); +} diff --git a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c similarity index 95% rename from hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c rename to hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c index d66d777..093afad 100644 --- a/hardware/esl_blaster/FW/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +++ b/hardware/esl_blaster/FW01/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -1,236 +1,236 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_IN; - pdev->ep_in[0].total_length = len; - pdev->ep_in[0].rem_length = len; - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Start the next transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_OUT; - pdev->ep_out[0].total_length = len; - pdev->ep_out[0].rem_length = len; - /* Start the transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - return USBD_OK; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) -{ - - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_IN; - - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, NULL, 0); - - return USBD_OK; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_OUT; - - /* Start the transfer */ - USBD_LL_PrepareReceive ( pdev, - 0, - NULL, - 0); - - return USBD_OK; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) -{ - return USBD_LL_GetRxDataSize(pdev, ep_addr); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + pdev->ep_in[0].total_length = len; + pdev->ep_in[0].rem_length = len; + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Start the next transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + pdev->ep_out[0].total_length = len; + pdev->ep_out[0].rem_length = len; + /* Start the transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + return USBD_OK; +} +/** +* @brief USBD_CtlSendStatus +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) +{ + + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, NULL, 0); + + return USBD_OK; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + + /* Start the transfer */ + USBD_LL_PrepareReceive ( pdev, + 0, + NULL, + 0); + + return USBD_OK; +} + + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval Rx Data blength +*/ +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) +{ + return USBD_LL_GetRxDataSize(pdev, ep_addr); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/ESLBlasterB0.bin b/hardware/esl_blaster/FW01/Release/ESLBlaster.bin similarity index 100% rename from hardware/esl_blaster/FW/ESLBlasterB0.bin rename to hardware/esl_blaster/FW01/Release/ESLBlaster.bin diff --git a/hardware/esl_blaster/FW01/Release/ESLBlaster.elf b/hardware/esl_blaster/FW01/Release/ESLBlaster.elf new file mode 100644 index 0000000000000000000000000000000000000000..1764200a27e83bb31a812a4f9db8216a364032ca GIT binary patch literal 144920 zcmeIZdwg5Pxh_0Qk{w@?*p36pmw+re!58BA5<(y$l`TiHty~=20mn(VB-=_P;@HBL z*`|aYlWx^%f+k|d^nbgYOGx-gHW%*VH>O2?Rv zCCz6hW`Hc4&ERq-|4o5PN=haE;F-dWNQxZgP#pOw0T^7I!C10JzBofid8RE@jBK!- zNt5Ml3(9YSj2?Vy0M+t@#YZq87!V8y1_T3w0l|P^KrkQ}5DW+g1OtKr!GK^uFd!HZ z3HG$*$)ZI1CAP!+j_arHu93BL%ABA=3>$pBo@8)S6Pdj*;S^#~X{>`zYXcbCGyaZ40=4l&GJ9wH}juJe5 z6n%j{0lD(-q)9zmui%P@bYBc%0j(8~^3*8s>FY_-Ov1bk& zm^Avv#ft^ISZu5-#zz0)ykuhL0%omYqq*mqDf0-%pds6vS&(kab}>_I?1PwY^!Cdn zfi08Hs)JOj%65^xw++nXA7(`}&+bSWV%If1X78vSne#LDU9sW=I-S(CCrS{11S6@u?vJw{lMT8Yfmi_jOs)P1viw@X>mUT%( z_VtdV#xK`ws$N$k?Ylkl9@>1=c+)*oX3w_%h-H|cvwqu_=6lY19lO&utGz11W)EBM zv_0us<;e50gC}hb-eY=pa$BU->R4Ij>hm^u_v#-!QEFYbvd{GspkuoGfofO&#PwH_ z>H2|knbmQ|CCyLsX0!LKJt4dO`_@V;+xtbx;ay{Y-li*kIi&Y)WGn1Pte@FRtxwn; z-UfTN^<`_jJ=>;tIlN8weKu*4RGM{ahnM7Ud1cuSm(BYV+l|cO%}cF8iD#@;Hk<1x zbiVFAVx47s9cA0>*)<~}ljBKWjr}^?lkOp3wpG7RKlBWGp3g_?N$*Pg9P7_m#?Aj? zJz|^3_RRh)>Dd|<4o0tA@odeM&`kVI4oOee*dMng-FjbCnjMJhX7@(f!EDqvT_s$Nq&GBrD6*SsBB(fz@F~*Rc{Qysh28Y@7RX z)IV&vu|D(%ORVbXdRBTTPwCC)T3lXMG%I9bMOCaon$65#_UHJ|_|Ld<-ED5EBEM=| z%@<({ORb7kVSbp~{Kg4sd4AO(q*jY$F7UqDggJq~wFM?`P1Dp0`kU4u=jSgv*CLsz z?sF~htRo+jHS?=2y3uDZ{UR!vz966dRV*fXTg|)Mf+nWZ+jcjR4}NZ0$BwR-O0z?h zl2C>fr-h$f6kD{lQbKK%OO{Bt(DF*l-=aFx1@v{rVK&!ucI%w!*3a3YyhAK?er&!W zXX~5_Yk~i>43Gbu>pj0}n}z${Rjt1_AeFLkAi_#lhIFN^A$@6kX!gK!Oz(Zd-d>wM z_~ZI?>yPV;ZJ6o7XTHKpS?DK`4n$uT-Vo7w8!gA%3I=}7nv6rnp!pc1x&8E@RPeAZ zH)t6cVmdG7vqFQ_3 ztk1H3vw>_qJ1Kt`^1sUSpO}=t1Nl37{+>zs4KEQO`pcOBlP^EYJKawhlNU^wYQzwhDwp6Ef&;Kqh5 z>xg-;wA#9s*S{^gIt8|-NGGKVvXv7&GpVKP(bDx?6YZR{FWyd-^>c&L?B~FT&O0G% z;C(RfqI?>&JHrz#z?h(Ix1(*ggtp0}RRziXt0Z&LiZb4cf`MIp4BfTqgYz45ts|Bp zso6TGA={SD8IZihQ_f)F@&YT3Q`V&3P~Ewxq4262$WvxQa@|#u>8RUyRozn?vaP9C z)taHy`tKj=Os78_v1ep377WH>BY1xG%~&iW6?l6r7JLZL&REP~U@RFAgFHAAi+vMw zGh;g7wpc84xZyA>x#R5C!l~BxSY94hB+TZc#;t_~)*Sz_j5h!0<|ej%y@d7Ql?bJ! zf^97azrsqY!)*hsWOgVQ{!V0*iLos=vzCQrN2DwoXN<4R?eS%PmB?MZDZ330hYH2_CdgE4gL)RO>DEl$$?r zh|lZJTJvBjMyd!SWuDX%%W|`oX2QX%TAK^ov#zpDoXms-PeQHJQES#!wWgz1JPEa? zD788f5!(@8Y0TB}rmqX%N90x8>>EOQ}fAB@&?Yb zPmK4ic){LTo1e3!r08^W>W~~W77ZO9(%lQ+wFKW{Yjbz8YGZ0etRjs^$01|R;HG$t z@bR&vmE=vq@x_#aWV1!+ple1ErPE%BDkf`&yI~`BhJ++-Vllyl&@836g8&7K5nApOlf7kBK zs@;TMc1E#sh1}63@2aYa_T0!)7sM7U82B6eQBG%0KJT45sJ4Cv)uPc>N9cXybfuOh zC2yX7l3Si1HNf)Kqxrt^mK+_l;r~H1{7j7-6f?-rbciGAY->S|RUTEVv7kIw&IbL< z7%LxE*WkP3>$~GHE1iAzE!M`zbtX%PcS*Bn`)THr2hQ|Qi~uv|`q?d|Vab~|nD5B7 z<~!Q(P|Tf(8RbW|TGFj&*fGUk$$Y7xz^_|u@fX9JS!pCRu`W-?Ov)^1;Ik<=_)hc? zkLfhCQ(+yuTdB=zfPG8w|HZ5dM}LJrW@gHJB6iJA`uV5ONcC2><)om=1f>xxI-vn=_aepH<0xR-Hu8 zPW>10B6C=(T9*QAlNgQL zyDT-2=JUfHZ*?$pT4x$7u9Qrfe(8>x{#Bb^uBkYEHt(&Db8JT5UiO@^vN9XdV_vAl zE3Yq~7>lZm13TDI+q&fYPO5puJjUD^Zmc@qHo}a?cKBd>?RMjmc_pVGKuoz1pSfSI z(_=4H5>f55f^f%8?0-gob@)TJAn#}FpK}g>eG&WdrXp`_Y)`BN^Z9sN(SizPAGeb4 z8g2@1i#&iCcOgD!vx8DZDlH7D?aBSd%W-?Mt$Sj{3#!nQmXK819#-{=(C#5tqU;10 zVr5#$d0!n_#d|Wtc+fbH_vMCQD5{o{dpj%M+v0d{(-L}HzB z_}}fT>~{Oe@b(uCtk$CQ9&gJ-%vg2S;;l6wY->tlCm%bfq_HEYEof_dsZM8YYm)Q! zDtW`2ykiD-@@q<&8A&rw)|wBr{d1jUJBZ3dpQc!%1~8rX@g zN}0W=^FbwjEJ?2OyWGC+#eC(YHhN@}ote)BYj2kRIRj^AllSPlp~F={YWw%j+&XBp z&$6=6k0VusXOkT#b%UGiXM)L9d4qXLy(c!=c?z2EozV|Ij6I${Xo8;}ZQF_c)zj;b zVFesAewBM_-r!Ku&@_3q-sfhefiNpD;Ra*Y6^pkK{5-&S>_bLbBkWyL+d{WN&3Z47s)wTb!5&_F0cwA%t;kGuKa9FJY3jCgKD~*~ zInQ*+HUIH)q2)cCIazpT^u0}VW(r0N&Cje4;=W}5?Iy3SiCLa$xi6a7pVbB-D~OH#Zrtq69$W_B%f^9G8hz&Sn&@?G?_jYnHul@`Qr~kvYD1}eYqTK+y`yYD@_Thn%5yG z)jL>o>oKkUoBzfa_RgyH*(xmnfVf!spibke0eiI!bVn9&IU$U zs`1DgmP>^O^ga8I@_ayf=1UK7E9r47(xrh9)YwmPpL~$c8?j5cP&|U~KjFDT zd!?z#87JlQhZ{Toq6({#l}rms=Iy;lgLzZ++vpDUZALO0DXZ~M(e1rEf`5%NCOM2= zx}(g*{dMLr-Oi4WJ$YGLsCTrwnE9Y9sWR6^_pfw+30;2oO1ckOa7JlmrAeW$n)fnR zaG;Uyj&!EWu$ejhHAR{cdI-{;t;Rc^S|2M)2_-c=y?)4B!1gZ-LL-KIGisTnW6WmJ z2U(qe*+NVyHN8cXejDjDMP~$Q+{3YlaNqmYwbE$Ir5&*LQR6dfX%|K5kBupdK58{q zz1MoyyMGy-aHwT|?4zc#)BzWEvbTgxrD@@FgRCSq>>8l(J_lX8(w}(7Vx# z%+j%%`atFNTWFpHAuGj3k*wW+ky5h7zKbaqy;-)p`Qq11LHO0%7n2y-k2JEPxgi5M z$s5FlL+k6f6O?T|b&=|{TI5>n7bzu6tQX&k2CHV?@m%W= zlXD)1?nhC{^kI}08+adHiTi`>DcjMOoW`B-uQo2B+*ey?E(&v$IV@vVa$U%Acl{qQCh1nGG$VxfQ@Bsf3~jX>u$eHndoJiB#mt0~*{Ion zL{9(k;`ykYI(qT1ID<@w|7D_{Y{rU-Ibe!Gv_wf!!_)58ryp~hu2(l=}c5EIfRlY;w68JlE0z* za$fIBrCwc0a)@Tld$^7M5?bIt@~SWCp66&2bCBD4 z>HO?=?jx|1kJ&|SEVy58@j5THk$Ncw@OK&My|RAX9IM>ca`BGX9rBI)IBxV`T`w(? zQRXmd9bK<4l}AYC_AFX97TUk;i)i|Q-tQQ&`QIFvq1!z$WV8hv?w_GczkkTMBlsp# zyOBB?^e>|k55m{~>Ac+Eubj`szQ25U$BPsN9Rqk%dwTb~@Zg5yt>3jb3}&YtI6S48 zojwp5Vn^!VLLS>fGvE`%i+k*k&f33B-r3O(wC`PtoGje)ZchF_ctckH!-qH7PX{F) z8?!HVyvt`|Sn-Q{?y>Jdd7Z`Pe@9{ZtS0YR^!VYV(%VlRWKTJUH1)1i>U}k;wq!`j zc`2TAR>^rWo|EU3Tl<4}&N?OMJMo+$CFk*I0oLz(V(GlSQ zCQp%0L2vrGMnmkANCA2t8(SLtFtU4)m72qE;qOi1D_BKnBxi&igIf#ptuc)3Yb^!v z$KS_jzQ1sR-7+OaFq-FIQXV(%~G`yy<#`@$Zs zZSx+exhZt|aBS?ySE?O313nk^>Y73{Jh0{W@v0sd@i^RtMWxO@QEIV8hOR12|Y?NJSj7YO6b?Ll=*Kl;b z4(|>#PDz%dE?SK!B1<7XP%)cYp)*shADq7xwjLd?j5tu&yfEqEeHP;6QLNDWmywQi z!J@G@{S;~Da!tJBnxy&Z`RTBB&v<&|9eTH4!BPtGJSs7hJf2@3XD0oN<=FpF9Gk}E zp6N@o!|C@+rPGv%N%ek$@uvCeKSI%F*;Z3&a`+4K z3*KHT@$g{ya0lL)%|?8;gR{@W7rEc)5Qp{H*R2_v08-Kgzap|z1qMWqz4@YIKnb7$( z${-uX+MCU2HPRLCY~0~K>Q2Kxl8vqd=k!~EY$oI8I3`^^bU(dg2lg#H8fE$NxLn4y z3Z|9Rfbo`B12#HOlb@u?zlG=fhX-GrJGN~f(5&DX|^`^ zIv>{HebP{-MZb^DPJZ0*xHKo}TYC!MPtyO8_WCo~PR+KMU`U)YChBobR_s>Uiqr@Un(|KKfn6 zKDXXdgI^)kHq7v5*QAAQkmF68w=qA(HDttFfy35@Z2y-WxdZxwH0zT3G(X<9q~!V+ zD!-hV?~u&7uC_=O>@CEZf1i7v1Gm4f`KWt{&2Ko^TH?rcRXK9KRgQx-si$vN%FV-f zIX{zUyNY4Gv_9Rtm)%k~qjkub?lMEa1T8sOGxu~cZ}H6V4GpXy%fH8bENO-h?=nx| z)|Xitnma69o)eY|%yn$EKQX$j>TGlM^WYk z@|b~HpM{;p$UB7Zap)U3Lk84j;5E_N=qbqXpOxepI0G>Y&TX!YI?0t$pRRe*Tp4Ju zR4^Tpdb$JeP^GqxX^u1AG#h>gfWNsoJ*jP^HmL2Vwo`kkozyRC7xgI>Z8_-5Vd>u7 zn#-Z&hJ9WG`G6}6el6$WMAn5j0EH6#rwE)$1yoC(cTPi=7mVxZmo!-{Xx^(!hre9L zuPfTTCY+`R%}sjvwCl`08F;IHrai|SG&dQjYz}D~WbK*I9)-Nk)#lB{9S(i#fu-B2 zYz~`hc6hU`DW#Xf)0WdY`1j}W-jug7+eJ8f9z1TM`>E^>Iz!TLc*xgdTVIXE&f^T* z^^T6tmD=CL{Px8wW0$VP#=ec)ms`i#=+MQt9H)IcbC&J2`?N31n(}DMfm6O zr;t-%o$~0E1N(gvqL0b8-+cf%$&V%@Cs=q$r{*L*n#6P7kLMU3H5@qLlL`xL2k=W1 z3;(4Fc7swX=JwRb)Amk#Y>z4Rha*W>#^#Ja?|8C(w)sqZ_8n~<2Yp^}e9)bHkJ*;n z-qsZ?NTuk|`Aoy(?eCjn<)QXHKI@!v+a7o3JtkXbdt;YmTiqG<7TCh@0hDpI`OJtW z`x{W3KHK#=P9@E)->TDFn;Rc@bQTJIZn0v%?I82?HEP)oLbLJ+j{p7$M0NI%x&(R%7g8(v40;A zI`-F;oeDbg2KU>ya$kSYalrmhE2qDZ9%;AJsC{Gnfd+bWa5*g9x^(GK^(-syj&ja2 zM{UlogM*LR&kk0(Sn)?8+>hiOW6ZL7RmeD!6a0#CjZ}4@=KQI%i0%jNLw0E&+sEek zVBOa+l)K;V<1;@iw2?=gc8Yd$a9RuRv7AlH^<`pZY^!Om&ePq6DB*-JuR}axq2rNr zQRyH%F#XxsSoQcTk*Ni15jUn^{AHwhh3@$$^6y$zI%o;%3QSmK^cPvtg|Ok)BQ>9g zUx-L$Ec}Cr4u4NX^!R%+V&H$1@b^q4xr~JlMw;v``85rz?aeJ6$&?$koMlhjpFq8j zM5-GkOW2!Ub2+@kk>|_9+vLTLI~&?u^xWad_33D?xf|?l?p)uJ3QFfPwM3=ktak`E zpg)VubC}F$TxDGUVbbx@?8$W(I&!f)|23m~s!X=j-j z>06Om+)^GQlT@(VmhH|54-a2RQ{v3ib~dLnBCjP3ckUEF7=EV~W0+@%UHFUOhPZ-Q zu^S5|+rm;P_EFs9F$Z`Q@rPpFW7z*#5ffPuk4c9gCT(2${H{O!hTw38CZ$Fa`rF-!;7QKOP7RNu&U)pzl6UxMei7Ne4l${@|>q}7N))tAH)x>57c+! zfcn;mhu)`de{rempX0OCm+egVf0p20q#J_(WBeby)M0}$Jk-zw@}L@C5I#w07w zc>EWSnZsAcesGEQF}k|(u{xwi?D^A}DLWpe+q_wIc%K3WGx42^?+pIk=AF*-5t~ih z5u0;2(T!kkNA9MeNoULLXxoH{jQ4*Bv6{%^J@x0YlvwO@ttSBp-S)YOQA*82=r`JzKx&-O;a4J$yBbAExjIps`><`$nJ{bE9f4>qN#ovF7 z{Uurm&d$RV7-OcHoImu}gx_`IK5e?!xSX=a$F7gj--R(&RuGyAZkq60&9jI1)#Qh6 zVcr{qIT;PH*;y>xJ7?gy@y1^IC16PXa{z=Ur!#Wd-(5{%_#!hFt zh%uwOY24^Hy3CwhPxYJ_PvYNa`R+~D$)Czh`ROQ&cBR(QjnZqahDGnSN+#M(`HvWu z+m?)cy0XiDDPL1A*5SKw=_~Y^^EQ?8P3U59XiAyoIqY=N75R?*c;;4fwr*w zxKGb_f^^Gplj+LX%NObIrx*W#wzBo`E%*X%gZLX3y3ZSF9Un`NkuSWZ{I)~B$ya3+ zlVk@ssrhc6ucE&K(J5qySBH~EZ0x!5ui+L@DsZhG9}C6k?{hIf>M$_1#2c|^aBG0R zA!a1gDvW&-{hpO{c0iI8Cd~+1_ph)`d!A$-Sz=?SF8!JM0$r+cRvqcR)@Z1TH0C+< zt`v*SmAq(&OYg>c&VAIaZ@)6ucZn5Q!h>j$k>8b2dwz1c73m;v;g2qlAia&Je{h-Z zP#A6#N$aW0L5piG;q3+EV+ZhiUq3u?(fFw-%@^V`b9j)mcx7zwrPx>zXJsbKWpb_s zJL%_;pU?AE%~jY#WKYWJ!j2+sQqFIXBOxb^TRO^bdsEMDEy%LI$yVd8e4Q~J=P=`d ze;MVyfw%LNSAv``aCT8^T8+B@bDTzZu<#IL=+VvRV`C>ZIakI;(VDmA9Hl2YsF&`$ zUqI}km@~tY&hNji@N?x7k zs?z-{{7ll#*Ht`LlXOg35D)xEQXR9r zQ#dPb$WKgqcut4 z8Fkt9k}F&JJF|Xf1GDHNCtAsSUNb&YbK!VaL)LO;ks{eHL*>&omyXBA`meCjS>Wu_ z#qlWpI|2iy-%WUom`4)6DX#J_#!La!n^MVA=zDPn_UxFe_#OD1sVk-}@60=t`Td$y ztO;y1=X~0VG$kh~>_74ooRIe~lNS6js;2%DWw4_@2BgmqBaZws<(J>VFWI$etBIxT z!4tyMt9+;3#8O6P$$81ha{;5#DJPJZc_T|%f`>3YBS`-zp5=J{0goTgc07;a`92;8 zI=8fWc}qlNMmu*6M5A-&obT?9@O)09Ku{rvsteGu`P7UjV zjXuSmi8Vpkeu+sdlSDomtP zzM!(wRMhL~^0@mv#in)DO)KVkHn)2^J3XCqZ=2iR>+bIGntDC=`TBf4-KNR~uyfm& z8JmiB#qdG*woIQojTx1`Y$<0cbx2oF&)jMFs{SF}HzbX&#C56cEqGETmXbyTbL|iJ zH$9UTMwsk>dOn;eutmi(k?){hGNWhkH~LhnI4J=qC*Uawn44jSc==RW&X|c3dPa`Q zSU^&7I>(DMR7|~__~_ZR34oNIO;5lXN)P311N(EV0Lk<49XUtG3Xzzp^pBzcw*nVx z@a@1iYOo!6fd)4KS8DKGz;+F82OiL1s$Yx!z;zmVAF%qN_Wl#VYl%1{YB1S%X)wtz-{Nj|EFsFHfDoB>yOF0#p0o z2J!JGdE>MRO!CeIyhVdafARFm`i&Y)a%0A1d3gd}ufe3>k~LXBkbqy*VA6kk=4Acz z8cgz5tm*i|N5}SEga0iW`E%Eh|6C&{dm|eBuh-CjO(Q4$hz1j%?`ts0Kh@yl*RVIL zk^d*;v`5KBIf^%AZz}dA_`*lW{s=kkW9D-t$D_p>Iq6$9SdSe9?QJNstMRK&BPadk z8k_@t+7D^luYf(;pQ-&L`5}$`A0Vgw zToCzcfAX=%1LQfRU#P*Gp-+22E0@ZAc537gLQea{LmD~ApJXpL0hcG>B?1(uizImcNwYM<= zyAp6P0q;q`&uTFC67i4f4?vlqW%xB(LSq2PWt}B34Lns8yd{{)L@c-q`@RF znmxIEiw2W?iw0Bqpazq?aL(lNi#3?!gT<5OA89bjpDmdze?x;w{+MRG2tT1?CVb%| z&)=sK@Sz0!YywvI|Fokfdy6a7`elE!Cg2tg{tV+mI1}Y0#XmbW@{5oYR^?MPXEk-a z-%jWs!#R+8LlHIa8u}?3Iq{#CfTt$l=?OS90UI@#`d_HQCD*9GNFyixfdrfxAD=XK z=QYajNzi{sgBz})|EWga3OSvZ>13v^$DNCt&RPO~}S4jqQOw^`nmeFE#p4Kz;;x29(tP zg*0-qpE7rHdovSoVFI=$;MN4ZAps9+FxB_022+1u&|s3E&|s3E(qNLelud5$`UKpa zfFDZ0`xEeU3HX-@cr*d)H0NJx-^>I&CjrmbU~2zD4So^h^8(_B3G3e(PJ_wbat-GEX)wuKHJIcs4JLV~29vx?gGuh!V3H4LFv+)QFv)jn zFv$ls_;vJe7jOykRe$}dMo#5FO2D|cGa(xvd4FY1z%2>5H30`S@%0$$Cwv2}sqyy_ zjr`A$6Q;W_RsMoTJ{5t2aIr>yN+U0UoG@LZQF$8$7UiSPU%ID~v*h^jQw?sohQ4~g zL5vZfA&tIKxnd%Fs{J=Ka?(Gc!K9~tNdH5WSMN6vDcBgcrnbDq8!2LRw z;#KrN1FlB<=zfOUn~E#Bbi{koC!9xDbjp}yg0E8GEXb+DBwqwf@j4SY3;x*z{5yku zo+5cC@B`SNFH!U#0A7pw=q8Tj-vmxk_$B+_27U?spQ^~82hPy6=NG`K8vJj-ze9g! zD*C5^)$z(?$?OB*o3TH>UXgzRtmPvK9r-|0Umoxep}zq0fZA6A{2S~y=uV070^lQv zmvp`(TnGGRU|N3&-vzA4c+h!>6f2rg9F);1lYPdh?*fMz}v9@{-uK70DfCz@3+8zhCiwL=YT1m(tQT;@j0;8zv$h`>+m0wVlNB$ zZM5H}=-&eTAm(44B3}Z$4dX%ch1$Cs_#I9CZs3ziEM>jofA<3a7<|5sxJ3Fpfwg>m zI|2UyI6ocyVf<;`@1-umeo0RrCfg|7t-QoS& z1ndTXs{BFVTTwsUmh-a*_)8dXb-q3e{6pxg{{OGQJ?O8Be*>I@^ZTnx`FDX&V?OOv z@E?Kq!9Ugbav8W9=f^=bi1?d^K=ml%(RxMS1dNY~{D=Bi3|x$OppN&Qz^R(~-3qMb zvlCd$e;@%5Cg5)a2Z zepcgucLLvu^Yi?@HEYO^*!KE zHTus3pN0R~NgwsS1bj2>u9{g!Qk$(2mYEyKM1@U^GzL} z1HgA;{-9aBKhFYd$MfgFquAe|dS3slzz#qfEyOjETz!U2g_TRwtj=5Hm zKLV_+|2x1>Y5eJ*f$`z~ki{hSGVrb7N1cyv1Lsd;{Cq_Gp90qU?}xxz`(p_>HH*Jb ziSw5Mtko|AzD~pEQs4^2A9Xz1fFFZ@;T;<1za3agXDN86#m5V4Im?5-8Xq18z8(Ij z`rDJhzsCNE<{SAhYYw=31O5Jaee$=nFR;0)azpuT_p=SX?#&)&XaDBS_p_e%dpsQh6kkw*;u?vQ zS~sbfv%k}KU!SiEy)RRe&c01PzZ2Qz&VZ*cz?_};ZSHgiy857_Fg7sY^t!vysY%$` z(bF673|y7H(eLZID%0Q5d96I>HOlvPbWBq1>T>o6d}vPx>+fstbar%-d`)vrtCo-3L0`_LxhK;qJK21^N)?G7qRlw`%ZT5RSomZ8i>Q?m! zCQLVb;A0c8*2CQ<-aL+c8{AzOpsL#|wTk!oIy|fU-Ce#7K2I-incP2kSG=!*u3pc* zKph)4`Z@>5#H}(5K4_6(v)k8=ufF>?xA$~8J-xj>y($R!HhcOK#%yz+pS0zffN}K& zc;UW)XR|s#253mp5@#oV?$I&Pl+F&Pk35@`&U@*!H*;j`fls1#1vYs)JihxpDkKId zt#q!NY;bx&zY_^3W?rDbk8SpBE?YQ%;e1)K6C(x1`tCqW&zf#uM^C3m;cnGRd;PLC zP1P;+t5!OjTbk-uE_2paw^YmG`jst9o9xxLrB{nqRIgkENz0n1rA=2$8=F?uuCcXD z643lXBRcOu48i{hA07Se9$%-&Sy5JARz4|fp1-Sqqp!Pf9wu~IUjY9r>SfR`+uYG# z<{1chdb{BX^fR5Zjotlod1@|xurrrymtFOPoqzOoS5?ZD$v@tiU$L-aK}GpIUUFW$ zuX|ou*}N`a`@D@E9rN71o9A}-bbIE~kA~*)U-!%lc>6cE&%1BI+|Bb4oqU+o|M&E! z8@+K(4sxBy@b`LX;NpRg@-!KIIk-wq&aJCn?rgNxI+r#&ZC$-^%&sn`<~4cxJOLYW z+T9(S7-`+zi{Rh5qMEH}buMeHU*#lMSM`?;I3dE+*x=j9yleW}Yx#7-L{JU#N_zSf zzeXIfb-DZcloHK+LbI0o6%|gK%~{{Hy3XC**@abyim$w@-sVJ!#$Ln$U*P_@O*tB( z;Tt{irq;Q8JMHfNu7FcD;auVCrfJu)$=U4tiib7d-`C;;Q007jV(NK%H@G`I&J8{O zKAOQ)Gw-L|abNdDG*jk$BTRbY6gZn#+2gHn_W3#yJGqf2^oWA5ZMnmaFvc1^-JQ*M z#j9VrqCTFE_jYNwyS>W;9x!yC0R%&=gq?B&mM?cU_xJe;*H_vqv}BRU6F~nE;A{w) zwyquw9`9dspc6yVgzBk|6@7j_dR&B3^?iKwmo`pRLE8wmC?%a(wFmIkNBaU^t`CvS z*MTM2qYP@3XQK~Q_wtdQ;BQh*)IM5jxR~4uj@G|G{eGzR)1u$x@q65XKJL}Dbdpm$)y)D@ z=pmK|bQ;?jZi0ASWk=t6#m$ZNlUOHbvi0+(t)iauDaK85Qk0RRQF1CX zq5mJr9JkZFwz;L==1?U{e|vr18=F17K6h8#HF#SY4I^e`#b)l^3U$~rT)n(Iors}W z-{N6IQ4Vy`+UD!-_cRT#n)?G_tvis|GtA>vaK3m?HFI@oYfF8lvr6lc)wPp7bPYzY zX`lwXMo+J@fU2WKbB?!Zf^(t^K1pHWHm%jBmPs+f=^>xw5i35EI9s%MV^3pm=KBpd z*7RNsw`||u?37~^mtljc>?M1-b6`8r<(2~tA1PaZZ!gFoQsQJaLeX|gSG~V-_6}M`ureLRW2_Adv zJZ`@ndTUoyBfxvz-QAw9Npnb@C)8tXI6;dhq}O^jObY0#GF%aHwP}F6C?nTunQ$%M zCs1m`uYBdTP4T4p+V-iYFgdF`J9|CwBW)Y!J12FH+l1pRcXw~BuWb(SeQdAKkK;{z zJ}9v{z7kOA!m#%8W7pLib=e0eZHyIz#BRBB5=*FG+jzA(6Mn1|bvpSkshwSP&|%!u zaT1UhS#>`5dN%jqFt?eunzXH!9Rs@Yv7g*OwX(+Ep3eRbjF7hT+z+ce=pZQ9-0wrx ztobfmd_vmk3`fHo_hdd{}uS)-#>XWIk5uLmTuBW z!3*N!zrx+!kBv~EzZa*%Nuylf)Y6K50FfBimY1T*dTW}in_4Qhy~HVDGh%Na&OjK5 zjclXSzoGjsoa1pXAe&Mac}|%Z=Vu(n~PtsRIkDQ5d zgbjsz#-~SoCa^M`Ujy!Tdn-peL#R9Kl@m{!a(CvB#jUJB2$Q*fK^K%m#x-jDkcRz?Gdbq}RH z?fo0&C6ZsP{dfN4L5c2{>5d8?+{NJ^$MB^5hh+4*84soD-P#EBMu76m0hABjQPO8F z9=g!OD;oYTjcvg_qGFt~RJ|`Dt=3EL0N*K>=q@_`QT3K7dR&Bep#e!_Op#HcrvIki z-O$4|q1?W|V~^_IfQRk@c|YhKY^4-$JF7j>;e1tx|vAz&*bDQT29d^ynSQ;tah1(!B3iO%Fj2b^6uvWUojC_*V6v zSJLW`J^{T467)#-r: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 20000174 .word 0x20000174 + 80000e0: 00000000 .word 0x00000000 + 80000e4: 080030c4 .word 0x080030c4 + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop ; (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 20000178 .word 0x20000178 + 8000104: 080030c4 .word 0x080030c4 + +08000108 <__udivsi3>: + 8000108: 2200 movs r2, #0 + 800010a: 0843 lsrs r3, r0, #1 + 800010c: 428b cmp r3, r1 + 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> + 8000110: 0903 lsrs r3, r0, #4 + 8000112: 428b cmp r3, r1 + 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> + 8000116: 0a03 lsrs r3, r0, #8 + 8000118: 428b cmp r3, r1 + 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> + 800011c: 0b03 lsrs r3, r0, #12 + 800011e: 428b cmp r3, r1 + 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> + 8000122: 0c03 lsrs r3, r0, #16 + 8000124: 428b cmp r3, r1 + 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> + 8000128: 22ff movs r2, #255 ; 0xff + 800012a: 0209 lsls r1, r1, #8 + 800012c: ba12 rev r2, r2 + 800012e: 0c03 lsrs r3, r0, #16 + 8000130: 428b cmp r3, r1 + 8000132: d302 bcc.n 800013a <__udivsi3+0x32> + 8000134: 1212 asrs r2, r2, #8 + 8000136: 0209 lsls r1, r1, #8 + 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> + 800013a: 0b03 lsrs r3, r0, #12 + 800013c: 428b cmp r3, r1 + 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> + 8000140: e000 b.n 8000144 <__udivsi3+0x3c> + 8000142: 0a09 lsrs r1, r1, #8 + 8000144: 0bc3 lsrs r3, r0, #15 + 8000146: 428b cmp r3, r1 + 8000148: d301 bcc.n 800014e <__udivsi3+0x46> + 800014a: 03cb lsls r3, r1, #15 + 800014c: 1ac0 subs r0, r0, r3 + 800014e: 4152 adcs r2, r2 + 8000150: 0b83 lsrs r3, r0, #14 + 8000152: 428b cmp r3, r1 + 8000154: d301 bcc.n 800015a <__udivsi3+0x52> + 8000156: 038b lsls r3, r1, #14 + 8000158: 1ac0 subs r0, r0, r3 + 800015a: 4152 adcs r2, r2 + 800015c: 0b43 lsrs r3, r0, #13 + 800015e: 428b cmp r3, r1 + 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> + 8000162: 034b lsls r3, r1, #13 + 8000164: 1ac0 subs r0, r0, r3 + 8000166: 4152 adcs r2, r2 + 8000168: 0b03 lsrs r3, r0, #12 + 800016a: 428b cmp r3, r1 + 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> + 800016e: 030b lsls r3, r1, #12 + 8000170: 1ac0 subs r0, r0, r3 + 8000172: 4152 adcs r2, r2 + 8000174: 0ac3 lsrs r3, r0, #11 + 8000176: 428b cmp r3, r1 + 8000178: d301 bcc.n 800017e <__udivsi3+0x76> + 800017a: 02cb lsls r3, r1, #11 + 800017c: 1ac0 subs r0, r0, r3 + 800017e: 4152 adcs r2, r2 + 8000180: 0a83 lsrs r3, r0, #10 + 8000182: 428b cmp r3, r1 + 8000184: d301 bcc.n 800018a <__udivsi3+0x82> + 8000186: 028b lsls r3, r1, #10 + 8000188: 1ac0 subs r0, r0, r3 + 800018a: 4152 adcs r2, r2 + 800018c: 0a43 lsrs r3, r0, #9 + 800018e: 428b cmp r3, r1 + 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> + 8000192: 024b lsls r3, r1, #9 + 8000194: 1ac0 subs r0, r0, r3 + 8000196: 4152 adcs r2, r2 + 8000198: 0a03 lsrs r3, r0, #8 + 800019a: 428b cmp r3, r1 + 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> + 800019e: 020b lsls r3, r1, #8 + 80001a0: 1ac0 subs r0, r0, r3 + 80001a2: 4152 adcs r2, r2 + 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> + 80001a6: 09c3 lsrs r3, r0, #7 + 80001a8: 428b cmp r3, r1 + 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> + 80001ac: 01cb lsls r3, r1, #7 + 80001ae: 1ac0 subs r0, r0, r3 + 80001b0: 4152 adcs r2, r2 + 80001b2: 0983 lsrs r3, r0, #6 + 80001b4: 428b cmp r3, r1 + 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> + 80001b8: 018b lsls r3, r1, #6 + 80001ba: 1ac0 subs r0, r0, r3 + 80001bc: 4152 adcs r2, r2 + 80001be: 0943 lsrs r3, r0, #5 + 80001c0: 428b cmp r3, r1 + 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> + 80001c4: 014b lsls r3, r1, #5 + 80001c6: 1ac0 subs r0, r0, r3 + 80001c8: 4152 adcs r2, r2 + 80001ca: 0903 lsrs r3, r0, #4 + 80001cc: 428b cmp r3, r1 + 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> + 80001d0: 010b lsls r3, r1, #4 + 80001d2: 1ac0 subs r0, r0, r3 + 80001d4: 4152 adcs r2, r2 + 80001d6: 08c3 lsrs r3, r0, #3 + 80001d8: 428b cmp r3, r1 + 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> + 80001dc: 00cb lsls r3, r1, #3 + 80001de: 1ac0 subs r0, r0, r3 + 80001e0: 4152 adcs r2, r2 + 80001e2: 0883 lsrs r3, r0, #2 + 80001e4: 428b cmp r3, r1 + 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> + 80001e8: 008b lsls r3, r1, #2 + 80001ea: 1ac0 subs r0, r0, r3 + 80001ec: 4152 adcs r2, r2 + 80001ee: 0843 lsrs r3, r0, #1 + 80001f0: 428b cmp r3, r1 + 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> + 80001f4: 004b lsls r3, r1, #1 + 80001f6: 1ac0 subs r0, r0, r3 + 80001f8: 4152 adcs r2, r2 + 80001fa: 1a41 subs r1, r0, r1 + 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> + 80001fe: 4601 mov r1, r0 + 8000200: 4152 adcs r2, r2 + 8000202: 4610 mov r0, r2 + 8000204: 4770 bx lr + 8000206: e7ff b.n 8000208 <__udivsi3+0x100> + 8000208: b501 push {r0, lr} + 800020a: 2000 movs r0, #0 + 800020c: f000 f806 bl 800021c <__aeabi_idiv0> + 8000210: bd02 pop {r1, pc} + 8000212: 46c0 nop ; (mov r8, r8) + +08000214 <__aeabi_uidivmod>: + 8000214: 2900 cmp r1, #0 + 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> + 8000218: e776 b.n 8000108 <__udivsi3> + 800021a: 4770 bx lr + +0800021c <__aeabi_idiv0>: + 800021c: 4770 bx lr + 800021e: 46c0 nop ; (mov r8, r8) + +08000220 : + 8000220: b510 push {r4, lr} + 8000222: 0004 movs r4, r0 + 8000224: f001 fac8 bl 80017b8 + 8000228: 21fa movs r1, #250 ; 0xfa + 800022a: 0089 lsls r1, r1, #2 + 800022c: f7ff ff6c bl 8000108 <__udivsi3> + 8000230: f000 f85e bl 80002f0 + 8000234: 2001 movs r0, #1 + 8000236: 2200 movs r2, #0 + 8000238: 0021 movs r1, r4 + 800023a: 4240 negs r0, r0 + 800023c: f000 f81a bl 8000274 + 8000240: 2000 movs r0, #0 + 8000242: bd10 pop {r4, pc} + +08000244 : + 8000244: b510 push {r4, lr} + 8000246: 4a06 ldr r2, [pc, #24] ; (8000260 ) + 8000248: 6813 ldr r3, [r2, #0] + 800024a: 2110 movs r1, #16 + 800024c: 430b orrs r3, r1 + 800024e: 6013 str r3, [r2, #0] + 8000250: 2000 movs r0, #0 + 8000252: f7ff ffe5 bl 8000220 + 8000256: f002 fc39 bl 8002acc + 800025a: 2000 movs r0, #0 + 800025c: bd10 pop {r4, pc} + 800025e: 46c0 nop ; (mov r8, r8) + 8000260: 40022000 .word 0x40022000 + +08000264 : + 8000264: 4a02 ldr r2, [pc, #8] ; (8000270 ) + 8000266: 6813 ldr r3, [r2, #0] + 8000268: 3301 adds r3, #1 + 800026a: 6013 str r3, [r2, #0] + 800026c: 4770 bx lr + 800026e: 46c0 nop ; (mov r8, r8) + 8000270: 200004cc .word 0x200004cc + +08000274 : + 8000274: b570 push {r4, r5, r6, lr} + 8000276: 2800 cmp r0, #0 + 8000278: db14 blt.n 80002a4 + 800027a: 0883 lsrs r3, r0, #2 + 800027c: 009b lsls r3, r3, #2 + 800027e: 4a15 ldr r2, [pc, #84] ; (80002d4 ) + 8000280: 4694 mov ip, r2 + 8000282: 4463 add r3, ip + 8000284: 26c0 movs r6, #192 ; 0xc0 + 8000286: 00b6 lsls r6, r6, #2 + 8000288: 599d ldr r5, [r3, r6] + 800028a: 2403 movs r4, #3 + 800028c: 4020 ands r0, r4 + 800028e: 00c0 lsls r0, r0, #3 + 8000290: 22ff movs r2, #255 ; 0xff + 8000292: 0014 movs r4, r2 + 8000294: 4084 lsls r4, r0 + 8000296: 43a5 bics r5, r4 + 8000298: 0189 lsls r1, r1, #6 + 800029a: 400a ands r2, r1 + 800029c: 4082 lsls r2, r0 + 800029e: 432a orrs r2, r5 + 80002a0: 519a str r2, [r3, r6] + 80002a2: bd70 pop {r4, r5, r6, pc} + 80002a4: b2c0 uxtb r0, r0 + 80002a6: 230f movs r3, #15 + 80002a8: 4003 ands r3, r0 + 80002aa: 3b08 subs r3, #8 + 80002ac: 089b lsrs r3, r3, #2 + 80002ae: 009b lsls r3, r3, #2 + 80002b0: 4a09 ldr r2, [pc, #36] ; (80002d8 ) + 80002b2: 4694 mov ip, r2 + 80002b4: 4463 add r3, ip + 80002b6: 69dd ldr r5, [r3, #28] + 80002b8: 2203 movs r2, #3 + 80002ba: 4010 ands r0, r2 + 80002bc: 00c0 lsls r0, r0, #3 + 80002be: 24ff movs r4, #255 ; 0xff + 80002c0: 0022 movs r2, r4 + 80002c2: 4082 lsls r2, r0 + 80002c4: 4395 bics r5, r2 + 80002c6: 0189 lsls r1, r1, #6 + 80002c8: 400c ands r4, r1 + 80002ca: 4084 lsls r4, r0 + 80002cc: 432c orrs r4, r5 + 80002ce: 61dc str r4, [r3, #28] + 80002d0: e7e7 b.n 80002a2 + 80002d2: 46c0 nop ; (mov r8, r8) + 80002d4: e000e100 .word 0xe000e100 + 80002d8: e000ed00 .word 0xe000ed00 + +080002dc : + 80002dc: 231f movs r3, #31 + 80002de: 4018 ands r0, r3 + 80002e0: 3b1e subs r3, #30 + 80002e2: 4083 lsls r3, r0 + 80002e4: 4a01 ldr r2, [pc, #4] ; (80002ec ) + 80002e6: 6013 str r3, [r2, #0] + 80002e8: 4770 bx lr + 80002ea: 46c0 nop ; (mov r8, r8) + 80002ec: e000e100 .word 0xe000e100 + +080002f0 : + 80002f0: 1e43 subs r3, r0, #1 + 80002f2: 4a0a ldr r2, [pc, #40] ; (800031c ) + 80002f4: 2001 movs r0, #1 + 80002f6: 4293 cmp r3, r2 + 80002f8: d80e bhi.n 8000318 + 80002fa: 4a09 ldr r2, [pc, #36] ; (8000320 ) + 80002fc: 6053 str r3, [r2, #4] + 80002fe: 4809 ldr r0, [pc, #36] ; (8000324 ) + 8000300: 6a03 ldr r3, [r0, #32] + 8000302: 021b lsls r3, r3, #8 + 8000304: 0a1b lsrs r3, r3, #8 + 8000306: 21c0 movs r1, #192 ; 0xc0 + 8000308: 0609 lsls r1, r1, #24 + 800030a: 430b orrs r3, r1 + 800030c: 6203 str r3, [r0, #32] + 800030e: 2300 movs r3, #0 + 8000310: 6093 str r3, [r2, #8] + 8000312: 3307 adds r3, #7 + 8000314: 6013 str r3, [r2, #0] + 8000316: 2000 movs r0, #0 + 8000318: 4770 bx lr + 800031a: 46c0 nop ; (mov r8, r8) + 800031c: 00ffffff .word 0x00ffffff + 8000320: e000e010 .word 0xe000e010 + 8000324: e000ed00 .word 0xe000ed00 + +08000328 : + 8000328: b5f0 push {r4, r5, r6, r7, lr} + 800032a: 46de mov lr, fp + 800032c: 4657 mov r7, sl + 800032e: 464e mov r6, r9 + 8000330: 4645 mov r5, r8 + 8000332: b5e0 push {r5, r6, r7, lr} + 8000334: b085 sub sp, #20 + 8000336: 680a ldr r2, [r1, #0] + 8000338: 2a00 cmp r2, #0 + 800033a: d100 bne.n 800033e + 800033c: e0ba b.n 80004b4 + 800033e: 2400 movs r4, #0 + 8000340: 2301 movs r3, #1 + 8000342: 4698 mov r8, r3 + 8000344: 330f adds r3, #15 + 8000346: 469a mov sl, r3 + 8000348: 3b0d subs r3, #13 + 800034a: 4699 mov r9, r3 + 800034c: 2380 movs r3, #128 ; 0x80 + 800034e: 055b lsls r3, r3, #21 + 8000350: 469b mov fp, r3 + 8000352: 4b5c ldr r3, [pc, #368] ; (80004c4 ) + 8000354: 18c3 adds r3, r0, r3 + 8000356: 425d negs r5, r3 + 8000358: 416b adcs r3, r5 + 800035a: 425b negs r3, r3 + 800035c: 9301 str r3, [sp, #4] + 800035e: e039 b.n 80003d4 + 8000360: 08e3 lsrs r3, r4, #3 + 8000362: 009b lsls r3, r3, #2 + 8000364: 18c3 adds r3, r0, r3 + 8000366: 6a1f ldr r7, [r3, #32] + 8000368: 2507 movs r5, #7 + 800036a: 4025 ands r5, r4 + 800036c: 00ad lsls r5, r5, #2 + 800036e: 220f movs r2, #15 + 8000370: 40aa lsls r2, r5 + 8000372: 4397 bics r7, r2 + 8000374: 690a ldr r2, [r1, #16] + 8000376: 40aa lsls r2, r5 + 8000378: 0015 movs r5, r2 + 800037a: 433d orrs r5, r7 + 800037c: 621d str r5, [r3, #32] + 800037e: e033 b.n 80003e8 + 8000380: 2500 movs r5, #0 + 8000382: 40b5 lsls r5, r6 + 8000384: 433d orrs r5, r7 + 8000386: 609d str r5, [r3, #8] + 8000388: 4b4f ldr r3, [pc, #316] ; (80004c8 ) + 800038a: 681b ldr r3, [r3, #0] + 800038c: 9a00 ldr r2, [sp, #0] + 800038e: 43d5 mvns r5, r2 + 8000390: 684a ldr r2, [r1, #4] + 8000392: 03d2 lsls r2, r2, #15 + 8000394: d500 bpl.n 8000398 + 8000396: e081 b.n 800049c + 8000398: 402b ands r3, r5 + 800039a: 4e4b ldr r6, [pc, #300] ; (80004c8 ) + 800039c: 6033 str r3, [r6, #0] + 800039e: 6873 ldr r3, [r6, #4] + 80003a0: 684a ldr r2, [r1, #4] + 80003a2: 0392 lsls r2, r2, #14 + 80003a4: d47d bmi.n 80004a2 + 80003a6: 402b ands r3, r5 + 80003a8: 4e47 ldr r6, [pc, #284] ; (80004c8 ) + 80003aa: 6073 str r3, [r6, #4] + 80003ac: 68b3 ldr r3, [r6, #8] + 80003ae: 684a ldr r2, [r1, #4] + 80003b0: 02d2 lsls r2, r2, #11 + 80003b2: d479 bmi.n 80004a8 + 80003b4: 402b ands r3, r5 + 80003b6: 4e44 ldr r6, [pc, #272] ; (80004c8 ) + 80003b8: 60b3 str r3, [r6, #8] + 80003ba: 68f3 ldr r3, [r6, #12] + 80003bc: 684a ldr r2, [r1, #4] + 80003be: 0292 lsls r2, r2, #10 + 80003c0: d475 bmi.n 80004ae + 80003c2: 402b ands r3, r5 + 80003c4: 001a movs r2, r3 + 80003c6: 4b40 ldr r3, [pc, #256] ; (80004c8 ) + 80003c8: 60da str r2, [r3, #12] + 80003ca: 3401 adds r4, #1 + 80003cc: 680a ldr r2, [r1, #0] + 80003ce: 0013 movs r3, r2 + 80003d0: 40e3 lsrs r3, r4 + 80003d2: d06f beq.n 80004b4 + 80003d4: 4646 mov r6, r8 + 80003d6: 40a6 lsls r6, r4 + 80003d8: 4032 ands r2, r6 + 80003da: 9200 str r2, [sp, #0] + 80003dc: d0f5 beq.n 80003ca + 80003de: 684b ldr r3, [r1, #4] + 80003e0: 4655 mov r5, sl + 80003e2: 43ab bics r3, r5 + 80003e4: 2b02 cmp r3, #2 + 80003e6: d0bb beq.n 8000360 + 80003e8: 6803 ldr r3, [r0, #0] + 80003ea: 0067 lsls r7, r4, #1 + 80003ec: 464d mov r5, r9 + 80003ee: 40bd lsls r5, r7 + 80003f0: 43ed mvns r5, r5 + 80003f2: 402b ands r3, r5 + 80003f4: 469c mov ip, r3 + 80003f6: 684b ldr r3, [r1, #4] + 80003f8: 464a mov r2, r9 + 80003fa: 4013 ands r3, r2 + 80003fc: 40bb lsls r3, r7 + 80003fe: 4662 mov r2, ip + 8000400: 4313 orrs r3, r2 + 8000402: 6003 str r3, [r0, #0] + 8000404: 684b ldr r3, [r1, #4] + 8000406: 4652 mov r2, sl + 8000408: 4393 bics r3, r2 + 800040a: 3b01 subs r3, #1 + 800040c: 2b01 cmp r3, #1 + 800040e: d811 bhi.n 8000434 + 8000410: 6883 ldr r3, [r0, #8] + 8000412: 402b ands r3, r5 + 8000414: 469c mov ip, r3 + 8000416: 68cb ldr r3, [r1, #12] + 8000418: 40bb lsls r3, r7 + 800041a: 4662 mov r2, ip + 800041c: 4313 orrs r3, r2 + 800041e: 6083 str r3, [r0, #8] + 8000420: 6843 ldr r3, [r0, #4] + 8000422: 43b3 bics r3, r6 + 8000424: 001e movs r6, r3 + 8000426: 684b ldr r3, [r1, #4] + 8000428: 091b lsrs r3, r3, #4 + 800042a: 4642 mov r2, r8 + 800042c: 4013 ands r3, r2 + 800042e: 40a3 lsls r3, r4 + 8000430: 4333 orrs r3, r6 + 8000432: 6043 str r3, [r0, #4] + 8000434: 68c3 ldr r3, [r0, #12] + 8000436: 402b ands r3, r5 + 8000438: 688d ldr r5, [r1, #8] + 800043a: 40bd lsls r5, r7 + 800043c: 431d orrs r5, r3 + 800043e: 60c5 str r5, [r0, #12] + 8000440: 684b ldr r3, [r1, #4] + 8000442: 465a mov r2, fp + 8000444: 4213 tst r3, r2 + 8000446: d0c0 beq.n 80003ca + 8000448: 4b20 ldr r3, [pc, #128] ; (80004cc ) + 800044a: 699d ldr r5, [r3, #24] + 800044c: 4642 mov r2, r8 + 800044e: 4315 orrs r5, r2 + 8000450: 619d str r5, [r3, #24] + 8000452: 699b ldr r3, [r3, #24] + 8000454: 4013 ands r3, r2 + 8000456: 9303 str r3, [sp, #12] + 8000458: 9b03 ldr r3, [sp, #12] + 800045a: 08a3 lsrs r3, r4, #2 + 800045c: 009b lsls r3, r3, #2 + 800045e: 4a1c ldr r2, [pc, #112] ; (80004d0 ) + 8000460: 4694 mov ip, r2 + 8000462: 4463 add r3, ip + 8000464: 689d ldr r5, [r3, #8] + 8000466: 464e mov r6, r9 + 8000468: 4026 ands r6, r4 + 800046a: 00b6 lsls r6, r6, #2 + 800046c: 270f movs r7, #15 + 800046e: 40b7 lsls r7, r6 + 8000470: 43bd bics r5, r7 + 8000472: 002f movs r7, r5 + 8000474: 2590 movs r5, #144 ; 0x90 + 8000476: 05ed lsls r5, r5, #23 + 8000478: 42a8 cmp r0, r5 + 800047a: d100 bne.n 800047e + 800047c: e780 b.n 8000380 + 800047e: 4d15 ldr r5, [pc, #84] ; (80004d4 ) + 8000480: 42a8 cmp r0, r5 + 8000482: d007 beq.n 8000494 + 8000484: 4d14 ldr r5, [pc, #80] ; (80004d8 ) + 8000486: 42a8 cmp r0, r5 + 8000488: d006 beq.n 8000498 + 800048a: 9d01 ldr r5, [sp, #4] + 800048c: 4642 mov r2, r8 + 800048e: 4395 bics r5, r2 + 8000490: 3505 adds r5, #5 + 8000492: e776 b.n 8000382 + 8000494: 2501 movs r5, #1 + 8000496: e774 b.n 8000382 + 8000498: 2502 movs r5, #2 + 800049a: e772 b.n 8000382 + 800049c: 9a00 ldr r2, [sp, #0] + 800049e: 4313 orrs r3, r2 + 80004a0: e77b b.n 800039a + 80004a2: 9a00 ldr r2, [sp, #0] + 80004a4: 4313 orrs r3, r2 + 80004a6: e77f b.n 80003a8 + 80004a8: 9a00 ldr r2, [sp, #0] + 80004aa: 4313 orrs r3, r2 + 80004ac: e783 b.n 80003b6 + 80004ae: 9a00 ldr r2, [sp, #0] + 80004b0: 431a orrs r2, r3 + 80004b2: e788 b.n 80003c6 + 80004b4: b005 add sp, #20 + 80004b6: bc3c pop {r2, r3, r4, r5} + 80004b8: 4690 mov r8, r2 + 80004ba: 4699 mov r9, r3 + 80004bc: 46a2 mov sl, r4 + 80004be: 46ab mov fp, r5 + 80004c0: bdf0 pop {r4, r5, r6, r7, pc} + 80004c2: 46c0 nop ; (mov r8, r8) + 80004c4: b7fff400 .word 0xb7fff400 + 80004c8: 40010400 .word 0x40010400 + 80004cc: 40021000 .word 0x40021000 + 80004d0: 40010000 .word 0x40010000 + 80004d4: 48000400 .word 0x48000400 + 80004d8: 48000800 .word 0x48000800 + +080004dc : + 80004dc: 2a00 cmp r2, #0 + 80004de: d101 bne.n 80004e4 + 80004e0: 6281 str r1, [r0, #40] ; 0x28 + 80004e2: 4770 bx lr + 80004e4: 6181 str r1, [r0, #24] + 80004e6: e7fc b.n 80004e2 + +080004e8 : + 80004e8: b570 push {r4, r5, r6, lr} + 80004ea: 1e04 subs r4, r0, #0 + 80004ec: d049 beq.n 8000582 + 80004ee: 23ea movs r3, #234 ; 0xea + 80004f0: 33ff adds r3, #255 ; 0xff + 80004f2: 5cc3 ldrb r3, [r0, r3] + 80004f4: 2b00 cmp r3, #0 + 80004f6: d03d beq.n 8000574 + 80004f8: 23ea movs r3, #234 ; 0xea + 80004fa: 33ff adds r3, #255 ; 0xff + 80004fc: 2203 movs r2, #3 + 80004fe: 54e2 strb r2, [r4, r3] + 8000500: 6860 ldr r0, [r4, #4] + 8000502: 2800 cmp r0, #0 + 8000504: d01d beq.n 8000542 + 8000506: 0023 movs r3, r4 + 8000508: 3328 adds r3, #40 ; 0x28 + 800050a: 2100 movs r1, #0 + 800050c: 2501 movs r5, #1 + 800050e: 2200 movs r2, #0 + 8000510: 705d strb r5, [r3, #1] + 8000512: 7019 strb r1, [r3, #0] + 8000514: 70da strb r2, [r3, #3] + 8000516: 60da str r2, [r3, #12] + 8000518: 611a str r2, [r3, #16] + 800051a: 615a str r2, [r3, #20] + 800051c: 3101 adds r1, #1 + 800051e: 331c adds r3, #28 + 8000520: 4281 cmp r1, r0 + 8000522: d1f5 bne.n 8000510 + 8000524: 0023 movs r3, r4 + 8000526: 3309 adds r3, #9 + 8000528: 33ff adds r3, #255 ; 0xff + 800052a: 2000 movs r0, #0 + 800052c: 2200 movs r2, #0 + 800052e: 705a strb r2, [r3, #1] + 8000530: 7018 strb r0, [r3, #0] + 8000532: 70da strb r2, [r3, #3] + 8000534: 60da str r2, [r3, #12] + 8000536: 611a str r2, [r3, #16] + 8000538: 615a str r2, [r3, #20] + 800053a: 3001 adds r0, #1 + 800053c: 331c adds r3, #28 + 800053e: 4288 cmp r0, r1 + 8000540: d1f5 bne.n 800052e + 8000542: 2340 movs r3, #64 ; 0x40 + 8000544: 2201 movs r2, #1 + 8000546: 6821 ldr r1, [r4, #0] + 8000548: 52ca strh r2, [r1, r3] + 800054a: 2200 movs r2, #0 + 800054c: 6821 ldr r1, [r4, #0] + 800054e: 52ca strh r2, [r1, r3] + 8000550: 2144 movs r1, #68 ; 0x44 + 8000552: 6820 ldr r0, [r4, #0] + 8000554: 5242 strh r2, [r0, r1] + 8000556: 310c adds r1, #12 + 8000558: 6820 ldr r0, [r4, #0] + 800055a: 5242 strh r2, [r0, r1] + 800055c: 4a0a ldr r2, [pc, #40] ; (8000588 ) + 800055e: 6821 ldr r1, [r4, #0] + 8000560: 52ca strh r2, [r1, r3] + 8000562: 2200 movs r2, #0 + 8000564: 3b1c subs r3, #28 + 8000566: 54e2 strb r2, [r4, r3] + 8000568: 2201 movs r2, #1 + 800056a: 23ea movs r3, #234 ; 0xea + 800056c: 33ff adds r3, #255 ; 0xff + 800056e: 54e2 strb r2, [r4, r3] + 8000570: 2000 movs r0, #0 + 8000572: bd70 pop {r4, r5, r6, pc} + 8000574: 33e9 adds r3, #233 ; 0xe9 + 8000576: 33ff adds r3, #255 ; 0xff + 8000578: 2200 movs r2, #0 + 800057a: 54c2 strb r2, [r0, r3] + 800057c: f002 fba8 bl 8002cd0 + 8000580: e7ba b.n 80004f8 + 8000582: 2001 movs r0, #1 + 8000584: e7f5 b.n 8000572 + 8000586: 46c0 nop ; (mov r8, r8) + 8000588: ffffbf00 .word 0xffffbf00 + +0800058c : + 800058c: 6801 ldr r1, [r0, #0] + 800058e: 2258 movs r2, #88 ; 0x58 + 8000590: 5a8b ldrh r3, [r1, r2] + 8000592: 2080 movs r0, #128 ; 0x80 + 8000594: 0200 lsls r0, r0, #8 + 8000596: 4303 orrs r3, r0 + 8000598: 528b strh r3, [r1, r2] + 800059a: 2000 movs r0, #0 + 800059c: 4770 bx lr + +0800059e : + 800059e: 23f4 movs r3, #244 ; 0xf4 + 80005a0: 005b lsls r3, r3, #1 + 80005a2: 5cc3 ldrb r3, [r0, r3] + 80005a4: 2b01 cmp r3, #1 + 80005a6: d013 beq.n 80005d0 + 80005a8: 23f4 movs r3, #244 ; 0xf4 + 80005aa: 005b lsls r3, r3, #1 + 80005ac: 2201 movs r2, #1 + 80005ae: 54c2 strb r2, [r0, r3] + 80005b0: 2900 cmp r1, #0 + 80005b2: d10a bne.n 80005ca + 80005b4: 3b9d subs r3, #157 ; 0x9d + 80005b6: 3bff subs r3, #255 ; 0xff + 80005b8: 327f adds r2, #127 ; 0x7f + 80005ba: 6801 ldr r1, [r0, #0] + 80005bc: 52ca strh r2, [r1, r3] + 80005be: 23f4 movs r3, #244 ; 0xf4 + 80005c0: 005b lsls r3, r3, #1 + 80005c2: 2200 movs r2, #0 + 80005c4: 54c2 strb r2, [r0, r3] + 80005c6: 2000 movs r0, #0 + 80005c8: 4770 bx lr + 80005ca: 2324 movs r3, #36 ; 0x24 + 80005cc: 54c1 strb r1, [r0, r3] + 80005ce: e7f6 b.n 80005be + 80005d0: 2002 movs r0, #2 + 80005d2: e7f9 b.n 80005c8 + +080005d4 : + 80005d4: b570 push {r4, r5, r6, lr} + 80005d6: b24d sxtb r5, r1 + 80005d8: 2d00 cmp r5, #0 + 80005da: db65 blt.n 80006a8 + 80005dc: 267f movs r6, #127 ; 0x7f + 80005de: 400e ands r6, r1 + 80005e0: 00f4 lsls r4, r6, #3 + 80005e2: 1ba4 subs r4, r4, r6 + 80005e4: 00a4 lsls r4, r4, #2 + 80005e6: 3409 adds r4, #9 + 80005e8: 34ff adds r4, #255 ; 0xff + 80005ea: 1904 adds r4, r0, r4 + 80005ec: 267f movs r6, #127 ; 0x7f + 80005ee: 4031 ands r1, r6 + 80005f0: 7021 strb r1, [r4, #0] + 80005f2: 0fed lsrs r5, r5, #31 + 80005f4: 7065 strb r5, [r4, #1] + 80005f6: 60e2 str r2, [r4, #12] + 80005f8: 70e3 strb r3, [r4, #3] + 80005fa: 23f4 movs r3, #244 ; 0xf4 + 80005fc: 005b lsls r3, r3, #1 + 80005fe: 5cc3 ldrb r3, [r0, r3] + 8000600: 2b01 cmp r3, #1 + 8000602: d100 bne.n 8000606 + 8000604: e173 b.n 80008ee + 8000606: 23f4 movs r3, #244 ; 0xf4 + 8000608: 005b lsls r3, r3, #1 + 800060a: 2201 movs r2, #1 + 800060c: 54c2 strb r2, [r0, r3] + 800060e: 78e3 ldrb r3, [r4, #3] + 8000610: 2b01 cmp r3, #1 + 8000612: d100 bne.n 8000616 + 8000614: e074 b.n 8000700 + 8000616: 2b00 cmp r3, #0 + 8000618: d04e beq.n 80006b8 + 800061a: 2b02 cmp r3, #2 + 800061c: d058 beq.n 80006d0 + 800061e: 2b03 cmp r3, #3 + 8000620: d062 beq.n 80006e8 + 8000622: 7825 ldrb r5, [r4, #0] + 8000624: 00aa lsls r2, r5, #2 + 8000626: 6803 ldr r3, [r0, #0] + 8000628: 469c mov ip, r3 + 800062a: 4462 add r2, ip + 800062c: 8813 ldrh r3, [r2, #0] + 800062e: 49b1 ldr r1, [pc, #708] ; (80008f4 ) + 8000630: 400b ands r3, r1 + 8000632: 49b1 ldr r1, [pc, #708] ; (80008f8 ) + 8000634: 4329 orrs r1, r5 + 8000636: 430b orrs r3, r1 + 8000638: 8013 strh r3, [r2, #0] + 800063a: 7aa3 ldrb r3, [r4, #10] + 800063c: 2b00 cmp r3, #0 + 800063e: d000 beq.n 8000642 + 8000640: e0b3 b.n 80007aa + 8000642: 7863 ldrb r3, [r4, #1] + 8000644: 2b00 cmp r3, #0 + 8000646: d100 bne.n 800064a + 8000648: e066 b.n 8000718 + 800064a: 6802 ldr r2, [r0, #0] + 800064c: 2350 movs r3, #80 ; 0x50 + 800064e: 5ad3 ldrh r3, [r2, r3] + 8000650: 7821 ldrb r1, [r4, #0] + 8000652: 00c9 lsls r1, r1, #3 + 8000654: 1852 adds r2, r2, r1 + 8000656: 189b adds r3, r3, r2 + 8000658: 2280 movs r2, #128 ; 0x80 + 800065a: 00d2 lsls r2, r2, #3 + 800065c: 4694 mov ip, r2 + 800065e: 4463 add r3, ip + 8000660: 88a2 ldrh r2, [r4, #4] + 8000662: 2101 movs r1, #1 + 8000664: 438a bics r2, r1 + 8000666: 801a strh r2, [r3, #0] + 8000668: 7823 ldrb r3, [r4, #0] + 800066a: 009b lsls r3, r3, #2 + 800066c: 6802 ldr r2, [r0, #0] + 800066e: 4694 mov ip, r2 + 8000670: 4463 add r3, ip + 8000672: 881a ldrh r2, [r3, #0] + 8000674: 0651 lsls r1, r2, #25 + 8000676: d504 bpl.n 8000682 + 8000678: 499e ldr r1, [pc, #632] ; (80008f4 ) + 800067a: 400a ands r2, r1 + 800067c: 499f ldr r1, [pc, #636] ; (80008fc ) + 800067e: 430a orrs r2, r1 + 8000680: 801a strh r2, [r3, #0] + 8000682: 7822 ldrb r2, [r4, #0] + 8000684: 0092 lsls r2, r2, #2 + 8000686: 6803 ldr r3, [r0, #0] + 8000688: 469c mov ip, r3 + 800068a: 4462 add r2, ip + 800068c: 8813 ldrh r3, [r2, #0] + 800068e: 499c ldr r1, [pc, #624] ; (8000900 ) + 8000690: 400b ands r3, r1 + 8000692: 2120 movs r1, #32 + 8000694: 404b eors r3, r1 + 8000696: 4998 ldr r1, [pc, #608] ; (80008f8 ) + 8000698: 430b orrs r3, r1 + 800069a: 8013 strh r3, [r2, #0] + 800069c: 23f4 movs r3, #244 ; 0xf4 + 800069e: 005b lsls r3, r3, #1 + 80006a0: 2200 movs r2, #0 + 80006a2: 54c2 strb r2, [r0, r3] + 80006a4: 2000 movs r0, #0 + 80006a6: bd70 pop {r4, r5, r6, pc} + 80006a8: 267f movs r6, #127 ; 0x7f + 80006aa: 400e ands r6, r1 + 80006ac: 00f4 lsls r4, r6, #3 + 80006ae: 1ba4 subs r4, r4, r6 + 80006b0: 00a4 lsls r4, r4, #2 + 80006b2: 3428 adds r4, #40 ; 0x28 + 80006b4: 1904 adds r4, r0, r4 + 80006b6: e799 b.n 80005ec + 80006b8: 7823 ldrb r3, [r4, #0] + 80006ba: 009b lsls r3, r3, #2 + 80006bc: 6802 ldr r2, [r0, #0] + 80006be: 4694 mov ip, r2 + 80006c0: 4463 add r3, ip + 80006c2: 881a ldrh r2, [r3, #0] + 80006c4: 498f ldr r1, [pc, #572] ; (8000904 ) + 80006c6: 4011 ands r1, r2 + 80006c8: 4a8f ldr r2, [pc, #572] ; (8000908 ) + 80006ca: 430a orrs r2, r1 + 80006cc: 801a strh r2, [r3, #0] + 80006ce: e7a8 b.n 8000622 + 80006d0: 7823 ldrb r3, [r4, #0] + 80006d2: 009b lsls r3, r3, #2 + 80006d4: 6802 ldr r2, [r0, #0] + 80006d6: 4694 mov ip, r2 + 80006d8: 4463 add r3, ip + 80006da: 881a ldrh r2, [r3, #0] + 80006dc: 4989 ldr r1, [pc, #548] ; (8000904 ) + 80006de: 4011 ands r1, r2 + 80006e0: 4a85 ldr r2, [pc, #532] ; (80008f8 ) + 80006e2: 430a orrs r2, r1 + 80006e4: 801a strh r2, [r3, #0] + 80006e6: e79c b.n 8000622 + 80006e8: 7823 ldrb r3, [r4, #0] + 80006ea: 009b lsls r3, r3, #2 + 80006ec: 6802 ldr r2, [r0, #0] + 80006ee: 4694 mov ip, r2 + 80006f0: 4463 add r3, ip + 80006f2: 881a ldrh r2, [r3, #0] + 80006f4: 4983 ldr r1, [pc, #524] ; (8000904 ) + 80006f6: 4011 ands r1, r2 + 80006f8: 4a84 ldr r2, [pc, #528] ; (800090c ) + 80006fa: 430a orrs r2, r1 + 80006fc: 801a strh r2, [r3, #0] + 80006fe: e790 b.n 8000622 + 8000700: 7823 ldrb r3, [r4, #0] + 8000702: 009b lsls r3, r3, #2 + 8000704: 6802 ldr r2, [r0, #0] + 8000706: 4694 mov ip, r2 + 8000708: 4463 add r3, ip + 800070a: 881a ldrh r2, [r3, #0] + 800070c: 497d ldr r1, [pc, #500] ; (8000904 ) + 800070e: 4011 ands r1, r2 + 8000710: 4a7f ldr r2, [pc, #508] ; (8000910 ) + 8000712: 430a orrs r2, r1 + 8000714: 801a strh r2, [r3, #0] + 8000716: e784 b.n 8000622 + 8000718: 6802 ldr r2, [r0, #0] + 800071a: 2550 movs r5, #80 ; 0x50 + 800071c: 5b53 ldrh r3, [r2, r5] + 800071e: 7821 ldrb r1, [r4, #0] + 8000720: 00c9 lsls r1, r1, #3 + 8000722: 1852 adds r2, r2, r1 + 8000724: 189b adds r3, r3, r2 + 8000726: 4a7b ldr r2, [pc, #492] ; (8000914 ) + 8000728: 4694 mov ip, r2 + 800072a: 4463 add r3, ip + 800072c: 88a2 ldrh r2, [r4, #4] + 800072e: 2101 movs r1, #1 + 8000730: 438a bics r2, r1 + 8000732: 801a strh r2, [r3, #0] + 8000734: 6803 ldr r3, [r0, #0] + 8000736: 5b5a ldrh r2, [r3, r5] + 8000738: 7821 ldrb r1, [r4, #0] + 800073a: 00c9 lsls r1, r1, #3 + 800073c: 1852 adds r2, r2, r1 + 800073e: 4976 ldr r1, [pc, #472] ; (8000918 ) + 8000740: 468c mov ip, r1 + 8000742: 4463 add r3, ip + 8000744: 18d3 adds r3, r2, r3 + 8000746: 68e2 ldr r2, [r4, #12] + 8000748: 2a3e cmp r2, #62 ; 0x3e + 800074a: d925 bls.n 8000798 + 800074c: 0951 lsrs r1, r2, #5 + 800074e: b289 uxth r1, r1 + 8000750: 06d2 lsls r2, r2, #27 + 8000752: d101 bne.n 8000758 + 8000754: 3901 subs r1, #1 + 8000756: b289 uxth r1, r1 + 8000758: 0289 lsls r1, r1, #10 + 800075a: 4a70 ldr r2, [pc, #448] ; (800091c ) + 800075c: 4311 orrs r1, r2 + 800075e: 8019 strh r1, [r3, #0] + 8000760: 7823 ldrb r3, [r4, #0] + 8000762: 009b lsls r3, r3, #2 + 8000764: 6802 ldr r2, [r0, #0] + 8000766: 4694 mov ip, r2 + 8000768: 4463 add r3, ip + 800076a: 881a ldrh r2, [r3, #0] + 800076c: 0451 lsls r1, r2, #17 + 800076e: d504 bpl.n 800077a + 8000770: 4960 ldr r1, [pc, #384] ; (80008f4 ) + 8000772: 400a ands r2, r1 + 8000774: 496a ldr r1, [pc, #424] ; (8000920 ) + 8000776: 430a orrs r2, r1 + 8000778: 801a strh r2, [r3, #0] + 800077a: 7823 ldrb r3, [r4, #0] + 800077c: 009b lsls r3, r3, #2 + 800077e: 6802 ldr r2, [r0, #0] + 8000780: 4694 mov ip, r2 + 8000782: 4463 add r3, ip + 8000784: 8819 ldrh r1, [r3, #0] + 8000786: 4a67 ldr r2, [pc, #412] ; (8000924 ) + 8000788: 4011 ands r1, r2 + 800078a: 22c0 movs r2, #192 ; 0xc0 + 800078c: 0192 lsls r2, r2, #6 + 800078e: 4051 eors r1, r2 + 8000790: 4a59 ldr r2, [pc, #356] ; (80008f8 ) + 8000792: 430a orrs r2, r1 + 8000794: 801a strh r2, [r3, #0] + 8000796: e781 b.n 800069c + 8000798: 0851 lsrs r1, r2, #1 + 800079a: b289 uxth r1, r1 + 800079c: 07d2 lsls r2, r2, #31 + 800079e: d501 bpl.n 80007a4 + 80007a0: 3101 adds r1, #1 + 80007a2: b289 uxth r1, r1 + 80007a4: 0289 lsls r1, r1, #10 + 80007a6: 8019 strh r1, [r3, #0] + 80007a8: e7da b.n 8000760 + 80007aa: 7823 ldrb r3, [r4, #0] + 80007ac: 009b lsls r3, r3, #2 + 80007ae: 6802 ldr r2, [r0, #0] + 80007b0: 4694 mov ip, r2 + 80007b2: 4463 add r3, ip + 80007b4: 881a ldrh r2, [r3, #0] + 80007b6: 495c ldr r1, [pc, #368] ; (8000928 ) + 80007b8: 4011 ands r1, r2 + 80007ba: 4a5c ldr r2, [pc, #368] ; (800092c ) + 80007bc: 430a orrs r2, r1 + 80007be: 801a strh r2, [r3, #0] + 80007c0: 6802 ldr r2, [r0, #0] + 80007c2: 2650 movs r6, #80 ; 0x50 + 80007c4: 5b93 ldrh r3, [r2, r6] + 80007c6: 7821 ldrb r1, [r4, #0] + 80007c8: 00c9 lsls r1, r1, #3 + 80007ca: 1852 adds r2, r2, r1 + 80007cc: 189b adds r3, r3, r2 + 80007ce: 2280 movs r2, #128 ; 0x80 + 80007d0: 00d2 lsls r2, r2, #3 + 80007d2: 4694 mov ip, r2 + 80007d4: 4463 add r3, ip + 80007d6: 88e2 ldrh r2, [r4, #6] + 80007d8: 2501 movs r5, #1 + 80007da: 43aa bics r2, r5 + 80007dc: 801a strh r2, [r3, #0] + 80007de: 6802 ldr r2, [r0, #0] + 80007e0: 5b93 ldrh r3, [r2, r6] + 80007e2: 7821 ldrb r1, [r4, #0] + 80007e4: 00c9 lsls r1, r1, #3 + 80007e6: 1852 adds r2, r2, r1 + 80007e8: 189b adds r3, r3, r2 + 80007ea: 4a4a ldr r2, [pc, #296] ; (8000914 ) + 80007ec: 4694 mov ip, r2 + 80007ee: 4463 add r3, ip + 80007f0: 8922 ldrh r2, [r4, #8] + 80007f2: 43aa bics r2, r5 + 80007f4: 801a strh r2, [r3, #0] + 80007f6: 7863 ldrb r3, [r4, #1] + 80007f8: 2b00 cmp r3, #0 + 80007fa: d13d bne.n 8000878 + 80007fc: 7823 ldrb r3, [r4, #0] + 80007fe: 009b lsls r3, r3, #2 + 8000800: 6802 ldr r2, [r0, #0] + 8000802: 4694 mov ip, r2 + 8000804: 4463 add r3, ip + 8000806: 881a ldrh r2, [r3, #0] + 8000808: 0451 lsls r1, r2, #17 + 800080a: d504 bpl.n 8000816 + 800080c: 4939 ldr r1, [pc, #228] ; (80008f4 ) + 800080e: 400a ands r2, r1 + 8000810: 4943 ldr r1, [pc, #268] ; (8000920 ) + 8000812: 430a orrs r2, r1 + 8000814: 801a strh r2, [r3, #0] + 8000816: 7823 ldrb r3, [r4, #0] + 8000818: 009b lsls r3, r3, #2 + 800081a: 6802 ldr r2, [r0, #0] + 800081c: 4694 mov ip, r2 + 800081e: 4463 add r3, ip + 8000820: 881a ldrh r2, [r3, #0] + 8000822: 0651 lsls r1, r2, #25 + 8000824: d504 bpl.n 8000830 + 8000826: 4933 ldr r1, [pc, #204] ; (80008f4 ) + 8000828: 400a ands r2, r1 + 800082a: 4934 ldr r1, [pc, #208] ; (80008fc ) + 800082c: 430a orrs r2, r1 + 800082e: 801a strh r2, [r3, #0] + 8000830: 7823 ldrb r3, [r4, #0] + 8000832: 009b lsls r3, r3, #2 + 8000834: 6802 ldr r2, [r0, #0] + 8000836: 4694 mov ip, r2 + 8000838: 4463 add r3, ip + 800083a: 881a ldrh r2, [r3, #0] + 800083c: 492d ldr r1, [pc, #180] ; (80008f4 ) + 800083e: 4011 ands r1, r2 + 8000840: 4a2e ldr r2, [pc, #184] ; (80008fc ) + 8000842: 430a orrs r2, r1 + 8000844: 801a strh r2, [r3, #0] + 8000846: 7821 ldrb r1, [r4, #0] + 8000848: 0089 lsls r1, r1, #2 + 800084a: 6803 ldr r3, [r0, #0] + 800084c: 469c mov ip, r3 + 800084e: 4461 add r1, ip + 8000850: 880b ldrh r3, [r1, #0] + 8000852: 4a34 ldr r2, [pc, #208] ; (8000924 ) + 8000854: 401a ands r2, r3 + 8000856: 23c0 movs r3, #192 ; 0xc0 + 8000858: 019b lsls r3, r3, #6 + 800085a: 4053 eors r3, r2 + 800085c: 4a26 ldr r2, [pc, #152] ; (80008f8 ) + 800085e: 4313 orrs r3, r2 + 8000860: 800b strh r3, [r1, #0] + 8000862: 7823 ldrb r3, [r4, #0] + 8000864: 009b lsls r3, r3, #2 + 8000866: 6801 ldr r1, [r0, #0] + 8000868: 468c mov ip, r1 + 800086a: 4463 add r3, ip + 800086c: 8819 ldrh r1, [r3, #0] + 800086e: 4c24 ldr r4, [pc, #144] ; (8000900 ) + 8000870: 4021 ands r1, r4 + 8000872: 430a orrs r2, r1 + 8000874: 801a strh r2, [r3, #0] + 8000876: e711 b.n 800069c + 8000878: 7823 ldrb r3, [r4, #0] + 800087a: 009b lsls r3, r3, #2 + 800087c: 6802 ldr r2, [r0, #0] + 800087e: 4694 mov ip, r2 + 8000880: 4463 add r3, ip + 8000882: 881a ldrh r2, [r3, #0] + 8000884: 0451 lsls r1, r2, #17 + 8000886: d504 bpl.n 8000892 + 8000888: 491a ldr r1, [pc, #104] ; (80008f4 ) + 800088a: 400a ands r2, r1 + 800088c: 4924 ldr r1, [pc, #144] ; (8000920 ) + 800088e: 430a orrs r2, r1 + 8000890: 801a strh r2, [r3, #0] + 8000892: 7823 ldrb r3, [r4, #0] + 8000894: 009b lsls r3, r3, #2 + 8000896: 6802 ldr r2, [r0, #0] + 8000898: 4694 mov ip, r2 + 800089a: 4463 add r3, ip + 800089c: 881a ldrh r2, [r3, #0] + 800089e: 0651 lsls r1, r2, #25 + 80008a0: d504 bpl.n 80008ac + 80008a2: 4914 ldr r1, [pc, #80] ; (80008f4 ) + 80008a4: 400a ands r2, r1 + 80008a6: 4915 ldr r1, [pc, #84] ; (80008fc ) + 80008a8: 430a orrs r2, r1 + 80008aa: 801a strh r2, [r3, #0] + 80008ac: 7823 ldrb r3, [r4, #0] + 80008ae: 009b lsls r3, r3, #2 + 80008b0: 6802 ldr r2, [r0, #0] + 80008b2: 4694 mov ip, r2 + 80008b4: 4463 add r3, ip + 80008b6: 881a ldrh r2, [r3, #0] + 80008b8: 490e ldr r1, [pc, #56] ; (80008f4 ) + 80008ba: 4011 ands r1, r2 + 80008bc: 4a18 ldr r2, [pc, #96] ; (8000920 ) + 80008be: 430a orrs r2, r1 + 80008c0: 801a strh r2, [r3, #0] + 80008c2: 7821 ldrb r1, [r4, #0] + 80008c4: 0089 lsls r1, r1, #2 + 80008c6: 6803 ldr r3, [r0, #0] + 80008c8: 469c mov ip, r3 + 80008ca: 4461 add r1, ip + 80008cc: 880b ldrh r3, [r1, #0] + 80008ce: 4a0c ldr r2, [pc, #48] ; (8000900 ) + 80008d0: 4013 ands r3, r2 + 80008d2: 4a09 ldr r2, [pc, #36] ; (80008f8 ) + 80008d4: 4313 orrs r3, r2 + 80008d6: 800b strh r3, [r1, #0] + 80008d8: 7823 ldrb r3, [r4, #0] + 80008da: 009b lsls r3, r3, #2 + 80008dc: 6801 ldr r1, [r0, #0] + 80008de: 468c mov ip, r1 + 80008e0: 4463 add r3, ip + 80008e2: 8819 ldrh r1, [r3, #0] + 80008e4: 4c0f ldr r4, [pc, #60] ; (8000924 ) + 80008e6: 4021 ands r1, r4 + 80008e8: 430a orrs r2, r1 + 80008ea: 801a strh r2, [r3, #0] + 80008ec: e6d6 b.n 800069c + 80008ee: 2002 movs r0, #2 + 80008f0: e6d9 b.n 80006a6 + 80008f2: 46c0 nop ; (mov r8, r8) + 80008f4: 00000f0f .word 0x00000f0f + 80008f8: ffff8080 .word 0xffff8080 + 80008fc: ffff80c0 .word 0xffff80c0 + 8000900: ffff8fbf .word 0xffff8fbf + 8000904: 0000090f .word 0x0000090f + 8000908: ffff8280 .word 0xffff8280 + 800090c: ffff8680 .word 0xffff8680 + 8000910: ffff8480 .word 0xffff8480 + 8000914: 00000404 .word 0x00000404 + 8000918: 00000406 .word 0x00000406 + 800091c: ffff8000 .word 0xffff8000 + 8000920: ffffc080 .word 0xffffc080 + 8000924: ffffbf8f .word 0xffffbf8f + 8000928: 00000e0f .word 0x00000e0f + 800092c: ffff8180 .word 0xffff8180 + +08000930 : + 8000930: b510 push {r4, lr} + 8000932: b24a sxtb r2, r1 + 8000934: 2a00 cmp r2, #0 + 8000936: db3a blt.n 80009ae + 8000938: 247f movs r4, #127 ; 0x7f + 800093a: 400c ands r4, r1 + 800093c: 00e3 lsls r3, r4, #3 + 800093e: 1b1b subs r3, r3, r4 + 8000940: 009b lsls r3, r3, #2 + 8000942: 3309 adds r3, #9 + 8000944: 33ff adds r3, #255 ; 0xff + 8000946: 18c3 adds r3, r0, r3 + 8000948: 247f movs r4, #127 ; 0x7f + 800094a: 4021 ands r1, r4 + 800094c: 7019 strb r1, [r3, #0] + 800094e: 0fd2 lsrs r2, r2, #31 + 8000950: 705a strb r2, [r3, #1] + 8000952: 22f4 movs r2, #244 ; 0xf4 + 8000954: 0052 lsls r2, r2, #1 + 8000956: 5c82 ldrb r2, [r0, r2] + 8000958: 2a01 cmp r2, #1 + 800095a: d100 bne.n 800095e + 800095c: e0c1 b.n 8000ae2 + 800095e: 22f4 movs r2, #244 ; 0xf4 + 8000960: 0052 lsls r2, r2, #1 + 8000962: 2101 movs r1, #1 + 8000964: 5481 strb r1, [r0, r2] + 8000966: 7a9a ldrb r2, [r3, #10] + 8000968: 2a00 cmp r2, #0 + 800096a: d141 bne.n 80009f0 + 800096c: 785a ldrb r2, [r3, #1] + 800096e: 2a00 cmp r2, #0 + 8000970: d025 beq.n 80009be + 8000972: 781a ldrb r2, [r3, #0] + 8000974: 0092 lsls r2, r2, #2 + 8000976: 6801 ldr r1, [r0, #0] + 8000978: 468c mov ip, r1 + 800097a: 4462 add r2, ip + 800097c: 8811 ldrh r1, [r2, #0] + 800097e: 064c lsls r4, r1, #25 + 8000980: d504 bpl.n 800098c + 8000982: 4c59 ldr r4, [pc, #356] ; (8000ae8 ) + 8000984: 4021 ands r1, r4 + 8000986: 4c59 ldr r4, [pc, #356] ; (8000aec ) + 8000988: 4321 orrs r1, r4 + 800098a: 8011 strh r1, [r2, #0] + 800098c: 781b ldrb r3, [r3, #0] + 800098e: 009b lsls r3, r3, #2 + 8000990: 6802 ldr r2, [r0, #0] + 8000992: 4694 mov ip, r2 + 8000994: 4463 add r3, ip + 8000996: 881a ldrh r2, [r3, #0] + 8000998: 4955 ldr r1, [pc, #340] ; (8000af0 ) + 800099a: 4011 ands r1, r2 + 800099c: 4a55 ldr r2, [pc, #340] ; (8000af4 ) + 800099e: 430a orrs r2, r1 + 80009a0: 801a strh r2, [r3, #0] + 80009a2: 23f4 movs r3, #244 ; 0xf4 + 80009a4: 005b lsls r3, r3, #1 + 80009a6: 2200 movs r2, #0 + 80009a8: 54c2 strb r2, [r0, r3] + 80009aa: 2000 movs r0, #0 + 80009ac: bd10 pop {r4, pc} + 80009ae: 247f movs r4, #127 ; 0x7f + 80009b0: 400c ands r4, r1 + 80009b2: 00e3 lsls r3, r4, #3 + 80009b4: 1b1b subs r3, r3, r4 + 80009b6: 009b lsls r3, r3, #2 + 80009b8: 3328 adds r3, #40 ; 0x28 + 80009ba: 18c3 adds r3, r0, r3 + 80009bc: e7c4 b.n 8000948 + 80009be: 781a ldrb r2, [r3, #0] + 80009c0: 0092 lsls r2, r2, #2 + 80009c2: 6801 ldr r1, [r0, #0] + 80009c4: 468c mov ip, r1 + 80009c6: 4462 add r2, ip + 80009c8: 8811 ldrh r1, [r2, #0] + 80009ca: 044c lsls r4, r1, #17 + 80009cc: d504 bpl.n 80009d8 + 80009ce: 4c46 ldr r4, [pc, #280] ; (8000ae8 ) + 80009d0: 4021 ands r1, r4 + 80009d2: 4c49 ldr r4, [pc, #292] ; (8000af8 ) + 80009d4: 4321 orrs r1, r4 + 80009d6: 8011 strh r1, [r2, #0] + 80009d8: 781b ldrb r3, [r3, #0] + 80009da: 009b lsls r3, r3, #2 + 80009dc: 6802 ldr r2, [r0, #0] + 80009de: 4694 mov ip, r2 + 80009e0: 4463 add r3, ip + 80009e2: 881a ldrh r2, [r3, #0] + 80009e4: 4945 ldr r1, [pc, #276] ; (8000afc ) + 80009e6: 4011 ands r1, r2 + 80009e8: 4a42 ldr r2, [pc, #264] ; (8000af4 ) + 80009ea: 430a orrs r2, r1 + 80009ec: 801a strh r2, [r3, #0] + 80009ee: e7d8 b.n 80009a2 + 80009f0: 785a ldrb r2, [r3, #1] + 80009f2: 2a00 cmp r2, #0 + 80009f4: d13a bne.n 8000a6c + 80009f6: 781a ldrb r2, [r3, #0] + 80009f8: 0092 lsls r2, r2, #2 + 80009fa: 6801 ldr r1, [r0, #0] + 80009fc: 468c mov ip, r1 + 80009fe: 4462 add r2, ip + 8000a00: 8811 ldrh r1, [r2, #0] + 8000a02: 044c lsls r4, r1, #17 + 8000a04: d504 bpl.n 8000a10 + 8000a06: 4c38 ldr r4, [pc, #224] ; (8000ae8 ) + 8000a08: 4021 ands r1, r4 + 8000a0a: 4c3b ldr r4, [pc, #236] ; (8000af8 ) + 8000a0c: 4321 orrs r1, r4 + 8000a0e: 8011 strh r1, [r2, #0] + 8000a10: 781a ldrb r2, [r3, #0] + 8000a12: 0092 lsls r2, r2, #2 + 8000a14: 6801 ldr r1, [r0, #0] + 8000a16: 468c mov ip, r1 + 8000a18: 4462 add r2, ip + 8000a1a: 8811 ldrh r1, [r2, #0] + 8000a1c: 064c lsls r4, r1, #25 + 8000a1e: d504 bpl.n 8000a2a + 8000a20: 4c31 ldr r4, [pc, #196] ; (8000ae8 ) + 8000a22: 4021 ands r1, r4 + 8000a24: 4c31 ldr r4, [pc, #196] ; (8000aec ) + 8000a26: 4321 orrs r1, r4 + 8000a28: 8011 strh r1, [r2, #0] + 8000a2a: 781a ldrb r2, [r3, #0] + 8000a2c: 0092 lsls r2, r2, #2 + 8000a2e: 6801 ldr r1, [r0, #0] + 8000a30: 468c mov ip, r1 + 8000a32: 4462 add r2, ip + 8000a34: 8811 ldrh r1, [r2, #0] + 8000a36: 4c2c ldr r4, [pc, #176] ; (8000ae8 ) + 8000a38: 400c ands r4, r1 + 8000a3a: 492c ldr r1, [pc, #176] ; (8000aec ) + 8000a3c: 4321 orrs r1, r4 + 8000a3e: 8011 strh r1, [r2, #0] + 8000a40: 781c ldrb r4, [r3, #0] + 8000a42: 00a4 lsls r4, r4, #2 + 8000a44: 6802 ldr r2, [r0, #0] + 8000a46: 4694 mov ip, r2 + 8000a48: 4464 add r4, ip + 8000a4a: 8822 ldrh r2, [r4, #0] + 8000a4c: 492b ldr r1, [pc, #172] ; (8000afc ) + 8000a4e: 400a ands r2, r1 + 8000a50: 4928 ldr r1, [pc, #160] ; (8000af4 ) + 8000a52: 430a orrs r2, r1 + 8000a54: 8022 strh r2, [r4, #0] + 8000a56: 781b ldrb r3, [r3, #0] + 8000a58: 009b lsls r3, r3, #2 + 8000a5a: 6802 ldr r2, [r0, #0] + 8000a5c: 4694 mov ip, r2 + 8000a5e: 4463 add r3, ip + 8000a60: 881a ldrh r2, [r3, #0] + 8000a62: 4c23 ldr r4, [pc, #140] ; (8000af0 ) + 8000a64: 4022 ands r2, r4 + 8000a66: 4311 orrs r1, r2 + 8000a68: 8019 strh r1, [r3, #0] + 8000a6a: e79a b.n 80009a2 + 8000a6c: 781a ldrb r2, [r3, #0] + 8000a6e: 0092 lsls r2, r2, #2 + 8000a70: 6801 ldr r1, [r0, #0] + 8000a72: 468c mov ip, r1 + 8000a74: 4462 add r2, ip + 8000a76: 8811 ldrh r1, [r2, #0] + 8000a78: 044c lsls r4, r1, #17 + 8000a7a: d504 bpl.n 8000a86 + 8000a7c: 4c1a ldr r4, [pc, #104] ; (8000ae8 ) + 8000a7e: 4021 ands r1, r4 + 8000a80: 4c1d ldr r4, [pc, #116] ; (8000af8 ) + 8000a82: 4321 orrs r1, r4 + 8000a84: 8011 strh r1, [r2, #0] + 8000a86: 781a ldrb r2, [r3, #0] + 8000a88: 0092 lsls r2, r2, #2 + 8000a8a: 6801 ldr r1, [r0, #0] + 8000a8c: 468c mov ip, r1 + 8000a8e: 4462 add r2, ip + 8000a90: 8811 ldrh r1, [r2, #0] + 8000a92: 064c lsls r4, r1, #25 + 8000a94: d504 bpl.n 8000aa0 + 8000a96: 4c14 ldr r4, [pc, #80] ; (8000ae8 ) + 8000a98: 4021 ands r1, r4 + 8000a9a: 4c14 ldr r4, [pc, #80] ; (8000aec ) + 8000a9c: 4321 orrs r1, r4 + 8000a9e: 8011 strh r1, [r2, #0] + 8000aa0: 781a ldrb r2, [r3, #0] + 8000aa2: 0092 lsls r2, r2, #2 + 8000aa4: 6801 ldr r1, [r0, #0] + 8000aa6: 468c mov ip, r1 + 8000aa8: 4462 add r2, ip + 8000aaa: 8811 ldrh r1, [r2, #0] + 8000aac: 4c0e ldr r4, [pc, #56] ; (8000ae8 ) + 8000aae: 400c ands r4, r1 + 8000ab0: 4911 ldr r1, [pc, #68] ; (8000af8 ) + 8000ab2: 4321 orrs r1, r4 + 8000ab4: 8011 strh r1, [r2, #0] + 8000ab6: 781c ldrb r4, [r3, #0] + 8000ab8: 00a4 lsls r4, r4, #2 + 8000aba: 6802 ldr r2, [r0, #0] + 8000abc: 4694 mov ip, r2 + 8000abe: 4464 add r4, ip + 8000ac0: 8822 ldrh r2, [r4, #0] + 8000ac2: 490b ldr r1, [pc, #44] ; (8000af0 ) + 8000ac4: 400a ands r2, r1 + 8000ac6: 490b ldr r1, [pc, #44] ; (8000af4 ) + 8000ac8: 430a orrs r2, r1 + 8000aca: 8022 strh r2, [r4, #0] + 8000acc: 781b ldrb r3, [r3, #0] + 8000ace: 009b lsls r3, r3, #2 + 8000ad0: 6802 ldr r2, [r0, #0] + 8000ad2: 4694 mov ip, r2 + 8000ad4: 4463 add r3, ip + 8000ad6: 881a ldrh r2, [r3, #0] + 8000ad8: 4c08 ldr r4, [pc, #32] ; (8000afc ) + 8000ada: 4022 ands r2, r4 + 8000adc: 4311 orrs r1, r2 + 8000ade: 8019 strh r1, [r3, #0] + 8000ae0: e75f b.n 80009a2 + 8000ae2: 2002 movs r0, #2 + 8000ae4: e762 b.n 80009ac + 8000ae6: 46c0 nop ; (mov r8, r8) + 8000ae8: 00000f0f .word 0x00000f0f + 8000aec: ffff80c0 .word 0xffff80c0 + 8000af0: ffff8fbf .word 0xffff8fbf + 8000af4: ffff8080 .word 0xffff8080 + 8000af8: ffffc080 .word 0xffffc080 + 8000afc: ffffbf8f .word 0xffffbf8f + +08000b00 : + 8000b00: b570 push {r4, r5, r6, lr} + 8000b02: 247f movs r4, #127 ; 0x7f + 8000b04: 4021 ands r1, r4 + 8000b06: 00cc lsls r4, r1, #3 + 8000b08: 1a64 subs r4, r4, r1 + 8000b0a: 00a4 lsls r4, r4, #2 + 8000b0c: 1904 adds r4, r0, r4 + 8000b0e: 0025 movs r5, r4 + 8000b10: 3519 adds r5, #25 + 8000b12: 35ff adds r5, #255 ; 0xff + 8000b14: 602a str r2, [r5, #0] + 8000b16: 0022 movs r2, r4 + 8000b18: 321d adds r2, #29 + 8000b1a: 32ff adds r2, #255 ; 0xff + 8000b1c: 6013 str r3, [r2, #0] + 8000b1e: 3508 adds r5, #8 + 8000b20: 2200 movs r2, #0 + 8000b22: 602a str r2, [r5, #0] + 8000b24: 3d17 subs r5, #23 + 8000b26: 702a strb r2, [r5, #0] + 8000b28: 0022 movs r2, r4 + 8000b2a: 3209 adds r2, #9 + 8000b2c: 32ff adds r2, #255 ; 0xff + 8000b2e: 7011 strb r1, [r2, #0] + 8000b30: 3415 adds r4, #21 + 8000b32: 34ff adds r4, #255 ; 0xff + 8000b34: 6822 ldr r2, [r4, #0] + 8000b36: 4293 cmp r3, r2 + 8000b38: d941 bls.n 8000bbe + 8000b3a: 00cc lsls r4, r1, #3 + 8000b3c: 1a64 subs r4, r4, r1 + 8000b3e: 00a4 lsls r4, r4, #2 + 8000b40: 1904 adds r4, r0, r4 + 8000b42: 341d adds r4, #29 + 8000b44: 34ff adds r4, #255 ; 0xff + 8000b46: 1a9b subs r3, r3, r2 + 8000b48: 6023 str r3, [r4, #0] + 8000b4a: 00cb lsls r3, r1, #3 + 8000b4c: 1a5b subs r3, r3, r1 + 8000b4e: 009b lsls r3, r3, #2 + 8000b50: 18c3 adds r3, r0, r3 + 8000b52: 3313 adds r3, #19 + 8000b54: 33ff adds r3, #255 ; 0xff + 8000b56: 781b ldrb r3, [r3, #0] + 8000b58: 2b00 cmp r3, #0 + 8000b5a: d143 bne.n 8000be4 + 8000b5c: 6804 ldr r4, [r0, #0] + 8000b5e: 3350 adds r3, #80 ; 0x50 + 8000b60: 5ae5 ldrh r5, [r4, r3] + 8000b62: 00cb lsls r3, r1, #3 + 8000b64: 1a5b subs r3, r3, r1 + 8000b66: 009b lsls r3, r3, #2 + 8000b68: 18c3 adds r3, r0, r3 + 8000b6a: 3309 adds r3, #9 + 8000b6c: 33ff adds r3, #255 ; 0xff + 8000b6e: 781b ldrb r3, [r3, #0] + 8000b70: 00db lsls r3, r3, #3 + 8000b72: 18eb adds r3, r5, r3 + 8000b74: 4d76 ldr r5, [pc, #472] ; (8000d50 ) + 8000b76: 46ac mov ip, r5 + 8000b78: 4464 add r4, ip + 8000b7a: 191c adds r4, r3, r4 + 8000b7c: 2a3e cmp r2, #62 ; 0x3e + 8000b7e: d928 bls.n 8000bd2 + 8000b80: 0953 lsrs r3, r2, #5 + 8000b82: b29b uxth r3, r3 + 8000b84: 06d2 lsls r2, r2, #27 + 8000b86: d101 bne.n 8000b8c + 8000b88: 3b01 subs r3, #1 + 8000b8a: b29b uxth r3, r3 + 8000b8c: 029b lsls r3, r3, #10 + 8000b8e: 4a71 ldr r2, [pc, #452] ; (8000d54 ) + 8000b90: 4313 orrs r3, r2 + 8000b92: 8023 strh r3, [r4, #0] + 8000b94: 00cb lsls r3, r1, #3 + 8000b96: 1a59 subs r1, r3, r1 + 8000b98: 0089 lsls r1, r1, #2 + 8000b9a: 1841 adds r1, r0, r1 + 8000b9c: 3109 adds r1, #9 + 8000b9e: 31ff adds r1, #255 ; 0xff + 8000ba0: 780a ldrb r2, [r1, #0] + 8000ba2: 0092 lsls r2, r2, #2 + 8000ba4: 6803 ldr r3, [r0, #0] + 8000ba6: 189b adds r3, r3, r2 + 8000ba8: 8819 ldrh r1, [r3, #0] + 8000baa: 4a6b ldr r2, [pc, #428] ; (8000d58 ) + 8000bac: 4011 ands r1, r2 + 8000bae: 22c0 movs r2, #192 ; 0xc0 + 8000bb0: 0192 lsls r2, r2, #6 + 8000bb2: 4051 eors r1, r2 + 8000bb4: 4a69 ldr r2, [pc, #420] ; (8000d5c ) + 8000bb6: 430a orrs r2, r1 + 8000bb8: 801a strh r2, [r3, #0] + 8000bba: 2000 movs r0, #0 + 8000bbc: bd70 pop {r4, r5, r6, pc} + 8000bbe: 00ca lsls r2, r1, #3 + 8000bc0: 1a52 subs r2, r2, r1 + 8000bc2: 0092 lsls r2, r2, #2 + 8000bc4: 1882 adds r2, r0, r2 + 8000bc6: 321d adds r2, #29 + 8000bc8: 32ff adds r2, #255 ; 0xff + 8000bca: 2400 movs r4, #0 + 8000bcc: 6014 str r4, [r2, #0] + 8000bce: 001a movs r2, r3 + 8000bd0: e7bb b.n 8000b4a + 8000bd2: 0853 lsrs r3, r2, #1 + 8000bd4: b29b uxth r3, r3 + 8000bd6: 07d2 lsls r2, r2, #31 + 8000bd8: d501 bpl.n 8000bde + 8000bda: 3301 adds r3, #1 + 8000bdc: b29b uxth r3, r3 + 8000bde: 029b lsls r3, r3, #10 + 8000be0: 8023 strh r3, [r4, #0] + 8000be2: e7d7 b.n 8000b94 + 8000be4: 00cb lsls r3, r1, #3 + 8000be6: 1a5b subs r3, r3, r1 + 8000be8: 009b lsls r3, r3, #2 + 8000bea: 18c3 adds r3, r0, r3 + 8000bec: 330a adds r3, #10 + 8000bee: 33ff adds r3, #255 ; 0xff + 8000bf0: 781b ldrb r3, [r3, #0] + 8000bf2: 2b00 cmp r3, #0 + 8000bf4: d169 bne.n 8000cca + 8000bf6: 6804 ldr r4, [r0, #0] + 8000bf8: 3350 adds r3, #80 ; 0x50 + 8000bfa: 5ae5 ldrh r5, [r4, r3] + 8000bfc: 00cb lsls r3, r1, #3 + 8000bfe: 1a5b subs r3, r3, r1 + 8000c00: 009b lsls r3, r3, #2 + 8000c02: 18c3 adds r3, r0, r3 + 8000c04: 3309 adds r3, #9 + 8000c06: 33ff adds r3, #255 ; 0xff + 8000c08: 781b ldrb r3, [r3, #0] + 8000c0a: 00db lsls r3, r3, #3 + 8000c0c: 18eb adds r3, r5, r3 + 8000c0e: 4d54 ldr r5, [pc, #336] ; (8000d60 ) + 8000c10: 46ac mov ip, r5 + 8000c12: 4464 add r4, ip + 8000c14: 191c adds r4, r3, r4 + 8000c16: 2a3e cmp r2, #62 ; 0x3e + 8000c18: d92d bls.n 8000c76 + 8000c1a: 0953 lsrs r3, r2, #5 + 8000c1c: b29b uxth r3, r3 + 8000c1e: 06d5 lsls r5, r2, #27 + 8000c20: d101 bne.n 8000c26 + 8000c22: 3b01 subs r3, #1 + 8000c24: b29b uxth r3, r3 + 8000c26: 029b lsls r3, r3, #10 + 8000c28: 4d4a ldr r5, [pc, #296] ; (8000d54 ) + 8000c2a: 432b orrs r3, r5 + 8000c2c: 8023 strh r3, [r4, #0] + 8000c2e: 00cb lsls r3, r1, #3 + 8000c30: 1a5b subs r3, r3, r1 + 8000c32: 009b lsls r3, r3, #2 + 8000c34: 18c3 adds r3, r0, r3 + 8000c36: 330a adds r3, #10 + 8000c38: 33ff adds r3, #255 ; 0xff + 8000c3a: 781b ldrb r3, [r3, #0] + 8000c3c: 2b00 cmp r3, #0 + 8000c3e: d171 bne.n 8000d24 + 8000c40: 6805 ldr r5, [r0, #0] + 8000c42: 2350 movs r3, #80 ; 0x50 + 8000c44: 5aec ldrh r4, [r5, r3] + 8000c46: 00cb lsls r3, r1, #3 + 8000c48: 1a5b subs r3, r3, r1 + 8000c4a: 009b lsls r3, r3, #2 + 8000c4c: 18c3 adds r3, r0, r3 + 8000c4e: 3309 adds r3, #9 + 8000c50: 33ff adds r3, #255 ; 0xff + 8000c52: 781b ldrb r3, [r3, #0] + 8000c54: 00db lsls r3, r3, #3 + 8000c56: 18e4 adds r4, r4, r3 + 8000c58: 4b3d ldr r3, [pc, #244] ; (8000d50 ) + 8000c5a: 469c mov ip, r3 + 8000c5c: 4465 add r5, ip + 8000c5e: 1964 adds r4, r4, r5 + 8000c60: 0953 lsrs r3, r2, #5 + 8000c62: b29b uxth r3, r3 + 8000c64: 06d2 lsls r2, r2, #27 + 8000c66: d101 bne.n 8000c6c + 8000c68: 3b01 subs r3, #1 + 8000c6a: b29b uxth r3, r3 + 8000c6c: 029b lsls r3, r3, #10 + 8000c6e: 4a39 ldr r2, [pc, #228] ; (8000d54 ) + 8000c70: 4313 orrs r3, r2 + 8000c72: 8023 strh r3, [r4, #0] + 8000c74: e78e b.n 8000b94 + 8000c76: 0853 lsrs r3, r2, #1 + 8000c78: b29b uxth r3, r3 + 8000c7a: 07d5 lsls r5, r2, #31 + 8000c7c: d501 bpl.n 8000c82 + 8000c7e: 3301 adds r3, #1 + 8000c80: b29b uxth r3, r3 + 8000c82: 029b lsls r3, r3, #10 + 8000c84: 8023 strh r3, [r4, #0] + 8000c86: 00cb lsls r3, r1, #3 + 8000c88: 1a5b subs r3, r3, r1 + 8000c8a: 009b lsls r3, r3, #2 + 8000c8c: 18c3 adds r3, r0, r3 + 8000c8e: 330a adds r3, #10 + 8000c90: 33ff adds r3, #255 ; 0xff + 8000c92: 781b ldrb r3, [r3, #0] + 8000c94: 2b00 cmp r3, #0 + 8000c96: d145 bne.n 8000d24 + 8000c98: 6805 ldr r5, [r0, #0] + 8000c9a: 2350 movs r3, #80 ; 0x50 + 8000c9c: 5aec ldrh r4, [r5, r3] + 8000c9e: 00cb lsls r3, r1, #3 + 8000ca0: 1a5b subs r3, r3, r1 + 8000ca2: 009b lsls r3, r3, #2 + 8000ca4: 18c3 adds r3, r0, r3 + 8000ca6: 3309 adds r3, #9 + 8000ca8: 33ff adds r3, #255 ; 0xff + 8000caa: 781b ldrb r3, [r3, #0] + 8000cac: 00db lsls r3, r3, #3 + 8000cae: 18e4 adds r4, r4, r3 + 8000cb0: 4b27 ldr r3, [pc, #156] ; (8000d50 ) + 8000cb2: 469c mov ip, r3 + 8000cb4: 4465 add r5, ip + 8000cb6: 1964 adds r4, r4, r5 + 8000cb8: 0853 lsrs r3, r2, #1 + 8000cba: b29b uxth r3, r3 + 8000cbc: 07d2 lsls r2, r2, #31 + 8000cbe: d501 bpl.n 8000cc4 + 8000cc0: 3301 adds r3, #1 + 8000cc2: b29b uxth r3, r3 + 8000cc4: 029b lsls r3, r3, #10 + 8000cc6: 8023 strh r3, [r4, #0] + 8000cc8: e764 b.n 8000b94 + 8000cca: 2b01 cmp r3, #1 + 8000ccc: d000 beq.n 8000cd0 + 8000cce: e761 b.n 8000b94 + 8000cd0: 6805 ldr r5, [r0, #0] + 8000cd2: 334f adds r3, #79 ; 0x4f + 8000cd4: 5aec ldrh r4, [r5, r3] + 8000cd6: 00cb lsls r3, r1, #3 + 8000cd8: 1a5b subs r3, r3, r1 + 8000cda: 009b lsls r3, r3, #2 + 8000cdc: 18c3 adds r3, r0, r3 + 8000cde: 001e movs r6, r3 + 8000ce0: 3609 adds r6, #9 + 8000ce2: 36ff adds r6, #255 ; 0xff + 8000ce4: 7836 ldrb r6, [r6, #0] + 8000ce6: 00f6 lsls r6, r6, #3 + 8000ce8: 19ad adds r5, r5, r6 + 8000cea: 1964 adds r4, r4, r5 + 8000cec: 4d1c ldr r5, [pc, #112] ; (8000d60 ) + 8000cee: 46ac mov ip, r5 + 8000cf0: 4464 add r4, ip + 8000cf2: 8022 strh r2, [r4, #0] + 8000cf4: 330a adds r3, #10 + 8000cf6: 33ff adds r3, #255 ; 0xff + 8000cf8: 781b ldrb r3, [r3, #0] + 8000cfa: 2b00 cmp r3, #0 + 8000cfc: d112 bne.n 8000d24 + 8000cfe: 6805 ldr r5, [r0, #0] + 8000d00: 3350 adds r3, #80 ; 0x50 + 8000d02: 5aec ldrh r4, [r5, r3] + 8000d04: 00cb lsls r3, r1, #3 + 8000d06: 1a5b subs r3, r3, r1 + 8000d08: 009b lsls r3, r3, #2 + 8000d0a: 18c3 adds r3, r0, r3 + 8000d0c: 3309 adds r3, #9 + 8000d0e: 33ff adds r3, #255 ; 0xff + 8000d10: 781b ldrb r3, [r3, #0] + 8000d12: 00db lsls r3, r3, #3 + 8000d14: 18e4 adds r4, r4, r3 + 8000d16: 4b0e ldr r3, [pc, #56] ; (8000d50 ) + 8000d18: 469c mov ip, r3 + 8000d1a: 4465 add r5, ip + 8000d1c: 1964 adds r4, r4, r5 + 8000d1e: 2a3e cmp r2, #62 ; 0x3e + 8000d20: d9ca bls.n 8000cb8 + 8000d22: e79d b.n 8000c60 + 8000d24: 2b01 cmp r3, #1 + 8000d26: d000 beq.n 8000d2a + 8000d28: e734 b.n 8000b94 + 8000d2a: 6804 ldr r4, [r0, #0] + 8000d2c: 334f adds r3, #79 ; 0x4f + 8000d2e: 5ae5 ldrh r5, [r4, r3] + 8000d30: 00cb lsls r3, r1, #3 + 8000d32: 1a5b subs r3, r3, r1 + 8000d34: 009b lsls r3, r3, #2 + 8000d36: 18c3 adds r3, r0, r3 + 8000d38: 3309 adds r3, #9 + 8000d3a: 33ff adds r3, #255 ; 0xff + 8000d3c: 781b ldrb r3, [r3, #0] + 8000d3e: 00db lsls r3, r3, #3 + 8000d40: 18e4 adds r4, r4, r3 + 8000d42: 192c adds r4, r5, r4 + 8000d44: 4b02 ldr r3, [pc, #8] ; (8000d50 ) + 8000d46: 469c mov ip, r3 + 8000d48: 4464 add r4, ip + 8000d4a: 8022 strh r2, [r4, #0] + 8000d4c: e722 b.n 8000b94 + 8000d4e: 46c0 nop ; (mov r8, r8) + 8000d50: 00000406 .word 0x00000406 + 8000d54: ffff8000 .word 0xffff8000 + 8000d58: ffffbf8f .word 0xffffbf8f + 8000d5c: ffff8080 .word 0xffff8080 + 8000d60: 00000402 .word 0x00000402 + +08000d64 : + 8000d64: 000b movs r3, r1 + 8000d66: 217f movs r1, #127 ; 0x7f + 8000d68: 4019 ands r1, r3 + 8000d6a: 00cb lsls r3, r1, #3 + 8000d6c: 1a59 subs r1, r3, r1 + 8000d6e: 0089 lsls r1, r1, #2 + 8000d70: 1840 adds r0, r0, r1 + 8000d72: 3021 adds r0, #33 ; 0x21 + 8000d74: 30ff adds r0, #255 ; 0xff + 8000d76: 8800 ldrh r0, [r0, #0] + 8000d78: 4770 bx lr + ... + +08000d7c : + 8000d7c: b530 push {r4, r5, lr} + 8000d7e: 23f4 movs r3, #244 ; 0xf4 + 8000d80: 005b lsls r3, r3, #1 + 8000d82: 5cc3 ldrb r3, [r0, r3] + 8000d84: 2b01 cmp r3, #1 + 8000d86: d057 beq.n 8000e38 + 8000d88: 23f4 movs r3, #244 ; 0xf4 + 8000d8a: 005b lsls r3, r3, #1 + 8000d8c: 2201 movs r2, #1 + 8000d8e: 54c2 strb r2, [r0, r3] + 8000d90: b24b sxtb r3, r1 + 8000d92: 2b00 cmp r3, #0 + 8000d94: db25 blt.n 8000de2 + 8000d96: 00cb lsls r3, r1, #3 + 8000d98: 1a5a subs r2, r3, r1 + 8000d9a: 0092 lsls r2, r2, #2 + 8000d9c: 1882 adds r2, r0, r2 + 8000d9e: 0014 movs r4, r2 + 8000da0: 340b adds r4, #11 + 8000da2: 34ff adds r4, #255 ; 0xff + 8000da4: 2501 movs r5, #1 + 8000da6: 7025 strb r5, [r4, #0] + 8000da8: 247f movs r4, #127 ; 0x7f + 8000daa: 400c ands r4, r1 + 8000dac: 3209 adds r2, #9 + 8000dae: 32ff adds r2, #255 ; 0xff + 8000db0: 7014 strb r4, [r2, #0] + 8000db2: 1a5b subs r3, r3, r1 + 8000db4: 009b lsls r3, r3, #2 + 8000db6: 18c3 adds r3, r0, r3 + 8000db8: 330a adds r3, #10 + 8000dba: 33ff adds r3, #255 ; 0xff + 8000dbc: 2200 movs r2, #0 + 8000dbe: 701a strb r2, [r3, #0] + 8000dc0: 2c00 cmp r4, #0 + 8000dc2: d12b bne.n 8000e1c + 8000dc4: 6801 ldr r1, [r0, #0] + 8000dc6: 880a ldrh r2, [r1, #0] + 8000dc8: 4b1c ldr r3, [pc, #112] ; (8000e3c ) + 8000dca: 401a ands r2, r3 + 8000dcc: 4b1c ldr r3, [pc, #112] ; (8000e40 ) + 8000dce: 405a eors r2, r3 + 8000dd0: 4b1c ldr r3, [pc, #112] ; (8000e44 ) + 8000dd2: 4313 orrs r3, r2 + 8000dd4: 800b strh r3, [r1, #0] + 8000dd6: 23f4 movs r3, #244 ; 0xf4 + 8000dd8: 005b lsls r3, r3, #1 + 8000dda: 2200 movs r2, #0 + 8000ddc: 54c2 strb r2, [r0, r3] + 8000dde: 2000 movs r0, #0 + 8000de0: bd30 pop {r4, r5, pc} + 8000de2: 237f movs r3, #127 ; 0x7f + 8000de4: 400b ands r3, r1 + 8000de6: 00da lsls r2, r3, #3 + 8000de8: 1ad2 subs r2, r2, r3 + 8000dea: 0092 lsls r2, r2, #2 + 8000dec: 1882 adds r2, r0, r2 + 8000dee: 0014 movs r4, r2 + 8000df0: 342a adds r4, #42 ; 0x2a + 8000df2: 2101 movs r1, #1 + 8000df4: 7021 strb r1, [r4, #0] + 8000df6: 3c02 subs r4, #2 + 8000df8: 7023 strb r3, [r4, #0] + 8000dfa: 3229 adds r2, #41 ; 0x29 + 8000dfc: 7011 strb r1, [r2, #0] + 8000dfe: 2b00 cmp r3, #0 + 8000e00: d0e0 beq.n 8000dc4 + 8000e02: 009b lsls r3, r3, #2 + 8000e04: 6802 ldr r2, [r0, #0] + 8000e06: 4694 mov ip, r2 + 8000e08: 4463 add r3, ip + 8000e0a: 881a ldrh r2, [r3, #0] + 8000e0c: 490e ldr r1, [pc, #56] ; (8000e48 ) + 8000e0e: 400a ands r2, r1 + 8000e10: 2110 movs r1, #16 + 8000e12: 404a eors r2, r1 + 8000e14: 490b ldr r1, [pc, #44] ; (8000e44 ) + 8000e16: 430a orrs r2, r1 + 8000e18: 801a strh r2, [r3, #0] + 8000e1a: e7dc b.n 8000dd6 + 8000e1c: 00a4 lsls r4, r4, #2 + 8000e1e: 6803 ldr r3, [r0, #0] + 8000e20: 469c mov ip, r3 + 8000e22: 4464 add r4, ip + 8000e24: 8822 ldrh r2, [r4, #0] + 8000e26: 4b09 ldr r3, [pc, #36] ; (8000e4c ) + 8000e28: 401a ands r2, r3 + 8000e2a: 2380 movs r3, #128 ; 0x80 + 8000e2c: 015b lsls r3, r3, #5 + 8000e2e: 405a eors r2, r3 + 8000e30: 4b04 ldr r3, [pc, #16] ; (8000e44 ) + 8000e32: 4313 orrs r3, r2 + 8000e34: 8023 strh r3, [r4, #0] + 8000e36: e7ce b.n 8000dd6 + 8000e38: 2002 movs r0, #2 + 8000e3a: e7d1 b.n 8000de0 + 8000e3c: ffffbfbf .word 0xffffbfbf + 8000e40: 00001010 .word 0x00001010 + 8000e44: ffff8080 .word 0xffff8080 + 8000e48: ffff8fbf .word 0xffff8fbf + 8000e4c: ffffbf8f .word 0xffffbf8f + +08000e50 : + 8000e50: b510 push {r4, lr} + 8000e52: b24a sxtb r2, r1 + 8000e54: 2a00 cmp r2, #0 + 8000e56: db38 blt.n 8000eca + 8000e58: 00cb lsls r3, r1, #3 + 8000e5a: 1a5b subs r3, r3, r1 + 8000e5c: 009b lsls r3, r3, #2 + 8000e5e: 3309 adds r3, #9 + 8000e60: 33ff adds r3, #255 ; 0xff + 8000e62: 18c3 adds r3, r0, r3 + 8000e64: 2400 movs r4, #0 + 8000e66: 709c strb r4, [r3, #2] + 8000e68: 347f adds r4, #127 ; 0x7f + 8000e6a: 4021 ands r1, r4 + 8000e6c: 7019 strb r1, [r3, #0] + 8000e6e: 0fd2 lsrs r2, r2, #31 + 8000e70: 705a strb r2, [r3, #1] + 8000e72: 22f4 movs r2, #244 ; 0xf4 + 8000e74: 0052 lsls r2, r2, #1 + 8000e76: 5c82 ldrb r2, [r0, r2] + 8000e78: 2a01 cmp r2, #1 + 8000e7a: d04a beq.n 8000f12 + 8000e7c: 22f4 movs r2, #244 ; 0xf4 + 8000e7e: 0052 lsls r2, r2, #1 + 8000e80: 2101 movs r1, #1 + 8000e82: 5481 strb r1, [r0, r2] + 8000e84: 785a ldrb r2, [r3, #1] + 8000e86: 2a00 cmp r2, #0 + 8000e88: d027 beq.n 8000eda + 8000e8a: 781a ldrb r2, [r3, #0] + 8000e8c: 0092 lsls r2, r2, #2 + 8000e8e: 6801 ldr r1, [r0, #0] + 8000e90: 468c mov ip, r1 + 8000e92: 4462 add r2, ip + 8000e94: 8811 ldrh r1, [r2, #0] + 8000e96: 064c lsls r4, r1, #25 + 8000e98: d504 bpl.n 8000ea4 + 8000e9a: 4c1f ldr r4, [pc, #124] ; (8000f18 ) + 8000e9c: 4021 ands r1, r4 + 8000e9e: 4c1f ldr r4, [pc, #124] ; (8000f1c ) + 8000ea0: 4321 orrs r1, r4 + 8000ea2: 8011 strh r1, [r2, #0] + 8000ea4: 781a ldrb r2, [r3, #0] + 8000ea6: 0092 lsls r2, r2, #2 + 8000ea8: 6803 ldr r3, [r0, #0] + 8000eaa: 469c mov ip, r3 + 8000eac: 4462 add r2, ip + 8000eae: 8813 ldrh r3, [r2, #0] + 8000eb0: 491b ldr r1, [pc, #108] ; (8000f20 ) + 8000eb2: 400b ands r3, r1 + 8000eb4: 2130 movs r1, #48 ; 0x30 + 8000eb6: 404b eors r3, r1 + 8000eb8: 491a ldr r1, [pc, #104] ; (8000f24 ) + 8000eba: 430b orrs r3, r1 + 8000ebc: 8013 strh r3, [r2, #0] + 8000ebe: 23f4 movs r3, #244 ; 0xf4 + 8000ec0: 005b lsls r3, r3, #1 + 8000ec2: 2200 movs r2, #0 + 8000ec4: 54c2 strb r2, [r0, r3] + 8000ec6: 2000 movs r0, #0 + 8000ec8: bd10 pop {r4, pc} + 8000eca: 247f movs r4, #127 ; 0x7f + 8000ecc: 400c ands r4, r1 + 8000ece: 00e3 lsls r3, r4, #3 + 8000ed0: 1b1b subs r3, r3, r4 + 8000ed2: 009b lsls r3, r3, #2 + 8000ed4: 3328 adds r3, #40 ; 0x28 + 8000ed6: 18c3 adds r3, r0, r3 + 8000ed8: e7c4 b.n 8000e64 + 8000eda: 781a ldrb r2, [r3, #0] + 8000edc: 0092 lsls r2, r2, #2 + 8000ede: 6801 ldr r1, [r0, #0] + 8000ee0: 468c mov ip, r1 + 8000ee2: 4462 add r2, ip + 8000ee4: 8811 ldrh r1, [r2, #0] + 8000ee6: 044c lsls r4, r1, #17 + 8000ee8: d504 bpl.n 8000ef4 + 8000eea: 4c0b ldr r4, [pc, #44] ; (8000f18 ) + 8000eec: 4021 ands r1, r4 + 8000eee: 4c0e ldr r4, [pc, #56] ; (8000f28 ) + 8000ef0: 4321 orrs r1, r4 + 8000ef2: 8011 strh r1, [r2, #0] + 8000ef4: 781b ldrb r3, [r3, #0] + 8000ef6: 009b lsls r3, r3, #2 + 8000ef8: 6802 ldr r2, [r0, #0] + 8000efa: 4694 mov ip, r2 + 8000efc: 4463 add r3, ip + 8000efe: 8819 ldrh r1, [r3, #0] + 8000f00: 4a0a ldr r2, [pc, #40] ; (8000f2c ) + 8000f02: 4011 ands r1, r2 + 8000f04: 22c0 movs r2, #192 ; 0xc0 + 8000f06: 0192 lsls r2, r2, #6 + 8000f08: 4051 eors r1, r2 + 8000f0a: 4a06 ldr r2, [pc, #24] ; (8000f24 ) + 8000f0c: 430a orrs r2, r1 + 8000f0e: 801a strh r2, [r3, #0] + 8000f10: e7d5 b.n 8000ebe + 8000f12: 2002 movs r0, #2 + 8000f14: e7d8 b.n 8000ec8 + 8000f16: 46c0 nop ; (mov r8, r8) + 8000f18: 00000f0f .word 0x00000f0f + 8000f1c: ffff80c0 .word 0xffff80c0 + 8000f20: ffff8fbf .word 0xffff8fbf + 8000f24: ffff8080 .word 0xffff8080 + 8000f28: ffffc080 .word 0xffffc080 + 8000f2c: ffffbf8f .word 0xffffbf8f + +08000f30 : + 8000f30: b510 push {r4, lr} + 8000f32: 3301 adds r3, #1 + 8000f34: 085b lsrs r3, r3, #1 + 8000f36: 2480 movs r4, #128 ; 0x80 + 8000f38: 00e4 lsls r4, r4, #3 + 8000f3a: 46a4 mov ip, r4 + 8000f3c: 4460 add r0, ip + 8000f3e: 1880 adds r0, r0, r2 + 8000f40: 2b00 cmp r3, #0 + 8000f42: d00a beq.n 8000f5a + 8000f44: 000c movs r4, r1 + 8000f46: 1a41 subs r1, r0, r1 + 8000f48: 7860 ldrb r0, [r4, #1] + 8000f4a: 0200 lsls r0, r0, #8 + 8000f4c: 7822 ldrb r2, [r4, #0] + 8000f4e: 4302 orrs r2, r0 + 8000f50: 530a strh r2, [r1, r4] + 8000f52: 3b01 subs r3, #1 + 8000f54: 3402 adds r4, #2 + 8000f56: 2b00 cmp r3, #0 + 8000f58: d1f6 bne.n 8000f48 + 8000f5a: bd10 pop {r4, pc} + +08000f5c : + 8000f5c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8000f5e: 0005 movs r5, r0 + 8000f60: 247f movs r4, #127 ; 0x7f + 8000f62: 400c ands r4, r1 + 8000f64: 00e1 lsls r1, r4, #3 + 8000f66: 1b09 subs r1, r1, r4 + 8000f68: 0089 lsls r1, r1, #2 + 8000f6a: 1841 adds r1, r0, r1 + 8000f6c: 638a str r2, [r1, #56] ; 0x38 + 8000f6e: 63cb str r3, [r1, #60] ; 0x3c + 8000f70: 2200 movs r2, #0 + 8000f72: 640a str r2, [r1, #64] ; 0x40 + 8000f74: 000a movs r2, r1 + 8000f76: 3229 adds r2, #41 ; 0x29 + 8000f78: 2001 movs r0, #1 + 8000f7a: 7010 strb r0, [r2, #0] + 8000f7c: 3a01 subs r2, #1 + 8000f7e: 7014 strb r4, [r2, #0] + 8000f80: 6b4f ldr r7, [r1, #52] ; 0x34 + 8000f82: 42bb cmp r3, r7 + 8000f84: d931 bls.n 8000fea + 8000f86: 1bdb subs r3, r3, r7 + 8000f88: 63cb str r3, [r1, #60] ; 0x3c + 8000f8a: 00e2 lsls r2, r4, #3 + 8000f8c: 1b12 subs r2, r2, r4 + 8000f8e: 0092 lsls r2, r2, #2 + 8000f90: 18aa adds r2, r5, r2 + 8000f92: 3232 adds r2, #50 ; 0x32 + 8000f94: 7813 ldrb r3, [r2, #0] + 8000f96: 2b00 cmp r3, #0 + 8000f98: d02f beq.n 8000ffa + 8000f9a: 682a ldr r2, [r5, #0] + 8000f9c: 00e3 lsls r3, r4, #3 + 8000f9e: 1b1b subs r3, r3, r4 + 8000fa0: 009b lsls r3, r3, #2 + 8000fa2: 18eb adds r3, r5, r3 + 8000fa4: 3328 adds r3, #40 ; 0x28 + 8000fa6: 7818 ldrb r0, [r3, #0] + 8000fa8: 0083 lsls r3, r0, #2 + 8000faa: 5a9b ldrh r3, [r3, r2] + 8000fac: 065b lsls r3, r3, #25 + 8000fae: d576 bpl.n 800109e + 8000fb0: 00e3 lsls r3, r4, #3 + 8000fb2: 1b1b subs r3, r3, r4 + 8000fb4: 009b lsls r3, r3, #2 + 8000fb6: 18eb adds r3, r5, r3 + 8000fb8: 3329 adds r3, #41 ; 0x29 + 8000fba: 781b ldrb r3, [r3, #0] + 8000fbc: 2b00 cmp r3, #0 + 8000fbe: d13d bne.n 800103c + 8000fc0: 3350 adds r3, #80 ; 0x50 + 8000fc2: 5ad3 ldrh r3, [r2, r3] + 8000fc4: 00c0 lsls r0, r0, #3 + 8000fc6: 1818 adds r0, r3, r0 + 8000fc8: 4b62 ldr r3, [pc, #392] ; (8001154 ) + 8000fca: 469c mov ip, r3 + 8000fcc: 4462 add r2, ip + 8000fce: 1882 adds r2, r0, r2 + 8000fd0: 2f3e cmp r7, #62 ; 0x3e + 8000fd2: d92a bls.n 800102a + 8000fd4: 097b lsrs r3, r7, #5 + 8000fd6: b29b uxth r3, r3 + 8000fd8: 06f9 lsls r1, r7, #27 + 8000fda: d101 bne.n 8000fe0 + 8000fdc: 3b01 subs r3, #1 + 8000fde: b29b uxth r3, r3 + 8000fe0: 029b lsls r3, r3, #10 + 8000fe2: 485d ldr r0, [pc, #372] ; (8001158 ) + 8000fe4: 4303 orrs r3, r0 + 8000fe6: 8013 strh r3, [r2, #0] + 8000fe8: e02a b.n 8001040 + 8000fea: 00e2 lsls r2, r4, #3 + 8000fec: 1b12 subs r2, r2, r4 + 8000fee: 0092 lsls r2, r2, #2 + 8000ff0: 18aa adds r2, r5, r2 + 8000ff2: 2100 movs r1, #0 + 8000ff4: 63d1 str r1, [r2, #60] ; 0x3c + 8000ff6: 001f movs r7, r3 + 8000ff8: e7c7 b.n 8000f8a + 8000ffa: b2bf uxth r7, r7 + 8000ffc: 00e6 lsls r6, r4, #3 + 8000ffe: 1b36 subs r6, r6, r4 + 8001000: 00b6 lsls r6, r6, #2 + 8001002: 19ae adds r6, r5, r6 + 8001004: 8db2 ldrh r2, [r6, #44] ; 0x2c + 8001006: 003b movs r3, r7 + 8001008: 6bb1 ldr r1, [r6, #56] ; 0x38 + 800100a: 6828 ldr r0, [r5, #0] + 800100c: f7ff ff90 bl 8000f30 + 8001010: 682a ldr r2, [r5, #0] + 8001012: 2350 movs r3, #80 ; 0x50 + 8001014: 5ad3 ldrh r3, [r2, r3] + 8001016: 3628 adds r6, #40 ; 0x28 + 8001018: 7831 ldrb r1, [r6, #0] + 800101a: 00c9 lsls r1, r1, #3 + 800101c: 1852 adds r2, r2, r1 + 800101e: 189b adds r3, r3, r2 + 8001020: 4a4e ldr r2, [pc, #312] ; (800115c ) + 8001022: 4694 mov ip, r2 + 8001024: 4463 add r3, ip + 8001026: 801f strh r7, [r3, #0] + 8001028: e081 b.n 800112e + 800102a: 087b lsrs r3, r7, #1 + 800102c: b29b uxth r3, r3 + 800102e: 07f9 lsls r1, r7, #31 + 8001030: d501 bpl.n 8001036 + 8001032: 3301 adds r3, #1 + 8001034: b29b uxth r3, r3 + 8001036: 029b lsls r3, r3, #10 + 8001038: 8013 strh r3, [r2, #0] + 800103a: e001 b.n 8001040 + 800103c: 2b01 cmp r3, #1 + 800103e: d024 beq.n 800108a + 8001040: 00e3 lsls r3, r4, #3 + 8001042: 1b1b subs r3, r3, r4 + 8001044: 009b lsls r3, r3, #2 + 8001046: 18eb adds r3, r5, r3 + 8001048: 8e1a ldrh r2, [r3, #48] ; 0x30 + 800104a: b2bb uxth r3, r7 + 800104c: 00e6 lsls r6, r4, #3 + 800104e: 1b36 subs r6, r6, r4 + 8001050: 00b6 lsls r6, r6, #2 + 8001052: 19ae adds r6, r5, r6 + 8001054: 6bb1 ldr r1, [r6, #56] ; 0x38 + 8001056: 6828 ldr r0, [r5, #0] + 8001058: f7ff ff6a bl 8000f30 + 800105c: 3629 adds r6, #41 ; 0x29 + 800105e: 7833 ldrb r3, [r6, #0] + 8001060: 2b00 cmp r3, #0 + 8001062: d054 beq.n 800110e + 8001064: 2b01 cmp r3, #1 + 8001066: d162 bne.n 800112e + 8001068: 00e3 lsls r3, r4, #3 + 800106a: 1b1b subs r3, r3, r4 + 800106c: 009b lsls r3, r3, #2 + 800106e: 18eb adds r3, r5, r3 + 8001070: 3328 adds r3, #40 ; 0x28 + 8001072: 781b ldrb r3, [r3, #0] + 8001074: 009b lsls r3, r3, #2 + 8001076: 682a ldr r2, [r5, #0] + 8001078: 4694 mov ip, r2 + 800107a: 4463 add r3, ip + 800107c: 881a ldrh r2, [r3, #0] + 800107e: 4938 ldr r1, [pc, #224] ; (8001160 ) + 8001080: 4011 ands r1, r2 + 8001082: 4a38 ldr r2, [pc, #224] ; (8001164 ) + 8001084: 430a orrs r2, r1 + 8001086: 801a strh r2, [r3, #0] + 8001088: e051 b.n 800112e + 800108a: 334f adds r3, #79 ; 0x4f + 800108c: 5ad3 ldrh r3, [r2, r3] + 800108e: 00c0 lsls r0, r0, #3 + 8001090: 1812 adds r2, r2, r0 + 8001092: 189a adds r2, r3, r2 + 8001094: 4b2f ldr r3, [pc, #188] ; (8001154 ) + 8001096: 469c mov ip, r3 + 8001098: 4462 add r2, ip + 800109a: 8017 strh r7, [r2, #0] + 800109c: e7d0 b.n 8001040 + 800109e: 00e3 lsls r3, r4, #3 + 80010a0: 1b1b subs r3, r3, r4 + 80010a2: 009b lsls r3, r3, #2 + 80010a4: 18eb adds r3, r5, r3 + 80010a6: 3329 adds r3, #41 ; 0x29 + 80010a8: 781b ldrb r3, [r3, #0] + 80010aa: 2b00 cmp r3, #0 + 80010ac: d11d bne.n 80010ea + 80010ae: 3350 adds r3, #80 ; 0x50 + 80010b0: 5ad3 ldrh r3, [r2, r3] + 80010b2: 00c0 lsls r0, r0, #3 + 80010b4: 1818 adds r0, r3, r0 + 80010b6: 4b29 ldr r3, [pc, #164] ; (800115c ) + 80010b8: 469c mov ip, r3 + 80010ba: 4462 add r2, ip + 80010bc: 1882 adds r2, r0, r2 + 80010be: 2f3e cmp r7, #62 ; 0x3e + 80010c0: d90a bls.n 80010d8 + 80010c2: 097b lsrs r3, r7, #5 + 80010c4: b29b uxth r3, r3 + 80010c6: 06f9 lsls r1, r7, #27 + 80010c8: d101 bne.n 80010ce + 80010ca: 3b01 subs r3, #1 + 80010cc: b29b uxth r3, r3 + 80010ce: 029b lsls r3, r3, #10 + 80010d0: 4821 ldr r0, [pc, #132] ; (8001158 ) + 80010d2: 4303 orrs r3, r0 + 80010d4: 8013 strh r3, [r2, #0] + 80010d6: e00a b.n 80010ee + 80010d8: 087b lsrs r3, r7, #1 + 80010da: b29b uxth r3, r3 + 80010dc: 07f9 lsls r1, r7, #31 + 80010de: d501 bpl.n 80010e4 + 80010e0: 3301 adds r3, #1 + 80010e2: b29b uxth r3, r3 + 80010e4: 029b lsls r3, r3, #10 + 80010e6: 8013 strh r3, [r2, #0] + 80010e8: e001 b.n 80010ee + 80010ea: 2b01 cmp r3, #1 + 80010ec: d005 beq.n 80010fa + 80010ee: 00e3 lsls r3, r4, #3 + 80010f0: 1b1b subs r3, r3, r4 + 80010f2: 009b lsls r3, r3, #2 + 80010f4: 18eb adds r3, r5, r3 + 80010f6: 8dda ldrh r2, [r3, #46] ; 0x2e + 80010f8: e7a7 b.n 800104a + 80010fa: 334f adds r3, #79 ; 0x4f + 80010fc: 5ad3 ldrh r3, [r2, r3] + 80010fe: 00c0 lsls r0, r0, #3 + 8001100: 1812 adds r2, r2, r0 + 8001102: 189a adds r2, r3, r2 + 8001104: 4b15 ldr r3, [pc, #84] ; (800115c ) + 8001106: 469c mov ip, r3 + 8001108: 4462 add r2, ip + 800110a: 8017 strh r7, [r2, #0] + 800110c: e7ef b.n 80010ee + 800110e: 00e3 lsls r3, r4, #3 + 8001110: 1b1b subs r3, r3, r4 + 8001112: 009b lsls r3, r3, #2 + 8001114: 18eb adds r3, r5, r3 + 8001116: 3328 adds r3, #40 ; 0x28 + 8001118: 781b ldrb r3, [r3, #0] + 800111a: 009b lsls r3, r3, #2 + 800111c: 682a ldr r2, [r5, #0] + 800111e: 4694 mov ip, r2 + 8001120: 4463 add r3, ip + 8001122: 881a ldrh r2, [r3, #0] + 8001124: 490e ldr r1, [pc, #56] ; (8001160 ) + 8001126: 4011 ands r1, r2 + 8001128: 4a0f ldr r2, [pc, #60] ; (8001168 ) + 800112a: 430a orrs r2, r1 + 800112c: 801a strh r2, [r3, #0] + 800112e: 00e1 lsls r1, r4, #3 + 8001130: 1b0c subs r4, r1, r4 + 8001132: 00a4 lsls r4, r4, #2 + 8001134: 192c adds r4, r5, r4 + 8001136: 3428 adds r4, #40 ; 0x28 + 8001138: 7823 ldrb r3, [r4, #0] + 800113a: 009b lsls r3, r3, #2 + 800113c: 682a ldr r2, [r5, #0] + 800113e: 18d2 adds r2, r2, r3 + 8001140: 8813 ldrh r3, [r2, #0] + 8001142: 490a ldr r1, [pc, #40] ; (800116c ) + 8001144: 400b ands r3, r1 + 8001146: 2130 movs r1, #48 ; 0x30 + 8001148: 404b eors r3, r1 + 800114a: 4909 ldr r1, [pc, #36] ; (8001170 ) + 800114c: 430b orrs r3, r1 + 800114e: 8013 strh r3, [r2, #0] + 8001150: 2000 movs r0, #0 + 8001152: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8001154: 00000406 .word 0x00000406 + 8001158: ffff8000 .word 0xffff8000 + 800115c: 00000402 .word 0x00000402 + 8001160: 00000f0f .word 0x00000f0f + 8001164: ffffc080 .word 0xffffc080 + 8001168: ffff80c0 .word 0xffff80c0 + 800116c: ffff8fbf .word 0xffff8fbf + 8001170: ffff8080 .word 0xffff8080 + +08001174 : + 8001174: b5f0 push {r4, r5, r6, r7, lr} + 8001176: 085f lsrs r7, r3, #1 + 8001178: 2480 movs r4, #128 ; 0x80 + 800117a: 00e4 lsls r4, r4, #3 + 800117c: 46a4 mov ip, r4 + 800117e: 4460 add r0, ip + 8001180: 1882 adds r2, r0, r2 + 8001182: 0010 movs r0, r2 + 8001184: 2f00 cmp r7, #0 + 8001186: d00d beq.n 80011a4 + 8001188: 000c movs r4, r1 + 800118a: 003e movs r6, r7 + 800118c: 1a50 subs r0, r2, r1 + 800118e: 5b05 ldrh r5, [r0, r4] + 8001190: 7025 strb r5, [r4, #0] + 8001192: 0a2d lsrs r5, r5, #8 + 8001194: 7065 strb r5, [r4, #1] + 8001196: 3e01 subs r6, #1 + 8001198: 3402 adds r4, #2 + 800119a: 2e00 cmp r6, #0 + 800119c: d1f7 bne.n 800118e + 800119e: 007f lsls r7, r7, #1 + 80011a0: 19d0 adds r0, r2, r7 + 80011a2: 19c9 adds r1, r1, r7 + 80011a4: 07db lsls r3, r3, #31 + 80011a6: d501 bpl.n 80011ac + 80011a8: 8803 ldrh r3, [r0, #0] + 80011aa: 700b strb r3, [r1, #0] + 80011ac: bdf0 pop {r4, r5, r6, r7, pc} + ... + +080011b0 : + 80011b0: b5f0 push {r4, r5, r6, r7, lr} + 80011b2: 46d6 mov lr, sl + 80011b4: 464f mov r7, r9 + 80011b6: 4646 mov r6, r8 + 80011b8: b5c0 push {r6, r7, lr} + 80011ba: b082 sub sp, #8 + 80011bc: 0004 movs r4, r0 + 80011be: 2344 movs r3, #68 ; 0x44 + 80011c0: 6802 ldr r2, [r0, #0] + 80011c2: 5ad3 ldrh r3, [r2, r3] + 80011c4: b21b sxth r3, r3 + 80011c6: 2b00 cmp r3, #0 + 80011c8: db4f blt.n 800126a + 80011ca: 6823 ldr r3, [r4, #0] + 80011cc: 2244 movs r2, #68 ; 0x44 + 80011ce: 5a9a ldrh r2, [r3, r2] + 80011d0: 0552 lsls r2, r2, #21 + 80011d2: d500 bpl.n 80011d6 + 80011d4: e294 b.n 8001700 + 80011d6: 6823 ldr r3, [r4, #0] + 80011d8: 2244 movs r2, #68 ; 0x44 + 80011da: 5a9a ldrh r2, [r3, r2] + 80011dc: 0452 lsls r2, r2, #17 + 80011de: d504 bpl.n 80011ea + 80011e0: 2144 movs r1, #68 ; 0x44 + 80011e2: 5a5a ldrh r2, [r3, r1] + 80011e4: 48b9 ldr r0, [pc, #740] ; (80014cc ) + 80011e6: 4002 ands r2, r0 + 80011e8: 525a strh r2, [r3, r1] + 80011ea: 6823 ldr r3, [r4, #0] + 80011ec: 2244 movs r2, #68 ; 0x44 + 80011ee: 5a9a ldrh r2, [r3, r2] + 80011f0: 0492 lsls r2, r2, #18 + 80011f2: d504 bpl.n 80011fe + 80011f4: 2144 movs r1, #68 ; 0x44 + 80011f6: 5a5a ldrh r2, [r3, r1] + 80011f8: 48b5 ldr r0, [pc, #724] ; (80014d0 ) + 80011fa: 4002 ands r2, r0 + 80011fc: 525a strh r2, [r3, r1] + 80011fe: 6823 ldr r3, [r4, #0] + 8001200: 2244 movs r2, #68 ; 0x44 + 8001202: 5a9a ldrh r2, [r3, r2] + 8001204: 04d2 lsls r2, r2, #19 + 8001206: d500 bpl.n 800120a + 8001208: e287 b.n 800171a + 800120a: 6823 ldr r3, [r4, #0] + 800120c: 2244 movs r2, #68 ; 0x44 + 800120e: 5a9a ldrh r2, [r3, r2] + 8001210: 0512 lsls r2, r2, #20 + 8001212: d514 bpl.n 800123e + 8001214: 2244 movs r2, #68 ; 0x44 + 8001216: 5a99 ldrh r1, [r3, r2] + 8001218: 48ae ldr r0, [pc, #696] ; (80014d4 ) + 800121a: 4001 ands r1, r0 + 800121c: 5299 strh r1, [r3, r2] + 800121e: 6820 ldr r0, [r4, #0] + 8001220: 2340 movs r3, #64 ; 0x40 + 8001222: 5ac1 ldrh r1, [r0, r3] + 8001224: 2508 movs r5, #8 + 8001226: 4329 orrs r1, r5 + 8001228: 52c1 strh r1, [r0, r3] + 800122a: 6820 ldr r0, [r4, #0] + 800122c: 5ac1 ldrh r1, [r0, r3] + 800122e: 2504 movs r5, #4 + 8001230: 4329 orrs r1, r5 + 8001232: 52c1 strh r1, [r0, r3] + 8001234: 6823 ldr r3, [r4, #0] + 8001236: 5a9b ldrh r3, [r3, r2] + 8001238: 04db lsls r3, r3, #19 + 800123a: d400 bmi.n 800123e + 800123c: e27f b.n 800173e + 800123e: 6823 ldr r3, [r4, #0] + 8001240: 2244 movs r2, #68 ; 0x44 + 8001242: 5a9a ldrh r2, [r3, r2] + 8001244: 0592 lsls r2, r2, #22 + 8001246: d500 bpl.n 800124a + 8001248: e27d b.n 8001746 + 800124a: 6823 ldr r3, [r4, #0] + 800124c: 2244 movs r2, #68 ; 0x44 + 800124e: 5a9a ldrh r2, [r3, r2] + 8001250: 05d2 lsls r2, r2, #23 + 8001252: d504 bpl.n 800125e + 8001254: 2144 movs r1, #68 ; 0x44 + 8001256: 5a5a ldrh r2, [r3, r1] + 8001258: 489f ldr r0, [pc, #636] ; (80014d8 ) + 800125a: 4002 ands r2, r0 + 800125c: 525a strh r2, [r3, r1] + 800125e: b002 add sp, #8 + 8001260: bc1c pop {r2, r3, r4} + 8001262: 4690 mov r8, r2 + 8001264: 4699 mov r9, r3 + 8001266: 46a2 mov sl, r4 + 8001268: bdf0 pop {r4, r5, r6, r7, pc} + 800126a: 466b mov r3, sp + 800126c: 2200 movs r2, #0 + 800126e: 80da strh r2, [r3, #6] + 8001270: 2744 movs r7, #68 ; 0x44 + 8001272: ae01 add r6, sp, #4 + 8001274: 230f movs r3, #15 + 8001276: 4698 mov r8, r3 + 8001278: 6820 ldr r0, [r4, #0] + 800127a: 5bc3 ldrh r3, [r0, r7] + 800127c: b29b uxth r3, r3 + 800127e: 8033 strh r3, [r6, #0] + 8001280: b21b sxth r3, r3 + 8001282: 2b00 cmp r3, #0 + 8001284: daa1 bge.n 80011ca + 8001286: 8835 ldrh r5, [r6, #0] + 8001288: 4643 mov r3, r8 + 800128a: 401d ands r5, r3 + 800128c: d000 beq.n 8001290 + 800128e: e0b1 b.n 80013f4 + 8001290: 8833 ldrh r3, [r6, #0] + 8001292: 06db lsls r3, r3, #27 + 8001294: d54b bpl.n 800132e + 8001296: 8802 ldrh r2, [r0, #0] + 8001298: 466b mov r3, sp + 800129a: 80da strh r2, [r3, #6] + 800129c: 3306 adds r3, #6 + 800129e: 881b ldrh r3, [r3, #0] + 80012a0: 051b lsls r3, r3, #20 + 80012a2: d472 bmi.n 800138a + 80012a4: 466b mov r3, sp + 80012a6: 3306 adds r3, #6 + 80012a8: 881b ldrh r3, [r3, #0] + 80012aa: b21b sxth r3, r3 + 80012ac: 2b00 cmp r3, #0 + 80012ae: dae3 bge.n 8001278 + 80012b0: 8803 ldrh r3, [r0, #0] + 80012b2: 4a8a ldr r2, [pc, #552] ; (80014dc ) + 80012b4: 4013 ands r3, r2 + 80012b6: 8003 strh r3, [r0, #0] + 80012b8: 6820 ldr r0, [r4, #0] + 80012ba: 2350 movs r3, #80 ; 0x50 + 80012bc: 5ac3 ldrh r3, [r0, r3] + 80012be: 2284 movs r2, #132 ; 0x84 + 80012c0: 0052 lsls r2, r2, #1 + 80012c2: 5ca2 ldrb r2, [r4, r2] + 80012c4: 00d2 lsls r2, r2, #3 + 80012c6: 1882 adds r2, r0, r2 + 80012c8: 189b adds r3, r3, r2 + 80012ca: 4a85 ldr r2, [pc, #532] ; (80014e0 ) + 80012cc: 4694 mov ip, r2 + 80012ce: 4463 add r3, ip + 80012d0: 881b ldrh r3, [r3, #0] + 80012d2: 059b lsls r3, r3, #22 + 80012d4: 0d9b lsrs r3, r3, #22 + 80012d6: 0022 movs r2, r4 + 80012d8: 3209 adds r2, #9 + 80012da: 32ff adds r2, #255 ; 0xff + 80012dc: 6193 str r3, [r2, #24] + 80012de: 2b00 cmp r3, #0 + 80012e0: d174 bne.n 80013cc + 80012e2: 2100 movs r1, #0 + 80012e4: 0020 movs r0, r4 + 80012e6: f001 fd1d bl 8002d24 + 80012ea: 6823 ldr r3, [r4, #0] + 80012ec: 2250 movs r2, #80 ; 0x50 + 80012ee: 5a9a ldrh r2, [r3, r2] + 80012f0: 497b ldr r1, [pc, #492] ; (80014e0 ) + 80012f2: 468c mov ip, r1 + 80012f4: 4463 add r3, ip + 80012f6: 189b adds r3, r3, r2 + 80012f8: 0022 movs r2, r4 + 80012fa: 3209 adds r2, #9 + 80012fc: 32ff adds r2, #255 ; 0xff + 80012fe: 68d1 ldr r1, [r2, #12] + 8001300: 293e cmp r1, #62 ; 0x3e + 8001302: d96e bls.n 80013e2 + 8001304: 094a lsrs r2, r1, #5 + 8001306: b292 uxth r2, r2 + 8001308: 06c9 lsls r1, r1, #27 + 800130a: d101 bne.n 8001310 + 800130c: 3a01 subs r2, #1 + 800130e: b292 uxth r2, r2 + 8001310: 0292 lsls r2, r2, #10 + 8001312: 4974 ldr r1, [pc, #464] ; (80014e4 ) + 8001314: 430a orrs r2, r1 + 8001316: 801a strh r2, [r3, #0] + 8001318: 6821 ldr r1, [r4, #0] + 800131a: 880a ldrh r2, [r1, #0] + 800131c: 4b72 ldr r3, [pc, #456] ; (80014e8 ) + 800131e: 401a ands r2, r3 + 8001320: 23c0 movs r3, #192 ; 0xc0 + 8001322: 019b lsls r3, r3, #6 + 8001324: 405a eors r2, r3 + 8001326: 4b71 ldr r3, [pc, #452] ; (80014ec ) + 8001328: 4313 orrs r3, r2 + 800132a: 800b strh r3, [r1, #0] + 800132c: e7a4 b.n 8001278 + 800132e: 8803 ldrh r3, [r0, #0] + 8001330: 4a6f ldr r2, [pc, #444] ; (80014f0 ) + 8001332: 4013 ands r3, r2 + 8001334: 8003 strh r3, [r0, #0] + 8001336: 6821 ldr r1, [r4, #0] + 8001338: 2350 movs r3, #80 ; 0x50 + 800133a: 5acb ldrh r3, [r1, r3] + 800133c: 2228 movs r2, #40 ; 0x28 + 800133e: 5ca2 ldrb r2, [r4, r2] + 8001340: 00d2 lsls r2, r2, #3 + 8001342: 188a adds r2, r1, r2 + 8001344: 189b adds r3, r3, r2 + 8001346: 4a6b ldr r2, [pc, #428] ; (80014f4 ) + 8001348: 4694 mov ip, r2 + 800134a: 4463 add r3, ip + 800134c: 881b ldrh r3, [r3, #0] + 800134e: 059b lsls r3, r3, #22 + 8001350: 0d9b lsrs r3, r3, #22 + 8001352: 6423 str r3, [r4, #64] ; 0x40 + 8001354: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8001356: 4694 mov ip, r2 + 8001358: 4463 add r3, ip + 800135a: 63a3 str r3, [r4, #56] ; 0x38 + 800135c: 2100 movs r1, #0 + 800135e: 0020 movs r0, r4 + 8001360: f001 fcee bl 8002d40 + 8001364: 2324 movs r3, #36 ; 0x24 + 8001366: 5ce3 ldrb r3, [r4, r3] + 8001368: 2b00 cmp r3, #0 + 800136a: d100 bne.n 800136e + 800136c: e784 b.n 8001278 + 800136e: 6be3 ldr r3, [r4, #60] ; 0x3c + 8001370: 2b00 cmp r3, #0 + 8001372: d000 beq.n 8001376 + 8001374: e780 b.n 8001278 + 8001376: 2224 movs r2, #36 ; 0x24 + 8001378: 5ca3 ldrb r3, [r4, r2] + 800137a: 2180 movs r1, #128 ; 0x80 + 800137c: 430b orrs r3, r1 + 800137e: 3934 subs r1, #52 ; 0x34 + 8001380: 6820 ldr r0, [r4, #0] + 8001382: 5243 strh r3, [r0, r1] + 8001384: 2300 movs r3, #0 + 8001386: 54a3 strb r3, [r4, r2] + 8001388: e776 b.n 8001278 + 800138a: 2350 movs r3, #80 ; 0x50 + 800138c: 5ac3 ldrh r3, [r0, r3] + 800138e: 2284 movs r2, #132 ; 0x84 + 8001390: 0052 lsls r2, r2, #1 + 8001392: 5ca2 ldrb r2, [r4, r2] + 8001394: 00d2 lsls r2, r2, #3 + 8001396: 1882 adds r2, r0, r2 + 8001398: 189b adds r3, r3, r2 + 800139a: 4a51 ldr r2, [pc, #324] ; (80014e0 ) + 800139c: 4694 mov ip, r2 + 800139e: 4463 add r3, ip + 80013a0: 881b ldrh r3, [r3, #0] + 80013a2: 059b lsls r3, r3, #22 + 80013a4: 0d9b lsrs r3, r3, #22 + 80013a6: 0022 movs r2, r4 + 80013a8: 3209 adds r2, #9 + 80013aa: 32ff adds r2, #255 ; 0xff + 80013ac: 6193 str r3, [r2, #24] + 80013ae: 8892 ldrh r2, [r2, #4] + 80013b0: 0021 movs r1, r4 + 80013b2: 31ed adds r1, #237 ; 0xed + 80013b4: 31ff adds r1, #255 ; 0xff + 80013b6: f7ff fedd bl 8001174 + 80013ba: 6822 ldr r2, [r4, #0] + 80013bc: 8813 ldrh r3, [r2, #0] + 80013be: 4947 ldr r1, [pc, #284] ; (80014dc ) + 80013c0: 400b ands r3, r1 + 80013c2: 8013 strh r3, [r2, #0] + 80013c4: 0020 movs r0, r4 + 80013c6: f001 fca3 bl 8002d10 + 80013ca: e755 b.n 8001278 + 80013cc: 0015 movs r5, r2 + 80013ce: 8892 ldrh r2, [r2, #4] + 80013d0: 6929 ldr r1, [r5, #16] + 80013d2: f7ff fecf bl 8001174 + 80013d6: 692b ldr r3, [r5, #16] + 80013d8: 69aa ldr r2, [r5, #24] + 80013da: 4694 mov ip, r2 + 80013dc: 4463 add r3, ip + 80013de: 612b str r3, [r5, #16] + 80013e0: e77f b.n 80012e2 + 80013e2: 084a lsrs r2, r1, #1 + 80013e4: b292 uxth r2, r2 + 80013e6: 07c9 lsls r1, r1, #31 + 80013e8: d501 bpl.n 80013ee + 80013ea: 3201 adds r2, #1 + 80013ec: b292 uxth r2, r2 + 80013ee: 0292 lsls r2, r2, #10 + 80013f0: 801a strh r2, [r3, #0] + 80013f2: e791 b.n 8001318 + 80013f4: 00ab lsls r3, r5, #2 + 80013f6: 4699 mov r9, r3 + 80013f8: 4448 add r0, r9 + 80013fa: 8802 ldrh r2, [r0, #0] + 80013fc: 466b mov r3, sp + 80013fe: 80da strh r2, [r3, #6] + 8001400: 3306 adds r3, #6 + 8001402: 881b ldrh r3, [r3, #0] + 8001404: b21b sxth r3, r3 + 8001406: 2b00 cmp r3, #0 + 8001408: db30 blt.n 800146c + 800140a: 466b mov r3, sp + 800140c: 3306 adds r3, #6 + 800140e: 881b ldrh r3, [r3, #0] + 8001410: 061b lsls r3, r3, #24 + 8001412: d400 bmi.n 8001416 + 8001414: e730 b.n 8001278 + 8001416: 6823 ldr r3, [r4, #0] + 8001418: 444b add r3, r9 + 800141a: 881a ldrh r2, [r3, #0] + 800141c: 4934 ldr r1, [pc, #208] ; (80014f0 ) + 800141e: 400a ands r2, r1 + 8001420: 801a strh r2, [r3, #0] + 8001422: 00eb lsls r3, r5, #3 + 8001424: 1b5b subs r3, r3, r5 + 8001426: 009b lsls r3, r3, #2 + 8001428: 18e3 adds r3, r4, r3 + 800142a: 3332 adds r3, #50 ; 0x32 + 800142c: 781b ldrb r3, [r3, #0] + 800142e: 2b00 cmp r3, #0 + 8001430: d000 beq.n 8001434 + 8001432: e0eb b.n 800160c + 8001434: 6820 ldr r0, [r4, #0] + 8001436: 3350 adds r3, #80 ; 0x50 + 8001438: 5ac3 ldrh r3, [r0, r3] + 800143a: 00ea lsls r2, r5, #3 + 800143c: 1b52 subs r2, r2, r5 + 800143e: 0092 lsls r2, r2, #2 + 8001440: 18a2 adds r2, r4, r2 + 8001442: 0011 movs r1, r2 + 8001444: 3128 adds r1, #40 ; 0x28 + 8001446: 7809 ldrb r1, [r1, #0] + 8001448: 00c9 lsls r1, r1, #3 + 800144a: 1841 adds r1, r0, r1 + 800144c: 185b adds r3, r3, r1 + 800144e: 4929 ldr r1, [pc, #164] ; (80014f4 ) + 8001450: 468c mov ip, r1 + 8001452: 4463 add r3, ip + 8001454: 881b ldrh r3, [r3, #0] + 8001456: 059b lsls r3, r3, #22 + 8001458: 0d9b lsrs r3, r3, #22 + 800145a: 6413 str r3, [r2, #64] ; 0x40 + 800145c: d100 bne.n 8001460 + 800145e: e102 b.n 8001666 + 8001460: 0011 movs r1, r2 + 8001462: 8d92 ldrh r2, [r2, #44] ; 0x2c + 8001464: 6b89 ldr r1, [r1, #56] ; 0x38 + 8001466: f7ff fd63 bl 8000f30 + 800146a: e0fc b.n 8001666 + 800146c: 4b1b ldr r3, [pc, #108] ; (80014dc ) + 800146e: 401a ands r2, r3 + 8001470: 8002 strh r2, [r0, #0] + 8001472: 00eb lsls r3, r5, #3 + 8001474: 1b5b subs r3, r3, r5 + 8001476: 009b lsls r3, r3, #2 + 8001478: 18e3 adds r3, r4, r3 + 800147a: 3313 adds r3, #19 + 800147c: 33ff adds r3, #255 ; 0xff + 800147e: 781b ldrb r3, [r3, #0] + 8001480: 2b00 cmp r3, #0 + 8001482: d139 bne.n 80014f8 + 8001484: 6820 ldr r0, [r4, #0] + 8001486: 3350 adds r3, #80 ; 0x50 + 8001488: 5ac2 ldrh r2, [r0, r3] + 800148a: 00eb lsls r3, r5, #3 + 800148c: 1b5b subs r3, r3, r5 + 800148e: 009b lsls r3, r3, #2 + 8001490: 18e3 adds r3, r4, r3 + 8001492: 3309 adds r3, #9 + 8001494: 33ff adds r3, #255 ; 0xff + 8001496: 781b ldrb r3, [r3, #0] + 8001498: 00db lsls r3, r3, #3 + 800149a: 18c3 adds r3, r0, r3 + 800149c: 18d3 adds r3, r2, r3 + 800149e: 4a10 ldr r2, [pc, #64] ; (80014e0 ) + 80014a0: 4694 mov ip, r2 + 80014a2: 4463 add r3, ip + 80014a4: 881a ldrh r2, [r3, #0] + 80014a6: 0592 lsls r2, r2, #22 + 80014a8: 0d93 lsrs r3, r2, #22 + 80014aa: 469a mov sl, r3 + 80014ac: d04e beq.n 800154c + 80014ae: 00eb lsls r3, r5, #3 + 80014b0: 1b5b subs r3, r3, r5 + 80014b2: 009b lsls r3, r3, #2 + 80014b4: 18e3 adds r3, r4, r3 + 80014b6: 001a movs r2, r3 + 80014b8: 320d adds r2, #13 + 80014ba: 32ff adds r2, #255 ; 0xff + 80014bc: 8812 ldrh r2, [r2, #0] + 80014be: 3319 adds r3, #25 + 80014c0: 33ff adds r3, #255 ; 0xff + 80014c2: 6819 ldr r1, [r3, #0] + 80014c4: 4653 mov r3, sl + 80014c6: f7ff fe55 bl 8001174 + 80014ca: e03f b.n 800154c + 80014cc: ffffbfff .word 0xffffbfff + 80014d0: ffffdfff .word 0xffffdfff + 80014d4: fffff7ff .word 0xfffff7ff + 80014d8: fffffeff .word 0xfffffeff + 80014dc: 00000f8f .word 0x00000f8f + 80014e0: 00000406 .word 0x00000406 + 80014e4: ffff8000 .word 0xffff8000 + 80014e8: ffffbf8f .word 0xffffbf8f + 80014ec: ffff8080 .word 0xffff8080 + 80014f0: ffff8f0f .word 0xffff8f0f + 80014f4: 00000402 .word 0x00000402 + 80014f8: 6820 ldr r0, [r4, #0] + 80014fa: 00eb lsls r3, r5, #3 + 80014fc: 1b5b subs r3, r3, r5 + 80014fe: 009b lsls r3, r3, #2 + 8001500: 18e3 adds r3, r4, r3 + 8001502: 3309 adds r3, #9 + 8001504: 33ff adds r3, #255 ; 0xff + 8001506: 781b ldrb r3, [r3, #0] + 8001508: 009a lsls r2, r3, #2 + 800150a: 5a12 ldrh r2, [r2, r0] + 800150c: 0452 lsls r2, r2, #17 + 800150e: d556 bpl.n 80015be + 8001510: 2250 movs r2, #80 ; 0x50 + 8001512: 5a82 ldrh r2, [r0, r2] + 8001514: 00db lsls r3, r3, #3 + 8001516: 18c3 adds r3, r0, r3 + 8001518: 18d3 adds r3, r2, r3 + 800151a: 4a8f ldr r2, [pc, #572] ; (8001758 ) + 800151c: 4694 mov ip, r2 + 800151e: 4463 add r3, ip + 8001520: 881a ldrh r2, [r3, #0] + 8001522: 0592 lsls r2, r2, #22 + 8001524: 0d93 lsrs r3, r2, #22 + 8001526: 469a mov sl, r3 + 8001528: d13a bne.n 80015a0 + 800152a: 00eb lsls r3, r5, #3 + 800152c: 1b5b subs r3, r3, r5 + 800152e: 009b lsls r3, r3, #2 + 8001530: 18e3 adds r3, r4, r3 + 8001532: 3309 adds r3, #9 + 8001534: 33ff adds r3, #255 ; 0xff + 8001536: 781b ldrb r3, [r3, #0] + 8001538: 009b lsls r3, r3, #2 + 800153a: 6822 ldr r2, [r4, #0] + 800153c: 4694 mov ip, r2 + 800153e: 4463 add r3, ip + 8001540: 881a ldrh r2, [r3, #0] + 8001542: 4986 ldr r1, [pc, #536] ; (800175c ) + 8001544: 4011 ands r1, r2 + 8001546: 4a86 ldr r2, [pc, #536] ; (8001760 ) + 8001548: 430a orrs r2, r1 + 800154a: 801a strh r2, [r3, #0] + 800154c: 4650 mov r0, sl + 800154e: 00e9 lsls r1, r5, #3 + 8001550: 1b49 subs r1, r1, r5 + 8001552: 0089 lsls r1, r1, #2 + 8001554: 1861 adds r1, r4, r1 + 8001556: 000a movs r2, r1 + 8001558: 3221 adds r2, #33 ; 0x21 + 800155a: 32ff adds r2, #255 ; 0xff + 800155c: 6813 ldr r3, [r2, #0] + 800155e: 4453 add r3, sl + 8001560: 6013 str r3, [r2, #0] + 8001562: 000b movs r3, r1 + 8001564: 3319 adds r3, #25 + 8001566: 33ff adds r3, #255 ; 0xff + 8001568: 681a ldr r2, [r3, #0] + 800156a: 4452 add r2, sl + 800156c: 601a str r2, [r3, #0] + 800156e: 311d adds r1, #29 + 8001570: 31ff adds r1, #255 ; 0xff + 8001572: 680b ldr r3, [r1, #0] + 8001574: 2b00 cmp r3, #0 + 8001576: d008 beq.n 800158a + 8001578: 00e9 lsls r1, r5, #3 + 800157a: 1b49 subs r1, r1, r5 + 800157c: 0089 lsls r1, r1, #2 + 800157e: 1861 adds r1, r4, r1 + 8001580: 3115 adds r1, #21 + 8001582: 31ff adds r1, #255 ; 0xff + 8001584: 6809 ldr r1, [r1, #0] + 8001586: 4288 cmp r0, r1 + 8001588: d235 bcs.n 80015f6 + 800158a: 00eb lsls r3, r5, #3 + 800158c: 1b5b subs r3, r3, r5 + 800158e: 009b lsls r3, r3, #2 + 8001590: 18e3 adds r3, r4, r3 + 8001592: 3309 adds r3, #9 + 8001594: 33ff adds r3, #255 ; 0xff + 8001596: 7819 ldrb r1, [r3, #0] + 8001598: 0020 movs r0, r4 + 800159a: f001 fbc3 bl 8002d24 + 800159e: e734 b.n 800140a + 80015a0: 00eb lsls r3, r5, #3 + 80015a2: 1b5b subs r3, r3, r5 + 80015a4: 009b lsls r3, r3, #2 + 80015a6: 18e3 adds r3, r4, r3 + 80015a8: 001a movs r2, r3 + 80015aa: 320f adds r2, #15 + 80015ac: 32ff adds r2, #255 ; 0xff + 80015ae: 8812 ldrh r2, [r2, #0] + 80015b0: 3319 adds r3, #25 + 80015b2: 33ff adds r3, #255 ; 0xff + 80015b4: 6819 ldr r1, [r3, #0] + 80015b6: 4653 mov r3, sl + 80015b8: f7ff fddc bl 8001174 + 80015bc: e7b5 b.n 800152a + 80015be: 2250 movs r2, #80 ; 0x50 + 80015c0: 5a82 ldrh r2, [r0, r2] + 80015c2: 00db lsls r3, r3, #3 + 80015c4: 18c3 adds r3, r0, r3 + 80015c6: 18d3 adds r3, r2, r3 + 80015c8: 4a66 ldr r2, [pc, #408] ; (8001764 ) + 80015ca: 4694 mov ip, r2 + 80015cc: 4463 add r3, ip + 80015ce: 881a ldrh r2, [r3, #0] + 80015d0: 0592 lsls r2, r2, #22 + 80015d2: 0d93 lsrs r3, r2, #22 + 80015d4: 469a mov sl, r3 + 80015d6: d0a8 beq.n 800152a + 80015d8: 00eb lsls r3, r5, #3 + 80015da: 1b5b subs r3, r3, r5 + 80015dc: 009b lsls r3, r3, #2 + 80015de: 18e3 adds r3, r4, r3 + 80015e0: 001a movs r2, r3 + 80015e2: 3211 adds r2, #17 + 80015e4: 32ff adds r2, #255 ; 0xff + 80015e6: 8812 ldrh r2, [r2, #0] + 80015e8: 3319 adds r3, #25 + 80015ea: 33ff adds r3, #255 ; 0xff + 80015ec: 6819 ldr r1, [r3, #0] + 80015ee: 4653 mov r3, sl + 80015f0: f7ff fdc0 bl 8001174 + 80015f4: e799 b.n 800152a + 80015f6: 00e9 lsls r1, r5, #3 + 80015f8: 1b49 subs r1, r1, r5 + 80015fa: 0089 lsls r1, r1, #2 + 80015fc: 1861 adds r1, r4, r1 + 80015fe: 3109 adds r1, #9 + 8001600: 31ff adds r1, #255 ; 0xff + 8001602: 7809 ldrb r1, [r1, #0] + 8001604: 0020 movs r0, r4 + 8001606: f7ff fa7b bl 8000b00 + 800160a: e6fe b.n 800140a + 800160c: 6820 ldr r0, [r4, #0] + 800160e: 00eb lsls r3, r5, #3 + 8001610: 1b5b subs r3, r3, r5 + 8001612: 009b lsls r3, r3, #2 + 8001614: 18e3 adds r3, r4, r3 + 8001616: 3328 adds r3, #40 ; 0x28 + 8001618: 781b ldrb r3, [r3, #0] + 800161a: 009a lsls r2, r3, #2 + 800161c: 5a12 ldrh r2, [r2, r0] + 800161e: 0652 lsls r2, r2, #25 + 8001620: d54c bpl.n 80016bc + 8001622: 2250 movs r2, #80 ; 0x50 + 8001624: 5a82 ldrh r2, [r0, r2] + 8001626: 00db lsls r3, r3, #3 + 8001628: 18c3 adds r3, r0, r3 + 800162a: 18d3 adds r3, r2, r3 + 800162c: 4a4a ldr r2, [pc, #296] ; (8001758 ) + 800162e: 4694 mov ip, r2 + 8001630: 4463 add r3, ip + 8001632: 881b ldrh r3, [r3, #0] + 8001634: 059b lsls r3, r3, #22 + 8001636: 0d9b lsrs r3, r3, #22 + 8001638: 00ea lsls r2, r5, #3 + 800163a: 1b52 subs r2, r2, r5 + 800163c: 0092 lsls r2, r2, #2 + 800163e: 18a2 adds r2, r4, r2 + 8001640: 6413 str r3, [r2, #64] ; 0x40 + 8001642: 2b00 cmp r3, #0 + 8001644: d134 bne.n 80016b0 + 8001646: 00eb lsls r3, r5, #3 + 8001648: 1b5b subs r3, r3, r5 + 800164a: 009b lsls r3, r3, #2 + 800164c: 18e3 adds r3, r4, r3 + 800164e: 3328 adds r3, #40 ; 0x28 + 8001650: 781b ldrb r3, [r3, #0] + 8001652: 009b lsls r3, r3, #2 + 8001654: 6822 ldr r2, [r4, #0] + 8001656: 4694 mov ip, r2 + 8001658: 4463 add r3, ip + 800165a: 881a ldrh r2, [r3, #0] + 800165c: 493f ldr r1, [pc, #252] ; (800175c ) + 800165e: 4011 ands r1, r2 + 8001660: 4a41 ldr r2, [pc, #260] ; (8001768 ) + 8001662: 430a orrs r2, r1 + 8001664: 801a strh r2, [r3, #0] + 8001666: 6821 ldr r1, [r4, #0] + 8001668: 2350 movs r3, #80 ; 0x50 + 800166a: 5aca ldrh r2, [r1, r3] + 800166c: 00eb lsls r3, r5, #3 + 800166e: 1b5b subs r3, r3, r5 + 8001670: 009b lsls r3, r3, #2 + 8001672: 18e3 adds r3, r4, r3 + 8001674: 0018 movs r0, r3 + 8001676: 3028 adds r0, #40 ; 0x28 + 8001678: 7800 ldrb r0, [r0, #0] + 800167a: 00c0 lsls r0, r0, #3 + 800167c: 1809 adds r1, r1, r0 + 800167e: 1852 adds r2, r2, r1 + 8001680: 4935 ldr r1, [pc, #212] ; (8001758 ) + 8001682: 468c mov ip, r1 + 8001684: 4462 add r2, ip + 8001686: 8812 ldrh r2, [r2, #0] + 8001688: 0592 lsls r2, r2, #22 + 800168a: 0d92 lsrs r2, r2, #22 + 800168c: 641a str r2, [r3, #64] ; 0x40 + 800168e: 6b99 ldr r1, [r3, #56] ; 0x38 + 8001690: 468c mov ip, r1 + 8001692: 4462 add r2, ip + 8001694: 639a str r2, [r3, #56] ; 0x38 + 8001696: 6bdb ldr r3, [r3, #60] ; 0x3c + 8001698: 2b00 cmp r3, #0 + 800169a: d127 bne.n 80016ec + 800169c: 00eb lsls r3, r5, #3 + 800169e: 1b5b subs r3, r3, r5 + 80016a0: 009b lsls r3, r3, #2 + 80016a2: 18e3 adds r3, r4, r3 + 80016a4: 3328 adds r3, #40 ; 0x28 + 80016a6: 7819 ldrb r1, [r3, #0] + 80016a8: 0020 movs r0, r4 + 80016aa: f001 fb49 bl 8002d40 + 80016ae: e5e3 b.n 8001278 + 80016b0: 0011 movs r1, r2 + 80016b2: 8dd2 ldrh r2, [r2, #46] ; 0x2e + 80016b4: 6b89 ldr r1, [r1, #56] ; 0x38 + 80016b6: f7ff fc3b bl 8000f30 + 80016ba: e7c4 b.n 8001646 + 80016bc: 2250 movs r2, #80 ; 0x50 + 80016be: 5a82 ldrh r2, [r0, r2] + 80016c0: 00db lsls r3, r3, #3 + 80016c2: 18c3 adds r3, r0, r3 + 80016c4: 18d3 adds r3, r2, r3 + 80016c6: 4a27 ldr r2, [pc, #156] ; (8001764 ) + 80016c8: 4694 mov ip, r2 + 80016ca: 4463 add r3, ip + 80016cc: 881b ldrh r3, [r3, #0] + 80016ce: 059b lsls r3, r3, #22 + 80016d0: 0d9b lsrs r3, r3, #22 + 80016d2: 00ea lsls r2, r5, #3 + 80016d4: 1b52 subs r2, r2, r5 + 80016d6: 0092 lsls r2, r2, #2 + 80016d8: 18a2 adds r2, r4, r2 + 80016da: 6413 str r3, [r2, #64] ; 0x40 + 80016dc: 2b00 cmp r3, #0 + 80016de: d0b2 beq.n 8001646 + 80016e0: 0011 movs r1, r2 + 80016e2: 8e12 ldrh r2, [r2, #48] ; 0x30 + 80016e4: 6b89 ldr r1, [r1, #56] ; 0x38 + 80016e6: f7ff fc23 bl 8000f30 + 80016ea: e7ac b.n 8001646 + 80016ec: 00e9 lsls r1, r5, #3 + 80016ee: 1b49 subs r1, r1, r5 + 80016f0: 0089 lsls r1, r1, #2 + 80016f2: 1861 adds r1, r4, r1 + 80016f4: 3128 adds r1, #40 ; 0x28 + 80016f6: 7809 ldrb r1, [r1, #0] + 80016f8: 0020 movs r0, r4 + 80016fa: f7ff fc2f bl 8000f5c + 80016fe: e5bb b.n 8001278 + 8001700: 2144 movs r1, #68 ; 0x44 + 8001702: 5a5a ldrh r2, [r3, r1] + 8001704: 4819 ldr r0, [pc, #100] ; (800176c ) + 8001706: 4002 ands r2, r0 + 8001708: 525a strh r2, [r3, r1] + 800170a: 0020 movs r0, r4 + 800170c: f001 fb2b bl 8002d66 + 8001710: 2100 movs r1, #0 + 8001712: 0020 movs r0, r4 + 8001714: f7fe ff43 bl 800059e + 8001718: e55d b.n 80011d6 + 800171a: 2240 movs r2, #64 ; 0x40 + 800171c: 5a99 ldrh r1, [r3, r2] + 800171e: 2004 movs r0, #4 + 8001720: 4381 bics r1, r0 + 8001722: 5299 strh r1, [r3, r2] + 8001724: 4b12 ldr r3, [pc, #72] ; (8001770 ) + 8001726: 6821 ldr r1, [r4, #0] + 8001728: 528b strh r3, [r1, r2] + 800172a: 0020 movs r0, r4 + 800172c: f001 fb3e bl 8002dac + 8001730: 6821 ldr r1, [r4, #0] + 8001732: 2244 movs r2, #68 ; 0x44 + 8001734: 5a8b ldrh r3, [r1, r2] + 8001736: 480f ldr r0, [pc, #60] ; (8001774 ) + 8001738: 4003 ands r3, r0 + 800173a: 528b strh r3, [r1, r2] + 800173c: e565 b.n 800120a + 800173e: 0020 movs r0, r4 + 8001740: f001 fb22 bl 8002d88 + 8001744: e57b b.n 800123e + 8001746: 2144 movs r1, #68 ; 0x44 + 8001748: 5a5a ldrh r2, [r3, r1] + 800174a: 480b ldr r0, [pc, #44] ; (8001778 ) + 800174c: 4002 ands r2, r0 + 800174e: 525a strh r2, [r3, r1] + 8001750: 0020 movs r0, r4 + 8001752: f001 fb01 bl 8002d58 + 8001756: e578 b.n 800124a + 8001758: 00000402 .word 0x00000402 + 800175c: 00000f0f .word 0x00000f0f + 8001760: ffff80c0 .word 0xffff80c0 + 8001764: 00000406 .word 0x00000406 + 8001768: ffffc080 .word 0xffffc080 + 800176c: fffffbff .word 0xfffffbff + 8001770: ffffbd00 .word 0xffffbd00 + 8001774: ffffefff .word 0xffffefff + 8001778: fffffdff .word 0xfffffdff + +0800177c : + 800177c: b510 push {r4, lr} + 800177e: 060c lsls r4, r1, #24 + 8001780: d50f bpl.n 80017a2 + 8001782: 247f movs r4, #127 ; 0x7f + 8001784: 4021 ands r1, r4 + 8001786: 00cc lsls r4, r1, #3 + 8001788: 1a61 subs r1, r4, r1 + 800178a: 0089 lsls r1, r1, #2 + 800178c: 3128 adds r1, #40 ; 0x28 + 800178e: 1840 adds r0, r0, r1 + 8001790: 2a00 cmp r2, #0 + 8001792: d00d beq.n 80017b0 + 8001794: 2201 movs r2, #1 + 8001796: 7282 strb r2, [r0, #10] + 8001798: 80c3 strh r3, [r0, #6] + 800179a: 0c1b lsrs r3, r3, #16 + 800179c: 8103 strh r3, [r0, #8] + 800179e: 2000 movs r0, #0 + 80017a0: bd10 pop {r4, pc} + 80017a2: 00cc lsls r4, r1, #3 + 80017a4: 1a61 subs r1, r4, r1 + 80017a6: 0089 lsls r1, r1, #2 + 80017a8: 3109 adds r1, #9 + 80017aa: 31ff adds r1, #255 ; 0xff + 80017ac: 1840 adds r0, r0, r1 + 80017ae: e7ef b.n 8001790 + 80017b0: 7282 strb r2, [r0, #10] + 80017b2: 8083 strh r3, [r0, #4] + 80017b4: e7f3 b.n 800179e + ... + +080017b8 : + 80017b8: 4b01 ldr r3, [pc, #4] ; (80017c0 ) + 80017ba: 6818 ldr r0, [r3, #0] + 80017bc: 4770 bx lr + 80017be: 46c0 nop ; (mov r8, r8) + 80017c0: 20000110 .word 0x20000110 + +080017c4 : + 80017c4: b510 push {r4, lr} + 80017c6: 21fa movs r1, #250 ; 0xfa + 80017c8: 0089 lsls r1, r1, #2 + 80017ca: f7fe fc9d bl 8000108 <__udivsi3> + 80017ce: 3801 subs r0, #1 + 80017d0: 4b03 ldr r3, [pc, #12] ; (80017e0 ) + 80017d2: 6058 str r0, [r3, #4] + 80017d4: 2200 movs r2, #0 + 80017d6: 609a str r2, [r3, #8] + 80017d8: 3205 adds r2, #5 + 80017da: 601a str r2, [r3, #0] + 80017dc: bd10 pop {r4, pc} + 80017de: 46c0 nop ; (mov r8, r8) + 80017e0: e000e010 .word 0xe000e010 + +080017e4 : + 80017e4: 4b01 ldr r3, [pc, #4] ; (80017ec ) + 80017e6: 6018 str r0, [r3, #0] + 80017e8: 4770 bx lr + 80017ea: 46c0 nop ; (mov r8, r8) + 80017ec: 20000110 .word 0x20000110 + +080017f0 : + 80017f0: 2386 movs r3, #134 ; 0x86 + 80017f2: 009b lsls r3, r3, #2 + 80017f4: 58c3 ldr r3, [r0, r3] + 80017f6: 2b00 cmp r3, #0 + 80017f8: d005 beq.n 8001806 + 80017fa: 2285 movs r2, #133 ; 0x85 + 80017fc: 0092 lsls r2, r2, #2 + 80017fe: 2100 movs r1, #0 + 8001800: 5099 str r1, [r3, r2] + 8001802: 2000 movs r0, #0 + 8001804: 4770 bx lr + 8001806: 2002 movs r0, #2 + 8001808: e7fc b.n 8001804 + ... + +0800180c : + 800180c: b510 push {r4, lr} + 800180e: 2387 movs r3, #135 ; 0x87 + 8001810: 009b lsls r3, r3, #2 + 8001812: 58c3 ldr r3, [r0, r3] + 8001814: 2b00 cmp r3, #0 + 8001816: d00f beq.n 8001838 + 8001818: 2286 movs r2, #134 ; 0x86 + 800181a: 0092 lsls r2, r2, #2 + 800181c: 5884 ldr r4, [r0, r2] + 800181e: 3a18 subs r2, #24 + 8001820: 5ca0 ldrb r0, [r4, r2] + 8001822: 28ff cmp r0, #255 ; 0xff + 8001824: d008 beq.n 8001838 + 8001826: 4a05 ldr r2, [pc, #20] ; (800183c ) + 8001828: 5ca2 ldrb r2, [r4, r2] + 800182a: 689b ldr r3, [r3, #8] + 800182c: 0021 movs r1, r4 + 800182e: 4798 blx r3 + 8001830: 2380 movs r3, #128 ; 0x80 + 8001832: 009b lsls r3, r3, #2 + 8001834: 22ff movs r2, #255 ; 0xff + 8001836: 54e2 strb r2, [r4, r3] + 8001838: 2000 movs r0, #0 + 800183a: bd10 pop {r4, pc} + 800183c: 00000201 .word 0x00000201 + +08001840 : + 8001840: 2343 movs r3, #67 ; 0x43 + 8001842: 8003 strh r3, [r0, #0] + 8001844: 4800 ldr r0, [pc, #0] ; (8001848 ) + 8001846: 4770 bx lr + 8001848: 20000038 .word 0x20000038 + +0800184c : + 800184c: 2343 movs r3, #67 ; 0x43 + 800184e: 8003 strh r3, [r0, #0] + 8001850: 4800 ldr r0, [pc, #0] ; (8001854 ) + 8001852: 4770 bx lr + 8001854: 2000007c .word 0x2000007c + +08001858 : + 8001858: 2343 movs r3, #67 ; 0x43 + 800185a: 8003 strh r3, [r0, #0] + 800185c: 4800 ldr r0, [pc, #0] ; (8001860 ) + 800185e: 4770 bx lr + 8001860: 200000cc .word 0x200000cc + +08001864 : + 8001864: 230a movs r3, #10 + 8001866: 8003 strh r3, [r0, #0] + 8001868: 4800 ldr r0, [pc, #0] ; (800186c ) + 800186a: 4770 bx lr + 800186c: 200000c0 .word 0x200000c0 + +08001870 : + 8001870: b570 push {r4, r5, r6, lr} + 8001872: 0004 movs r4, r0 + 8001874: 2686 movs r6, #134 ; 0x86 + 8001876: 00b6 lsls r6, r6, #2 + 8001878: 5985 ldr r5, [r0, r6] + 800187a: f001 fb54 bl 8002f26 + 800187e: 2383 movs r3, #131 ; 0x83 + 8001880: 009b lsls r3, r3, #2 + 8001882: 50e8 str r0, [r5, r3] + 8001884: 59a3 ldr r3, [r4, r6] + 8001886: 2b00 cmp r3, #0 + 8001888: d00a beq.n 80018a0 + 800188a: 2383 movs r3, #131 ; 0x83 + 800188c: 009b lsls r3, r3, #2 + 800188e: 18e9 adds r1, r5, r3 + 8001890: 3b08 subs r3, #8 + 8001892: 58e8 ldr r0, [r5, r3] + 8001894: 3318 adds r3, #24 + 8001896: 58e3 ldr r3, [r4, r3] + 8001898: 68db ldr r3, [r3, #12] + 800189a: 4798 blx r3 + 800189c: 2000 movs r0, #0 + 800189e: bd70 pop {r4, r5, r6, pc} + 80018a0: 2002 movs r0, #2 + 80018a2: e7fc b.n 800189e + +080018a4 : + 80018a4: b570 push {r4, r5, r6, lr} + 80018a6: 0005 movs r5, r0 + 80018a8: 000c movs r4, r1 + 80018aa: 7809 ldrb r1, [r1, #0] + 80018ac: 2360 movs r3, #96 ; 0x60 + 80018ae: 400b ands r3, r1 + 80018b0: d02c beq.n 800190c + 80018b2: 2b20 cmp r3, #32 + 80018b4: d10a bne.n 80018cc + 80018b6: 88e2 ldrh r2, [r4, #6] + 80018b8: 2a00 cmp r2, #0 + 80018ba: d109 bne.n 80018d0 + 80018bc: 7860 ldrb r0, [r4, #1] + 80018be: 2387 movs r3, #135 ; 0x87 + 80018c0: 009b lsls r3, r3, #2 + 80018c2: 58eb ldr r3, [r5, r3] + 80018c4: 689b ldr r3, [r3, #8] + 80018c6: 2200 movs r2, #0 + 80018c8: 0021 movs r1, r4 + 80018ca: 4798 blx r3 + 80018cc: 2000 movs r0, #0 + 80018ce: bd70 pop {r4, r5, r6, pc} + 80018d0: 33f9 adds r3, #249 ; 0xf9 + 80018d2: 33ff adds r3, #255 ; 0xff + 80018d4: 58c6 ldr r6, [r0, r3] + 80018d6: b249 sxtb r1, r1 + 80018d8: 2900 cmp r1, #0 + 80018da: da0b bge.n 80018f4 + 80018dc: 7860 ldrb r0, [r4, #1] + 80018de: 3304 adds r3, #4 + 80018e0: 58eb ldr r3, [r5, r3] + 80018e2: 689b ldr r3, [r3, #8] + 80018e4: 0031 movs r1, r6 + 80018e6: 4798 blx r3 + 80018e8: 88e2 ldrh r2, [r4, #6] + 80018ea: 0031 movs r1, r6 + 80018ec: 0028 movs r0, r5 + 80018ee: f000 fca1 bl 8002234 + 80018f2: e7eb b.n 80018cc + 80018f4: 7862 ldrb r2, [r4, #1] + 80018f6: 2380 movs r3, #128 ; 0x80 + 80018f8: 009b lsls r3, r3, #2 + 80018fa: 54f2 strb r2, [r6, r3] + 80018fc: 88e2 ldrh r2, [r4, #6] + 80018fe: 4b07 ldr r3, [pc, #28] ; (800191c ) + 8001900: 54f2 strb r2, [r6, r3] + 8001902: 88e2 ldrh r2, [r4, #6] + 8001904: 0031 movs r1, r6 + 8001906: f000 fcab bl 8002260 + 800190a: e7df b.n 80018cc + 800190c: 7863 ldrb r3, [r4, #1] + 800190e: 2b0a cmp r3, #10 + 8001910: d1dc bne.n 80018cc + 8001912: 2201 movs r2, #1 + 8001914: 4902 ldr r1, [pc, #8] ; (8001920 ) + 8001916: f000 fc8d bl 8002234 + 800191a: e7d7 b.n 80018cc + 800191c: 00000201 .word 0x00000201 + 8001920: 20000190 .word 0x20000190 + +08001924 : + 8001924: b570 push {r4, r5, r6, lr} + 8001926: 0004 movs r4, r0 + 8001928: 2181 movs r1, #129 ; 0x81 + 800192a: f001 faac bl 8002e86 + 800192e: 2101 movs r1, #1 + 8001930: 0020 movs r0, r4 + 8001932: f001 faa8 bl 8002e86 + 8001936: 2182 movs r1, #130 ; 0x82 + 8001938: 0020 movs r0, r4 + 800193a: f001 faa4 bl 8002e86 + 800193e: 2386 movs r3, #134 ; 0x86 + 8001940: 009b lsls r3, r3, #2 + 8001942: 58e3 ldr r3, [r4, r3] + 8001944: 2b00 cmp r3, #0 + 8001946: d00b beq.n 8001960 + 8001948: 2387 movs r3, #135 ; 0x87 + 800194a: 009b lsls r3, r3, #2 + 800194c: 58e3 ldr r3, [r4, r3] + 800194e: 685b ldr r3, [r3, #4] + 8001950: 4798 blx r3 + 8001952: 2586 movs r5, #134 ; 0x86 + 8001954: 00ad lsls r5, r5, #2 + 8001956: 5960 ldr r0, [r4, r5] + 8001958: f001 faf0 bl 8002f3c + 800195c: 2300 movs r3, #0 + 800195e: 5163 str r3, [r4, r5] + 8001960: 2000 movs r0, #0 + 8001962: bd70 pop {r4, r5, r6, pc} + +08001964 : + 8001964: b570 push {r4, r5, r6, lr} + 8001966: 0004 movs r4, r0 + 8001968: 7c03 ldrb r3, [r0, #16] + 800196a: 2b00 cmp r3, #0 + 800196c: d134 bne.n 80019d8 + 800196e: 2580 movs r5, #128 ; 0x80 + 8001970: 00ad lsls r5, r5, #2 + 8001972: 002b movs r3, r5 + 8001974: 2202 movs r2, #2 + 8001976: 2181 movs r1, #129 ; 0x81 + 8001978: f001 fa79 bl 8002e6e + 800197c: 002b movs r3, r5 + 800197e: 2202 movs r2, #2 + 8001980: 2101 movs r1, #1 + 8001982: 0020 movs r0, r4 + 8001984: f001 fa73 bl 8002e6e + 8001988: 2308 movs r3, #8 + 800198a: 2203 movs r2, #3 + 800198c: 2182 movs r1, #130 ; 0x82 + 800198e: 0020 movs r0, r4 + 8001990: f001 fa6d bl 8002e6e + 8001994: 2087 movs r0, #135 ; 0x87 + 8001996: 0080 lsls r0, r0, #2 + 8001998: f001 facc bl 8002f34 + 800199c: 0005 movs r5, r0 + 800199e: 2386 movs r3, #134 ; 0x86 + 80019a0: 009b lsls r3, r3, #2 + 80019a2: 50e0 str r0, [r4, r3] + 80019a4: 2800 cmp r0, #0 + 80019a6: d02d beq.n 8001a04 + 80019a8: 3304 adds r3, #4 + 80019aa: 58e3 ldr r3, [r4, r3] + 80019ac: 681b ldr r3, [r3, #0] + 80019ae: 4798 blx r3 + 80019b0: 2300 movs r3, #0 + 80019b2: 2285 movs r2, #133 ; 0x85 + 80019b4: 0092 lsls r2, r2, #2 + 80019b6: 50ab str r3, [r5, r2] + 80019b8: 3204 adds r2, #4 + 80019ba: 50ab str r3, [r5, r2] + 80019bc: 7c23 ldrb r3, [r4, #16] + 80019be: 2b00 cmp r3, #0 + 80019c0: d016 beq.n 80019f0 + 80019c2: 2381 movs r3, #129 ; 0x81 + 80019c4: 009b lsls r3, r3, #2 + 80019c6: 58ea ldr r2, [r5, r3] + 80019c8: 3bc5 subs r3, #197 ; 0xc5 + 80019ca: 3bff subs r3, #255 ; 0xff + 80019cc: 2101 movs r1, #1 + 80019ce: 0020 movs r0, r4 + 80019d0: f001 faa0 bl 8002f14 + 80019d4: 2000 movs r0, #0 + 80019d6: bd70 pop {r4, r5, r6, pc} + 80019d8: 2340 movs r3, #64 ; 0x40 + 80019da: 2202 movs r2, #2 + 80019dc: 2181 movs r1, #129 ; 0x81 + 80019de: f001 fa46 bl 8002e6e + 80019e2: 2340 movs r3, #64 ; 0x40 + 80019e4: 2202 movs r2, #2 + 80019e6: 2101 movs r1, #1 + 80019e8: 0020 movs r0, r4 + 80019ea: f001 fa40 bl 8002e6e + 80019ee: e7cb b.n 8001988 + 80019f0: 3380 adds r3, #128 ; 0x80 + 80019f2: 3a14 subs r2, #20 + 80019f4: 58aa ldr r2, [r5, r2] + 80019f6: 009b lsls r3, r3, #2 + 80019f8: 2101 movs r1, #1 + 80019fa: 0020 movs r0, r4 + 80019fc: f001 fa8a bl 8002f14 + 8001a00: 2000 movs r0, #0 + 8001a02: e7e8 b.n 80019d6 + 8001a04: 2001 movs r0, #1 + 8001a06: e7e6 b.n 80019d6 + +08001a08 : + 8001a08: 2900 cmp r1, #0 + 8001a0a: d004 beq.n 8001a16 + 8001a0c: 2387 movs r3, #135 ; 0x87 + 8001a0e: 009b lsls r3, r3, #2 + 8001a10: 50c1 str r1, [r0, r3] + 8001a12: 2000 movs r0, #0 + 8001a14: 4770 bx lr + 8001a16: 2002 movs r0, #2 + 8001a18: e7fc b.n 8001a14 + +08001a1a : + 8001a1a: 2386 movs r3, #134 ; 0x86 + 8001a1c: 009b lsls r3, r3, #2 + 8001a1e: 58c3 ldr r3, [r0, r3] + 8001a20: 2082 movs r0, #130 ; 0x82 + 8001a22: 0080 lsls r0, r0, #2 + 8001a24: 5019 str r1, [r3, r0] + 8001a26: 2184 movs r1, #132 ; 0x84 + 8001a28: 0089 lsls r1, r1, #2 + 8001a2a: 505a str r2, [r3, r1] + 8001a2c: 2000 movs r0, #0 + 8001a2e: 4770 bx lr + +08001a30 : + 8001a30: 2386 movs r3, #134 ; 0x86 + 8001a32: 009b lsls r3, r3, #2 + 8001a34: 58c2 ldr r2, [r0, r3] + 8001a36: 3b14 subs r3, #20 + 8001a38: 50d1 str r1, [r2, r3] + 8001a3a: 2000 movs r0, #0 + 8001a3c: 4770 bx lr + +08001a3e : + 8001a3e: b510 push {r4, lr} + 8001a40: 2386 movs r3, #134 ; 0x86 + 8001a42: 009b lsls r3, r3, #2 + 8001a44: 58c2 ldr r2, [r0, r3] + 8001a46: 2a00 cmp r2, #0 + 8001a48: d015 beq.n 8001a76 + 8001a4a: 3b04 subs r3, #4 + 8001a4c: 58d1 ldr r1, [r2, r3] + 8001a4e: 2301 movs r3, #1 + 8001a50: 2900 cmp r1, #0 + 8001a52: d001 beq.n 8001a58 + 8001a54: 0018 movs r0, r3 + 8001a56: bd10 pop {r4, pc} + 8001a58: 2385 movs r3, #133 ; 0x85 + 8001a5a: 009b lsls r3, r3, #2 + 8001a5c: 3101 adds r1, #1 + 8001a5e: 50d1 str r1, [r2, r3] + 8001a60: 3b04 subs r3, #4 + 8001a62: 5ad3 ldrh r3, [r2, r3] + 8001a64: 2182 movs r1, #130 ; 0x82 + 8001a66: 0089 lsls r1, r1, #2 + 8001a68: 5852 ldr r2, [r2, r1] + 8001a6a: 3988 subs r1, #136 ; 0x88 + 8001a6c: 39ff subs r1, #255 ; 0xff + 8001a6e: f001 fa48 bl 8002f02 + 8001a72: 2300 movs r3, #0 + 8001a74: e7ee b.n 8001a54 + 8001a76: 2302 movs r3, #2 + 8001a78: e7ec b.n 8001a54 + +08001a7a : + 8001a7a: b510 push {r4, lr} + 8001a7c: 2386 movs r3, #134 ; 0x86 + 8001a7e: 009b lsls r3, r3, #2 + 8001a80: 58c2 ldr r2, [r0, r3] + 8001a82: 2a00 cmp r2, #0 + 8001a84: d016 beq.n 8001ab4 + 8001a86: 7c03 ldrb r3, [r0, #16] + 8001a88: 2b00 cmp r3, #0 + 8001a8a: d009 beq.n 8001aa0 + 8001a8c: 2381 movs r3, #129 ; 0x81 + 8001a8e: 009b lsls r3, r3, #2 + 8001a90: 58d2 ldr r2, [r2, r3] + 8001a92: 3bc5 subs r3, #197 ; 0xc5 + 8001a94: 3bff subs r3, #255 ; 0xff + 8001a96: 2101 movs r1, #1 + 8001a98: f001 fa3c bl 8002f14 + 8001a9c: 2000 movs r0, #0 + 8001a9e: bd10 pop {r4, pc} + 8001aa0: 3380 adds r3, #128 ; 0x80 + 8001aa2: 2181 movs r1, #129 ; 0x81 + 8001aa4: 0089 lsls r1, r1, #2 + 8001aa6: 5852 ldr r2, [r2, r1] + 8001aa8: 009b lsls r3, r3, #2 + 8001aaa: 2101 movs r1, #1 + 8001aac: f001 fa32 bl 8002f14 + 8001ab0: 2000 movs r0, #0 + 8001ab2: e7f4 b.n 8001a9e + 8001ab4: 2002 movs r0, #2 + 8001ab6: e7f2 b.n 8001a9e + +08001ab8 : + 8001ab8: b510 push {r4, lr} + 8001aba: 2800 cmp r0, #0 + 8001abc: d016 beq.n 8001aec + 8001abe: 2385 movs r3, #133 ; 0x85 + 8001ac0: 009b lsls r3, r3, #2 + 8001ac2: 58c3 ldr r3, [r0, r3] + 8001ac4: 2b00 cmp r3, #0 + 8001ac6: d003 beq.n 8001ad0 + 8001ac8: 2385 movs r3, #133 ; 0x85 + 8001aca: 009b lsls r3, r3, #2 + 8001acc: 2400 movs r4, #0 + 8001ace: 50c4 str r4, [r0, r3] + 8001ad0: 2900 cmp r1, #0 + 8001ad2: d002 beq.n 8001ada + 8001ad4: 2384 movs r3, #132 ; 0x84 + 8001ad6: 009b lsls r3, r3, #2 + 8001ad8: 50c1 str r1, [r0, r3] + 8001ada: 23fe movs r3, #254 ; 0xfe + 8001adc: 005b lsls r3, r3, #1 + 8001ade: 2101 movs r1, #1 + 8001ae0: 54c1 strb r1, [r0, r3] + 8001ae2: 7002 strb r2, [r0, #0] + 8001ae4: f001 f978 bl 8002dd8 + 8001ae8: 2000 movs r0, #0 + 8001aea: bd10 pop {r4, pc} + 8001aec: 2002 movs r0, #2 + 8001aee: e7fc b.n 8001aea + +08001af0 : + 8001af0: 2900 cmp r1, #0 + 8001af2: d004 beq.n 8001afe + 8001af4: 2385 movs r3, #133 ; 0x85 + 8001af6: 009b lsls r3, r3, #2 + 8001af8: 50c1 str r1, [r0, r3] + 8001afa: 2000 movs r0, #0 + 8001afc: 4770 bx lr + 8001afe: 2002 movs r0, #2 + 8001b00: e7fc b.n 8001afc + +08001b02 : + 8001b02: b510 push {r4, lr} + 8001b04: f001 f9aa bl 8002e5c + 8001b08: 2000 movs r0, #0 + 8001b0a: bd10 pop {r4, pc} + +08001b0c : + 8001b0c: b510 push {r4, lr} + 8001b0e: 2385 movs r3, #133 ; 0x85 + 8001b10: 009b lsls r3, r3, #2 + 8001b12: 58c3 ldr r3, [r0, r3] + 8001b14: 2b00 cmp r3, #0 + 8001b16: d005 beq.n 8001b24 + 8001b18: 681b ldr r3, [r3, #0] + 8001b1a: 4798 blx r3 + 8001b1c: 1e43 subs r3, r0, #1 + 8001b1e: 4198 sbcs r0, r3 + 8001b20: 0040 lsls r0, r0, #1 + 8001b22: bd10 pop {r4, pc} + 8001b24: 2002 movs r0, #2 + 8001b26: e7fc b.n 8001b22 + +08001b28 : + 8001b28: b510 push {r4, lr} + 8001b2a: 2385 movs r3, #133 ; 0x85 + 8001b2c: 009b lsls r3, r3, #2 + 8001b2e: 58c3 ldr r3, [r0, r3] + 8001b30: 685b ldr r3, [r3, #4] + 8001b32: 4798 blx r3 + 8001b34: 2000 movs r0, #0 + 8001b36: bd10 pop {r4, pc} + +08001b38 : + 8001b38: b570 push {r4, r5, r6, lr} + 8001b3a: 0004 movs r4, r0 + 8001b3c: 2382 movs r3, #130 ; 0x82 + 8001b3e: 009b lsls r3, r3, #2 + 8001b40: 18c5 adds r5, r0, r3 + 8001b42: 0028 movs r0, r5 + 8001b44: f000 f911 bl 8001d6a + 8001b48: 23fa movs r3, #250 ; 0xfa + 8001b4a: 005b lsls r3, r3, #1 + 8001b4c: 2201 movs r2, #1 + 8001b4e: 50e2 str r2, [r4, r3] + 8001b50: 4b12 ldr r3, [pc, #72] ; (8001b9c ) + 8001b52: 5ae2 ldrh r2, [r4, r3] + 8001b54: 3b16 subs r3, #22 + 8001b56: 50e2 str r2, [r4, r3] + 8001b58: 3310 adds r3, #16 + 8001b5a: 5ce1 ldrb r1, [r4, r3] + 8001b5c: 3bea subs r3, #234 ; 0xea + 8001b5e: 3bff subs r3, #255 ; 0xff + 8001b60: 400b ands r3, r1 + 8001b62: 2b01 cmp r3, #1 + 8001b64: d00f beq.n 8001b86 + 8001b66: 2b00 cmp r3, #0 + 8001b68: d007 beq.n 8001b7a + 8001b6a: 2b02 cmp r3, #2 + 8001b6c: d010 beq.n 8001b90 + 8001b6e: 237f movs r3, #127 ; 0x7f + 8001b70: 4399 bics r1, r3 + 8001b72: 0020 movs r0, r4 + 8001b74: f001 f990 bl 8002e98 + 8001b78: e003 b.n 8001b82 + 8001b7a: 0029 movs r1, r5 + 8001b7c: 0020 movs r0, r4 + 8001b7e: f000 f913 bl 8001da8 + 8001b82: 2000 movs r0, #0 + 8001b84: bd70 pop {r4, r5, r6, pc} + 8001b86: 0029 movs r1, r5 + 8001b88: 0020 movs r0, r4 + 8001b8a: f000 faa9 bl 80020e0 + 8001b8e: e7f8 b.n 8001b82 + 8001b90: 0029 movs r1, r5 + 8001b92: 0020 movs r0, r4 + 8001b94: f000 fac3 bl 800211e + 8001b98: e7f3 b.n 8001b82 + 8001b9a: 46c0 nop ; (mov r8, r8) + 8001b9c: 0000020e .word 0x0000020e + +08001ba0 : + 8001ba0: b510 push {r4, lr} + 8001ba2: 0004 movs r4, r0 + 8001ba4: 0013 movs r3, r2 + 8001ba6: 2900 cmp r1, #0 + 8001ba8: d129 bne.n 8001bfe + 8001baa: 22fa movs r2, #250 ; 0xfa + 8001bac: 0052 lsls r2, r2, #1 + 8001bae: 5882 ldr r2, [r0, r2] + 8001bb0: 2a03 cmp r2, #3 + 8001bb2: d001 beq.n 8001bb8 + 8001bb4: 2000 movs r0, #0 + 8001bb6: bd10 pop {r4, pc} + 8001bb8: 1d42 adds r2, r0, #5 + 8001bba: 32ff adds r2, #255 ; 0xff + 8001bbc: 6891 ldr r1, [r2, #8] + 8001bbe: 68d2 ldr r2, [r2, #12] + 8001bc0: 4291 cmp r1, r2 + 8001bc2: d80f bhi.n 8001be4 + 8001bc4: 2385 movs r3, #133 ; 0x85 + 8001bc6: 009b lsls r3, r3, #2 + 8001bc8: 58c3 ldr r3, [r0, r3] + 8001bca: 691b ldr r3, [r3, #16] + 8001bcc: 2b00 cmp r3, #0 + 8001bce: d005 beq.n 8001bdc + 8001bd0: 22fe movs r2, #254 ; 0xfe + 8001bd2: 0052 lsls r2, r2, #1 + 8001bd4: 5c82 ldrb r2, [r0, r2] + 8001bd6: 2a03 cmp r2, #3 + 8001bd8: d100 bne.n 8001bdc + 8001bda: 4798 blx r3 + 8001bdc: 0020 movs r0, r4 + 8001bde: f000 fb57 bl 8002290 + 8001be2: e7e7 b.n 8001bb4 + 8001be4: 1a89 subs r1, r1, r2 + 8001be6: 3005 adds r0, #5 + 8001be8: 30ff adds r0, #255 ; 0xff + 8001bea: 6081 str r1, [r0, #8] + 8001bec: 428a cmp r2, r1 + 8001bee: d900 bls.n 8001bf2 + 8001bf0: 000a movs r2, r1 + 8001bf2: b292 uxth r2, r2 + 8001bf4: 0019 movs r1, r3 + 8001bf6: 0020 movs r0, r4 + 8001bf8: f000 fb42 bl 8002280 + 8001bfc: e7da b.n 8001bb4 + 8001bfe: 2385 movs r3, #133 ; 0x85 + 8001c00: 009b lsls r3, r3, #2 + 8001c02: 58c3 ldr r3, [r0, r3] + 8001c04: 699b ldr r3, [r3, #24] + 8001c06: 2b00 cmp r3, #0 + 8001c08: d0d4 beq.n 8001bb4 + 8001c0a: 22fe movs r2, #254 ; 0xfe + 8001c0c: 0052 lsls r2, r2, #1 + 8001c0e: 5c82 ldrb r2, [r0, r2] + 8001c10: 2a03 cmp r2, #3 + 8001c12: d1cf bne.n 8001bb4 + 8001c14: 4798 blx r3 + 8001c16: e7cd b.n 8001bb4 + +08001c18 : + 8001c18: b570 push {r4, r5, r6, lr} + 8001c1a: 0004 movs r4, r0 + 8001c1c: 0013 movs r3, r2 + 8001c1e: 2900 cmp r1, #0 + 8001c20: d14e bne.n 8001cc0 + 8001c22: 22fa movs r2, #250 ; 0xfa + 8001c24: 0052 lsls r2, r2, #1 + 8001c26: 5882 ldr r2, [r0, r2] + 8001c28: 2a02 cmp r2, #2 + 8001c2a: d006 beq.n 8001c3a + 8001c2c: 2380 movs r3, #128 ; 0x80 + 8001c2e: 009b lsls r3, r3, #2 + 8001c30: 5ce3 ldrb r3, [r4, r3] + 8001c32: 2b01 cmp r3, #1 + 8001c34: d03f beq.n 8001cb6 + 8001c36: 2000 movs r0, #0 + 8001c38: bd70 pop {r4, r5, r6, pc} + 8001c3a: 69c2 ldr r2, [r0, #28] + 8001c3c: 6a05 ldr r5, [r0, #32] + 8001c3e: 42aa cmp r2, r5 + 8001c40: d81e bhi.n 8001c80 + 8001c42: 6986 ldr r6, [r0, #24] + 8001c44: 0029 movs r1, r5 + 8001c46: 0030 movs r0, r6 + 8001c48: f7fe fae4 bl 8000214 <__aeabi_uidivmod> + 8001c4c: 2900 cmp r1, #0 + 8001c4e: d106 bne.n 8001c5e + 8001c50: 42b5 cmp r5, r6 + 8001c52: d804 bhi.n 8001c5e + 8001c54: 23fc movs r3, #252 ; 0xfc + 8001c56: 005b lsls r3, r3, #1 + 8001c58: 58e3 ldr r3, [r4, r3] + 8001c5a: 429e cmp r6, r3 + 8001c5c: d31d bcc.n 8001c9a + 8001c5e: 2385 movs r3, #133 ; 0x85 + 8001c60: 009b lsls r3, r3, #2 + 8001c62: 58e3 ldr r3, [r4, r3] + 8001c64: 68db ldr r3, [r3, #12] + 8001c66: 2b00 cmp r3, #0 + 8001c68: d006 beq.n 8001c78 + 8001c6a: 22fe movs r2, #254 ; 0xfe + 8001c6c: 0052 lsls r2, r2, #1 + 8001c6e: 5ca2 ldrb r2, [r4, r2] + 8001c70: 2a03 cmp r2, #3 + 8001c72: d101 bne.n 8001c78 + 8001c74: 0020 movs r0, r4 + 8001c76: 4798 blx r3 + 8001c78: 0020 movs r0, r4 + 8001c7a: f000 fb15 bl 80022a8 + 8001c7e: e7d5 b.n 8001c2c + 8001c80: 1b52 subs r2, r2, r5 + 8001c82: 61c2 str r2, [r0, #28] + 8001c84: b292 uxth r2, r2 + 8001c86: 0019 movs r1, r3 + 8001c88: f000 fae2 bl 8002250 + 8001c8c: 2300 movs r3, #0 + 8001c8e: 2200 movs r2, #0 + 8001c90: 2100 movs r1, #0 + 8001c92: 0020 movs r0, r4 + 8001c94: f001 f93e bl 8002f14 + 8001c98: e7c8 b.n 8001c2c + 8001c9a: 2200 movs r2, #0 + 8001c9c: 0020 movs r0, r4 + 8001c9e: f000 fad7 bl 8002250 + 8001ca2: 23fc movs r3, #252 ; 0xfc + 8001ca4: 005b lsls r3, r3, #1 + 8001ca6: 2200 movs r2, #0 + 8001ca8: 50e2 str r2, [r4, r3] + 8001caa: 2300 movs r3, #0 + 8001cac: 2100 movs r1, #0 + 8001cae: 0020 movs r0, r4 + 8001cb0: f001 f930 bl 8002f14 + 8001cb4: e7ba b.n 8001c2c + 8001cb6: 2380 movs r3, #128 ; 0x80 + 8001cb8: 009b lsls r3, r3, #2 + 8001cba: 2200 movs r2, #0 + 8001cbc: 54e2 strb r2, [r4, r3] + 8001cbe: e7ba b.n 8001c36 + 8001cc0: 2385 movs r3, #133 ; 0x85 + 8001cc2: 009b lsls r3, r3, #2 + 8001cc4: 58c3 ldr r3, [r0, r3] + 8001cc6: 695b ldr r3, [r3, #20] + 8001cc8: 2b00 cmp r3, #0 + 8001cca: d0b4 beq.n 8001c36 + 8001ccc: 22fe movs r2, #254 ; 0xfe + 8001cce: 0052 lsls r2, r2, #1 + 8001cd0: 5c82 ldrb r2, [r0, r2] + 8001cd2: 2a03 cmp r2, #3 + 8001cd4: d1af bne.n 8001c36 + 8001cd6: 4798 blx r3 + 8001cd8: e7ad b.n 8001c36 + +08001cda : + 8001cda: b570 push {r4, r5, r6, lr} + 8001cdc: 0004 movs r4, r0 + 8001cde: 2340 movs r3, #64 ; 0x40 + 8001ce0: 2200 movs r2, #0 + 8001ce2: 2100 movs r1, #0 + 8001ce4: f001 f8c3 bl 8002e6e + 8001ce8: 2540 movs r5, #64 ; 0x40 + 8001cea: 2388 movs r3, #136 ; 0x88 + 8001cec: 005b lsls r3, r3, #1 + 8001cee: 50e5 str r5, [r4, r3] + 8001cf0: 3bd0 subs r3, #208 ; 0xd0 + 8001cf2: 2200 movs r2, #0 + 8001cf4: 2180 movs r1, #128 ; 0x80 + 8001cf6: 0020 movs r0, r4 + 8001cf8: f001 f8b9 bl 8002e6e + 8001cfc: 6225 str r5, [r4, #32] + 8001cfe: 23fe movs r3, #254 ; 0xfe + 8001d00: 005b lsls r3, r3, #1 + 8001d02: 2201 movs r2, #1 + 8001d04: 54e2 strb r2, [r4, r3] + 8001d06: 331c adds r3, #28 + 8001d08: 58e3 ldr r3, [r4, r3] + 8001d0a: 2b00 cmp r3, #0 + 8001d0c: d006 beq.n 8001d1c + 8001d0e: 7921 ldrb r1, [r4, #4] + 8001d10: 2385 movs r3, #133 ; 0x85 + 8001d12: 009b lsls r3, r3, #2 + 8001d14: 58e3 ldr r3, [r4, r3] + 8001d16: 685b ldr r3, [r3, #4] + 8001d18: 0020 movs r0, r4 + 8001d1a: 4798 blx r3 + 8001d1c: 2000 movs r0, #0 + 8001d1e: bd70 pop {r4, r5, r6, pc} + +08001d20 : + 8001d20: 7401 strb r1, [r0, #16] + 8001d22: 2000 movs r0, #0 + 8001d24: 4770 bx lr + +08001d26 : + 8001d26: 23fe movs r3, #254 ; 0xfe + 8001d28: 005b lsls r3, r3, #1 + 8001d2a: 5cc1 ldrb r1, [r0, r3] + 8001d2c: 22fe movs r2, #254 ; 0xfe + 8001d2e: 32ff adds r2, #255 ; 0xff + 8001d30: 5481 strb r1, [r0, r2] + 8001d32: 3afa subs r2, #250 ; 0xfa + 8001d34: 3aff subs r2, #255 ; 0xff + 8001d36: 54c2 strb r2, [r0, r3] + 8001d38: 2000 movs r0, #0 + 8001d3a: 4770 bx lr + +08001d3c : + 8001d3c: 23fe movs r3, #254 ; 0xfe + 8001d3e: 33ff adds r3, #255 ; 0xff + 8001d40: 5cc2 ldrb r2, [r0, r3] + 8001d42: 3b01 subs r3, #1 + 8001d44: 54c2 strb r2, [r0, r3] + 8001d46: 2000 movs r0, #0 + 8001d48: 4770 bx lr + +08001d4a : + 8001d4a: b510 push {r4, lr} + 8001d4c: 23fe movs r3, #254 ; 0xfe + 8001d4e: 005b lsls r3, r3, #1 + 8001d50: 5cc3 ldrb r3, [r0, r3] + 8001d52: 2b03 cmp r3, #3 + 8001d54: d001 beq.n 8001d5a + 8001d56: 2000 movs r0, #0 + 8001d58: bd10 pop {r4, pc} + 8001d5a: 2385 movs r3, #133 ; 0x85 + 8001d5c: 009b lsls r3, r3, #2 + 8001d5e: 58c3 ldr r3, [r0, r3] + 8001d60: 69db ldr r3, [r3, #28] + 8001d62: 2b00 cmp r3, #0 + 8001d64: d0f7 beq.n 8001d56 + 8001d66: 4798 blx r3 + 8001d68: e7f5 b.n 8001d56 + +08001d6a : + 8001d6a: 780b ldrb r3, [r1, #0] + 8001d6c: 7003 strb r3, [r0, #0] + 8001d6e: 784b ldrb r3, [r1, #1] + 8001d70: 7043 strb r3, [r0, #1] + 8001d72: 78ca ldrb r2, [r1, #3] + 8001d74: 0212 lsls r2, r2, #8 + 8001d76: 788b ldrb r3, [r1, #2] + 8001d78: 189b adds r3, r3, r2 + 8001d7a: 8043 strh r3, [r0, #2] + 8001d7c: 794a ldrb r2, [r1, #5] + 8001d7e: 0212 lsls r2, r2, #8 + 8001d80: 790b ldrb r3, [r1, #4] + 8001d82: 189b adds r3, r3, r2 + 8001d84: 8083 strh r3, [r0, #4] + 8001d86: 79ca ldrb r2, [r1, #7] + 8001d88: 0212 lsls r2, r2, #8 + 8001d8a: 798b ldrb r3, [r1, #6] + 8001d8c: 189b adds r3, r3, r2 + 8001d8e: 80c3 strh r3, [r0, #6] + 8001d90: 4770 bx lr + +08001d92 : + 8001d92: b510 push {r4, lr} + 8001d94: 0004 movs r4, r0 + 8001d96: 2180 movs r1, #128 ; 0x80 + 8001d98: f001 f87e bl 8002e98 + 8001d9c: 2100 movs r1, #0 + 8001d9e: 0020 movs r0, r4 + 8001da0: f001 f87a bl 8002e98 + 8001da4: bd10 pop {r4, pc} + ... + +08001da8 : + 8001da8: b530 push {r4, r5, lr} + 8001daa: b083 sub sp, #12 + 8001dac: 0005 movs r5, r0 + 8001dae: 000c movs r4, r1 + 8001db0: 784b ldrb r3, [r1, #1] + 8001db2: 2b09 cmp r3, #9 + 8001db4: d900 bls.n 8001db8 + 8001db6: e18b b.n 80020d0 + 8001db8: 009b lsls r3, r3, #2 + 8001dba: 4ac1 ldr r2, [pc, #772] ; (80020c0 ) + 8001dbc: 58d3 ldr r3, [r2, r3] + 8001dbe: 469f mov pc, r3 + 8001dc0: 884a ldrh r2, [r1, #2] + 8001dc2: 0a13 lsrs r3, r2, #8 + 8001dc4: b299 uxth r1, r3 + 8001dc6: 2907 cmp r1, #7 + 8001dc8: d900 bls.n 8001dcc + 8001dca: e099 b.n 8001f00 + 8001dcc: 009b lsls r3, r3, #2 + 8001dce: 49bd ldr r1, [pc, #756] ; (80020c4 ) + 8001dd0: 58cb ldr r3, [r1, r3] + 8001dd2: 469f mov pc, r3 + 8001dd4: 7c00 ldrb r0, [r0, #16] + 8001dd6: 2384 movs r3, #132 ; 0x84 + 8001dd8: 009b lsls r3, r3, #2 + 8001dda: 58eb ldr r3, [r5, r3] + 8001ddc: 681b ldr r3, [r3, #0] + 8001dde: 466a mov r2, sp + 8001de0: 1d91 adds r1, r2, #6 + 8001de2: 4798 blx r3 + 8001de4: 466b mov r3, sp + 8001de6: 3306 adds r3, #6 + 8001de8: 881b ldrh r3, [r3, #0] + 8001dea: 2b00 cmp r3, #0 + 8001dec: d100 bne.n 8001df0 + 8001dee: e173 b.n 80020d8 + 8001df0: 88e2 ldrh r2, [r4, #6] + 8001df2: 2a00 cmp r2, #0 + 8001df4: d100 bne.n 8001df8 + 8001df6: e16f b.n 80020d8 + 8001df8: 1c19 adds r1, r3, #0 + 8001dfa: 4293 cmp r3, r2 + 8001dfc: d900 bls.n 8001e00 + 8001dfe: 1c11 adds r1, r2, #0 + 8001e00: b28a uxth r2, r1 + 8001e02: 466b mov r3, sp + 8001e04: 80d9 strh r1, [r3, #6] + 8001e06: 0001 movs r1, r0 + 8001e08: 0028 movs r0, r5 + 8001e0a: f000 fa13 bl 8002234 + 8001e0e: e163 b.n 80020d8 + 8001e10: 7c03 ldrb r3, [r0, #16] + 8001e12: 2b00 cmp r3, #0 + 8001e14: d109 bne.n 8001e2a + 8001e16: 2385 movs r3, #133 ; 0x85 + 8001e18: 009b lsls r3, r3, #2 + 8001e1a: 58c3 ldr r3, [r0, r3] + 8001e1c: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001e1e: 466a mov r2, sp + 8001e20: 1d90 adds r0, r2, #6 + 8001e22: 4798 blx r3 + 8001e24: 2302 movs r3, #2 + 8001e26: 7043 strb r3, [r0, #1] + 8001e28: e7dc b.n 8001de4 + 8001e2a: 2385 movs r3, #133 ; 0x85 + 8001e2c: 009b lsls r3, r3, #2 + 8001e2e: 58c3 ldr r3, [r0, r3] + 8001e30: 6adb ldr r3, [r3, #44] ; 0x2c + 8001e32: 466a mov r2, sp + 8001e34: 1d90 adds r0, r2, #6 + 8001e36: 4798 blx r3 + 8001e38: 2302 movs r3, #2 + 8001e3a: 7043 strb r3, [r0, #1] + 8001e3c: e7d2 b.n 8001de4 + 8001e3e: b2d3 uxtb r3, r2 + 8001e40: 2b05 cmp r3, #5 + 8001e42: d839 bhi.n 8001eb8 + 8001e44: 009a lsls r2, r3, #2 + 8001e46: 4ba0 ldr r3, [pc, #640] ; (80020c8 ) + 8001e48: 589b ldr r3, [r3, r2] + 8001e4a: 469f mov pc, r3 + 8001e4c: 7c00 ldrb r0, [r0, #16] + 8001e4e: 2384 movs r3, #132 ; 0x84 + 8001e50: 009b lsls r3, r3, #2 + 8001e52: 58eb ldr r3, [r5, r3] + 8001e54: 685b ldr r3, [r3, #4] + 8001e56: 466a mov r2, sp + 8001e58: 1d91 adds r1, r2, #6 + 8001e5a: 4798 blx r3 + 8001e5c: e7c2 b.n 8001de4 + 8001e5e: 7c00 ldrb r0, [r0, #16] + 8001e60: 2384 movs r3, #132 ; 0x84 + 8001e62: 009b lsls r3, r3, #2 + 8001e64: 58eb ldr r3, [r5, r3] + 8001e66: 689b ldr r3, [r3, #8] + 8001e68: 466a mov r2, sp + 8001e6a: 1d91 adds r1, r2, #6 + 8001e6c: 4798 blx r3 + 8001e6e: e7b9 b.n 8001de4 + 8001e70: 7c00 ldrb r0, [r0, #16] + 8001e72: 2384 movs r3, #132 ; 0x84 + 8001e74: 009b lsls r3, r3, #2 + 8001e76: 58eb ldr r3, [r5, r3] + 8001e78: 68db ldr r3, [r3, #12] + 8001e7a: 466a mov r2, sp + 8001e7c: 1d91 adds r1, r2, #6 + 8001e7e: 4798 blx r3 + 8001e80: e7b0 b.n 8001de4 + 8001e82: 7c00 ldrb r0, [r0, #16] + 8001e84: 2384 movs r3, #132 ; 0x84 + 8001e86: 009b lsls r3, r3, #2 + 8001e88: 58eb ldr r3, [r5, r3] + 8001e8a: 691b ldr r3, [r3, #16] + 8001e8c: 466a mov r2, sp + 8001e8e: 1d91 adds r1, r2, #6 + 8001e90: 4798 blx r3 + 8001e92: e7a7 b.n 8001de4 + 8001e94: 7c00 ldrb r0, [r0, #16] + 8001e96: 2384 movs r3, #132 ; 0x84 + 8001e98: 009b lsls r3, r3, #2 + 8001e9a: 58eb ldr r3, [r5, r3] + 8001e9c: 695b ldr r3, [r3, #20] + 8001e9e: 466a mov r2, sp + 8001ea0: 1d91 adds r1, r2, #6 + 8001ea2: 4798 blx r3 + 8001ea4: e79e b.n 8001de4 + 8001ea6: 7c00 ldrb r0, [r0, #16] + 8001ea8: 2384 movs r3, #132 ; 0x84 + 8001eaa: 009b lsls r3, r3, #2 + 8001eac: 58eb ldr r3, [r5, r3] + 8001eae: 699b ldr r3, [r3, #24] + 8001eb0: 466a mov r2, sp + 8001eb2: 1d91 adds r1, r2, #6 + 8001eb4: 4798 blx r3 + 8001eb6: e795 b.n 8001de4 + 8001eb8: 0021 movs r1, r4 + 8001eba: f7ff ff6a bl 8001d92 + 8001ebe: e10b b.n 80020d8 + 8001ec0: 7c03 ldrb r3, [r0, #16] + 8001ec2: 2b00 cmp r3, #0 + 8001ec4: d107 bne.n 8001ed6 + 8001ec6: 2385 movs r3, #133 ; 0x85 + 8001ec8: 009b lsls r3, r3, #2 + 8001eca: 58c3 ldr r3, [r0, r3] + 8001ecc: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001ece: 466a mov r2, sp + 8001ed0: 1d90 adds r0, r2, #6 + 8001ed2: 4798 blx r3 + 8001ed4: e786 b.n 8001de4 + 8001ed6: 0021 movs r1, r4 + 8001ed8: f7ff ff5b bl 8001d92 + 8001edc: e0fc b.n 80020d8 + 8001ede: 7c03 ldrb r3, [r0, #16] + 8001ee0: 2b00 cmp r3, #0 + 8001ee2: d109 bne.n 8001ef8 + 8001ee4: 2385 movs r3, #133 ; 0x85 + 8001ee6: 009b lsls r3, r3, #2 + 8001ee8: 58c3 ldr r3, [r0, r3] + 8001eea: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001eec: 466a mov r2, sp + 8001eee: 1d90 adds r0, r2, #6 + 8001ef0: 4798 blx r3 + 8001ef2: 2307 movs r3, #7 + 8001ef4: 7043 strb r3, [r0, #1] + 8001ef6: e775 b.n 8001de4 + 8001ef8: 0021 movs r1, r4 + 8001efa: f7ff ff4a bl 8001d92 + 8001efe: e0eb b.n 80020d8 + 8001f00: 0021 movs r1, r4 + 8001f02: 0028 movs r0, r5 + 8001f04: f7ff ff45 bl 8001d92 + 8001f08: e0e6 b.n 80020d8 + 8001f0a: 888b ldrh r3, [r1, #4] + 8001f0c: 2b00 cmp r3, #0 + 8001f0e: d122 bne.n 8001f56 + 8001f10: 88cb ldrh r3, [r1, #6] + 8001f12: 2b00 cmp r3, #0 + 8001f14: d11f bne.n 8001f56 + 8001f16: 33fd adds r3, #253 ; 0xfd + 8001f18: 33ff adds r3, #255 ; 0xff + 8001f1a: 5cc3 ldrb r3, [r0, r3] + 8001f1c: 2b03 cmp r3, #3 + 8001f1e: d012 beq.n 8001f46 + 8001f20: 884b ldrh r3, [r1, #2] + 8001f22: 247f movs r4, #127 ; 0x7f + 8001f24: 401c ands r4, r3 + 8001f26: 23ff movs r3, #255 ; 0xff + 8001f28: 005b lsls r3, r3, #1 + 8001f2a: 54c4 strb r4, [r0, r3] + 8001f2c: 0021 movs r1, r4 + 8001f2e: f000 ffdf bl 8002ef0 + 8001f32: 0028 movs r0, r5 + 8001f34: f000 f9ac bl 8002290 + 8001f38: 2c00 cmp r4, #0 + 8001f3a: d007 beq.n 8001f4c + 8001f3c: 23fe movs r3, #254 ; 0xfe + 8001f3e: 005b lsls r3, r3, #1 + 8001f40: 2202 movs r2, #2 + 8001f42: 54ea strb r2, [r5, r3] + 8001f44: e0c8 b.n 80020d8 + 8001f46: f7ff ff24 bl 8001d92 + 8001f4a: e0c5 b.n 80020d8 + 8001f4c: 23fe movs r3, #254 ; 0xfe + 8001f4e: 005b lsls r3, r3, #1 + 8001f50: 2201 movs r2, #1 + 8001f52: 54ea strb r2, [r5, r3] + 8001f54: e0c0 b.n 80020d8 + 8001f56: 0021 movs r1, r4 + 8001f58: 0028 movs r0, r5 + 8001f5a: f7ff ff1a bl 8001d92 + 8001f5e: e0bb b.n 80020d8 + 8001f60: 7889 ldrb r1, [r1, #2] + 8001f62: 4b5a ldr r3, [pc, #360] ; (80020cc ) + 8001f64: 7019 strb r1, [r3, #0] + 8001f66: 2901 cmp r1, #1 + 8001f68: d80a bhi.n 8001f80 + 8001f6a: 23fe movs r3, #254 ; 0xfe + 8001f6c: 005b lsls r3, r3, #1 + 8001f6e: 5cc3 ldrb r3, [r0, r3] + 8001f70: 2b02 cmp r3, #2 + 8001f72: d009 beq.n 8001f88 + 8001f74: 2b03 cmp r3, #3 + 8001f76: d01e beq.n 8001fb6 + 8001f78: 0021 movs r1, r4 + 8001f7a: f7ff ff0a bl 8001d92 + 8001f7e: e0ab b.n 80020d8 + 8001f80: 0021 movs r1, r4 + 8001f82: f7ff ff06 bl 8001d92 + 8001f86: e0a7 b.n 80020d8 + 8001f88: 2900 cmp r1, #0 + 8001f8a: d011 beq.n 8001fb0 + 8001f8c: 6041 str r1, [r0, #4] + 8001f8e: 23fe movs r3, #254 ; 0xfe + 8001f90: 005b lsls r3, r3, #1 + 8001f92: 2203 movs r2, #3 + 8001f94: 54c2 strb r2, [r0, r3] + 8001f96: f7ff fdb9 bl 8001b0c + 8001f9a: 2802 cmp r0, #2 + 8001f9c: d003 beq.n 8001fa6 + 8001f9e: 0028 movs r0, r5 + 8001fa0: f000 f976 bl 8002290 + 8001fa4: e098 b.n 80020d8 + 8001fa6: 0021 movs r1, r4 + 8001fa8: 0028 movs r0, r5 + 8001faa: f7ff fef2 bl 8001d92 + 8001fae: e093 b.n 80020d8 + 8001fb0: f000 f96e bl 8002290 + 8001fb4: e090 b.n 80020d8 + 8001fb6: 2900 cmp r1, #0 + 8001fb8: d011 beq.n 8001fde + 8001fba: 6843 ldr r3, [r0, #4] + 8001fbc: 4299 cmp r1, r3 + 8001fbe: d01f beq.n 8002000 + 8001fc0: b2d9 uxtb r1, r3 + 8001fc2: f7ff fdb1 bl 8001b28 + 8001fc6: 4b41 ldr r3, [pc, #260] ; (80020cc ) + 8001fc8: 7819 ldrb r1, [r3, #0] + 8001fca: 6069 str r1, [r5, #4] + 8001fcc: 0028 movs r0, r5 + 8001fce: f7ff fd9d bl 8001b0c + 8001fd2: 2802 cmp r0, #2 + 8001fd4: d00f beq.n 8001ff6 + 8001fd6: 0028 movs r0, r5 + 8001fd8: f000 f95a bl 8002290 + 8001fdc: e07c b.n 80020d8 + 8001fde: 23fe movs r3, #254 ; 0xfe + 8001fe0: 005b lsls r3, r3, #1 + 8001fe2: 2202 movs r2, #2 + 8001fe4: 54c2 strb r2, [r0, r3] + 8001fe6: 2300 movs r3, #0 + 8001fe8: 6043 str r3, [r0, #4] + 8001fea: f7ff fd9d bl 8001b28 + 8001fee: 0028 movs r0, r5 + 8001ff0: f000 f94e bl 8002290 + 8001ff4: e070 b.n 80020d8 + 8001ff6: 0021 movs r1, r4 + 8001ff8: 0028 movs r0, r5 + 8001ffa: f7ff feca bl 8001d92 + 8001ffe: e06b b.n 80020d8 + 8002000: f000 f946 bl 8002290 + 8002004: e068 b.n 80020d8 + 8002006: 88cb ldrh r3, [r1, #6] + 8002008: 2b01 cmp r3, #1 + 800200a: d109 bne.n 8002020 + 800200c: 23fe movs r3, #254 ; 0xfe + 800200e: 005b lsls r3, r3, #1 + 8002010: 5cc3 ldrb r3, [r0, r3] + 8002012: 2b02 cmp r3, #2 + 8002014: d007 beq.n 8002026 + 8002016: 2b03 cmp r3, #3 + 8002018: d00d beq.n 8002036 + 800201a: f7ff feba bl 8001d92 + 800201e: e05b b.n 80020d8 + 8002020: f7ff feb7 bl 8001d92 + 8002024: e058 b.n 80020d8 + 8002026: 2300 movs r3, #0 + 8002028: 6083 str r3, [r0, #8] + 800202a: 0001 movs r1, r0 + 800202c: 3108 adds r1, #8 + 800202e: 2201 movs r2, #1 + 8002030: f000 f900 bl 8002234 + 8002034: e050 b.n 80020d8 + 8002036: 1d01 adds r1, r0, #4 + 8002038: 2201 movs r2, #1 + 800203a: f000 f8fb bl 8002234 + 800203e: e04b b.n 80020d8 + 8002040: 23fe movs r3, #254 ; 0xfe + 8002042: 005b lsls r3, r3, #1 + 8002044: 5cc3 ldrb r3, [r0, r3] + 8002046: 3b02 subs r3, #2 + 8002048: 2b01 cmp r3, #1 + 800204a: d80f bhi.n 800206c + 800204c: 2301 movs r3, #1 + 800204e: 60c3 str r3, [r0, #12] + 8002050: 2381 movs r3, #129 ; 0x81 + 8002052: 009b lsls r3, r3, #2 + 8002054: 58c3 ldr r3, [r0, r3] + 8002056: 2b00 cmp r3, #0 + 8002058: d001 beq.n 800205e + 800205a: 2303 movs r3, #3 + 800205c: 60c3 str r3, [r0, #12] + 800205e: 0029 movs r1, r5 + 8002060: 310c adds r1, #12 + 8002062: 2202 movs r2, #2 + 8002064: 0028 movs r0, r5 + 8002066: f000 f8e5 bl 8002234 + 800206a: e035 b.n 80020d8 + 800206c: f7ff fe91 bl 8001d92 + 8002070: e032 b.n 80020d8 + 8002072: 884b ldrh r3, [r1, #2] + 8002074: 2b01 cmp r3, #1 + 8002076: d12f bne.n 80020d8 + 8002078: 2381 movs r3, #129 ; 0x81 + 800207a: 009b lsls r3, r3, #2 + 800207c: 2201 movs r2, #1 + 800207e: 50c2 str r2, [r0, r3] + 8002080: 3310 adds r3, #16 + 8002082: 58c3 ldr r3, [r0, r3] + 8002084: 689b ldr r3, [r3, #8] + 8002086: 4798 blx r3 + 8002088: 0028 movs r0, r5 + 800208a: f000 f901 bl 8002290 + 800208e: e023 b.n 80020d8 + 8002090: 23fe movs r3, #254 ; 0xfe + 8002092: 005b lsls r3, r3, #1 + 8002094: 5cc3 ldrb r3, [r0, r3] + 8002096: 3b02 subs r3, #2 + 8002098: 2b01 cmp r3, #1 + 800209a: d80e bhi.n 80020ba + 800209c: 884b ldrh r3, [r1, #2] + 800209e: 2b01 cmp r3, #1 + 80020a0: d11a bne.n 80020d8 + 80020a2: 2381 movs r3, #129 ; 0x81 + 80020a4: 009b lsls r3, r3, #2 + 80020a6: 2200 movs r2, #0 + 80020a8: 50c2 str r2, [r0, r3] + 80020aa: 3310 adds r3, #16 + 80020ac: 58c3 ldr r3, [r0, r3] + 80020ae: 689b ldr r3, [r3, #8] + 80020b0: 4798 blx r3 + 80020b2: 0028 movs r0, r5 + 80020b4: f000 f8ec bl 8002290 + 80020b8: e00e b.n 80020d8 + 80020ba: f7ff fe6a bl 8001d92 + 80020be: e00b b.n 80020d8 + 80020c0: 080030dc .word 0x080030dc + 80020c4: 08003104 .word 0x08003104 + 80020c8: 08003124 .word 0x08003124 + 80020cc: 20000191 .word 0x20000191 + 80020d0: 0021 movs r1, r4 + 80020d2: 0028 movs r0, r5 + 80020d4: f7ff fe5d bl 8001d92 + 80020d8: 2000 movs r0, #0 + 80020da: b003 add sp, #12 + 80020dc: bd30 pop {r4, r5, pc} + 80020de: 46c0 nop ; (mov r8, r8) + +080020e0 : + 80020e0: b570 push {r4, r5, r6, lr} + 80020e2: 0004 movs r4, r0 + 80020e4: 000d movs r5, r1 + 80020e6: 23fe movs r3, #254 ; 0xfe + 80020e8: 005b lsls r3, r3, #1 + 80020ea: 5cc3 ldrb r3, [r0, r3] + 80020ec: 2b03 cmp r3, #3 + 80020ee: d113 bne.n 8002118 + 80020f0: 790b ldrb r3, [r1, #4] + 80020f2: 2b01 cmp r3, #1 + 80020f4: d80d bhi.n 8002112 + 80020f6: 2385 movs r3, #133 ; 0x85 + 80020f8: 009b lsls r3, r3, #2 + 80020fa: 58c3 ldr r3, [r0, r3] + 80020fc: 689b ldr r3, [r3, #8] + 80020fe: 4798 blx r3 + 8002100: 88eb ldrh r3, [r5, #6] + 8002102: 2b00 cmp r3, #0 + 8002104: d001 beq.n 800210a + 8002106: 2000 movs r0, #0 + 8002108: bd70 pop {r4, r5, r6, pc} + 800210a: 0020 movs r0, r4 + 800210c: f000 f8c0 bl 8002290 + 8002110: e7f9 b.n 8002106 + 8002112: f7ff fe3e bl 8001d92 + 8002116: e7f6 b.n 8002106 + 8002118: f7ff fe3b bl 8001d92 + 800211c: e7f3 b.n 8002106 + +0800211e : + 800211e: b570 push {r4, r5, r6, lr} + 8002120: 0005 movs r5, r0 + 8002122: 000c movs r4, r1 + 8002124: 780a ldrb r2, [r1, #0] + 8002126: 2360 movs r3, #96 ; 0x60 + 8002128: 4013 ands r3, r2 + 800212a: 2b20 cmp r3, #32 + 800212c: d106 bne.n 800213c + 800212e: 33f5 adds r3, #245 ; 0xf5 + 8002130: 33ff adds r3, #255 ; 0xff + 8002132: 58c3 ldr r3, [r0, r3] + 8002134: 689b ldr r3, [r3, #8] + 8002136: 4798 blx r3 + 8002138: 2000 movs r0, #0 + 800213a: bd70 pop {r4, r5, r6, pc} + 800213c: 888a ldrh r2, [r1, #4] + 800213e: b2d1 uxtb r1, r2 + 8002140: 7863 ldrb r3, [r4, #1] + 8002142: 2b01 cmp r3, #1 + 8002144: d025 beq.n 8002192 + 8002146: 2b00 cmp r3, #0 + 8002148: d046 beq.n 80021d8 + 800214a: 2b03 cmp r3, #3 + 800214c: d1f4 bne.n 8002138 + 800214e: 33fa adds r3, #250 ; 0xfa + 8002150: 33ff adds r3, #255 ; 0xff + 8002152: 5cc3 ldrb r3, [r0, r3] + 8002154: 2b02 cmp r3, #2 + 8002156: d005 beq.n 8002164 + 8002158: 2b03 cmp r3, #3 + 800215a: d008 beq.n 800216e + 800215c: 0021 movs r1, r4 + 800215e: f7ff fe18 bl 8001d92 + 8002162: e7e9 b.n 8002138 + 8002164: 064b lsls r3, r1, #25 + 8002166: d0e7 beq.n 8002138 + 8002168: f000 fe96 bl 8002e98 + 800216c: e7e4 b.n 8002138 + 800216e: 8863 ldrh r3, [r4, #2] + 8002170: 2b00 cmp r3, #0 + 8002172: d103 bne.n 800217c + 8002174: 064b lsls r3, r1, #25 + 8002176: d001 beq.n 800217c + 8002178: f000 fe8e bl 8002e98 + 800217c: 2385 movs r3, #133 ; 0x85 + 800217e: 009b lsls r3, r3, #2 + 8002180: 58eb ldr r3, [r5, r3] + 8002182: 689b ldr r3, [r3, #8] + 8002184: 0021 movs r1, r4 + 8002186: 0028 movs r0, r5 + 8002188: 4798 blx r3 + 800218a: 0028 movs r0, r5 + 800218c: f000 f880 bl 8002290 + 8002190: e7d2 b.n 8002138 + 8002192: 23fe movs r3, #254 ; 0xfe + 8002194: 005b lsls r3, r3, #1 + 8002196: 5cc3 ldrb r3, [r0, r3] + 8002198: 2b02 cmp r3, #2 + 800219a: d005 beq.n 80021a8 + 800219c: 2b03 cmp r3, #3 + 800219e: d008 beq.n 80021b2 + 80021a0: 0021 movs r1, r4 + 80021a2: f7ff fdf6 bl 8001d92 + 80021a6: e7c7 b.n 8002138 + 80021a8: 064b lsls r3, r1, #25 + 80021aa: d0c5 beq.n 8002138 + 80021ac: f000 fe74 bl 8002e98 + 80021b0: e7c2 b.n 8002138 + 80021b2: 8863 ldrh r3, [r4, #2] + 80021b4: 2b00 cmp r3, #0 + 80021b6: d1bf bne.n 8002138 + 80021b8: 064b lsls r3, r1, #25 + 80021ba: d103 bne.n 80021c4 + 80021bc: 0028 movs r0, r5 + 80021be: f000 f867 bl 8002290 + 80021c2: e7b9 b.n 8002138 + 80021c4: f000 fe71 bl 8002eaa + 80021c8: 2385 movs r3, #133 ; 0x85 + 80021ca: 009b lsls r3, r3, #2 + 80021cc: 58eb ldr r3, [r5, r3] + 80021ce: 689b ldr r3, [r3, #8] + 80021d0: 0021 movs r1, r4 + 80021d2: 0028 movs r0, r5 + 80021d4: 4798 blx r3 + 80021d6: e7f1 b.n 80021bc + 80021d8: 23fe movs r3, #254 ; 0xfe + 80021da: 005b lsls r3, r3, #1 + 80021dc: 5cc3 ldrb r3, [r0, r3] + 80021de: 2b02 cmp r3, #2 + 80021e0: d005 beq.n 80021ee + 80021e2: 2b03 cmp r3, #3 + 80021e4: d008 beq.n 80021f8 + 80021e6: 0021 movs r1, r4 + 80021e8: f7ff fdd3 bl 8001d92 + 80021ec: e7a4 b.n 8002138 + 80021ee: 064b lsls r3, r1, #25 + 80021f0: d0a2 beq.n 8002138 + 80021f2: f000 fe51 bl 8002e98 + 80021f6: e79f b.n 8002138 + 80021f8: 0613 lsls r3, r2, #24 + 80021fa: d412 bmi.n 8002222 + 80021fc: 247f movs r4, #127 ; 0x7f + 80021fe: 400c ands r4, r1 + 8002200: 0124 lsls r4, r4, #4 + 8002202: 3405 adds r4, #5 + 8002204: 34ff adds r4, #255 ; 0xff + 8002206: 1904 adds r4, r0, r4 + 8002208: 0028 movs r0, r5 + 800220a: f000 fe57 bl 8002ebc + 800220e: 2800 cmp r0, #0 + 8002210: d00d beq.n 800222e + 8002212: 2301 movs r3, #1 + 8002214: 6023 str r3, [r4, #0] + 8002216: 2202 movs r2, #2 + 8002218: 0021 movs r1, r4 + 800221a: 0028 movs r0, r5 + 800221c: f000 f80a bl 8002234 + 8002220: e78a b.n 8002138 + 8002222: 247f movs r4, #127 ; 0x7f + 8002224: 400c ands r4, r1 + 8002226: 0124 lsls r4, r4, #4 + 8002228: 3414 adds r4, #20 + 800222a: 1904 adds r4, r0, r4 + 800222c: e7ec b.n 8002208 + 800222e: 2300 movs r3, #0 + 8002230: 6023 str r3, [r4, #0] + 8002232: e7f0 b.n 8002216 + +08002234 : + 8002234: b510 push {r4, lr} + 8002236: 0013 movs r3, r2 + 8002238: 22fa movs r2, #250 ; 0xfa + 800223a: 0052 lsls r2, r2, #1 + 800223c: 2402 movs r4, #2 + 800223e: 5084 str r4, [r0, r2] + 8002240: 6183 str r3, [r0, #24] + 8002242: 61c3 str r3, [r0, #28] + 8002244: 000a movs r2, r1 + 8002246: 2100 movs r1, #0 + 8002248: f000 fe5b bl 8002f02 + 800224c: 2000 movs r0, #0 + 800224e: bd10 pop {r4, pc} + +08002250 : + 8002250: b510 push {r4, lr} + 8002252: 0013 movs r3, r2 + 8002254: 000a movs r2, r1 + 8002256: 2100 movs r1, #0 + 8002258: f000 fe53 bl 8002f02 + 800225c: 2000 movs r0, #0 + 800225e: bd10 pop {r4, pc} + +08002260 : + 8002260: b510 push {r4, lr} + 8002262: 0013 movs r3, r2 + 8002264: 22fa movs r2, #250 ; 0xfa + 8002266: 0052 lsls r2, r2, #1 + 8002268: 2403 movs r4, #3 + 800226a: 5084 str r4, [r0, r2] + 800226c: 3aec subs r2, #236 ; 0xec + 800226e: 5083 str r3, [r0, r2] + 8002270: 3204 adds r2, #4 + 8002272: 5083 str r3, [r0, r2] + 8002274: 000a movs r2, r1 + 8002276: 2100 movs r1, #0 + 8002278: f000 fe4c bl 8002f14 + 800227c: 2000 movs r0, #0 + 800227e: bd10 pop {r4, pc} + +08002280 : + 8002280: b510 push {r4, lr} + 8002282: 0013 movs r3, r2 + 8002284: 000a movs r2, r1 + 8002286: 2100 movs r1, #0 + 8002288: f000 fe44 bl 8002f14 + 800228c: 2000 movs r0, #0 + 800228e: bd10 pop {r4, pc} + +08002290 : + 8002290: b510 push {r4, lr} + 8002292: 23fa movs r3, #250 ; 0xfa + 8002294: 005b lsls r3, r3, #1 + 8002296: 2204 movs r2, #4 + 8002298: 50c2 str r2, [r0, r3] + 800229a: 2300 movs r3, #0 + 800229c: 2200 movs r2, #0 + 800229e: 2100 movs r1, #0 + 80022a0: f000 fe2f bl 8002f02 + 80022a4: 2000 movs r0, #0 + 80022a6: bd10 pop {r4, pc} + +080022a8 : + 80022a8: b510 push {r4, lr} + 80022aa: 23fa movs r3, #250 ; 0xfa + 80022ac: 005b lsls r3, r3, #1 + 80022ae: 2205 movs r2, #5 + 80022b0: 50c2 str r2, [r0, r3] + 80022b2: 2300 movs r3, #0 + 80022b4: 2200 movs r2, #0 + 80022b6: 2100 movs r1, #0 + 80022b8: f000 fe2c bl 8002f14 + 80022bc: 2000 movs r0, #0 + 80022be: bd10 pop {r4, pc} + +080022c0 : + 80022c0: b570 push {r4, r5, r6, lr} + 80022c2: b088 sub sp, #32 + 80022c4: 4b1d ldr r3, [pc, #116] ; (800233c ) + 80022c6: 6959 ldr r1, [r3, #20] + 80022c8: 2080 movs r0, #128 ; 0x80 + 80022ca: 03c0 lsls r0, r0, #15 + 80022cc: 4301 orrs r1, r0 + 80022ce: 6159 str r1, [r3, #20] + 80022d0: 695a ldr r2, [r3, #20] + 80022d2: 4002 ands r2, r0 + 80022d4: 9202 str r2, [sp, #8] + 80022d6: 9a02 ldr r2, [sp, #8] + 80022d8: 695a ldr r2, [r3, #20] + 80022da: 2180 movs r1, #128 ; 0x80 + 80022dc: 0289 lsls r1, r1, #10 + 80022de: 430a orrs r2, r1 + 80022e0: 615a str r2, [r3, #20] + 80022e2: 695b ldr r3, [r3, #20] + 80022e4: 400b ands r3, r1 + 80022e6: 9301 str r3, [sp, #4] + 80022e8: 9b01 ldr r3, [sp, #4] + 80022ea: 2310 movs r3, #16 + 80022ec: 9303 str r3, [sp, #12] + 80022ee: 2500 movs r5, #0 + 80022f0: 9506 str r5, [sp, #24] + 80022f2: 9504 str r5, [sp, #16] + 80022f4: 2601 movs r6, #1 + 80022f6: 9605 str r6, [sp, #20] + 80022f8: 2490 movs r4, #144 ; 0x90 + 80022fa: 05e4 lsls r4, r4, #23 + 80022fc: a903 add r1, sp, #12 + 80022fe: 0020 movs r0, r4 + 8002300: f7fe f812 bl 8000328 + 8002304: 2340 movs r3, #64 ; 0x40 + 8002306: 9303 str r3, [sp, #12] + 8002308: 9506 str r5, [sp, #24] + 800230a: 3b3e subs r3, #62 ; 0x3e + 800230c: 9304 str r3, [sp, #16] + 800230e: 9607 str r6, [sp, #28] + 8002310: a903 add r1, sp, #12 + 8002312: 0020 movs r0, r4 + 8002314: f7fe f808 bl 8000328 + 8002318: 2180 movs r1, #128 ; 0x80 + 800231a: 2201 movs r2, #1 + 800231c: 0189 lsls r1, r1, #6 + 800231e: 0020 movs r0, r4 + 8002320: f7fe f8dc bl 80004dc + 8002324: 2320 movs r3, #32 + 8002326: 9303 str r3, [sp, #12] + 8002328: 9506 str r5, [sp, #24] + 800232a: 3b1d subs r3, #29 + 800232c: 9304 str r3, [sp, #16] + 800232e: a903 add r1, sp, #12 + 8002330: 0020 movs r0, r4 + 8002332: f7fd fff9 bl 8000328 + 8002336: b008 add sp, #32 + 8002338: bd70 pop {r4, r5, r6, pc} + 800233a: 46c0 nop ; (mov r8, r8) + 800233c: 40021000 .word 0x40021000 + +08002340 : + 8002340: b510 push {r4, lr} + 8002342: 4b4b ldr r3, [pc, #300] ; (8002470 ) + 8002344: 781b ldrb r3, [r3, #0] + 8002346: 2b00 cmp r3, #0 + 8002348: d100 bne.n 800234c + 800234a: e08b b.n 8002464 + 800234c: 4b49 ldr r3, [pc, #292] ; (8002474 ) + 800234e: 681b ldr r3, [r3, #0] + 8002350: 2b00 cmp r3, #0 + 8002352: d000 beq.n 8002356 + 8002354: e082 b.n 800245c + 8002356: 4b48 ldr r3, [pc, #288] ; (8002478 ) + 8002358: 681b ldr r3, [r3, #0] + 800235a: 2b00 cmp r3, #0 + 800235c: d127 bne.n 80023ae + 800235e: 4a47 ldr r2, [pc, #284] ; (800247c ) + 8002360: 6993 ldr r3, [r2, #24] + 8002362: 2110 movs r1, #16 + 8002364: 430b orrs r3, r1 + 8002366: 6193 str r3, [r2, #24] + 8002368: 2303 movs r3, #3 + 800236a: 4a42 ldr r2, [pc, #264] ; (8002474 ) + 800236c: 6013 str r3, [r2, #0] + 800236e: 4a44 ldr r2, [pc, #272] ; (8002480 ) + 8002370: 6812 ldr r2, [r2, #0] + 8002372: 4213 tst r3, r2 + 8002374: d10a bne.n 800238c + 8002376: 4b43 ldr r3, [pc, #268] ; (8002484 ) + 8002378: 681b ldr r3, [r3, #0] + 800237a: 4943 ldr r1, [pc, #268] ; (8002488 ) + 800237c: 680a ldr r2, [r1, #0] + 800237e: 1c50 adds r0, r2, #1 + 8002380: 6008 str r0, [r1, #0] + 8002382: 189b adds r3, r3, r2 + 8002384: 781b ldrb r3, [r3, #0] + 8002386: b2db uxtb r3, r3 + 8002388: 4a40 ldr r2, [pc, #256] ; (800248c ) + 800238a: 7013 strb r3, [r2, #0] + 800238c: 4b3f ldr r3, [pc, #252] ; (800248c ) + 800238e: 781a ldrb r2, [r3, #0] + 8002390: 2103 movs r1, #3 + 8002392: 400a ands r2, r1 + 8002394: 493e ldr r1, [pc, #248] ; (8002490 ) + 8002396: 700a strb r2, [r1, #0] + 8002398: 781a ldrb r2, [r3, #0] + 800239a: 0892 lsrs r2, r2, #2 + 800239c: 701a strb r2, [r3, #0] + 800239e: 4a38 ldr r2, [pc, #224] ; (8002480 ) + 80023a0: 6813 ldr r3, [r2, #0] + 80023a2: 3301 adds r3, #1 + 80023a4: 6013 str r3, [r2, #0] + 80023a6: 4b34 ldr r3, [pc, #208] ; (8002478 ) + 80023a8: 2201 movs r2, #1 + 80023aa: 601a str r2, [r3, #0] + 80023ac: e05a b.n 8002464 + 80023ae: 4a33 ldr r2, [pc, #204] ; (800247c ) + 80023b0: 6993 ldr r3, [r2, #24] + 80023b2: 4938 ldr r1, [pc, #224] ; (8002494 ) + 80023b4: 400b ands r3, r1 + 80023b6: 6193 str r3, [r2, #24] + 80023b8: 4b2f ldr r3, [pc, #188] ; (8002478 ) + 80023ba: 2200 movs r2, #0 + 80023bc: 601a str r2, [r3, #0] + 80023be: 4b34 ldr r3, [pc, #208] ; (8002490 ) + 80023c0: 781b ldrb r3, [r3, #0] + 80023c2: 009b lsls r3, r3, #2 + 80023c4: 4a34 ldr r2, [pc, #208] ; (8002498 ) + 80023c6: 589a ldr r2, [r3, r2] + 80023c8: 4b2a ldr r3, [pc, #168] ; (8002474 ) + 80023ca: 601a str r2, [r3, #0] + 80023cc: 4b33 ldr r3, [pc, #204] ; (800249c ) + 80023ce: 681a ldr r2, [r3, #0] + 80023d0: 4b33 ldr r3, [pc, #204] ; (80024a0 ) + 80023d2: 429a cmp r2, r3 + 80023d4: d909 bls.n 80023ea + 80023d6: 4a27 ldr r2, [pc, #156] ; (8002474 ) + 80023d8: 6813 ldr r3, [r2, #0] + 80023da: 3301 adds r3, #1 + 80023dc: 6013 str r3, [r2, #0] + 80023de: 4a2f ldr r2, [pc, #188] ; (800249c ) + 80023e0: 6813 ldr r3, [r2, #0] + 80023e2: 4930 ldr r1, [pc, #192] ; (80024a4 ) + 80023e4: 468c mov ip, r1 + 80023e6: 4463 add r3, ip + 80023e8: 6013 str r3, [r2, #0] + 80023ea: 4b29 ldr r3, [pc, #164] ; (8002490 ) + 80023ec: 781a ldrb r2, [r3, #0] + 80023ee: 492b ldr r1, [pc, #172] ; (800249c ) + 80023f0: 680b ldr r3, [r1, #0] + 80023f2: 0092 lsls r2, r2, #2 + 80023f4: 482c ldr r0, [pc, #176] ; (80024a8 ) + 80023f6: 5812 ldr r2, [r2, r0] + 80023f8: 189b adds r3, r3, r2 + 80023fa: 600b str r3, [r1, #0] + 80023fc: 4b22 ldr r3, [pc, #136] ; (8002488 ) + 80023fe: 681a ldr r2, [r3, #0] + 8002400: 4b2a ldr r3, [pc, #168] ; (80024ac ) + 8002402: 681b ldr r3, [r3, #0] + 8002404: 429a cmp r2, r3 + 8002406: d92d bls.n 8002464 + 8002408: 4b29 ldr r3, [pc, #164] ; (80024b0 ) + 800240a: 681b ldr r3, [r3, #0] + 800240c: 2b00 cmp r3, #0 + 800240e: d114 bne.n 800243a + 8002410: 4a17 ldr r2, [pc, #92] ; (8002470 ) + 8002412: 2100 movs r1, #0 + 8002414: 7011 strb r1, [r2, #0] + 8002416: 2290 movs r2, #144 ; 0x90 + 8002418: 05d2 lsls r2, r2, #23 + 800241a: 6912 ldr r2, [r2, #16] + 800241c: 06d2 lsls r2, r2, #27 + 800241e: d401 bmi.n 8002424 + 8002420: 2380 movs r3, #128 ; 0x80 + 8002422: 005b lsls r3, r3, #1 + 8002424: 4a23 ldr r2, [pc, #140] ; (80024b4 ) + 8002426: 6353 str r3, [r2, #52] ; 0x34 + 8002428: 4b23 ldr r3, [pc, #140] ; (80024b8 ) + 800242a: 681b ldr r3, [r3, #0] + 800242c: 2b00 cmp r3, #0 + 800242e: d119 bne.n 8002464 + 8002430: 2101 movs r1, #1 + 8002432: 4822 ldr r0, [pc, #136] ; (80024bc ) + 8002434: f000 fc2a bl 8002c8c + 8002438: e014 b.n 8002464 + 800243a: 4a1d ldr r2, [pc, #116] ; (80024b0 ) + 800243c: 6813 ldr r3, [r2, #0] + 800243e: 3b01 subs r3, #1 + 8002440: 6013 str r3, [r2, #0] + 8002442: 2300 movs r3, #0 + 8002444: 4a10 ldr r2, [pc, #64] ; (8002488 ) + 8002446: 6013 str r3, [r2, #0] + 8002448: 4a0d ldr r2, [pc, #52] ; (8002480 ) + 800244a: 6013 str r3, [r2, #0] + 800244c: 600b str r3, [r1, #0] + 800244e: 4b1c ldr r3, [pc, #112] ; (80024c0 ) + 8002450: 681a ldr r2, [r3, #0] + 8002452: 2332 movs r3, #50 ; 0x32 + 8002454: 4353 muls r3, r2 + 8002456: 4a07 ldr r2, [pc, #28] ; (8002474 ) + 8002458: 6013 str r3, [r2, #0] + 800245a: e003 b.n 8002464 + 800245c: 4a05 ldr r2, [pc, #20] ; (8002474 ) + 800245e: 6813 ldr r3, [r2, #0] + 8002460: 3b01 subs r3, #1 + 8002462: 6013 str r3, [r2, #0] + 8002464: 4a05 ldr r2, [pc, #20] ; (800247c ) + 8002466: 6913 ldr r3, [r2, #16] + 8002468: 4916 ldr r1, [pc, #88] ; (80024c4 ) + 800246a: 400b ands r3, r1 + 800246c: 6113 str r3, [r2, #16] + 800246e: bd10 pop {r4, pc} + 8002470: 2000029c .word 0x2000029c + 8002474: 200004d8 .word 0x200004d8 + 8002478: 200008f4 .word 0x200008f4 + 800247c: 40014400 .word 0x40014400 + 8002480: 200004e4 .word 0x200004e4 + 8002484: 200004ec .word 0x200004ec + 8002488: 200004dc .word 0x200004dc + 800248c: 200004e0 .word 0x200004e0 + 8002490: 200004d0 .word 0x200004d0 + 8002494: 0000ffef .word 0x0000ffef + 8002498: 08003164 .word 0x08003164 + 800249c: 200004e8 .word 0x200004e8 + 80024a0: 000003e7 .word 0x000003e7 + 80024a4: fffffc18 .word 0xfffffc18 + 80024a8: 08003154 .word 0x08003154 + 80024ac: 200008f0 .word 0x200008f0 + 80024b0: 200004d4 .word 0x200004d4 + 80024b4: 40000400 .word 0x40000400 + 80024b8: 200002a8 .word 0x200002a8 + 80024bc: 0800313c .word 0x0800313c + 80024c0: 200002a4 .word 0x200002a4 + 80024c4: 0000fffe .word 0x0000fffe + +080024c8 : + 80024c8: 4b04 ldr r3, [pc, #16] ; (80024dc ) + 80024ca: 2201 movs r2, #1 + 80024cc: 601a str r2, [r3, #0] + 80024ce: 4a04 ldr r2, [pc, #16] ; (80024e0 ) + 80024d0: 6913 ldr r3, [r2, #16] + 80024d2: 4904 ldr r1, [pc, #16] ; (80024e4 ) + 80024d4: 400b ands r3, r1 + 80024d6: 6113 str r3, [r2, #16] + 80024d8: 4770 bx lr + 80024da: 46c0 nop ; (mov r8, r8) + 80024dc: 200002a0 .word 0x200002a0 + 80024e0: 40002000 .word 0x40002000 + 80024e4: 0000fffe .word 0x0000fffe + +080024e8 : + 80024e8: 4b0f ldr r3, [pc, #60] ; (8002528 ) + 80024ea: 6018 str r0, [r3, #0] + 80024ec: 2300 movs r3, #0 + 80024ee: 480f ldr r0, [pc, #60] ; (800252c ) + 80024f0: 6003 str r3, [r0, #0] + 80024f2: 480f ldr r0, [pc, #60] ; (8002530 ) + 80024f4: 6001 str r1, [r0, #0] + 80024f6: 490f ldr r1, [pc, #60] ; (8002534 ) + 80024f8: 600b str r3, [r1, #0] + 80024fa: 490f ldr r1, [pc, #60] ; (8002538 ) + 80024fc: 600b str r3, [r1, #0] + 80024fe: 490f ldr r1, [pc, #60] ; (800253c ) + 8002500: 600b str r3, [r1, #0] + 8002502: 490f ldr r1, [pc, #60] ; (8002540 ) + 8002504: 600a str r2, [r1, #0] + 8002506: 4a0f ldr r2, [pc, #60] ; (8002544 ) + 8002508: 6013 str r3, [r2, #0] + 800250a: 2101 movs r1, #1 + 800250c: 4b0e ldr r3, [pc, #56] ; (8002548 ) + 800250e: 7019 strb r1, [r3, #0] + 8002510: 4b0e ldr r3, [pc, #56] ; (800254c ) + 8002512: 2280 movs r2, #128 ; 0x80 + 8002514: 01d2 lsls r2, r2, #7 + 8002516: 635a str r2, [r3, #52] ; 0x34 + 8002518: 4b0d ldr r3, [pc, #52] ; (8002550 ) + 800251a: 68da ldr r2, [r3, #12] + 800251c: 430a orrs r2, r1 + 800251e: 60da str r2, [r3, #12] + 8002520: 681a ldr r2, [r3, #0] + 8002522: 430a orrs r2, r1 + 8002524: 601a str r2, [r3, #0] + 8002526: 4770 bx lr + 8002528: 200004ec .word 0x200004ec + 800252c: 200004dc .word 0x200004dc + 8002530: 200008f0 .word 0x200008f0 + 8002534: 200004d8 .word 0x200004d8 + 8002538: 200008f4 .word 0x200008f4 + 800253c: 200004e4 .word 0x200004e4 + 8002540: 200004d4 .word 0x200004d4 + 8002544: 200004e8 .word 0x200004e8 + 8002548: 2000029c .word 0x2000029c + 800254c: 40000400 .word 0x40000400 + 8002550: 40014400 .word 0x40014400 + +08002554 : + 8002554: 4b09 ldr r3, [pc, #36] ; (800257c ) + 8002556: 2201 movs r2, #1 + 8002558: 609a str r2, [r3, #8] + 800255a: 0019 movs r1, r3 + 800255c: 680b ldr r3, [r1, #0] + 800255e: 421a tst r2, r3 + 8002560: d0fc beq.n 800255c + 8002562: 4a06 ldr r2, [pc, #24] ; (800257c ) + 8002564: 6893 ldr r3, [r2, #8] + 8002566: 2104 movs r1, #4 + 8002568: 430b orrs r3, r1 + 800256a: 6093 str r3, [r2, #8] + 800256c: 0011 movs r1, r2 + 800256e: 2204 movs r2, #4 + 8002570: 680b ldr r3, [r1, #0] + 8002572: 421a tst r2, r3 + 8002574: d0fc beq.n 8002570 + 8002576: 4b01 ldr r3, [pc, #4] ; (800257c ) + 8002578: 6c18 ldr r0, [r3, #64] ; 0x40 + 800257a: 4770 bx lr + 800257c: 40012400 .word 0x40012400 + +08002580 : + 8002580: b510 push {r4, lr} + 8002582: 4b28 ldr r3, [pc, #160] ; (8002624 ) + 8002584: 681a ldr r2, [r3, #0] + 8002586: 2101 movs r1, #1 + 8002588: 430a orrs r2, r1 + 800258a: 601a str r2, [r3, #0] + 800258c: 681b ldr r3, [r3, #0] + 800258e: 4a26 ldr r2, [pc, #152] ; (8002628 ) + 8002590: 6811 ldr r1, [r2, #0] + 8002592: 2380 movs r3, #128 ; 0x80 + 8002594: 025b lsls r3, r3, #9 + 8002596: 430b orrs r3, r1 + 8002598: 6013 str r3, [r2, #0] + 800259a: 0011 movs r1, r2 + 800259c: 2280 movs r2, #128 ; 0x80 + 800259e: 0292 lsls r2, r2, #10 + 80025a0: 680b ldr r3, [r1, #0] + 80025a2: 4213 tst r3, r2 + 80025a4: d0fc beq.n 80025a0 + 80025a6: 4b20 ldr r3, [pc, #128] ; (8002628 ) + 80025a8: 685a ldr r2, [r3, #4] + 80025aa: 4920 ldr r1, [pc, #128] ; (800262c ) + 80025ac: 4011 ands r1, r2 + 80025ae: 2288 movs r2, #136 ; 0x88 + 80025b0: 0352 lsls r2, r2, #13 + 80025b2: 430a orrs r2, r1 + 80025b4: 605a str r2, [r3, #4] + 80025b6: 6ada ldr r2, [r3, #44] ; 0x2c + 80025b8: 210f movs r1, #15 + 80025ba: 438a bics r2, r1 + 80025bc: 62da str r2, [r3, #44] ; 0x2c + 80025be: 6819 ldr r1, [r3, #0] + 80025c0: 2280 movs r2, #128 ; 0x80 + 80025c2: 0452 lsls r2, r2, #17 + 80025c4: 430a orrs r2, r1 + 80025c6: 601a str r2, [r3, #0] + 80025c8: 0019 movs r1, r3 + 80025ca: 2280 movs r2, #128 ; 0x80 + 80025cc: 0492 lsls r2, r2, #18 + 80025ce: 680b ldr r3, [r1, #0] + 80025d0: 4213 tst r3, r2 + 80025d2: d0fc beq.n 80025ce + 80025d4: 4b14 ldr r3, [pc, #80] ; (8002628 ) + 80025d6: 685a ldr r2, [r3, #4] + 80025d8: 21f0 movs r1, #240 ; 0xf0 + 80025da: 438a bics r2, r1 + 80025dc: 605a str r2, [r3, #4] + 80025de: 685a ldr r2, [r3, #4] + 80025e0: 4913 ldr r1, [pc, #76] ; (8002630 ) + 80025e2: 400a ands r2, r1 + 80025e4: 605a str r2, [r3, #4] + 80025e6: 685a ldr r2, [r3, #4] + 80025e8: 2103 movs r1, #3 + 80025ea: 438a bics r2, r1 + 80025ec: 3901 subs r1, #1 + 80025ee: 430a orrs r2, r1 + 80025f0: 605a str r2, [r3, #4] + 80025f2: 0019 movs r1, r3 + 80025f4: 220c movs r2, #12 + 80025f6: 684b ldr r3, [r1, #4] + 80025f8: 4013 ands r3, r2 + 80025fa: 2b08 cmp r3, #8 + 80025fc: d1fb bne.n 80025f6 + 80025fe: 4c0d ldr r4, [pc, #52] ; (8002634 ) + 8002600: 0020 movs r0, r4 + 8002602: f7ff f8df bl 80017c4 + 8002606: 4a0c ldr r2, [pc, #48] ; (8002638 ) + 8002608: 6813 ldr r3, [r2, #0] + 800260a: 2104 movs r1, #4 + 800260c: 430b orrs r3, r1 + 800260e: 6013 str r3, [r2, #0] + 8002610: 0020 movs r0, r4 + 8002612: f7ff f8e7 bl 80017e4 + 8002616: 4a04 ldr r2, [pc, #16] ; (8002628 ) + 8002618: 6b13 ldr r3, [r2, #48] ; 0x30 + 800261a: 2180 movs r1, #128 ; 0x80 + 800261c: 430b orrs r3, r1 + 800261e: 6313 str r3, [r2, #48] ; 0x30 + 8002620: bd10 pop {r4, pc} + 8002622: 46c0 nop ; (mov r8, r8) + 8002624: 40022000 .word 0x40022000 + 8002628: 40021000 .word 0x40021000 + 800262c: ffc27fff .word 0xffc27fff + 8002630: fffff8ff .word 0xfffff8ff + 8002634: 02dc6c00 .word 0x02dc6c00 + 8002638: e000e010 .word 0xe000e010 + +0800263c
: + 800263c: b5f0 push {r4, r5, r6, r7, lr} + 800263e: 46de mov lr, fp + 8002640: 4657 mov r7, sl + 8002642: 464e mov r6, r9 + 8002644: 4645 mov r5, r8 + 8002646: b5e0 push {r5, r6, r7, lr} + 8002648: b0cf sub sp, #316 ; 0x13c + 800264a: f7fd fdfb bl 8000244 + 800264e: f7ff ff97 bl 8002580 + 8002652: f7ff fe35 bl 80022c0 + 8002656: f000 fa9b bl 8002b90 + 800265a: 4bcb ldr r3, [pc, #812] ; (8002988 ) + 800265c: 69d9 ldr r1, [r3, #28] + 800265e: 2202 movs r2, #2 + 8002660: 4311 orrs r1, r2 + 8002662: 61d9 str r1, [r3, #28] + 8002664: 69d9 ldr r1, [r3, #28] + 8002666: 4011 ands r1, r2 + 8002668: 9108 str r1, [sp, #32] + 800266a: 9908 ldr r1, [sp, #32] + 800266c: 69d8 ldr r0, [r3, #28] + 800266e: 2480 movs r4, #128 ; 0x80 + 8002670: 0064 lsls r4, r4, #1 + 8002672: 4320 orrs r0, r4 + 8002674: 61d8 str r0, [r3, #28] + 8002676: 69d9 ldr r1, [r3, #28] + 8002678: 4021 ands r1, r4 + 800267a: 9107 str r1, [sp, #28] + 800267c: 9907 ldr r1, [sp, #28] + 800267e: 6998 ldr r0, [r3, #24] + 8002680: 3401 adds r4, #1 + 8002682: 34ff adds r4, #255 ; 0xff + 8002684: 4320 orrs r0, r4 + 8002686: 6198 str r0, [r3, #24] + 8002688: 6999 ldr r1, [r3, #24] + 800268a: 4021 ands r1, r4 + 800268c: 9106 str r1, [sp, #24] + 800268e: 9906 ldr r1, [sp, #24] + 8002690: 6998 ldr r0, [r3, #24] + 8002692: 2480 movs r4, #128 ; 0x80 + 8002694: 02a4 lsls r4, r4, #10 + 8002696: 4320 orrs r0, r4 + 8002698: 6198 str r0, [r3, #24] + 800269a: 6999 ldr r1, [r3, #24] + 800269c: 4021 ands r1, r4 + 800269e: 9105 str r1, [sp, #20] + 80026a0: 9905 ldr r1, [sp, #20] + 80026a2: 6998 ldr r0, [r3, #24] + 80026a4: 2480 movs r4, #128 ; 0x80 + 80026a6: 02e4 lsls r4, r4, #11 + 80026a8: 4320 orrs r0, r4 + 80026aa: 6198 str r0, [r3, #24] + 80026ac: 6999 ldr r1, [r3, #24] + 80026ae: 4021 ands r1, r4 + 80026b0: 9104 str r1, [sp, #16] + 80026b2: 9904 ldr r1, [sp, #16] + 80026b4: 6999 ldr r1, [r3, #24] + 80026b6: 2401 movs r4, #1 + 80026b8: 4321 orrs r1, r4 + 80026ba: 6199 str r1, [r3, #24] + 80026bc: 699b ldr r3, [r3, #24] + 80026be: 4023 ands r3, r4 + 80026c0: 9303 str r3, [sp, #12] + 80026c2: 9b03 ldr r3, [sp, #12] + 80026c4: 2380 movs r3, #128 ; 0x80 + 80026c6: 019b lsls r3, r3, #6 + 80026c8: 9309 str r3, [sp, #36] ; 0x24 + 80026ca: 2500 movs r5, #0 + 80026cc: 950c str r5, [sp, #48] ; 0x30 + 80026ce: 920a str r2, [sp, #40] ; 0x28 + 80026d0: 940d str r4, [sp, #52] ; 0x34 + 80026d2: 2090 movs r0, #144 ; 0x90 + 80026d4: a909 add r1, sp, #36 ; 0x24 + 80026d6: 05c0 lsls r0, r0, #23 + 80026d8: f7fd fe26 bl 8000328 + 80026dc: 4bab ldr r3, [pc, #684] ; (800298c ) + 80026de: 629d str r5, [r3, #40] ; 0x28 + 80026e0: 2225 movs r2, #37 ; 0x25 + 80026e2: 62da str r2, [r3, #44] ; 0x2c + 80026e4: 3a13 subs r2, #19 + 80026e6: 635a str r2, [r3, #52] ; 0x34 + 80026e8: 699a ldr r2, [r3, #24] + 80026ea: 2168 movs r1, #104 ; 0x68 + 80026ec: 430a orrs r2, r1 + 80026ee: 619a str r2, [r3, #24] + 80026f0: 6a1a ldr r2, [r3, #32] + 80026f2: 4322 orrs r2, r4 + 80026f4: 621a str r2, [r3, #32] + 80026f6: 6c5a ldr r2, [r3, #68] ; 0x44 + 80026f8: 2180 movs r1, #128 ; 0x80 + 80026fa: 0209 lsls r1, r1, #8 + 80026fc: 430a orrs r2, r1 + 80026fe: 645a str r2, [r3, #68] ; 0x44 + 8002700: 4aa3 ldr r2, [pc, #652] ; (8002990 ) + 8002702: 6295 str r5, [r2, #40] ; 0x28 + 8002704: 20e4 movs r0, #228 ; 0xe4 + 8002706: 30ff adds r0, #255 ; 0xff + 8002708: 62d0 str r0, [r2, #44] ; 0x2c + 800270a: 6990 ldr r0, [r2, #24] + 800270c: 2640 movs r6, #64 ; 0x40 + 800270e: 4330 orrs r0, r6 + 8002710: 6190 str r0, [r2, #24] + 8002712: 6a10 ldr r0, [r2, #32] + 8002714: 4320 orrs r0, r4 + 8002716: 6210 str r0, [r2, #32] + 8002718: 6c50 ldr r0, [r2, #68] ; 0x44 + 800271a: 4301 orrs r1, r0 + 800271c: 6451 str r1, [r2, #68] ; 0x44 + 800271e: 68d1 ldr r1, [r2, #12] + 8002720: 4321 orrs r1, r4 + 8002722: 60d1 str r1, [r2, #12] + 8002724: 681a ldr r2, [r3, #0] + 8002726: 4322 orrs r2, r4 + 8002728: 601a str r2, [r3, #0] + 800272a: 695a ldr r2, [r3, #20] + 800272c: 4322 orrs r2, r4 + 800272e: 615a str r2, [r3, #20] + 8002730: 4a98 ldr r2, [pc, #608] ; (8002994 ) + 8002732: 2380 movs r3, #128 ; 0x80 + 8002734: 039b lsls r3, r3, #14 + 8002736: 6013 str r3, [r2, #0] + 8002738: 21c5 movs r1, #197 ; 0xc5 + 800273a: 0089 lsls r1, r1, #2 + 800273c: 5853 ldr r3, [r2, r1] + 800273e: 4896 ldr r0, [pc, #600] ; (8002998 ) + 8002740: 4003 ands r3, r0 + 8002742: 5053 str r3, [r2, r1] + 8002744: 4b95 ldr r3, [pc, #596] ; (800299c ) + 8002746: 2164 movs r1, #100 ; 0x64 + 8002748: 6299 str r1, [r3, #40] ; 0x28 + 800274a: 4895 ldr r0, [pc, #596] ; (80029a0 ) + 800274c: 62d8 str r0, [r3, #44] ; 0x2c + 800274e: 619d str r5, [r3, #24] + 8002750: 621d str r5, [r3, #32] + 8002752: 68d9 ldr r1, [r3, #12] + 8002754: 4321 orrs r1, r4 + 8002756: 60d9 str r1, [r3, #12] + 8002758: 6819 ldr r1, [r3, #0] + 800275a: 4321 orrs r1, r4 + 800275c: 6019 str r1, [r3, #0] + 800275e: 6959 ldr r1, [r3, #20] + 8002760: 4321 orrs r1, r4 + 8002762: 6159 str r1, [r3, #20] + 8002764: 2380 movs r3, #128 ; 0x80 + 8002766: 031b lsls r3, r3, #12 + 8002768: 6013 str r3, [r2, #0] + 800276a: 26c4 movs r6, #196 ; 0xc4 + 800276c: 00b6 lsls r6, r6, #2 + 800276e: 5993 ldr r3, [r2, r6] + 8002770: 021b lsls r3, r3, #8 + 8002772: 0a1b lsrs r3, r3, #8 + 8002774: 2180 movs r1, #128 ; 0x80 + 8002776: 05c9 lsls r1, r1, #23 + 8002778: 430b orrs r3, r1 + 800277a: 5193 str r3, [r2, r6] + 800277c: 4b89 ldr r3, [pc, #548] ; (80029a4 ) + 800277e: 62d8 str r0, [r3, #44] ; 0x2c + 8002780: 2270 movs r2, #112 ; 0x70 + 8002782: 619a str r2, [r3, #24] + 8002784: 621c str r4, [r3, #32] + 8002786: 2280 movs r2, #128 ; 0x80 + 8002788: 0152 lsls r2, r2, #5 + 800278a: 635a str r2, [r3, #52] ; 0x34 + 800278c: 681a ldr r2, [r3, #0] + 800278e: 4322 orrs r2, r4 + 8002790: 601a str r2, [r3, #0] + 8002792: 695a ldr r2, [r3, #20] + 8002794: 4314 orrs r4, r2 + 8002796: 615c str r4, [r3, #20] + 8002798: 4b83 ldr r3, [pc, #524] ; (80029a8 ) + 800279a: 60dd str r5, [r3, #12] + 800279c: 2207 movs r2, #7 + 800279e: 615a str r2, [r3, #20] + 80027a0: 3219 adds r2, #25 + 80027a2: 629a str r2, [r3, #40] ; 0x28 + 80027a4: f7ff fed6 bl 8002554 + 80027a8: 4b80 ldr r3, [pc, #512] ; (80029ac ) + 80027aa: 4298 cmp r0, r3 + 80027ac: d82e bhi.n 800280c + 80027ae: 4b80 ldr r3, [pc, #512] ; (80029b0 ) + 80027b0: 881b ldrh r3, [r3, #0] + 80027b2: 4698 mov r8, r3 + 80027b4: 4b7f ldr r3, [pc, #508] ; (80029b4 ) + 80027b6: 2201 movs r2, #1 + 80027b8: 601a str r2, [r3, #0] + 80027ba: 4b7d ldr r3, [pc, #500] ; (80029b0 ) + 80027bc: 4699 mov r9, r3 + 80027be: 4e7e ldr r6, [pc, #504] ; (80029b8 ) + 80027c0: ac0e add r4, sp, #56 ; 0x38 + 80027c2: e00b b.n 80027dc + 80027c4: 4662 mov r2, ip + 80027c6: 0020 movs r0, r4 + 80027c8: f7ff fe8e bl 80024e8 + 80027cc: 4a7b ldr r2, [pc, #492] ; (80029bc ) + 80027ce: 7813 ldrb r3, [r2, #0] + 80027d0: 2b00 cmp r3, #0 + 80027d2: d1fc bne.n 80027ce + 80027d4: 3501 adds r5, #1 + 80027d6: 4545 cmp r5, r8 + 80027d8: 419b sbcs r3, r3 + 80027da: 401d ands r5, r3 + 80027dc: 00eb lsls r3, r5, #3 + 80027de: 195b adds r3, r3, r5 + 80027e0: 00db lsls r3, r3, #3 + 80027e2: 444b add r3, r9 + 80027e4: 8919 ldrh r1, [r3, #8] + 80027e6: 889a ldrh r2, [r3, #4] + 80027e8: 4694 mov ip, r2 + 80027ea: 88db ldrh r3, [r3, #6] + 80027ec: 6033 str r3, [r6, #0] + 80027ee: 2900 cmp r1, #0 + 80027f0: d0e8 beq.n 80027c4 + 80027f2: 00ea lsls r2, r5, #3 + 80027f4: 1952 adds r2, r2, r5 + 80027f6: 00d2 lsls r2, r2, #3 + 80027f8: 2300 movs r3, #0 + 80027fa: 4f6d ldr r7, [pc, #436] ; (80029b0 ) + 80027fc: 18d0 adds r0, r2, r3 + 80027fe: 19c0 adds r0, r0, r7 + 8002800: 7a80 ldrb r0, [r0, #10] + 8002802: 5518 strb r0, [r3, r4] + 8002804: 3301 adds r3, #1 + 8002806: 4299 cmp r1, r3 + 8002808: d8f8 bhi.n 80027fc + 800280a: e7db b.n 80027c4 + 800280c: 2300 movs r3, #0 + 800280e: 469a mov sl, r3 + 8002810: 469b mov fp, r3 + 8002812: 9301 str r3, [sp, #4] + 8002814: 9300 str r3, [sp, #0] + 8002816: 2600 movs r6, #0 + 8002818: 4b69 ldr r3, [pc, #420] ; (80029c0 ) + 800281a: 4699 mov r9, r3 + 800281c: 4a69 ldr r2, [pc, #420] ; (80029c4 ) + 800281e: 1a9b subs r3, r3, r2 + 8002820: 4698 mov r8, r3 + 8002822: 4b69 ldr r3, [pc, #420] ; (80029c8 ) + 8002824: 681b ldr r3, [r3, #0] + 8002826: 2b00 cmp r3, #0 + 8002828: d011 beq.n 800284e + 800282a: 4b67 ldr r3, [pc, #412] ; (80029c8 ) + 800282c: 2200 movs r2, #0 + 800282e: 601a str r2, [r3, #0] + 8002830: 4b62 ldr r3, [pc, #392] ; (80029bc ) + 8002832: 781b ldrb r3, [r3, #0] + 8002834: 2600 movs r6, #0 + 8002836: 2b00 cmp r3, #0 + 8002838: d109 bne.n 800284e + 800283a: 2390 movs r3, #144 ; 0x90 + 800283c: 05db lsls r3, r3, #23 + 800283e: 691a ldr r2, [r3, #16] + 8002840: 2310 movs r3, #16 + 8002842: 4013 ands r3, r2 + 8002844: 425a negs r2, r3 + 8002846: 4153 adcs r3, r2 + 8002848: 021b lsls r3, r3, #8 + 800284a: 4a56 ldr r2, [pc, #344] ; (80029a4 ) + 800284c: 6353 str r3, [r2, #52] ; 0x34 + 800284e: 4b5f ldr r3, [pc, #380] ; (80029cc ) + 8002850: 681a ldr r2, [r3, #0] + 8002852: 685b ldr r3, [r3, #4] + 8002854: 429a cmp r2, r3 + 8002856: d000 beq.n 800285a + 8002858: e0d3 b.n 8002a02 + 800285a: e7e2 b.n 8002822 + 800285c: 9a01 ldr r2, [sp, #4] + 800285e: 9900 ldr r1, [sp, #0] + 8002860: a80e add r0, sp, #56 ; 0x38 + 8002862: f7ff fe41 bl 80024e8 + 8002866: e0c1 b.n 80029ec + 8002868: 210c movs r1, #12 + 800286a: 4859 ldr r0, [pc, #356] ; (80029d0 ) + 800286c: f000 fa0e bl 8002c8c + 8002870: e0bc b.n 80029ec + 8002872: 4d53 ldr r5, [pc, #332] ; (80029c0 ) + 8002874: ab02 add r3, sp, #8 + 8002876: 1c9c adds r4, r3, #2 + 8002878: 4f56 ldr r7, [pc, #344] ; (80029d4 ) + 800287a: 882b ldrh r3, [r5, #0] + 800287c: 8023 strh r3, [r4, #0] + 800287e: 2102 movs r1, #2 + 8002880: 0020 movs r0, r4 + 8002882: f000 fa03 bl 8002c8c + 8002886: 2800 cmp r0, #0 + 8002888: d1f9 bne.n 800287e + 800288a: 3504 adds r5, #4 + 800288c: 42bd cmp r5, r7 + 800288e: d1f4 bne.n 800287a + 8002890: e0ac b.n 80029ec + 8002892: 2e01 cmp r6, #1 + 8002894: d100 bne.n 8002898 + 8002896: e0a7 b.n 80029e8 + 8002898: 2e02 cmp r6, #2 + 800289a: d100 bne.n 800289e + 800289c: e0d4 b.n 8002a48 + 800289e: 2e03 cmp r6, #3 + 80028a0: d100 bne.n 80028a4 + 80028a2: e0d5 b.n 8002a50 + 80028a4: 2e04 cmp r6, #4 + 80028a6: d100 bne.n 80028aa + 80028a8: e0d5 b.n 8002a56 + 80028aa: 2e05 cmp r6, #5 + 80028ac: d100 bne.n 80028b0 + 80028ae: e0da b.n 8002a66 + 80028b0: 2e06 cmp r6, #6 + 80028b2: d000 beq.n 80028b6 + 80028b4: e09a b.n 80029ec + 80028b6: 4652 mov r2, sl + 80028b8: 1c54 adds r4, r2, #1 + 80028ba: 4a42 ldr r2, [pc, #264] ; (80029c4 ) + 80028bc: 4651 mov r1, sl + 80028be: 5453 strb r3, [r2, r1] + 80028c0: 0663 lsls r3, r4, #25 + 80028c2: d100 bne.n 80028c6 + 80028c4: e0da b.n 8002a7c + 80028c6: 2380 movs r3, #128 ; 0x80 + 80028c8: 00db lsls r3, r3, #3 + 80028ca: 46a2 mov sl, r4 + 80028cc: 429c cmp r4, r3 + 80028ce: d000 beq.n 80028d2 + 80028d0: e08c b.n 80029ec + 80028d2: 4a41 ldr r2, [pc, #260] ; (80029d8 ) + 80028d4: 2301 movs r3, #1 + 80028d6: 68d1 ldr r1, [r2, #12] + 80028d8: 420b tst r3, r1 + 80028da: d1fc bne.n 80028d6 + 80028dc: 4b3e ldr r3, [pc, #248] ; (80029d8 ) + 80028de: 691b ldr r3, [r3, #16] + 80028e0: 061b lsls r3, r3, #24 + 80028e2: d504 bpl.n 80028ee + 80028e4: 4b3c ldr r3, [pc, #240] ; (80029d8 ) + 80028e6: 4a3d ldr r2, [pc, #244] ; (80029dc ) + 80028e8: 605a str r2, [r3, #4] + 80028ea: 4a3d ldr r2, [pc, #244] ; (80029e0 ) + 80028ec: 605a str r2, [r3, #4] + 80028ee: 4b3a ldr r3, [pc, #232] ; (80029d8 ) + 80028f0: 691a ldr r2, [r3, #16] + 80028f2: 2102 movs r1, #2 + 80028f4: 430a orrs r2, r1 + 80028f6: 611a str r2, [r3, #16] + 80028f8: 464a mov r2, r9 + 80028fa: 615a str r2, [r3, #20] + 80028fc: 691a ldr r2, [r3, #16] + 80028fe: 313e adds r1, #62 ; 0x3e + 8002900: 430a orrs r2, r1 + 8002902: 611a str r2, [r3, #16] + 8002904: 001a movs r2, r3 + 8002906: 2301 movs r3, #1 + 8002908: 68d1 ldr r1, [r2, #12] + 800290a: 420b tst r3, r1 + 800290c: d1fc bne.n 8002908 + 800290e: 4b32 ldr r3, [pc, #200] ; (80029d8 ) + 8002910: 68db ldr r3, [r3, #12] + 8002912: 069b lsls r3, r3, #26 + 8002914: d400 bmi.n 8002918 + 8002916: e0b6 b.n 8002a86 + 8002918: 4b2f ldr r3, [pc, #188] ; (80029d8 ) + 800291a: 2220 movs r2, #32 + 800291c: 60da str r2, [r3, #12] + 800291e: 4b2e ldr r3, [pc, #184] ; (80029d8 ) + 8002920: 691a ldr r2, [r3, #16] + 8002922: 2102 movs r1, #2 + 8002924: 438a bics r2, r1 + 8002926: 611a str r2, [r3, #16] + 8002928: 691a ldr r2, [r3, #16] + 800292a: 3901 subs r1, #1 + 800292c: 430a orrs r2, r1 + 800292e: 611a str r2, [r3, #16] + 8002930: 4b24 ldr r3, [pc, #144] ; (80029c4 ) + 8002932: 001a movs r2, r3 + 8002934: 2180 movs r1, #128 ; 0x80 + 8002936: 00c9 lsls r1, r1, #3 + 8002938: 468c mov ip, r1 + 800293a: 4462 add r2, ip + 800293c: 0010 movs r0, r2 + 800293e: 4645 mov r5, r8 + 8002940: 195a adds r2, r3, r5 + 8002942: 8819 ldrh r1, [r3, #0] + 8002944: 8011 strh r1, [r2, #0] + 8002946: 3302 adds r3, #2 + 8002948: 4283 cmp r3, r0 + 800294a: d1f9 bne.n 8002940 + 800294c: 46a8 mov r8, r5 + 800294e: 4a22 ldr r2, [pc, #136] ; (80029d8 ) + 8002950: 2301 movs r3, #1 + 8002952: 68d1 ldr r1, [r2, #12] + 8002954: 420b tst r3, r1 + 8002956: d1fc bne.n 8002952 + 8002958: 4b1f ldr r3, [pc, #124] ; (80029d8 ) + 800295a: 68db ldr r3, [r3, #12] + 800295c: 069b lsls r3, r3, #26 + 800295e: d400 bmi.n 8002962 + 8002960: e096 b.n 8002a90 + 8002962: 4b1d ldr r3, [pc, #116] ; (80029d8 ) + 8002964: 2220 movs r2, #32 + 8002966: 60da str r2, [r3, #12] + 8002968: 4a1b ldr r2, [pc, #108] ; (80029d8 ) + 800296a: 6913 ldr r3, [r2, #16] + 800296c: 2101 movs r1, #1 + 800296e: 438b bics r3, r1 + 8002970: 6113 str r3, [r2, #16] + 8002972: 481c ldr r0, [pc, #112] ; (80029e4 ) + 8002974: f000 f98a bl 8002c8c + 8002978: 4b0a ldr r3, [pc, #40] ; (80029a4 ) + 800297a: 2280 movs r2, #128 ; 0x80 + 800297c: 01d2 lsls r2, r2, #7 + 800297e: 635a str r2, [r3, #52] ; 0x34 + 8002980: 46a2 mov sl, r4 + 8002982: 2600 movs r6, #0 + 8002984: e032 b.n 80029ec + 8002986: 46c0 nop ; (mov r8, r8) + 8002988: 40021000 .word 0x40021000 + 800298c: 40014800 .word 0x40014800 + 8002990: 40014400 .word 0x40014400 + 8002994: e000e100 .word 0xe000e100 + 8002998: ffff00ff .word 0xffff00ff + 800299c: 40002000 .word 0x40002000 + 80029a0: 0000ffff .word 0x0000ffff + 80029a4: 40000400 .word 0x40000400 + 80029a8: 40012400 .word 0x40012400 + 80029ac: 00000a8b .word 0x00000a8b + 80029b0: 08007c00 .word 0x08007c00 + 80029b4: 200002a8 .word 0x200002a8 + 80029b8: 200002a4 .word 0x200002a4 + 80029bc: 2000029c .word 0x2000029c + 80029c0: 08007c00 .word 0x08007c00 + 80029c4: 200004f0 .word 0x200004f0 + 80029c8: 200002a0 .word 0x200002a0 + 80029cc: 20000194 .word 0x20000194 + 80029d0: 08003140 .word 0x08003140 + 80029d4: 08008000 .word 0x08008000 + 80029d8: 40022000 .word 0x40022000 + 80029dc: 45670123 .word 0x45670123 + 80029e0: cdef89ab .word 0xcdef89ab + 80029e4: 0800313c .word 0x0800313c + 80029e8: 9300 str r3, [sp, #0] + 80029ea: 3601 adds r6, #1 + 80029ec: 4b2e ldr r3, [pc, #184] ; (8002aa8 ) + 80029ee: 6859 ldr r1, [r3, #4] + 80029f0: 3101 adds r1, #1 + 80029f2: 22ff movs r2, #255 ; 0xff + 80029f4: 400a ands r2, r1 + 80029f6: 605a str r2, [r3, #4] + 80029f8: 681a ldr r2, [r3, #0] + 80029fa: 685b ldr r3, [r3, #4] + 80029fc: 429a cmp r2, r3 + 80029fe: d100 bne.n 8002a02 + 8002a00: e70f b.n 8002822 + 8002a02: 4b2a ldr r3, [pc, #168] ; (8002aac ) + 8002a04: 2200 movs r2, #0 + 8002a06: 625a str r2, [r3, #36] ; 0x24 + 8002a08: 4b27 ldr r3, [pc, #156] ; (8002aa8 ) + 8002a0a: 685a ldr r2, [r3, #4] + 8002a0c: 189b adds r3, r3, r2 + 8002a0e: 7a1b ldrb r3, [r3, #8] + 8002a10: b2db uxtb r3, r3 + 8002a12: 2e00 cmp r6, #0 + 8002a14: d000 beq.n 8002a18 + 8002a16: e73c b.n 8002892 + 8002a18: 2b4c cmp r3, #76 ; 0x4c + 8002a1a: d03e beq.n 8002a9a + 8002a1c: 2b54 cmp r3, #84 ; 0x54 + 8002a1e: d100 bne.n 8002a22 + 8002a20: e71c b.n 800285c + 8002a22: 2b3f cmp r3, #63 ; 0x3f + 8002a24: d100 bne.n 8002a28 + 8002a26: e71f b.n 8002868 + 8002a28: 2b57 cmp r3, #87 ; 0x57 + 8002a2a: d038 beq.n 8002a9e + 8002a2c: 2b52 cmp r3, #82 ; 0x52 + 8002a2e: d100 bne.n 8002a32 + 8002a30: e71f b.n 8002872 + 8002a32: 2b53 cmp r3, #83 ; 0x53 + 8002a34: d1da bne.n 80029ec + 8002a36: 4a1e ldr r2, [pc, #120] ; (8002ab0 ) + 8002a38: 6993 ldr r3, [r2, #24] + 8002a3a: 491e ldr r1, [pc, #120] ; (8002ab4 ) + 8002a3c: 400b ands r3, r1 + 8002a3e: 6193 str r3, [r2, #24] + 8002a40: 4b1d ldr r3, [pc, #116] ; (8002ab8 ) + 8002a42: 2200 movs r2, #0 + 8002a44: 701a strb r2, [r3, #0] + 8002a46: e7d1 b.n 80029ec + 8002a48: 4a1c ldr r2, [pc, #112] ; (8002abc ) + 8002a4a: 6013 str r3, [r2, #0] + 8002a4c: 3601 adds r6, #1 + 8002a4e: e7cd b.n 80029ec + 8002a50: 9301 str r3, [sp, #4] + 8002a52: 3601 adds r6, #1 + 8002a54: e7ca b.n 80029ec + 8002a56: 021b lsls r3, r3, #8 + 8002a58: 9a01 ldr r2, [sp, #4] + 8002a5a: 431a orrs r2, r3 + 8002a5c: 9201 str r2, [sp, #4] + 8002a5e: 2300 movs r3, #0 + 8002a60: 469b mov fp, r3 + 8002a62: 3601 adds r6, #1 + 8002a64: e7c2 b.n 80029ec + 8002a66: 465a mov r2, fp + 8002a68: 3201 adds r2, #1 + 8002a6a: a90e add r1, sp, #56 ; 0x38 + 8002a6c: 4658 mov r0, fp + 8002a6e: 540b strb r3, [r1, r0] + 8002a70: 4693 mov fp, r2 + 8002a72: 9b00 ldr r3, [sp, #0] + 8002a74: 429a cmp r2, r3 + 8002a76: d1b9 bne.n 80029ec + 8002a78: 2600 movs r6, #0 + 8002a7a: e7b7 b.n 80029ec + 8002a7c: 2101 movs r1, #1 + 8002a7e: 4810 ldr r0, [pc, #64] ; (8002ac0 ) + 8002a80: f000 f904 bl 8002c8c + 8002a84: e71f b.n 80028c6 + 8002a86: 2101 movs r1, #1 + 8002a88: 480e ldr r0, [pc, #56] ; (8002ac4 ) + 8002a8a: f000 f8ff bl 8002c8c + 8002a8e: e746 b.n 800291e + 8002a90: 2101 movs r1, #1 + 8002a92: 480c ldr r0, [pc, #48] ; (8002ac4 ) + 8002a94: f000 f8fa bl 8002c8c + 8002a98: e766 b.n 8002968 + 8002a9a: 2601 movs r6, #1 + 8002a9c: e7a6 b.n 80029ec + 8002a9e: 2300 movs r3, #0 + 8002aa0: 469a mov sl, r3 + 8002aa2: 2606 movs r6, #6 + 8002aa4: e7a2 b.n 80029ec + 8002aa6: 46c0 nop ; (mov r8, r8) + 8002aa8: 20000194 .word 0x20000194 + 8002aac: 40002000 .word 0x40002000 + 8002ab0: 40014400 .word 0x40014400 + 8002ab4: 0000ffef .word 0x0000ffef + 8002ab8: 2000029c .word 0x2000029c + 8002abc: 200002a4 .word 0x200002a4 + 8002ac0: 0800313c .word 0x0800313c + 8002ac4: 08003150 .word 0x08003150 + +08002ac8 : + 8002ac8: 4770 bx lr + ... + +08002acc : + 8002acc: b082 sub sp, #8 + 8002ace: 4b0c ldr r3, [pc, #48] ; (8002b00 ) + 8002ad0: 6999 ldr r1, [r3, #24] + 8002ad2: 2201 movs r2, #1 + 8002ad4: 4311 orrs r1, r2 + 8002ad6: 6199 str r1, [r3, #24] + 8002ad8: 6999 ldr r1, [r3, #24] + 8002ada: 400a ands r2, r1 + 8002adc: 9200 str r2, [sp, #0] + 8002ade: 9a00 ldr r2, [sp, #0] + 8002ae0: 69da ldr r2, [r3, #28] + 8002ae2: 2180 movs r1, #128 ; 0x80 + 8002ae4: 0549 lsls r1, r1, #21 + 8002ae6: 430a orrs r2, r1 + 8002ae8: 61da str r2, [r3, #28] + 8002aea: 69db ldr r3, [r3, #28] + 8002aec: 400b ands r3, r1 + 8002aee: 9301 str r3, [sp, #4] + 8002af0: 9b01 ldr r3, [sp, #4] + 8002af2: 4a04 ldr r2, [pc, #16] ; (8002b04 ) + 8002af4: 6813 ldr r3, [r2, #0] + 8002af6: 2110 movs r1, #16 + 8002af8: 430b orrs r3, r1 + 8002afa: 6013 str r3, [r2, #0] + 8002afc: b002 add sp, #8 + 8002afe: 4770 bx lr + 8002b00: 40021000 .word 0x40021000 + 8002b04: 40010000 .word 0x40010000 + +08002b08 : + 8002b08: 4770 bx lr + +08002b0a : + 8002b0a: e7fe b.n 8002b0a + +08002b0c : + 8002b0c: 4770 bx lr + +08002b0e : + 8002b0e: 4770 bx lr + +08002b10 : + 8002b10: b510 push {r4, lr} + 8002b12: f7fd fba7 bl 8000264 + 8002b16: bd10 pop {r4, pc} + +08002b18 : + 8002b18: b510 push {r4, lr} + 8002b1a: 4802 ldr r0, [pc, #8] ; (8002b24 ) + 8002b1c: f7fe fb48 bl 80011b0 + 8002b20: bd10 pop {r4, pc} + 8002b22: 46c0 nop ; (mov r8, r8) + 8002b24: 20000d1c .word 0x20000d1c + +08002b28 : + 8002b28: 4b13 ldr r3, [pc, #76] ; (8002b78 ) + 8002b2a: 681a ldr r2, [r3, #0] + 8002b2c: 2101 movs r1, #1 + 8002b2e: 430a orrs r2, r1 + 8002b30: 601a str r2, [r3, #0] + 8002b32: 685a ldr r2, [r3, #4] + 8002b34: 4811 ldr r0, [pc, #68] ; (8002b7c ) + 8002b36: 4002 ands r2, r0 + 8002b38: 605a str r2, [r3, #4] + 8002b3a: 681a ldr r2, [r3, #0] + 8002b3c: 4810 ldr r0, [pc, #64] ; (8002b80 ) + 8002b3e: 4002 ands r2, r0 + 8002b40: 601a str r2, [r3, #0] + 8002b42: 681a ldr r2, [r3, #0] + 8002b44: 480f ldr r0, [pc, #60] ; (8002b84 ) + 8002b46: 4002 ands r2, r0 + 8002b48: 601a str r2, [r3, #0] + 8002b4a: 685a ldr r2, [r3, #4] + 8002b4c: 480e ldr r0, [pc, #56] ; (8002b88 ) + 8002b4e: 4002 ands r2, r0 + 8002b50: 605a str r2, [r3, #4] + 8002b52: 6ada ldr r2, [r3, #44] ; 0x2c + 8002b54: 200f movs r0, #15 + 8002b56: 4382 bics r2, r0 + 8002b58: 62da str r2, [r3, #44] ; 0x2c + 8002b5a: 6b1a ldr r2, [r3, #48] ; 0x30 + 8002b5c: 480b ldr r0, [pc, #44] ; (8002b8c ) + 8002b5e: 4002 ands r2, r0 + 8002b60: 631a str r2, [r3, #48] ; 0x30 + 8002b62: 6b1a ldr r2, [r3, #48] ; 0x30 + 8002b64: 2080 movs r0, #128 ; 0x80 + 8002b66: 4302 orrs r2, r0 + 8002b68: 631a str r2, [r3, #48] ; 0x30 + 8002b6a: 6b5a ldr r2, [r3, #52] ; 0x34 + 8002b6c: 438a bics r2, r1 + 8002b6e: 635a str r2, [r3, #52] ; 0x34 + 8002b70: 2200 movs r2, #0 + 8002b72: 609a str r2, [r3, #8] + 8002b74: 4770 bx lr + 8002b76: 46c0 nop ; (mov r8, r8) + 8002b78: 40021000 .word 0x40021000 + 8002b7c: 08ffb80c .word 0x08ffb80c + 8002b80: fef6ffff .word 0xfef6ffff + 8002b84: fffbffff .word 0xfffbffff + 8002b88: ffc0ffff .word 0xffc0ffff + 8002b8c: fffffe6c .word 0xfffffe6c + +08002b90 : + 8002b90: b510 push {r4, lr} + 8002b92: 2200 movs r2, #0 + 8002b94: 4911 ldr r1, [pc, #68] ; (8002bdc ) + 8002b96: 4812 ldr r0, [pc, #72] ; (8002be0 ) + 8002b98: f7fe ff8e bl 8001ab8 + 8002b9c: 2800 cmp r0, #0 + 8002b9e: d111 bne.n 8002bc4 + 8002ba0: 4910 ldr r1, [pc, #64] ; (8002be4 ) + 8002ba2: 480f ldr r0, [pc, #60] ; (8002be0 ) + 8002ba4: f7fe ffa4 bl 8001af0 + 8002ba8: 2800 cmp r0, #0 + 8002baa: d10e bne.n 8002bca + 8002bac: 490e ldr r1, [pc, #56] ; (8002be8 ) + 8002bae: 480c ldr r0, [pc, #48] ; (8002be0 ) + 8002bb0: f7fe ff2a bl 8001a08 + 8002bb4: 2800 cmp r0, #0 + 8002bb6: d10b bne.n 8002bd0 + 8002bb8: 4809 ldr r0, [pc, #36] ; (8002be0 ) + 8002bba: f7fe ffa2 bl 8001b02 + 8002bbe: 2800 cmp r0, #0 + 8002bc0: d109 bne.n 8002bd6 + 8002bc2: bd10 pop {r4, pc} + 8002bc4: f7ff ff80 bl 8002ac8 + 8002bc8: e7ea b.n 8002ba0 + 8002bca: f7ff ff7d bl 8002ac8 + 8002bce: e7ed b.n 8002bac + 8002bd0: f7ff ff7a bl 8002ac8 + 8002bd4: e7f0 b.n 8002bb8 + 8002bd6: f7ff ff77 bl 8002ac8 + 8002bda: e7f2 b.n 8002bc2 + 8002bdc: 20000124 .word 0x20000124 + 8002be0: 200008f8 .word 0x200008f8 + 8002be4: 20000000 .word 0x20000000 + 8002be8: 20000114 .word 0x20000114 + +08002bec : + 8002bec: 2000 movs r0, #0 + 8002bee: 4770 bx lr + +08002bf0 : + 8002bf0: 2000 movs r0, #0 + 8002bf2: 4770 bx lr + +08002bf4 : + 8002bf4: b570 push {r4, r5, r6, lr} + 8002bf6: 0005 movs r5, r0 + 8002bf8: 680e ldr r6, [r1, #0] + 8002bfa: 4c18 ldr r4, [pc, #96] ; (8002c5c ) + 8002bfc: 0001 movs r1, r0 + 8002bfe: 0020 movs r0, r4 + 8002c00: f7fe ff16 bl 8001a30 + 8002c04: 0020 movs r0, r4 + 8002c06: f7fe ff38 bl 8001a7a + 8002c0a: 2e00 cmp r6, #0 + 8002c0c: d021 beq.n 8002c52 + 8002c0e: 4a14 ldr r2, [pc, #80] ; (8002c60 ) + 8002c10: 6813 ldr r3, [r2, #0] + 8002c12: 6852 ldr r2, [r2, #4] + 8002c14: 3301 adds r3, #1 + 8002c16: b2db uxtb r3, r3 + 8002c18: 4293 cmp r3, r2 + 8002c1a: d01c beq.n 8002c56 + 8002c1c: 002c movs r4, r5 + 8002c1e: 1e68 subs r0, r5, #1 + 8002c20: 1980 adds r0, r0, r6 + 8002c22: 4a0f ldr r2, [pc, #60] ; (8002c60 ) + 8002c24: 25ff movs r5, #255 ; 0xff + 8002c26: 0011 movs r1, r2 + 8002c28: 6813 ldr r3, [r2, #0] + 8002c2a: 7826 ldrb r6, [r4, #0] + 8002c2c: 18d3 adds r3, r2, r3 + 8002c2e: 721e strb r6, [r3, #8] + 8002c30: 6813 ldr r3, [r2, #0] + 8002c32: 3301 adds r3, #1 + 8002c34: 402b ands r3, r5 + 8002c36: 6013 str r3, [r2, #0] + 8002c38: 4284 cmp r4, r0 + 8002c3a: d008 beq.n 8002c4e + 8002c3c: 680b ldr r3, [r1, #0] + 8002c3e: 684e ldr r6, [r1, #4] + 8002c40: 3401 adds r4, #1 + 8002c42: 3301 adds r3, #1 + 8002c44: 402b ands r3, r5 + 8002c46: 42b3 cmp r3, r6 + 8002c48: d1ee bne.n 8002c28 + 8002c4a: 2002 movs r0, #2 + 8002c4c: e000 b.n 8002c50 + 8002c4e: 2000 movs r0, #0 + 8002c50: bd70 pop {r4, r5, r6, pc} + 8002c52: 2000 movs r0, #0 + 8002c54: e7fc b.n 8002c50 + 8002c56: 2002 movs r0, #2 + 8002c58: e7fa b.n 8002c50 + 8002c5a: 46c0 nop ; (mov r8, r8) + 8002c5c: 200008f8 .word 0x200008f8 + 8002c60: 20000194 .word 0x20000194 + +08002c64 : + 8002c64: b510 push {r4, lr} + 8002c66: 4c06 ldr r4, [pc, #24] ; (8002c80 ) + 8002c68: 2200 movs r2, #0 + 8002c6a: 4906 ldr r1, [pc, #24] ; (8002c84 ) + 8002c6c: 0020 movs r0, r4 + 8002c6e: f7fe fed4 bl 8001a1a + 8002c72: 4905 ldr r1, [pc, #20] ; (8002c88 ) + 8002c74: 0020 movs r0, r4 + 8002c76: f7fe fedb bl 8001a30 + 8002c7a: 2000 movs r0, #0 + 8002c7c: bd10 pop {r4, pc} + 8002c7e: 46c0 nop ; (mov r8, r8) + 8002c80: 200008f8 .word 0x200008f8 + 8002c84: 20000c1c .word 0x20000c1c + 8002c88: 20000b1c .word 0x20000b1c + +08002c8c : + 8002c8c: b570 push {r4, r5, r6, lr} + 8002c8e: 0005 movs r5, r0 + 8002c90: 4809 ldr r0, [pc, #36] ; (8002cb8 ) + 8002c92: 2386 movs r3, #134 ; 0x86 + 8002c94: 009b lsls r3, r3, #2 + 8002c96: 58c4 ldr r4, [r0, r3] + 8002c98: 3b04 subs r3, #4 + 8002c9a: 58e3 ldr r3, [r4, r3] + 8002c9c: 2001 movs r0, #1 + 8002c9e: 2b00 cmp r3, #0 + 8002ca0: d000 beq.n 8002ca4 + 8002ca2: bd70 pop {r4, r5, r6, pc} + 8002ca4: 4c04 ldr r4, [pc, #16] ; (8002cb8 ) + 8002ca6: 000a movs r2, r1 + 8002ca8: 0029 movs r1, r5 + 8002caa: 0020 movs r0, r4 + 8002cac: f7fe feb5 bl 8001a1a + 8002cb0: 0020 movs r0, r4 + 8002cb2: f7fe fec4 bl 8001a3e + 8002cb6: e7f4 b.n 8002ca2 + 8002cb8: 200008f8 .word 0x200008f8 + +08002cbc : + 8002cbc: 2800 cmp r0, #0 + 8002cbe: d004 beq.n 8002cca + 8002cc0: 3802 subs r0, #2 + 8002cc2: 1e43 subs r3, r0, #1 + 8002cc4: 4198 sbcs r0, r3 + 8002cc6: 3001 adds r0, #1 + 8002cc8: 4770 bx lr + 8002cca: 2000 movs r0, #0 + 8002ccc: e7fc b.n 8002cc8 + ... + +08002cd0 : + 8002cd0: b500 push {lr} + 8002cd2: b083 sub sp, #12 + 8002cd4: 4b0c ldr r3, [pc, #48] ; (8002d08 ) + 8002cd6: 6802 ldr r2, [r0, #0] + 8002cd8: 429a cmp r2, r3 + 8002cda: d001 beq.n 8002ce0 + 8002cdc: b003 add sp, #12 + 8002cde: bd00 pop {pc} + 8002ce0: 4a0a ldr r2, [pc, #40] ; (8002d0c ) + 8002ce2: 69d1 ldr r1, [r2, #28] + 8002ce4: 2080 movs r0, #128 ; 0x80 + 8002ce6: 0400 lsls r0, r0, #16 + 8002ce8: 4301 orrs r1, r0 + 8002cea: 61d1 str r1, [r2, #28] + 8002cec: 69d3 ldr r3, [r2, #28] + 8002cee: 4003 ands r3, r0 + 8002cf0: 9301 str r3, [sp, #4] + 8002cf2: 9b01 ldr r3, [sp, #4] + 8002cf4: 2200 movs r2, #0 + 8002cf6: 2100 movs r1, #0 + 8002cf8: 201f movs r0, #31 + 8002cfa: f7fd fabb bl 8000274 + 8002cfe: 201f movs r0, #31 + 8002d00: f7fd faec bl 80002dc + 8002d04: e7ea b.n 8002cdc + 8002d06: 46c0 nop ; (mov r8, r8) + 8002d08: 40005c00 .word 0x40005c00 + 8002d0c: 40021000 .word 0x40021000 + +08002d10 : + 8002d10: b510 push {r4, lr} + 8002d12: 0001 movs r1, r0 + 8002d14: 31ed adds r1, #237 ; 0xed + 8002d16: 31ff adds r1, #255 ; 0xff + 8002d18: 2387 movs r3, #135 ; 0x87 + 8002d1a: 009b lsls r3, r3, #2 + 8002d1c: 58c0 ldr r0, [r0, r3] + 8002d1e: f7fe ff0b bl 8001b38 + 8002d22: bd10 pop {r4, pc} + +08002d24 : + 8002d24: b510 push {r4, lr} + 8002d26: 00cb lsls r3, r1, #3 + 8002d28: 1a5b subs r3, r3, r1 + 8002d2a: 009b lsls r3, r3, #2 + 8002d2c: 18c3 adds r3, r0, r3 + 8002d2e: 3319 adds r3, #25 + 8002d30: 33ff adds r3, #255 ; 0xff + 8002d32: 681a ldr r2, [r3, #0] + 8002d34: 2387 movs r3, #135 ; 0x87 + 8002d36: 009b lsls r3, r3, #2 + 8002d38: 58c0 ldr r0, [r0, r3] + 8002d3a: f7fe ff31 bl 8001ba0 + 8002d3e: bd10 pop {r4, pc} + +08002d40 : + 8002d40: b510 push {r4, lr} + 8002d42: 00cb lsls r3, r1, #3 + 8002d44: 1a5b subs r3, r3, r1 + 8002d46: 009b lsls r3, r3, #2 + 8002d48: 18c3 adds r3, r0, r3 + 8002d4a: 6b9a ldr r2, [r3, #56] ; 0x38 + 8002d4c: 2387 movs r3, #135 ; 0x87 + 8002d4e: 009b lsls r3, r3, #2 + 8002d50: 58c0 ldr r0, [r0, r3] + 8002d52: f7fe ff61 bl 8001c18 + 8002d56: bd10 pop {r4, pc} + +08002d58 : + 8002d58: b510 push {r4, lr} + 8002d5a: 2387 movs r3, #135 ; 0x87 + 8002d5c: 009b lsls r3, r3, #2 + 8002d5e: 58c0 ldr r0, [r0, r3] + 8002d60: f7fe fff3 bl 8001d4a + 8002d64: bd10 pop {r4, pc} + +08002d66 : + 8002d66: b570 push {r4, r5, r6, lr} + 8002d68: 0004 movs r4, r0 + 8002d6a: 6883 ldr r3, [r0, #8] + 8002d6c: 2b02 cmp r3, #2 + 8002d6e: d001 beq.n 8002d74 + 8002d70: f7ff feaa bl 8002ac8 + 8002d74: 2587 movs r5, #135 ; 0x87 + 8002d76: 00ad lsls r5, r5, #2 + 8002d78: 2101 movs r1, #1 + 8002d7a: 5960 ldr r0, [r4, r5] + 8002d7c: f7fe ffd0 bl 8001d20 + 8002d80: 5960 ldr r0, [r4, r5] + 8002d82: f7fe ffaa bl 8001cda + 8002d86: bd70 pop {r4, r5, r6, pc} + +08002d88 : + 8002d88: b510 push {r4, lr} + 8002d8a: 0004 movs r4, r0 + 8002d8c: 2387 movs r3, #135 ; 0x87 + 8002d8e: 009b lsls r3, r3, #2 + 8002d90: 58c0 ldr r0, [r0, r3] + 8002d92: f7fe ffc8 bl 8001d26 + 8002d96: 69a3 ldr r3, [r4, #24] + 8002d98: 2b00 cmp r3, #0 + 8002d9a: d004 beq.n 8002da6 + 8002d9c: 4a02 ldr r2, [pc, #8] ; (8002da8 ) + 8002d9e: 6913 ldr r3, [r2, #16] + 8002da0: 2106 movs r1, #6 + 8002da2: 430b orrs r3, r1 + 8002da4: 6113 str r3, [r2, #16] + 8002da6: bd10 pop {r4, pc} + 8002da8: e000ed00 .word 0xe000ed00 + +08002dac : + 8002dac: b510 push {r4, lr} + 8002dae: 0004 movs r4, r0 + 8002db0: 6983 ldr r3, [r0, #24] + 8002db2: 2b00 cmp r3, #0 + 8002db4: d105 bne.n 8002dc2 + 8002db6: 2387 movs r3, #135 ; 0x87 + 8002db8: 009b lsls r3, r3, #2 + 8002dba: 58e0 ldr r0, [r4, r3] + 8002dbc: f7fe ffbe bl 8001d3c + 8002dc0: bd10 pop {r4, pc} + 8002dc2: 4a04 ldr r2, [pc, #16] ; (8002dd4 ) + 8002dc4: 6913 ldr r3, [r2, #16] + 8002dc6: 2106 movs r1, #6 + 8002dc8: 438b bics r3, r1 + 8002dca: 6113 str r3, [r2, #16] + 8002dcc: f7ff fbd8 bl 8002580 + 8002dd0: e7f1 b.n 8002db6 + 8002dd2: 46c0 nop ; (mov r8, r8) + 8002dd4: e000ed00 .word 0xe000ed00 + +08002dd8 : + 8002dd8: b570 push {r4, r5, r6, lr} + 8002dda: 0004 movs r4, r0 + 8002ddc: 481d ldr r0, [pc, #116] ; (8002e54 ) + 8002dde: 2387 movs r3, #135 ; 0x87 + 8002de0: 009b lsls r3, r3, #2 + 8002de2: 50c4 str r4, [r0, r3] + 8002de4: 3304 adds r3, #4 + 8002de6: 50e0 str r0, [r4, r3] + 8002de8: 4b1b ldr r3, [pc, #108] ; (8002e58 ) + 8002dea: 6003 str r3, [r0, #0] + 8002dec: 2308 movs r3, #8 + 8002dee: 6043 str r3, [r0, #4] + 8002df0: 3b06 subs r3, #6 + 8002df2: 6083 str r3, [r0, #8] + 8002df4: 6103 str r3, [r0, #16] + 8002df6: 2300 movs r3, #0 + 8002df8: 6183 str r3, [r0, #24] + 8002dfa: 61c3 str r3, [r0, #28] + 8002dfc: 6203 str r3, [r0, #32] + 8002dfe: f7fd fb73 bl 80004e8 + 8002e02: 2800 cmp r0, #0 + 8002e04: d123 bne.n 8002e4e + 8002e06: 2588 movs r5, #136 ; 0x88 + 8002e08: 00ad lsls r5, r5, #2 + 8002e0a: 2318 movs r3, #24 + 8002e0c: 2200 movs r2, #0 + 8002e0e: 2100 movs r1, #0 + 8002e10: 5960 ldr r0, [r4, r5] + 8002e12: f7fe fcb3 bl 800177c + 8002e16: 2358 movs r3, #88 ; 0x58 + 8002e18: 2200 movs r2, #0 + 8002e1a: 2180 movs r1, #128 ; 0x80 + 8002e1c: 5960 ldr r0, [r4, r5] + 8002e1e: f7fe fcad bl 800177c + 8002e22: 23c0 movs r3, #192 ; 0xc0 + 8002e24: 2200 movs r2, #0 + 8002e26: 2181 movs r1, #129 ; 0x81 + 8002e28: 5960 ldr r0, [r4, r5] + 8002e2a: f7fe fca7 bl 800177c + 8002e2e: 2388 movs r3, #136 ; 0x88 + 8002e30: 005b lsls r3, r3, #1 + 8002e32: 2200 movs r2, #0 + 8002e34: 2101 movs r1, #1 + 8002e36: 5960 ldr r0, [r4, r5] + 8002e38: f7fe fca0 bl 800177c + 8002e3c: 2380 movs r3, #128 ; 0x80 + 8002e3e: 5960 ldr r0, [r4, r5] + 8002e40: 005b lsls r3, r3, #1 + 8002e42: 2200 movs r2, #0 + 8002e44: 2182 movs r1, #130 ; 0x82 + 8002e46: f7fe fc99 bl 800177c + 8002e4a: 2000 movs r0, #0 + 8002e4c: bd70 pop {r4, r5, r6, pc} + 8002e4e: f7ff fe3b bl 8002ac8 + 8002e52: e7d8 b.n 8002e06 + 8002e54: 20000d1c .word 0x20000d1c + 8002e58: 40005c00 .word 0x40005c00 + +08002e5c : + 8002e5c: b510 push {r4, lr} + 8002e5e: 2388 movs r3, #136 ; 0x88 + 8002e60: 009b lsls r3, r3, #2 + 8002e62: 58c0 ldr r0, [r0, r3] + 8002e64: f7fd fb92 bl 800058c + 8002e68: f7ff ff28 bl 8002cbc + 8002e6c: bd10 pop {r4, pc} + +08002e6e : + 8002e6e: b510 push {r4, lr} + 8002e70: 0014 movs r4, r2 + 8002e72: 001a movs r2, r3 + 8002e74: 2388 movs r3, #136 ; 0x88 + 8002e76: 009b lsls r3, r3, #2 + 8002e78: 58c0 ldr r0, [r0, r3] + 8002e7a: 0023 movs r3, r4 + 8002e7c: f7fd fbaa bl 80005d4 + 8002e80: f7ff ff1c bl 8002cbc + 8002e84: bd10 pop {r4, pc} + +08002e86 : + 8002e86: b510 push {r4, lr} + 8002e88: 2388 movs r3, #136 ; 0x88 + 8002e8a: 009b lsls r3, r3, #2 + 8002e8c: 58c0 ldr r0, [r0, r3] + 8002e8e: f7fd fd4f bl 8000930 + 8002e92: f7ff ff13 bl 8002cbc + 8002e96: bd10 pop {r4, pc} + +08002e98 : + 8002e98: b510 push {r4, lr} + 8002e9a: 2388 movs r3, #136 ; 0x88 + 8002e9c: 009b lsls r3, r3, #2 + 8002e9e: 58c0 ldr r0, [r0, r3] + 8002ea0: f7fd ff6c bl 8000d7c + 8002ea4: f7ff ff0a bl 8002cbc + 8002ea8: bd10 pop {r4, pc} + +08002eaa : + 8002eaa: b510 push {r4, lr} + 8002eac: 2388 movs r3, #136 ; 0x88 + 8002eae: 009b lsls r3, r3, #2 + 8002eb0: 58c0 ldr r0, [r0, r3] + 8002eb2: f7fd ffcd bl 8000e50 + 8002eb6: f7ff ff01 bl 8002cbc + 8002eba: bd10 pop {r4, pc} + +08002ebc : + 8002ebc: 000a movs r2, r1 + 8002ebe: 2388 movs r3, #136 ; 0x88 + 8002ec0: 009b lsls r3, r3, #2 + 8002ec2: 58c3 ldr r3, [r0, r3] + 8002ec4: b249 sxtb r1, r1 + 8002ec6: 2900 cmp r1, #0 + 8002ec8: db09 blt.n 8002ede + 8002eca: 217f movs r1, #127 ; 0x7f + 8002ecc: 4011 ands r1, r2 + 8002ece: 00ca lsls r2, r1, #3 + 8002ed0: 1a51 subs r1, r2, r1 + 8002ed2: 0089 lsls r1, r1, #2 + 8002ed4: 185b adds r3, r3, r1 + 8002ed6: 330b adds r3, #11 + 8002ed8: 33ff adds r3, #255 ; 0xff + 8002eda: 7818 ldrb r0, [r3, #0] + 8002edc: 4770 bx lr + 8002ede: 217f movs r1, #127 ; 0x7f + 8002ee0: 4011 ands r1, r2 + 8002ee2: 00c8 lsls r0, r1, #3 + 8002ee4: 1a41 subs r1, r0, r1 + 8002ee6: 0089 lsls r1, r1, #2 + 8002ee8: 185b adds r3, r3, r1 + 8002eea: 332a adds r3, #42 ; 0x2a + 8002eec: 7818 ldrb r0, [r3, #0] + 8002eee: e7f5 b.n 8002edc + +08002ef0 : + 8002ef0: b510 push {r4, lr} + 8002ef2: 2388 movs r3, #136 ; 0x88 + 8002ef4: 009b lsls r3, r3, #2 + 8002ef6: 58c0 ldr r0, [r0, r3] + 8002ef8: f7fd fb51 bl 800059e + 8002efc: f7ff fede bl 8002cbc + 8002f00: bd10 pop {r4, pc} + +08002f02 : + 8002f02: b510 push {r4, lr} + 8002f04: 2488 movs r4, #136 ; 0x88 + 8002f06: 00a4 lsls r4, r4, #2 + 8002f08: 5900 ldr r0, [r0, r4] + 8002f0a: f7fe f827 bl 8000f5c + 8002f0e: f7ff fed5 bl 8002cbc + 8002f12: bd10 pop {r4, pc} + +08002f14 : + 8002f14: b510 push {r4, lr} + 8002f16: 2488 movs r4, #136 ; 0x88 + 8002f18: 00a4 lsls r4, r4, #2 + 8002f1a: 5900 ldr r0, [r0, r4] + 8002f1c: f7fd fdf0 bl 8000b00 + 8002f20: f7ff fecc bl 8002cbc + 8002f24: bd10 pop {r4, pc} + +08002f26 : + 8002f26: b510 push {r4, lr} + 8002f28: 2388 movs r3, #136 ; 0x88 + 8002f2a: 009b lsls r3, r3, #2 + 8002f2c: 58c0 ldr r0, [r0, r3] + 8002f2e: f7fd ff19 bl 8000d64 + 8002f32: bd10 pop {r4, pc} + +08002f34 : + 8002f34: 4800 ldr r0, [pc, #0] ; (8002f38 ) + 8002f36: 4770 bx lr + 8002f38: 200002ac .word 0x200002ac + +08002f3c : + 8002f3c: 4770 bx lr + ... + +08002f40 : + 8002f40: 2312 movs r3, #18 + 8002f42: 800b strh r3, [r1, #0] + 8002f44: 4800 ldr r0, [pc, #0] ; (8002f48 ) + 8002f46: 4770 bx lr + 8002f48: 20000140 .word 0x20000140 + +08002f4c : + 8002f4c: 2304 movs r3, #4 + 8002f4e: 800b strh r3, [r1, #0] + 8002f50: 4800 ldr r0, [pc, #0] ; (8002f54 ) + 8002f52: 4770 bx lr + 8002f54: 20000154 .word 0x20000154 + +08002f58 : + 8002f58: 2327 movs r3, #39 ; 0x27 + 8002f5a: 800b strh r3, [r1, #0] + 8002f5c: 4800 ldr r0, [pc, #0] ; (8002f60 ) + 8002f5e: 4770 bx lr + 8002f60: 080031d8 .word 0x080031d8 + +08002f64 : + 8002f64: 2329 movs r3, #41 ; 0x29 + 8002f66: 800b strh r3, [r1, #0] + 8002f68: 4800 ldr r0, [pc, #0] ; (8002f6c ) + 8002f6a: 4770 bx lr + 8002f6c: 080031ac .word 0x080031ac + +08002f70 : + 8002f70: 2317 movs r3, #23 + 8002f72: 800b strh r3, [r1, #0] + 8002f74: 4800 ldr r0, [pc, #0] ; (8002f78 ) + 8002f76: 4770 bx lr + 8002f78: 08003174 .word 0x08003174 + +08002f7c : + 8002f7c: 231d movs r3, #29 + 8002f7e: 800b strh r3, [r1, #0] + 8002f80: 4800 ldr r0, [pc, #0] ; (8002f84 ) + 8002f82: 4770 bx lr + 8002f84: 0800318c .word 0x0800318c + +08002f88 : + 8002f88: b530 push {r4, r5, lr} + 8002f8a: 0052 lsls r2, r2, #1 + 8002f8c: d010 beq.n 8002fb0 + 8002f8e: 2400 movs r4, #0 + 8002f90: 2500 movs r5, #0 + 8002f92: e007 b.n 8002fa4 + 8002f94: 3337 adds r3, #55 ; 0x37 + 8002f96: 700b strb r3, [r1, #0] + 8002f98: 704d strb r5, [r1, #1] + 8002f9a: 0100 lsls r0, r0, #4 + 8002f9c: 3402 adds r4, #2 + 8002f9e: 3102 adds r1, #2 + 8002fa0: 4294 cmp r4, r2 + 8002fa2: d205 bcs.n 8002fb0 + 8002fa4: 0f03 lsrs r3, r0, #28 + 8002fa6: 2b09 cmp r3, #9 + 8002fa8: d8f4 bhi.n 8002f94 + 8002faa: 3330 adds r3, #48 ; 0x30 + 8002fac: 700b strb r3, [r1, #0] + 8002fae: e7f3 b.n 8002f98 + 8002fb0: bd30 pop {r4, r5, pc} + ... + +08002fb4 : + 8002fb4: b570 push {r4, r5, r6, lr} + 8002fb6: 231a movs r3, #26 + 8002fb8: 800b strh r3, [r1, #0] + 8002fba: 4b0b ldr r3, [pc, #44] ; (8002fe8 ) + 8002fbc: 6818 ldr r0, [r3, #0] + 8002fbe: 4b0b ldr r3, [pc, #44] ; (8002fec ) + 8002fc0: 681b ldr r3, [r3, #0] + 8002fc2: 18c0 adds r0, r0, r3 + 8002fc4: 2800 cmp r0, #0 + 8002fc6: d101 bne.n 8002fcc + 8002fc8: 4809 ldr r0, [pc, #36] ; (8002ff0 ) + 8002fca: bd70 pop {r4, r5, r6, pc} + 8002fcc: 4b09 ldr r3, [pc, #36] ; (8002ff4 ) + 8002fce: 681d ldr r5, [r3, #0] + 8002fd0: 4c07 ldr r4, [pc, #28] ; (8002ff0 ) + 8002fd2: 1ca1 adds r1, r4, #2 + 8002fd4: 2208 movs r2, #8 + 8002fd6: f7ff ffd7 bl 8002f88 + 8002fda: 0021 movs r1, r4 + 8002fdc: 3112 adds r1, #18 + 8002fde: 2204 movs r2, #4 + 8002fe0: 0028 movs r0, r5 + 8002fe2: f7ff ffd1 bl 8002f88 + 8002fe6: e7ef b.n 8002fc8 + 8002fe8: 1ffff7ac .word 0x1ffff7ac + 8002fec: 1ffff7b4 .word 0x1ffff7b4 + 8002ff0: 20000158 .word 0x20000158 + 8002ff4: 1ffff7b0 .word 0x1ffff7b0 + +08002ff8 : + 8002ff8: 4813 ldr r0, [pc, #76] ; (8003048 ) + 8002ffa: 4685 mov sp, r0 + 8002ffc: 4813 ldr r0, [pc, #76] ; (800304c ) + 8002ffe: 6801 ldr r1, [r0, #0] + 8003000: 0e09 lsrs r1, r1, #24 + 8003002: 4a13 ldr r2, [pc, #76] ; (8003050 ) + 8003004: 4291 cmp r1, r2 + 8003006: d105 bne.n 8003014 + 8003008: 4812 ldr r0, [pc, #72] ; (8003054 ) + 800300a: 4913 ldr r1, [pc, #76] ; (8003058 ) + 800300c: 6001 str r1, [r0, #0] + 800300e: 4813 ldr r0, [pc, #76] ; (800305c ) + 8003010: 4913 ldr r1, [pc, #76] ; (8003060 ) + 8003012: 6001 str r1, [r0, #0] + +08003014 : + 8003014: 4813 ldr r0, [pc, #76] ; (8003064 ) + 8003016: 4914 ldr r1, [pc, #80] ; (8003068 ) + 8003018: 4a14 ldr r2, [pc, #80] ; (800306c ) + 800301a: 2300 movs r3, #0 + 800301c: e002 b.n 8003024 + +0800301e : + 800301e: 58d4 ldr r4, [r2, r3] + 8003020: 50c4 str r4, [r0, r3] + 8003022: 3304 adds r3, #4 + +08003024 : + 8003024: 18c4 adds r4, r0, r3 + 8003026: 428c cmp r4, r1 + 8003028: d3f9 bcc.n 800301e + 800302a: 4a11 ldr r2, [pc, #68] ; (8003070 ) + 800302c: 4c11 ldr r4, [pc, #68] ; (8003074 ) + 800302e: 2300 movs r3, #0 + 8003030: e001 b.n 8003036 + +08003032 : + 8003032: 6013 str r3, [r2, #0] + 8003034: 3204 adds r2, #4 + +08003036 : + 8003036: 42a2 cmp r2, r4 + 8003038: d3fb bcc.n 8003032 + 800303a: f7ff fd75 bl 8002b28 + 800303e: f000 f81d bl 800307c <__libc_init_array> + 8003042: f7ff fafb bl 800263c
+ +08003046 : + 8003046: e7fe b.n 8003046 + 8003048: 200017ff .word 0x200017ff + 800304c: 00000004 .word 0x00000004 + 8003050: 0000001f .word 0x0000001f + 8003054: 40021018 .word 0x40021018 + 8003058: 00000001 .word 0x00000001 + 800305c: 40010000 .word 0x40010000 + 8003060: 00000000 .word 0x00000000 + 8003064: 20000000 .word 0x20000000 + 8003068: 20000174 .word 0x20000174 + 800306c: 08003208 .word 0x08003208 + 8003070: 20000174 .word 0x20000174 + 8003074: 20000f3c .word 0x20000f3c + +08003078 : + 8003078: e7fe b.n 8003078 + ... + +0800307c <__libc_init_array>: + 800307c: b570 push {r4, r5, r6, lr} + 800307e: 2600 movs r6, #0 + 8003080: 4d0c ldr r5, [pc, #48] ; (80030b4 <__libc_init_array+0x38>) + 8003082: 4c0d ldr r4, [pc, #52] ; (80030b8 <__libc_init_array+0x3c>) + 8003084: 1b64 subs r4, r4, r5 + 8003086: 10a4 asrs r4, r4, #2 + 8003088: 42a6 cmp r6, r4 + 800308a: d109 bne.n 80030a0 <__libc_init_array+0x24> + 800308c: 2600 movs r6, #0 + 800308e: f000 f819 bl 80030c4 <_init> + 8003092: 4d0a ldr r5, [pc, #40] ; (80030bc <__libc_init_array+0x40>) + 8003094: 4c0a ldr r4, [pc, #40] ; (80030c0 <__libc_init_array+0x44>) + 8003096: 1b64 subs r4, r4, r5 + 8003098: 10a4 asrs r4, r4, #2 + 800309a: 42a6 cmp r6, r4 + 800309c: d105 bne.n 80030aa <__libc_init_array+0x2e> + 800309e: bd70 pop {r4, r5, r6, pc} + 80030a0: 00b3 lsls r3, r6, #2 + 80030a2: 58eb ldr r3, [r5, r3] + 80030a4: 4798 blx r3 + 80030a6: 3601 adds r6, #1 + 80030a8: e7ee b.n 8003088 <__libc_init_array+0xc> + 80030aa: 00b3 lsls r3, r6, #2 + 80030ac: 58eb ldr r3, [r5, r3] + 80030ae: 4798 blx r3 + 80030b0: 3601 adds r6, #1 + 80030b2: e7f2 b.n 800309a <__libc_init_array+0x1e> + 80030b4: 08003200 .word 0x08003200 + 80030b8: 08003200 .word 0x08003200 + 80030bc: 08003200 .word 0x08003200 + 80030c0: 08003204 .word 0x08003204 + +080030c4 <_init>: + 80030c4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80030c6: 46c0 nop ; (mov r8, r8) + 80030c8: bcf8 pop {r3, r4, r5, r6, r7} + 80030ca: bc08 pop {r3} + 80030cc: 469e mov lr, r3 + 80030ce: 4770 bx lr + +080030d0 <_fini>: + 80030d0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80030d2: 46c0 nop ; (mov r8, r8) + 80030d4: bcf8 pop {r3, r4, r5, r6, r7} + 80030d6: bc08 pop {r3} + 80030d8: 469e mov lr, r3 + 80030da: 4770 bx lr diff --git a/hardware/esl_blaster/FW01/Release/ESLBlaster.map b/hardware/esl_blaster/FW01/Release/ESLBlaster.map new file mode 100644 index 0000000..8c42d48 --- /dev/null +++ b/hardware/esl_blaster/FW01/Release/ESLBlaster.map @@ -0,0 +1,1472 @@ +Archive member included to satisfy reference by file (symbol) + +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (exit) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (__libc_init_array) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (memset) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o (__aeabi_uidiv) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) (__aeabi_idiv0) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_exit) + +Allocating common symbols +Common symbol size file + +hUsbDeviceFS 0x224 Src/usb_device.o +Symbol 0x1 Src/main.o +Repeats 0x4 Src/main.o +TickCounter 0x4 Src/main.o +uwTick 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o +pFlash 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o +ByteSentCounter 0x4 Src/main.o +UserRxBufferFS 0x100 Src/usbd_cdc_if.o +CurrentByte 0x1 Src/main.o +UserTxBufferFS 0x100 Src/usbd_cdc_if.o +SymbolCounter 0x4 Src/main.o +ErrorAcc 0x4 Src/main.o +FrameData 0x4 Src/main.o +flash_data_buffer 0x400 Src/main.o +ByteCount 0x4 Src/main.o +hpcd_USB_FS 0x220 Src/usbd_conf.o +Burst 0x4 Src/main.o + +Discarded input sections + + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + .data 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + .text 0x0000000000000000 0x78 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .ARM.extab 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .ARM.exidx 0x0000000000000000 0x8 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .ARM.attributes + 0x0000000000000000 0x1b d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DeInit + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetTick + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_Delay + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_SuspendTick + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_ResumeTick + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetHalVersion + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetREVID + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetDEVID + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x0000000000000000 0x1c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x0000000000000000 0x48 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Init + 0x0000000000000000 0x74 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start + 0x0000000000000000 0x6c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x0000000000000000 0x92 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort + 0x0000000000000000 0x2e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x0000000000000000 0x4a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x0000000000000000 0xca Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x0000000000000000 0xaa Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x60 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .rodata.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetState + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetError + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x0000000000000000 0x3c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x0000000000000000 0x70 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x0000000000000000 0x160 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0x5c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Program + 0x0000000000000000 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + COMMON 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_MassErase + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBErase + 0x0000000000000000 0x60 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x0000000000000000 0x184 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetUserData + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_PageErase + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x0000000000000000 0xc0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x0000000000000000 0x60 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x0000000000000000 0x11c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_ReadPin + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_TogglePin + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x0000000000000000 0x2a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x0000000000000000 0x1c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x0000000000000000 0x1e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_TransferConfig + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x0000000000000000 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x0000000000000000 0x78 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x0000000000000000 0x46 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x0000000000000000 0x8e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x0000000000000000 0x8a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x0000000000000000 0x50 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x0000000000000000 0x88 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Init + 0x0000000000000000 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x0000000000000000 0x188 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x0000000000000000 0x188 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x0000000000000000 0x1a4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x0000000000000000 0x194 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x0000000000000000 0x90 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x0000000000000000 0x90 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x0000000000000000 0x10c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x0000000000000000 0x10c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x0000000000000000 0xa8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x0000000000000000 0xac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x0000000000000000 0x1cc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x0000000000000000 0x1c4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x0000000000000000 0xe8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x0000000000000000 0xec Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x0000000000000000 0x12c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x0000000000000000 0x130 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x0000000000000000 0x174 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Sequential_Transmit_IT + 0x0000000000000000 0x84 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Sequential_Receive_IT + 0x0000000000000000 0x8c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Sequential_Transmit_IT + 0x0000000000000000 0xa0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Sequential_Receive_IT + 0x0000000000000000 0xa0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x0000000000000000 0x62 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x0000000000000000 0x12 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterSequentialCplt + 0x0000000000000000 0x52 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveSequentialCplt + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITError + 0x0000000000000000 0xf8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x0000000000000000 0x118 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x0000000000000000 0x1ec Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x0000000000000000 0x86 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x0000000000000000 0xd4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x0000000000000000 0x170 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x0000000000000000 0xdc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAError + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x0000000000000000 0x74 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAAbort + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableFastModePlus + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableFastModePlus + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_Stop + 0x0000000000000000 0x32 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DeInit + 0x0000000000000000 0x26 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DataOutStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DataInStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SetupStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SOFCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ResetCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SuspendCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ResumeCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ISOINIncompleteCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ConnectCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DisconnectCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DevConnect + 0x0000000000000000 0x2e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DevDisconnect + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_EP_Flush + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ActivateRemoteWakeup + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DeActivateRemoteWakeup + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_GetState + 0x0000000000000000 0xa Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x0000000000000000 0x3c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0x4c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_OscConfig + 0x0000000000000000 0x4a4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DisableCSS + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetSysClockFreq + 0x0000000000000000 0x80 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_ClockConfig + 0x0000000000000000 0x16c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetPCLK1Freq + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x0000000000000000 0xc0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x0000000000000000 0x38 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .rodata 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_PeriphCLKConfig + 0x0000000000000000 0x13c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x0000000000000000 0x3c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x0000000000000000 0x140 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_DeInit + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_Init + 0x0000000000000000 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_StructInit + 0x0000000000000000 0xe Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_DeInit + 0x0000000000000000 0xc4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_Init + 0x0000000000000000 0xb6 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_StructInit + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_DeInit + 0x0000000000000000 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetHCLKClockFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetPCLK1ClockFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_PLL_GetFreqDomain_SYS + 0x0000000000000000 0x4c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetUSBClockFreq + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetSystemClockFreq + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetSystemClocksFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetUSARTClockFreq + 0x0000000000000000 0x5c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetI2CClockFreq + 0x0000000000000000 0x40 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .comment 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.UTILS_SetFlashLatency + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.UTILS_EnablePLLAndSwitchSystem + 0x0000000000000000 0xac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_mDelay + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSI + 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSE + 0x0000000000000000 0xa0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_DeInit + 0x0000000000000000 0x26 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_Stop + 0x0000000000000000 0x1a Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_RunTestMode + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_IsoINIncomplete + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_IsoOUTIncomplete + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_DevConnected + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_DevDisconnected + 0x0000000000000000 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .text.USBD_GetRxCount + 0x0000000000000000 0xa Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .text 0x0000000000000000 0x0 Src/gpio.o + .data 0x0000000000000000 0x0 Src/gpio.o + .bss 0x0000000000000000 0x0 Src/gpio.o + .text 0x0000000000000000 0x0 Src/main.o + .data 0x0000000000000000 0x0 Src/main.o + .bss 0x0000000000000000 0x0 Src/main.o + .text 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .data 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .bss 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .text 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .data 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .bss 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .text 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .data 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .bss 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0x94 Src/system_stm32f0xx.o + .rodata.AHBPrescTable + 0x0000000000000000 0x10 Src/system_stm32f0xx.o + .rodata.APBPrescTable + 0x0000000000000000 0x8 Src/system_stm32f0xx.o + .text 0x0000000000000000 0x0 Src/usb_device.o + .data 0x0000000000000000 0x0 Src/usb_device.o + .bss 0x0000000000000000 0x0 Src/usb_device.o + .text 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .data 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .bss 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .text 0x0000000000000000 0x0 Src/usbd_conf.o + .data 0x0000000000000000 0x0 Src/usbd_conf.o + .bss 0x0000000000000000 0x0 Src/usbd_conf.o + .text.HAL_PCD_MspDeInit + 0x0000000000000000 0x2c Src/usbd_conf.o + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_ISOINIncompleteCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_ConnectCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_DisconnectCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.USBD_LL_DeInit + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_Stop + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_FlushEP + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_Delay + 0x0000000000000000 0x8 Src/usbd_conf.o + .text 0x0000000000000000 0x0 Src/usbd_desc.o + .data 0x0000000000000000 0x0 Src/usbd_desc.o + .bss 0x0000000000000000 0x0 Src/usbd_desc.o + .text 0x0000000000000000 0x14 Startup/startup_stm32f070f6px.o + .data 0x0000000000000000 0x0 Startup/startup_stm32f070f6px.o + .bss 0x0000000000000000 0x0 Startup/startup_stm32f070f6px.o + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .data.impure_data + 0x0000000000000000 0x60 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .rodata._global_impure_ptr + 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .text.memset 0x0000000000000000 0x10 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000000000 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .text._exit 0x0000000000000000 0x2 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .debug_frame 0x0000000000000000 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o + .eh_frame 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + +Memory Configuration + +Name Origin Length Attributes +FLASH 0x0000000008000000 0x0000000000008000 xr +FLASH_USER 0x0000000008007c00 0x0000000000000400 rw +RAM 0x0000000020000000 0x0000000000001800 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o +LOAD Src/gpio.o +LOAD Src/main.o +LOAD Src/stm32f0xx_hal_msp.o +LOAD Src/stm32f0xx_it.o +LOAD Src/system_stm32f0xx.o +LOAD Src/usb_device.o +LOAD Src/usbd_cdc_if.o +LOAD Src/usbd_conf.o +LOAD Src/usbd_desc.o +LOAD Startup/startup_stm32f070f6px.o +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a +END GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + 0x00000000200017ff _estack = 0x200017ff + 0x0000000000000180 _Min_Heap_Size = 0x180 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xc0 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xc0 Startup/startup_stm32f070f6px.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000c0 . = ALIGN (0x4) + +.text 0x00000000080000c0 0x301c + 0x00000000080000c0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080000c0 0x48 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + .text 0x0000000008000108 0x114 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) + 0x0000000008000108 __aeabi_uidiv + 0x0000000008000108 __udivsi3 + 0x0000000008000214 __aeabi_uidivmod + .text 0x000000000800021c 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o) + 0x000000000800021c __aeabi_idiv0 + 0x000000000800021c __aeabi_ldiv0 + *(.text*) + .text.HAL_InitTick + 0x0000000008000220 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000220 HAL_InitTick + .text.HAL_Init + 0x0000000008000244 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000244 HAL_Init + .text.HAL_IncTick + 0x0000000008000264 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000264 HAL_IncTick + .text.HAL_NVIC_SetPriority + 0x0000000008000274 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x0000000008000274 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x00000000080002dc 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x00000000080002dc HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x00000000080002f0 0x38 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x00000000080002f0 HAL_SYSTICK_Config + .text.HAL_GPIO_Init + 0x0000000008000328 0x1b4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x0000000008000328 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x00000000080004dc 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x00000000080004dc HAL_GPIO_WritePin + .text.HAL_PCD_Init + 0x00000000080004e8 0xa4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080004e8 HAL_PCD_Init + .text.HAL_PCD_Start + 0x000000000800058c 0x12 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x000000000800058c HAL_PCD_Start + .text.HAL_PCD_SetAddress + 0x000000000800059e 0x36 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x000000000800059e HAL_PCD_SetAddress + .text.HAL_PCD_EP_Open + 0x00000000080005d4 0x35c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080005d4 HAL_PCD_EP_Open + .text.HAL_PCD_EP_Close + 0x0000000008000930 0x1d0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000930 HAL_PCD_EP_Close + .text.HAL_PCD_EP_Receive + 0x0000000008000b00 0x264 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000b00 HAL_PCD_EP_Receive + .text.HAL_PCD_EP_GetRxCount + 0x0000000008000d64 0x16 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000d64 HAL_PCD_EP_GetRxCount + *fill* 0x0000000008000d7a 0x2 + .text.HAL_PCD_EP_SetStall + 0x0000000008000d7c 0xd4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000d7c HAL_PCD_EP_SetStall + .text.HAL_PCD_EP_ClrStall + 0x0000000008000e50 0xe0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000e50 HAL_PCD_EP_ClrStall + .text.PCD_WritePMA + 0x0000000008000f30 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000f30 PCD_WritePMA + .text.HAL_PCD_EP_Transmit + 0x0000000008000f5c 0x218 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000f5c HAL_PCD_EP_Transmit + .text.PCD_ReadPMA + 0x0000000008001174 0x3a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008001174 PCD_ReadPMA + *fill* 0x00000000080011ae 0x2 + .text.HAL_PCD_IRQHandler + 0x00000000080011b0 0x5cc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080011b0 HAL_PCD_IRQHandler + .text.HAL_PCDEx_PMAConfig + 0x000000000800177c 0x3a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + 0x000000000800177c HAL_PCDEx_PMAConfig + *fill* 0x00000000080017b6 0x2 + .text.HAL_RCC_GetHCLKFreq + 0x00000000080017b8 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x00000000080017b8 HAL_RCC_GetHCLKFreq + .text.LL_Init1msTick + 0x00000000080017c4 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + 0x00000000080017c4 LL_Init1msTick + .text.LL_SetSystemCoreClock + 0x00000000080017e4 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + 0x00000000080017e4 LL_SetSystemCoreClock + .text.USBD_CDC_DataIn + 0x00000000080017f0 0x1a Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x000000000800180a 0x2 + .text.USBD_CDC_EP0_RxReady + 0x000000000800180c 0x34 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetFSCfgDesc + 0x0000000008001840 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetHSCfgDesc + 0x000000000800184c 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetOtherSpeedCfgDesc + 0x0000000008001858 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetDeviceQualifierDescriptor + 0x0000000008001864 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001864 USBD_CDC_GetDeviceQualifierDescriptor + .text.USBD_CDC_DataOut + 0x0000000008001870 0x34 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_Setup + 0x00000000080018a4 0x80 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_DeInit + 0x0000000008001924 0x40 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_Init + 0x0000000008001964 0xa4 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_RegisterInterface + 0x0000000008001a08 0x12 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a08 USBD_CDC_RegisterInterface + .text.USBD_CDC_SetTxBuffer + 0x0000000008001a1a 0x16 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a1a USBD_CDC_SetTxBuffer + .text.USBD_CDC_SetRxBuffer + 0x0000000008001a30 0xe Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a30 USBD_CDC_SetRxBuffer + .text.USBD_CDC_TransmitPacket + 0x0000000008001a3e 0x3c Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a3e USBD_CDC_TransmitPacket + .text.USBD_CDC_ReceivePacket + 0x0000000008001a7a 0x3e Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a7a USBD_CDC_ReceivePacket + .text.USBD_Init + 0x0000000008001ab8 0x38 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001ab8 USBD_Init + .text.USBD_RegisterClass + 0x0000000008001af0 0x12 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001af0 USBD_RegisterClass + .text.USBD_Start + 0x0000000008001b02 0xa Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001b02 USBD_Start + .text.USBD_SetClassConfig + 0x0000000008001b0c 0x1c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001b0c USBD_SetClassConfig + .text.USBD_ClrClassConfig + 0x0000000008001b28 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001b28 USBD_ClrClassConfig + .text.USBD_LL_SetupStage + 0x0000000008001b38 0x68 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001b38 USBD_LL_SetupStage + .text.USBD_LL_DataOutStage + 0x0000000008001ba0 0x78 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001ba0 USBD_LL_DataOutStage + .text.USBD_LL_DataInStage + 0x0000000008001c18 0xc2 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001c18 USBD_LL_DataInStage + .text.USBD_LL_Reset + 0x0000000008001cda 0x46 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001cda USBD_LL_Reset + .text.USBD_LL_SetSpeed + 0x0000000008001d20 0x6 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001d20 USBD_LL_SetSpeed + .text.USBD_LL_Suspend + 0x0000000008001d26 0x16 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001d26 USBD_LL_Suspend + .text.USBD_LL_Resume + 0x0000000008001d3c 0xe Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001d3c USBD_LL_Resume + .text.USBD_LL_SOF + 0x0000000008001d4a 0x20 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001d4a USBD_LL_SOF + .text.USBD_ParseSetupRequest + 0x0000000008001d6a 0x28 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001d6a USBD_ParseSetupRequest + .text.USBD_CtlError + 0x0000000008001d92 0x14 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001d92 USBD_CtlError + *fill* 0x0000000008001da6 0x2 + .text.USBD_StdDevReq + 0x0000000008001da8 0x338 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001da8 USBD_StdDevReq + .text.USBD_StdItfReq + 0x00000000080020e0 0x3e Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x00000000080020e0 USBD_StdItfReq + .text.USBD_StdEPReq + 0x000000000800211e 0x116 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x000000000800211e USBD_StdEPReq + .text.USBD_CtlSendData + 0x0000000008002234 0x1c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002234 USBD_CtlSendData + .text.USBD_CtlContinueSendData + 0x0000000008002250 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002250 USBD_CtlContinueSendData + .text.USBD_CtlPrepareRx + 0x0000000008002260 0x20 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002260 USBD_CtlPrepareRx + .text.USBD_CtlContinueRx + 0x0000000008002280 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002280 USBD_CtlContinueRx + .text.USBD_CtlSendStatus + 0x0000000008002290 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002290 USBD_CtlSendStatus + .text.USBD_CtlReceiveStatus + 0x00000000080022a8 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x00000000080022a8 USBD_CtlReceiveStatus + .text.MX_GPIO_Init + 0x00000000080022c0 0x80 Src/gpio.o + 0x00000000080022c0 MX_GPIO_Init + .text.TIM16_IRQHandler + 0x0000000008002340 0x188 Src/main.o + 0x0000000008002340 TIM16_IRQHandler + .text.TIM14_IRQHandler + 0x00000000080024c8 0x20 Src/main.o + 0x00000000080024c8 TIM14_IRQHandler + .text.IRTX 0x00000000080024e8 0x6c Src/main.o + 0x00000000080024e8 IRTX + .text.adc_read + 0x0000000008002554 0x2c Src/main.o + 0x0000000008002554 adc_read + .text.SystemClock_Config + 0x0000000008002580 0xbc Src/main.o + 0x0000000008002580 SystemClock_Config + .text.main 0x000000000800263c 0x48c Src/main.o + 0x000000000800263c main + .text.Error_Handler + 0x0000000008002ac8 0x2 Src/main.o + 0x0000000008002ac8 Error_Handler + *fill* 0x0000000008002aca 0x2 + .text.HAL_MspInit + 0x0000000008002acc 0x3c Src/stm32f0xx_hal_msp.o + 0x0000000008002acc HAL_MspInit + .text.NMI_Handler + 0x0000000008002b08 0x2 Src/stm32f0xx_it.o + 0x0000000008002b08 NMI_Handler + .text.HardFault_Handler + 0x0000000008002b0a 0x2 Src/stm32f0xx_it.o + 0x0000000008002b0a HardFault_Handler + .text.SVC_Handler + 0x0000000008002b0c 0x2 Src/stm32f0xx_it.o + 0x0000000008002b0c SVC_Handler + .text.PendSV_Handler + 0x0000000008002b0e 0x2 Src/stm32f0xx_it.o + 0x0000000008002b0e PendSV_Handler + .text.SysTick_Handler + 0x0000000008002b10 0x8 Src/stm32f0xx_it.o + 0x0000000008002b10 SysTick_Handler + .text.USB_IRQHandler + 0x0000000008002b18 0x10 Src/stm32f0xx_it.o + 0x0000000008002b18 USB_IRQHandler + .text.SystemInit + 0x0000000008002b28 0x68 Src/system_stm32f0xx.o + 0x0000000008002b28 SystemInit + .text.MX_USB_DEVICE_Init + 0x0000000008002b90 0x5c Src/usb_device.o + 0x0000000008002b90 MX_USB_DEVICE_Init + .text.CDC_DeInit_FS + 0x0000000008002bec 0x4 Src/usbd_cdc_if.o + .text.CDC_Control_FS + 0x0000000008002bf0 0x4 Src/usbd_cdc_if.o + .text.CDC_Receive_FS + 0x0000000008002bf4 0x70 Src/usbd_cdc_if.o + .text.CDC_Init_FS + 0x0000000008002c64 0x28 Src/usbd_cdc_if.o + .text.CDC_Transmit_FS + 0x0000000008002c8c 0x30 Src/usbd_cdc_if.o + 0x0000000008002c8c CDC_Transmit_FS + .text.USBD_Get_USB_Status + 0x0000000008002cbc 0x12 Src/usbd_conf.o + *fill* 0x0000000008002cce 0x2 + .text.HAL_PCD_MspInit + 0x0000000008002cd0 0x40 Src/usbd_conf.o + 0x0000000008002cd0 HAL_PCD_MspInit + .text.HAL_PCD_SetupStageCallback + 0x0000000008002d10 0x14 Src/usbd_conf.o + 0x0000000008002d10 HAL_PCD_SetupStageCallback + .text.HAL_PCD_DataOutStageCallback + 0x0000000008002d24 0x1c Src/usbd_conf.o + 0x0000000008002d24 HAL_PCD_DataOutStageCallback + .text.HAL_PCD_DataInStageCallback + 0x0000000008002d40 0x18 Src/usbd_conf.o + 0x0000000008002d40 HAL_PCD_DataInStageCallback + .text.HAL_PCD_SOFCallback + 0x0000000008002d58 0xe Src/usbd_conf.o + 0x0000000008002d58 HAL_PCD_SOFCallback + .text.HAL_PCD_ResetCallback + 0x0000000008002d66 0x22 Src/usbd_conf.o + 0x0000000008002d66 HAL_PCD_ResetCallback + .text.HAL_PCD_SuspendCallback + 0x0000000008002d88 0x24 Src/usbd_conf.o + 0x0000000008002d88 HAL_PCD_SuspendCallback + .text.HAL_PCD_ResumeCallback + 0x0000000008002dac 0x2c Src/usbd_conf.o + 0x0000000008002dac HAL_PCD_ResumeCallback + .text.USBD_LL_Init + 0x0000000008002dd8 0x84 Src/usbd_conf.o + 0x0000000008002dd8 USBD_LL_Init + .text.USBD_LL_Start + 0x0000000008002e5c 0x12 Src/usbd_conf.o + 0x0000000008002e5c USBD_LL_Start + .text.USBD_LL_OpenEP + 0x0000000008002e6e 0x18 Src/usbd_conf.o + 0x0000000008002e6e USBD_LL_OpenEP + .text.USBD_LL_CloseEP + 0x0000000008002e86 0x12 Src/usbd_conf.o + 0x0000000008002e86 USBD_LL_CloseEP + .text.USBD_LL_StallEP + 0x0000000008002e98 0x12 Src/usbd_conf.o + 0x0000000008002e98 USBD_LL_StallEP + .text.USBD_LL_ClearStallEP + 0x0000000008002eaa 0x12 Src/usbd_conf.o + 0x0000000008002eaa USBD_LL_ClearStallEP + .text.USBD_LL_IsStallEP + 0x0000000008002ebc 0x34 Src/usbd_conf.o + 0x0000000008002ebc USBD_LL_IsStallEP + .text.USBD_LL_SetUSBAddress + 0x0000000008002ef0 0x12 Src/usbd_conf.o + 0x0000000008002ef0 USBD_LL_SetUSBAddress + .text.USBD_LL_Transmit + 0x0000000008002f02 0x12 Src/usbd_conf.o + 0x0000000008002f02 USBD_LL_Transmit + .text.USBD_LL_PrepareReceive + 0x0000000008002f14 0x12 Src/usbd_conf.o + 0x0000000008002f14 USBD_LL_PrepareReceive + .text.USBD_LL_GetRxDataSize + 0x0000000008002f26 0xe Src/usbd_conf.o + 0x0000000008002f26 USBD_LL_GetRxDataSize + .text.USBD_static_malloc + 0x0000000008002f34 0x8 Src/usbd_conf.o + 0x0000000008002f34 USBD_static_malloc + .text.USBD_static_free + 0x0000000008002f3c 0x2 Src/usbd_conf.o + 0x0000000008002f3c USBD_static_free + *fill* 0x0000000008002f3e 0x2 + .text.USBD_FS_DeviceDescriptor + 0x0000000008002f40 0xc Src/usbd_desc.o + 0x0000000008002f40 USBD_FS_DeviceDescriptor + .text.USBD_FS_LangIDStrDescriptor + 0x0000000008002f4c 0xc Src/usbd_desc.o + 0x0000000008002f4c USBD_FS_LangIDStrDescriptor + .text.USBD_FS_ProductStrDescriptor + 0x0000000008002f58 0xc Src/usbd_desc.o + 0x0000000008002f58 USBD_FS_ProductStrDescriptor + .text.USBD_FS_ManufacturerStrDescriptor + 0x0000000008002f64 0xc Src/usbd_desc.o + 0x0000000008002f64 USBD_FS_ManufacturerStrDescriptor + .text.USBD_FS_ConfigStrDescriptor + 0x0000000008002f70 0xc Src/usbd_desc.o + 0x0000000008002f70 USBD_FS_ConfigStrDescriptor + .text.USBD_FS_InterfaceStrDescriptor + 0x0000000008002f7c 0xc Src/usbd_desc.o + 0x0000000008002f7c USBD_FS_InterfaceStrDescriptor + .text.IntToUnicode + 0x0000000008002f88 0x2a Src/usbd_desc.o + *fill* 0x0000000008002fb2 0x2 + .text.USBD_FS_SerialStrDescriptor + 0x0000000008002fb4 0x44 Src/usbd_desc.o + 0x0000000008002fb4 USBD_FS_SerialStrDescriptor + .text.Reset_Handler + 0x0000000008002ff8 0x80 Startup/startup_stm32f070f6px.o + 0x0000000008002ff8 Reset_Handler + .text.Default_Handler + 0x0000000008003078 0x2 Startup/startup_stm32f070f6px.o + 0x0000000008003078 TIM1_CC_IRQHandler + 0x0000000008003078 I2C1_IRQHandler + 0x0000000008003078 SPI1_IRQHandler + 0x0000000008003078 EXTI2_3_IRQHandler + 0x0000000008003078 ADC1_IRQHandler + 0x0000000008003078 TIM17_IRQHandler + 0x0000000008003078 RTC_IRQHandler + 0x0000000008003078 TIM3_IRQHandler + 0x0000000008003078 EXTI4_15_IRQHandler + 0x0000000008003078 RCC_IRQHandler + 0x0000000008003078 DMA1_Channel1_IRQHandler + 0x0000000008003078 Default_Handler + 0x0000000008003078 DMA1_Channel4_5_IRQHandler + 0x0000000008003078 EXTI0_1_IRQHandler + 0x0000000008003078 WWDG_IRQHandler + 0x0000000008003078 DMA1_Channel2_3_IRQHandler + 0x0000000008003078 USART2_IRQHandler + 0x0000000008003078 FLASH_IRQHandler + 0x0000000008003078 USART1_IRQHandler + 0x0000000008003078 TIM1_BRK_UP_TRG_COM_IRQHandler + *fill* 0x000000000800307a 0x2 + .text.__libc_init_array + 0x000000000800307c 0x48 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + 0x000000000800307c __libc_init_array + *(.glue_7) + .glue_7 0x00000000080030c4 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x00000000080030c4 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x00000000080030c4 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + *(.init) + .init 0x00000000080030c4 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + 0x00000000080030c4 _init + .init 0x00000000080030c8 0x8 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + *(.fini) + .fini 0x00000000080030d0 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + 0x00000000080030d0 _fini + .fini 0x00000000080030d4 0x8 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o + 0x00000000080030dc . = ALIGN (0x4) + 0x00000000080030dc _etext = . + +.vfp11_veneer 0x00000000080030dc 0x0 + .vfp11_veneer 0x00000000080030dc 0x0 linker stubs + +.v4_bx 0x00000000080030dc 0x0 + .v4_bx 0x00000000080030dc 0x0 linker stubs + +.iplt 0x00000000080030dc 0x0 + .iplt 0x00000000080030dc 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + +.flash_data_array + 0x0000000008007c00 0x242 + 0x0000000008007c00 . = ALIGN (0x4) + .flash_data_array + 0x0000000008007c00 0x242 Src/main.o + 0x0000000008007c00 userdata + +.rodata 0x00000000080030dc 0x124 + 0x00000000080030dc . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.USBD_StdDevReq + 0x00000000080030dc 0x60 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .rodata.TIM16_IRQHandler.str1.4 + 0x000000000800313c 0x2 Src/main.o + *fill* 0x000000000800313e 0x2 + .rodata.main.str1.4 + 0x0000000008003140 0x14 Src/main.o + 0x12 (size before relaxing) + .rodata.symbol_error + 0x0000000008003154 0x10 Src/main.o + .rodata.symbol_times + 0x0000000008003164 0x10 Src/main.o + .rodata.USBD_CONFIGURATION_STRING_DATA + 0x0000000008003174 0x17 Src/usbd_desc.o + *fill* 0x000000000800318b 0x1 + .rodata.USBD_INTERFACE_STRING_DATA + 0x000000000800318c 0x1d Src/usbd_desc.o + *fill* 0x00000000080031a9 0x3 + .rodata.USBD_MANUFACTURER_STRING_DATA + 0x00000000080031ac 0x29 Src/usbd_desc.o + *fill* 0x00000000080031d5 0x3 + .rodata.USBD_PRODUCT_STRING_DATA + 0x00000000080031d8 0x27 Src/usbd_desc.o + 0x0000000008003200 . = ALIGN (0x4) + *fill* 0x00000000080031ff 0x1 + +.rel.dyn 0x0000000008003200 0x0 + .rel.iplt 0x0000000008003200 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + +.ARM.extab 0x0000000008003200 0x0 + 0x0000000008003200 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000008003200 . = ALIGN (0x4) + +.ARM 0x0000000008003200 0x0 + 0x0000000008003200 . = ALIGN (0x4) + 0x0000000008003200 __exidx_start = . + *(.ARM.exidx*) + 0x0000000008003200 __exidx_end = . + 0x0000000008003200 . = ALIGN (0x4) + +.preinit_array 0x0000000008003200 0x0 + 0x0000000008003200 . = ALIGN (0x4) + 0x0000000008003200 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0000000008003200 PROVIDE (__preinit_array_end = .) + 0x0000000008003200 . = ALIGN (0x4) + +.init_array 0x0000000008003200 0x4 + 0x0000000008003200 . = ALIGN (0x4) + 0x0000000008003200 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0000000008003200 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + 0x0000000008003204 PROVIDE (__init_array_end = .) + 0x0000000008003204 . = ALIGN (0x4) + +.fini_array 0x0000000008003204 0x4 + 0x0000000008003204 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0000000008003204 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0000000008003208 . = ALIGN (0x4) + 0x0000000008003208 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0x174 load address 0x0000000008003208 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.USBD_CDC + 0x0000000020000000 0x38 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000020000000 USBD_CDC + .data.USBD_CDC_CfgFSDesc + 0x0000000020000038 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000020000038 USBD_CDC_CfgFSDesc + *fill* 0x000000002000007b 0x1 + .data.USBD_CDC_CfgHSDesc + 0x000000002000007c 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x000000002000007c USBD_CDC_CfgHSDesc + *fill* 0x00000000200000bf 0x1 + .data.USBD_CDC_DeviceQualifierDesc + 0x00000000200000c0 0xa Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x00000000200000ca 0x2 + .data.USBD_CDC_OtherSpeedCfgDesc + 0x00000000200000cc 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000200000cc USBD_CDC_OtherSpeedCfgDesc + *fill* 0x000000002000010f 0x1 + .data.SystemCoreClock + 0x0000000020000110 0x4 Src/system_stm32f0xx.o + 0x0000000020000110 SystemCoreClock + .data.USBD_Interface_fops_FS + 0x0000000020000114 0x10 Src/usbd_cdc_if.o + 0x0000000020000114 USBD_Interface_fops_FS + .data.FS_Desc 0x0000000020000124 0x1c Src/usbd_desc.o + 0x0000000020000124 FS_Desc + .data.USBD_FS_DeviceDesc + 0x0000000020000140 0x12 Src/usbd_desc.o + 0x0000000020000140 USBD_FS_DeviceDesc + *fill* 0x0000000020000152 0x2 + .data.USBD_LangIDDesc + 0x0000000020000154 0x4 Src/usbd_desc.o + 0x0000000020000154 USBD_LangIDDesc + .data.USBD_StringSerial + 0x0000000020000158 0x1a Src/usbd_desc.o + 0x0000000020000158 USBD_StringSerial + 0x0000000020000174 . = ALIGN (0x4) + *fill* 0x0000000020000172 0x2 + 0x0000000020000174 _edata = . + +.igot.plt 0x0000000020000174 0x0 load address 0x000000000800337c + .igot.plt 0x0000000020000174 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + 0x0000000020000174 . = ALIGN (0x4) + +.bss 0x0000000020000174 0xdc8 load address 0x000000000800337c + 0x0000000020000174 _sbss = . + 0x0000000020000174 __bss_start__ = _sbss + *(.bss) + .bss 0x0000000020000174 0x1c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + *(.bss*) + .bss.ifalt.8392 + 0x0000000020000190 0x1 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .bss.cfgidx.8395 + 0x0000000020000191 0x1 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x0000000020000192 0x2 + .bss.RX_FIFO 0x0000000020000194 0x108 Src/main.o + 0x0000000020000194 RX_FIFO + .bss.SendOperationReady + 0x000000002000029c 0x1 Src/main.o + 0x000000002000029c SendOperationReady + *fill* 0x000000002000029d 0x3 + .bss.comm_reset_flag + 0x00000000200002a0 0x4 Src/main.o + 0x00000000200002a0 comm_reset_flag + .bss.ram_frame_repeat_delay + 0x00000000200002a4 0x4 Src/main.o + 0x00000000200002a4 ram_frame_repeat_delay + .bss.remote_mode + 0x00000000200002a8 0x4 Src/main.o + 0x00000000200002a8 remote_mode + .bss.mem.8484 0x00000000200002ac 0x220 Src/usbd_conf.o + *(COMMON) + COMMON 0x00000000200004cc 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x00000000200004cc uwTick + COMMON 0x00000000200004d0 0x428 Src/main.o + 0x00000000200004d0 Symbol + 0x00000000200004d4 Repeats + 0x00000000200004d8 TickCounter + 0x00000000200004dc ByteSentCounter + 0x00000000200004e0 CurrentByte + 0x00000000200004e4 SymbolCounter + 0x00000000200004e8 ErrorAcc + 0x00000000200004ec FrameData + 0x00000000200004f0 flash_data_buffer + 0x00000000200008f0 ByteCount + 0x00000000200008f4 Burst + COMMON 0x00000000200008f8 0x224 Src/usb_device.o + 0x00000000200008f8 hUsbDeviceFS + COMMON 0x0000000020000b1c 0x200 Src/usbd_cdc_if.o + 0x0000000020000b1c UserRxBufferFS + 0x0000000020000c1c UserTxBufferFS + COMMON 0x0000000020000d1c 0x220 Src/usbd_conf.o + 0x0000000020000d1c hpcd_USB_FS + 0x0000000020000f3c . = ALIGN (0x4) + 0x0000000020000f3c _ebss = . + 0x0000000020000f3c __bss_end__ = _ebss + +._user_heap_stack + 0x0000000020000f3c 0x584 load address 0x000000000800337c + 0x0000000020000f40 . = ALIGN (0x8) + *fill* 0x0000000020000f3c 0x4 + [!provide] PROVIDE (end = .) + [!provide] PROVIDE (_end = .) + 0x00000000200010c0 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000f40 0x180 + 0x00000000200014c0 . = (. + _Min_Stack_Size) + *fill* 0x00000000200010c0 0x400 + 0x00000000200014c0 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o + .ARM.attributes + 0x000000000000001e 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o + .ARM.attributes + 0x000000000000004a 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .ARM.attributes + 0x000000000000007b 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .ARM.attributes + 0x00000000000000ac 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .ARM.attributes + 0x00000000000000dd 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .ARM.attributes + 0x000000000000010e 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .ARM.attributes + 0x000000000000013f 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .ARM.attributes + 0x0000000000000170 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .ARM.attributes + 0x00000000000001a1 0x31 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .ARM.attributes + 0x00000000000001d2 0x31 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .ARM.attributes + 0x0000000000000203 0x31 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .ARM.attributes + 0x0000000000000234 0x31 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .ARM.attributes + 0x0000000000000265 0x31 Src/gpio.o + .ARM.attributes + 0x0000000000000296 0x31 Src/main.o + .ARM.attributes + 0x00000000000002c7 0x31 Src/stm32f0xx_hal_msp.o + .ARM.attributes + 0x00000000000002f8 0x31 Src/stm32f0xx_it.o + .ARM.attributes + 0x0000000000000329 0x31 Src/system_stm32f0xx.o + .ARM.attributes + 0x000000000000035a 0x31 Src/usb_device.o + .ARM.attributes + 0x000000000000038b 0x31 Src/usbd_cdc_if.o + .ARM.attributes + 0x00000000000003bc 0x31 Src/usbd_conf.o + .ARM.attributes + 0x00000000000003ed 0x31 Src/usbd_desc.o + .ARM.attributes + 0x000000000000041e 0x21 Startup/startup_stm32f070f6px.o + .ARM.attributes + 0x000000000000043f 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x000000000000046b 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) + .ARM.attributes + 0x0000000000000489 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000000000004a7 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o +OUTPUT(ESLBlaster.elf elf32-littlearm) + +.comment 0x0000000000000000 0x7b + .comment 0x0000000000000000 0x7b Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x7c (size before relaxing) + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .comment 0x000000000000007b 0x7c Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .comment 0x000000000000007b 0x7c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .comment 0x000000000000007b 0x7c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .comment 0x000000000000007b 0x7c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .comment 0x000000000000007b 0x7c Src/gpio.o + .comment 0x000000000000007b 0x7c Src/main.o + .comment 0x000000000000007b 0x7c Src/stm32f0xx_hal_msp.o + .comment 0x000000000000007b 0x7c Src/stm32f0xx_it.o + .comment 0x000000000000007b 0x7c Src/system_stm32f0xx.o + .comment 0x000000000000007b 0x7c Src/usb_device.o + .comment 0x000000000000007b 0x7c Src/usbd_cdc_if.o + .comment 0x000000000000007b 0x7c Src/usbd_conf.o + .comment 0x000000000000007b 0x7c Src/usbd_desc.o + +.debug_frame 0x0000000000000000 0x4c + .debug_frame 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o) + .debug_frame 0x000000000000002c 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) diff --git a/hardware/esl_blaster/FW01/Release/makefile b/hardware/esl_blaster/FW01/Release/makefile new file mode 100644 index 0000000..9e12f8b --- /dev/null +++ b/hardware/esl_blaster/FW01/Release/makefile @@ -0,0 +1,75 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Startup/subdir.mk +-include Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk +-include Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +ESLBlaster.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +ESLBlaster.list \ + +OBJCOPY_BIN += \ +ESLBlaster.bin \ + + +# All Target +all: ESLBlaster.elf secondary-outputs + +# Tool invocations +ESLBlaster.elf: $(OBJS) $(USER_OBJS) C:\Users\furrtek\Documents\Electro\ESLBlaster\FW\STM32F070F6PX_FLASH.ld + arm-none-eabi-gcc -o "ESLBlaster.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0 -T"C:\Users\furrtek\Documents\Electro\ESLBlaster\FW\STM32F070F6PX_FLASH.ld" --specs=nosys.specs -Wl,-Map="ESLBlaster.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +ESLBlaster.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "ESLBlaster.list" + @echo 'Finished building: $@' + @echo ' ' + +ESLBlaster.bin: $(EXECUTABLES) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "ESLBlaster.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets diff --git a/hardware/esl_blaster/FW01/Release/program.bat b/hardware/esl_blaster/FW01/Release/program.bat new file mode 100644 index 0000000..1ee9ed8 --- /dev/null +++ b/hardware/esl_blaster/FW01/Release/program.bat @@ -0,0 +1 @@ +..\dfu-util-0.9-win64\dfu-util --device 0483:df11 -a 0 -s 0x08000000:leave --download ESLBlaster.bin \ No newline at end of file diff --git a/hardware/esl_blaster/FW01/Release/readback.bat b/hardware/esl_blaster/FW01/Release/readback.bat new file mode 100644 index 0000000..09a7f49 --- /dev/null +++ b/hardware/esl_blaster/FW01/Release/readback.bat @@ -0,0 +1,2 @@ +..\dfu-util-0.9-win64\dfu-util --device 0483:df11 -a 0 -s 0x08000000:leave --upload readback.bin +pause \ No newline at end of file diff --git a/hardware/esl_blaster/FW/STM32F070F6PX_FLASH.ld b/hardware/esl_blaster/FW01/STM32F070F6PX_FLASH.ld similarity index 100% rename from hardware/esl_blaster/FW/STM32F070F6PX_FLASH.ld rename to hardware/esl_blaster/FW01/STM32F070F6PX_FLASH.ld diff --git a/hardware/esl_blaster/FW/Src/gpio.c b/hardware/esl_blaster/FW01/Src/gpio.c similarity index 97% rename from hardware/esl_blaster/FW/Src/gpio.c rename to hardware/esl_blaster/FW01/Src/gpio.c index dd71183..5c5214d 100644 --- a/hardware/esl_blaster/FW/Src/gpio.c +++ b/hardware/esl_blaster/FW01/Src/gpio.c @@ -1,54 +1,54 @@ -/** - ****************************************************************************** - * File Name : gpio.c - * Description : This file provides code for the configuration - * of all used GPIO pins. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#include "gpio.h" - -void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct; - - // GPIO Ports Clock Enable, GPIOB isn't used - LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); - LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); - - // Configure PA4 as input - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // Red LED off - //HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); - - // Configure PA6 as push-pull output - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Alternate = GPIO_AF1_IR; // TIM3_CH1 - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // IR LEDs off - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_SET); - - // Configure PA7 as analog input - GPIO_InitStruct.Pin = GPIO_PIN_5; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); -} +/** + ****************************************************************************** + * File Name : gpio.c + * Description : This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#include "gpio.h" + +void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct; + + // GPIO Ports Clock Enable, GPIOB isn't used + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); + + // Configure PA4 as input + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // Red LED off + //HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); + + // Configure PA6 as push-pull output + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Alternate = GPIO_AF1_IR; // TIM3_CH1 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // IR LEDs off + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_SET); + + // Configure PA7 as analog input + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +} diff --git a/hardware/esl_blaster/FW/Src/main.c b/hardware/esl_blaster/FW01/Src/main.c similarity index 96% rename from hardware/esl_blaster/FW/Src/main.c rename to hardware/esl_blaster/FW01/Src/main.c index 657a500..e17a623 100644 --- a/hardware/esl_blaster/FW/Src/main.c +++ b/hardware/esl_blaster/FW01/Src/main.c @@ -1,452 +1,452 @@ -// ESL Blaster firmware v1.00 -// For board rev. B -// 2019 furrtek -// DO NOT COMPILE WITH -O3 ! Only -O1, or USB won't work anymore - -// TODO: Load custom symbol lengths and IR timer settings ? - -// Bloated stuff: -// HAL_GPIO_Init 0x1b4 -// HAL_PCD_Init 0x240 -// HAL_PCD_EP_Open 0x35c -// HAL_PCD_IRQHandler 0x5cc -// USBD_StdDevReq 0x338 - -#include "main.h" -#include "usb_device.h" -#include "gpio.h" - -void SystemClock_Config(void); -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -volatile FIFO RX_FIFO = {.head=0, .tail=0}; - -volatile uint32_t ByteSentCounter, ByteCount; -volatile uint32_t SymbolCounter; -volatile uint32_t TickCounter, Burst, Repeats, ErrorAcc; -volatile uint8_t SendOperationReady = 0, CurrentByte, Symbol; -volatile const uint8_t * FrameData; -volatile uint32_t comm_reset_flag = 0, ram_frame_repeat_delay = 0; -volatile uint32_t remote_mode = 0; - -typedef struct { - uint16_t flags; - uint16_t repeats; - uint16_t delay; - uint16_t frame_size; - uint8_t frame_data[64]; -} entry_t; - -typedef struct { - uint16_t entry_count; // 0~8 - entry_t entries[8]; -} userdata_t; - -#define RED_LED_OFF TIM3->CCR1 = 0x0000; -#define RED_LED_NORMAL TIM3->CCR1 = (GPIOA->IDR & GPIO_IDR_4) ? 0x0000 : 0x0100; // Off/Charge -#define RED_LED_MAX TIM3->CCR1 = 0x4000; // IR transmit - -#define CDC_NOK CDC_Transmit_FS((uint8_t*)"N", 1); -#define CDC_OK CDC_Transmit_FS((uint8_t*)"K", 1); - -/* -static const uint8_t frame_button1[11] = { - 0x84, 0x00, 0x00, 0x00, 0x00, 0xAB, 0x09, 0x00, 0x00, 0xF2, 0xA7 -}; - -static const uint8_t frame_dmchange1[11] = { - 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x09, 0x00, 0x00, 0xBD, 0xC3 -}; - -static const uint8_t frame_dmchange2[11] = { - 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x11, 0x00, 0x00, 0xEA, 0x80 -};*/ - -// PP4 symbol times in TIM16 steps -static const uint32_t symbol_times[4] = { - 6-1, 24-1, 12-1, 18-1 -}; -static const uint32_t symbol_error[4] = { - 103, 414, 207, 310 // All *100 -}; - -void TIM16_IRQHandler(void) { - if (SendOperationReady) { - if (!TickCounter) { - if (Burst == 0) { - // Start burst ASAP - TIM16->CCMR1 |= TIM_CCMR1_OC1M_0; // OC1REF forced high - TickCounter = 4-1; - - if (!(SymbolCounter & 3)) - CurrentByte = FrameData[ByteSentCounter++]; // Load byte - - // Load symbol - Symbol = CurrentByte & 3; - CurrentByte >>= 2; - SymbolCounter++; - - Burst = 1; - } else { - // Stop burst ASAP - TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // OC1REF forced low - - Burst = 0; - - TickCounter = symbol_times[Symbol]; - // Auto-adjust symbol time depending on timing error accumulation - if (ErrorAcc >= 1000) { - TickCounter++; - ErrorAcc -= 1000; - } - ErrorAcc += symbol_error[Symbol]; - - if (ByteSentCounter > ByteCount) { - if (Repeats) { - Repeats--; - ByteSentCounter = 0; - SymbolCounter = 0; - ErrorAcc = 0; - TickCounter = ram_frame_repeat_delay * 50; //2000; - } else { - SendOperationReady = 0; - RED_LED_NORMAL - if (!remote_mode) CDC_OK - } - } - } - } else - TickCounter--; - } - - // Clear TIM_ENV update interrupt - TIM16->SR &= (uint16_t)(~TIM_SR_UIF); -} - -void TIM14_IRQHandler(void) { - comm_reset_flag = 1; - - // Clear TIM_ENV update interrupt - TIM14->SR &= (uint16_t)(~TIM_SR_UIF); -} - -// Check MCP73831 STAT output -// Low: Charging -// High: Charge done -// Hi-z: No battery - -void IRTX(const uint8_t * data, const uint32_t length, const uint32_t rpt) { - FrameData = data; - ByteSentCounter = 0; - ByteCount = length; - TickCounter = 0; - Burst = 0; - SymbolCounter = 0; - Repeats = rpt; - ErrorAcc = 0; - SendOperationReady = 1; - - // RED LED ON - RED_LED_MAX - - TIM16->DIER |= TIM_DIER_UIE; // Enable TIM16 update interrupt - TIM16->CR1 |= TIM_CR1_CEN; // Enable all TIM16 interrupts -} - -uint32_t adc_read() { - ADC1->CR = ADC_CR_ADEN; - while (!(ADC1->ISR & ADC_ISR_ADRDY)); // Wait for ADRDY - ADC1->CR |= ADC_CR_ADSTART; - while (!(ADC1->ISR & ADC_ISR_EOC)); // Wait for EOC flag - return ADC1->DR; -} - -userdata_t userdata __attribute__((section(".flash_data_array"))); - -uint8_t flash_data_buffer[1024]; - -int main(void) { - enum comm_states { - STATE_IDLE, - STATE_GET_FRAME_SIZE, - STATE_GET_FRAME_REPEAT_DELAY, - STATE_GET_FRAME_REPEATS_LOW, - STATE_GET_FRAME_REPEATS_HIGH, - STATE_GET_FRAME_DATA, - STATE_FLASH_LOAD - }; - - enum comm_states comm_state = STATE_IDLE; - uint8_t ram_frame_data[256]; - uint32_t ram_frame_size = 0, ram_frame_repeats = 0, ram_frame_data_counter = 0; - uint32_t flash_data_counter = 0; - - // Reset all peripherals, initializes the Flash interface and the Systick - HAL_Init(); - - // Configure the system clock - SystemClock_Config(); - - // Initialize all configured peripherals - MX_GPIO_Init(); - MX_USB_DEVICE_Init(); - - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14); - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_ADC1); - - // TIM17: Carrier, TIM16: Envelope - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM16); // These can be ORed - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM17); - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); - - GPIO_InitTypeDef GPIO_InitStruct; - // Configure PA13 as push-pull output for IR_OUT - GPIO_InitStruct.Pin = GPIO_PIN_13; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Alternate = GPIO_AF1_IR; // IR_OUT - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // t=1/32768: 30.52us - // 00: 61us (2t=61.03) (TIM16 6 *10=60 Err=-1.03) - // 01: 244us (8t=244.14) (TIM16 24 *10=240 Err=-4.14) - // 10: 122us (4t=122.07) (TIM16 12 *10=120 Err=-2.07) - // 11: 183us (6t=183.10) (TIM16 18 *10=180 Err=-3.10) - // Burst: 40us (TIM16 4 *10=40 Err=0) - - // TIM17: Carrier - TIM17->PSC = 0; - TIM17->ARR = 38 - 1; // 48M / 1.25M = 38.4, 38: 1.26MHz - TIM17->CCR1 = (uint16_t)(37 / 2); // 50% duty cycle - TIM17->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; // PWM mode 1 - TIM17->CCER |= TIM_CCER_CC1E; // CC1 output enable - TIM17->BDTR |= TIM_BDTR_MOE; - - // TIM16: Symbol timing - TIM16->PSC = 0; - TIM16->ARR = 484 - 1; // 48M / 100k = 480 (10us steps) - TIM16->CCMR1 |= TIM_CCMR1_OC1M_2; // Output forced low - TIM16->CCER |= TIM_CCER_CC1E; // CC1 output enable - TIM16->BDTR |= TIM_BDTR_MOE; - TIM16->DIER |= TIM_DIER_UIE; // Update interrupt enable - - TIM17->CR1 |= TIM_CR1_CEN; // Enable timer - TIM17->EGR |= TIM_EGR_UG; - - NVIC_EnableIRQ(TIM16_IRQn); - NVIC_SetPriority(TIM16_IRQn, 0); - - // TIM14: Comm timeout - TIM14->PSC = (uint16_t)(100); // 48M/100/65535 = ~7.32Hz (137ms) - TIM14->ARR = (uint16_t)(0xFFFF); - TIM14->CCMR1 = 0; - TIM14->CCER = 0; - TIM14->DIER |= TIM_DIER_UIE; // Update interrupt enable - TIM14->CR1 |= TIM_CR1_CEN; // Enable timer - TIM14->EGR |= TIM_EGR_UG; - - NVIC_EnableIRQ(TIM14_IRQn); - NVIC_SetPriority(TIM14_IRQn, 1); - - // TIM3: Red LED PWM - TIM3->ARR = (uint16_t)(0xFFFF); - TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; // PWM mode 2 - TIM3->CCER = TIM_CCER_CC1E; - TIM3->CCR1 = 0x1000; - TIM3->CR1 |= TIM_CR1_CEN; // Enable timer - TIM3->EGR |= TIM_EGR_UG; - - ADC1->CFGR1 = 0; - ADC1->SMPR = ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0; - ADC1->CHSELR = ADC_CHSELR_CHSEL5; - - // ADC step = 3.3/(2^12-1) = ~806uV - // USB: 5V - // Batt full charge: 4.2V - // 5/2 = 2.5V -> v = ~3102 - // 4.2/2 = 2.1V -> v = ~2605 - // (3102+2605)/2 = 2854 - - if (adc_read() < 2700) { - uint32_t remote_frame_count = userdata.entry_count; - uint32_t remote_frame_index = 0; - - remote_mode = 1; - - for (;;) { - //HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_6); // Battery mode - /*RED_LED_MAX - for (uint32_t c = 0; c < 1000000; c++) {}; - RED_LED_OFF - for (uint32_t c = 0; c < 1000000; c++) {};*/ - - /*if (userdata.entries[1].frame_data[0] == 0x85) { - for (;;) { RED_LED_OFF }; - }*/ - - ram_frame_size = userdata.entries[remote_frame_index].frame_size; - ram_frame_repeats = userdata.entries[remote_frame_index].repeats; - ram_frame_repeat_delay = userdata.entries[remote_frame_index].delay; - for (uint32_t c = 0; c < ram_frame_size; c++) - ram_frame_data[c] = userdata.entries[remote_frame_index].frame_data[c]; - - IRTX(ram_frame_data, ram_frame_size, ram_frame_repeats); - - while (SendOperationReady) {}; - - remote_frame_index++; - if (remote_frame_index >= remote_frame_count) remote_frame_index = 0; - } - } - - // Main loop - while (1) { - - if (comm_reset_flag) { - comm_reset_flag = 0; - comm_state = STATE_IDLE; - if (!SendOperationReady) RED_LED_NORMAL // Update LED - //HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_6); // DEBUG - } - - while (RX_FIFO.head != RX_FIFO.tail) { - TIM14->CNT = (uint16_t)0; // Reset comm. timeout - - // Process one byte from the RX FIFO - uint8_t byte = RX_FIFO.data[RX_FIFO.tail]; - - if (comm_state == STATE_IDLE) { - if (byte == 'L') { - // Load new frame data - comm_state = STATE_GET_FRAME_SIZE; - } else if (byte == 'T') { - // Transmit loaded frame - IRTX(ram_frame_data, ram_frame_size, ram_frame_repeats); - } else if (byte == '?') { - // Reply ID - CDC_Transmit_FS((uint8_t*)"ESLBlasterB0", 12); - } else if (byte == 'W') { - flash_data_counter = 0; - comm_state = STATE_FLASH_LOAD; - } else if (byte == 'R') { - // Read flash - uint16_t buff; - uint16_t* ptr = (uint16_t*)0x8007C00; - for (uint32_t d = 0; d < (1024/4); d++) { - buff = *ptr; - while(CDC_Transmit_FS((uint8_t*)&buff, 2) != USBD_OK) {}; - ptr += 2; - } - } else if (byte == 'S') { - // E-Stop - // Stop burst - TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // OC1REF forced low - SendOperationReady = 0; - } - } else if (comm_state == STATE_GET_FRAME_SIZE) { - ram_frame_size = byte; - comm_state = STATE_GET_FRAME_REPEAT_DELAY; - } else if (comm_state == STATE_GET_FRAME_REPEAT_DELAY) { - ram_frame_repeat_delay = byte; - comm_state = STATE_GET_FRAME_REPEATS_LOW; - } else if (comm_state == STATE_GET_FRAME_REPEATS_LOW) { - ram_frame_repeats = byte; - comm_state = STATE_GET_FRAME_REPEATS_HIGH; - } else if (comm_state == STATE_GET_FRAME_REPEATS_HIGH) { - ram_frame_repeats |= ((uint32_t)byte << 8); - ram_frame_data_counter = 0; - comm_state = STATE_GET_FRAME_DATA; - } else if (comm_state == STATE_GET_FRAME_DATA) { - ram_frame_data[ram_frame_data_counter++] = byte; - if (ram_frame_data_counter == ram_frame_size) - comm_state = STATE_IDLE; - } else if (comm_state == STATE_FLASH_LOAD) { - flash_data_buffer[flash_data_counter++] = byte; - - if (!(flash_data_counter & 0x7F)) - CDC_OK - - if (flash_data_counter == 1024) { - // Write flash - // Unlock - while ((FLASH->SR & FLASH_SR_BSY) != 0) {} - if (FLASH->CR & FLASH_CR_LOCK) { - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } - // Main flash: 0x0800 0000 - 0x0800 7FFF - // 32 pages de 1kB - // Page #31: data - - // Erase - FLASH->CR |= FLASH_CR_PER; - FLASH->AR = (uint32_t)0x8007C00; - FLASH->CR |= FLASH_CR_STRT; - while ((FLASH->SR & FLASH_SR_BSY) != 0) {} - if (FLASH->SR & FLASH_SR_EOP) - FLASH->SR = FLASH_SR_EOP; - else - CDC_NOK - FLASH->CR &= ~FLASH_CR_PER; - - // Program halfword - FLASH->CR |= FLASH_CR_PG; - __IO uint16_t* ptr = (uint16_t*)0x8007C00; - uint16_t* src = (uint16_t*)flash_data_buffer; - for (uint32_t d = 0; d < 1024; d += 2) { - *ptr++ = *src++; - } - while (FLASH->SR & FLASH_SR_BSY) {} - if (FLASH->SR & FLASH_SR_EOP) - FLASH->SR = FLASH_SR_EOP; - else - CDC_NOK - FLASH->CR &= ~FLASH_CR_PG; - - CDC_OK - RED_LED_MAX - - comm_state = STATE_IDLE; - } - } - - RX_FIFO.tail = FIFO_INCR(RX_FIFO.tail); - } - } -} - -void SystemClock_Config(void) { - LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); // 1ws - - if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1) - Error_Handler(); - - LL_RCC_HSE_Enable(); - - // Wait for HSE ready - while (LL_RCC_HSE_IsReady() != 1) {}; - - // 4 * 12 = 48MHz - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1); - LL_RCC_PLL_Enable(); - - // Wait for PLL ready - while (LL_RCC_PLL_IsReady() != 1) {}; - - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - - // Wait for System clock ready - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}; - - LL_Init1msTick(48000000); - LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK); - LL_SetSystemCoreClock(48000000); - LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL); -} - -void Error_Handler(void) { - /* User can add his own implementation to report the HAL error return state */ -} +// ESL Blaster firmware v1.00 +// For board rev. B +// 2019 furrtek +// DO NOT COMPILE WITH -O3 ! Only -O1, or USB won't work anymore + +// TODO: Load custom symbol lengths and IR timer settings ? + +// Bloated stuff: +// HAL_GPIO_Init 0x1b4 +// HAL_PCD_Init 0x240 +// HAL_PCD_EP_Open 0x35c +// HAL_PCD_IRQHandler 0x5cc +// USBD_StdDevReq 0x338 + +#include "main.h" +#include "usb_device.h" +#include "gpio.h" + +void SystemClock_Config(void); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +volatile FIFO RX_FIFO = {.head=0, .tail=0}; + +volatile uint32_t ByteSentCounter, ByteCount; +volatile uint32_t SymbolCounter; +volatile uint32_t TickCounter, Burst, Repeats, ErrorAcc; +volatile uint8_t SendOperationReady = 0, CurrentByte, Symbol; +volatile const uint8_t * FrameData; +volatile uint32_t comm_reset_flag = 0, ram_frame_repeat_delay = 0; +volatile uint32_t remote_mode = 0; + +typedef struct { + uint16_t flags; + uint16_t repeats; + uint16_t delay; + uint16_t frame_size; + uint8_t frame_data[64]; +} entry_t; + +typedef struct { + uint16_t entry_count; // 0~8 + entry_t entries[8]; +} userdata_t; + +#define RED_LED_OFF TIM3->CCR1 = 0x0000; +#define RED_LED_NORMAL TIM3->CCR1 = (GPIOA->IDR & GPIO_IDR_4) ? 0x0000 : 0x0100; // Off/Charge +#define RED_LED_MAX TIM3->CCR1 = 0x4000; // IR transmit + +#define CDC_NOK CDC_Transmit_FS((uint8_t*)"N", 1); +#define CDC_OK CDC_Transmit_FS((uint8_t*)"K", 1); + +/* +static const uint8_t frame_button1[11] = { + 0x84, 0x00, 0x00, 0x00, 0x00, 0xAB, 0x09, 0x00, 0x00, 0xF2, 0xA7 +}; + +static const uint8_t frame_dmchange1[11] = { + 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x09, 0x00, 0x00, 0xBD, 0xC3 +}; + +static const uint8_t frame_dmchange2[11] = { + 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x11, 0x00, 0x00, 0xEA, 0x80 +};*/ + +// PP4 symbol times in TIM16 steps +static const uint32_t symbol_times[4] = { + 6-1, 24-1, 12-1, 18-1 +}; +static const uint32_t symbol_error[4] = { + 103, 414, 207, 310 // All *100 +}; + +void TIM16_IRQHandler(void) { + if (SendOperationReady) { + if (!TickCounter) { + if (Burst == 0) { + // Start burst ASAP + TIM16->CCMR1 |= TIM_CCMR1_OC1M_0; // OC1REF forced high + TickCounter = 4-1; + + if (!(SymbolCounter & 3)) + CurrentByte = FrameData[ByteSentCounter++]; // Load byte + + // Load symbol + Symbol = CurrentByte & 3; + CurrentByte >>= 2; + SymbolCounter++; + + Burst = 1; + } else { + // Stop burst ASAP + TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // OC1REF forced low + + Burst = 0; + + TickCounter = symbol_times[Symbol]; + // Auto-adjust symbol time depending on timing error accumulation + if (ErrorAcc >= 1000) { + TickCounter++; + ErrorAcc -= 1000; + } + ErrorAcc += symbol_error[Symbol]; + + if (ByteSentCounter > ByteCount) { + if (Repeats) { + Repeats--; + ByteSentCounter = 0; + SymbolCounter = 0; + ErrorAcc = 0; + TickCounter = ram_frame_repeat_delay * 50; //2000; + } else { + SendOperationReady = 0; + RED_LED_NORMAL + if (!remote_mode) CDC_OK + } + } + } + } else + TickCounter--; + } + + // Clear TIM_ENV update interrupt + TIM16->SR &= (uint16_t)(~TIM_SR_UIF); +} + +void TIM14_IRQHandler(void) { + comm_reset_flag = 1; + + // Clear TIM_ENV update interrupt + TIM14->SR &= (uint16_t)(~TIM_SR_UIF); +} + +// Check MCP73831 STAT output +// Low: Charging +// High: Charge done +// Hi-z: No battery + +void IRTX(const uint8_t * data, const uint32_t length, const uint32_t rpt) { + FrameData = data; + ByteSentCounter = 0; + ByteCount = length; + TickCounter = 0; + Burst = 0; + SymbolCounter = 0; + Repeats = rpt; + ErrorAcc = 0; + SendOperationReady = 1; + + // RED LED ON + RED_LED_MAX + + TIM16->DIER |= TIM_DIER_UIE; // Enable TIM16 update interrupt + TIM16->CR1 |= TIM_CR1_CEN; // Enable all TIM16 interrupts +} + +uint32_t adc_read() { + ADC1->CR = ADC_CR_ADEN; + while (!(ADC1->ISR & ADC_ISR_ADRDY)); // Wait for ADRDY + ADC1->CR |= ADC_CR_ADSTART; + while (!(ADC1->ISR & ADC_ISR_EOC)); // Wait for EOC flag + return ADC1->DR; +} + +userdata_t userdata __attribute__((section(".flash_data_array"))); + +uint8_t flash_data_buffer[1024]; + +int main(void) { + enum comm_states { + STATE_IDLE, + STATE_GET_FRAME_SIZE, + STATE_GET_FRAME_REPEAT_DELAY, + STATE_GET_FRAME_REPEATS_LOW, + STATE_GET_FRAME_REPEATS_HIGH, + STATE_GET_FRAME_DATA, + STATE_FLASH_LOAD + }; + + enum comm_states comm_state = STATE_IDLE; + uint8_t ram_frame_data[256]; + uint32_t ram_frame_size = 0, ram_frame_repeats = 0, ram_frame_data_counter = 0; + uint32_t flash_data_counter = 0; + + // Reset all peripherals, initializes the Flash interface and the Systick + HAL_Init(); + + // Configure the system clock + SystemClock_Config(); + + // Initialize all configured peripherals + MX_GPIO_Init(); + MX_USB_DEVICE_Init(); + + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_ADC1); + + // TIM17: Carrier, TIM16: Envelope + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM16); // These can be ORed + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM17); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + + GPIO_InitTypeDef GPIO_InitStruct; + // Configure PA13 as push-pull output for IR_OUT + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Alternate = GPIO_AF1_IR; // IR_OUT + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // t=1/32768: 30.52us + // 00: 61us (2t=61.03) (TIM16 6 *10=60 Err=-1.03) + // 01: 244us (8t=244.14) (TIM16 24 *10=240 Err=-4.14) + // 10: 122us (4t=122.07) (TIM16 12 *10=120 Err=-2.07) + // 11: 183us (6t=183.10) (TIM16 18 *10=180 Err=-3.10) + // Burst: 40us (TIM16 4 *10=40 Err=0) + + // TIM17: Carrier + TIM17->PSC = 0; + TIM17->ARR = 38 - 1; // 48M / 1.25M = 38.4, 38: 1.26MHz + TIM17->CCR1 = (uint16_t)(37 / 2); // 50% duty cycle + TIM17->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; // PWM mode 1 + TIM17->CCER |= TIM_CCER_CC1E; // CC1 output enable + TIM17->BDTR |= TIM_BDTR_MOE; + + // TIM16: Symbol timing + TIM16->PSC = 0; + TIM16->ARR = 484 - 1; // 48M / 100k = 480 (10us steps) + TIM16->CCMR1 |= TIM_CCMR1_OC1M_2; // Output forced low + TIM16->CCER |= TIM_CCER_CC1E; // CC1 output enable + TIM16->BDTR |= TIM_BDTR_MOE; + TIM16->DIER |= TIM_DIER_UIE; // Update interrupt enable + + TIM17->CR1 |= TIM_CR1_CEN; // Enable timer + TIM17->EGR |= TIM_EGR_UG; + + NVIC_EnableIRQ(TIM16_IRQn); + NVIC_SetPriority(TIM16_IRQn, 0); + + // TIM14: Comm timeout + TIM14->PSC = (uint16_t)(100); // 48M/100/65535 = ~7.32Hz (137ms) + TIM14->ARR = (uint16_t)(0xFFFF); + TIM14->CCMR1 = 0; + TIM14->CCER = 0; + TIM14->DIER |= TIM_DIER_UIE; // Update interrupt enable + TIM14->CR1 |= TIM_CR1_CEN; // Enable timer + TIM14->EGR |= TIM_EGR_UG; + + NVIC_EnableIRQ(TIM14_IRQn); + NVIC_SetPriority(TIM14_IRQn, 1); + + // TIM3: Red LED PWM + TIM3->ARR = (uint16_t)(0xFFFF); + TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; // PWM mode 2 + TIM3->CCER = TIM_CCER_CC1E; + TIM3->CCR1 = 0x1000; + TIM3->CR1 |= TIM_CR1_CEN; // Enable timer + TIM3->EGR |= TIM_EGR_UG; + + ADC1->CFGR1 = 0; + ADC1->SMPR = ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0; + ADC1->CHSELR = ADC_CHSELR_CHSEL5; + + // ADC step = 3.3/(2^12-1) = ~806uV + // USB: 5V + // Batt full charge: 4.2V + // 5/2 = 2.5V -> v = ~3102 + // 4.2/2 = 2.1V -> v = ~2605 + // (3102+2605)/2 = 2854 + + if (adc_read() < 2700) { + uint32_t remote_frame_count = userdata.entry_count; + uint32_t remote_frame_index = 0; + + remote_mode = 1; + + for (;;) { + //HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_6); // Battery mode + /*RED_LED_MAX + for (uint32_t c = 0; c < 1000000; c++) {}; + RED_LED_OFF + for (uint32_t c = 0; c < 1000000; c++) {};*/ + + /*if (userdata.entries[1].frame_data[0] == 0x85) { + for (;;) { RED_LED_OFF }; + }*/ + + ram_frame_size = userdata.entries[remote_frame_index].frame_size; + ram_frame_repeats = userdata.entries[remote_frame_index].repeats; + ram_frame_repeat_delay = userdata.entries[remote_frame_index].delay; + for (uint32_t c = 0; c < ram_frame_size; c++) + ram_frame_data[c] = userdata.entries[remote_frame_index].frame_data[c]; + + IRTX(ram_frame_data, ram_frame_size, ram_frame_repeats); + + while (SendOperationReady) {}; + + remote_frame_index++; + if (remote_frame_index >= remote_frame_count) remote_frame_index = 0; + } + } + + // Main loop + while (1) { + + if (comm_reset_flag) { + comm_reset_flag = 0; + comm_state = STATE_IDLE; + if (!SendOperationReady) RED_LED_NORMAL // Update LED + //HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_6); // DEBUG + } + + while (RX_FIFO.head != RX_FIFO.tail) { + TIM14->CNT = (uint16_t)0; // Reset comm. timeout + + // Process one byte from the RX FIFO + uint8_t byte = RX_FIFO.data[RX_FIFO.tail]; + + if (comm_state == STATE_IDLE) { + if (byte == 'L') { + // Load new frame data + comm_state = STATE_GET_FRAME_SIZE; + } else if (byte == 'T') { + // Transmit loaded frame + IRTX(ram_frame_data, ram_frame_size, ram_frame_repeats); + } else if (byte == '?') { + // Reply ID + CDC_Transmit_FS((uint8_t*)"ESLBlasterB0", 12); + } else if (byte == 'W') { + flash_data_counter = 0; + comm_state = STATE_FLASH_LOAD; + } else if (byte == 'R') { + // Read flash + uint16_t buff; + uint16_t* ptr = (uint16_t*)0x8007C00; + for (uint32_t d = 0; d < (1024/4); d++) { + buff = *ptr; + while(CDC_Transmit_FS((uint8_t*)&buff, 2) != USBD_OK) {}; + ptr += 2; + } + } else if (byte == 'S') { + // E-Stop + // Stop burst + TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // OC1REF forced low + SendOperationReady = 0; + } + } else if (comm_state == STATE_GET_FRAME_SIZE) { + ram_frame_size = byte; + comm_state = STATE_GET_FRAME_REPEAT_DELAY; + } else if (comm_state == STATE_GET_FRAME_REPEAT_DELAY) { + ram_frame_repeat_delay = byte; + comm_state = STATE_GET_FRAME_REPEATS_LOW; + } else if (comm_state == STATE_GET_FRAME_REPEATS_LOW) { + ram_frame_repeats = byte; + comm_state = STATE_GET_FRAME_REPEATS_HIGH; + } else if (comm_state == STATE_GET_FRAME_REPEATS_HIGH) { + ram_frame_repeats |= ((uint32_t)byte << 8); + ram_frame_data_counter = 0; + comm_state = STATE_GET_FRAME_DATA; + } else if (comm_state == STATE_GET_FRAME_DATA) { + ram_frame_data[ram_frame_data_counter++] = byte; + if (ram_frame_data_counter == ram_frame_size) + comm_state = STATE_IDLE; + } else if (comm_state == STATE_FLASH_LOAD) { + flash_data_buffer[flash_data_counter++] = byte; + + if (!(flash_data_counter & 0x7F)) + CDC_OK + + if (flash_data_counter == 1024) { + // Write flash + // Unlock + while ((FLASH->SR & FLASH_SR_BSY) != 0) {} + if (FLASH->CR & FLASH_CR_LOCK) { + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } + // Main flash: 0x0800 0000 - 0x0800 7FFF + // 32 pages de 1kB + // Page #31: data + + // Erase + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = (uint32_t)0x8007C00; + FLASH->CR |= FLASH_CR_STRT; + while ((FLASH->SR & FLASH_SR_BSY) != 0) {} + if (FLASH->SR & FLASH_SR_EOP) + FLASH->SR = FLASH_SR_EOP; + else + CDC_NOK + FLASH->CR &= ~FLASH_CR_PER; + + // Program halfword + FLASH->CR |= FLASH_CR_PG; + __IO uint16_t* ptr = (uint16_t*)0x8007C00; + uint16_t* src = (uint16_t*)flash_data_buffer; + for (uint32_t d = 0; d < 1024; d += 2) { + *ptr++ = *src++; + } + while (FLASH->SR & FLASH_SR_BSY) {} + if (FLASH->SR & FLASH_SR_EOP) + FLASH->SR = FLASH_SR_EOP; + else + CDC_NOK + FLASH->CR &= ~FLASH_CR_PG; + + CDC_OK + RED_LED_MAX + + comm_state = STATE_IDLE; + } + } + + RX_FIFO.tail = FIFO_INCR(RX_FIFO.tail); + } + } +} + +void SystemClock_Config(void) { + LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); // 1ws + + if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1) + Error_Handler(); + + LL_RCC_HSE_Enable(); + + // Wait for HSE ready + while (LL_RCC_HSE_IsReady() != 1) {}; + + // 4 * 12 = 48MHz + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1); + LL_RCC_PLL_Enable(); + + // Wait for PLL ready + while (LL_RCC_PLL_IsReady() != 1) {}; + + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + // Wait for System clock ready + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}; + + LL_Init1msTick(48000000); + LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK); + LL_SetSystemCoreClock(48000000); + LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL); +} + +void Error_Handler(void) { + /* User can add his own implementation to report the HAL error return state */ +} diff --git a/hardware/esl_blaster/FW/Src/stm32f0xx_hal_msp.c b/hardware/esl_blaster/FW01/Src/stm32f0xx_hal_msp.c similarity index 96% rename from hardware/esl_blaster/FW/Src/stm32f0xx_hal_msp.c rename to hardware/esl_blaster/FW01/Src/stm32f0xx_hal_msp.c index 18d15aa..f9ff1de 100644 --- a/hardware/esl_blaster/FW/Src/stm32f0xx_hal_msp.c +++ b/hardware/esl_blaster/FW01/Src/stm32f0xx_hal_msp.c @@ -1,86 +1,86 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : stm32f0xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - /* System interrupt init*/ - - __HAL_REMAP_PIN_ENABLE(HAL_REMAP_PA11_PA12); - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + __HAL_REMAP_PIN_ENABLE(HAL_REMAP_PA11_PA12); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Src/stm32f0xx_it.c b/hardware/esl_blaster/FW01/Src/stm32f0xx_it.c similarity index 96% rename from hardware/esl_blaster/FW/Src/stm32f0xx_it.c rename to hardware/esl_blaster/FW01/Src/stm32f0xx_it.c index 46721a1..2d5562c 100644 --- a/hardware/esl_blaster/FW/Src/stm32f0xx_it.c +++ b/hardware/esl_blaster/FW01/Src/stm32f0xx_it.c @@ -1,159 +1,159 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f0xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32f0xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern PCD_HandleTypeDef hpcd_USB_FS; -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex-M0 Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVC_IRQn 0 */ - - /* USER CODE END SVC_IRQn 0 */ - /* USER CODE BEGIN SVC_IRQn 1 */ - - /* USER CODE END SVC_IRQn 1 */ -} - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F0xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f0xx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles USB global Interrupt / USB wake-up interrupt through EXTI line 18. - */ -void USB_IRQHandler(void) -{ - /* USER CODE BEGIN USB_IRQn 0 */ - - /* USER CODE END USB_IRQn 0 */ - HAL_PCD_IRQHandler(&hpcd_USB_FS); - /* USER CODE BEGIN USB_IRQn 1 */ - - /* USER CODE END USB_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern PCD_HandleTypeDef hpcd_USB_FS; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB global Interrupt / USB wake-up interrupt through EXTI line 18. + */ +void USB_IRQHandler(void) +{ + /* USER CODE BEGIN USB_IRQn 0 */ + + /* USER CODE END USB_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_FS); + /* USER CODE BEGIN USB_IRQn 1 */ + + /* USER CODE END USB_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Src/system_stm32f0xx.c b/hardware/esl_blaster/FW01/Src/system_stm32f0xx.c similarity index 97% rename from hardware/esl_blaster/FW/Src/system_stm32f0xx.c rename to hardware/esl_blaster/FW01/Src/system_stm32f0xx.c index 36b4652..410809c 100644 --- a/hardware/esl_blaster/FW/Src/system_stm32f0xx.c +++ b/hardware/esl_blaster/FW01/Src/system_stm32f0xx.c @@ -1,333 +1,333 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f0xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. This file configures the system clock as follows: - *============================================================================= - * Supported STM32F0xx device - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** @addtogroup STM32F0xx_System_Private_Includes - * @{ - */ - -#include "stm32f0xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI48_VALUE */ -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is - updated automatically. - */ -uint32_t SystemCoreClock = 8000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001U; - -#if defined (STM32F051x8) || defined (STM32F058x8) - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80CU; -#else - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80CU; -#endif /* STM32F051x8 or STM32F058x8 */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFFU; - - /* Reset PREDIV[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; - -#if defined (STM32F072xB) || defined (STM32F078xx) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; -#elif defined (STM32F071xB) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; -#elif defined (STM32F091xC) || defined (STM32F098xx) - /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; -#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) - /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; -#elif defined (STM32F051x8) || defined (STM32F058xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; -#elif defined (STM32F042x6) || defined (STM32F048xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; -#elif defined (STM32F070x6) || defined (STM32F070xB) - /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; - /* Set default USB clock to PLLCLK, since there is no HSI48 */ - RCC->CFGR3 |= (uint32_t)0x00000080U; -#else - #warning "No target selected" -#endif - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFEU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ - SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ - || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ - || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ - SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || - STM32F091xC || STM32F098xx || STM32F030xC */ - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F0xx device + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001U; + +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80CU; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80CU; +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFFU; + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; + +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080U; +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFEU; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000U; + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW/Src/usb_device.c b/hardware/esl_blaster/FW01/Src/usb_device.c similarity index 96% rename from hardware/esl_blaster/FW/Src/usb_device.c rename to hardware/esl_blaster/FW01/Src/usb_device.c index 1dfb829..a787ae8 100644 --- a/hardware/esl_blaster/FW/Src/usb_device.c +++ b/hardware/esl_blaster/FW01/Src/usb_device.c @@ -1,101 +1,101 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usb_device.c - * @version : v2.0_Cube - * @brief : This file implements the USB Device - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usb_device.h" -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_cdc.h" -#include "usbd_cdc_if.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* USB Device Core handle declaration. */ -USBD_HandleTypeDef hUsbDeviceFS; - -/* - * -- Insert your variables declaration here -- - */ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* - * -- Insert your external function declaration here -- - */ -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * Init USB device Library, add supported class and start the library - * @retval None - */ -void MX_USB_DEVICE_Init(void) -{ - /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ - - /* USER CODE END USB_DEVICE_Init_PreTreatment */ - - /* Init Device Library, add supported class and start the library. */ - if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) - { - Error_Handler(); - } - if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) - { - Error_Handler(); - } - if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) - { - Error_Handler(); - } - if (USBD_Start(&hUsbDeviceFS) != USBD_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ - - /* USER CODE END USB_DEVICE_Init_PostTreatment */ -} - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.c + * @version : v2.0_Cube + * @brief : This file implements the USB Device + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_device.h" +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_cdc.h" +#include "usbd_cdc_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USB Device Core handle declaration. */ +USBD_HandleTypeDef hUsbDeviceFS; + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ +void MX_USB_DEVICE_Init(void) +{ + /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + + /* USER CODE END USB_DEVICE_Init_PreTreatment */ + + /* Init Device Library, add supported class and start the library. */ + if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) + { + Error_Handler(); + } + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) + { + Error_Handler(); + } + if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) + { + Error_Handler(); + } + if (USBD_Start(&hUsbDeviceFS) != USBD_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + + /* USER CODE END USB_DEVICE_Init_PostTreatment */ +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Src/usbd_cdc_if.c b/hardware/esl_blaster/FW01/Src/usbd_cdc_if.c similarity index 97% rename from hardware/esl_blaster/FW/Src/usbd_cdc_if.c rename to hardware/esl_blaster/FW01/Src/usbd_cdc_if.c index abbdd69..23e5ac9 100644 --- a/hardware/esl_blaster/FW/Src/usbd_cdc_if.c +++ b/hardware/esl_blaster/FW01/Src/usbd_cdc_if.c @@ -1,184 +1,184 @@ -/** - ****************************************************************************** - * @file : usbd_cdc_if.c - * @version : v2.0_Cube - * @brief : Usb device for Virtual Com Port. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#include "usbd_cdc_if.h" - -/* Define size for the receive and transmit buffer over CDC */ -/* It's up to user to redefine and/or remove those define */ -#define APP_RX_DATA_SIZE 256 -#define APP_TX_DATA_SIZE 256 - -/* Create buffer for reception and transmission */ -/* It's up to user to redefine and/or remove those define */ -/** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; - -/** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; - -extern USBD_HandleTypeDef hUsbDeviceFS; - -static int8_t CDC_Init_FS(void); -static int8_t CDC_DeInit_FS(void); -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); - -USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = { - CDC_Init_FS, - CDC_DeInit_FS, - CDC_Control_FS, - CDC_Receive_FS -}; - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief Initializes the CDC media low layer over the FS USB IP - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Init_FS(void) { - /* Set Application Buffers */ - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); - return (USBD_OK); -} - -/** - * @brief DeInitializes the CDC media low layer - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_DeInit_FS(void) { - return (USBD_OK); -} - -/** - * @brief Manage the CDC class requests - * @param cmd: Command code - * @param pbuf: Buffer containing command data (request parameters) - * @param length: Number of data to be sent (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { - // Since this is not an actual COM port, absolutely no fucks are given about control requests - switch(cmd) { - case CDC_SEND_ENCAPSULATED_COMMAND: - break; - - case CDC_GET_ENCAPSULATED_RESPONSE: - break; - - case CDC_SET_COMM_FEATURE: - break; - - case CDC_GET_COMM_FEATURE: - break; - - case CDC_CLEAR_COMM_FEATURE: - break; - - /*******************************************************************************/ - /* Line Coding Structure */ - /*-----------------------------------------------------------------------------*/ - /* Offset | Field | Size | Value | Description */ - /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ - /* 4 | bCharFormat | 1 | Number | Stop bits */ - /* 0 - 1 Stop bit */ - /* 1 - 1.5 Stop bits */ - /* 2 - 2 Stop bits */ - /* 5 | bParityType | 1 | Number | Parity */ - /* 0 - None */ - /* 1 - Odd */ - /* 2 - Even */ - /* 3 - Mark */ - /* 4 - Space */ - /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ - /*******************************************************************************/ - case CDC_SET_LINE_CODING: - break; - - case CDC_GET_LINE_CODING: - break; - - case CDC_SET_CONTROL_LINE_STATE: - break; - - case CDC_SEND_BREAK: - break; - - default: - break; - } - - return (USBD_OK); -} - -/** - * @brief Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { - uint32_t len = *Len; - - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); - USBD_CDC_ReceivePacket(&hUsbDeviceFS); - - // Add data to FIFO - while (len--) { - if (FIFO_INCR(RX_FIFO.head) == RX_FIFO.tail) { - return USBD_FAIL; // Overrun - } else { - RX_FIFO.data[RX_FIFO.head] = *Buf++; - RX_FIFO.head = FIFO_INCR(RX_FIFO.head); - } - } - - return (USBD_OK); -} - -/** - * @brief CDC_Transmit_FS - * Data to send over USB IN endpoint are sent over CDC interface - * through this function. - * @note - * - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY - */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { - uint8_t result = USBD_OK; - - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; - if (hcdc->TxState != 0) - return USBD_BUSY; - - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); - result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); - - return result; -} +/** + ****************************************************************************** + * @file : usbd_cdc_if.c + * @version : v2.0_Cube + * @brief : Usb device for Virtual Com Port. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#include "usbd_cdc_if.h" + +/* Define size for the receive and transmit buffer over CDC */ +/* It's up to user to redefine and/or remove those define */ +#define APP_RX_DATA_SIZE 256 +#define APP_TX_DATA_SIZE 256 + +/* Create buffer for reception and transmission */ +/* It's up to user to redefine and/or remove those define */ +/** Received data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; + +/** Data to send over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; + +extern USBD_HandleTypeDef hUsbDeviceFS; + +static int8_t CDC_Init_FS(void); +static int8_t CDC_DeInit_FS(void); +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = { + CDC_Init_FS, + CDC_DeInit_FS, + CDC_Control_FS, + CDC_Receive_FS +}; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) { + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + return (USBD_OK); +} + +/** + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) { + return (USBD_OK); +} + +/** + * @brief Manage the CDC class requests + * @param cmd: Command code + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { + // Since this is not an actual COM port, absolutely no fucks are given about control requests + switch(cmd) { + case CDC_SEND_ENCAPSULATED_COMMAND: + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + break; + + case CDC_SET_COMM_FEATURE: + break; + + case CDC_GET_COMM_FEATURE: + break; + + case CDC_CLEAR_COMM_FEATURE: + break; + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + case CDC_SET_LINE_CODING: + break; + + case CDC_GET_LINE_CODING: + break; + + case CDC_SET_CONTROL_LINE_STATE: + break; + + case CDC_SEND_BREAK: + break; + + default: + break; + } + + return (USBD_OK); +} + +/** + * @brief Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * untill exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { + uint32_t len = *Len; + + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + + // Add data to FIFO + while (len--) { + if (FIFO_INCR(RX_FIFO.head) == RX_FIFO.tail) { + return USBD_FAIL; // Overrun + } else { + RX_FIFO.data[RX_FIFO.head] = *Buf++; + RX_FIFO.head = FIFO_INCR(RX_FIFO.head); + } + } + + return (USBD_OK); +} + +/** + * @brief CDC_Transmit_FS + * Data to send over USB IN endpoint are sent over CDC interface + * through this function. + * @note + * + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { + uint8_t result = USBD_OK; + + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + if (hcdc->TxState != 0) + return USBD_BUSY; + + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + + return result; +} diff --git a/hardware/esl_blaster/FW/Src/usbd_conf.c b/hardware/esl_blaster/FW01/Src/usbd_conf.c similarity index 96% rename from hardware/esl_blaster/FW/Src/usbd_conf.c rename to hardware/esl_blaster/FW01/Src/usbd_conf.c index 442383c..0f66dd0 100644 --- a/hardware/esl_blaster/FW/Src/usbd_conf.c +++ b/hardware/esl_blaster/FW01/Src/usbd_conf.c @@ -1,650 +1,650 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usbd_conf.c - * @version : v2.0_Cube - * @brief : This file implements the board support package for the USB device library - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" -#include "stm32f0xx_hal.h" -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_cdc.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -PCD_HandleTypeDef hpcd_USB_FS; -void Error_Handler(void); - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* Private functions ---------------------------------------------------------*/ -static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status); -/* USER CODE BEGIN 1 */ -static void SystemClockConfig_Resume(void); -/* USER CODE END 1 */ -extern void SystemClock_Config(void); - -/******************************************************************************* - LL Driver Callbacks (PCD -> USB Device Library) -*******************************************************************************/ -/* MSP Init */ - -void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) -{ - if(pcdHandle->Instance==USB) - { - /* USER CODE BEGIN USB_MspInit 0 */ - - /* USER CODE END USB_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USB_CLK_ENABLE(); - - /* Peripheral interrupt init */ - HAL_NVIC_SetPriority(USB_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(USB_IRQn); - /* USER CODE BEGIN USB_MspInit 1 */ - - /* USER CODE END USB_MspInit 1 */ - } -} - -void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) -{ - if(pcdHandle->Instance==USB) - { - /* USER CODE BEGIN USB_MspDeInit 0 */ - - /* USER CODE END USB_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USB_CLK_DISABLE(); - - /* Peripheral interrupt Deinit*/ - HAL_NVIC_DisableIRQ(USB_IRQn); - - /* USER CODE BEGIN USB_MspDeInit 1 */ - - /* USER CODE END USB_MspDeInit 1 */ - } -} - -/** - * @brief Setup stage callback - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); -} - -/** - * @brief Data Out stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#else -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); -} - -/** - * @brief Data In stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#else -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); -} - -/** - * @brief SOF callback. - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Reset callback. - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_SpeedTypeDef speed = USBD_SPEED_FULL; - - if ( hpcd->Init.speed != PCD_SPEED_FULL) - { - Error_Handler(); - } - /* Set Speed. */ - USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); - - /* Reset Device. */ - USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Suspend callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - /* Inform USB library that core enters in suspend Mode. */ - USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); - /* Enter in STOP mode. */ - /* USER CODE BEGIN 2 */ - if (hpcd->Init.low_power_enable) - { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ - SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - /* USER CODE END 2 */ -} - -/** - * @brief Resume callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - /* USER CODE BEGIN 3 */ - if (hpcd->Init.low_power_enable) - { - /* Reset SLEEPDEEP bit of Cortex System Control Register. */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - SystemClockConfig_Resume(); - } - /* USER CODE END 3 */ - USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief ISOOUTIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#else -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief ISOINIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#else -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief Connect callback. - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Disconnect callback. - * @param hpcd: PCD handle - * @retval None - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -#else -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/******************************************************************************* - LL Driver Interface (USB Device Library --> PCD) -*******************************************************************************/ - -/** - * @brief Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) -{ - /* Init USB Ip. */ - /* Link the driver to the stack. */ - hpcd_USB_FS.pData = pdev; - pdev->pData = &hpcd_USB_FS; - - hpcd_USB_FS.Instance = USB; - hpcd_USB_FS.Init.dev_endpoints = 8; - hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; - hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - hpcd_USB_FS.Init.low_power_enable = DISABLE; - hpcd_USB_FS.Init.lpm_enable = DISABLE; - hpcd_USB_FS.Init.battery_charging_enable = DISABLE; - if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) - { - Error_Handler( ); - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - /* Register USB PCD CallBacks */ - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback); - HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback); - - HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback); - HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); - HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); - HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - /* USER CODE BEGIN EndPoint_Configuration */ - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); - /* USER CODE END EndPoint_Configuration */ - /* USER CODE BEGIN EndPoint_Configuration_CDC */ - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); - /* USER CODE END EndPoint_Configuration_CDC */ - return USBD_OK; -} - -/** - * @brief De-Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_DeInit(pdev->pData); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Starts the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Start(pdev->pData); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Stops the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Stop(pdev->pData); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Opens an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param ep_type: Endpoint type - * @param ep_mps: Endpoint max packet size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Closes an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Flushes an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Sets a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Clears a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Returns Stall condition. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Stall (1: Yes, 0: No) - */ -uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - - if((ep_addr & 0x80) == 0x80) - { - return hpcd->IN_ep[ep_addr & 0x7F].is_stall; - } - else - { - return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; - } -} - -/** - * @brief Assigns a USB address to the device. - * @param pdev: Device handle - * @param dev_addr: Device address - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Transmits data over an endpoint. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be sent - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Prepares an endpoint for reception. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be received - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; -} - -/** - * @brief Returns the last transfered packet size. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Recived Data Size - */ -uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); -} - -/** - * @brief Delays routine for the USB device library. - * @param Delay: Delay in ms - * @retval None - */ -void USBD_LL_Delay(uint32_t Delay) -{ - HAL_Delay(Delay); -} - -/** - * @brief Static single allocation. - * @param size: Size of allocated memory - * @retval None - */ -void *USBD_static_malloc(uint32_t size) -{ - static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ - return mem; -} - -/** - * @brief Dummy memory free - * @param p: Pointer to allocated memory address - * @retval None - */ -void USBD_static_free(void *p) -{ - -} - -/* USER CODE BEGIN 5 */ -/** - * @brief Configures system clock after wake-up from USB Resume CallBack: - * enable HSI, PLL and select PLL as system clock source. - * @retval None - */ -static void SystemClockConfig_Resume(void) -{ - SystemClock_Config(); -} -/* USER CODE END 5 */ - -/** - * @brief Retuns the USB status depending on the HAL status: - * @param hal_status: HAL status - * @retval USB status - */ -USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) -{ - USBD_StatusTypeDef usb_status = USBD_OK; - - switch (hal_status) - { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.c + * @version : v2.0_Cube + * @brief : This file implements the board support package for the USB device library + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" +#include "usbd_def.h" +#include "usbd_core.h" +#include "usbd_cdc.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +PCD_HandleTypeDef hpcd_USB_FS; +void Error_Handler(void); + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* Private functions ---------------------------------------------------------*/ +static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status); +/* USER CODE BEGIN 1 */ +static void SystemClockConfig_Resume(void); +/* USER CODE END 1 */ +extern void SystemClock_Config(void); + +/******************************************************************************* + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB) + { + /* USER CODE BEGIN USB_MspInit 0 */ + + /* USER CODE END USB_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(USB_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_IRQn); + /* USER CODE BEGIN USB_MspInit 1 */ + + /* USER CODE END USB_MspInit 1 */ + } +} + +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB) + { + /* USER CODE BEGIN USB_MspDeInit 0 */ + + /* USER CODE END USB_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_CLK_DISABLE(); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(USB_IRQn); + + /* USER CODE BEGIN USB_MspDeInit 1 */ + + /* USER CODE END USB_MspDeInit 1 */ + } +} + +/** + * @brief Setup stage callback + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); +} + +/** + * @brief Data Out stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); +} + +/** + * @brief Data In stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); +} + +/** + * @brief SOF callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + if ( hpcd->Init.speed != PCD_SPEED_FULL) + { + Error_Handler(); + } + /* Set Speed. */ + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + + /* Reset Device. */ + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Suspend callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* Inform USB library that core enters in suspend Mode. */ + USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + /* Enter in STOP mode. */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + /* USER CODE END 2 */ +} + +/** + * @brief Resume callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* USER CODE BEGIN 3 */ + if (hpcd->Init.low_power_enable) + { + /* Reset SLEEPDEEP bit of Cortex System Control Register. */ + SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + SystemClockConfig_Resume(); + } + /* USER CODE END 3 */ + USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief ISOOUTIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief ISOINIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief Connect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Disconnect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/******************************************************************************* + LL Driver Interface (USB Device Library --> PCD) +*******************************************************************************/ + +/** + * @brief Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + /* Init USB Ip. */ + /* Link the driver to the stack. */ + hpcd_USB_FS.pData = pdev; + pdev->pData = &hpcd_USB_FS; + + hpcd_USB_FS.Instance = USB; + hpcd_USB_FS.Init.dev_endpoints = 8; + hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_FS.Init.low_power_enable = DISABLE; + hpcd_USB_FS.Init.lpm_enable = DISABLE; + hpcd_USB_FS.Init.battery_charging_enable = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) + { + Error_Handler( ); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + /* Register USB PCD CallBacks */ + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback); + + HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback); + HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); + HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); + HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /* USER CODE BEGIN EndPoint_Configuration */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); + /* USER CODE END EndPoint_Configuration */ + /* USER CODE BEGIN EndPoint_Configuration_CDC */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); + /* USER CODE END EndPoint_Configuration_CDC */ + return USBD_OK; +} + +/** + * @brief De-Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_DeInit(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Starts the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Start(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Stops the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Stop(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Opens an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Closes an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + + if((ep_addr & 0x80) == 0x80) + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + } +} + +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param dev_addr: Device address + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns the last transfered packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); +} + +/** + * @brief Delays routine for the USB device library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/** + * @brief Static single allocation. + * @param size: Size of allocated memory + * @retval None + */ +void *USBD_static_malloc(uint32_t size) +{ + static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + return mem; +} + +/** + * @brief Dummy memory free + * @param p: Pointer to allocated memory address + * @retval None + */ +void USBD_static_free(void *p) +{ + +} + +/* USER CODE BEGIN 5 */ +/** + * @brief Configures system clock after wake-up from USB Resume CallBack: + * enable HSI, PLL and select PLL as system clock source. + * @retval None + */ +static void SystemClockConfig_Resume(void) +{ + SystemClock_Config(); +} +/* USER CODE END 5 */ + +/** + * @brief Retuns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + USBD_StatusTypeDef usb_status = USBD_OK; + + switch (hal_status) + { + case HAL_OK : + usb_status = USBD_OK; + break; + case HAL_ERROR : + usb_status = USBD_FAIL; + break; + case HAL_BUSY : + usb_status = USBD_BUSY; + break; + case HAL_TIMEOUT : + usb_status = USBD_FAIL; + break; + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW/Src/usbd_desc.c b/hardware/esl_blaster/FW01/Src/usbd_desc.c similarity index 97% rename from hardware/esl_blaster/FW/Src/usbd_desc.c rename to hardware/esl_blaster/FW01/Src/usbd_desc.c index ba86aef..10267e2 100644 --- a/hardware/esl_blaster/FW/Src/usbd_desc.c +++ b/hardware/esl_blaster/FW01/Src/usbd_desc.c @@ -1,268 +1,268 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : usbd_desc.c - * @version : v2.0_Cube - * @brief : This file implements the USB device descriptors. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_conf.h" - -#define USBD_VID 1155 -#define USBD_PID_FS 22336 -#define USBD_LANGID_STRING 1033 - -//#define USBD_MANUFACTURER_STRING "Furrtek engineering" -// USB uses UTF-16LE -// unicode[idx++] = *len; -// unicode[idx++] = USB_DESC_TYPE_STRING; -static const uint8_t USBD_MANUFACTURER_STRING_DATA[] = { - "\x28\x03" "F\0u\0r\0r\0t\0e\0k\0 \0e\0n\0g\0i\0n\0e\0e\0r\0i\0n\0g\0" -}; - -//#define USBD_PRODUCT_STRING_FS "ESL Blaster Rev. B" -static const uint8_t USBD_PRODUCT_STRING_DATA[] = { - "\x26\x03" "E\0S\0L\0 \0B\0l\0a\0s\0t\0e\0r\0 \0R\0e\0v\0.\0 \0B\0" -}; - -//#define USBD_CONFIGURATION_STRING_F "CDC Config" -static const uint8_t USBD_CONFIGURATION_STRING_DATA[] = { - "\x16\x03" "C\0D\0C\0 \0C\0o\0n\0f\0i\0g\0" -}; - -//#define USBD_INTERFACE_STRING_FS "CDC Interface" -static const uint8_t USBD_INTERFACE_STRING_DATA[] = { - "\x1C\x03" "C\0D\0C\0 \0I\0n\0t\0e\0r\0f\0a\0c\0e\0" -}; - -static void Get_SerialNum(void); -static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); - -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); - -#ifdef USBD_SUPPORT_USER_STRING_DESC -uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); -#endif /* USBD_SUPPORT_USER_STRING_DESC */ - -USBD_DescriptorsTypeDef FS_Desc = { - USBD_FS_DeviceDescriptor, - USBD_FS_LangIDStrDescriptor, - USBD_FS_ManufacturerStrDescriptor, - USBD_FS_ProductStrDescriptor, - USBD_FS_SerialStrDescriptor, - USBD_FS_ConfigStrDescriptor, - USBD_FS_InterfaceStrDescriptor -}; - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -/** USB standard device descriptor. */ -__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { - 0x12, /*bLength */ - USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ - 0x00, /*bcdUSB */ - 0x02, - 0x02, /*bDeviceClass*/ - 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID_FS), /*idProduct*/ - HIBYTE(USBD_PID_FS), /*idProduct*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ -}; - -/** USB lang indentifier descriptor. */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { - USB_LEN_LANGID_STR_DESC, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING) -}; - -/* -// Internal string descriptor. -__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; -*/ - -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 -#endif -__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { - USB_SIZ_STRING_SERIAL, - USB_DESC_TYPE_STRING, -}; - -/** - * @brief Return the device descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - *length = sizeof(USBD_FS_DeviceDesc); - return USBD_FS_DeviceDesc; -} - -/** - * @brief Return the LangID string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - -/** - * @brief Return the product string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - //if (speed == 0) - // USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - //else - //USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - //return USBD_StrDesc; - - *length = sizeof(USBD_PRODUCT_STRING_DATA); //38 - return (uint8_t*)USBD_PRODUCT_STRING_DATA; -} - -/** - * @brief Return the manufacturer string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - //USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - //return USBD_StrDesc; - - *length = sizeof(USBD_MANUFACTURER_STRING_DATA); //40 - return (uint8_t*)USBD_MANUFACTURER_STRING_DATA; -} - -/** - * @brief Return the serial number string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - *length = USB_SIZ_STRING_SERIAL; - - Get_SerialNum(); - - return (uint8_t *) USBD_StringSerial; -} - -/** - * @brief Return the configuration string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - //if (speed == USBD_SPEED_HIGH) - // USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - //else - //USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - //return USBD_StrDesc; - - *length = sizeof(USBD_CONFIGURATION_STRING_DATA); //22 - return (uint8_t*)USBD_CONFIGURATION_STRING_DATA; -} - -/** - * @brief Return the interface string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - //if (speed == 0) - // USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - //else - //USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - //return USBD_StrDesc; - - *length = sizeof(USBD_INTERFACE_STRING_DATA); //28 - return (uint8_t*)USBD_INTERFACE_STRING_DATA; -} - -/** - * @brief Create the serial number string descriptor - * @param None - * @retval None - */ -static void Get_SerialNum(void) { - uint32_t deviceserial0, deviceserial1, deviceserial2; - - deviceserial0 = *(uint32_t *) DEVICE_ID1; - deviceserial1 = *(uint32_t *) DEVICE_ID2; - deviceserial2 = *(uint32_t *) DEVICE_ID3; - - deviceserial0 += deviceserial2; - - if (deviceserial0 != 0) { - IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); - IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); - } -} - -/** - * @brief Convert Hex 32Bits value into char - * @param value: value to convert - * @param pbuf: pointer to the buffer - * @param len: buffer length - * @retval None - */ -static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { - uint32_t idx = 0, temp; - - for (idx = 0; idx < (len << 1); idx += 2) { - temp = value >> 28; - - if (temp < 10) - pbuf[idx] = temp + '0'; - else - pbuf[idx] = temp + 'A' - 10; - - pbuf[idx + 1] = 0; - - value = value << 4; - } -} +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v2.0_Cube + * @brief : This file implements the USB device descriptors. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_conf.h" + +#define USBD_VID 1155 +#define USBD_PID_FS 22336 +#define USBD_LANGID_STRING 1033 + +//#define USBD_MANUFACTURER_STRING "Furrtek engineering" +// USB uses UTF-16LE +// unicode[idx++] = *len; +// unicode[idx++] = USB_DESC_TYPE_STRING; +static const uint8_t USBD_MANUFACTURER_STRING_DATA[] = { + "\x28\x03" "F\0u\0r\0r\0t\0e\0k\0 \0e\0n\0g\0i\0n\0e\0e\0r\0i\0n\0g\0" +}; + +//#define USBD_PRODUCT_STRING_FS "ESL Blaster Rev. B" +static const uint8_t USBD_PRODUCT_STRING_DATA[] = { + "\x26\x03" "E\0S\0L\0 \0B\0l\0a\0s\0t\0e\0r\0 \0R\0e\0v\0.\0 \0B\0" +}; + +//#define USBD_CONFIGURATION_STRING_F "CDC Config" +static const uint8_t USBD_CONFIGURATION_STRING_DATA[] = { + "\x16\x03" "C\0D\0C\0 \0C\0o\0n\0f\0i\0g\0" +}; + +//#define USBD_INTERFACE_STRING_FS "CDC Interface" +static const uint8_t USBD_INTERFACE_STRING_DATA[] = { + "\x1C\x03" "C\0D\0C\0 \0I\0n\0t\0e\0r\0f\0a\0c\0e\0" +}; + +static void Get_SerialNum(void); +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); + +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + +#ifdef USBD_SUPPORT_USER_STRING_DESC +uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +USBD_DescriptorsTypeDef FS_Desc = { + USBD_FS_DeviceDescriptor, + USBD_FS_LangIDStrDescriptor, + USBD_FS_ManufacturerStrDescriptor, + USBD_FS_ProductStrDescriptor, + USBD_FS_SerialStrDescriptor, + USBD_FS_ConfigStrDescriptor, + USBD_FS_InterfaceStrDescriptor +}; + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/** USB standard device descriptor. */ +__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { + 0x12, /*bLength */ + USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ + 0x00, /*bcdUSB */ + 0x02, + 0x02, /*bDeviceClass*/ + 0x02, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID_FS), /*idProduct*/ + HIBYTE(USBD_PID_FS), /*idProduct*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ +}; + +/** USB lang indentifier descriptor. */ +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING) +}; + +/* +// Internal string descriptor. +__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; +*/ + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { + USB_SIZ_STRING_SERIAL, + USB_DESC_TYPE_STRING, +}; + +/** + * @brief Return the device descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = sizeof(USBD_FS_DeviceDesc); + return USBD_FS_DeviceDesc; +} + +/** + * @brief Return the LangID string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = sizeof(USBD_LangIDDesc); + return USBD_LangIDDesc; +} + +/** + * @brief Return the product string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == 0) + // USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_PRODUCT_STRING_DATA); //38 + return (uint8_t*)USBD_PRODUCT_STRING_DATA; +} + +/** + * @brief Return the manufacturer string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_MANUFACTURER_STRING_DATA); //40 + return (uint8_t*)USBD_MANUFACTURER_STRING_DATA; +} + +/** + * @brief Return the serial number string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = USB_SIZ_STRING_SERIAL; + + Get_SerialNum(); + + return (uint8_t *) USBD_StringSerial; +} + +/** + * @brief Return the configuration string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == USBD_SPEED_HIGH) + // USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_CONFIGURATION_STRING_DATA); //22 + return (uint8_t*)USBD_CONFIGURATION_STRING_DATA; +} + +/** + * @brief Return the interface string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == 0) + // USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_INTERFACE_STRING_DATA); //28 + return (uint8_t*)USBD_INTERFACE_STRING_DATA; +} + +/** + * @brief Create the serial number string descriptor + * @param None + * @retval None + */ +static void Get_SerialNum(void) { + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t *) DEVICE_ID1; + deviceserial1 = *(uint32_t *) DEVICE_ID2; + deviceserial2 = *(uint32_t *) DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) { + IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); + IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + } +} + +/** + * @brief Convert Hex 32Bits value into char + * @param value: value to convert + * @param pbuf: pointer to the buffer + * @param len: buffer length + * @retval None + */ +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { + uint32_t idx = 0, temp; + + for (idx = 0; idx < (len << 1); idx += 2) { + temp = value >> 28; + + if (temp < 10) + pbuf[idx] = temp + '0'; + else + pbuf[idx] = temp + 'A' - 10; + + pbuf[idx + 1] = 0; + + value = value << 4; + } +} diff --git a/hardware/esl_blaster/FW/Startup/startup_stm32f070f6px.s b/hardware/esl_blaster/FW01/Startup/startup_stm32f070f6px.s similarity index 97% rename from hardware/esl_blaster/FW/Startup/startup_stm32f070f6px.s rename to hardware/esl_blaster/FW01/Startup/startup_stm32f070f6px.s index e5aa3b8..d1c1326 100644 --- a/hardware/esl_blaster/FW/Startup/startup_stm32f070f6px.s +++ b/hardware/esl_blaster/FW01/Startup/startup_stm32f070f6px.s @@ -1,307 +1,307 @@ -/** - ****************************************************************************** - * @file startup_stm32f070x6.s - * @author MCD Application Team - * @brief STM32F070x4/STM32F070x6 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/*Check if boot space corresponds to test memory*/ - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - BNE ApplicationStart - - /*SYSCFG clock enable*/ - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -/*Set CFGR1 register with flash memory remap at address 0*/ - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] - -ApplicationStart: -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* Reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word 0 /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word USB_IRQHandler /* USB */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USB_IRQHandler - .thumb_set USB_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file startup_stm32f070x6.s + * @author MCD Application Team + * @brief STM32F070x4/STM32F070x6 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* Reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW01/dfu-util-0.9-win64/README.txt b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/README.txt new file mode 100644 index 0000000..5aa2e67 --- /dev/null +++ b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/README.txt @@ -0,0 +1,26 @@ +dfu-util 0.9 + +These binaries are for Microsoft Windows 64-bit + +They were built using MinGW-64 from MSYS2 with gcc 5.3.0, +for build instructions please see: +http://dfu-util.sourceforge.net/build.html + +Source code: +https://sourceforge.net/p/dfu-util/dfu-util/ci/v0.9/tree/ + +dfu-util.exe requires libusb-1.0.dll. The shipped libusb-1.0.dll +is built from libusb 1.0.20 and can be replaced with another +version if desired. + +dfu-util-static.exe has the libusb 1.0.20 code embedded and runs +without any libusb-1.0.dll. + +Notes: +1. To work around a bug in gcc/mingw, a small patch was applied, see + https://sourceforge.net/p/dfu-util/tickets/13/ +2. The dfu-util-static.exe includes libusb that has been patched + to work around a silicon bug in STM32F42X devices: + https://github.com/axoloti/axoloti/blob/master/platform_osx/src/libusb.stdfu.patch + +2016-02-11 Tormod Volden diff --git a/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-prefix.exe b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-prefix.exe new file mode 100644 index 0000000000000000000000000000000000000000..5ae088804979feab4339592abc9c90e694d2b516 GIT binary patch literal 178765 zcmeEv30Pc3wtro?-85UeV*rT;Z6hS0fdBylS(FY9X_6)oAe%;^X&QoIOD|b8DzQP+ zwkWQn<1%sA(Q)FERgI9ukf@`GTioM1jp!Jc$;9Xk|KF)w7djZ7_ulv3_r3T1?eDwy z)H!wP)TyddrKE{$yzW(w zL~Ngl8>vWTM>&Fj)vT;Kt=8tYfp}EHtqd2*oP#Uqm(QxZ)0_(9q49{Q#&rrVGp?W? z`0~?Q6+T|ZHbhdHFAQQrFrTI8r>zz8D8DXT#8-nW=*RhLTrMJg8IIc~3jO@oM*1}< z@_1cu22T{Oy5o5vuRE=vyppIZ=+=#k@^|72`sK6y?lgBJ&zJM{A(Hs0LW6!vy||oq z(0JP(LV)U+Y%J(U`A*GJ2yIl(!?=iVy+Tv(`OGk9YDOMM7k)?pjdBR!3JQ<>IN!7k zPOzT=a0q-80c)rcM}C|yE1MIljQ|D|g814`z?VIp^X(r4kPkis-~*%i^5;yQp3eE! zY5>Z>N9EW$nh)j3RrJeQg7|9iEd_k$1blg!h+u594!3UbQD2Dx4Ej+yg3#ZB|BGv2 zkN$Lcg}OBT>Fr!gi}%Z9i(jLuWh|q=mkgQ#)dC$x!h?~Q(3yr~T52F_LvG1=?zKpC zH==y8_g=@CpLKM*m+T-b3Al0~vA1Ukzrdg4NqX!-B(wNJ5Za}NG>J&;H$ckyMDjDA zA+RcjLYkd6#=N}LeYJGG@{}2cHpW-Gm^saRy z*{NVM``ZFMU13KzB@E*U&7K69cG z{ITFS`*nc};0?M^%v`in8?s`iMW)I{OBPpHHhg(2W!=3a8o<(7iDbUFzOy`H@y|}? ziS>mjO~*4Kj5#cRIf>kW#h)+>wP*3S>N38v`je*JjY=D9$=j!I&jR0$KqxX8dfnm+ z9Jc5mpJwUk_IzydXU8K=##er=_o$?Ap9n_37UgYUg;1~N=}zwUK;zNzAa;DE$U`|w zswq1LN$#k^jP9L?Wf=#C`T{pm(|1NEoQ7#f?7f?aE4GW6eIbGP1RiJmCrsoT_~Af3 zDj&iOJYMtaEgZ`v45Ah37iJt7jMbmc+WXy8ydO#K$=oa~-fl_1)zEg#c-iMB-+q(# zu+(;JqDgPwKlo`KxBT{g&)C6JM(iJ~mq&_Zh&ycYX_g^Bvp)=N?2bEPPFyZ+C!eS9 z_y%{M=4lMnW`EM_*DzMt*_bGm*uN_7`7G4x8whNMt1RsJ)Z%*{jq(T>^w*vbW6gNi z;*a_;Fb}bo&Q{6d`zCNDg?;AtQJRAp!0nPX-0M)D^O>kfe{?K@KFv7XVI1vmK$t)F zpMGHdp2$Eqa`S7B0JUt`OV)M%g;f`rmYXivGg3eLZRW)40SydYsXv&<511}Ii*gAQ z==cEbw&Qf*fi)zM+eJqJL?{`}b&WoPB!LXXc6`;VC7aN9yaEQaANtr;p#!^t2>HHO zhhnGQ#n?a&(YhdG0EsRB=zf4+E#({dE5@#YOAud}@zuZ^{~8+d^#oj?b%9^;XR*jv zaZ`aA7%2l=ei|C;qK=h}j+Os&|MwXQhiI@y5P!!Af7fxpMHb&@!SzEp@-$k!v%6>t z=T3)}|85>x`2}}EZy3>3cz_#0K_d^vmI-1w*s76Ws1JdYkr28WFBs??gHWgD7S#9P z`=qIo--rqoJTrg7e#jYm4QbDZWNW9T+O$0$b+eP#56uC1AT?RbvBH>rFQW^`eomUhPCMsHmb`yj^m796888%&A*-*uq|>UCP>4wt7$bN}-`kleWw+Eb zsMBvfV45~zV{u-OXTan;3b)XUJo9=zk-me-G?^D+DE72F(5ZBRaiotwq3?D8-}BVE zu^UPdM$;Gj0)a+EbD~QSO}=j+G*Bt%Wz{>#iv?x@-vN_hfjJ0ubq$X%=r@HK{idg3 zc|*JC_8i^ne5J5nhS%BKMq-@fl2(08Px@56&cq7XxG^8R2!a3^bnmqO>b1jr5=UIGqEOM_0A zjDW8|2X_B_9opHnofs5Tt^(I=LVX1WeMb*Qvz>$y=Z4)pWbY3go5Dqr5Pkb+;DIRn zd;^yNd6v-mIz?u{0CD~bgS1(m1U;8fvOf=T=%q;fZ zXk^nuV4ZI1aOa#Kt({g$+DJ!><^&kJrbOx~ZM8;LAwsA%Dzf*7F#UBh+ME}}%p+oG+?@g%O_DxIaO={C3r zc|TW-x_B;y*TujO7#&eRQ$Ry!>MX0a_rUV2yzzAR#UoThc>A9*>M*|P==upaj7O7+J5joKC8Ou`*e2cjzidLbrTo}ai z?Id1$n$LnIU9c#9Vjqti$#j>%qtAzc(Z;et5p*RNl>OHmQLwwHqxlowMVJ?C_X(2C zQ<9Y;89BJ~;jg+z<}>Pi4uiPGAMSe#x;*=SCjvavET)wjFn3j+da6o^M)s&99oo>F`hIGBX0fM-x9gUbBN zUtq+#)xFkx6rOfG3hOU0oLvxa?WA>hFK) zTFi&+-GS>UIUciM>8bvxy3%=Pj1IpN0?Q ziZJI1oJR!O{~@zT#=3;a$$_(}uzvJ740eGcp2$kkntPBkkPQNt4Z>|isHH6UIwKv6 z8^7lJ1%$snWI%<1GE!c&ZeT7|658^nZvEEofAGc09#J4_eI$Ql3gylhObJ-h`Zarr z&{>AM%GX(Zv0Dhm_R=TR9(#iPlVU$G(@#oB0yYnZe0$s}9q+pJ%6jSGP|QB>pyWA% zD!z{NfPnKa9H>Q*`cuZcgCV{>ofTL%&UzCi=<|FtxI0L`UvtqVWQT6;cYNjFt62=3 z<{*RZR0PXVQpdHl5E8$PZnb0zLF~SHzs!dpzK%+eA8-yd~4y$ z2YNKhCOWgN1w%){Ud4O)5xPT9=7-GFI`~luX`O8 zw`-bEd~koz_<#oBI~c84=A(+2UyR-#`^7a7>Q9)9s={>I(z)m$*+%TUMDFOus!88| zFLkEQ!b4OGxzw}ZxGnxg2eG7wJz^K6Fu)BH>wX<%a@!q>y_*Zx{0$Uh%x*%USF`6b z#=>RR-K%*PA!;0yXg7i|q*HnM3J)V_RDwr`VrxiDXY?!R`a`iEAVaaQ_%X*IA$(c6 z5VSxmHl-~7!gvU~lvL;}gehuHLU3TM+9}C?y~je`CwKI_$0=JGWTC_MA9y+n59zo{ z+;UZW)r^}DKbITg*7mXxD2$oAdmQHR?)+iq^DpG>pD=JM<(>U8fxPeBA7V|6N_2;y zpLqA^K=OPQoF-6=90zxZ{om2{2z{5LDi%@YK**GD^@jGuHYnhuu205h@l_@!f2$u` znV63I^2A)+&58L#eKZs3$@PYNh9{{%z-Z+A%5Wai_{{!JxVF2%ba(sWc`1YgKg6n7haSXhE zaxHMZOUa9)u9sS2@6}e+{|dzuUys7TIB!5Uqi5cCVUxt-cf(ybawgP??;Y&_24WEr z=*DgI_!_i7v(#cw-LM`4DBm}&zFsUTul){<0()oz9eZ!yZa7?+)Qip-D;#ejF00f7 zTz|!8FnV{xO?JoUec{2N@pj;FB+^oM-m7o_gyeKKHZcn}vx|LSSwmCDLuRqB&|vB< zL?rY}kH*x2t3GD^97s*2B2i!Q0#XbxnQ^3Z%#CKmUVkSeh$0z z0oi-#M|WbeZ@?NF{S3HG+w(~bB;t_?cau*bA*?#ttN9&y>0(-&e@jCgELYu}9x$DX zvVJu%11&fdd-y6y=#0J-Dq`YyAzuh+sz^A*>JT#@F;>4hSr;%-WM}j#AfVO*nLxX` z7MT`P71I+I?gp#<3FDC(<4>%`_a*YAJqXiOe`M92k zsl)RhIvm)ETEcjCCUp{j!W052d*S1djDBP~=%bpafs+$Y!Ekys?6MnhkGyP>*?($b z$GiHDLgZlfSIC95H3{=~{sT!=t%O1IVbh1K^pwl*!Hl4(25VlBSHzQ7_{v?y6RAMk75S%)TiH{%GDyp~q= zP~gKWsXKUHviehBLU3?ATr511cOOi0PyEd62a!aNSvBNfAPLpn4%}~mSAO5(w_t~k zTb%D0J+6Y(_LHCvjLrkD5^UD^7X>W-l0LIvjyDaxG5GMX|K@c-O$`;gspUH_?c*gk zZI`+7$B;d$;G8JPrD-V^QK_Uw`q27pUUe`-}CKeoM;k zd7W~IiF704Dcu{Gy* zTRQrAHM_U)$f5pWnfYus_7J+=j@j51>GtF!In_(xNSvw?910&O*YOBahYtphpZ$}6+5HJ zgA&gbT%^Q*gf>&Cye7|8s4tQQiS^3x{L>hCJPbwgJ@40ST1{TklVs`m%56lW=9L5D%1h7^%v9 zZxyF}NspI(Zw;pH3kx^<>SYT$tG_IY`nj*-`%p~o;h$3i7H_Z4SMZas;;6;@FQYq? z9&mcJTnEqdmX0I(b{DF__bu=5cvb<8k09@%*!5RnAYMWhM_CSjO8SZCTVpZE`9pj? z8$Lp`al;P<1#^x1_E*5hO;vwYI|a#H^*DsTZ+9TfZCc;49zoTvPZOft z7T(Qlh!S=^Fb!dPo+>)f_v4fjd#($z$`3&thydfr{3ggIdnoqH<1O+}L_0W4<9+is z&;on0#WL_5B2-5rp!z%vjr=%o4lEXM@A{3MNJn6u}$m z!Ya(tpvUU#`X1O4EZVBpZso`f^fI^C7i!XY^45zJymfC@>7g z?m;x~{M3{7aFZFlL&;y{{wMJIUPRVr z5ZwqvL-$yVf0-fh&RD|UMVIh=4VCv$WUuB{0Q&W6ZV{oO*u=}A&2373`88L7jtYq5 z+4gE$fKu})eGu#A=yjkB#m=Qf?{)~Zm-JXo@x((~%aqj0PtmW%AMKt$F)BpJa4@7rdV#>=BFUz%m1s z>Zoqb1U&OG&*n?%x(zd+&M7p1B0mCa!umQ0>$3P>4J4yB3BoBte9Vc7zesphDr(-l>4!o}CW5mZ;V+Dy<&PU*+$d*~8 z4p!hV)S37JE}az?NP`qg8F&!=8X0|AY|ozsg{&z(#ZtEkPn5K{<;P$q(rIS#?w7n@ zK#`amP)U8s!XHvyS@U}E9Nej+5hCwZ=Y-+9LXK)Ssy$;bVT5F+3Zwm`*jVUC?MStS z0S9`i>pj$uPEjvF^`qZrHqaw_zGN5aQNA~3{#yBZVMA*9l#*FQ$qpzb>le+B1@->q zBl(k!a7&nqPP9;o(ef6wd?2VaBldKn@<5+L=#$Ye>N*nJRH96n!u14lxjM!A!ag-( zL>|=#(rYL^T-R`O1*boX8KhdAUumw4OYvXn7!2>pMJ){PZ{T19?R4->4m?Rh40bUH`f~%DuwjJ>Wls(PI*xKQ@IL0V zG~CAoygZVqhiTP41rdQ3PE()6Jq!}uq3?7uH@Gaxo(Fuo7qm<>X+e42ZaHt(#fvi}Yww&u)|VpUB`EpvCs*aePT*l@4Qd zmRAwbx6}9>B$x7~aS`%8n@0MZ85<>2uo2+C)a=*15=(NiZn5~=d4;s)&cNv08NDx? zwr&ExV}U8~mA#tZgOPsQ&&3T@ZBZNFbfF1#?)&?|Stu&m6Q4umRUFoLw1VQ#kIySm zPI&3fPzcpIWnc&*m4fVpG_&t-7W+ObOR==il4$N+v$&*zbepn+d=aSXMf zzI`9aL0ahBX(I!g9GgbDeG%xVb^G0%37hwr7wOw?gjh_LaK_Ekh_!Ra8WhCpM^%tr zbu>_g#-2*z``wrmj5HaY$|*nrN$e#MD=NzmalM)kFm0uun!ua-8YmK)THo;!vfmEZ z%LXPRgxZfEI86k6nuozQa2rrs_;d^+fbBT!wB5w}kheR;r@0y|7CZWg)jw;u)i-|bvmg4WzI`l$9sQVtet!|t;pdL&)m%gJ@x%I9gv|a&hn)qPg~|I_h{^k@ zG;jqF%s(|_GAWO*;AgQ-w;ZYT9YqjLCenT~0%m{qIiQ-n|AOL=!e-3=*(sbbG~}Lc z_8l|R);2$#@Hgxl__GrcY4#oU$JRqJbIM`tA!6=KTKT?7>G4G$1_n=pXE_L97>L34 z;im}Vq{}&l?XVom)nZS0542v*X`*y_gT4>+owJa?#lFYt&+0X`os(+yW&aUe`i?9} zFU09Ci3`|FTzC% zlGT?~Oss8}(XpcjL?18Lt;+ohxmbNio~GRBkWt&Q8T$75;HQ+ngZhqF5#iN@L6|h~ zJi>}S^=i&(P!?Gkcw6as9meWaMuZTH zS1}`L;3H7$x_k*&Ai+Q~Uqy7c- zYTPY$%~r%&^0Io}mlCtS{Yh{gQ9PjRZpi2cb%y&Cwbe}eU2g@Rqh^H9<5g;foos?A zt8h>_+ok#pxPN2dJk$ayibwgg`5{@~?CHpo?{&d&&qkOG*9v2S@DIH|&VbFta)oz8 ztoKLg)Jd8Pd&H#RT#_%t^GgWKgJWfyW$N6M(Fm_{rCArOL-Evg~)YF2=s z$mC|*7eJsgG)+J|P~M&}uf_@%$sawBBp+~}s-`8$II$T`=fhC8N9Zg{LIRi+3GYCA z^qvqj7>Nxk?G=R1%=%E@&Ub_15opGr{Z2G0w;uWOt~7Y9FX0)Y)M1=}uhZ2*NzxNa zx###b+YyKQ{=0(;Kf3@r&@4!EH^|sl_szbB(k_M$N@qR--gO`q`;H7GLtMR7!uPMbH(~qAOeOoFo`evL-=(*ztN;J+G`eE%lk z2LkRBaI1h12zZNtmkHP`;9?Gk=aYU-aSdZ5`)$}3xk{5mB)&i#N{SQdv;rQ%q=nk& za{=EJaG!u%1$;ojTLipPz|{iQ3Ak9mA^~#*oFrhJfLZ~MU_QX}7w}C1_X)UFzy}1p zg+sNx$Iah1d`S}`JR*4ER1EtWUzvO_S$uC`pDD35@Z@_mm(4CiuCx}cHPIO{OFH_3 z@+2*zKd=#<66fH*7*8y*f8`*003g86GkYV%TObx&FITWSxYGcKJ;P? zQ2O>;fO!LE@6oAi!Yy{$Ymp8P9SZDxiM*1g0NK)`=X^Tgf&;L(lUqRM)LB=w}yZF1_AK!k9QBxnc45Vl9 zOBG(8PvFpBxC-tF^Grp&rwaMqK&|&DxW$nScuEL|h5wG=Lk?sfH z5+(DXh^lCPdp$62RM9cW!HSIp({`AlI5=F340)`&Yv2MwIhMFii85_Z05_%M&orRv zt?_8G=M|Za2rDvAAC_rA!oVXhaC6AQxo(Re50B}b_-SBPb}|kIXaE@O5KlL{y7=P; zY&27%XBO^_CY92{3e{__~aPM5p>S@Mc~Rg<5v;t;_q_}>^q?DUxS(d+UDm& zuaTchAEEsBgd+Zpn5SykltU2w~6={e<2=Qf&AD1 z3-K-y|EY)<=rE`hp}+k?yj8@HuJ_IVrd^1CI1>bpLx7X32>z+^)pXgb@_96E%ut<; zt~ZsBGvQ{Oo6m#k0;-1*)%d@N(|#&G8a6i6)Y~sg&B#fsZER#!^Hx`tJL(%;Zilm= z(dKeF)Ou9YEpplF9W#uzb)M8#r=zZ6t?~SpR(C^7v+Dw5T3T9!(U`izn3}r6(byUu z9$w~bXm%Uj^i>d|7@Hg}N>5yi!L{1qbRlUFqr)g@#%51bjl)Ttc5vEPIP5Epv+5ce z9p{9H7jVp6vg;swi(0S2>H7p3l-SdXmd8WNU9U1HqH`(bBsn3URi9c zP`I= zy8~(K9cj%D_te&@YTBvp2K!2f+cj0Oyn>e2bei@dPYVnZkbepb+%?>g?&X+ zL#=xX#bg;5t#KIVv@|z6ToK28jRq!IU6ZWIPno1Prb{CcHsqBvDiMtHp4ulb;jx$wKH5Z zDy^)zd9|&vq1M>g1pU?aoB?*V-z;nK7@HlAS`y-Fb=Vu~)){R^vgc-7lOuwaDTeG` z*Xl4fd0hOnISOBcqn5#98k*}>YljF*$QHDy6f~;SvC89s*&zqWVC9acmeoONxV`gK zjLrXSXejzuu7Y2QqjWPxy#L?u1?RC&@Yeh%(gdeh!zUp;z2BZ|7eY~0diGA)c({AAh05W?iLut z3bHZu0^Xrqo;vu|VUr>^q>!LeJ^YTx>0m*`g7O07?QrqT&;{))SZZ+o!$qrWa5izv zuR#V5CrrdvYfNfTieTgh;&Q{zcn=-XzopgDEL3)J9i2!A%TmM!#i(hh4=T6I z;aEwft-*NG+)N4RHzJqBj8qHH9^ECVVCqPav=$mIYIb>AsVl<3gLu$=>fwP=nQ9L_ zVdP@oIfJ68E23XvE^JgfZcyBshQ>zz)hhI;1}E~vr>oFaJyh|0;3LB}|8E2fq z%QfsS(Cr*X$65@b)cb{_Z0Ugak)M>8@}s!3_(h+ont$R7V)-g64f##+bf z20JvMQfA@tWtp?3)`K}lv3Z2H*wI`I&lOCfq{wN6$I83ujPUTJh6o0Sg%GbedLsJo zf48KEt(jsQ^S7M~!*3hEw<+wp?=Nc2zTZA@@6EM$Wo~?T%zfM6TX)*P8;3T&-T%9@ zty{yNUH|xHVX52ydVRukUA2a73EvtwUu0Re-|Id!-{*_xI?mza>mh8q`pP2LJfv4Zi|KXWOKWRLe=~@0^;VaQ^zPD`l ztB*XI{`RC9?1P1E3*XuwXX|@z%lA*6apvA97vFaC&R6vJKfC>|?IFp!jhd<_-j3Rr zI1u^xRqI=(j`bdJUXLf4c)-Ka~tF^1%m7X#7-+Gqejjw$jkFPp?%U13EpFa18 zX|Hb&+;bpoZPpL?vdlx_x5VE%=A);hFS zH4f|RKQ6UBQS$P_Ei>HgnR`D@fBJRP{U6SI>*j;AoA$nX-;dwF`PxMT4Fx~F-JDgl zvHnke+pFJkrOM{d5<;g{StI^Ay2}(z~)Z?mgE@k@ip8XV%_y&P7ep51n_>#gVU!`Si}A z@Ea#T#v&fSE9_G9jrzm=_v)@%@vU^)zjkXIE?83Yj~DA5ZL4w`$NyEkvU&BXum9`N z*{}J|yZ9Z$OY`2ZZ~1V?4?ldp>)L`{+fIJt+RfF0d*6KXvKwE$d++Xpx#iz}So%%< z)34SqdFFxlwOh`epYw#}owK74T2GDm^O1R>In@`-rafO*f4Jzw`iH*0wmDnj(aciMBLaE@~}4ij&pOy40hCqImazw znk(i#cXQ0e+dqEn?8h(3J#}l;?br6-5WVY-&$fO2-ug2>d^hs-{@1RY^YQE79DVZr z70upvPX9~Xt_|l;+HvHgHJe-3%-t6M`FXmHtrzKsUYMz^TOKKm9lFbLUBhEFM_(IS zX)AoCF>dY05u5(jAN^LPS6;CD$To^WgM~$DVok`MaL};PO|Vm^(1EC4IuT&pvzg?wv2B-}q$31NT0asLAQud878N zzoabrpz^u;x6e$wxbDgA^K5%VPF-=qO=q{9HGNm)Q+Hn*wdd3iHRpAH9g!1$Q}Ke7k!Tl20uQao-0O_V6~%KA z$A6`mWz=CDG&*g~^%%I7w4FjXC(b$M_RhbpmH#gKZ;Meu^=vKE-HEb~@ac*USb24?AJU&`{I%p`kup@8S9q*H5^j zKrcbPtVvyylSLotbT>3%l(aQ8Vx}XOv|^w$Cbja#Qge&3p$RMaRF}g}3t(n6E^ctT zJ+{V$9tY;llo-0xR5nRWj*T|Ax*&oSrPi@;p{B!-;)X0WB_EaS_(-S`1H@Y5Q_J4! za(HT6Xx>FLby|GmL!<5%drRZ+od=V*V5Hswj^fv!~CjV>h~~JoKNS=N-K(& zT9;K7l$Mtl7N}cCoJAdXl}!*Vm4nuN#BhRmyDFQYNJkU+=E>M9v8|+)snMpIH3>{R zYj_#SY}k9K_q2FmjC|XL=NQZoEPO;htqw7l#gu21>=DVM5(-r0@{8$@E6fQ*v@Xm) zj=Fgi-Zg4J?a;d8`A6fMn~#rY?0DS$7($nQT10gO219%$ICY+ACI$9{OP0c)=kIr$B&AS8HF20 z;fF?*w`&wWx1eB#F}d8aI%A4)j;8@`ux6dHq+(e`CUxhF;0aQU*=f_#(wXub=Fj|J z#{Zwy|2O_$Z{OeQ=ePPnmmlu$|I_yHpYI0gjtVxagbS2Ec`5 z@o8^_s{tRz6@~C-zz=XtH3s2BfFU@pn~X4hlRXoc1>t zk8n5OSRB1>N7x8>(#eRYFrW!nH^OCrdOU93kFWvob3C3si11-R(?on%oOl3NpUK!y z2)6-FPQ>@#uV*YBuo#yC;WEGuT=58Z0e*(di11;+s3gXwAZ!3U8CN>OM!++1Wg(mn zsGY=EF7W_HPDU9i40tZCr3mK(K8&jx;mv?g;%Y>=8&FC{*@+);0^UE z;Z1-GGf`HAs{voYbrj(~z{- z`2Ih_)qwFhx!j1b5pWZ(^#~K3cMfA4i61bl5Hy7I0c&t=N4OQR3s*P71UKW_kFaqr zbjQ_)a5~^jT(2W+urM}#K4aIwe)0j^aNS3?1b8*BgW&o9<;R~f%Mz34z-|fF0P1y2 zFO6fm^ss7etENou4(SUQJOAJOj@}ZE!k~WlS=Y*t7)kve$FkOwD9$FpJ z%4Mi&i9RQY9u>x-<^-4E1ZjiilALnr5L_2jC&4@@H?J>(5n2}E)TV2y<<`)$kZvhL zqlxI(hK8nxR4Zi@bvimd$-hU)i3?|O8@0@UkMl>akeT*lQO4kWD1D8fQ^Ox!?OlD!3T>Dl@+0X(I_+^b zC6TOhk*6V?8Lk-J@~9`G*PMV(d6BJ-hN`Z@-hlr0`;{7)wRt3R;|`1=PhgySe1x`q zCw%ggBY1G=r>7JwW{U!+2$(P6VgVZkTrXgkfcFUalz=Y__S_Xzk$0e1=bl7ImLj|r%jDPo%vnke8D0cQv}Pr$_j)(Yqr@Ja!HFW`LwJ|W;U z0`3#APr!Es{8Yfh0v;7GWV@nQlz=e;P7p9zz)S&W30NfH0s)r_SS{d10y+h}Sima; zyjsAU1iVYYhXi~=z-I*9E8xol9u)9n0lyURsDL4`H~K{h7$=}Y#klgDeetUJ&At?i z`0uu_gG@OWRzMGm?Y71Wv8Vk5E5r`Gb2OQ~EX{Se3p`FIHt5ToEp|L8XRrL6R$R+o z3!+x8pa=ILvaumZZ?(DHh4hqxu_VGv@I`g8@NJ1g@0L4_|;1rHoG`kr)7E;`dvf=c@#g5U%v4&b5 zw$(o)vt6NlE58iSMd(Nuo^x|wWVdHr&VP}l{(j9y+JYJk-?&796vz4+$&c&+>4r5@H(h1Tx)mmt!W>I6>iYuzvX$g|Nf2$P{Vmc>_K>r&4%vu_9nq zRRvYz%$2=L(FUzl1Uk0kS2MN%A)J!Lp^dc-Znh9uy~9mUoe=F}<-i+I+m7bdtb)QV zHC1(}DaOtN)`&v~t9d-uI>22Hca^QRwMse5P@_;hE|gGtuEUs%RoU!KwT;c}VuYGp z^;JAub`7htE1^3O!gDDHV+U9jo&`1I4UjKb6&-Ux@JEE`-`22xl6c0b%qF%?s>1V= zm8=_(PUtXZ52+F*sz(TieOOya6`3siLkOv<$cPE8qNhVSS!`Npm8Y4@cq_DuA8x{G zS+>>SYz{kFMmItn){nBH<8-;Ml@5W{u{?x4ZabU7p^MFy>v%5b5QLV+a-ER2Kt{b% zHL`UwJscx>8)Tf!vbVy5u9k&BcC8G7F2-(_A&9fxB}3uWIN!wnAoIggcqijg+2wZH zSD+=Ipb+Yb`rcC%Mm;gMjY7@#rdGCxLT((~VsFW-Rkg|W&>ZQ1_?ll>zM#-LEt4O^ zMRqaB@BjMMrcwUL`d!?U%PJGx-WlIk+cAZR^@|$(; z+NR-y8M7y5q@_1odV9~3riA|*pYoNn>ZQ6U8dVfb`C-e_5k`BlBcrN#xv7Oq7?I-6p3 ztajkg5Zz}_w7GCNxn-rpIdQ6*Xx7wUlsIc@aPG6F4i|#b&O*Ukar&jEp^;89{o6V^ zj-6^tQD7FPo{d=YkgCHfospVKr%Q{?IQ&c}qA)in7CJOC!i}To{1`Sr;V_J5`wA`9JTWWS~9`vZIsZGswWY(tIGPAPMGc&X6@}}ATd-TZt zRXwt7nRS`Dj%lgc(`xckv$C=>Qfq8^_SD*(yxJ^VmMzCIE%(1kkF<6tO=|A6+Vr}d+Voo6bgqe!_Y7Fzf4ylk(tlNxTt|A{bX!Jd zYE50uG_;K)Hx(_Fotl+fSDT$~%gDCn@wQPknKd=YDtXtKdYrMtl}uHA$vNt&Fx5N# z2Gtsvf9M>WBz;vSMCZe_^#;tevz8K?M#L9KrmBKSmCcLQTfXf75-;}c!GlyfP}Cy z6)Jyl9EFv5^U`06SMrmVsqyN(Ic&5bfh+unE>QW6VxIjA)yEY6E2~ugbiw~FJ(xPd zPm~AiT+zOxcocd2hvU_G{Jo?2R8*07spr?_<*rfVyT!V|`V0Cg`M-6k%5O-?=UM%F z`R~HVK!yDX{uoukQBaY;$gA?_3;qK^bCuvEO8Ji5sPYHLQCN}p*iCA@AuXS?n0`T? z!vE)oRsQNsh5sU@)A6*yHzoi2Csh96I0`HAr$6~i@k)MYKc&X^W#w}b^L|yo3B4+R zb)Lds7R8hO>?ZO*sPd0yQ1bt7INmr{kwr1oi9nB7B175^#vSBN2_S)Q>REn%Orj};ng=cr|?D}R;ULK1on1P9H zYs*yZ(<;ZxQ?Ub-THoNF>T=pgs3ReYpDHfLT1T24Lr6Zarr;4MMAF(<*qkhsj%`=D zS?HP1fG0#3hP6XI&gSFhX{HT7oIS^8BVsfoF+>RU;NI$XQrh{HHgpXMB(#P;^A{2l zro4oCyck)-rOApk3d_0&kXqIyP$D_(cy?VF>BqNp5qAQ$B;9ZVULIN34mp~t!lea; zWtGLH3#xFwytLfRZk2x*o(3189o`Kupsif_*6?{65#vCXLuy0P)4TH z$+{e55sstq3n~kjRzFd1Iglfw&EG>8hA-8Go<|>wDD)$GLl6#NQ~8?VvwF%3+P50kq& z`5`%yo}bOZ%R2TIl`TA<9v-tfIHm|6ci?fmdE9m-Zn!IngnM{o_o&F>w0n83wAjq#W8@v83M{5_ zCdWzSlcFdgljEgC2i>0>+vzQi`t%Xd!R^o|?UrFBVXhs>P;C(8t zXL_pcLn>Z{{5}UVmb+`6T-)NIN0uQ5nLB5J%DM(UVWCoA*sFuuO6J?D`{S(JF6Nc(|jAPw|p?rVlSRY}~ zWHZMO5eB#QIL8i00)u~kf@APlK;faEuD%OadMd_wp2e8sdcQI&k?#tp z`O0zKTf}S%Ux1Xdj?xFuXUa;8F;OV5Kv&-qehVU%DazLHEQFQLgaZTR4m}!962tp^1`{r@OP%*iIhR!%o)euLHUjU z5qA<#QXziJn50NZR8C*O+P01%pBAS+`Ez4U>C0HGVv)ZPc2ac$LvyJsgVz z)>vobO6}#8cu-na=x@3m-6x*cVVwvzVT$iz0dN3RQ5QiifkPpVhhiVr&fBB&zI0G4#z>Sx50| zYZVn+3)SX|ktfAnHwLX!VzaMkXoiVRj#HXTnfaI2iL*{9W-^b#aE0R?uxtnH5@#Xg zlsGbHSu4z{vZZ2OQ%y^wa^^=qi^uB3LIUD=B&40qBcinQ<%-g}Qht!f)~I^(DLgNO zwg77{n;q6lpGmPJSt^e>Nv(z8vdC$1yHQxRm}XO@smfeT@8On~FJn5nChlu0sW{#< zywtICMKCf$5hm9vrBUUN5+Xa|9)=7xi&DN6Gg;NzJR~>79We0Prltm23vEQiuKITE8KzffAI zI2sqH#fNPt1~*40gw+z_;fOJ847|6znj?u}-;&TZT*c(DODSe8N6rfCC1f2(ri85| zp6X4n>DyOfL03OkEpF5^gU*r$}{a*oUjBj+l&aU>rD zIgkxpfH^Fm1YE(9qObx=k+QJG6mumUYBE&K>aL<>L45z)eb;)rPB$GB+G!hhz7XyMHq5iR^U zM??!h!3BsGev%`ig`eU@5G}lgBV|epZ{^5RrG>X~q*`g=?OgN~-!}W$kFs_6E0=_+hgd!|wnEV;fTaBr-R#X+3tkyZE zg85k8o$?S*`xx%0?7@u>?|ibsLlAoa)My%J4pKDDve>DX;sq6zrUeCsRagXR`hG&p z1Wz+g7}hdPA1#NlDjntlDH=QIvW^6VmQ|LPRapxc7g~chrr?q>k7HqDNd>HDe~ss) zaS(QD74k2yTvS%Pps3WuR_IQrcL68ZYnaZ+XG#+qTh+w@)1C1?)YpMzcDPo$TUwcJ zB2f&WR5rM=X49QXc>ILgHA|T;kpvhK#sH8+;Y6ZySFf8ycrwK)_+-MTP&_}!N<)u} z>5_?>PF%s%6ryHll$#khin-f$}(9-HavrJe~;jS%i#sNmAn>q+e8K;zb+?Dqiz}-NOUf$oV2gqa7Fn%KqEK-r3*j(}g%T`B zf8;QiX$Tf9V_Je3atm1)h33$ngpSjSE6Plj1r`=gSYdg2X*rAFEVSJcNg?P`jPEhB zC_)x3n7^QO$pRKlh`F!;6C*1dLr8H3GjI+B#wvkKc9IgvV&gbVE{jnJxh$3wAT~~+ zAapW?_})r9g-{(8s24V#5ZaA7g#s0(qC)yW+fZ6%vU=sXRqQC@5lcIkZ+_W6456eEp^Zo6$%qvMV-H zN+60RLwdp&^C=kmC?QHs;Bzg+xU9Ue2z`OVsK&zb#bj4)gce(^g>%tp_!G|&ti)6? z9~_F*%4KDRL;%V{tI8G^EoPA?%a~IDDJCSIc6ZK@BX8(~Sx&$ln;%e)yixeHDjY?j zqw)joM5J-+RDLrOr<~>#_{9=mK{WZ#|&X-l8ned zdzW)0`-N0N(YvA4;pVqvQSw^sS~S;X+cLvtsS)mbneILz#b+Rr}YkXu@_Py(_UU^ z=qbnzt`i@;Q?~38!D)qS;qZ`v3C<)EZ7 zq_^O_CN(hW51ax2F(7T?w6iB6`hMv#NGI<`Y*VUe0(kk^? z67u3d>5ln$5Si*&OP^VyPY*L`RU~XnDo>@O`ut&sNiL2pO>LxQl;kEW zl9r{8j9ilEuMiz_y^*EyPmyBf+Kdk*)zayHCSAabA<>7+C$(ZdEv6Atm2?l*G?QA( z3ROzA;-+1S8~vtThX5@?rrnD`E2m|7M9Te%jAbKTwp1=< zvaAh){2It53OOWvh~@lQ&_4h@>!qNyt3=uiHhs$2d@g$cJh@Ui+L0Fp??O-)WYX>G zQRHII2959d3aO{xC(?aSsz~MGp~g*$ploSjcxe1EvNSx@pduk_jNze7V5qdJD*nDk zL3t%sx#T67^a0h~W+6LG96ONiNH#K-*VyX182tq;T5ILae~8F8L$4VkJv}93(not? zj-l80U6$9-Z01|c3q5$tgh?OMld(hKpP7$aoRMUrJ6G{H9;EN6vn)dPd3Cg{ge?Z? zdm^nP5@1)#loDUILk3jy5l)yxN-#RWILFJ7IsX+Ri_%8+h z55(_8;I9Z|YzD`)jldF6r_*jipn?K-A#fK0b38&yDwl}jx}^+VjShv_vRi@|o`O5j zAIU%u3I2&xbNESjTxEn2(|{*EN(^bJ;G83ZYcul5`B5O$xmgjtMine|A0;w~!(}5< z-yfE`pBU;$>LkI%rJgMiE_DV5DGWCAiFL$Z5EbLjLK;Ix9LEg2a0GWyu25AEG8eqO z5Q|904APRLixrVkoARMNkKj(9`}`$JoKB6yN5-q{{Hcw!REd(+C_Y!=GZkqWO=m`& zl?5-CHMZc(o$wd7M)(4HzQm%fBmi*@O|4bp^)4wjhtqHpx1q7tZo?cz%2L>dCr8b} z$+(}T*Q+8|)5xnz6EB-ZUP3hhB26S#W1CfRlmy|?BJa*dW2De5>gO!v+F0a0OTZ!P zF2KE*%f@I}RfGL3EJUTrwBxDfi1V6!?j~g_B~V^hlQKwI{U1>s_d>=zVqe=(Wnn4Z=qFATHUiEY+%g3Vq9w%G!!UDsUYZgla&SJ7K)HQ0VXZa8Hj=GWttf6r z#o--FCe5WKczEc>hZU3g8Ea!}L6aC}EHuo7hqnC^Ycs7o!Of&%T8P4G$`qkcRMD%Y zvDUHH-s&EHjZr!;2P?(-N^GlL8EWgOlF>1`g-U8{D`w9$6xUPX!$Wl<-cnUkykPDU zEL*S$wOX+Po3m(cRf(z6f~6ai8mI=WiVRBM=yuiOWy>m@Bcbvy;Zvbe@n{qgz4Qdp zE>DXZy=-(e=D|3gvX)8b@tBg`j4`?*A1t{ogfY4zA1gT@6uKfemZ0_-U1OdoF+x$g zB7e6)yagzLetM~R;ZOiWw^SxxJQSeB1Q~Qm%S-M7piA0QB0(Ho249IE6uP981!xXf z0bcIpK(a32kl!LZ7l`*b1sI!Gk_G{EMP6Bw2SAsUQ_5eYkeCprR@PfXnC%A`Fhp`1^d$z4yKM{iYN|XX=0c z^M&T!bMCqOx#!&VT(u5)vA+^%XnP{-uQ-GCuFqI`!3U9)7d(N#fBP9LH`?~MhcYtu z|1-{GBzRVADvpM^L;IoBX~#3fZ^9IM4!;xG6ZnLQglk>~>}z|Os>(a%`v{xl;||KJ zqgy4Z2%t}tH&ogU6rltB^JZ5RVIdISd)mwU_cv#0bP|V1(n1{bDWy9wtmIZ z#xU@r#VD% z)u9dvEO#apI1OHQnWOUlH5M#cqA3_`iw(A{Nh70R%29=dhV)X9B6c?bQD3=;-Duuv zfZ}zEw47T?Hq5*U;OrlOu*G^vCKLydBw-B3meTLffcxoL_j2;Qw{Oqx5DEXkZGM&WX%Kc?k5_1^$W<4x9|7omA(YWTZ{(7!baxu zFC@~P7DEFlO@sILy>VXt&*#^H1P4rzxvLP01^*!H)7_50m}pLF)&vF48mLjDgbOh1 zf zhR{7v<=afWg4C{+)Rtqu#o|pujd1E!o-~DI2grZg0RIX4@95m2qR40yO`ZJ8P$Zz* zerxl8gQ)XHBHKU zA&kEz7Jo-t6w+e5V<}u3OWwpkQRRQkP>e?Ww}cd`{2_y9Ps{&?0j7ZHo0`ZuS>^w; zL6aX|HDQC(RDQuiU1$jlKWU!LAyeqi?JQO0{R|=N8X}cUU-20S(`p3j{|2BeVRbCU z)eiwG;@C=b08vc+8D;=F^m>|=a7M6)q&#cGcc3xQ(Ac=1mU}V0HHa)_9D|~<3Jkhc z)gmMO=Pe#&Ei2fsf5;hRO)S`Na+fp6*mf|Vq(m z4s_FoS>h+dtit|gFZt`W6@MV%|}R8&JI00h7cqY&^=q7{W1+9&#D5_kf9IPDs$vyBPF6519Ip{gnH?KcIZx z6^JUYk!O;CA%G&&qYoR+OwODuz5x%1fAXYpoGT83Bp>%YlyfD~svszA?ra9<@D(rR ztYTw04*FSMQ*$#;jA=|BUQxo4K4%pxRVTq=h_-Hn6KohP9F&l&8FC{aa!_96kw=p= z&O!0kIT4C{j3%xTJ`9305wvd+hcTH~9G(6D2EXEa;q_sN{eF+aQL@6wa%lY07UTXx z32fl1;GyJ;r?}0(@Trtbl?kw{MDm6X-II;pRd?us%CF+p)^k z)rDmm)Lfgrlli(NfC}5c6RNoXhL$c=L>qg@{m5s3T#+X=rO>I=Ffto&CwLFQN~w~w z84^R$gLM*DC5CC;VRFjpBsKKV^0>FKfz!p-PI=2r$b6WPZ((xe*#_}&I=7X#rUH-F!oZVKQ{0WQAIoo3Vh0| z39EWJMjNQ`s6b`Tn#vwEacGaKHlK+@t0xY9>%8sit@HZ7rOG%K?14DwTUsX>V8jyX z+$d7-ciaXU%zh1PpsE_fbXBf|SE@{~!4jBF@l#L;uZ%$chmco33PNWpl;!;r7B~KZEedUM7&A#$eWJLPP^02NOFmhKVKaK@> zBNm_>Ig$Vku>d_lt>JjSSzCnjw>@-l7Uu^>BAh+yz!bD^X zRR}I#k6lt(iowR>bHF(V5MQ322d$xdB$b$RCbbZxAeG!G_FBHkrf2!iodqV{=TT(- zoc&i8qD$&X?qnntg!K-k(Sy#Nx3Vi^P0ZkJF7BifxxE+yk&rdpChc0pvq~DCZu6qa_(`UX69e;Ox5kayE!*>`TNj$etkCUl3|61>)5v z^RI!_`TEo7$im>=sI76t36~!NRC=qSB$wX^@@omV+{;#bRLS9pp!D0u-Jd*#9D@^_3Fz&TLd|~|-_guRRk==%q%$)~OJ`PU zU-tEN;tL`2N5fL8=1t>G-YxB8GERQIRL6vAS&aSIiANctQxQUh#|t5W&Y~MsW5`g2 zW;+FvZ-6MK-%?|}iV(HS$v&@>AeSxs1*L5U z&(8F5jfcJ}z1W~x?7MAjYLkx5wvHRjR;6EvMey}7f|8#O)U*@~e>QGLrf_UpvNpe0 zWYbj1Ut*#94AL<$XG3%-=B(79+0CbEG_`3-mBBN?6O5ZJyH#kQwVyI|L9LCFmrRZV zl+2FYrKiUN-)sZllo7Zg3Q)2!a+h`*H>>&kCU;D%J4SQ9akF55(ljVo$%QeJtBjj9 zHUVrUHTG(l2hDlTJXLaa6i7{^7HKhTum^19%y8NfxcH;Me;Z6Pj>sXL<5pClCA0+i zlL>Hy0bYHY^c)T~gJK+UA^|=Rs5H@EHwY!by*g8}&hVgi@>yOR#a4f+0VgVX#fR3;LY%UI;80^7FOq4!v+${H}Bp6iWg&Emqr+Fa? z#Q85sQ=Ftt<^ZS*Hz8Zh2|0WD!rsyHi=`yG)>kot&84Z=+>CSVY z{Z!;(2SM7yt%UFpb=u%ipEeQ37-)?IJ8b}lwTr6in4J2e{KZ%qdh$e3xfeUkfxEA+ z^nOFbf%kU!>t04BAl2hcSLMHqk;J@nQG3oLBvUxJP7-K0$+#G|O~t$Hdj7_pJWPaa zf+t{Pwq3IL46=9v?VLKhqyVo0F7GjMF*{LO`|6k$QW>_#_^&r*!RJnkyuL%nD{!*8z#eUZ9zKNK7@DY|J{8>0Z8uKW5=9 zbrSA`?=WoIhy!S0&EM!OtFB{gYB*xx&)L5g5gSgwQ8@j1RQ#~IA$8(ELH^>MoPOX; znM>R*iqKhAy3&wP&*i`yxl4KTTXi^9es;`Tybf3|Rr<+lO~s&m`A7U;u>Pg{W8N*+ zyW%VpbLnj{?+dN>xX}BdnD@2TdsgWEOw9W+>%BVk{+F2dPptPw>pkhUn77hRlJdH& zcWHjC(1Wb^p|D^>V&11%?_b!FL;1v*w^YfAHl!Ln)KTgz1d%5H3+_V5(p0yY(RN0B z3_dCEpvgyyZF;g@iuWfxr!dsCE9Lf!74zvwU(QaMk60k5XYdx_Y@feTdOQ{OB|a7*gvWV>J0+jR6He zGC(5&EYblmGA+bGhkfe`F-qOHS>^xA(3}OD{6EHkg504x?H>4iC`_*JV1q{Lh>Q|} zJ+uhNNcnt1VwFSLP-}?FCHJhF7ZHQ0nyCzMZWUGoPBLWOKp;N7V&2al%QPo8%UC@r z&pyE$dQ07vYtMr>*GWnxthrIha48+C%p9rJO`x30Q{e?`7WiAf9=eeK{6iJ`?F9YT z=~sR}u>9xrFYm;M|NJ{D?DGir>y)VLkg(500RU7_+JAj*f1nDQZLl@Hx%%7+M}e6&+5 zAG)pbp*vJQ1R~`_C{jLzwDO_LDj)4O$|v%OG|e1K5uxgdN>e^WQ2EGLD<3+0E1wiY z#*`1?Q27wB%0~!|@}WDXdTVqa);FkcnDckIXqHs zFKjv!9VC$Q)*aLoh3tM?5T>sx!Ye+o4AQs=rhs_kAa@@rZ4{sCJ1jUhrJ8|{017^x$G9SZ{ipN*bfCT>0RZ@{xSN7 z5x@yJwE(7z0$9Ef!2D7G%NGKeUkYG;wE(6|3t+*80+^5yz(OJdn66L&69@$`flvSw zpa2#M3SjMk0M-r&U?G73)(8k-K~Ml|3V7jaT)@~z!BacYh&ao5`s-CDc0Zar1uza-urn9#I zPBLUn022-cFaaxoh0q9Kx?=*EU?hNJP$+PBqdFA!FmA>9hW&oSbw0aZE9V{>JpN002q0I??1UNUM#w%tV z2J+%MH+;REEXc!@H^*p!Y?daX-rn526|Z50)VZ3v&gzUWv+QaXb`g*BGK;+c2dVi6 z#@a44p+zaD>RuMgTV`_YY1_W)Ur;j%*`PhnnKu`jkoN+k_pmY~zctWD{|hvL7j#gl zzlJistupX4l!1p3?qy%W-{dirK~|^?NRQF@5;Q9NsZj=WYGoiD8p=SvPzL-`8ORsP zfL|&Dezh{7ODhAxh01`CQ3gUH%7Cs=84w7S0fA5%5TG&;3MvEbfHKeyC<7sZGSCPp z13^$3XbhDBU0NB?6)FP)q73MWDFcF58PJ`k42UqwKs&WEpxY_~xT+akaC$8V_K z_X095As8hTGi+wW+ZFERsR|bhLZO*(vAFMEks5)qQ4Fn3fVrO+d?I-RMt|;=Dfagu z3Tw?!x?f0r8o>+vUKaP={SrZ06eezQ-~D2W7I3RnR^SEI$W{=uxbN;x<|9(ySloB_ zB=<-bjm3TU!vY7svAFM^FK~fxEbhA(2wdhHi~H_{0$2IQ;=cP4fouFUi~H_JldOnZ zUt8RFKPKQLA7=7rcPaOxWPkWhB?ycA?#Bf@nP5G@PY5`jAS~{?7Yld_!Fd2bDPSGJ zl>k2_;4I%*+;=aLl;-%fxbJ>i@-`p91m*4(U>N|Y^nC&}060OpmkO{Bz!c?vMu5!# zPE_t^1?cc;ao@d6fSo=q?z^88V2@9W`|jleT;$W@zI%lLdwp8mcRw${74QLYr2q%v z)2iGr2yhc30I*+xLq06-yI&Od13oP7y9dO5#HYo5_bLIN1c1^U6yR9^D9zOZyZ`{D zxkiAO08CQuwF3MCz+~lKC%|hyt=+rV3-J5Y4y+g`Cp*L9zWZ?UW_ozW!s3uRD2G_eXP}d_c8H%K>LMVNn6}^9~aLf8J=O-uZTA+?&pZH zeDC5D(W!F8s=oKhA0g{G+Qh#1scLvYWxTBw{hV-Uk{JIb28^ugCniJ)*i%Y8Dxfv8 zpLk3_ZDim50|kP%tM8UMe?UY6h>3jnXU;Q3L`L)7mmLP~6S%)~-eCWPQG3{=!qxCM z9FZZ(`zR~kboRqDLAtk`N^CGhbia?&{imVJYg{yQ#k_hBz3S(|0%PF5?(k|t{xgWC zphvlXkkks6_cYN27Lxmub2Ge<*R*i%pCz?~HNEf7^Dj54D|fzsm_d9oz3(pY89``z z-#yLW0?I;?--~~JOHln;8h*mU`KpjY={XBGLS$u{dB^6!S;Bw6LyY3yZ0-#s_U+AlijxHl&^p{x7GwwQa1 zfM7IjMBlwNN(@5iwj>+&Ad^O=-Y(D~La2^A1Ufnu|D%X7~N$dCitd>o!ZQ)4a z>%tkzuW#EB;+_^A zcMqgEBR`5cfA?VOa*2rH6S2WkWX|8cH}xVs_4wz$)Q8~K-8wSo@7|w!3K>CGqvt@v z2;2u!UqqOG(Y!J6eta@kI!ZR|fZ#+~Tjchi_oB#7U@4m-^h-oTRfN+{?h@+YLhIm+bnbzMN1G&)$PGh8{-coiZ?ENU12!mh&R0XWxQt12%r-ix%iQwuz4aGx%U z1yGHr(Mro-F+MMSJ#qPz`>~ z;CEnZrV81vtUDt(s#)3n=dElEM>ysM3uhR6Ov+n#y^fzWW*BWLhEse*Wk`#~nDxYV zTFqdj8|8Bd`x-2bhHPnDbPRKr@}4!z0li5YVP&ghYsS0am!BEWRbRDs*RwgE}aGnn7|A8Ts=D{le5=X#jsO`TjmSEp@ z$ptTCK=)=P&C?la2G#wNiV5&c1SjHeun2!rUqfQ4?fgR*w$Sy98w?h{G=aH7jbB!g zhar3pq-8H>#M+GCU+@JHel~2=&4Lu~ zQhufQmF29I$28WqbhgihU2^3Qs9+l+Bo2 zb}I5fn2WOnF|&EFj>u&W=VsJFpC|FhS@Aue$M`q1hA6SB}^)B2tY~h5+*l~pd@(-liUNa zaI)!kH$xz(zN?W|ox!w9oQ(C$h_$E#USCFtqI2PxGZc=G!tpIQiub`$%$uqGI!xH% zCM@^hB;?v*Cgf-6V95L7D9NNRWmK=hrxIs1Q$WXpAZcCq?!U%UcV5n*H)wp@rvc@0PEgjnNY_;9YquQT}m#`>X{I2!qW zB$M(gZ_r`1ACx_mfiu2H{M55?KRH5It9{mmK8-uKG6xg;fmc%A)G#IDk%JR7ep!g8 z{Y80!z?n>YNVxcKqN*H&G7M;h0no<97=$fmE%c9AgiGTwn~mH4D1i?d9bU;~K#fFc zpFk&C7bZ$Pt|A}O`1uz9wss2dX5z35YU?JQFfv$pkESa=DqYNS;k}x!z|al+F^bB6 z&LDL^Qc9?w6&!bUEA}8;X zj{3AVL$gl!JkhzYZu~D3jW_B;T4}ag?sUgy1qqr`C0NBI(zf(i8 zjbb@yqqj#Z=}y}yCgT524ROyowoyzl+9-}e;YKlW@r~lFM%d?Vk>}A=P2#4@!H0pE zHcZ_7mIyFyvGW%32(WvI$0TpP4n740@QBrI1j+()6CiOr!77yszKEEzIh4-XxEikl zE^g}Hj8#tvJX#J)1rOnGE>n0Kjz0VYBzr-g-AL|iYK5(4y!?z=Kc4A3WF^Z?kn-p3 z-wgGekIX73k1=h+s3u>s>*O)J_YiKH0N?B2`x}8K8ffGQl%TU~E5;f5^u@agg|xX? z$Sh!8q3@r}*r&*>euUY=9x8?oe34q`>q`YSb%+3^k-yB>gUlB$=MH31TaZ$5rJ(P~SfO#n6L58f3+5=_pH;DNC^_OA`hH|KOvh;N7X&Xa_yx zu3m=1O@UwC%O1sF{}?B;lHtiL(nH}cB+o(?8ih-zKAA-qkLk)6C$sqF$t?NeWEQ_X znZ>U@nMIdAnI*XJWELTFGD}G0WENfF$t(il$t(il$t(gqnI#lFnWY^#nWY^#nI$AR znWYgpnI#CG%+eU1%%V%5%%UqinMFWOX3-H-xCHIVEV|PaE)hoIYNtM#MYlbfMR#~I zi$J*jIh;_qL|#WopUk4mp3Ks2b22OPh>l^+u@n)io~X2wSw!$;mVEWeEINCi%#s@x zv6ET)HibEvMZliS5<+t_i|&}hB^W8(7!)d8;^GQ7Xl!ZYGuw?F=AB%pd?8rU=>kKh zP)eoGUYk}g4M-C6Ky@sjoX_VvC`kI+_J||2oDn_Yvk4X`~dib zok&=uJLoo`T^c>4<(b*E9VRnpPWXwUe-)} zY7cW1UVmPu$@g-VFB#lK!bJwRk2pZm=@XxqYt2E9EA!E`V+sk^*X3gw+~`<>KY=yp zu3WITzHycEKU0ISu8uDG2S%3&1#==@Fb9o`>lfoG+(x|dw_rBpz}%%P@FoLy8f%kP zh5ey!Q{33Gn~KT7h4T=(O3jqFMfm2G?E56E1s}xlFiF~t_vTe{NZ}D=p&-Sr>Gn1* zN2=t|!jlk9Sqh7xFs+#!CL~pxe zt>x*WmX|NIJipZP@`aY?ms*}*t>x*`T3&FWmM3JiypV{Nrz_O*1VSxOAk^{%sO5!% zT3$P#<+TG^UPz$jH3C{*5Y+M-LoH92*79_PTAqMtc{*ZRo}kt8bf;-~B8-;TPOatX zwpyOFllL`!Zxq z%M%VS;}Eb~UI>krr#q(Q2}W8z28CLlxVV-t3Y=+IgZYY^Hf)eJ>**8`s+i|*Imwto z5a*#gd)l}?->4NNHrUZY8(X_uwl!{_pqx|4zeTyu+_xB2*Dlxzo|hiae2J%+FL+?d zegPq{{V`(21o*TkbgYZS@aeWDyd{pb7VC%w1kn;5armaf(ql!v9RZg0$GMb#1JOgv zoSW~0yBKf((8R7tZs%4VJ@$?DOHO!>>v?9j7>|)`R?h8|h6Q*A6(8r0vk|jb{o+XqpXTyf1>$RJJ{*Xrk>C8#gm|CrVo7a7}e?N2(R& zc%5&vbGJCLr7T7hwmDKK6nSikWWZKV24oxTBABxlSo`3%)Ji*KY62JW=j?CKhDE$> zU3esPC7qwI!Oq1%uotp?=}$r7?rRvd$qckcU?5m^z5ylzn1T?4c@0)|)G;~$%bf{> zapqy68uZC{s4o~`6+$&hsO32S07{zY8+5htrI9)0y$1x<9G?x@*3`L$rv#|hr6IL( zp?jPoAQ`IL@Se9&vBTCY=ROV&hJg+4CmRgI#oY&%!%Gc+2=#KvB+*C=e$M^^EVYdI z9=yJVGLQHP9IHmc@f$e44@b>8Na7(AY7b&|`Z&MN0l^i(FB}CswnUD)4v@ER@9xpJ z!*L_fqwj;GWHf53U{swX)qzqiMM%^X%B%*}8T`4xk7+f)4k1|1s8}mOtr~NU@w!;N zfU8qgKQ%a>y0}HhiT5l_?W?N4#Jr!f-gVY{Z2oASBZiiCtBTrYUySmF>{b$HCAbz>_Y2Q@7O+3}*Y3f0QG{|W1!&GJ)e7Ib6wV&(iy z*mZnkM@#DoQ>QdqAtN#ihK0bT&pHJrpZ|#t$)B_Tqu2nb-GLW}xOt|W?|{!R((&qU zs1t$-+g7$TBl+(MzG*a?kG*`OiRTEL?=nR;28V4 zv6`G*i`shn=lRS)zN8u`s$9>0oqjEuw2WYIGA!WOo_gI!5*t=gT&-VF)UbEue#u zZDnNNKWb#iTh*P$hy4BmViBHyA?yyRak}Ee?r_k0AtMwIXN}PWdzg`5Iy>{(>){?f z5uTq$+M{SLm-RVnjyOKKd(7h|%sdc>Z7u!z72|WJ_^iQ`GivOgVmXxDg`E}6x72VM zO=+ruSSe;l1D78`iO50-+)i0St`vVgUVJkFz^bX=gVyDap8}VOi)roIsH7(m(O`AFbg#4HK zkaJS}+*VGVGi4?4{O8;-B@Z9|b8b92{o%SPwZQV9bG^C;sV7t$EX*C}b6z{UcXsoI zCoE1ZEe5OGH!YKgkV9P7y`c_YFpRmZ`)AN3)D_1+-_1CViFdU(Y;ED@Yr#03&6%iO z{_bH>%u0#JRS8)dc@#eXm=@mfS|^l)Pm7dE7k{wW(1uS|?BH+gmQ)#ZOb{M?w6~;& zp_j+d;VmiR6RBrVGq@$i6oM%1Obqt$>;!Jkq^Iei?mC6nh zK^3xmK1@G zz}%7|urn~XqzLQ@%q=Mb7X{{)6oI{gxg|y53i#k+(v_0VLHNimDf--m2;`O&fkT15 zB}MlGfxab0_mRNdk|OXV0F>sS#Puuyl;&yyUI2j7TqD3s0B{H3S^<6mKyFDfg4Y6b zONzknb2;2mPM_Ylq{e`ylxIBHy11yKa7&884kr3!-jX8vrbM5k+>)Ztp}0?Y)9EpZ z>;df;cBSx^6ayZ~@C?I#MZ)5ilxJ2i=b}@2X7%#d%(`8@oB)q-)5o)`m-7*MB4F3R zIZYkKKH`pb_#$>r)1UBYm zz*(^yNe=c-104TXxRLZYGNl50Bk4cQ)#k_oy55m8KVMr=V!{aTS zuku++T5=QrMo8bp26>(x3s4DJoiSZXHVA|?VYgRu~oXQ z8^o?EG2KL9Z|#6<+mb~20k-1XJC}BFBSPV-5+h3*WO!AH{TMTO8KbLssLAe(yl78 zArAJjg+?DdC&{)rh({+gFM{E!QUkmS<*L%J&=G^^suDr)KzLOtOiZpSvBeKEX;kX% zNkWGRp*rpm=m;T{?@oc9C4`(D66hsDa#e}pUh4x$t|}3NBmgK^l?WCHC|8vTRtYFq zl?c`fsIMv!uG28GbiX9DOvA|30|KwpFtYV!fjcyej2#wukA~%{663>FC1GufC}CX( zhOKy2iK3|}c2$WC3OIIEiJ0PV;g61CIs!-xD|$NR0JK{kX zl~RmUg`R047mH_gkh%TfE|DmQqDhZhC+^bHAD~JS0V_EXyb5>8^+@JTIFj#U{dmh( zEnU{QsQ&c&MX>=Xmb+KsHf*x+B@jZB9gC(fBP-3=+UQ4>aakv3p=HO|+9(gVHb{>( z-albhT!vL=v$a8|-rAsxTO0Dl)&{@a+K?}{Hu&Y%2ETf1gD$Vk3rjx1KGr*7i!3Ae5z(NCeeKD8se>>JWDo@8w zA{I4fwr$Xp5~q@b4^@e+*{$uHWS`U-K$KHCyB!-LOE+pE&Z!($LI%>yt&|&oR>31K zGsJKP(c7yubGM}%!{O_EJs(z1m1qX##q;J2E*h7XZ>*qJh61$y6E9V28dD@xu z6>#(C?7tc(s|IrV=zM^)$M0heX;3{j6VmS`Hge#3AC|)gQrtW1sNX(=<-$R8TDv-$ zU{|N5)6CP9(?r^i6ClZ&Wbp@&S1{?tld$~s35MRls$B$InS(nBw$L|g3Rc+9F!TJ! zF~7eOOH4yxS9#hHtf1Dap=TSv+bv#I-x?!-%Altj@+XYn4=r9*|0+iQdxM^2$kq5d zsgE4g22-7+s!ud1W@dyzOY9TWu<6F{d+@7X8Y5g5C#+S~TVj4&<9-uV^~Ev2i)^~g z&jdC6>X=_x3lm}uELS#K%o2%mPGB7#GJ$?AMM2H(zo0Mj&P8gp5B7j2lPcwHzCjnZ z3aBY}gZR^^{HhMD)nSK+`tt{b8y9dzO@jRdUIy^EOmuiR;@`(O-8pE2-UT;* z&i)yQ9M2+~v%ZabFY7U4*C4-|;l4tKdjnv|kxwwPk7J2iv*1@*G3T6wBK^T6z*Zkn zl+J<$6Y3<Kz8jIGPNt<;zbQzix|H)sMx<_Zqb2%NLB_wHB|c ze;p%##Gp;=)y_nnL#F&MaX+xzpqSrVHag92)hERKiV!x&a@F%B|GY{RQIx>?501|C;)O_S$Snx2J+ZwrNtss-vu6!>$b) zyCYm3RLRiP>$wtDA;Z{pVag*KZKCsKj+Lb=itMC&hRn!&@tSc<3DGZ zysVl~FO*>@;>=sJx@z`GCsj=zcfz>ZsOR5f<##Hz7f-5X|rhfg{Q)(cJ^&;8Eva-ePOjwzGIVqtUarq=H9*x-$@k&FK0 z`43mQx;J-jz~bjRQ^#jPs`7VxiL52a5vza9zVMpM71IA)YFH6p8CEh>abVLQ)=P(V5y+vL`UDest+@f!* zCO#nEF1%rk8E3J~{t0YE40sxm1X&nkG-FA3Q9CZMF5-E@#JT|~6sjOg%mv7JLnWF9 ztVb$US)!A15~ID%c&rzXp{N2LtVlEqSabB;$jVS+gXCyT*2<2i&KA82)*`5JsNJKL z8`mv%NM^HSC6DXLDzS6Gw~>97#eAEr>>6-4@)%^{-hPjarwsla!RKZz-O&bPuB$f7 z>obXS2OI%)fkd#fWm{7R4l%Z<#0LdkhTOHQG!l^;7D;}BAX0{hH8|~j?UY-rDYdJl1}9s_*y%H z29LuegLum!7c|PLVr!{feMNOJ_mF~Iyl;W9)g&rF4tedQ50kMMHW(4MswEL)hJ3yA zA_(#kCC*B0kdXN}kl8QF>42qQk7#3PJ_gYUSr}Cmj!lH+P|nEL z5d2va^c)=(GFgR%n{uhHk*uyWk(qK`VMS-!zQi|6(G#9BVzl z(OGmR^us7?zAC9WLFY68aeCH^PcmNVXfy=dpjQDpah7L$ORNlaEW3ags>C zZhH=kHt`g};6~AQK2&@z`ETl}7*ml0{Ykps51~Dr%lBb5Z6KY4$byyk8c*`Fp|3Ki zmq`DSM@dhorhg)hzUU+a&NEpqLxwAKm$-V5M zlYH129KGU|e8e#u&O0k0Igb0dWgEsX7`ODpAj%D|oaY`wDPeGRIcgj~yWt#wEfVUQ zT-$RK~UXy7o&z|9bha(Pw4z|vU%imy%lu*z7 z1JngBj5V_Yo;6H=nsh~_e$EQX*mrk_JcQE!V-7?UfoBJz-tIq>?PNdByLcwpPH*XX zpZq!TdQj?pY79KWL8;l&^Y$J9)(@H)C^WsYf|SP?r^dGQ5))WOIt^`$<&ke9bW#Sc zewmXX5N+GR_=>L5x7kd~Vn(K7#1d4&kp)BYdf|7@(v|icew}}RzfWO!lFf^zI0viz z2l};xn26@}TRW8hWr1D7fDQ|kAk?`P)DH@r6yK&!9{uzm5>x;bl!cZ?{yzyWo4BT( z2KTVwa)IlDg_TDH$|HnijtEo$sJW|WoAMtOxG!Ls*YqC~s91cJ|F}RUfVOUIl1zO? zFlE5BZ*OZ?{u2UM0LCE)<$qO5TuJYiZLJ%W|26R+Y7iWT`cDdKxDGN=`A_xxB5J7y zFcQJwLHS?r_ZsSHy2@g8(Nikf)9~#UPAOyKC06JD)BV^e)+SE6&r1mD2lThC#Wh#k zT*dzI61i8rxT$$FZYwB%M2T)LdrcucN9EUukDK#v=#&1)l5>&GM0U8@uyWV7_3c|% z$)Qw#l=ueOVI<;-sv0dGx!HQlW2xMdZrWmgVLP1UvD%Kw>Kwn$lc&`0%C9k4b zwm?{OpBb6+ficMSC9floIfEHZv!tjbMdfeM*|w2pg!EfV?nl5Zh8~2#(gOKmI!l-F z#tG(G^Xq5Msb7IT^4I+RC5xd`vlnY#|Dvh9#Z70mcVZJ|OG~F&vQ_?p680W9dvR-9 zFTbnA&ok8`2XFj?I;#e^AbKN*yTZ!9TD$|}y&5x?@DUwNaE%b;W=G4pwCX19rTlBf zvml#`Y)d!l1g{fZadx!&=3ig(XXLpo+c3e*tytj@dt?3$LR^&%vqdd2^o@cZiuynW zEX9>t+>L45v=S!sTDFBXag)?ijjoBeBf43LM(LO&OJVq1#A}QWpYC<5c#YGcR`#r? zvA$T!w~2SH4%yrLcJZE=eMW2B2@_3nr^__Pze5T($+iX;D3yPwAg3Cn=3+4UAwf^i zp1rxHdCN+Qo4W*4mmMal{4YsbbFwj@&D>b??-swgCSIIKXx?Hr-<5xlG|Bw9-|Y5n z+i()tzgN7LMcL^HL)|A{4KXhp=zj58m%XUHX#|sf7T#4=&IR1A^3b6`^a$+g2n+6sA?@D%+aHE|f8L2}c(ShRJ4@?!nq- zw(KkWvr2h;5aNc{+Wfht+<6bQoSP@{SjlR)jQ#n7E{NoG=(9k4ieo;p9bx}8@hyvd z<6FZ1Lh-GP_#+;4Q7JV@Rp^-(aaM^aOOu);8E|6+AQsZFxuXB5oa>l+0 zr;ctsqbq)eG1oFcaV>K&p#TJ`}DL&yq-telA`7`lvM`@56jfgf|NN?0QW22(G1q_Y1n zjKsm8)d*Xe3x~73q7@jH+U=_t#`ej5p zn3Y#eSZXgS|B##F@&4%Hw#ZzQ#irA~_f1^LS={vpmv48&UB`s+}T6HyRd0UKBWHNrtH zdWWH! z66W?IfF`X2GxTFz9W=1%ckl^`g&OU`_RJ&w!)j-{4k=^ZSfe(twqt}WR>^L#Z?_0@thV6 z9-ObVfSIoXR@cN6tO-NVg%M|G_lnbJD(9=zvOfToRMIMwI!;R|=c)BbSyvL_%u3p2 zXf->HVL!gaps*M#Kj%AAQLE;eiW-|qAeFWQ-co6Y>0qV(2oC(l@nz@u)tkPYC6Djw z?&Q5y^GTjaL|ZfNo!W15vHA;mHlaoh!074tEn05FAZ|SFF1L4Z#cSP3byBKjC?J1X z{V`eWWx?a0;Bzz!9?t=P6bl|V0v%cK_ydXFy# zM}}RDBx(#Bi>fMdN&>^-EOro;sH0nD;r4SQM1e}oWOjnAjhNA>#4L)Af-K$=PRyo9 z8S(vS9nU1KzK@#KzK@#08c3j z1y3nz2Tmz!2Tmyp2~H_$1WqXm0%sFTGzP9xy7VbUy24Y61mu(=9kEl21nntBy3NVh$uNOyQjkwA1xkx+C>k&r&6NS8gOsNLq2V&oAWNt|OTB2+z5X{Qv4 z;3-A<>Qjnz_CBT9haqF96bXl?6baZJSE(KUg;4A|?3ZS4($PK2rO=k}!5b~LmL z$EOxzI>r9lWn_C@fK1+8!u{$o@GF@E#~0uzrAOK6fL;cKpC8*1 zbUg^s6Ay8r0rn!qr*#NSN=Vub(vQbT2VG%+{U9BPBVQ*Y)+(F}k~E7nS}v z8~LE2z6H9UKWG1a814)fu6UeW@d|Q3nCA?f$65Z$#Q;|j{0a$I0_@w0cfp*mP({pM z0*>OHDd#JU97ZgQu_MkgC|P+s21IPwb3jEi8;wv7&?p*th{!l`qj25VevM2GSqeXJ z-II)TH-V;Y>svSVwD+JGg8VI!uwK~=n+<|!S%!N4FH^V&Q58?1Wl$YBs)*WlgBfbT zhG}&yv3dr+zfAMRVExk1XSTz-UB*pz{9Z<0`E&MvHW$_3$QIQUHOm1Dcg%Lk9=8(~_L%LEKQ3GW zSomX(Lk9UN;Gx1Ga~yIASYjy06ll0PlBBz@W?1`HH11r7yivXqGj6b`3LW@I+%j+cXHAa?gat3sss!^1?-^W0mt#}^( zE=OCknb?!ou+t65t<#j`nBQwkZ(l)DSY|9(Cgxq5BN4^Dj~MUQ5PFLCPI<#jGpGS| zGox(qH63Py>=@5L`K%}dyVFt#cB^3O&|vCtHDInGqHMa&L_~&z%@5|a!P{4c&l+!E zRZeNUn_ZezHPmHJ^I70YqohcZJ7*ofbD5jGw zQ9LFRebo>#>)SMu^p&GzeW1Ie3J1ss71ir_*?O$953;0?ds1_khR%aA{Ymi-=5fQd3v6yLfm}siP+U9yH`ctU!H8{6Bq?ox@R%=O-0x#nxEx(>%kuD#Q3 zuE$8OrxTW3kC9yW5SCnzm0aHeSm%0dnCn~LORgtlDYIiMPG2f#qYM?iz02#Qa{H$b ziCS5Zly^~vuZ)4t(tZ~jzfsR2f>%(&(PtsdVAUUD1xiZ`qHPYAwW59zJO?^MfO)aJ zUEelTNUYQq5{dI9;3dv7)nD|Ma@v;(tyLJoNPt4yVrfSxlmy8ur-Kgi=)}CWSWH=E( zb7XUL$X^(Waof=M`7c;C-dc0E-(Z(hdn&y6FZhr%VPi*6ce9GDbZQvpLIgh%RnWY- zldBp0q^1#(w!V>COjK+QBy}Q}8Cu%5EAz?PR{#T!RH3`IVv#?AfNj;xtq2`6zGUV~EMy!LCk&BxWh4j91 zZ%X{%Qi`hJ8pHo@mr`<3`1n!^;czL1fL%%vLbH@YcWfzzV6>DHgTkd0;^IpweHs^V z-hy+rTUs{YmL)FJZE7(msg(PH1dl9x{|@fVGrJbR38)XF7z*@=H$jt6>H;l9A>T12 zdK=M$hZ-ILsTDt%Fv`!_U#J5^ZyhUel7VZD?7}$P1bzTot1nN#hc^O+&{De9OJ0sZ^My&2GRY(un8uD!@5RomJoaiDP++>3znkc-yx?tCC~#Y?@6N_ z{NUS&p^P!u2;QNdiq4P-j)W2LG3WoU{hUH)SWuMX1%*!Etb$S~grO=Y=M*5oTqW2= zI5}rp&VnLH&V1nM@QWNT$jJfTcK{~)Xd-_>(Nwf|7Qj6EX)s_YRI`NfZJ6vn3f`#h zoLFFhxh6pb#!-%b&WQ2_MNA{l2R(S$aWq^o81Q(+Ti8#L2E0WF7G;JDVR4a@6DHQL zGzOGJ38I~u4YWB3!s3)m)(~|ClV{@n!}8`3tTZv8E?C|H38{?*MXV?K53E6bRKjOa z%tvafN_ue8VSZTUSTVpNJ{w8u zY(x=&>8OaBaVk9==0B6Aw4=r$!=xWku45aW1C}3SusI{j$q032m(P;Ik2OglGj16+ z)1tsOGvlL>3yRXh;>p$tMJt@ur42c2B;ONq0O0DyBsBpQbpk&w;7K1p-vJv=kfxse ziSr%UP}nyMsZD{0q6ZESSQ?xx))YA0VM@-tA)1q8AOfRySC_IurZXGNn9atF7y_+v zif{69Y7TPIHw&|BVw9R0%fB?>EKR^jXUF3pVvf!ro%PzO)ZDP~P^}r2GcU@mQu8C= z)N(f80?ho>X@l`+Vcd&Nu*e|L-kNqXn|gYATb||`rIr{(pgS*2siq-N(jXE7(y~?vpeaNM=x!Lq`8;I=gCWU|^$v+5$M&1t%ns2f;;@f7 z>Fk-OIpj0smVC=1Y=eRr8x>j)h>3B!v!Fey&_#=m)sr)EC+Qek4nfFkh80mCRRkJSE0My853KO% zI~@FrR@5Cllv-#zEn3iOtof1{o0M8^Ae)rM*n}-5VhAl2=ZiF%)<4Q5WlpRC*;=vY zqwl~>W*DTCK$B_5WwXkey}_0-sx4y-v9b~J-hy>koHzh zF@TZzQUQ!_a+pErrL+uAF*Oc($ABlAgbAYLQ)AHrJgIjyMv=v|gYIh6GP}|AG=y}u z8E@aSn8!>>nbxnY*!1lXC8>ufc%YKQr%2xiR`8`_K2m4dcEFGm7OS@+$xY|TKBhvb z6j330F%Y#!8EN>VKsTn=x`nZR&{uoJrK5~J()vNM4V@+#Pc3JfCDFjGR1e(BqFm_8 zFVC#liuB5lYo))grZFImRikikmaX6*<|7rHvK5>iui!NH%ZakivgO7=)Mp=E4W=LG z#cDCXcZ`M;S@CEC6Q|+)tRGE@bt6w3!s8FqbHDH!ja~L&2 zK!np5jGOda36mx(L1pR`FKYV4$*6QmGOtv`4F~*`v-x_;QxL_4NmPsl^|Y!8F@zZ? zj?bU^g$0r(vC}Cts4F!yDe)_d1{2ut?A;xV0;-4_gz~+A3JG-N4~X@yff~)h zP)xCfqeByQRk~;#tUDexZnfs*A$sI8G)hxTuwn1e>oV!zHIv8NESga3c262la06Ie zD~rHRLQ`6hW{1@;tr?#_gP(Ham0^cSeNYMEI3T7Dzzgy5looncL`7lPCLBN;tLoO{b?TGm( zqv1@6dGyxMHJ`MdBFm1+g3MMww&aKj-FGdH!`77$LDYdLEmBrOX6usY#Iv6p>0C58 zIVdk))oB%t3s_-Aqjd{nAS${rDkhsD8V$s{pV9tCh4l+l>OD@#oF_$`RHnNyd*eHd z2GX=%C~f1CIV|40k;_=h%4{3os>=A-L3)@TJ0J%^SjgCv1-;VNB(!7HHB2|kvE%dD zs6jLDQCKJ5njV|l3)qZ_NPqf9PFOz3;^aqbi*Wghvuv{(M4rix%ak0;(z%wU`@~ni z@}i)S4VhI`V5_Jw<|9?q*N!HrHNs`B;&kSv-oQwMb6Cpq667lsN~J~)g)35JrdmZ3 zmK%N)pn_{v{Uf;*N_3K|>rj&a&)IvbYTqJ_PX z?-_(sGSl?zxG;hqf~bm#%nlaaBI!ISo-fS6qT*;lI>ji#P>`OOrWIv^G&PL|-Q=V+ z8X!)N5b@3_qBx!+v-~%zQL8I)^G{T0C{2Y;tu!@*ExR0Lz--;OawJSR^vShjuRc-V z;MglK-mQ+ZDjgp_^^FgoilTV1wV}siT%Qj6Z+z|)>u7pFWxHT`%ty*rVY}cvtW}4+ z(|Z~@5Ug!_Bzq3-)>_F%uqtXQf`b9Zh^sBLk`0H%`q9vcp@+d~y4`R~j)jX@ykGz> zUtkFaYt`BTo@bQkDK;}&e2$KoiV}s(*BNV|M-i}*AQkZn(Ha-Ie!NMO>8!&&jhIl4 z7QQUUWowSp+!G2paF5M4WpN)p=7e6>SiAn7AC(Tum;w$9T^Wl$eXWQniu$in!kB=^ zYMd)ws6p16S?EF?Vx8+4Egv6up>5;iE`a@QV=+pO#!Vv*h)ECO&VgF04Ps8y83qkI zIIY3ZgQE6%_mbeeduk~WMI{#-n|O@XnZ1ucI66!NL%WNlL2PLI_>5EQoxV}$Oj{#>42gOo7$NGkP_Ypc8Rdw@7`-Zr_^Kkcgj* zsL;B2Sd63N(n71{nyAAtcO&CzXklSx6MUgu!^U8GDDr(NMOybeAK^9;7EHiW$=C_@Y(dN29cj_?Q~KX!~~ ze7V<)&YlpcwP_SUOh{*7 z?i}H*J;vV_ZVW~|{og2Ct&+^rN;2a0kcEY(kIL=B+_{#yu@M-JeJy+2Z6h=SrY%~> z7W7{E17D;ud^v5yh_;T~jOwB1hL(+808m{! zTHD&XwG%}E1TPKpCEM<<4I04FU^%daN@(h6)i^xpN$a?`iL+?g}EnNhrB6qT^~Nk#_P_tajl@FVeH_4Y(Yx-6mlTU@gg21$Dxe-kZwtQm;GS ztIlcXdb`GLdg`gCz0aNZeAlK;R|l^K%hr0S!`{|z?^n+AJr4)#zV3bYykPI6-jAK` zgWh%LxkH?VyMp?U1$TJU4*$aI6I3N!@B3ab4hrhl555lIrQ~UF-?D3*x3hb~Wk5Wi zJRgW_cAf8KH+VhWUe35f*B$)QM_zeoO|W_GLu>!#Y1p@OAM$dZ_j*o4gii(w7wp(^ zA&uT8Ur)ArKT_SnsVAM%bKz4@1*1N<&%1JWcjG^|Yzk^OZ2rhqcY@6Ewgh{h9?PJwIphK)Uq8(|;|kfzeD z1}cVV*F@9Vp}NPmww*#Ew&0O|b>i|y;!@Ahir|QwgWSTSV7~GA7MiwSFwSf1KFQ17 z=yf-&^ERTzf_>fqV9UpOo4UQ72R`8qnC`7<@CJ=r<>fYbn;L=-U$FKw-q%#n*IV2W zT=hdQwb46goOjmwYtFcEE&t6pW3AWK;0^A6Bsh3!uy9e=hqtfs%7O!4SI`hFWEK2;%zT9!n>Zo&Tbu(0z81%p6t{zzMWknXe zVfSr!{ybRxA6+|Yzjs5hXM1oa1Pt)o4tsrXyXwQi#D*Db&J3RZ=+tX~_Po1x2M5IQ zEtr{m-w$qf*OhtMhi7bBbB5QA?lIllb((ih_v{_s_69F!`ulfwUK&jFRs_#q<&EFF zFu3rH8Mg<6r!CwZJh<}xCriUZiTd-y1 zOtkr{or^AbbD}Ow&+m38I^OS9x0mnMI^Nlby^D9FlWsY~#Zg;ffJ*(WMj+kCBuCd4Ap0 z_x*0{__Ms7_YsuqLu=No@p>8-UcldSZ`b(?FWNcr%DRyY7w)@s`vu-Z zyI=N-&cBR(0j%F=uh+Hlb8Ft`?K*Hb{&}hC-i~o~3wL@guX{Ngy`GIzXRYyeH2}Ze z>lx?eoOV*~w~UiWqd(_aZ5 zTKI}P1Wa@)7|c~Z{vNG&ya#26-f(=BD@@75UU(}lSfDg%>JHj9RCjQP-4E`V>VuqM zSKBkh^eMasJ@cXYYiqB1uxriQudZEt`YCJ9=;8k}Q2AcY;a@ELoe1(gslq1^__$Z0 z+SJ^<4c5Zmxeg+sl~EzAf@MQZ6%;#*Umbt*;*F`P-1$E)7|9qPo`Rj*m?{VB^Sn)kDaWrC!kDAcVAsfLB zvwm_f7M0zbk(#6m&U~9Hcn?`(VK6M*x&b%o_#_50po;LvRlooHCi0#J*6*=}qI$-C zA=uA-XTI&-UkirSp#re7U*HrMx>;a9R1~UZE&l!;JEYpMbt|v)nW{%Gsj>+dImNDr zv_?pCeD&{}?t5zvwW+JItEYq3n{6?5BEuH*LmdugIO^c)8usOXptY?Kt3N zci(>drl*1#UQ5I6ZUL(5zo&aN;`WDm>6_hyeZ*Cd|3kC~-m*b^82%1tdhgI0u|}g< zE*MeAQYr5e$64l;?+wPR^{(H2+m;76ul4d8yq(YY{L=-aF88_)dnM0%rH=6Ae@{g> z)5dQ&l~tZp^ux&7-?78JN5Y#rx2i;jG9>8drGHf@>_ z%q-eocv)~}aJ5(2?auD!wFKus+~ei!?YS8L@hby?9>n0Pzqibv4U?f8J0{ddf~R0) z9W$%Elv5^+{7nF^`V#*B1Jpm(25<$dWh)HtbiH#!u+D33dCIXcbc*Ys6lG`*SCxRT zj(>^b&m!moZHIwkS*bxT(*{z<60Nb${0@Ut%a55;LNjSJoLXmV?Yo$QpSsbT+2EZT zRILqO2`=(}se;omO*)K8KsUa7gGCnvCw=LHX*0G2n=UxG;gr)C1=|+B;SMeHz7B%a zUT?=??{k>=4D4?4dY<=o1c$v#+@Nnz<`o~nl=`%TYdlQnHhMQW&(HWGoQK=Il8u{! z3%u;Ti!uG*=;a<>&AIIPCL=do9^wLJ_pz*y(Ref;(0GWe6H6Mj00VY9bdWDC*d(R7=?Ce?K zecCzfa`EuLN2KlS-q{_~9dC+A&Q_D-Ybzc?$sTV2v?sgS%IAKd~DN4Ie6 zx8tzFVc5;Snu%Gkv(!DY9&hcb}4M_%U5j2i~e7G-vVD(Rpotd zZY`lLAwq$w9So(Ef+eI-N@0p7eL!1UxOudsP`pW#n>03$OCEhdg$e~3MGabJP#F>( zRMes!WRy`H>rk~IkB%P$sHhzUWgMKZQyD=A*IxT^&OPVh^3kE1TR)oKvLZdXdFXve75g@~U6HO_k?z0qxj(;P?wKne-rPU1 zs`JeB;Pr6!y7gzJ-?}2*_3ZaIU7ntdembxsUD^CFHWhYc(?iduPcL7%Hr;h7ea@5V zi}$6gp8WCy7q9+6|2-q=z9-R`*!D}m<<4}+VA<*LbBh_X-snj>Jf@%CfyaXP7#Z#O z`v!L6pm03kXL3Z^bo7+6;PE$B+Bj!H*xJXNoOJj-+!RreR^0xh_I|!u8`Db6IyRkg z^J#yZzN&g!`pCiZn@`wu>+;`yea2wAabfy`!E}CCx^f|QY!|Kq zN%@Rr>&mx0j$N)5X4JWQA;5*{$AasBlfHOGdclhHvW|CMRxX^<^O|eZs}7~lUib() z@{07+7^LpLu39$c(^r=-y!6(ur0)Rw1r)a|1h_E$N^pI;@6f8vmzD3tWccb8%bFm$ zY{sD^>6=s6m!HvDJ}Z3)$lHL#9fL#HE=+$ig+1d#>Fr>7eQE`& zK##H+$BQDb1`lqP!MO4|m5a7b}_fVzn(5g+H>0e&E0=8Wu#JAx^M$;Fj zuR4^Tbm(FzVY1ZV#La83E-Oa_e#&e_V|w#OMWej7b)0)`yg6X@5sFS{+#Li&LCLX# z``Mu5{R9K*jUvF&xr|9f=hdRCU=}-)O8v!|XvlNUOm|eTJ>!D%E3QhvZN*2+Z=Cba zFO|=!JNN8O?@Vv*_+HhdA5zNNpHd3orTzwE`Mk(7M7Ec!@rFns5rDf zy=gFAc_^K4PFIvyuRQKk``c|?j6%a1YC=}mV&l)fCdCFUMV zpLYE{BM)_^2L^YVOHWS3j`o#MYZ4|@3(-^Vxy|73ocPecetGnLL+RGx^xQksD~HoZ zK6@KBjZaURrSeJTD_%Oc{L&u8kRjhU@oDU2Z`ysvJ!huhQois5u)6_E>Y?0F@9pJN zp=)GV6U*O;f%6#I&rg*P$=}OvO~2jj@28;i#K+R74&ReL37g)xek1+d zwdGafxbokYpLtWd`Va={+*6moh*jm09dPOU5zarm7FmAgp^?iv(>>LHn?B`w!+08o zP#fK{!(X;<;>d{E9Guu8mnXjZmt`}jrcY^pD&1mjC?A}7Yr3+0&|F2~;nDI9xu;BN zg}D2D)~CZ0(Kek%Ys>&1da6^Hr&rvWK4Dk+P0MQ1Ex4ofgJ9P^-$+j$9QtB<)z{Ns zL6?0rSeQQT(8akk%a64zQT6Hfb*48Ck3N*1T6RV%{pIUW@#>C?2ZpxZ`f&Qsp2P&9 z{K@pB6*7NCgp_YcAK8q*W)0Vgh%5_Q@%IfHGE66x!5gch@XbOpUdXpH%Yy0n`$mcy z*MRYVdtV&e=tW-jVTT~>+LgH39Z4-nl5QHRJMvW*)xurK6cwqd=}mIS_vvzcFf9Fr z&3Br`qPh4#fBv8Kz*K1V8V)S%w^U6zqI^`MABW)0q0b2@I+#PW;_LLnl8TzLdnQ$s z*G(?Vo0HN_*K^C8YYntq%S$S1%a&A>2kW%FTd!A}xC(+r6_p<eMHTx~>35e+s#s9>U`0*c-iq0E->Imo`)5}Og~$6r%~4lTc>@fq>DKGK z8GmYM*GI&z52qJZRDEc|qKetKh+Q{{T{j+4S5dp8ysl!|4M$#7aWIwsx74JHWw5Xo z7A}B=HL!3tEUbcs(-u7jOCJ}Hi{N5<&cwBS(33Z*YlRpG^xRQaS268|G+F{>X$PU> zUF$VXS_0`OQm;mD zTjD7^bD)bfN&hP*PwH()J>Kp#KQ#sp_3~0r^pWes%6GNl8nd^rz`*6!K#?c)4r)D- zBS$ek1YiCp*q}FCG<-_Z%TGky4JgCCIDg3#8$i#SIZrA*;`0{icQ;ADyHWbx4#^WY zOk7ft@0o;5@F2R{Ui823phdrnOz=oW`C^lM6ECrOO+OTQm9uJ%r2kTRjJF*k?}iDB zkD6#N6!XhWT*hm61K#&IQ~98M8j$~2Ouj@~$;PG7)t*{wD7wtwSUcqk+G+9R!dA1% z4Ru5h;j>%$XgV$04$`iBK+k&ybt)Gs?pEQn3 zJM9B~t@3HLY$ACf1Kc{L+pTn2%^zds$>CJlA4}#zmDi;FE8kITFuyO%bN+aEql||; zWIV(I|EP%#lOC+wTlbwsk1Tq0(PMSropQv2WwtvP^|xt9L?E|DZ&!N|pJiNe3a-TeJ*dC?%vvc1jDr&WGILFlez_F7&I1qOH(FCG?1H~l zeGpe>zEC!(`SZfb=nZBlG<~*Md@KQv(IfHYv9oH0o!L&4Gy8FLyv~$eR%B!rJB3gD zd-mXSqvRjW2gvXkVXKgJrXlN8BI`)Dxip4C{EMB!FaB+L+KJ>~j9WIj>_P=iW@f$k z7u{K}Q;8w6*0`B$z_*E zeTZMKDgR)8Eg*d8!TdGj+&UACW#EfwU18H{ApKeN8C81u?13CIo`P^0reG%TlJ5bf z`=BKgI^`?m7khl;U+w~ZGYFSVULEBd|G<``Grg;B@=Dd0dc;3T73yK_+p6@^4oP{e z3HaeDXb0Vyl4nNcD4n0m{$^5<^#MZF9Fix5Z~TiGUi)UshT?4}47#;``~wrv>#*ke zODcv_>B|m(o=|aK}cwJhll-27+vB&p>BZo@5R1OO>ucyq>p5CE{y%;rEwAF^lb2myN~v#BIT+ zzAcTZrbHIwf23PKvw3O9((v2d#x~D|mc#PcN4}jl_+afoQ0k-G(eHHgyX=MEb;f&$ zbLP8h4LN+0q&-OZFm)E+Ucv{xH|6XHn}+go9?S*C2d3TF;s#UX)81gx*4LiP=KIWJ zg+bw$r!Vuqylsq%@RqQ^cXql4x0;s12UPktcIEU388%epHvrxEptbq+MIfaC#BI(N z2R8I=#$$RN`1wY*wHNPbH^1c2do%W{7ZzoC;ieoq38EfsY%LWPWZU7X0z=}4WwUsC z(LNrHXiIio-0RD_IyYqG6ISh;8*;4!_{!Y|G{iFK*_{izO*iV_lxqjS9<#aKw6d|S zwYz&gLe%z`!j6sCCHJk*b`166a{?DdzvelBuDiUqqc7OR&k&F!2(??=@1zzoDfOvX z)5Fozhdfz*-R*pmB8Yx!*L((baUWiWy=73tE=r)^;*ERBC6v6X8Z;q8A-m+z>+q?^ z{3T8L?c>FG#I>~zy}4^(u&Zq#$cO1=O;`UQKHsE$Fz6yHNeG)lzaU)jB*yZ>@?h4k2sJPT$#A>C3{IrpHJ%fzbln2k{ zpu9w)Z>i+Hx=1VwYDNg3rz?LbdcH1xAJemtS?=LqvU;?D72&58mkJtws^H5Zir^m< z^`>A;F!$7v!x8$d>YvuCNs7I!H0D$7&^Hw{k@ZDt4^W{Y7GkZ_3pf+*aGqH+OF58Z zDp*5sWr4E@f5Hh|^Cbo8Q`C&>KZe6a|0cd{V)>cy*u(Dj2XQCOs9b_G@wH(N$)xA+0T@6aH((rGmyd zrz8)tNm(61Pmmr#1I0Ok$|I$OP5qz7XCIt9^)d)-HUhD`BkAgow`+BlJ z#<5>RkPL-=eFA&0qgJgIgcDmW5ePVum2u8@jlFUuo0))&*GRCS~z($cmbt>6FiODtK*(dP>0`hA8^) z#Sj(OfH&sqU6?iy-0o0bXRSKE)-YP2XAEHkf9+6B1b?F_+c8+0e1heHv`g^K4pmR^ z7)9B-aqX$c1x{!^!GCk8)dVTo_8^v~IH9Wv77DHR#&ln3Gljn3gsve-F|E>VPfp=$ zcKCPlb{;^~7nIJJoeGXWcJASmg7T!AYEx^3qK}AV?K3IVQL_q>B54+Fb2OnhB0NR6RkOCB`;;Q9)h< zuHssPUvj9`1gV_xT06oLC13#*S2e3VsGkHK;hXi^#2_DB6-@V3i_?{Xj&SI!dq(%L#*Nm-m54Za4dc2ZH|!OKPk!*vh>V!M@aB_ zMOi|YUJeNfF8MQC*AlX{TCvcP;HC&6OP>h|34SX=$kP7`2?-v3Vxef3PF5^L6U;^k zS?UN034S0#$kGELA;BL;2w6H15)wQ?pRBU(Vd+H0LPvtwoR~~L9kv?vW#SC*16DJcaFx?au-|c z2xb%|HAfZxTu8>KoZ~`c9pmqk5XDGivqLjBEZYqz-|BTSqXXaSW?FrZ>ym2-(o$*o zW@q<4XZIR{?1Yw(rJp%7*AS$+mXM{enYAb1VhKJrei2tx7(S2vM<=U+;HRo;jk53=!9OU<&M{be z^9)Bwuuf5yFo+!#TJ9v&6MWgBRuiNc;Z;Av((g~IHCz#O1nXv4lqED*3;s}Og_F=s z@b?b2h9JcVuVyE-Zbq%)m~gk~Wp&``%FCn*78W}J^-C1|szYVIrr`4-isH-FO2dtX zL1%jXW(Bu7REFS>3ahg4laP+!&mF3sAk9oncPFTpv<;b=;7iVcCK`}-+%p6z1*=nn zzY3`c{?4Ji)S1^yw6rX!^-@?)X}TSo3_-eYZZJ@Z_3Si^mnZ-6h!B1)T?m&~&8)GT zrRUA^r0i1efA6F;6MRZhM+5`YcTPC}l%jPXa&lpnbf^Y`=Q>m)!Al&ff#4>G@=~-B zi$6yz01XJ{9IBDvZHlsHvh>-Ikl^Pcgj#SXvg>jcGX!@!R3kx(L2qyz6xglj`(3RD zf)6Rms;UKd;#~DIS208I3WsXkrr-{T$`A~d@?1(rv=T|4;09%s4hF6pVPTWw?y;i5 z&5mRp!4^eL!6y3@dEE7_+pv8^ECn9tuI82MR3YQ#9%T}e4HlB|@)jjK(Q$KRn+oZN zmF`|WBMlM!nxc*j();UcO@XK{08!kE#i0QM+I1sPLREqVl>n_6%a6zilZhuv6>dVVmYXwWcsa92q1mCbU*CLjeRK!9Q1&tbqvEDXw&9 zBQ-i3!NQ7ubWjUYr-C+utawE5+X?@9>|H6(0e;=~#JW=x>Sna^6?%sC1lK7l+0quh zx;v~$keSj}WNBr}QbK}Oai`lAI;3Z5C8a)6&uG-3uhv{2Ax_?bAP27Hd5yR^;k9MF zM%=>iS{1JmM=ingv%F@d_J`DN#>wo2%7CkdhI_1SwXOs2^d8l0ir?RHA8YPc(l@Y2NFUSWS?U zkw*wptSHg!ln5nq7Ul%sq!7iR#R&E|iH&4S6F@~Ui<%-EM6_j}Q=vX?i;y`U3LIT#f#dX?FcJQtUiw)`LJ%F&9B3DU zM=DBgmJvQ)aYqFM!OjVsQO@{{qK}*4xDcGKs8|g?IJzRNL9jl##ubY04Quo%_@NL* zaHpbTVy$}N-$wPs!=Xp$B>7~39Eh9GDY)06G6bJgR7Ef_p}-*{#Q!k7zOC>&@jrJg z8|cI;XH5gWv^qr54eLV`L3$>x3*B^kSmgl)_c;`Y4r?_2-l#6wF z4>?v|r((UC&e%p8duQ=lj00MnG(CyaV9U=Lpa4kAKTRKHF2D+?BQ-78L$Ac-Ue zkrS81NMd+kj3D?66>erlEYM8}Go7C*JxR-gd7jd7nuHxBb(|)_ zJtQfJ@3vq8NhB!<__(Cg)q5*klh=$8W+P!uNJSXr3Cl!sUZeo>1wpRe z?HJDzXZ0W?_<+{6ge?7Y$dTYn5ki*u8wYSC$lpj0$P*`))Fi< zZf$~bYm%>Fg$iCCqG(ZPi0W4G>JUYHhC`GJ zawoQ2QY(E#sl;T$cRAc#*Gg1b=m>K)D6VFoDdoa1sEW_%S$Msm@F_au5gg%L6qhgn zkfhd;WUf$fV~BDdP~ct_cE6s{h6MlBq1I5PQ2d%WqhXaX;$$@toTP&rW)B1>D@w9U z!w5_BLqdWJ9IAmJe-UTvvQ$@m2KQ@K={2WXrc>E&bL=zsD)_w+^^AfCL)7mStZ?Eo zQx%*MqGl^NKSag-b(<=~WsbBm;Ww!ebKi~5d9NacknnYdge>eUASC=~At4J#t9HVX zFpV*ySva|XkT6X&geAMWilE zzYYl%awlK4da8DdtJOr1%7|+9BP`wK2jASW!KA{eUBKoz>33Jq};P|+Et0LRa-gtZ9%gQBdj zSmI6-^dk6HO>>rzCH{mLgaqFeA!O+y#e$IFr4d4wnnFT?mq!R$Y7Yqsz9&LBwioJ? zyih;ld!atb3-u$u7wVI|P(MO1taLip6Qtd?pRq*Ku}C3EyDcG0G#!Kl3%%ekQv6tG zPVz!?f)|>TywIHBh2|tLG$(kWImrvnBfb}!lf2M8;(MVv$qW8!=75HMI5leccSZfq zb&^JcuR4@>bAk*=nlK144v$a(U4Y=*6=gdW33;wkV6L7~k>FX1dV?$0DqAiHq_-;S z#*z|A#Zdtj39{lbGDAFh;m!$o0H?fa778=GA)T4)1{Ic&%P6T`Ns=<|uwJ{u?Axa~12Au{*t>&^sJSBSG>`a7~Q(A%d=+(b)5}M;AT)Q&yz?S=!n!FRti!)9# zuTm52X)e(=%vErKL)8;ptte|TOP>r0@9kU3pBZT6FW{Xz$j=L9`ljx6!^P=b;7DVy&*2@M2Ut0K6@ zrLt=RKa)}Ru_}9Fa1CyI%@|>Msp1pj{Oc-}#(;z%xmHG{pFEu674khbBWE~y; z{Rdxic+o;6p+69(1gYd$uHm|z^oZbMQhuxoC4~^{tW^M-5d4awY=g6Oe@Mu>@$>PH zq@Eymy|7LsNQT0`euSlvJx9Jc_kj8#Xih)pr~~4-s`-f zmE$G_CIlWysGE45FrNdM7`!(a#4jRQrtETyKRGo*47Fj6xHo7>w_Xrwgt?|gn-ct} zGp_$S_iPij09~B@n-%dTJ>v;)f^)an(-ZveZHpbNeC~1lRue4bhj%p8C-GaY z)!Zp=K5jeF`s9TWQEawkLq>VB$Yyqe(I4wWG|&!OrGzSE)B(bzED zJ=1(~Ysi}$GKfB(k>~S2Q?XP7))NdFts}U^DOvCH_EO9qrGClPY9M$)%HlAWCs?Z} zn^CliJN-tX1+HR~yQTn1C<75oFs#)WuSK!kUO+8^zt#byEVwmZD`2&Lr%ye>f@u39s}zj4!&cN4s?U|P~V!qOi@LV_DKiQ5#%5@!IZ;N1kj79nKmw~7TJ!SAW< zmLp3)c0=mB3DR0iIJUiOX)i0nyVK&;u2lDY(V4o2*0Wl|&q+S3wF>6E1i$M1y_z7s zgm?dpUdO^_=ZOqK3N&k#Q+@VXHec7}A+>%|Ziw}x(~6p{E&C10awxm!ciXoS$kV@YuFuo2u?GR+=2 zb$uYzm1eS_3$(2tVd^yf8PQCT%!RC& z(@t?tTT8H@nwOp?sFb%jX&HjE6@_GL-OU1%K#JjlWRvV2HXxMXh%t!ELUF*G3m+jgKoxci`=OXLx;h zRJHg=Jxf0){G8%o`*M{<*-7c(fXaKtsn9^MY>IV&?GkbK_!aAuD*C&%e#Pdbiv9*? zrRsCKp3&_I)|6D$uUMZ{(O1>4*ql`Ha8zBJRMCHGgNCdKZ6uf}X`^4UKB=N_qhGN( zsiJSAUvX_xMc+ndg|})*p&jGF6(^Ag-alV!sJzY)ulxURd8(?;1@e9^SLuZ0Y&~-y zGj1tg27A1Yk2QK8)$?vW|5VTM`Y$X0Kj?X?&Ib72*f@RsMXvF8pT_A=URG;Rr|bD6 zdj3m2e^Jl7^?a|M`F>8mob#OJme09*=363RCC-^c5{=_}bKmP8CvFND>Un_9h+pKxN>Nx#FF?v2nU5x%emHuTt^SPgCY7d`|=0nzTc~>djpq}5a=V3kX z)HD4buRm5h#pyqzd6J9XjJ8vYp5yd;l%DsTNyod}ar)0FVwax3tmm)lnd8ILT8^LQ zsk}eeGrtcSzdN>8ugB|idD^Pi`DEigTBbb@7ODS);(x4XE^|3f9aKEWow$6CKW|fi zp2U8jXWj-ouZX|zQapDx?$Pq!>6!g%Uy=IHD*oT}d{EE4i^cv_uJIbzpZ%*+ud{z$ zS%iLv;ywi$K5JdyOwAaz-Vd7EF=!+&%g`L^^EHt* zhR1#inyN84%S`9s7<^6!&4Cg$^1-S89NyCr(QpxJZ68B=GidT-(DZ_4bPO697ly~6 z`2=VVz=;w+a14%Jz&vX(;@RqMe9owSbMT782+dbPQ;EGeTMIP!I#mCld?5l2?P}r6 zhz=vQzJpr($I$2BM4u8g)$#!$VTMCwrBm|hiB+b|Kh^E6gRNQ+o6;$XlIT&reqewY z6F;e$EV^^`mXHyIfX@c}o#d_yP@NBHL`pif41W<8u_KL(l5OOFJd2X_D9}`mLBmHj zB&yP>2TlnB&hE%12>3YrQHDk&`^Q|x%Dv%qN@ljU^$RH%DvfOMrBgNd>(gAUG-7c& zbpU_;W3AFu;8Hpzvl(f*=#f(z8GF(x&X}S!dC=rtRzE#@QA^h-pQ8<*DhLu!g$KvV zYk<0>Xo_Dt6mg4X+VmtV#>mSml-Q%vjw36vROme-ltZqp`XSC~;HT#Juh`D_M1a z7|&=Z(9F;)(UY{rXov{X_wZd7-hFo`EYVA=UCe2bLuL@1& z0_GnneOp?`=_5W4n@IeM&v%*rUIo~;DO<r!|QG`HYv zWy#p@A1{Jt3(%!xNk)=9WHd>wK{(ZUj3gsT9548v~Ki}j3jxe66kblW%Qz!q!;XW zQCB=8NglEp>2B0SrGkU~;>W<*ej#5mlqr2-&wvhSsMcqxmes zsD0^R{ZL2sIrHYv6(5>RB9(&kK$D4JmPsw#zY6&@3QYvl0n8`{Lle)2Pd_kn^D(To z9hes9ABpF%>FM#m0?k1~ZU@~Yvi(x;tc1c^TK^To1iTvaGDJ?bY6kfGwKa2W( z!eu{bVC+iCcd-5Ao49V z#^30{oG=Wu<+BWsM1S;glv z4%ZD$@qW4wTG)QN41z>zc(9+o0+j8i_(E>4d`C9gPhWulWQK2|*Yk|!_j}M(mYC(@ z^Oo{`TC=8(_5#aUEPV*9VjAkuT?47&r=%>wUeJQ;CIcjB$f%RmxQ#mTZS-K&Jq@%t zH=RNt7>-doiMpR$$f)}Zh~(|NkWQlRO!PAwb$qrxye^PL-8bLPsN?fuQ5uQ5-9VL^ zuS!JSf#|gnwHOxq4v>gi?;>hWREU-&qG}E!qAEdWBPx%YC=?uws1u=rji}DHHksZ; z11dNkUX!^^v53l7pLf>W1@i;f?ncIJ)EZ_jgE=3V?dWc{7x>v2--R`EtAmkRm!Vb* z>f?l(%*Iw9X?NNCfkO)pW@D#MY}ZIg{Wy&J#?a{cYnqEgiLvOxI6Mfna7dcdN)3s_ zj#Z4qyEVtjmGF=_{5VE58;2s*KO_$Ct705}&L;py;_v{@W5wam&;&LPkAW;-oWxkm zVZ_*W(AgNf8B(R4!h*p$9eSy;7{{y+j`Z>w6Advq4 zVb|aN7!z^Q7Q-dlf_`2C6|A2(cXhY7wf47<&(9g~v3`c&*ztP&yrh|a{wBCc&yODB z=S7&hTR$g{jN)hM%VYWZMf4r(=Uh~Xmc)m94#S5n&WCOIrgKm0me7TUQyYTI#%fh^ ztm+<77|)WQz_j3CjuKgi@8^WJ&>SWHv14Tdjjp?=f<~?;&h!>HG|g;YzIZmSOK&K) zM_P@ZMp?DQ6Y9nn^qkUeSuG>l5>Kz>4L*((@%rF&TR&=14H>dKCxcV ztie@qa7~Fe71eGA&3^E)?G+s>7)hg`IWPvzgP^H|U3Nw-oSy_{JI*+1Zj`4tTVPj+ z`2)aFxXXCM&3~-U;vcz7eIn|I$M|Awi-b|+V2sIqR2ySek?T_6{6~Ioizb0SGJc8n z;lWj{vm#ZAi}YMbCvkXFmT`D9Z04^{LK=y~^IRPAhvMONfn<(!#Yvna$x{ya7ds?Y zcLP0EtUm8zRetsB^O3RpvuGNzD4lvsOo}Z^JZBCgo;SF7z8@7)so-Fax(_PYc+U3b zHuvdCfvUe)yzDqm+kd+ktpcMA?R3bs{=u$XL+O*QO zsYGn_V1I9he{6r3z8pQ+-({XD5t_8#sWx+ol}nc4y0I&1{bgwu*OsEuUF+Rwbcw8_ zIf<3ErKxKMF4U)h0AMvjK`>SLFI#Tu)NK3}3&TV0x;z6^Q9jnLx&@_Z zAZzC3mm8g}Ea4VCM4y>;b#;O*MkCjx5AJh)@bA#N?+|q4kUm)N`rt>=a{eJXv*Kjt z%(Za0PbN82f_lmCQ6Vxz{zMinUhc9$H!4UIKc4nI($-Pxw{ zRtejtJ-Pn=cm~IKi!5r}6#3a##aPe*8rNP1GYCv2TxMrz*p3?90Pa-|<44O%@D_W* zN<#+pUM2kF^Ggc<~7Z)u@K$b5~GRYyAN&Gv` zB1b;DX?*ZfU zl4$uHW<+Dn{k9)QBs`D&WAnyV$nqmWT3O~}W3{s61>4G!Jt4T@U@K=`E6al!o3rv% zK(2qlHT4I;|$M{;=_c~{Bx4TwOm|f_OkkAN+q*a@! zC#`(vwQS|Dq2%{vY2|-%t^C=TRkmnWTZhrgt;j95m4ASW$*r6}j8@+6T6r1xh=t+7 zR{nr%<@`WysJ-uu{#7PeE!&lo3i2nVWH!)8?O- zqMco-WwiSEY>rm7@Th-C^d1-^dgZB)?Jyk80i9(gIJVSelm>k z68j0i`xx8wevw$9u?3|~doe#8YfO>fE{wIGa4C|oZHt^IM-bxY{U!WNAAZ~U5YO;s zH?;P)cjpSHq-}_*O5?-gbJ6#LW;gCHhkJt`17-s~X7u|sFp}A%C9P+62_{1GRbWP| z$cGugN|zR_gH6$0wb#>vEtHiSh0W1}z58i|ik)3Rjo887{RC*B2=tkWzp}m!4`z}| zj0Iw4It7yx4#@yt+R121VGnniMM}+zvIRk0$zApCt}`XnS)g$wK18 zw||8`oC1zO#18S{rw_x2^6TQUM(VB3hrKZ=wkSRvJ`5k$Iv?h-RBtN`L&NBO@T&D; zRib}{=#!v1II}R1eF>P#QwlNP1g0f|`2jGJ%);^ge*-fb!5lFO^UMh5t-$0@Ev$7q zFuNm|i-5_@CXF8nE8rUu9vKlKoNL#3;ss$ zR|=^_)I08DMEwVn*Hwa!91>BFxQKdpVrb3<%@=B!MK4R7I!G4X@1ibwG?y$Y_eyLQ zEk2+Bm5aU7(izz)YI)Y^|QkW%~(6hly6TQ%xx<-1$ka-be&rVUzq)^~LRvzv3;ptlcC zlK`{bVNeJ@13tA8%)P)Ih+yO;P?_pN4Ic-_^<`lbJO|7UCtWZHfw?(?c@>x{+9f1G zInr>8lVyDfea^A6tgXj_CLh7P9hhNB9 zZ2oC4;9x=KpHa{tjI<9P7op>dql&htW<-@yYROU4zsDSv2K5Ice54>b>U1oy?9AZ_ z21tZXa+FL;!2tUFQYHu9AvsDEhI2tvJV(inh0RfUkB1;+266=Un(PeZGYDeeG|5r& z8w{JH-j&El`k?Gy+Fo#aB8}vzVYIf*Q3oL?Y8w0LPe5m9GIoDeZ?l;0%J|uBB1&xc zMKOM4k4PL`>i3nU;zu}}natB{(Xy#&uvDZmmv|)QCrM8FF;-dGw&9-G=iCb zJmvt3(ae88TjzC2Z}Oze?|dV&=I!vLPw}Mh8JF~oC;b^u`ZiB`nJ0bUxTLT2q(9+F zAM~WZjNTpf{QhxCU*<`F#FH*rG}0FHU+|Jn4Hq>Fu8MpL@~|j7xg0C;b6W z`Z`bg)1LI_$0dECC;dK8dXp#pF;DuzaYGBq*h^6!9dD8Fpq*snh z`fN}7EuQo_p7c9C>C?s~eWoXUhbLXuj1h0l-|0!O8kh7cPx>}b`gBkF2R!Ms$0dEb zCw08Dn{Y6juOi%h=Px@?6`u1^2Kj=xH?n!^ZlRn*(e)G7bzu-xq>Pf%P zlRnjxK0Gez&wJ9Rc+z)y(x-URZy%TRXFcf?Jn46N(#t&QqvMi(z?1$8mh6%KHSZ2j z`pY0t8ePNQJud0bc+y|=r0?{kAM~W}9+&i|J?Sra(r@vkKkG@qe_Ya^@T5QMNtazm z^|Q@~^MCXPN#E~DmrqGYWX;>=Ntfrblt$Zq&$w)V#FPGnCwGyilpB|U=J)ZOjJn8E^>34b34~$Ft1DCQte&-XQ7sd(!3Ycv0yqJ?S@j(w`rf?e}@o@A9NC@ubT$^s1ruxP#-8zT1<2 zhbMiZC%xU1{_?n_@A9PY^rX-8q_6R$%flcblO5OBv3GH|C;b*r`W#RCiZ@95U7mD# zlcTn&_V<~d^z%LG<>Rt_)RVr=lRn*(KF5<@IWFmUc+v+w=~F%FGu|NSw|mmNJ?T?C z>61d~`X=62F&_(`75S>%l!zQPz*HIkR3+YF(PtQg@D74hZz`yTWju}nU~0(6VE(EA zQ|6xSv9iz$Qn(dm?%5b(^T+EK3BL~Z?*?Kr89Vqi!hWb`?*=B&=yUHcf(9;vKDe!H zo^OaUleXf00n^ zPM_R4Istc}?42Wd54z7s?i_6|apy?H${o7xU}EpkEdvIKf`fPHCc}X?emYt=<_ZV^ zZs=|85mXq59fKQ&dN<;o4`Hlo=C5TR^wo9wP@ZLwXiB`(r_Up8N53fg6pGDAXUX#r z=m_8=5L78R^lsO@P-ou%D$rT`&b|`1^X}W9(5`tq;T&sMLOfgB&v_BeI0ntR>$p#n z@?+Vv%WoZbSJAZv?;)PM!^>Lh!bs5ZLf%?tG-R#$@?HbQXtXS2w7f3qqECeLIZdAQ z7d`3Ed(t!GlD^H8zS5Kaf+zhEPkQsXq;K)0FY%;5>q-9yPkPI^qz`)17kbj4@uYvj zlfGeG(q(Llw);F!y4=r?(9Hj|Cp|wd>D`|6IiB=KJn1_;>08DneS;@`rYC)`Cq3^; z-##ws?Vj}Mo^-yI%{^%_e~l;o=5a}H@uW}nq~GV+zQ~h4JTB?$Jn2(B>AO7Xb3Ey{ zk4t*9Cw+n^{Vq@XF`o3%aY=9Tq`$(kiCKN#9iH?*U_6cH`Mbv@J>yB2SzM%d&)exq z|EVW^_qe35^rXMwNx#LD{+K8I{&7iP=1G6nlfJ`~exE0O&$y&7@uWZFN#Ev4|FkE4 z-?*gLdeWcpqz`)1hdt^0$0dECC;bsmdbcNin2o~kyFBSDJ?ZkjiD<5Sd0f(Gd(!Xn zq%ZNL%l9v$(t`!@-6yx&Dlwm*=}EuClfKZC{>lU=T~|_1LZ7i#ks%+hA`4{cx*&X$ zJcPy$?jAV1l2)3pV-+dvjSow#B14_IiY(AsZGX0e?ObjB3GJFU0e-P|6<k`^dMLLhQ&{T*&9)`6|H!E3J(b0U;_Ml*n= znFkD?vapz1U>F+~vrbIGAtj612+ZATg~ePA%(GBfBGY2t56p`Wlke~99qhnGvxi@$ zG#>*E*E_b>7l6rYrY#Ew2K({Wp1ywjtSoDN7c_h>r7XzeT@M?<*xm&u&Hn<890+oi z^>biq@eTp;s+DB}ztBHNp)2rh>foH+(w%L^yL3<^^y-IJeoivfI0O)Oi3j+#xRu@T(1cU<*GWj(F@w(9}#VwBjyc? zLd-t{WAC0&)&XGdbFCxw|K0GZDyUVC{Y8oQkk3qDqTZMf40EP>tlj>8JM>rsX!dEA z01bXPDqn(X0q3xFHiKrn{)WZ+@I%0?Lr(}J>f^xFy4XPV;IqI?!#R|7KQKY0l^+G> zfrzC)1tx06zXS6`gyz41IS|q3SlMdDVRi1w^|a-;Lb7X}O}YN{eFM2*7zDQ6@d}|$ z_)bP(pEsuGPXwPG5xd?2%yw5xWGn^dfU_b$WWP9LpWP*&HJ}-dXee*wYKcVMZNNML zcZNRv5-_!q_<0lLNeqYjaIk-{Z>T%4zf+*?vp~}wX|Fn9!u}=o z+kx30k#&u5#{V#$KZX+L;a2)*f!XamFMPfZ%%E#8Sc;4U&pX?N<~yKiiPZWbFx*SA zoPP(*vWPx!!q0|kBJDL5m}c+`<9QY^uS8m~4w%`Frh6cllk8`oz@dLG1x;l{R=Z$a zE2BbiEilhV+Uq00a4l?g{xmRE&aT$=c;zl?wnSp%LD2C1Hn!GpfC;V0X7LW@Y*s`T zc>Yz;L@~!8mbn(Td}@Hcizf^I`ZdNXKtMr7rrR-`vw z1xz?|z`M@O;JwW8F&`D`?F;TV7+UcW)Z!kR)#vlTJmO?EcIR?p!G?%k_k-pj{)cVx z5K7Vm!d~z+F!J_>(9h2Sv(0e^ac~HjXCoN-VeNepOa(B*k$KB>V0J`om(f)Yn={eh zyL#I(#zmyB0L}i06;}ZBg6mC~IdsW^|_h5w0H#h+u1IdOMsChv|YYFA@{_?=U59}|(M3x*k zgXWG%>wFTJg%QlXz;GYQ*7_bW(N=yEnBC}Op*Ma9Of4oiaIDHY<#>#hk!U#!m=^fa z)`IP3XtclI5e?-{^75Xg?U7!v2(`GgWc67Kj2z*((+$joh!r0I=81^(zXIl#2<9&3 zBU~-#Zvs<=Qt0Q0f!Xicy+a$UX1-WTul}p>0fSJVSAcmDm@qb`pMYLzYEjl{zyv17 z$md*Oc11K?3e4SxhPAT5tc=jS2N)m;Q-PTf(fJ%; z_MKZ8QA>b{u96yn+2UwSmS~OlOv!X^zx-85r?|rO9?kAAna~-VhEGvDSGyqVt=9Igqmc zvwp4yW=TYPEieb2&cdfbYDM_80n-%m{8fT+d^#{)ZbQvlSIe|JP_@8@w%>$W8-TH+ zF!DV9AxA|t{1|9PBUx(%nA;;7ehrv)PC6I{4+HZ;1oIMIAq1H1IudWtZ zksj9$j2vNXZ1XT50%mW7&nJMH8Nu8Q%p(y??*pdlw8FmgZD4jsJpU9hvM&)@`X9jT ziL`}0lytyhvi75D!R--CrwR>x4F%Ab?K&K7;rt^O&H~MzNb6h-jI=>$dnYh*gqZ7q znG><}L%`hSEX`u&fJsxZC!)`%K{L&@U{*g=(-M*Xbd>=G?-litJ4Gfs*IV{{ke|(V1G61bq#h84z&084Q4y~ z`r9DYymPt;+1B2}pc)wJ8;eR~J}xYq?doam%w^ZN4&*RMC#uq#&u0g>=5s+$YcFWq zQH~R4H4k8@FLud%uGzb22ez14Q7WI+K`(x7)$&U&x-7f=lE$XGl`FGLmM&U-QFc{b z)3T)v4c7P2Hp%-glbi3U*{Fy*KHJ{M&wycHa!@|6hh3OP`B?f;g2nhWTh}JMvDRL< zTcmMivoRtNW4XAYbs*c;HrR(Ki)oN;M|;cWomh~SrS1Aw?7VtpHkA6h+jCpm^6o8~ zKArJnYgaYtqhw% zve^}j8?q~xH#VU+WwZE1WVRpQDIY+B$dW>k?YS5_<~&T4WVg@U%Bj{63+zL?VbMIF z>x%LrV!O3iokz%4*93ye_xE+;P3r^b;r&5(>%gGH$hU>hvM8CZNbzh_MfWH9VdJcs z-elWwKLr2JJ}W!ey1qMSD7*Vw+s!^jyivGOD?A1e=s8O@u%T}=zAM$y(X}OubO}{* z0M$y2FzO_5s4mAeQBq2t6Acl!} z7hK$QscS*$hFwVWSLfP;o~_yLw!Yp?HoIiyRnX?FyZ6)#9 zw!WTxcdjSbI|$YKbMnEhZ0A5nYghMBe=fMFF}t|0S8nV!BA-x zUcN47Y9bM{3yO)EQTLjW^STk0TElv|zqJbk1H0J3;Oc=~|0;awVJS9fITB)tJ_Iz0 z5Zi57tz`37nE>m*Xqk4J+fLwO;|sg}ef?V*y7-P@BVIX(eh*{vxvsMp%+K}@^-7?k zI!0xD&bL3cm#$uNX|`eM%1am9&bjoGCH`=i z%@(g9z1g~?ap^LdW%l*EjKnJ@Y3KNJ08tJf#K=K8Xcy#q&>79IS_HBm7sw`OIOT^| z(2C93jk&Ehdg+{k>um!8FK4@vW}szu^Za>MRbkND-tHLC1i`mi&w2FyXaVDyCk!Oi;MdZ9WhQzx8$H07-W_@t%B_GflK;&CFUfJE$>}C)ZdTpX9yhM zT<=hiOhTkPc6Y7sZ|&cTp}YsPN_^X(XJ{~oS!QQK?l9x6T-y{N2cze7_w{yWWrI@! zxeJ?Hd3?_mTfLpw=fn3#JGEe6ABR{*@0I<)eBVIVmhP=c4^R$o-aPN@dGpT3Yw&te zU-nZ7nvp?S$qY|L7*KhN26CfQYFcf2kz;Kr0}YvG9-D=}b|M>wb?M8N1v-Bz7Nsv2 zl`R2fMpD~Pqhn>(PMu8puAYC+IcJ{(;xW3eG|WYaBs*DKjx|9YDhbx!amh+Equ=1~ zMl?aL8{=Fn46~6a-PTU@%&4ASQZPhBCaYR7izN#;40f;S!UVFldv)(-+2(G{4X*CB zIilU=@(a7V(ekR1^fOFLV3W)QO%t13Wmgf|xi*H(BhU9CiG$S zsQ1vF4PM7FM5D~Vv)%c{J?$&aT38pVZoCg!AI`w&Ek~@H2sO>IO&esde7P(U6IR4w zwDB@hmP~>}2ATf8Hl%-WXzCsS8Y9b4E@(nZMo%5g>18$7?8|4fc%037Tm6<@oE^yL z+PXTr+QMX4DudW8gs!|2v$>)Cg@{PW=u3MCO`|e=H{@FLk?6HaC+u}JEV|N^mN$DG z?sCCu+NxYcv<4UK9>gf2o!2eb88!Ks{VQ{=n-ap^_S(FJ4?LLQBB~d5Z*D4ZtVV;G zuR3W9poN;c+BVvunYA6Qzj$SWD;{jNAwt9Ktp&ppoxX1%(%Z$aP$4nTq3Lq{UY9Sm zw_qE>Y_Wx=;1*=7F&1;4a1TZ8aMNm0#O@KJ9T&Ie2QjzTc|9r**m-Ui^QX>USqYd_ zr5gvhuWvdjf_b2?SN&=?`b_`E#JgRwyj2zy9bWu~3oS9}$Ie_Zl+-mvGL1foV_je$ zhbYxuOy-8ouoe?G_Le5IY_vQu?Xk0er+|K+Rbx2cmS-TEv6t;^x{7tBV`QFP(ULw5 zl$4IK7{{$dBs?>7!^|8@*Mu=&vdyZ#_Mz^a-O!V1f}{|u0o4sX8Qsc@M0`v}&%h=b zek5MBaW}QKbz{`Qf<_zHj!$hWEXjRT!0|9c*-+kYKUps%$F>>H%;vKR985)WTS8UH z24`$gv4gc0WDYyV+g&^>2gYh*5A(9Ug4tBzN?BU1NRkE*sT|JhBLit@Etj*BoeK8F zHs@M5R%cgi$~NdG%VKPC4CDr?i)_7!CVI=Ayt!53Y>KyjWafj33cMq1%!r=J^> zebF{_Xe>b791a04cLFS_Zm2Nxap3K3#C8bAUKjHw^-`~*YeRWvI+iR%pXKn3-Ky}? zTC_Df3%h|a1@UKQoTXTZ2%U@cm>E_=vgOvjnhoQ1D&lO?fsIilc_um+)2BAA--;$O zd%4t1ni6eCEf^BT4&Jo#g0FC1kKPxZxRa$7o(-p>SOLWaFp-Kh`$$faLD#4wnLDzB z;wHpqMo~DswHactz-!@57iqV(V9JPb#qLkpEvV>LlgKTcLwS7}ZRlwwmH42N^+Id{ zg1jM17G`UkGEfRicb3>3+4w|42i>VBx*{o9Ohh*8ts4tg3q|q;C%6dvf)U%qsS#$a zLgzIP%D5KiwA@C%ty{RRkbO|u;O%bhv>1V&Y1ZhFsl<}iu$ZwWeHhLb>;pEgE#xtLxdXw;qIn9;6-&+FO0Dyf wCT3$!L;Z0F`eVkX%VDd2*f3n4IA!fG3OLxBjU6-hbJG$|8QexhtWO932g@l}9RL6T literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-suffix.exe b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-suffix.exe new file mode 100644 index 0000000000000000000000000000000000000000..e54eb25d97c6508377c8c808a261e98292560a02 GIT binary patch literal 179276 zcmeFa30Pc3);C@kZa2-A?ifIfiMA0U(LmS(BvBd~(wHU?Ae%;^X&QoI3*DU%jY@3L z^t5Okbw+12X52!gTRWo1oV{ZVdouK;bGAv= zm(HnJTJJQrv^LkZ+8T{^TT@fB%UJC&wz`{)^-V@|Nx8AHxyF$c85tHQM3)vYR&)Jn z?4i!57cgTG8yCXZF?Jpc4+=Vi%>+{$t}w<7(SQa@luI`y9Hi(?sD=TdUmu{Bv3F{N zdAS%faJ%Rw$G1*wakMfTHG zGUsd10F;7{%CT)UAIg!X=y(4@#8-iD5#Y{K@MWhWg0XfTZr$Lcz7hi%@S}1BpuYtF z7uUdU{n=*5YLoP5D@JSae41eKX+A<9N$Kw;gJwWK20DZc1R{?HA|=%jwI-|h5?31% ztwEGG`o5bP^Rdou*TU^&CI0+ONbKzy#Ls_iEJ=^vhGZ6R5JKzKkVZygp8-;45Xr~9 z2EQqaLYm*%81rOFE=NkY#q(^!?(L+b|5J3EqkpVjXR%vmTBN;evS?t@ce;^{eyb(6 zcFlL;lB<9~kiN4LRL?dl@EHB|Wk7suPXI~j@7$-qeb+!PB~t67D{@~9py1EKb~gk>~_Cz@nxK-LPnqYw4M`^zGD&?eOi>aV>v>-ny0$B+XIb9)40_6nIaG6 zNJLV!9wfOU3R1dvAeN=<8|?GfP}6rsel`))j_CU~5La{yF?)mj{s}zJ_79lI68K^N zbW}cs9jl~x&8xrR*l9wvBK`7|eMh79XS0re*Hq7YlIuKf78Xypq~Bs_KWV(?W0QBU z$#YC!9=xT_QitV2j^?Vd;^$z&k;VKI{KeTwCL!&$b2K`N!!dO$@ zviKqn`^O{J($ykaykGbiP}pmJ2c?WUT;xTrJr>Vy$)5?jDf{hfUoP@|rn|V;oQN!m zGx0J=^RuzMBEGwvKy)5RzDO(XRN-EO)u)-pk?3S%{wj^4qY?CK#^Da*=y)B%e9`~# z0qb{%`_~~ipXNAF%bI7&x-PxE@-ovB(`CDd>qo!U99K1MMO-4Hym3y6^KeRVK8 zZ9QWHnM7L$8T%9&n*e&Xl&^m)#;$>@5MPk;*}&`n931ra`13(q2Y$t$eM8LLoB6{q zQu;UlFgUo5I#vQYR_>4e-*cQFvYG!)J#L-D{Od;i=3BfU1=bJY$kS-?%-Tp(I9D>P z{I?gAm0xx@Di%gG4IbcDP|(PO(WQbI3buA680js#>)mS8-q}n<~OMCqwkQW zN`AvCQ27R6@k(H2Y?Xpyvw&_r*J9yoMqvLPSrGlg&w2u1@&!<^W(Yz2I!wTc{ zzKkvz9kZSYJ(jN7k|p~e7JZ%{e!voXf=?DKdb8isB|nqWk9)i2+ixtM6K7cTg$FG& zCVrQLVy=XiN4z8<@;eSDz7KNBK1=qYGx|O6PxS0Eu8q=JJUx=d^W7P4Aq+0@5#sKO zTs@c4u8uSA(L4?cNOHTS=SUD`<^8e<4LWHWsGjf7aGg&6kW3Rz$1K^AUhuoyj}Aae z1())r$}sTvB$yUzZPn)hX^ zcbD1wiYwXFRWxYzb{BV9brK4ZS&o5^r}Q35MJckjuGM5YP62!qjc??NZh`NxqyzKIMN9LC^lFp^t}5k_+sdHwzdM027?5KZ1M zAk<$W=%rQL$t(G10^bfZVE#OW)~y>FFJLDHDgCCWU`c~J>GllWYQ4*+TD&jRdRHa& z()bE@2`(J3O8>C%| z%yNTkGe(u1OZiaCN6W9EzvrZ0f73q^Fwxk_Gqc!tp^@j!1J>n|j&O0r-kZ!)d^EQO^TjuKZ zTNaD~V>lRl-Z%8T7c0FAQe@BjI_Y`DM@Y|S@A8(%={xN_L19SG5uJCJeoLWN>Vq>} zeF+-Mo1b9z1|nVF=W4@zxgxNIz(uY zlMH!MA4HrFLNEwHDq$)J7(HV+j&Te;N%{^KHJA@|O~WeY152Qm=lzS?Pmb4j+>EfV zJj(3Lk2OhsrtH1?n_op0cJ}K#-vRXe1N@QDLbZNAws7l!t@vMszMb9PJ^HnOM#aNc zw^98gVy_a>t6!Ul=EXE3r5~MX6Q}As_kqi5|J-|(fyUejP`P3C3By7sv3PfZ{|dy+ zAUm={i1!QB`4aRK|E(ayD5%wMHel#5d47PFry(^$LHdq)2%*-f$e!;)^f$|Bb6yZL zkBFjibSh{x>3J8bpiTUXkmNL!x?>z7eC0+DRa7Wd)Je=f|HvD%G^piZ` zA)(Ks;ntzy0;^_V+WD}XHVGE=AT;aEHzFnL&5xqBmwsz$P|y2e-tq}M2n{Ze&3;~g z(+Xrba2amu{1x&g-aHrSJ8g;(s#OTVFvxb$?dWdg{Ynw);+ZMDE(X5CXovcl2^u<6 zS80{S`R?lSAQ(Bg>(yB8P@&rI?SA zoY#(S8H`>FHfU1}0vuotO;NqQT&Wjkt4f{lKggrcIBdYanVtM4iL@w`hNPuEbo(Dm`iGK)?ml_~1 zQk54nB#%Y|rIdS-cJQ@)i_Ly z7x?+W;{+ZLJi*enB+gjmJqY?_K|c?U`Of3y7OY+Q5vJ|%sjTM{o%f5i=D4YAE8-Hp zyLvt`Adp0XSOlhdclqlm#TWjA@u&)T24ym+%)fm3Myx|!ZJrbGv}d5OzI?+4`LWh6 zT37eth76c#JNZ3AVfKunFvjt?opTXxQwMQN9PC>APYe^9LDU-XBqB~5)LVMIU-X;^ zg>sWH-UFQLf9o6W)EU~09uXW%rH{#;CRdi-Ii zIx~sl%7Gm3?ExCsGhpcP$5JKnYBA-#Eu|PKv8qd)<5vz;_0|pS4;BGX22lSv4j|CHz*Z&3l{XjJ;OrgD50NOjC zVNe0fcw%{(SS|ufK>Fo6g+GiK{tO116Cpt|OqwDLEdSU@58osJfDQ zXN=6g9s+LU)14E8d}GJ8g4>0E5a}$w$XH@nMhw2lD1$h}&%NHlRMS-aGkvyIchJ3*^5ld8`CW;7MrKqc1oy8liAr#w1A5eSj4)9Nk z{lHAWDh3B_1`K+4yQXx$< zj%DM_11LeC`-`Ky0_0;q@G7!Hm-Z{ZlJC`A51i&8M?0tpmcjVVH_<{!{8GBrk|_kS zo96j67k>EgROq-Z_1?pYcf!jKxeH77ZY(;#ea+&X_!4n=p3PNuMs{O=p$kni7=33K z9ICH|f|nzR?x?^$gVEOmC$40y>Y{HUzO))3Ut0L`fu6ZpQ~qX2dBfuUrzPd@mUH%4 zvfp)~VUJn9?X!3@=1`7aO~t5;hwOdZin6FcvDa?q1Dj2vOspL|-BZ)@4-F z-hyKYwkW|9gVDbxFiZE!bqT_zGen?9Ze^R{=~> zlZW6yo7ySKemy6HU8i^UyT&P78DybD_V0fxLOc&qELXKx&AD^n=dyxa+Flj}g)wt? zjl(?Nl{+Nl(#v`KPdwvJ$~)sU0@+`=4r5J>N^}LGpLllbKyrT;n8sg(9FJ}n`?;g- z5&AAdRdiD2K*-cD^@fhPb|~Pbu205h@m9noe5oH>5toenlDI6~&2hPdeKZsZh!ZD>dt zC%j=8&nA4yF#Z?9t-=7_`e0;#w|MuW)dK5h?+6B7KUo&I-bLiaQP+#Cu=gq}>VK)? ziElw+V4U|No6$4x_1Gk__*`(;4V(#e;(ZhQx&CNG_`7i%J-!C)&n&Xo6CYm<0hI3n ztG5?R%A3AIqre{S1|55Eo^Ci?nA8icQC2wK0$f(92e|&ajbQZbf}8A)&HluVLF17B zSUA#BcYapi@d3%{YG`B@Y)%(>KeGlW7C~l_x4>ZPEkGpnOOC|U$X5{;VcM2V?ATzS zaR@xfRWqJc^H~#ggVE=DxnP&eXO1&>m3DjHe+Ikme%W*6dskeMcfcAP`6)brX_08?5q8EJA9GKhYNN zr^u7`AWWCjUSd0xg|nKBXmU~hc~pIOU?VaY*K;s+c>W{D{5w!f7|+tEllUgiBrxS! z_&B&7`jP3Nk7|yRM}iZdg5mT;$Th#lJ^Y%+esH8%DY?Ib0r z>X6Wf{hV@G$Pugbp64W<2rzwz34-+32jT8HY1DUI#RIwe&dU)fn$m6ceq!~0j;&2g zu!L=7Dv-CJ&p)3QElQTH5BfA=C|t^0DaWDYO|+_q0{R=MJGfu8`VxP*9v%1$xL9~1 z&mNfM?${X_Z>&PTm{mg#29jXS3&4E_c;$C2J_~l}xW#!-(&Hyc?KlnUz~~+TS1~qg zeDnPlUvZz=C&!uwUqAZrkpJd&Kurx5`l#i*uI}R{H*J%-@+Xl!s^Gm~iOSJM3$E<1 zTHhX+jwh7Uo04-hw_vGyg5$qmhK1;?OTgi6HG&5pRHV;A#>P zJn_~xDr96$9@S4i+B9G1E7keUU;+8hAp5frR_8l3{`sU?SR-_=w9mr$-tD|<7Mc}R z9EmE{-|!alnFW2@^&LM@P(yK@uOXPyza2e*`Muchfc0VvD}@?`T1STfj~wh14@K4a z$Sf>n!GKL%wlaSf7AipQC%LyG=)M**$)@}nLMFE6TrNvzKd)xjW*#}%KO{4k&BCrh zx63gLyCU80TqLJ@@gI*-Rf2oq1LZ0nLF(|KVaPsa!4G%4dS_w2(Cs>FXdK?ncQzDV z9)>Xg{_h3{MYgJrw}?!jqrP(yEF&O|8*#`=0#&gynp7z9T*3KD{Cj9Kh01I4B8B<_ zS&&$-49!1{{>MX56z_9BP2URglJ0m*=VvY>8r5PVzqAEZR6FypLKD&4AWAKbQOrhZ ze5dhpCE~lH?*;#M>Q&aR_~YolDaS3|!+1cv-AGmDeWPf~r}Vhk`^M3vJt3iHZ=GyG zXZ4jvP(SyUe;tg;J^b?&zs1w5^XC8HEk9xL{L|=4r3aR7E!V;QoTc-)zQc)X@P5hr zJDycQq=dj%T3iag`26{teWV@QBa4Qs8KOd*A!u%e3Fgf1&?^Re%v1P z9X^uDZQ@;cnT2j%8W-l^G!z*xwG18+pNE?sM_^eLX^wGyO|A9!mbC>5T@s&q62+B zPAReb<^Zca4B|i-7>DOK0XEq~v7e5#$UhV9;1G@X%{xK!KZ`AvfoBk*IuZfZ=V55% z_h4Xy(Ut8`#5eItAQp_OX%=7Nr<^p)0kF;&KKMFqV7>u^9s^@>h0;zsOo&#Iml}}7 z{WfIXPRaSouktc1*{YFL89!*?#^Y3<=2CEYU%|u(g2H$sU0#Wq+>TfVGw1zcG4w{Y zVSVhH>CLiuTWESPlPkI7T2fM@r(C)s69{-GN*v@H2BW`1H1GV>lXi2HIeM3pzsUU^ zScvxpWUUu`>U;s>4k2zZdZCiVqr#NN`wZEyxx?mqY5k>o+1 zWc6^i5JwhITFx_Ayrl;JrKfRSS98uXa30-n@s%R32g~h3P>;Sn)SvkC1#~vniboB> z?lCxb0S1~u+zsNen?QZ}G^dFu_+~uqmw}<k5R&uv)C z*RILNaidTyqm=YVU#40awttaczZE-JU1lj(zqLqv6%KRHc+Wf=vGd^GoOlCd?{VKCI{+_ zr}-245m*z}*8$i%i}zK30!oJ(dedUhL)muex8^~&B|*?F4+m>pyF7mACbwI&HR#+enQYfYW zkLcIP=+h#5?o23Tozhbzb(`=+NsC)<6lNk_W)|yu(enuuiTX7vsV_nJL#iulb`PF| zx9Vtw$bPkT!cbiyM>QMOp0SrOOfpl2(SA~NJoKY>q}sxO1HFWNsvn)Ao}cPRztwD@ zNA!HjF4CiXAIeda@-lzvgy;n=1UWx^D$$DhU3Dbg48sS(5Ss6LQBn$p8{4K-I_`V*Kz zs>S)4=1LjaT#7$AMSEcjaLBfKHon}rZ~J=uXNx>h%cJ$1=+5EwjU8;1aRwSKz@85I z7Y->nXQov;JNhv?yHY+Abrw%|l+S`?k~;*`7qnw9R!`S{WcFDiilsxU z`6>QnUa4gkot34nl-SlYENcch<_Tq%L>}U?EB|Jh(qjQ}(c%%i1H! z!3Nst;F}zHl7txSVi5FY`8Qz03KPm#GYQafloS4UXl;z)KFaUmkwiU4tL~|Y@Hcas z`XugQkZ5lzncSgip|T(s^9bmXNlO7=;<*I8H^xy7TD-T#-2u1*P8G|)Jyy^kLeT8H zKW-x+He@iq58#*$LNmRZuVRqtn_;9bl%$`YZhKAhtKBLL^H$e)J65fAS1U?krTI(dxVE2qwfx;<^Gwwt7z@OaBt&f@#3J zRy+}3L^)>n>O0;-dbFr}m&x-FWN;(UBKvbVzNE2A$FMrfF8Av@XnYQkOZn2c2>I>} z!~M;SjgqO@2yk6(_G!*Wx#(2KSr%UhuaNev9E{Fgkq0tp>&EXr>7NQ;*{k^^8j|qa zb`fr)PX^WR0^^O z(#+n!TkLzNEJe~Dldn*R(qC!utd2`&u2x^^Hsi!_?@qILA0A<)35c|M9-P~Wi!Vxy+_@43vHDOIWLKT_RH4z!NPNEwbAsU} zqf|0`C=!}l-}xf4-v-yq2F^nWwI4fhmI!z?-_hLt zPN1~#={$-6w&SqVb{p?Qp6(#8=1rOs+tEj?zL~qM-dTTNh9o7VCpd9-714aQJFpj( zPU5|q`$#I;hBBWT)nBuU@ih4*er~XXXG2|+x~jh8ZEPZ#eUWuYPiLt*P6O_lH3KNR z#2G+*(JPTXZFq$PqvBFu*Kc7n6LExwr`AOB)R?&54}9hY`i{E*J^l+G`iH(_EP|c= zn1jYa4Es3y-pq4=Y)8MANJDoz+2bWJyVPnv0Ko1aejJ9Z6x87@Sc zy(fIpzr6y1DaU#>g`kjD-Y=%~cq4Ox!IR)w4gwekqOg6KPHFU8E-dJPr5;df(M|%|!kd`);c*z1P%!VWQQWaT4=#eP=qP7vOZ4#06|5E}!B&cO)XQ z|3zh!K;ID#Mx0N68mVxg2_^a4~nNHEZa z-oWPbvZfyS?ScvQ~e&EzL+UWYFV%g=LxDd&Y?!|iyfOz=ny5FlY z6X`BA%6SOzM(JDzeT%wQNT&9|L_9W&K?EEUwJQ7^^)H~mqN=iMw1~50r}w(9CT4xd z6W}_octF`zpVAF#j%&QyY9{^8H~h~~Gs5TbDz(B+Hb9hBI4GR$Qhf&8ztMjQYJn8R zqx@N4;S8z8JL?84Huzo_4EHL8$#AVO76?D=`923W;{a9Pu?u27-$SP^(p=ahCIuIX z{5$?YMHnv8v(%8^FVuHFMU}^mXokLX6A;DxUV<3RjUgMuc=mH%O&Dc!^TR}r4ni31 zTFO<_d^m=?T|QE-LoVt_Ibj;65eq@^2jOIkYDm4BZQv&|x!I1n5U31I6VMKnw>!k6 zxeF|kFY<2|{h4ULGgXIP8^=cpiwe@mO|1n*`Ek z=nR1WD|8FYtms9Y5&H|^w_r4_q7-Ogs6w6SIh7mhyWx2FHxd7U8b26c+l*mp-C+Cz z0Sg7p6mYVDF#>7@Jl>?F`&hsO0`3uTi+~Rb_!|MQ7jT7uwE`{>uu#BE0VfL>BcN8m z5j|F3V;3^wCekco$2vLi z3*AcTw#eEQxeCukkoyYC1FKRaCg#)N%_`ZMti=-8v>YKJ<{KQ@jo}>G3KvHzq^rLrDRB2#TgA$cBa24DR#aaSm=PI!? z`BCd4UkDAbyl1xz%;EgOnjWgr`rlzsk9NJD~h0|jXmLCFJAJelV1^BH>vvq6lW zLf-fArnKB@!GMwmp^%U~i>lIf{;cr?&gBgj={tjJiQfH5Lvp_D@7F`R|IHUrKZ7{Q z{y6BK!C>X#hv##w89s(=^_)GOEq&!B48wTA3m&i=qcq=P0i6r0^>)Pl4iYFn-Gr$G z5$+O%nS`ttNHQTbXYp6Q4&AZe4%PgZ!qH;9Tk|ZL;E3fZa!`)?D@tDsB}kd;-oQHW zrGOYBCL(gAa-<4O^y~d7<i%j2&MW!F0gbc4zK^KFdRM6SrQS$mb;{Ds7 zS2vsC0r=wvYls z!OVZ9b8<TcLK3bD|N)FTx|2_T_@e4%!b`ekAA@FAx$TL3?Zxivm ze$(+=yq)X7wt^^A}I$W5KyS^2mVy~ zYP#s8`DziCg7kw3mD8@#IlhPB{0&uNxv^tSAfYD(TG-H#y zvD(o}oOW>9mpbgrj5BNN8ypvghURn3TsYq-bZD*>al~%}zpbWbh}(p40I#b#fY%J( z8b^b}Y;Km{|zIKCb0z}~JH;VG4 z;0g#>K>}7dnrfO`htezPzf4|3I#co*$BKHpV<@?T{>$X$NbYQL*o`ykK9rg(3qpNu zz1>C)`tyQVa#A)UD{#B&8+br8MMAuDiZR|9CI*(JE>}y=v}w*}cdOk|+uT~`NNRGp zrnO8{(@t~M+m|_9&S{FFN2J#r=%p}mTD|_IcjZ9#&Y}8#`+r9REkNX zm~>-Bb1Ob5WL(hPP~&I{8}aoam|S72!(l9Mu63=nwK|NprW)f?o6~5@D=)FmuPCrC zHqI?EE;N;undVk34l8YN*qjbytD~j46(22f*Ex-7LSB%i3+y?z9CJ=f&WfCxobnuJ zP6b=s>^3$z95uv5^;loK%4jo^eKy$|9bv4bsbQ6303+%&xh***IhpH1!4w-TxP@|b z)F>5Ju5>D=+ipi+sdYC%42)UHh{TKjcq+bDM`QB}aB_PUypMh~I2iI@ylx6ecSAt< zU&(U|UOQmHe~^ykM*IZ-d7zUEVZuK!?hzQOhAI7*p-VFKDu%AXs6~W5DIcM-H8eEC ztR3(`jm@pAjBpsv`YRpA_!?vNDi^$5WV|!<(s($r__T(Gn)rBQd`c<;A~r1EX{>2( zawLVZcxR3gqVt>Gh^6mat!%A_TvZU+164f;tdO9q83wYHYzo#N;1XC-(+XPyx^aM) zaMsr~*<9{c2MZwPm*pdGhm&X4Xmi<@vc$mrhl*BP-`dD6y&5*;Xk}#%Ta7WkUMYfN z6i!!7eG@mdVf~w198E%HC)cqR>FS&66!m#6p)XM}s_W|l%I$PGmQiV|Fjp5&6Z223spyhs;IDSy_+zaxHbBDPi*~Nf(SuEsj=Ky~7!XVX75=CC4a!$!+n; zS#4pZwp9(yXfCBjb5P&HeGlj7ZgMo)TUWKfQyJ$jDm7Y5^Z)&9e=Og)tUeDNFANR8 ztf_e=J`Oir1lOt-)y)Oi(~sHhZ*Fqg>YJQsg#S`4<%BV{otek2a z^Yo%p43;}w?W+rN6(w6o*t{cnyx`r$i`^EU7Qy0`N+&w@J|#&tim ztmew^s{irnKF6<0mPk>D8nkx%Ed9xEB6VGRjZHHyH`H4{G*!Lcy1ee*S3eA%IeWi6 z=O3Ms{mV9oJ#g}&%^3}MY|1;Z@2R(PzkB-84;l`px|bX-cqQ_{+lyzt`pBcnhbHH+ zcjvXwdt+~mt?!x5Uq5-yxz9ea;Lh83yrO^LuiMsd3rf(f)l_ae6tO36ApG$gRyR)@ zYhAkNk%_jRS&6k<)|uX3pu@R@tk_HXmwyDy|I z{X2X)=%LWx#NILHy{96txHfTCqwcp2HMdAh>>qzUZ`rbHTf>Bd$&SvstoqB(Zr3(k z^?-C{&)2%^7Cx*0X3wFGj?#gxr+u<*r*HMz?LQoz_)c|E;+xT5t$yuBhjst=i)@>U zU!J!)$Hkt$@BQSb_M09!eDNE%ADq?r?5p>G|Mh{_t{AA#|KU(mdg0o-Klg2`defOG zn?ITuoK|TK`_sPFk?+i0t||SKDd;?dA$;fc#)y6Ko0l$pqO;i;y1#b&Js;X$9`oJ1 zm*27P(3DAc^lg0dp*MO@pY_DzHIYvy%~`)tb-&-^ap{Vl=2>wnyp zJ^S@f{<5S%`+Vn3`8&6s{`yTDtNiyJIB?Caum0iLT?ezuzC2v=Mcq@c)-8Pc!FRNq zFPf9N$@1m}kq513hW+LE#le|XSIVZ{pI058f4J_U&u?lFO2upKE0v8 zIX?6KrDeCTjCe74cKB1DQM$d4YVz6HER$_{Of3SNb;l z)*qTW@v(O=-MFjf_mjW0e|pz_SGdD&Z47!?8+zA8nPZN2)`hf=TgWumUHr`LQCDtz z|FH`mzbfm@EfK%JssGoJJ7523>*sH;KIiaT;rshvyFTyz{a>7T;+>^Uo;S~aDQ4%I zODAtX{@%)s%`0bbjs5r%-P)Eb^n=gO(AF*qm&OjRcide6SoMk52AA0iUTKJFdp~T$ z-}@uqsPM>hcRdlDZJS*8$8Te*`if`Q7rnKz>B5Vzc=fTjFFA0iHvDkzu^9)amp}IO z!_TdM>fLK!*))4#aC7p6FaP@2U+voQeDbYNls|ailX05Nz8$w}-*{=t!gnj4sXKIT z(v`JOY`fU@Y|xoYFT3r6=JTiT41e+uH%06|^RVWUuFr!Ks~*VZ4x)X70uARWkP~q; zwbr>C9au!xG&jPh8y&5!m_{X-ONvcJbEgbPJ24WtX)tuHGA5K4%|;ymm0*@pi*eA{ zYHO;)z^x=NSx`_`Xf0Vdg_YVcFxnc74H#FISz%ohUjjAR9ma%GYe{)ImsHX0`bn;e zAuh)KGDcW;gUcvpP0mKl(3FW1tu7FW;$RR>m_OI7YM~B-Ts^LLC1!d{fhJ7BXzZjZ zO1v{6zHX{9zHW-qn9%BQVO}!}2s~`W_QAo+whaz;<9ZR-+qgc(^#iVA)XU1mm6_@E z5mr}yBSuMEeFJ7X7y;-f20CMW3tt>HH5=<2u|iLDI_$IvWJcqH`c{|Q)-ccQz`U6f zLwB0W#*4|Z(dME_4^1l|g$u=PC>@3r7i6g^`KV;aM_`Q@AliseEqja8;jU?>c^A#p zX#t9Pi>uk*+%U8!5MP4{xbpkCbk&$GiP`-Szp9t|y;BwE)A`bp@}fo7#g+LbWn~5V z6>1zob=*}pIk0p_JN%1yvGP#3L^_(lH=T#A5Zf|Zi5hLHS(Ct|^M^&+8ZpauH@jhs zd|QR*7|0NqIl_XgRhi3T$}>v#u;ft*1^Tbjk0{J3M68>aJA&Fb3a=WqAKJZYB>!l9 zUDL>T#zx|4ZDg?~5-m!BM&zUsk|_{N7v;t!3&?-+$|7=^R$k?9Si@Yqp! z@+iDzRQ;8X(yt|Xr2J!}{3RR3pF9e0*)TGF?5OytQMh3geq>a6*Nwtw=jZ1b6UrPb zQl=X7-1TsS)vJuf<%`QxsXJc*PcX%pk(8E{%#_~{f9n4-{{K|}U-*B%eSfK+U+M>4 zeyG3yPus(P>QDZs_4!Zb|C{;?H~L=(I1M4;qHnqz0OyUxr`-{*0(=-(1i~8u-^H2a zD1?sy2H|*j0>bo7{#0BRgmVE4aV=vYcIk_0Jq>_{XvAg0mn|lcjbu(u<%^Qen7Ys@LOEETTq5L#?HWHK-dU4 zA6G2GRe+mu84>OVd>hwPgpUCJ4OcS4#{j>=m5wlrXY2s3EaCxtYck46VL<(P_%u4g z2EbLgst|4m^x$ehcpc!YxLSxG@KaoE2p_*s+0k9O;{bWmkm*6@`{Qr;q_!$COVsak*0KsZNy^iUnaZHySQl)Ltl*-*feW8Nq z2DoPhl^~D;OO|MXxIuaiYF+^K^i$&DwTA>8eJ-d0%&Ufvfp5)#u z*(KwI_(IXl1NsW$kPzY4A+frdDIipt4~3v zJjqr^LseH{Z$N+f{Y(wa+&CP$c00zNO&IeZAEqtY0iXQDFdi8C;YkIH+N{8-0_F<1 zK)?n8R|~jKzyk5ZH33$JNn*@AXz&!%?3HYXf9}0L(z!L%nZBz7$ z5HL!>2?8bvm@42*0Sg73E8rpls|374z*YgT6!1C$efjeZdV#t5iTF|Pb#U%V=Qu`k6U{=4n#AXCnI<+MY~Yu+Hq!we_R5cGMK$cT0BXfjdaw^78ykf5R-4mRKu;ks zpC-H*XUG~H7MxCMaG3B;646Mw*qFy@W}=k4@SMWkQq)x2Y+^o6S%pJ-jTP9@H#zB` z35D2$6jOl%RXB#xrckBu;xaa!RaWL#DrdRs?Ujl)Xr)5Xv0cA{ zvAGE0lq3#ywAH)VJYaPW7d@3iw3C$quSab=npUuK3O83*)}p4crU2G}LkTN*Jk}_{ zoeo!}t)-<>IqOiZP~1+GP}ntF$YjyAZ;2D+goy zSS6knHQ~*mPgo@#gFx_mgy`S)7`s^F8KW{A*;c6%&sUbQZa_N0!!CwrU)4VyDaKMu@}uQC4)E zF4wluA<$ZujgZ@AXE_`?*(|x1=W-!IXjvrJ3Tbm?)GJjZTP4%OGm^JP#>p*v3oPhY zvJl8_k|EH^*zGa|aklj`6kdVzPwXCWSF3#~T5=PG#3QyRDU5nzY%7JD z?2RpK7lmBSNb`ogLRFhw56zMOhp#yWWpfLxX{r1eF0zY4e*d>$jm{PJR+m~Ls>ok{ z|66OIYHaQ)RWleA`jNPwh(AxnPd;@#`{nn4cMbF@?OG+^ga;Kow_Ab#cNgv#?MK#t z#9~3f)jpa|`(DYXpc9`3*PC;Ln@KO7G*;u(JJL5fXH9aqHsv^R*t^l@Ol+*Tw>CR* zpg+;x+?Zo?HYTk|nPkKqwZ7KjbS+TcCQ&lG5HDKHbhWyjE}Ap{o5Ip2Q8FaN=@&O0 zB~nlj=zImTaMa+9mKB&^)j6DMTwrWL8xqpl6{}-~1BZ&}K5LTAiNnjy%N(tfrm2Z$ zPWwrTGp7aSK6BboAt>!k6ubqeW2);L=%mxXtfLX^R9lJyGcomS5bt>msdP?aBAq_P z+bh*LgR>H6j%tX-fkP$3-0J%Z{0PuOur#l9;)oDh5+_xLL=Bzg#y>t6)y$f7m4n{q zNY9v_n39p6nV6nt&q%ao)H)KAle20Z4o6x|T5a;x0oC(g*Jb+8>XDX_l9pASZA;9k z$%Y=a)isG(j?|h&TWWfGa%yTuZFZXNzekU(pVcGXmRg&d9$NqTGoG)9!V)bt4T_2=JZVa^vuMpWJgM3dTLsBVs=J#bz)XpO>%8! zO>&KGI@iR=dj>4+}mLs`#x-BI&vAVW84Q=DdN<>R#B&KK8)?_5xQZj7W zyloUsW=;#RO5Qc5jWBk&l4+_hxllbdrh2Depjrb{5eVXlP9cf;UaCgr7zy#+M({r! zk0)q6qB}a5LyQglcVu=hhY7(7KKibtZ%b0s9~0>pL@JzyIk`Nb+!b2jUC}omPob3j zOV3p}_XRQqgcbf5tt!7!%wwMp;0X*)020JpWh#GQ9EFwmKP~*JcqPBOMQXe{Zw?tP zNZ<;8;bkiSF`?g2R3B6LKfPS#XYsjQ(pxk@pW-LV(>TOGibs)`gmth|pGU+z{=QLs zDyqo)0Q)DxUepKy6?yBic30xpiS>c?C-hVJXI-uGA4$mNl77DY@--^|F~J`-N)HuP zptI8i3M`1-?)NN|~k;GiiV)_Yr3V-y&Dt~gS!heO* z>3G_}o09)acmi|k`c>jPH~mz+lHVig&T7{@Qa|AjTM4W3*v4V^T5?tEi@cD8ap)0o(ZL*t2!F1+3} ztIpBnXsySK*o`)9rOj%~%1orlI%8r^PE<%j+p{1PYS0_NBH~7EH&wD_t!3+^4}4qzl2? zp$=#FadS7(h9AzRW3v%4n&B8C1iNu>akWy~Ig~bdB?%<7nm!8|6cnPoq&ZTItl`pR zMH+==-GfLi>n2hnIbsTe^rlg<6tsC;=~ztm}XrO=ZEN{DRVoqLR6lIDcMJ zW@dNDzYR@-i_i}3hUe2(u6#%6#Tw*4OfGD&VeeVKlhfspWTcUQ7mAOCG2Jke`Yb{I zedtCcH)!Ybm+SHF1Kw4}wlD^xi zC|Fd%`egZ9?YR)DElsgB;}L}1uKfd7u{2e|*Kk~?ElpGK>o{)EmZmGXhvTu@(hLRf z;J8s+nyKKO98b`SXA7dh*K4UFlC{Nc`Oa1*-@wsyZMmZ^AEjBVy%4ckgqneRIhsRg z0nlG@bS9yNKz$s&kkHvcZ{%n$q2)lkIGU#|5EH014n(E0hl<$}A$lFO|%% zD4L7JPX$faG8RcSF&}|3|FLTKfp;^NA3(}IFZQ(1v2EtOjI z3auM+D(;71sSBH1YnZ%@dk3b)^I4bMsn8lYEl68ot5XP#T2e~Zmf_W}R(zlVy{n0n zG+O>7xTJ+%h+=XxPpB2d+FCrzVsZ=jH*n_k%(xscrBgRz@^a1_F(eb6w3U;_Xw5d4 ztwf}D^3(=S8&2%voKZuG(W%{>6r=jn6+B(6f>svWoXeQJlG7$=3(2t6jtmdkrrn4t zHfk3&HU>~vX{nVqgsX*yueef64YfgH5uD@Bk7If8{@M z6b9m`v)NZM`H|tw;ISUnk~wUktWl|d=GaEUP#uqPteY^D?=KwdBMh2sqBY2GNOBnm<^$G zky6%C`oQ^2X-N?#3T5T!>YGDK z=|&)CE*&b6H;ws*5WGUU0`0<)5qXsr%r1hzGX+kh4Dv?Kc*b3n-x=TIPU1-_#BUxG z9}bDi=?hrfmNDehV$^5<@>Y%$=iV{&cW^O<_4p_ebucFH^d{~`7wNIrm37; zQCU%x$Fk(zV+N3BcuHl(HYt;zRTL+eVPBSqZ_Y6JIW9`4kgWBMI9(v`;WUG`++AHR zj(SuxxtCL8&mgspT2m`tb!@e@u9^?WQre91gSyO%oF@Sjn1)&=zr>Y*Y3ir|5kfin zWnP|$QWbw?%owcrWZmar(o_}|n`ReOnoG(nEd?gLrOI;UtiCM!wMzxPG2LMGo4%=^Es7N9Pb%g>e#s=7@466 zlWUaHsPab%ksUD)Lx!3~315nttZHo@k?Ujj8F+1S(_g04WyssGf4L!s2KS(lIygqT zkt4w&uTo5tl4r=v6w}NRUC51uv~VOMLlF*f0#e|TnDW;7h=ZEwXvWg>9LzWS8B}bA%=)aoe zt2mMz;wI6nIg%Q(nb@x8qSHgpr z(^N4%S-~N+67OI7p>8v(F)@{se-(2Qe6lV=|C4Qw`SvmSu9!zo8*cTxc^R0}>gxkr z{hq*9-@uiVl~(@)M?|aN%MsD)_i;qD`u!YQx~N`5Ma zjU9HBr)2mPEh+1WEmVwd82OaJtsEkBlH4CtIu5N}KJ*PP`8BQu)6(%u)r0NlepS|v z_H3_nTZtVqyAjgm12GMdE$hC77OFoV=3w$iJa09o!dhOLZ?anRO!;%Lx*PuxPx~0| z<9Fl6hj%{N;30_J2Wlh@GY2V}W?Ae^OVQl&3e(*Df=VocG<`oHW`es3Ck$(trjM3G zSd|X(fE0-xbXi9Nf=eq(N-M1e3ks|O8&hz}n8&e@v7`dlvp>gk+BgV1vl982Rm?9f znp;?6VoP;r)4PBZ?A1(X8fa%V82kPrUGCQ2hT+J;^H;E_)P%7$OShMNQ zB|LUQ&B{eg7e@k&2x9<#N-^5?}Z+T?$dESn!BS)ump7nhvBf zT@h8YtV>1{PjuPp@-YD~s>m~y7ciOrOeFO7aWRaYHB7E7o^P!vs<2?4Yc4RuEY4nl zHSgT{#R`8I3%WZN2^LgT78I9OELMVZ=Uc5zB4SZ03*s=H1rsbof8;QWX$a;oW?F(6 zatl}ph4N@mLdR)E<)x;IdP1e7TRtJrx0{0!uJ_j1R?Y1&Y4@Xa4w4^ z#9WY%iIJ6!A*3jU88`<5W0gQEJ533svvHgyi$y7fEEdfP5F4XV5IUVgd~YR|La2^% z)C)U<5Za9yPl0k%VF7(GaxpuT(0nC4fx`343(Cv|h1er8vx!7d_Fm3Xf(xn4XH!^g z@WxRXOCv5jo{;$}HkmM*0aX+g7qDEy@~kC!%tRr`DKHhYJSALGhIu;6AC4$6SC-^m zOy4jus~p3m0wR$pm8Xyhc$PYwLu)xUmMj#+*Kx|R8I6=8yCNf{1fpm%s3&{@pMs%} z5~9=uef9;6i^~cM(HAI;YAh&QKz7wmXpz-gFdL1AKYbm>icRHnz@bR3SX^2_1fVRq zvUEY=0v3L{j5!66B0^$mcjp{A{MUUj%L$lc^8?D^w+f$DiK8fVRKA|(=i#?)1=FN* znl+H|hu=-#B0sAVCz$D|wsJ5YQz=k}a6GwyWd{)8F@xB-BqRKu4bS}xTF}u^Ye!8!o%?BZU=I_E(>jN`*b6F`X)iB0csz20>%<4~lr4Ki za9Tkd93B!d!5L429N0gFrb=4)3i`1B6p}L{%OB-+xsum>%Buor-l;T~E7>Rq@PUyO zc7BapIbP(bY-z!nYE-F{Nq0%oW=d+aQ<$17-nN2*M4fC~(ZHnj(i?DIlk1su4`;xC zPe>a$?E?G_gYpLEw8Jcvwm zw9#jn=+nbYS{@GDlFAb4s6Kz#A+>VKyhJ)j&m&GD>oh6-kQ|hes~S{WpjX zy2Z$n_$NuRa&5u~lxpa7Ka(!w#gMik*U2qdPm5`UR4LtyHO=If(gKxICADH;o!m0F zLZM)yD%m8O&<@iuQIV>p7chxn(@=s+yYfPTbPZLedQ#UU3M<{^nSddV3LIs~<;AC) z)P5GoDHKe-0&!_q<3_)KOz>_7Fp&fZq@Gb;(K_>lPJ&Ih!*`V=VpCR@1 z`$f91NfoIqG}yR75tJd#3k{APLKcMv8&o7{r7<*^2@I81S;^nm$SYv#4^2_FhYVHW%+eLXl4|74waiYPdf3oipb4H7RJoi4QjG596_9`J+^+75zr zJn1aPE<6VEA|$-3_Go(dCW7Dewn28Z5OYl|NF%Y~iDwo1+sP4u|WARmq3+c~G!ekV2Is(ibby_ZQ zvB`*ofZ#BHFf*?d#C(M)CBx{XRAee8v&_{ZG6i~=y#ld;lgvBw4ndfS*!24aG8;&j zA`1p8Itt5tSVWg0IX~f z3*~tPclzAtFI3`mY8*Z~UTNn~ZKOp?l&nVaxeA}DNQ-GYGwiG^c)6^h8DI8|OJFstnkrolPG0y*dP}Vu+wV-u)trlGem9Qef|d8+_y?_-ly^2_ zWF2LIJe4SX3YSUw6k$=O9%yjo6+Wqew4S3*N$_GL*-GWoq9#-v-l1gDY+8bc2Cscs zF_|B+Hnik7iebh=!%S#!`%kep(Yh1dOe&&6hMX1$^691^K2V(9N=X?yyY(-R zZLtXD4;ygeDnDmQqjQxrGkwWYoZwmFTG6~j{da~${LRA>9Nl8HouK|=FhZ**vi^fJ zSpW7Jt6<$~WEHG?4)_1>XRLyTAN#9^GDbcBA9Wr>rn6#MI2sld7mZSnIG(}dQZgxW z@?W4H$J0^?PxuhHM){s5GyWg;-UPs^;>sJZd+)oi@9VwkrZ>8wX|`r>5D*2lS(<%c zv;kw&bT`lf-EA){ng9_^j7bb=T;d?2QKQBMcSJ{V4QeJai_RpIM3ShJWRe+1;}u3Z(-~2Ws=tl|X>0{AGnQ3??v8iS0j-KhVi*v(dd=^p zs8}CjMo0?zgo%ok5i<%EKNru0t`1(SFH|wMYOG%=L@s^dqWWbkX3m^b$8c@!jAcG( zr7xJea$2nq+A5*jCz8XU^Gptlu{IIO!GL}a21E{GnWS{9;zp)juxLhY{X(pY_~EHD zW+Ps4U#qZ&rXG;D_Wc35Wxi?VDH#~UZvm0TH=61-HK;9t zCDxcMtIkRHY?bXFksk?Ckl7xHa^wzlz4?TKvd*w_wTf9t2}nJJZ|ysTm)tx(8xo5B zP#T0W4_e5$KLPHgUw9W&+?>6;cINYo8rBkKc%BR0$&YJj@F{})&V~jnu^^K#pWM*! zWrVe5U&?0x1>geKdgyGhj-Nm0x6U1koN$UsqbKp00ua&`GuLV)+9Kgh2>`s^onZi# zeNH5yB-#_uA<-J2PW3*fuy#(aFdIDoc>uSg&b{Rtm9U=1_GaN_ldm9|)*KyMhvW}P@+DR^(pfbsvn&$#t(3Sk zBXPe`<({J?)kam`&HH729KXNJhwIQaM zXa3Y=Nx|HqOG-F(L4~zo+TLlZ=q*Dj$@1pvO7B3jdvr3qdIda=d`6<6? zD9G2^B#LU4`7;wqzCNuZ6V9Q4FMFP@H5=PBJuFOT;1jEV=<|1y!Z9sUg%thS1M^Q+wn>-hB^S=yiS-hI1^=7!j)pHQHn9xAi z%t73eO9587!5qXbC1My5{v5>ZL(B+Cq30lO88M@9#{B>oNnB6vy$wL6N2eof7q{PU zK#>udj$|ZHM>0~TBk9rUh~zM6H0r<{{OO3v!Jm$p9D?acChHuNq{Fu}>8jeLk;L;C zVCv=PWo6(iG=x_ytX(*L>B_~+v5^zxltuAV_V?dM{haHORdzj3{s2P&Rc1sMJI%ZT zS=avqA}s#Nmd>%RKLC;(+@?_04MeM4FR!tq5t74iX(?+tJHxUt&axXC8*wg6W3urr zBOIKwma|cH5u9;oA2K*62HSiA*7w}>2i-fGTc z^0~m6dXdoD_iu)w_E&|v$v z!SMBIYVJfsv~qL|f>r5*i|C}L7P^P9yz{mZtW01qNRwR1l$bsqsFA$N@a4v?pg3i9 zkUHViEQv;o7+9U`?S!+~q|9MyqOh>l!6?`X&9t(*nah%N;LzS%2%L!%H+?CM@xmH_ zkV^TBs&xGkioM_pL|q7)e%U4-&4KxbD!SLeKSC4nz$NflWoWLE}hno%kIj-SzQ&kp2 z3QLs8%5jsdzt8`^pMgST%U?|AS^6qN7UkiZt)%X)z#94dei* zFcDO*{8{@pqZ11%5LJZJM+HL>*uua#1Y)@eoQ=R@1P07Q;64QUejBAPHu?0@*(mGw zItX#WJBa#Mrs6BafILJF+GQx~4dqgn$6}fhJy?o)$Ev$&Fw3!43??Vm@*%0Idb9MZ zFPgj*jCJ8x48XB+w+VBs{0xl9SQ!(vbsZ+ks_@=Og6AR$O2CmMm>5aW4b)0bp9^1z zB>TPzbBIlrWHQ8FH|Su9%|&HPE;QH-aLa)wLPW7pd643@*o)LJ&DP3SfwT4_zij== zvy$PVG-B3jS|Mmb8o6N{wfrucewViHJ7!9F4OQmP+IIsQwU5r^K4x+`VZ9G%?4Whu z*Ey660=&<~eKaC{dSg7b>BIWg{XasU-y{ZV?g29SS=756yP*#f7>#=6K!GUhA%erD z7;H{kBdrl@!0uxln{=rqY8YhClWa3mjif@nu($@Gg6A(V{?f}(9wOjBL;NV>M9TXX zLohEkl$7#^K!?V3Y9qQ_PndbIdxzm#7~x+PA!+NBDw2nmXAHsL-f zw-6jd609*8?UGs53nq3rVvCMPNT;Tf7Uh*`W~fBgNGz1dKO2!!RnMDf%5Kq*4M2Il zO6QbtqVmc?{JtSN8!1G2917%9vuJyjm@*tkTb+ef>~b+o|3Qnj9IaMeOYwP|0`Vfi z^35&SU~XMs?~B1Z?2JD%23^$2o#)?D$8-N}3`h9X5?!5Ogez+j^r;N-H$WsqysQ+N z6uoXpS@Tt(5oX)h>GY~-l&MDp>d~R2ISPu-GI$QA&uKjDRnh85wIB3zJ7#k8d&l;s ztD=pO3|;iAEj#CQ6MFHcEa6(%U05QdAU znJ}CA2ZlQqHX}l_)Pz~FKWZ9OtZ;dRq|JocVq+jy(qbEfBWsG)hQtM*0sd?V$tWTRTt$sUk%`_uSq^iy?)Yw_lqs7sV|9vFEKbbIluMqPUk%Q_~ zA)luTe;6jJ`n3s5@xKcriZaajXKmL=ZYi~8@mUciQDwp`{u;mdKB>jeP=&+7M1>Q> zaM7|z2LI@1u&ak!8?6dggsH05o3K=%(~m%Rea3`Yf&MTUkl&u&b!8;Mt&s$EeuBk8 z1=wAjKCzcSAF7F>+fA7D{-PvL7L!8+IUWYI&t5y+01~>v5pwZ zB^cuTS^L&wYBNDkfzFXh)n_pBCx|Q0!1$eGy$aetgc1HENJq4nL3xNdt+QxPzfBl( zpp}yBP&wvLWfe6nPTeSfu`UZcdAgX~&s*fc-dj`jSwq8#_ZGzKQN~v{X&!5`DtRnI z5{b@4>sjMa%uh{xn<>W5#|eo|?Tz~VP4--@Zok0OFf-dCES}jH4AYyawOuN3KH!qt z{xy;d*$Kd7&)3_g_tVYTGxuCRl0;_%~?T(X_ zHW8}k=cePR{q~?F$efdI?dHrY{SgZ~C(<%JaIQI4MNb<%Ro9UaU-gtJPlWqr13;-2 z{ltVR-2bHu>M7hmk0kidNP^L*u8f8Qfod0BRQS6{f_NpG4?k+nrIJA23i2vzh*i{@ z;WTvyZeDLSVp@-5Uco!U*Q|=l8s?@3BM1JheXEeMk@T;L zq|ZRZ56T@-Bk^P8uTn#LLo(%E;vO-C*7BkOhJY zuScSP>POG?qsJYIL@V7T31^ufUG#b+x}P7tC*b^@Nc35L^id-es>DuhvLZjF>Oas@ z>H;K@F8?!b9LUmCmpH4ohVYdNM=J~;3HIrk{;Ik==2eBMrtkXKf5x|4leO>Sa9vx& z38kNt!o~HpvDTy>i|dn;PZgvcv8GIR@Jfq+>2oG&x5xUgx5%2L{UYnX@fWN~zIS8) znf5gJ(c}?^Gy)vyfN%^S(&2`HtifxJJ5fnGU6wy-Pg#@1@3Z{z=2(-oXK4M`n}{-`<&K)y|XRF?Y@}G!3*Chb|KTyrBCT#Qy|qX*d=K&5oT%sB#Zwadzt^Q zu#6uZPB@u&2y+gJ>-klmgq+8`OYqnI4~T7KwLaCo!R?@lr=?s5i2-R}^JDz=PI4I} z5nKi#y`${)ux1|4?wiXX4C>1u4Dm9EJaHL>PhJL*CoY5V$;%*o>dPPu>B}I33oe5Y zGM7PwL@t9c6kG-&5L^Z!5L^Z!z{?;)!OI{zfXg5{fXg64g3BNpfy*F*;AIev;bjnp z^koo+g3BNTCtU_1!dwQ?L46s7VgE7+!~XS;K?K6fAcVrpAcXW~ z5QhBAAUbR=gM<;`&5s#AMTn{;D(Nx^5xfi{PkkAL!Jd~v(wQ=H8H8|f8H9j;8AJ%p zWe|oVmq7@Imq8*>a2bTS6I=#yiw-~#Gt4nJ?TX*(zY#cp%zq7ofj?{Cl`a+`#0S5o z7+!&WhonP(14v@;U1P9vzHgw$ZOFz+PoB!L1~K;oNSo6%pavP^d@NL6?sfw#29S+x z^02x+QRQ3~p~<;60_5IffO;gDuM=Qqnuqo7y=(F?OWnIc{A1R0}x2PM`z#9I=dbj>r`(8&5rfDWJ!7nSY8jvt# zT|gi|y<*BSF+K%A z+Shysf74E4e7wN;kRHZ|+k0uy3&!{`sErRpG(Pf#@!^xkN1iY~eA4*vsf`aq+V}`A zFg}Eg@evX+J`4rMhd^L_2n5E50F94O(D>*8jE@e$_y`G%k4C`w2!h5(V`zLB(#D6O z!1xdl z;IOzNKWpD~kmvr$pbvsYmBEAC{M3GrU78pxp9`15Wi8m~@H{+D+XkUxU|A^O@{{b%uAE<|&6b1ZS z^r&^sUFhG~NffXfC}7gt%9j0Oj18lJV+d*m%n%i@JfVR3qym;F6fmDuz2%#c>V zf(sNdA)|nWL=-SXfdVEFC}0AC0wzEOEEH70IsgT%15m(10tKuQP{4wq0@fHRV1~2; zW++g=1VjNd5K+JceFe;Lk^&~eC}17b3YcME0W%yZU;?26CKM`QLRtYc_H!hr%N;45GuGzysEhyo@UD&PndC}85E z3OMZ&O#5P#!q|=5poU^S?r;MWC@;Cg9Yx3;Zcp;Ki87q{fcs5O*4G*9++ilL=`5=! zvD|cWvj0(N4;tDG@5g{MLu!00jMG3~59fxjlaU5}hy{3K1=3lYka|mF<0gD_BB0LH z)N6d3@fho_DzS@rikDgZYi7`zKg3+yh9&e-%Bpynm2%n**N*m}tNs}+6I1g~J@e+; z5O_ak>>gHzc>&14>SgDiZO7I!oKD?{EeT)7^DTpfb^J+FGQzu zoEl@mpf(0FpkWN;31h$~je$I24EUrm;8Pm|hO{vdTwn|c8Dk(MVhk7xi~)hb7!U}I z0Rb8Vp`bC)0T=@vfH4pf7z2%fF%SfefyU4nFrg$=3-=Tiaxe*j?^Fn{B8js zG4-=kuijvCc&i8ME%ieZ=YYBY0qX4ob(+I(Rq7i}z1VrF^|$t^OK~nErb=+0pOe2|1R+*B+qqw__eq9Ne0DXny6oU`^E(Q z%vPv0&+#h3mKX7BZ|{ufAXC@)wYPW0cL|Heuf6?gfj!swwYM)3IM+3P?d{zH7rVx< zy?v>`6|V7XZ(k;Gm7C<(-u_IS4N>iCzxMWL1svzX8U6H5WnUiegV>1#;n&{&oPcK% ztOa<5fRhQruf6?w0nZ{h3*Z+7tRc7z;1>m)<{H2D_LWl743~cG?Jo&$vjL1z_8tKi z1As~2D?lB9)0BOc0BZnDQ1;aVYyfb&vcD`qyGy_J_B8@*bLrRKzE*%;F8$iu*9maB zOTYH^^#bg1>DS)=iU8Lm2EYvh96(Hqvj0wiJCFf@eF7YG;n&{2QNo8@__eq9OZbRO zzxMV`0vrW^+8hwz6#%Hs%>w)r0MzCd0geF}r|ho^@CyLrm3^xK$6flAw{H{RcZsc7 zF~I%L6u@_r4AMR)(eP`ZAuj2i&!3J#l_9?CoiF?ttY>IP_Rbe85do9&fxhZ9 zf~iSt^aD&7`mT?S2@&vG6nk1g-<5sr83DB`d;5JV1ns@vF1FrBMgoWDBbU(biX%r+4b|M zE}d1&saNeR_&N0Kw=G^x$oVF+$?aD5`%+r&lI{jNnnH1ZwC+R{cuh)Y|4B-V`3~;w zS?+bFbY;(W4>O4?4({zaE;9%m+}m^AjiAgU`NR0vs}Rkfrs3y(I7j7CDZT2$^-x)< z&eX9va6x<=HX1~=_^#^hjWXbsyDW57Z*LNu?JhU2>g~;<^J1>=!w>_eRjWZa>Z;yu zlZ0`D)aTdX-=7@-{hZ{g-o8+1GlM)a?m7gO?b5-m?<1{KQs)XTa8+-231vZ$7~`~C zP=&sV+#>0UHK<+H+gk-!=BBu+x3|S_L(5gTaP1zts<*et+1>}z{Yqo_UleDPW2do) zt9tw5I9osefMwqqUyq^g8V_FfT>?TNwX1sj>tSI~LU+g6u?JW*8ucE54iZ9h+$+!# zLa5(;0=+^AoE#MB7$In)`vp3l4hSmu0fC@|07B_LC}6ID(1#BRSRo)(;==+~3rMZ_ zh`==(21}0$yja6v>X5)|Gz_*L6S!T&VC=BKyEF{e9v66zr6rcyQ6$(>1rW&FMJwj| zuIlZtiGTw3UDexn2qtGfW z>Hl42+AqfGW8R(CyuPJ1m?^v@lA+w%)}{dWvfyH_{vN$JUADg|I1J9kJ#x1HAx>ZS zj`u@wn70NZ-vm%9dm^X#_WlIl$WP!j-#(DIPBLQpSY)ykI?cBqPP~ptJ^y(m@hOD$ zunwK(+m9w*1S4QI{OCrIfqf`(BhvH^-y1#WCud@%qp)c!6esH1EVuuh*F|>%OWhQr zj}Z-15xjOfKYbthWh`6{7ck3LEW@TO^=y%6^}7tY7O(57?}T$5UU2JAH7y8y!4zH} ztV))Ptd?Wvg4Y&G>M>>4-&r+YdD_}Gw&4EYSbs|V8tD16_LX5$T-s>j$1O&YFZRdn z8F($x_t?g>bZ76uoqgcka9ty>CQev^@rGleW%CBrNG=)3qn!S%4(?QaI}H*D(BO_5 zy*P44UcbI`T|>*J?hY`r{+OZqgJeKP4&d#f0xGm|<8;H#dP=~rD#4Ad5cJ`rjr?s0}IyW?T%;X1|3^CX$MNMjv#dc+F zqAXVoKq(tqn?yvd&7AYvduNxuZ@7G0R}iP$4(J-Ivb@1Mln0Jj)lU3{8-oqyIM-gS z%9fev`8wLF2A(vyPZ#C_sLI~54UcMjOFJGDne+yewBApu%D!e$7iko7X!ZGc+(ca^ zQA^@^pSyh5u1~7|M+|-|Ud>b<`;~2H6h|c+yU(m;^}!6sd?&&h#1WHl*4(D^Cykj# z`xJwzKEgUAKgtdH9Kf*#f1ZI@`aL>=oF$y&W;viINj-d7wQp+P+>B3z zStB*ITB^Al)UXzErSxC7#!`=r=D|o^1>T5S85yBGO<po zWRk0#;_)ySj(l;-*{vA%C*+I>zAObF+_Eg`d}TG!Cz+?~jAgYlHingRbV~Pqri`1< zLb+F30)|s<_YLv4`hiO>`2GZpaa!Dbpd!g_xm#E|29YuEbo}+^<4@unC@isse;C3R zy8f;OlLg;%z`H_~TU?rrDSQUBY)6+d(u>wDZJ@PkP;N=-&zU?UwBV7*Qi=33f@E{V zxr^IJ@VOy=Iy}HlgBI^pZkfatXDpLXR;+67XqyS|-^wj7C9@S7(^EcH;r5k?fhvCD z3b_4BS>F@IDtD~Z%{Vr;O0z+jiL(R|=XCHv$Yl=ePP9SR6Zm5-{XXEV2PH_Bvc4ff zeo7*{T_0~-PU`G-sI(P7K;xj@X9Iz~e?MoQQBc;E%-J6@qe+OLwXZOScN{6|N*49W z0RW}AD_Pvb1f|F;S>(R~%yWm-NZLE05LB-fC@a@sS_IErA49JB?T8vO5P^#kcz}V= zATVVR4hHN+pnx}1d)Jt>gH2lQ!AZ)app%pqq9o-Y1PW8>izg-@lyC6gezZV)e-?mI7e!PSmWVd zaHhtuG59{l$Dnu=8u|$olW@vz*J*Sdj6IBjH9BA7)GN_AIYL*hW7Y&Q_1iX)gR#9K zD+y;}P!jRr;53b29N_8YQ2hK``URMTEnqA32}OiU;}Oq@ zoBtq*_ZS;q#$rH?Lg}AC7g`e(N<6M2AJq8SKK=u}0Y1pW;eFF@n`FY!E#O0%uHb}p z5&wV>Yr0%R*Y~@qD*svi)T1aVrk>3`<>pqrE;h?YPS?VOehf49k*(5SZjXEwNU{(iJmL!`$> zaZL;fu!r}*r-mXM#d6R_Z;zHSoU~C)#Q&Ze;+}J4qnKd0Q5=DSjbh@W8^vk$&Hg@< zs*2rl9puoH&ojsFd`}dZ_KSI!M0nUe#3viSek)>f3E)#vcM~Y~%uRsUJp?OM!n+YU zrE@Bsv2F#vy|BY=0xUqoD;Jk@0aKjkH-ip}O0*y7$b%1g^IyYgS zk;7Pgogj}c4)e$Y))jhv)9A5$v-%ORg*{YE9r)d6&DR6R3?-Hpk*M_DG+8R0f*9L-2`dX~OaYOa%ASW)+DYW(y2uwVGWl4*h`n2MtA#*S?A>AsRL9;exfKd2ud^$u z&oXa8L6{}ouJb9OFCG4iJy`M{9{lGnFZC}2`cHSerJe;_G40xl^p+{ZlLSt|l)F-nT;xS!$ z;$#+|Jeeg=oXp~rC$sp}C$kvRC$j_>oXjF*PG$*-oXlblUW+WlUWSulUWP}C$k91$t(sU2A80JGK=9PgG+=l zxH_m$W-;ua%wjk=nMEMj{v1pwSR$_>q)%osll^?UN zZ#Q3~wMyneB&|-WSh+qSuu7+ds-ZP9uo>jf+IKC28N7~$SMN-%4MGq5{r(d)a0+*O z4T<3j0-7zR&dopN+PA&4xx1-tWJfcO1w(7)nrgjh>Qw^8YU6Vbt=*0FTN>)I(%+@* z;%86;2QNy#zg9oyhrq}D7YQF}_q!Wtn@$huIds6EN#v!;N6h6**iJt+z$6M7C6(+ni%VR-?}({#A^Ys)!<*ypc7 z!M2<;h<#xa!+KdW_QhS~D7gN-Sd;JJDqq~YgM{-9ZZC0wWYEXHBG;O|3|rnula49G zY**Khb+E%@3GNuSoV{$$s@nSH%DuV@X>FZd{C#E@3tr}8$%@&lUr@UMADpenm-OaL zhaQ-@XeqvYz@5hGctu_xnA-$5cKl7nc>lav$Xq3+$`?HNWhvSBiB}5Vi{Rmsv&@qu|~Ae-U@7DM4$Gd@U2DiT4O!Gai=SiZd-(L)5Pg0u1u zVm4ltw;35`uwCba>C7$!(o|L~KD~&?mWc zpv&+jIJAWSz1*t!)FO`L#6s?7#itd~&w)xTXn|+T_{<^}>m^dY*BhTDS!O0!K)9eA zpDpOzMDQ76e;qhJM`8*hF&uyL^|MYDpDVG&VJtu3)Y`on-&sQJJc%t!_+LX_8cjOC z=pj_NB8W^%xj-T-6RC^B@r9D*K$UJ*!&BNMzNqLSG)Y|UAmpT2`6l+kHOCR3dlD<3 z7g%}HdpM+!h6GT+#>z9Otvo}t^74e0=aW`mp0M(K(#rFxtvo~8$_p;A@`Q|)7ZS1Z z3vH*XyqBwR-U22$`cSP&p^b= z6ZEY-!%0@22xH}SP+NJ1eJjs!VC4yfR-RC3Fd{VRGkl5=RZCQo zl_!E$UY^>@GuYG0_hQP3l_wlr#v$Nac_B1bp5cg&a9Rs(|Nj`I0e(U<}86x?8zDU#|@$HrO#h>sz{-H`i|&qpY(izxkQg%=eg8 z=XUrBo|T->Y{{p9-^sv|{TxCN`;+8~7vQs;rH<5T%qJ<3|3GZqj;3w6f9=Mxs4 zEbA>uu(%J-rS$HF5n62Bc|XDh_`(id?26{LzOJ*!zOnvZ5mF*u zTvf>Q*1Z=Zc~QM_dyKEjv~hpmwXFAnFGh=Y5TY?E=7(1hc4+~`yOgVM^B3XnX|zqT z31C@Y!-jXU*u!ssf$KPPCSEo199 zkh{~RtP+GKTKAyT(h__FZ-e!q1hJ(oP7^j;(k4`S?1{L?UXFVd8|)&OvldwU;I`B< zf6CMVDdNxC*Om^Cc$+)%Db8gKrVYi;MPG;)Sib6Kps@GW^*h~6w1!|JSh3UqV*yM+ zivGL?d(5m2^rw^2{y6h6PxU)5nrfo~mLpYzq*{XW51^!bzJ3>)SUQ;l@7*A%D zQ$#&6_*wgMvD7l;`-qx?IuH3N0?#n;8w6$zgIB(bP{bEZs>R6J%Cdf)0fOs+e+&de zi5zw-AZPEMox|@zp!aaNi+u!vOA)9zW)iofR*R4lErmL(e!0VHgoTTNA902OwhF-# zX2n+Vs?~@N6ZLtC0CesqN&J@WNPwDg-YQRp|a zrqrnG49RD}97wpvgh)J=fGs@g&?{Kt5MOop^hnFP7JP!!^bmB%>(+8KE8G63YY!|(e>@kEvHSKQ12@l(OGaT1Sx&RI%b&oJq9Fy*1peR1E6{ZYDb{oC4xFJu@ z46f%+J7Qv{DE;e~4Zg1c-(5&Iv>n+Gy9N*|IF7aWfuTRZg4->r!Bc*rKlclbSEJB( zPFUzTmLm<~j;xU~Utv~HTANU^WH%Ivr9l=jz&f-uyD^45xejAYW}h~(xmW?Up0ghF zGrQW)>`_0nA2PE$Pna2atJrB`I9mP*xrodk3WmcEBGD4H%Z~yhR1asGTJxNd^-F78 z4o5x0!^a}>PbhmB-Q}`9hs}_{7j}-g+N7BU;-If(JU?t=R!huEd@@Fj{AMZ(!C-~h z^)pgNSDLCXR*E^$Ams-SAcurA`*z*tagTrxg=e9CxtO>J#=RfQA2{s=5XMOF=+-$LCs}M$F%)hc|o^6UM=%N6NU3KUi#N#Um|p@HcWxsu(uL3l2W|x1&AmUYK?&CVTko1a8hGt_NAJccNQT%%C_-lX6Sy2ozO?O7~)3 z1=z|+z9p4~q+WPS>T>`AkDZNg2`b!@BJ6qLEh)meUU*B2aIqKOk|JE;g}0;#S9#`m zr>XE~;^ep53vNjf9OvO`lfETY0&pTheM^eqnFMRm3RlDlP9~^tNfA7YpuQzVu!f+% zB}H(W7v7R$Ni#fiONzYB27u%9d!(X^0pP`ZuK;xbaB%)A0oDMJTT)E30f5|+BGB%c zTT%qJdFGZBfnA=tB}L$J&)kwCu*WmEqzGJ(7+g%cLCQIR7`Y|Im^+Yx+>#=2(9^f1 z7(V3bTT%=k@ysnL0!IO$HU}iHR{)?kHw*Aj08pD-1ULo&cL2UBz%KyEEh%Pj+%vbN z2>dRS(;a1H^}HoD0wSdx6T#laMHPixQcQLrmX&%-is(CHStqz9#h8Q9nBb<8o6Q?TNNO~1;4$1rBU+y3jm8Rj*KAfX+ zSW9|xllc1Rftchq)Ql5fReBV!gfhM(SCu&Gl*dKS?#^@D@JVA_RU*#zB3G4IZp`y< z?LcZ<<3zb0w&L457PWIDLgA_s6UGfPxT?f)3?-R*Rf)8jL7ou)4oRNv@$hMQRf(x{ z1sA=l#KZ+bVhomUNnGgbsV$0v#hHSCyFVcorbJszeBy0H9n|BA6?nTvZ}iA)s7UB3Lb;zN$pH zM#Es~Q7LG#hQZV!f!AmlY&|A$yN1EoVS#sPSgtBDKU`H3(WZ(L(Y4^%idU7Wn(`x8 zl_;QqBUhD(Dfl-2=o}^^f#gtv_4CMGC0=Yy3ud@USChC}CIuI}_rFYDpUUUcG{M79Sdqxp! zn;+eNuxkYe_D;P0U{5W20*efuY(Lo3iq;}y<;nJgJ+p|#dS1%*gFQ>K%=D7CAMDwJ z#&kt*XTo-vW9arAi7AN0MD`Huxe|+Mjh`;MiD1u@*fKK_!)`}3>HH$9k%}NPDdhr* ztn^a1AMAyaa7ii^wx&pf~^fgW@|%8WNU+=U~7Xwu(d%T z*xDe#tqq~z)`kvXYeNUHwIL+f+RzAWZ3u!}8ydr{4TkjA21B#4Cck3-a#cb=wl)}u zY;6#nZcYp`oV2w;gxT8ALA|xXu)npzaIm#OAl%v@6mD%0(pwu0`CA)0Y_>MSh;Scc zhEEZqYKcnP+8|;&wl?Icw>B8;xwTQsl##6s!ok)C0e@>l2+h_8!;!5Gg5lOi1PZn` zh>LD*IQ8}I_1H_VU)PGA_C)o$kjFldf^+9!p@F-;c$e>U57s%#&cRM17B!}}HtClV ztBjKmRfetEO>OICpVTTR$|{@QhK-O#>$DQ*s~lEB`ZCHclN*1&fk$3uiedF*v{Po@ z-4?A2rmwU0`>?Vq#4;!+%A3_c7p#^0hYXk1&aRgwcKJ;MB1`)El3@Rix0Uu3nK8QVR92OCG#2v^VI{r(0lF%5uU zAdtoT^M4 z9Wpb-pe6S)YEY($`#u=0>=z+i93`w)m6IZIo1$@JRORYO+~t0`uZ{50QMNRfR}O}mkAH=hVuIiUw7I~()$tS&)PQynfKEtNx3DX z_p+WL_8Z_=3*2)QxV2c24kYq__f;RSDxZjuKV{G+_sZ`? z;{G`r2XXuNNZflSPKrUCGgeoF9OvU-MC2-qB60jk3*-E8P-fyd4ludkWx+hu@d zg4a(CY2J(vpz3ZJJso&lx;0&%Lv6Yvg>;)Ht!~w%MpTFSiVeFq=J{i!+(& z8bdjp$D!c6-8>SLM{ox~b^%t8Xho3!tidC`jtBo)14mqe2me`v)I)e9h^a%xn2K1l z7Otq6e#RLU<42t~s=8w2<_Y8Qr>ncQdCL0c*5;0uMt}_+jT@$Hn>b-4BiC1qTr{>~ zWM@~?6v*%yXTW>GnWMSiIa&_1jodn6+(;~Jj$Gf;H5wbdAvO##el-8#Dp%KrjwURA zR+~1y09uv5tFb!kFMj@QE_XU!3`SF~vD!P2gXNg4p4eaDqI^uRp4eaPhanfNp2W=2 zF8eFBM4#kJYb-p|<&3!x8M?Ci5i6FX=B~NY8oSbBMsdBLP`hyX(v|QH`w81YBc{#V z)Y7_9#m*N8nwVzjlI zh_w~tPI7PgrgB@%i0?{n)NDJv!F(ybx%}pT({UN%%;go9@mpq zY+Lzvz`jZ&--ea#4(Z9WzO*Y$alSKY|92!zBH9%OMjq%Bo;* zsZ4!EwSP76UM9Y8fwYw*$_0m_UJ3lD)pAqGEdUo)(GuV)d}ekSz)8l!OVi7WZhX?HIw(5n$!aIuN)jk5z? zh%c-)hy@@664xp2tkDUJZU|{3XnqW$9=b4WC>)yz>Y=Qm$C3PiNqUja3QSgD;ig2I zYbcxRMKDvMTWly>tZ5RCqu>Y%Gg8)YQvVsKKHoMOT?ftn8_l9MrZ;9;vsK}*Oq>Ve zWY!B3r|C*0qtOxUgB}&=z*(Lx&5=6PunrX_k9|QMejC)GhILpy89d{D#um-=G*I!6PQc4}%(1BcqZHGd69~ZzG`NxV!-z;v|v&y6r`*+JUnKgBwL#_@Uy9DSx-0 zjX4!1@KuxTF7$_W-CnGw^<}UhMX>C$ak}Lx%ZC2Ap+89a%bq4ZgPQ)DB>Mb>0cRPO zi@|WI9uk+cG4Dq1r5ITPybGYLuSp?oG}{0vZB+276XPo)!<`%9CB-Nrl=b9jb5x|X z6D;AY=Vq8>iKu`>`I>+}ByJ5RtMI~MX!^5X+8UL4#GkbKhhOoEKV_K>=ekm8j#EBw z*^K!M<}H6Hg2@c7oM#?Hehd?e*cNyH4YUO=j5V?W4j7@ID?|{UA`TSIfo!-)OzVI)^>q)8e#Sw@ICZ%Re z&)KsdSl4T0qQLdaQc|8|o*LQGi;ZCu=`yr0mZ!dj)Nz@(y2VzEK)7uO=PSBNV@++{ zYd2vdD|s_5jf_mhjK!-!APtV>^}_FrMa%qi_%-gMy}yX*Njfi@u5W2n?xEgoASR-5 z?WT6+J|?hD7|>yXVuU(2f%%Psb&m>auud{oxi9v<5v^1O7=>W+pxl>w zA4fY)R%vW5MoJ?)8otMe6TXj^NSnJa_hzT~K5>#`cr4HL81MHM*IfPXDsTrE%Dv(R z4UHRcTS2))3Uzn+*A#+tRBn~T*cm^=m~@90UJN#4>A_~hvhADKwryH2hf>{P66>W0 znMfp>YPdvXrt2+_MeTe+XxL=72;C7@vGS+tlpPVk;JyLRe~ z+NIbdKkn`;TmYMzzCg?Rji&JyG+fZuflZW+%^haRR=N8NIeP5$1ud;T;%<^S$25x^ zym1d`Rt;`W_>COy3M=(H>}kMYvLnyD_cn zm%(LT^X8x>?vPfh(k<~pM0X0&FrAaI6r{gPqDJWS$x&aIs8KrAvhKBX))y)HZi%ke zDSJlWBhh2i&uwWvZLBHo9C?j#@0E&;^Lv8}l*+wNkP{73OEHA}pr9wGPv6koxN#ZP z&HaL@Ne_xt?gLWRjC4$BQ#aP!2PJN%$rmRQ8aJBFcjZ1LT{1fwH@$81W}F0eAC{=a zAv^6ssz)TME)wM@dQ@W8q|a|_Xo539c{_Ix3BMbH@w;?O1NI3xXi>e#Byv+a#cW1P z2MjiE6S#*9=_R(^A6h*Ji~D#X2bHg;PDpSi29xWZgbbRra5IQ9jp>8T3nRT<620gp+!yRQ}Un6&FXi1Phf zgcQnsQ_9YYxzmewgRsZ7Hg`r5m1felHn&!AfsXN)aCD{Mm~3j%F05^)%f7NZt%$b= zp>BAs&7E1qop(>`xml8ruUY*qV|TWob3;8H#LSVHf=EncN7$V!vBhC*bW7NsC$VLr zd_PC-HgIZo;tgbXQPFbEisF(4un|EM5dx1v6@wVI>8d$xCs;`>fL146JVO!h+KF zY`P?hrO#~Z*xJy6k$^$j(h8rgf`=vJwL*8MK$(!Gu((-*%k|~HXL0Uq;oGm|2?*wt zeg^E|3=#h3)kEX7U@5ve)WcTsa|MvM)nok@L)!)~3a^{>q*;l9FYefkkYc>qzF>yJJg(vPQm+pw4bIvn%)k zbFOBBf`Q~@G^l1o;L|`2P*!W3mm}%Rkv#sf@ZT0vX$#;K{`+sC%5un|W5V!()6iBz! zvH|-^C(LB4RZRydEjNpK%_AtSH=C{ZX@C`Mz*%9l!A-7BA%^J+C<}M={ z7z6(KU282Ff5qhXcR?fk2xlewVy$oOt*FRtsEBTWCN@BoNKi8+$XY5D{Ju%gr7>&6 z4M?jiNI12Ezc;kHfU5`{5tKG&e z&r8_22Myup0}cvu(YVbEal!49dx5+Z710b`N`{7sd|gI{tU4`SpJ6^f2bq?x&r-Td zFdl^AhfMy*$nX_LvQEJ84^kP1KrF6}D4_!^z2@{9;d4U3?d9NBvv&&#q|6zHssamU z)~%+q5l(HS4Tdggq&b}n+gkZCdA>)?X`SBP(E<0i!UXO&QVZ@fN%jT|d^(S^xZK4%vGTLN zD-HDwvX_P$nMxpy_9mjG(W+*fMw^EKexvwh=jhd&UVKX)-PzT_d#mOVKb?ryM%+8~ zpYa9i&yd-eN-swToVrEJ&6vcE#@*$%cCL6;pHU;VS`4Y+?>D7*S?uA#rH~J#QtLE9T9gJzJHDszZh|}7}gC`MeM8? zro(9*ASzbFuu8-2=X$6D6`M+SytH+AqfxPGR2{i#yd@l)&WK|0n~ns+dLl*#ld)M# zfk4KwNJjvd>64 zrN|=PYwlu^Cpo2<8JtoieH>pyb&&uE$jm842K6aL`JO#aDasS46#3*SMS0?sBA+~^ z$frJ~$j~&Lc2l0Vlw%qc}7kyDBc1*a4V1g8`U1g8`U@RXuZ@RXts;FO{c;FO|} z;FO|9;FO{ucuG-YcuJ8WeM*s`;FKZ(Ii<)z1hs`O)Fd{sXIK!t1QME)Rol+!%rxfL>Pbo6k^ORy1 zQ$|iH5)Mu&67Wwc3ZXfr$Z+J8BEj&KVgw3KDH0bwrI@|G5!-23aPU}bAcQ%1O%Nyt z7n>!J3$r3#c2pi#el~Y^HFJc(bnW+*+aZil{_sr$%s_gzH?+33Vl?><4E8hgHfZ-S zM%)Pq{&C_-9HL6+;6-O7c(HC`e%8u@Mw}m{tK*xQ(>g>KG;VL))GUq+1h=0!m`eek zCUAiPM$d(YXccmUDQMN~p$0;JB`6BWuaEc%5$$b0IBFii&aDlY7vI7WzZGzAj@Ri% zx956b^3Fo;SKolR!Wjr8=Hq3B5yj^KS_%k1*Sj6{5w%fLzXdO(t?;DSZG8vGoOPQ~ zziukK9G2AmVPKXoBYXZa)pd=fwt^6zWGDWbYiQ}o4ox^ASXjiy*` zfIUd@C7l8BS*vOo-UAzW^28Y}CUzz@lhm-$g)1iR(q`zVT}?wU=>_x}(hWHv}3suWec1 z-PVn22(o@LknmpF2%imt_#P1D-!heZ98K{&dIrs5Z((cO-V{|nZc+_vtiFlZUna%k zV!7hvU*@nAIX`Fc6e-?40Ump#K@aj?KC{>Y(rYK{Vn}+fPrBxWq<0un zmeyuUV-|g@C7W4cB0=(7~Ch{tq`^6@rdk&hV`1!VCu96uHT znPE{vAQA&Pr$EQekRt89RfF0#p>tRQU-5u^!4;P^TWAx`fh9G#g!>XKNJo?hi0gXD{x+-zDfvb`wX^N)Ed6 z9~nwY%CtbP=ZH$S4}U$3!1T^aLH9aNG-Z8daVXHp5?PUTG;=uI4~$_uCIjHsLLHW^Xi;PZpL);W8N@mT5Xt%$4g7DLP& zUrx#q^;YHoW}+#c$8|JxQHL%->V2*%ubr-867_~eh)Tp4ZC9~HaZT4x0DAWYS!<)({g?7z_x`N&cpLVZLTcG;j z>nDNIypX4};n2oU@M(aCz~{B&6(OmJl8oSbKs!$OiKR|^@RuNQy;cl`k(@HLHmO*l zZm}m!ixH3iRjf$k4@K~}!-5-L8h<2$XO&`obe|o&Q&(xEe~t~A;Y0x4k)N}!a0Dpu(y3v%3laQSG(qEr4z6bKk(fk8 z()vbX0a1}Pki_X+W@v8RqRb<0y`^4(u*B3)`k~BIyab|;021QRJsDI|(r(-$NCWJ@U-!BPt8U1i@9 z``@J$RmwGn|KBd9WTNuXr4+)!QVIcoDMbj)QVPS7r4)kUQc460mQsj|E~RAE&*6Iu z&ed*gZo(}~T&7#!Y)(=s`}`P>EIa=W>C85}7QhLp52F|gjEHwZlSArUtwf>U@k;ao zss|rxI0RB({osXBe%8J`ofvlOWQpTUtY+0nBFwYphaFp3tzJC+9^42NLThP0hnG)} zHxW(m6&wS41?Eu&-$7s-0+^8pX=5xT;j|mGSxE30N=TE!;lWZY{D*LwQ3yMbaDHK| zgX?_i=BW{D(GXRmRB}4JnT?m)4jToANk61S=Qcb8gK>nxW(+BzAk-9JH%%&!w@9G| zGj=hy`NG6LGo!s`c--eMu^@(H zq^rkYaft=*4tuAevGT9(wJ{waa z2=vBTuHobC3~^JB z-4Hmtgxxm>@1$yOfBcyjjbazfHwg5%rd`0Uo?OzJt))h(g$Cj2o`aLuBm}CwI7Fa` zKn3*iRutt~sY<{f_pzup2$g{Jtgi&n6`}<6F!Z8wo`?(wNt5mml#EbRtETb_hMZ}l~Zpo2fG$D$n-i}rz= zth?B2M$<^IB`Z2n-PAA%-J9vD9hl*FU}mZc%S!G8t!JRbeN}=^3mXDmrj0~iC!QQ6DEx-UoE=+6eO;vAow&Ur$?bZ_xxcJ)qv7wS_7hIpaH|~OEDCg$r71m z8pIgn>lEjN=Y-cXthsTnZRTUpT2#C@}fcY?W+OPw3)-K z2nr&2JxTcQLU<|iHK@EAMXQ?pVq{FZ6q#Kl>V^|~>e(FqN|PJrg_op=2K#-_y2O87GV{73^QI(m#o=Uv13sd`k_K304n+MPnE`RUmFWRS*2^QKtFK1m zB`TV4>g=#0SvB_81CJKBQcLmxJ#!hDDieb~WYne7e`Fz#_F4GCtouD~A|VYBacwL- z|0Oe_6={0V{L-7z*JH?2X0$Q}Q5H7adLs z%8oX5QbXhFSJ2StU3Ruv#bLYWh1Db&&ITgG&scwB!g>cK$r?mbS%s0@P*(J9NDpC- z#t)edBw0P?F8vtQ%t4VKMK5EiDz$H1-&98D4l=^@+yNYTK_z9l=vNkuO26r34&hJL zjYMbo^Yh58K@0B*L?_yt4!hd%*p0E!e!50a_;QfOmmh5{g5@b#3*pF^l=P@h$?!!w z(--Ni=*m`hm=wApwTW{5Cd!M%NE7w)XA`sS#qe!5G0{S>f~~t0*r> z6O(8#OwLH60piRM5gnW|grg;r<-gF3`nEEz6<}JRO+`$7ZE8ja2MQ(7A1HckWk{M} z>XYfuy|Tiw!MRsJ^CDksLX=)$2<-!HTe}2=)gUA+Gd=m0~y`GL8m@0zC*pGwcTY z1d@&#rOSc}#H$UL*eNb#A`>T`G~RMaS3o=#cgJb{7@6{)CKsMe^;b)#Jx zPZk~SS(uSULmV!A`4WcG9cSvMfF4gk9EHe|W7? z1!FY&B8GnDBs`)?GLu!vNla{*4wEp^G{_BoAARH0cBfZ3IFr^0phLou2tf!3EhgWg z5ExY+|U>%XCl z3dywf8=WMvAPprpkgljmon*>J)eveF87#g=G4IWut{4^oqYH!K21rETOL8u#`)i0| z0J3}o5YaCF3t(ir4>=3#DYE9PqNF~hxJCLDZ+JnUqD3ikk=WkJ&0pvXS&{Byku};3 ztN{3hX`wDfUeVV&_GMJTL={iph(MS{bkQIrx zTAf4z#F%6O=FZXBWK>k9{~L9yZzR*Skql)$5Mhz&6H2=Xccw4g;kJ?VqZT87+X$V2 z*A{JKb9=7*K`xR6K1E)lB9HdYPgWDr{iHzlK^C2@rFL1dzmAD!{(tz_3s-e)^{<$f zSk@o#ifG}7>Ja|eZi^LC^0W3$ILbVFGu-}67^i(3;|VXx^>BbpC&+Tr>9nz;@e6sVI&QMy81_h2t!%W{+ojnL5EqH*}tDE;=rYin~uQ)hr~Y}?GF z0lc*fUvoF5`L}A20nTX2RTiCBBZ+j7=XG@mhmBF5A8x|6bsaVZYXECaw#uy$sde5} zmXmnfa^AA$UhHfiwf@ByUv{qD@mlBl^*4KOd5c#$iNnsOF6UR)Yu!(JYhH4`yu;h` zwDS|I>wt6X4tsz#Z@X9fS?^wF(&1k?SzblVc7EV^qhP?k{>iri9E;CI_^$1voNZlW zt^wk;_$5Hxvi%Y#z0T?Gaxz98y!F5Xm%aJKN^ireCszIQ%kaEsKjCD&=5)_RhDW`5 zbGB~1l@&{lzVyWxy%Hox4VT??AIL0cqqoPY zdAscs_d4nO@AbwGZ$YX55Z{BCtG2)G6u$lHdS{=t-?@9|CC-m_>|ap&;>uNHorE_^ zhin&PU@nBfR@ZSLoM2RZWRX^?vwPjTmTizK{NNEBorx|$<~a0*^XWR=w642;9b9(- z(p0+FK*bbonrJcyRM*Is*0V^&9z4>!MncX|Yo3$gy=`ZJS>TV&GWc&P%Nylnu5-HT z&cDdH=n`k0x6a$^JcqR|XLZ+&&bCX&I|IC~Gghov;k4CxpWeOdYUil(x||tx-tKB| z_bPAqC#IacYSol;>z%cAPHvaC+v%w5KKD|mPu){qfA7WB-hp>M;SJq=-pt)EzO>RQ zIPA20b>8URW4zJc?wg#ouX!)paWGXXI_40#{R>+&Xent=ep*~NPB=VGqxsDoB=DQo zZ%(vq(8@k8xru|3ge=+Ix${i3UT0YswAa|xy0wq{z3}h2D+ob*Ls8If-+A|a|Kct9 z&(5vY-@o14wZ&TvH3IzR!%nZeZ~C-1wrf=Q>>&1e2ZZbDfL2rf+q&)HxZGKe4UjDsQZ_)O+nFXY`(V-lgYGxyS22 zY2F6!@nxSleY{iYjrx`3_QM_C8xpwF@+wv@xDa70zAk>#ZI>fAZ{yIZPGa3#9rJg; zHUG@BHs0^$d-+b*VW)GllQq}*>W*~_pZcZqs)Z5b^>QxTdGy7Rqg&n@QQhLzOmZIH zIeEA9vf4A>I}Zbx!x)44jKeoOckVbk-}$Mv=PH)vReJ@`?Dan9Y(MN=wWIE)?(To} z+TQ7Q{$0HWCMP?SySx{juk5tPTF&oOmy=^xTh4`tozL$?E$wNR^BxW(TF&Qo+Etc4 zr_^4Y_PcXHZv&(@{*c~=e;v>^aakg zQEQwb>*jdpU50vnYURq6PIukB-TWps2MtM-rlRW>~@~m`G%8!$u(#f zr?bw<+T(PtyLRPy&i4He;-8b4>}(xXGjE&I{I-*^&got^aoS2}dmZpwobFLh#@sXN zm(Lq9f6Al2r8EeepkknDf&y#7Tcht>aN#HZbN$U{;L~?8d~XLTgX7CN=M&w{&bFgO#z)1S z9B)tlZ*R`EZM4Fl(H6G){Rgzj|M}$XW6rLOD1Hnf4(Dajxe@v~5F>=)R#5KcqOp4l zQiC+X>JMmwkHHcvgUR2fCfwxXCpo}?%EupD{qC<@$j6#Kf6N{V+Zp$j;J^37<+kT| zJ?0B*u2qm{r$PMCP-vD_f8AzLO`A6HI-zNLjFRJi!TDB!?V#Kt(j71Sb<6#D-J#ZZ z)^~Qd(|eR=*ne$+q()yG0EVv(C(s0HPz|bs&6Ba#SO0YNDyL$<({%LS^LOvwa89+8 zI0{=bYWmstc6WQvJ9%E+{^>7vzcXpd1}ER1U^$sxuuB);c3}r)Z_Mv`O-Lt2giu5o@L+!^XQK`20vzh;9ENA4Ha+a<5MOA-AHGvzqZbw4wt3t+Q(Ffisx8W4Ovu9 z!YY&o?_mw)>~+r6I_GS! zVwLx%ce(RR<;}%w(qX&=bm6(jo4?yT^9U);aUN&GUY14=i?G0zqPr zv-PlZEna;3b~QWQuQ^-2!_Jkq*UKw*3idm#-rNH#9lXx1b8fd@n{p$9hg+S(b?fm) zp1x;+(;E?)hvz%}@lv&RKVIubIa}wR?qpAPwoRS^>``YS{=L5AjVCX5y1h|e^>6V~ z_ItivdDFhT(7EWSGiv|p4NlqH&U)|Y2B!!weA~UFoxAZ8wA#r#>^!`~JKE7b$N7?V z*ya-9e~(Jr*0rrGVmsaymBz0koO%I-i1~Lawfsdz>7&|`9t(n$-RSHVa4@??Sbw_? zD;!4L{I7Q6E!bLQpI-R*ZC7_YXOF__!BJ5&-HA|Kb#ka%$_G$#u@cx;LGTU2i(m-?)WqZB~4L ze0AqdPM`fNoeghvcdlt0z8o%@}!-hM_sxpV(}kg&SPH(%}KzVY}5ik!07482*1d#9g-h$5?l+ua-sF`|%iGTQ*PMC(UwhvIUsqM-eUe*BC=db^EK)I)f(1)R zp)JL!n)Cr}DR}c}n?m6xO>WZIJT7_k0Tp5?54Fw&EiiDD{lW$d;jR%8rX#)8V`IQRkG>a zThIPl>YA!)siOwUZhgz9+m`?K+czw0KJUqa#i_>KsdEQX4GUB69!TYOrz#ev`pXtx z29mNF%hr```2lvhR+v%e+JyiYrk)J8|2lQ)iqwJ?sb%f&T~j8UQgfSXQkT7yx?tgc zbmSGOXE8|Kb3>JEzo)J(Tll`)?n~VX^ouBNSqN}p>eXO-s`sVKHm@n$g~{->E0#4v za_Nj|sXtx6B6V}gKz-NZc2A>H3AKPnB#>VQ+p2EVq}e zKo#gwI^$$f>bNi=K$2FxIhf}$IxRr8{69SCrkA zn)6cX?CtlCJl>J&AJ}CsJv|va+E+oXDVR_#L{GW*c7wlb^5g&WtD_$rOtlQB=G>K9 zIh;D`;O*EnKBvSil}|5Q@w*Gl-q(#7GUWRvKZ~90O?%G0_q^08WeYzHyX&!}9?TB* z+)*|ax|Yqj^E0XRupwSCx$Hd{I8TuM{F1Uk`Mc(})Z5MeehGA*{AB7K!}q36$ENpf z-%h=7eOaYAuIxX`&bv8P^%4f^>@!!qj8)}P?QrQW2NqP82obT zvIkT5q02rIEKHsK(xut+%1*Q_QT5pmcBD2Ak3OE7T6%6t>Z>=P;> zJ&g%M+0&^hD`ftP2r1i;I;shO%^I!)Nvf(F?q4#128&wJUNtN0yCBzrZ1QbLevdiVkKIt@v8Ku%x`Y^xi4u zWwl3_=FCayrt7)+_!5Ai z725SzV%J}$7L`|ibkd^oSv$q9o5il1j;t-O*-=(ozU;=ME-61$lDZKVE`x3dEkUl}5bZJ9^KH`}>mCu;+c^dEckfV5f!NSx> zi-lM1(Ww(kiiF?Nqf=9gU$<&FJNLf5#$f6&QH1 zq@PH=KyTIHDLr$b$s48r6_O|QhER_;Ld{Q+fkVBV)DwN=db9FfWw^%d?aecAxiwJa zNxi*VPvpo^NDsl69f5wV^cp@z>E$OR?$(syUYNh+i4CCVZJwu<9`U(T`rXaa?{1QQ zw?p#8jgyy@=enmL6FiKr_6Yjl_t2t`A`|Q{FI#MKZ{j63ujz*(Z|uw(Bk7MSkMXuc z*iNdF{0L z==@f*$qjWx58*SUd^DXFYzJxAy`bmagj$u0p1qB6C)dZ6-!Xc9q1HR3_!kwQ-;ah% z(tk7MjEbkDh%d>{8ISkiP_753ItT}{U@WI(NrksyY z8poxb_JN*z)h(u0)ck>TM?kk zk1o9wr=>@it})YCTg=fcmo{A8m|4)){dc%3d?Q($BkJB81v^10S< zF??>4{G<5*86G2SC9=*mWSt6R9mzKDi=hzzVyEznfAyYrA~_i2mK|Msv4SQuvtImL z^Q_mQ#E|*{1s6#O6!MSY_fCN>x^0Gc>zaf3y^22}h96V>QpHQZ5I*s5&q1%4f7(4~ ztcYP29bI}w)Q9+GoAQr;)(vsG&IDsA_##?Y*mN35e-?dm^J@Tw-%100BM6sa3TE;y z`R-A=j~Hq*ekxxfztrPfb7764oFCFRfpE#utD<~|l`guK=>78_l0D>Kpnqj80^Ql zgYe@5c>%lqO!#v1wdFZl#Z07~|QAgikk35i#udw4)x_A<_FUWv_dHuV7$};>k z^=0zeZ6}%ElEyO@_J!@yj~P=PdEh0J<=bhE9-;_@`DIf(|koc;mhCF z2z-mxeU91GF1UFH?%0Bt2RdO%e~@YE?(fLRGp+%CsnR)s7YBE%M0}?&{4#VXX0iPq zw6Pc;-_837xur4Hl*nTI&xh*=K;PHCH2i9~vCVU#<*+>V`EjQWKBe0q6#E=_^b6wr zVtoD=r}2j5toh^0su!HrQ7-Vzr00#N6`R?|}Wv`g>C&TJsR2wQa7?w)EqhdmG^VWze%L8+4hj)3+(x27cXUtGjV! zLu*S{*LsAd?IZb}882_{U7u+m?7_zkE{T3yv>)Adc~5(9u!$c0yqbHK)(ze_mWE@IaM`iL{>sZ$)cy> z!;`to8}&=fi}Ao~ODlSCXa7KFYk!anQ_AYjz5#qpO8Z^VNmh~sHidpcxZt^vf!^LA z@+~Z(Y7Ox79()%ODI@gsM050iWxZ#V`7~XRlmzJu6s!wTaSeVRtCb3J(?;U;3^HC* z9!Zyj@)C*uK_x$;i^S5PdW7&ry7Gsj@6yHZlX@01%RT%{R!`)yBK(ZvN`m_56?`Q` z5&VOqjtI5{bKWs>I6@Dq{wb}Rq}VG;V?H7eeM^Eyvc5#^0V*`aLacR89%sVs&NHje zQV!%;609b;GS69rKj{Rn{)&S1DQd=bpmo2dl|h;B_o=F&Jdzh9rFsD$O7DoC?ZbA7KG^ zZ_SY)9zU=)$2;|G>al=V7Zs|nN*L>rp-9E61DuXW>Xi!iNN@zoE-h z-hjnLRE8qfuKGotFYTS5_guV-Or zD1u;~h`pYORIDu|x+&n7dJWzCMFlT)>{q1~T&3sI;DQmtSA}Hj6}%%vjVky#J(mXO zj}ZQ2NXEFL{!k;{29K&*KXjU=$>@QsGdU=4i0Z(_GqMl&dp}f?MR2{*eMe4@gKs}BPD-!&+L#-l6$+o|;^jt_t zFkfh$H-qqnHc{w9j@N2}6w@L};*1h})ery97~%m$U0&(jStY^AC(b#1Qc#{=U1e&G zP}IMKS`ef~e+Dh$ZL~nOsc~AR3I3f!H4tQ5)dz#Y`7;ND8G1T@=8WH6zbW|L^{4(W zSYG&2o-2?41buwNZ0jHLX470OO>+KB{FyQDw2*revM68jqyI~#QA55c{Fk=7^~s-K zWKo~c7e5Z0nBa4Y`mbnW@@Cw>SxroS>_`9I#3y=ragDZXvz}!{CA`yxL47H=$`Pj){IFfpTA8@Ef zfIh!xPz_frxL(i427O49TY?$8CiMsJ7$JIFSc4!{z%-KJ zu8^vbHY*%S6TzHA)e)pwVr-Ka6|`)ztGJfn^$xX)Ae9qdYe!h3goKIEdCG(ONzf5) z(rc50TyRY=-BT@2R|-1Tp)Y~EA?_a5JN%Z3bD&{G+F(qTf7i4cQyWt(g4e#4s0M=D z6=egCrQ1(+gakjWC`-uF?&*$@-~)=Xge>g~2?9ggpj4VAtAv{5ki(e6cQ4=H$uqLH$%c8b}%^KlkTlc4)?i zWxE08TfHu3bl_XvM5{mGy5wqtv{c%&$=Q8}vwJl`c0x+p9ea(7?^OgtUti_>dR5%lA6J#X z5UNfv)U%OIdugZ?!7Ci9k=A@ZMA4exhA67u<5X|-^=ypmIag!5*2Q@B2;t?5E5k6| zU$$$KKLUMP`_KKZAEgN%Qq-iNX5q{cmL@ApjN^WPNHZkeQ!byUIX0bDxX1A6 z?*f6%i@6)c?S1k_Dc@Mecf z-=g3HA<@Rg~ez!V+hC-6aaHbf`4JFDc4YW#QhCj^NiFs*WJdOiXvbj2Vj1qnVF6 z0~%?-KRHyIAf@1@8^Lcm9nu6Jbto@&*61Z#S{l@NDQuq7EOczr1nIsxL4O6-v(qqM zp7Ez6L-_SnK3rBgv)XQ!UUZfxWt(#Ukdx9x@C%AMGU%VaYtp;UELiswu5Owj>mCcCntZb|d(pLp2cGt0>zkS^8c`Nbs=;Axl4Yg!KduI#dI}-#An~!6VP8 z3FJT`A$XcY)f2qfp}Z7rYU9sw3cyT)S%+#Mc)OyknJj%iBqaES2%#3-iR?OE#WcZP z4%I-AV$d5L2L<-%`2km}p5Wt(vZ`vqoj6xr<0_^JUg=N`+Z5d4P-%jpQl3l6h*qL) z2yReDsi6Oc5f(N%?j9=|+~i2s5o}h}G1z23Mjozx>o#m35lew5xvM#)dWVqla%o0Qqf8L4h4w50CaV?X59|5#q=IJeA5j z%}@-2kl zfQn$q+jHsD%KLRaV>(GNG(|RuXv;pQLS5VzA#*$w zIIh$JC+Rt1BK#x0^wW@ppnTmz4zvrwqZB1K%Lt#WxMPF8lK9Eh7QDENp& zr3pT*sPdqHQl3Lbi2qS|eOvx@;(z8?*3*fV&YF69X;p}#8`g&?g7i#W7rN<=u*yRU z?sKTLwKn{Fle%QLb4>$5dJ6;izzA7A?pS%9iuGnXV;gAfU4?5g4rp=G^dwGG5?mEp zU?Gy^`7lnxs6JKoD-9NS-78L$Ac-V-krS81NMd+kj3D@P6>erlEYM8}Go9y^o}{J0 zTud|c8w>b(`N z$?-IS!fYh038@H!JYktg&WjX4z97i8yB*_M;;bHo1Rv76mXM`?4mlG1U4)P&{-OdL z3Gx>imLp5=a)VPn!8;UX36;Hfdbd-hjv&pEigj+AfnXzH$DlP&Ei>QAx0tV7_r{6O3D%WZc>W7*RY`LUX`YWXplL_DLaC2NMQDvbc%+;W{ znti623%{f)KBs5l^`gRO>WoKlgm)?~VE`aWjU!24so=&CIw4qceXA|wS{MJ|E4Ov z?o>;6DBEq0efsMPJ{F>$Q}9rT`mKWHPF#Abf-^$YECuI>sJOpwS7o@&kya*rgbFeD z-RPVTC{hRs-;htp!oEC0!cXKAvT&SgCmadW7$cg6Gx7)t(?mna0vo{?6SFwUVA?h# zPh~dfm3cVA*Ermq5t>WcB9m~a#~d$dPglK~^_(!Ly-+VLa3pDh+;>RmfH|eU+108i z_)&*iMer{bWuurS4tbbD5&T(Lm*CGMby@nikWe9a@>Q#&YCB!6MuJpERI3|d>2^n0 zNAO=As*xa-v2|GrRipo$YM)c+?;Ni*!7+zwAfsP7RGMJO+gtE)?Bp#Jc$MH9m)sf% zHYv)s2unLdLY3`KZ_`V2^ehobc(JRNCZ`P{ihE&Xp44Av#<(LhlQ}2Nu!kTgETAG7 zs!&fAx||C2aTQR}8KwZo&-=n!1pi)9)>kZXrwMuye5XN)rH{yGtF3AgZBfb~vlDtqiLNBazI@b}T z-L{{xMANZIAxOI|AxktJgaq@w;4f1ASZGS}LQ{elnv%TGl;DM?Brh~2c%doD3r!=w z7n+j1&@|$Ep()7={%U4S!#mS(%)Xe3yr zsN~k+5LoIe)+u9mdQqWwI+6y0lL;1Viv2BZN+A z1>Ub$Kjb7d#Ywn!W#WM?4=6QxCzuy!oMc{wCfKuGqOG5!-~xxLBe+UY)?$`E6%xi3 zC&>pLN&035!&(etS9yt&wCXuY@iD!|SB0Ph5qwQASuI&QGG+OrT?legog8*2YlSvf z(Mx8h=p`=DS5`yGf5tV+%a0#!FKPnNV%6=v5= z6ICcFgji>-0?>rueTuRT&e8)RA?wD^Cp(flg534OI*}k53j4YdmO}O%`QqFI>W7dc z$lAiIDS?;Q0r?Q!r=6--5&V*(Qo#pq@P<~7n-rK3cqE~2;&sA&4q$TdfnWf?h-8_v z%Pjtkk`ZF44Qs@`K|{Lqf=DCGH7(kd;K!VCeK)vgo2Uio;_Q!C#8>o;C%g&L1!dBH zn1@VH@VmDycB1mR*YR6LFrOdZ(NLGfZIx?ge?7sVnImoF}2-tWa%evNWGdMt+j;X+q;(bvLd`YEne*^ zb2+~VyEI-A%zfp*O5f6CU~Vo)f4=IL#-xQp{c`WLzbR8+OdoK zkxJA$CF%%LGGdHiqmx)i@O6h;MUY}eiMkP%UQ*S-j^Lm2w5=Oq>0?u*Voq`r%FZ46g*yJIP{Q#F{>Y&key-r5 z5Ot-BTJJ=H+Z+wAjV{a@exM-Tfp-C(>-FJL)#88XS^7EQ7ZeBEm#ZwwPD%%3D(_XN zLOsFKW2^&gmx#N^uUMB<(ci80D>fxn^fx#wRG)M7jBZb`x~Qst#k!=5zN&u3rlg98 zqw3nEivCj@G-O3+Bf)f08~uuPNfmt?{fbRV6@451iffZ9`Zh8vyj4RA?HCWPI0+t3 z&wa7RPlXMU@;Lwa+a1QEryl&_{_o#v_2XMX z`0@k(ia)L=UuM7;7sT};U;d7teE2qi_%Hb5_4lhj{P{kAh0oWX#Oe7H{NYor9e3)P za_HADOt;tX(=+`{zh3+{dp*vd?R@bW_Bvmn$+u<3>9;B3Mm_J;Gk-V0hxqw(fO!40 zH2&x6`7%9o3wMuB{NvB0^1rIzFT0+l~m&&TNb z1U+-Z`cy5)>p!CSAL{vOJ@WzPIQ`=>dOoRKi2gs7{uMp*$(m_u51&8gW6W`R*C^e9 zo^R3fu%376nf{O0AFrL_^qOZCUpXiwjNsc>*6wh%a zE}!Gcsp`+u*$?#08%-A#@b}${=f1(cTK`!GHuW|j^ zzbf=P``1+k=yxdoBYM6~&+!{IUo24nL{)&Bhw)9hxPFf*;z>QfpyyxdnOkVwFH`h? zpZ*{5KvjDuJ|7YU?fCzv*Mp#=q_q#<+{jk7MiqR&7E6N4AfGl^sSNyRI0A=4YU(9EYY1tPdf4i^)10G@~aJr?~_)W8?72f<~;7 z1+?u*IbdqWsr3=iRF6Y*4`@cmp^-TPY$Dm1%Lo*po&5$&EwvNzjbJi4s5Jm>}2<%t3<@&sKHe(?)HZgI66!Xub)W3ha*ATA;z#q51~o z3lV5&R|{W8bQr1iJ=EGWjz0ejG<%ECRLRGLgc%Nzl`4@>Ph4io{8QD|GSH$0u_;v| zQ4&3>*7x@lW8$Y|CX4P|wIyT(A>gwCf2X+X0#xNf8j+GJS%$v|i`bFEMaeeuKb}QN zdMs!v$D!dv6cSabl84R=0?r1>B?$O{`LTvZB>Tr4#me2s%XbW4>~ zJtQNE4{b)O0VLjx9+Hv9fU+5B2#{zNJtQMZ9;_KnFBb#b4N%PwE%K z@+8n4!vAnIKMSQAwJ#N{A8fChH+TLV7pq2(i$IeGWO9qaEE7H`hI|@;sl+{|5YrCK z5C%hO0ow|Fz>Gy`hJdMY{*icwDtgf4e*>Dma8Ahi^T1T1`7DP0)Y>I&u^M4CN;c-q zep*9I%{nDQ68KqkR+IoGX1_5sk+G{pzJu)_-+_jmngl(uBX!gE?UsXv;_XjYNO+kbb(Qiv9E--va-JjiIE{Prm^{ zwx3>Mn>EVD^wWPwE8Bj$5Q*bKkB{`z9O{kNPn%KG_EXsds*Xtt0_mr1_;35^Y0!sJ z6Ou|lt;UrKpi(7%o)b#xr(-S-3-{A~(8Bi9We_A%!-M_wRiJD?#TRmW|C(b?8n*s&Gll66^)d zxNiD;f`*JbS&iGM6W>M;M%}YO!?}=!KrkGmbP{!oFJ{zz2qJkyEu@pEI}ZKKMjf9v z53dU(qr*EZ8FhSuD@r3#w+E?Xj9IAF z%vuKXF2NLuI(#G6%&qoDYORr4sE-q@Wj40@i0!iX1Bd1v%*IZi*shU~`f(WbjiJ%? z*EAQ05@XSWad-%5;gB?^l^PO<`&Tj!@6jA5SHeT$a4SYM8;2s*KO_!koX$A>f=>X9 z#Nimu*plPf?06%7{?Z!y`8(hu*(!R7pJ!l#Z2g>^$HdRohvDZRqwiQhXQM*2Bt9HH3?E92 zSs%9I`_A1hTS6BaPOS(o8>^Mcv8sDSVLVHI0@J*M@jUc~{G8Ahnxn)&cC1XG(LJK6 zppmPIGrh(2jWe5;FP??#(i`Hl0;(>3r=y8&`cssmxmW0kT(69Yg24}BplMF63^qc>1yz?ZMp?qP$70mn+7LCU!01~Z5A9xn|=oDZJT!V zXZi$nX2cdzxj5l12S)Ii{a##B_)DMq|#n=`JqsYM+ll!hV#wsJ%rNH@*`~p^* zEomOkRjsq4qym)moN%#+#NmrqGY)Ts&HNn*DQs>z1%rhhFMb25{vmUu$4}=RNuG-E z$s|_y06ku;KIvjreuwMxk+ECuVTeVkl2d$TfRT8vK8$$Y;NtlK)Iz1agE{Jcs9@tc z)05rY-P@M8OXKEIkR_TX%{JahY)BBAI83;IA*z{qR5#n}L6Iov$RT;-NF?6z#`iHO zY}=v|^?g6fJnHvgV)I5eB7+6-b8`_t(}yoQ9}aZ&BPZnN1L1WXhO{x`!^%V-3e9Pt zsgOO4pi(3GTwrR7u5PxpWm*FB%UUzS2AK>n*FtCTvl!vL1bl`ZXTME93z}$GeIspJ z;o4LpHhQqXH^D!)zx#7h_IH_QN`xk@cdE=>V&#%$xL#;3p)`wYiqYt<^)Rzv(mKw_ zT5?5mgbxaNhn2OY7SonIeewtZRv{DwQ;Gkw<%V5r{1pqsLv_9)4OD1XcwHc+sa;Tv z2C`;eafQ*@$`WqTL-d(hTU#sGLNszs`e0QL``|awy6+TpHTa^|)( zm^0U+Bl~2MGbPx^%b8cBy=*_71SUQo$(i>-g3X!HyAae&`top*zASVyud9T`c3w9M zjAX0uV1Jiq6m&k{+0z+)GKKwX*z`DQ_pm;pH`2dEAJHO_kBQaASBTxk<7aWL$SzK^ z{EF)FX=(N*? zHVWtPy+zucZ7T11ux;9%?dywYaI7tmMQxiRKl`c}{o6s~+RI=DfEjbS7u!(-8^HaL z!}!s%61>Hp@R(S%BxC?x+2tU?X5*Qm5QUhHH-HAtP0q%eMMt3~Ivr?gKn+7XM!bb4%56L9|d=@jw`Dmx;XeBiyTGB3BB#u#t9TF{%xo9~O zvV3upNq*rniGRmgSV|^2R3xH=Ml#7>SZp)NFfh?xz^IcKdf2E#SI)HO=2VA~hhkqA ztHd#Mxk9T6B?%mjo6lQ}w2rh<^mro?RSm^O_r(085w#1Bv=IffV+SKjer+sQllBUv zibTu1Kfq{t3>cr6M9VFh5sf$Z8#;_gcoO-?=8dh84Gg z)UlN_u9fA%jLjK&Dj?g}@0$7};Blx(D~o?VB^~S(jRe=qww8Dm+X%5^Vy*0ZowK+* zTq`H!7TpmN8sU(%Y7_OOl_y=#R{j=BeqWYW{+es$&&RB?MYGyEj8?t`xy82f4^c6> zmD7jO%0sS|mw}I17#?ip54%>*^=Aj$de804cJ;QpMh?CV9u?YxNxexpJ_wp2(ijm3 zfLX#m7-0Co#!+kkGKUeO=Rh-t+fd=!;kUrlL}-pcqveXMCWOy?&*8kXDvo zctrcg8;Lrnp;^C+2I0Xq{unx!?SuZP%g7vcktws}=)wFWYjbJ0r1gc=kjVV@c1Gr> zksaEjj8KxuT!TBIHvjw%?d=~jS{->dN2?mYtDuTR@7OreD^Go-VK|xtI?GJRKV(EZ z1q3$2<=1I`gv*FlivKVOeAfF+fRS7$E5z|~-9AK>&2_J!7Q!p~$E%s?|qgReq0lmJqt*jl`z zf#T;sqAy!Nw?&0$N&H+>#Lx7hd^yYdP%3uA%J5*{IUFBK^hqC0^s_!o9Qx4q=1`J_ z#D_P1ojyDU9D#@(;=}ES;ln+L;lm94V|~~YlVXeF!`xx`u*Uf?hoyRJei#}?AB0z} z4=WS>BSfD9&EA>$dF(5|j72ct0jB!Qe3~Bub0C8GcVKczZ{aH7NIbu=CxUq^Fg5SU zr#T0hp$O&@U@B*k#*c&*@C`)e9qdhq6A3v~E!3NsMQ0*NkZ|C!WqDF8$SgVwG*ARI zTktn}zfveAqHep75%s^3ysi;+?1IUQ~BmB1`eq+QQ79@H{i$t%`nGqi?Z8Plw2*Ok&?_j$hGLayD zK0oiO1>dxG*XLWR&$bpPW)giC^#3--M04@afg=84h8%FcyCXY*A6(=OGR6U&@SoK= zxp!}F>Fbf`JY?(wjj6Q>we}z$r4)ZEh9M{~lFFT9`yk$()Ya0O1+}bUg(4NSbg%F1 z05p8O@(Fr+@iYlA%?^V?@Hz0Qj9|VF%-#q_UdvQjMOjko2f#Q#3nF*{n7f^H!5jkS zo(SeOU}TbD>=Kfo3=5_jC(HT}kvq@IvbLTmG!e|(foXOa#$gy6@CfnjcR7>4IuD|Fq?Cupsl#C}(9`LpvieW1R*n! zUn6JQ(era?Y~M7=QRl*eHb=cTk&pC2+0V4S;G9Gn$x*{-ZJVPGK~U5*_S1g>ot??p z{Z+lqV!A8iXUIg9*yW32{74oQ2N(N&WwH1X&Soa_4BPZ6;U?(FA#M6R*5>2Q2CG45 z+p7}weZ{3MK8B&sw#CMX3>L)C)kXa5`6r+^#^??AY_qdHsOpq-JoCaP^m!Q)@f@|q z%zF{?BAB^5;nE0Z{>hjFC`L2?t!$k)B)!p-F2D1Q$eO#ulYWdReRx9B)1LI_Jn7p! z>7}0ZJ0>K3r6>I7DeZMDNvS_3&=D+Akzh^?ymw3`2@uatT z(tqYj-!mcUHJCbx7ADEEzg`V{LJ?V{}^d~*(dnY7)fhT>pCtbe85^eWK zJn8!;Bz>+Y{ccaX+)<56mtSy3WB$N|q*r^=@ARZE^rU~?lm6_4q|f%G%Uho!md>5) zNx#RFJ~kogvpnfLJ?XPO>34b3e>EZLGd<}$Jn6D#jCf=IE>HTQ2}!T?q;K=2PxqvM z*pvRsgrraRqz`z~r+U)2d(wmXb_RiwT31qsGrmvrq<4AJkMX2m>q#%0ko2jZ^fpiW zBu{#uC%s}q(knda>pbbNVvZDzy7zn1r%g!uF`o2BPx{NA^kz?b<%Fb{dD2&U(&eew zsO?Rj^jQ;|_yMDtv%j$(_i8vl)EV_$ zPrBUgih6#bC%tAu(qHkU&-SG6_oSciNnbW0=`VZIXL`~f@ubi4q^Bn&{g5Ypx+nc1 zPx^FEdeelYzvxMy>Pf%flRnjx-aH}czw)FX<4ND`Nk7JuzF|Vr4|>ukdD3O~DH`*o zp7h*=q>p*hU&WF=B5UrQp7d8hpftLM-7+ER&w0{c_N4Ffq#yF64^2q=v!3)9J?T3= z=?6XOw@ygSuUrZ)G^-R4P`=dqMV+kJRKw(s|(Kjldu z@T5QLNxx%4()W4N_j}U2Jn0X4(nlvG{Si;Pyn$D}s-AE2q<`I$e$RxY@AafV_X-$BRl|=}EuYlm5VjY`@==ezzxmi6>p2 zp;ryH$L*bv^gW*RJ3Z+OJ?U+p^nDYOzT1<&%acCWlfK%Meqch<@A0JX^rX-Bq_23B zq~GmHmp3_Tn`(cb=}DK5ohXgA`?C|Webke_&67UelRn#%J~kogcY4wXJn2(C=`-FW z>34Y2yFBT~c+#hY()CTeuVFqGJ}dG~xhWAjs)0FV{8O2Dhee-Z48l7IQoS*+7MAfi z`h_zdcamoqpeT;N$-|VoXM3zH+;=EB6*RW4A;%wYe*6>c> z`*0DB7dvFNn#O;TQ0Pvd+&Oy9-8qu?ru%&4&QWubJ4Yf`?$8b4_LIFsw+t8{@($ji zI~oqO@zdV2F`GvKa6?Z^x1ho}Y#-P#*t0PR@?uppK!u47u`9|$N^EzzPbd+QNTbgq z4WVBYdn@z9P2s?%SWyuDQG59BWrX zJX_o6y^LlYhvvd{+$SmVW7)IIZyk46(X|D=df^T)YpwILmb|shXvkXg<-G=q(P){* zXn8}@MV|=gd5xa*mp$pf@}yTzNcuKU`btmwi=OoTp7dE0lD@^0zQmJ$(3Af6p7iPo zNgwc}FZ858=SlyPCw;+$q|4Y8ZTGpJbh)1&p_%^~PkPOSq<4AJXM583d(wA!(w9w0 z`UX$>Oi%hFp7fk2Jv|}mZJzY$o^-yI%{^%_f3+vQX+qMQJ?T?D>GylKFY=@}Pe}SY zPx>*Q^xdBH*`D+b6O!KKNuT6NzuS|3f+syUA?b~t^jA4HF{{tL)06%OjHl5&zhy$w z)1Gvh#YKAe++CjZ=RN5|6Oz8tlm4P7eWxe=Nl*H%6Oz8nlYY>XzQdD#zbAcoLeiIb z(x3CBZ}X&o#*==>grwJa(x39A4|vjtJ?WzplD^QBzTcDHNxx@8(ieErAMvEO zdD6Q)>3b$5eXb|{Ay4``Px@+4`U4Y^UhPT0-;>_xNw4vw@12nJ*`D;>p7fQTbot&y zG}rB$kn~xe^t(OjOFZfF{fnsd0~3-y)02LuCw-wO{nbfMx~`<2hCbu1B11l0Mdr!U zb-@^|_%o~`VV3n_kyT`pmdHf$@0a}5G!av;SkXH>v!QJYj>GL;slywOUh8y2%pOwk$^vk{mrYK6sI3(P@{I*Yjln3o+U*VoxI(2ie!m}jvnRr<$4!}X4> z^(A0xG)t5Q{R4e?Yfo>VeO8vW9t91bODPR9c-O;5XlL&Nljfg5BL{+9Wyw1)EAb8i zX%j2U27bPOjzw4C+tk51v!yH35(EoSBlPMSpy3?A@~H-fvq6hl1`OZNW-%FH_G+7g zbE|zTyS(CRzSp5Vr6)rYVJ@`B@vhN$pdH|TQ2%jf_c_?D(^T0%{ z_zf^mMQHvA%-#r}6J@Ivht;_|+ufSmik#r$c~iD;eQ$p@7zP2BX|NQp5ZZ+AWCZqk zV|xBH@YxZu>z%+1xmqG)DKPwYRcVkLv|pUD&+d}XYN-{`a2qhq5N)LkpWA_X2<{Ah z_!VF(Bk}VDFx3vz-O`2r1RpxPgwJ!J;oJ``D6dSqtT7mNZHk|0nIA!oMXWf4TC*bU z^(rt2BeoxfIIWJ*ycHNefny`#Oi61vLc1;irYq83mje^_FQL8$m~@2mt-=TY!+0J= ziSuwP>pozHBU$1xUxZDJiPZW9Fx*SAoaI+W(<1tu01V&qWNA(Z zrV0GQc)kFbS8*|H!OMY}i}r@ej8is55R<0WHNXMb0&j&`JSJG$PF>b^8>wI$fA*` zdpl^jI<}nO4Gibu7E=!le?4R|y};b<+Dl|y3rx;gA(#&VgBHt+ggbz#!G8o5dafMz zpfoqa=YC+CA}#nRFwuy54j6fYLU>p{FAK);Y1RHUE8;`(aV2V?IkeUkV5YlTKnJG? zO+@=#Rb;V&Gm^tHfnK3^Ja?!!wHQDZ?wdKNUhBC`6VR-}Jj4@@|hz}wHv za6ZlPF`pUg=?!i*7+P^BYH?T1>hn!t_B&Y(UD>QyupnaB_ds(1|HHO;8YSryVZV3* zm}y`sTrKC9fZ66a10B2$%>5C}vB-1Hk$KCh!0d=vdLA%x*dB-e-r3WJEE;Lk<)9gj z=zIk*FS_1@nM0?{$Ev|6)VWEFVG8IyGv<4 zYTe^(7tCeA$PwC}0Y>hLhq2lX4EF)dOs}W4I~NSkv-hB_KDU78&PeNg5}1V%%-4Y7 zK9a5VC@|4h{%2r@(GNp!{3kH7!vM!>{LDNVtsIG#Il$DwkG2+UH$$WS{f>A;-Xt&Y zSxQG@z81B(vt;#Y0!EH-+}Q}sq=*$C0_LfR^uGpXX9V+ES~{L4P;3C~Fol2O@mt1G77#;SylBT$u0GtASY= zq3Hw$h&<`n1M^~p=A*#ujQHnofvI+Op?Yv1FyYKoFy95{kw~p4fm!J=W51KfI%gt$+Sx!fLC4K5DrIRt#eOAXL)y>I9Pma{d_JkOCr+W3(Q`pv+$_{W>19A zdSDtOp3e!!@oC3&xfL}lTrJb?K-B;n+I|yiZ2-oOxybYQ2R|brgc^PfG^3HMb(hqN zX!uQF);Z~57(5QlixJF^fSDTc&mmxP5m~PSvnx{TSp3?XZ_KtHI}?~u7aM$Uyd>2y zuPy}5kh8sAhx|kHm;o{ao!!~_bAx4uhHY^%YCRY6YNN=C#C$6-a)hyQorl>8%p(y# zp8#fN1oH)8_D3we4;a4h!dki)m^~5CKMjoRON5pl0%kbU7Qv~gu5ox^O#t8CTPYYt+N6c(JZvR9T+)6%=N&`j##=An7f^&8LS*IMGA%^`g|HR z(_9N?^g}g65$S&in&%uJk@^@gcSdAA1x!~2GX_lBwIJr$UD+PwC>IIB=ifmyaIF!rd# z+nzBNT}pWjB*mw{<^mI}>-z=WBtwM$m-@K1!# z_d&zwZAybpI`JKHwqt~qN`d{2A#|2Pa1gclG*oHuTa>EWvg-#sGA(^AJssJ87CU>| zdkMF!U*DJA#8OvhPnK|dpFF3f9N>O}vQSs7vc-4T%zJJ-dp5Onb+)A;t{dA(eaq~d z31M+!2?7}q2$I=HAEXJqVIyd2swf4H*B8@AXi4lPqi^B~q{h8L* zfnG#eOoL1t+FLg7#Da`0WY@P~=hY*#q14;emfg~tb8pe~>5Ly+TD#l2dJ0@Ll4KLq zlVP^Ildvrbw6YZQX*)3;TGQEcSy*+$Ys3%5Wh@u~p zSX^7H&~kxnN+^;8!u}o08__J1pDRpyunl+ZwJ_Vtuo)ziS+Tf2vvPSuBYIONgHJ?e z`tY6dek6ztDFoS;jiF=C!$e7T`^>GJDh)CH=yX^#&*!?Le2Ca?Emq|avQ^cAU~+xE z9eC4vKYDmy(ACmE;4t!S;qxs@rYlmsz*N!wNq*QkW2QHmR@@K4{|nB~479B8${Nb9 z-j+7AD-mxLZqy2oegt~fQuS}>-Hh)_wYPU}$sk=ql`KHD5@Sr~#%$MCni-a@ovy6G zZ@%Ul7p$p6XC>Gd>&yRlP75P5Y>-o@6U_)KeWcdjejo$VQbYJFMx;8v!i zzrCfiYp^dHT+)zP+}k5JcI&gPy?t$hSjrBOfJ*mb%Lp%D7c(`Hh}n6?#LTFB&B%FO zh)S(tz1-K*iGhJ#tbbrtf41*3eCS~*HfT8#Vu?NoG>H(~tyryOa#ooD>%VB3cADEx z;9}zoyZya=TN%3ej$i{`If#A_V{+Nf3l_}J^bPh%prSfPWqi)JFW8JkDi&2;biuqi z7x_(Dzv}YF<(DnZq#Ks5TJpY3{nC~1TWmY$(#x0l!(Ap*xPtU%>yn10%Vd_>+vhS8 zub8Br<<9{`IeZW!3+13)knKiiG;b#m$bMWPlbqp{A6`K#HfJ_wx7z5XbMmgY_6NM2 z=|Y-;mYL1-=UP>TK}%bkV?YxG-)cSQ(f6SlFshL$t7IBiHn`y^{}u4(id5XI&a9T% z5JtD4ekPyAotB#)e;dskU&exM=I;G8dy$FUbxl-Nn6qwQX&Z%n~jx?nQLO zI4#|hg<@ckUh1?8GRylf@9mM8lQg!xXYpWPAG)6*aD1~pgWWO-k?z>lxxTNZZ!3oK zZpp^|lPa$YV24y8PJQZO;Z& z{=9h?%meW_T~`|B5=4@ntS!fypca(`Ywx&Zq?yrg@OLAcAlrp;t_6nKNR)1CCwgX7 z&n(FsA|jJjEttiUh3f~pR(E0o+0wPDXR~Z`H)ID^_1GNI=5qPPon2^o)kyjorX{dR zW`d@PO|G)5h)nXFGLs2IoC^-sMh8QfzY^m=GB+}(_+l$&CEbn4sI~o&pA|^sLJ}F) zDB-dKV-qG0{U-CON~)~6^`sIg*G7gik%7pra}23je7Cg1TI7vRWFbkc{TN^~z3pOa z>qZ$9yD|Hf3!S~|Gwp*t;tbQZbSfLKA)k`zL)J1$y5;>y&HaPx`;C1WOhx)-`Y6{h zi5ZXw4(LRTLCC<^ zXO}}Xw!6Or^It3^sd=aFr78hNA?$U;SRiO|0}2!RFnZK`=*|YO;~1h*=HHpF+~V%G zm1Zrh3spDXhpZ20VDy$FR!xMO=Gev!vRA%bmWT-};xO8H87WI9!6AcmUvDeYKR7gY z^#hHOWl%;6@f|X$+}~_Oenz()$SSQ~HJkLA41OWyT(3^dEY9@jvaOx%ovmT!E0#`d zN0=jS{Yq-iYaEp!(Gl>T3eM1h}KAh z-2)ghv?sf@J3~kuh1G%WU68dh+p;Mk_H7r=Ni4yG2`-{~VPEGC0|#!jp83R+wg8%| zv9oof9j95_(fTV{X1l_XXB#3k%-&}(ERg|v`y*Xn{0bEklOCEb+voNFVjB&%Ap~mjghpYkL6ew*k>b(br+My z!4KAA_Qu}QXx5OH2YRku3OEJyW33v)xz-#5(G0|FXVX=zE0vKx43w0Ou@=XjMC3a& zal^zME7yb}Uy{vby={YCS-YPnvjj;RRwfk;eHY!yi^O%7L+(*Tb}IuV6BjzfhKTDv*}JLn?>U`p7sMTFcd}RH-$q; z%Z&g_s{1L-bsTql8n7FJq1Q#ZNw(Ch;L=bYnU19g(Pue4V|OaNL>6t0j{I(5OhNpa z31=}DB0{Gk-DZN7kY2fSuV%w|oryS`bSPsKNoI+TM*7gE^;^NzWiJ<-NK>NisCk2+ z*ui^NUhw5l>(Tq7^LDbd!ZYDa6bqoZ0H#inW}m+)Fw7ctBv(f^P~3dj%pvk8w>Coz zvR;TyIgmGG#lrk-QwB;w z@y-&PA{(Db=%71wM;9b{Yl+BSy>(;WVxd63;QSV0pEpLEI5onoRp`9tIT_dDoR!x_g2L)G9_L}bk(*k;zP{l|9g+0R> zBF!2dGL=}e8rCwlq))!tf_=WmwS_!|FE=1KJv0x2xni+7Td`$c(o}5RiKjpAK!429 lbTw?%4;zLH5~r;FK>-I_v#(=jdv037DTCXGi1q2<{{R@CPJ;jd literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util-static.exe b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util-static.exe new file mode 100644 index 0000000000000000000000000000000000000000..fe7f875326eecc3b6e8809605871001701da5abb GIT binary patch literal 799602 zcmeFaeS8!}*7!SY2$T`aI9?-p~Ex z{&D$yNOx78I(5#eQ>RXys_Lnly3&>Ha=CK&pGde|4Ls#vh5GwH|EZ<8_keZ1UC;M; zV_<_j@W#N2bFP_RH1EdiufFlh-xSqcdEIr_2aB$nRdi$Mx}s~YEAm}5q3Ac)&zvT-z7-Qhd2wMJn5=s{p#BlW3h>m#Zw>_0-WM=4HEV zK|U|bRjb-f0sPO;q8Zt)lAi&o9)grp#QseA;NYxr+9={S0CV}CS{q# zS>Y zaq#GiCrX_;@~0X&0lBLyTt(yH;9S+Nf};-<+^Vi{BA59$)_}t4Ti`^-qGK8Vq}{WI zI2q4$=UEG!$oo%S;qphFRqj=QXSwOzmC`QHM}7wGoN@(s?-U*nfpjX*$2xa#g$sN` zhAOx%zm*4#-YQQaqT`=}8~RI?@yumBYJr=^^VY6#6{F7jWtoC|XaJ90z!mY_(G`w% zhdK29y-{fI;c_+eZ2uWJ@7a{2dct@ z)&|rmGL7)w62tPmIzG!)zO}_A27}~AlIg^z%)}j;i7PJ3a?M^ktZHg-A(gJA$SnBF zgIO-i6=@7kUMreqUv`h%WwbOU_-8*I67${lO|s>!C1QYUTL~y3@zOV-NU>r@0%%+-Z^h{53r< zGGY6yQ{QH8@JHtsyQ^xxsBHQ?J7C7_>bu-7f8;a6e3edl5&&)aWhiU;`-au)V|(45 z!sR@-VeYq21Cp-)5Wf0;Txrs3lM!C;w!4w9dp}sRr84|Q?u9MBGij1;G|!w4HoNRM zN-RABB9DSmWLbFu{xVz)Ge2N?&QghjG6Bv;ldQY~UQN$2{6#tH-T|3a@Z)`?wuX+f zAEGtObAY6=bc1NuWtU$uU7w~;U*91gZH=#ZM$ChvJMu$4Vq>#h|B^xIs6gZ+`faUD zH}(~RP^nGCCKDom1lF+f{>{VgL22ZRmTsaGTI5Xt=s(8T?b)$r5=s2#TZw`Tin3j? zb0u#jICeTXnt8NzQ-l8%L>aq4LRvJ;cMbDRK|Qg!gz=3ow*Uv)|lOX}<0=>xv(emP43V4GwvH;yd5LAs%Qt3B>4z-pX2{_;&??T5vOlyB9|CPux_-0yRLZ(j;7zxM}i zMI)60h-(;Vx(nu-ZFVm(__Q@|XsajpGpvh-`Ayp}gT+O9^cuH4;0%m!qi(j`{1g`F z%99Y@cIs|zaXMCYsoo$SyuBfcN>G>*;s>O`5A^*&SDJ11!-GNgesF@=r^lq!@@N;z zq>QZ?Y&krj%{_+yNr@md%!k0k8;q3E&@b1oSijO=o{0Yytk;6oe9!I=qIfgui%Hwv zCG{XZwz_{(duJs{)f?b5se{J>B}$MYwVbrm-@oK-W#{qRrN5?>C+J?<8zG3zjk>wr zzVi;T*w^Lz&bY3S5Hhy2WC%X8^HBN{BOz&=?Nmj3AT z{;1vY7TNwtq5(o(e)Gpl&A&lgJ%L^sI}8PQRZZpo=nZb$D3xx}>a!SgRW z-%ifwhWWK&?zA6OAPY~|R{M&L5uV_j5j}%5tw6CavMKmMqTs*@GS(F2Eei7Hcad7{ ziAkybbz^Ge7Nw>3snuC(-;-W@A;q>E{uvC8zgK%}aRt^lA6|S>-$>EeAz(9VwpZ0O z+7AqJxxBX)kAR;o+6n>$i8O}{_7;2<5HdfPI1JK+)C9-AR~;pq4gwVC-3!FiK?adY zfZ%zYDh!E81Lo)PV-(k6yW0r&f?q2qB=Js?+h`K=k2IsL4is0|@zb3*!>6sDTU=3T zZnWDGiMD!Tu|dPHtA-l`GA8`Y!B72;DaeuIA8>6tTDs{Tpvz&^UJ6M3l9YdCei1Nt z#m-?8q5OKV*;i8Tw0(W5ZEf|m;tB@3y(pvU@lMmuaHLPmsi%g-luko}j%ztS*>PJp zq&iN*8;;36oobotK1#@2L#;biExiFEl$}=K5UJB{yp@+iUd+SxT9euEUSYuMKRsDT zrem?~sXA}aaBK%NrkX#(huxLt=78C>_*`9EoyDm3>b1Xh4-DRbO^^4hs%gC_dSXwC zvMD-gbnUG@DZ5N}H|o&}x3_u8M-6C3LT0SX*3+ncT#~(y)9lHN=CC&w>N44@A)QgZ z%G^eq;r1Rc_MnP3Zim@6CfY08SK8?FLg9N_U`L>4z5PW!tnP4HWK?$eC!NOs(!Dzv za<#ubn!$5NG4mCMZM#-?jz`9GU2!8Vpu=-{08m%_kUYtk5iRM*<(af}qF-|ZB%DkK zo8e4$8!K{M_UJik3`E||kxHKDM~kC#hr*>azrG)>YOBY4ylq56 zH_~HbB@R=jt#+sz(Os(x5hNIqt1Ww+X9{EO%{eZuu3DOcff>*#j6i|Q6(103TzGnz z6rQi1W8GRj#~?K$-`lP&Kgl8P0*JF*!+{BH4OlaaX9TjZ%-8B%lU`}M~&3_`}RH3L}Wb48lZ*#~( zes2o|7Gq%^wI}x!q1}Lv>B`X*F-UJ3(N)FI(5QW^&k_D_$kbN*bL+4)-$_&SW*Y!v ziw*HS3}fx2abw3_G^?RZK}3<;%dmW5E-a=@tg;x zhLvkzsrwk#L`>Aa2#zgS8|l%thR}COiQr$Di_3?>N~(>~Qc*#nT2}t2-6%a2ZZeu; z*=h~vbbpG^O0%12L@U60{g_;P!7wG%$vv^l7xY3v7v)x(W6JD{2wKh7%`psBB%Z1* zIr);)Q{MW>TQ7O*E4nSZuC1={fcID=m&LOm&upHB_E*H1QdqRrjZ&$%{e;R46dTE$ zUUobD;@Cn$kydxPQZcdApQN)(w7Lt(MruKiUOVnMw|-zu&#d4HBIWAmSpo6b$p3s< zT~tdm-KA@~ry_@WxJ+vL_+vz0a+E#^ zk*+Epv3V=)|2|pe2jS;){&etT51;LFVK3&or3a42e9XmgM7}!=-lZGFoOYVb5X}P7 zwkznAk^7Fp?lb!r3?MKqzPE1f*UcSvJ?v)sn)67f`|0BE!7P!Ay)+TOFO~0Dxa%15 z0qe^As>o+r-IXfwl(LxRUtpiMGE@63Ur8=Y^Tm_O6Bw+c4NK2gYSU8UomP^&_*XDp zm7PuSAd^ZIe^yLrc%$39Z!xhbJ>LkwnqO&d zsC4fQEsJc`>b9s^wu><`&zBAfO-)T5sh-l;x&|_C8?fW9b+!D#WDk>&3(qo{?RXaP zP!_1f9<{<5eA3D0di!o2tnX{)Cx=95`q%YI&aro=S8cxn(3xZZv$XRZn;arW}vrCXm}#CTrJ{=hTun@W?~el9yDi*c2f!ns!e%lY8!!(WFb{8zUQOG+VUg z_fjIxCMElg=+I05K=9%b!r*B7Oxnj0ZKOoU+w4u#;eKmNO->wJ!z;#Gi%fm#}FdL6@{cyndxxkCzZdsyR=L;7JBc&hv=n z^-Qmi*4rh*xHY!SUO|`eQe+?NSc5VYbclry(Md@LyG}#kx?c=loDCWci6XN z^fbJ826lyZuPI`EsI9)a(6B1Y>@UUet{L0+!06-Lh<_#F5^eSTe)Q61$Fl04(3?MF z`|xLUz7g#ol4y!Kvv>+7xd=_3N7`WZSWORZ6GN+9305L3ji(it`Amdwp8$0tgBgw; z?HYei#&bLqy&{f65y#QOlusON>#_Su(F*suFrhU?|uE&GqI|b zHL+lC!|GFsm0Pz+mc6GL?z8;nCwl2lpV?dCQ87N;_Mzpy8B~Ns3JQe}%(uW{zBf@( z@>A>YXGuFN$u+!n8Bch)Zp4KbsAo0p&TZP2?{hc1n@MIj?J9J)b>+8Hbfv7;dmf`t zt7FOIS|>Y8_EWb)i>T>(t&Y(PUFk@ZJw?h?&?d5gBGdDi+ljHR&i9qbGKY zU8m;1{s)h8%yB`15P;?o%(CwSU8WiSEonz>gnsm`Not9{9iOhX!=5I!-i^1W;uFd~ zFpyfcHCq{?!x%$l0sO@hT;EMHfz}hw!h!9lH{hGN*8Q136c^dq^~!v2T-Y5gCnzNg z(~A_H?8BVYI9hhCN{~Pq6lCE_F`J?EWfBR4A zd8Mbw4SE(Q9VY0Rkfdiq7kY-L>CrRk=`?eaN=dO z5}Z+ffMAr7qeY$&P;)nf&W;|dq_$qGpDNTH2<9hYZcwyk1+QSm<T z9BOCFP>kk%wp#ed9LCOuHU*_REjEU733%uI76{Dx!H))hBzkWF8-F%M{h2B1Ph8VM zeXF1w2|6bVb`8NCd1C>XjDjtomr?<^W2mT`J1b3WHZeH+3@WFvzu7%0n`1Mu|5~tr ztPIJ}e+Yn>gulPwG%xc{B>;(cV=pTZN65=ki2N{<67oPnbdQ4SKPv_BLmE-L?Gk_x z02%&3(*HA9Lio%^U6zinfaY%&^P;V3lf8i+ERb*nU)Abmw@IRwY=4Zb>4x$atQ59~ z)gJZ)&#gV&Ggw}GxO*^=j9tEkWfJwjOZqTSJcIzjTZ!$d3ZXaEdQ~c%fC`nlLMIc- zSEdTLu48_P=KWc^^aDm`Tq3KhCAEc=bU~T@0f9q#8z!AmCLzf^oXk;;0K5$DQ$0ba z*bh)o1>55Pg{oG-f@o!4KX5u;bP=>FeX;)nXr{`(NZL`^Cf=x>rE2R961mI_Ek64K zls2a9Wv6%?es)0iP2OMw1TLpgx0K%Bm?cLBM zyU_2UhH6vPiI3EX4LAYLWRK@%bVXoR17j6T5$s!o#a6*o-jrhyv+o0qBTF)5$sMy> z84$X8Fm^P=TMKi*cir<$FfHygMh>JRJ#+4SMw%?%t)Ut@Xv^E#$)SG=pfX~0T!iZZ z%ha*Sq#Yfb&KtEJNY={R^ju0q`@^fFp>AMA(R`WbSGwriLhGgCUDOyA4Q3@OS=d>5 zw=IIiZL)LMMnQnU@D85l*Y=e-j7qR_Yz@KYXmyYA274z$b4tV5(DIjmX4fGxv`qAC z7%OW*#cP?_Ub=%P6M<*6>R@;`^OMX9R$f2w7}lBl&J^v`B4?5r9dwdak?Z|XTXsOIx=mlEEz-MaDnTC{*=D z4tvJ_Oo6jMOv$B`;AT#==WyVN`F~>kpLFLjFef3w(6QDkB?jpvAY~XW0Eappw6Mdw zVDt0f4lD0ZY*7lkF+W1V>3!XmoZ+@Tn;Hi@?5k-gbA@#gX=fZv;!Tc^^j{_QWGDO# z+H}Sb5eM5IBvrS?#k;*B1!AO8@3VV3<$p=rW9Re`Tll&)C0{>dN+JLI;w{3CONnHo zZocg^H~Y*tW%8YSJz}aE*H`*YlrfM!E*I6q3f!fp#ZYf5enW%yc|a-`OLp^FT{tVf zPUCUuUg;G=arwk^av58dHPw9?m8EU^85M<<+10rtivd7ha}9c6p|<=X73F`vxR%Z| zSj){77jmJVTJXFqoSOS_7G;IIZy)h?aoxUoOuMU5`+ak1v-WZ`Q#Wp}7P(pN4g9G% z0zmEeZY?6GH6^V6JB2%M4YlOyx@8A zR)LZP5W`(c?j!#!(ij2)+@9iUeQh6VK%Vkw_uFHINLiplWF!oFA>lzlwAHJMAK(e1 z+rgl%eyR8&k}RfQDi#CZv@6%$*7TozpLy8bE}4I(wCO*E?slm5v1Q%#8_|rsYlV-) z_H(2J^?gaye{@h!qf}v%=KdrYcIUg>Byqn=6uO)3g;XW_JEl>f&yQ0NP!`i9a3pQ z)2D^*_4adfl{C(j=HIg)B}LRf)XN;Xcmdl8|AIIddkJ&3JMQK!#jRtzFw>%(0mxm5 z%A1EVBS^T&evrAad{dfZ@(lZyFEKB?h~F+7aH1;6=@} zs2p@cOXfxnghYcHpFz<3uVr3)i2?o44_Ru==Pe-H@y}!**O~pY;V5(NJb|`dr#t2K10rTYLVIYU{XkTfgs8>uJ)CeR_d6Y9IJsDAgOf zZZjYGJAS};W%>GVRWLBArCTUWw=h(-5N9iJ=o11bYXCQJLN|TB-u4N=yRn7f>J;B} z&Lb67ML10JnhJjfa|7lk`;jli+!87TThgsEL*iDAqf>lV-W(F@faH_VVC79BiGO~& zRWMoJn2axU)VG)P$Q8eq`5#1tq9p)xJ7X9eLy|b^)=)Bg>EaSLKkH;@5dIJwxzk?G zjsp9AR$d;UcA1buu7RUrdG-Wps8PJFy}U8GOVOEN&hWM*Yw9=P*q02|t;ZXFLBN@a zW+M1Shm$JuNLr|uq=mZcn$DfwPTJ|VBfL5DU6Sm`U#OKP`vOIFOk$3D16DH0_DV)8 z{dXr#*#R&x;$Pq){eQ^me{s$-*8+W>p#Ou({!hZl`SDDc8$lPVc3}RIgemI+vsz#V zIWWIdFwn6x&2lN=&ZziePG^=q&?ky1r`0nXeM1nw&#a$}KTE7+%UaP#`w4Latz+1o z%_m8RvGX&5wTZ04dlOR)Y4OuL))R*LmSK&T&ArgKhNG*ZGjI0V&k!@n{ z(F;7o$LHL{c3>q{H-)||Z%m$lGtAcYvoqGG$$0RkfW05`#0L@xwF_a=un0jrLGQit z40HA(mbjV%^R@Vw9rSgXeO&8LTo1jTRb`4F;l575_Ea zFo>T@wo)Oj)Fu;C9DD>W1Sv%YcY!oOpq_~0OgRU*GeGpd$gZG)aC_F`uu-#0u@ipP z?JqxIxVMGd@r-eH;hm|Si0eWO+*-mmGMle{UXg&`f%h@2S*sIgIXdR$5vOXme<(CW z3(liK*)6Kcxy^7lCw9+X>90GWMP89owptge-BT|(9lQ7PMmqp4nR};0NMjI_O$~5S zKQt~;5ITVLq6PDkRmC&xBQ*=Ase)AK{=h8M{*dGBI`K^Xw2X7!adi0aRN?tAx{lG>Rx&0ML|KW(a2T*L#e=xAL}my?B)I|Q=irfellF8I1x2=J zCeD?^vi7ti0=F|*YKITfA_wrbW#b?=5`Tg10((&nl!e>fAk$RP;n zhdHVro`6PY+K*M4yX zd-yyE32!h`_L2IsEjbSijUY-P@gc@C!6cy>C2VH}=pZ?8eG&;fZ~y1@8RyQ1g1tIj zU(FX&2zomcqpSfcm^wCQ_1-utx97%DJ!U{_%3z+-B8pDMH%uE3doU#ZjqcJ%aHh{>yp9}dx^XpZUv!mdr=0G zRL|k^ID%4)+VvpdL`Gln%`Xy?GVTvJ(Z@X<@lEa_^SDHy*_)t&ncIUK$ zrwENVHyJg3>kW5XVwV$NiF$5EIhl?fd&j80p-cMOF6o*s>8rY=r*%nR)+ODwd`g${ zE4rjF&rIV8bnI`+%^G7mdu;-l!k-r3WSOJom# z2a*6?*A>?Zz=L8@Qs*~bl+}vb|K{NJ7Oof-oV-sQiY6m^0S6j>G_+AR_nM3z?J6*Y zv9^t9&MWxy(VSZ2;CC3);|y)g4r6%#L$|nH!379=#x;T=?`HMrzng51?0a_}w>7-G zf4I4*zHcrEJJ?D-bX+KjjH%%afsW?&l35VfqG+S1oE)-frfFA}G-ZBWiBr_)av;Lr zAIHIpuv|DG>QB!b-n<^bhic>OIOlyP6A;_aNr2c#)A1kZ^$!2e@ekRh_>>|Rp}}qd z%Q0NK@)-i8Y+U*>gN z(cKis$ZXQjIkCRd+Z2lFW;>y^?X>A_2_2=vJ~+LwkSI9&OLQdH{*+)MJ@~;FBEwfj zM+ycCH)==Bwu4kvna3nE)mgE2ds;F-<+1okJ34bAZ!1@3+{NI+$yWVEe2K)%^5+%# zGuymj5c)scym@eoPH>y0z4>;FE{?rxw$B`2;xk|6dFkmb`iYW<3#SPIR%Nc;q$ti_ zD`uaK6p7EM6`M7*A55?$mHRp~d0pqK#c-1NJ&Cn07t5hpQddF%E3vbNIXV|`Yb>WS zn`BFgJvucYt_EtPB+b$JTBHg8b)BRHa%r=AtJ!MrzD%JKBwF3)z<{b|Y`($(J|lZ< zu7lGq1f4Y@-`(usoRH5BsO9-}p}IP#7PrjLuJB<^TYiKW{Uya2jTtq~bn+)SqwHq6 z_eDp2ABYCrZe^Rz=Ch9$wPtHqTfJ33Cue2AyD1c_UEI@$u>Q(0*CLEQSMA~+W3-3_ ztZEnMPSPT)c+*yo)3nu>V5mmk2Ox2qrcVmpOkS7dF>$$>xW@HzZ}v8u6N zbSHRYaz12CH+LJyF`w$k6;g9_iOmY=|s zWR1=DzNxMF0;z+7BORCIs9+E%xJxl6n~bbf#vn2{mvXF1`y-zLGgzw&N{3m!T zRZkB(QmvNi|Bm40iiyad0+&C_o{6b2GbtcLxUolfC|)nW!{o6do8`lRf^S? zR4hiGL6CC4{V*lNMUQGgA_vn(?)@v8xQ%R-LVA5gKAyfF{sAicP@6X*_Tza&YQl2( zPgf;!_2EXmveAP=~oqOREUK zI;(Auwwf-k&TiV>y~k!cPUhoG(ZmK^>UPyG6b*U|%34MjQPb5jx^FHIZA~=?hI*P4 zPFyF+>>w(|M(+w=u)<&$jsLM8RB#n*KtKHS}0ghS{Qsx-3mpyDjjBb%M(830)~-?;$^SE!~zV zIK@Hq_9d$IH~u4txEBa_ebR{b*|Su`NbmVF<6ltA7}3-+uu==~1p!}N5bV2aap57qS0 zEY-9llMB*Kx7&YI#lx-3@|9S|rnx*M`zg0l8XFHfx}x#l$(9poB8R72K1H?Maq4b3 zX(zs`s|NbtmaJVcD%k>-!S1hW#lFUgqk$_@AV-q)3CQ6|ihH?l3&@Bhh%+X(sIrbm zHzw10--E#EmJVfE>L6OC5Doq2^DI~F0kxj&{~z9!NUusW)=}+3r`knS69aeDwM^?B z{!GfBQ%-CTb360(I(Hc3)v%g@Xum*Z$ELnYGV;Yb(FrZ`E@BJRjK)%r%{TY^OPd1O zqjP;{j4iZ#v5zPlIrjs>+0DWF+Frbw&76!WnZ%#cG5k5*$DcFu>p8|byD65-b0DyT zc%Gb0pF;X{(#6U2siaHPX<^1D`KKlGe}Q5C0~?Me6YS_-`dVzNt7%WJxt{}3gX$+1 zpJ_I8+LxEX@>0mlS!T0+wba;e7s8wz4RxGB$N#cM7qQF_E+ihMMUI16;(lk0E|e2k zYTZ^u11^27*uAua4>Lu_^Jn1s{23&NfX+-r>yI!^coImB^kB(6E1?-p=KiMk9uRjj z^F5DK?DxM@M(rP{sCb&HxxUV(4eeTEPo!p%n?D0_ty-I6ec=8S+#C)BBRZd;QpAyc zs@X)cxG9$3WEYB%lo)^0YDhnOv6zUVPkh>8Yrc9YHKg0^Q4^%t zu{C4T<86n1I{BHluMcU*_7(Eh)&F(ky_U|F=WF41JgldYT)3UvPg{AB`B%0BnebV_ z&X+K7G;cqR*)t)I1HgkxpMp}`6P@%R(!Y?j&q<$7`V2`Aank5W-e5@=leQ+vebX{Y z7N}%#vecOkVlFbB*NpQ&*3ke7zxF5NF&*m2r^@^FU&wodJSG)Do{;3r0&+ew?O0!1 zHxRcL9Dfvm`vDN2i1aSfGG*g?U81J!W_yWLmrX1uRwIA;Vn%iU;LYWYyiD#JoX4Z_ z*pN1R>EUa;>zuVi`7~b>xlf-II%jtHaCYcSE;H-lO*-Kf%>-3BP)UGi`SIq;yj+s`Rj z&#k=}J>i8#E{;=$SqMUv+A0V)w1d?Z+~b7BxZuFPc@iSlG6Uo2d|!m?0dl_T1Km&7tdj;%3=lTx!|aj&=9TT z%Ci=)6_8HC+wHjUN_dA-kTLTL)|M%K=_J2E^hyZaBHNOm*v&}Cu*P5l#^oDc;u2HZ zg1;DkOGT(p{Jf6&PxmgYkdGvc9u|mJv;h||*N66$zb_ct1Vd-JtrU6AAwP_$<^3t% z<6ArMi9Rwq3e}N9pG$o|g7k5jX>K+ZWu_@F$xK`NAkl3lk4X}6z^WyCgPzz^)6x3i zG=(LXNfqaN6m%Ap#s6Y(p0*&!odlh$-v`ls7Itlzim!x({BF?aH3Vm%A8o!_Zb!YOzR_i&u?7< zZ*necij2ExUQd|_UK*=LuU0of4aO$>dos-Rv2#fVqIsJiPSO%k$fxfjUhoL@WTUJ| z*)~x&jXe|2ap_BcNZ?#(w?B*^Dr+`4<=ooF(>F?+16H&GQE(A&qtCO;W#4?E_;3q* z>Cs*}OAkrS#l0HDT>46PNuE*jmJx2wGL{~evYWbl#B(WaHSSfP88h7bW}AJp69u=u z4_j(2x6?ir;$tQ*3#9jhboB`*-j9~|Ar4Dlb6zG^qPX3uC@ep~LB8_F*fjFe^0M-t znB<&d`>mj}&OCu;T0D1>i6r&rIRR)l?X<& zs?~^2-({aOhxx&(Y9+AB9N{UZ5`8Z69hQ=BfSsf=pHT)Y`Mec2w~?^ z-aE$wlk-o75%pv8aMcXc-)_sdbHuZ(5JmKLiU+3jJ7ZJ_tbu{yS7NHU2eJ(j;^C3(DSf zOkUWg<)_Jvw6K6nT$9+X%w14c!47Bdiu(DbYFA#(kMMU|lD{X3)CqT-YS!LAA=7wm@`Ze!_ox@o8R6l>iQp;z`kuHkMU|xGXuwB4bA9PH-P^WgNK#nS*F(@#4nhAS#G*c` z6)<W-!~H_sJF}Di9dk}bdpj`X^y-AJ?d@Y-A?@`cmXu>|Tl#6D zyBy@rc889W*01c;dQ$$goAw+P-klw8c56?+7vGVj>ADA1cMnL@^e78kho)D$jJK4& zmB}n+z7{;*-pQvJiLPNFqw^Bx{9L|Busk1&&Q&~)pES5ts-rV@)MVdmmnuXq_J4s-+6tV zqPIxVyCqo8iSLsPs|U&8u}1WA+{X2}_Nl7PvF)OPUm`rP$ykZq54PmHV@W1C7m(6E zBSvS-S}_Kd<~#O90LcsmEIph z#P@$yWrpNyZXCToA?3fYKmHN6if^~=MvaZ(C*Amk=-ws)HWFBPkaztLs<{CDlK zc$@UJ{Y6JxJ<@H_#z?1)lQP?Ir`vcZ!~gA~pB3WV$|nUtQV0@m@>CKOK^0Z_P;RHZ zqqNZ(i+W-Crhv6Z=6*FO@5jbkmrQA3Y$hZi{wNAm868(<&m5&xoye_LcRbL}is*sK zVyQU40hp-4%dAwwV`L)SZ)aU93OsgD`PM3?HFJJZ%jgo(M;1-;un+5CWQF4KIZzjiy|ykW3RpAps~B&M!U+MF0Vv>4GF+e0VEWW|z_*BHVJ z*ckI0BaA2I-5y*lZu{_CszaY17(I*#ne6ceqVp@TYSnU~;?N`!^VkL!sTdrr6R)N& zi|Yo^LeqX;8|Bq#!E;BI`w6MsFZiPpf){5?w#Ly{zP6C^w??BD>dFw(ZK#Y+|)vaz0WkB&`tv+iQFA5lB}6d+w{MY9ya;34es15gz)Y!STmtuhcmMrs}eXc$(Pd=&EG>RjNLpVoT;a zIJhSP4lQyR71cSlDOy2>l1nv88rw?&vJL)T$@W8h3Z=o)<~~ji(}g*~;Q+km0K6ms z=%hmMCIGR4wAW!TyD}`krtMT+nu&XrRQ)$?cl94r{>2O`&bdbsRYFCznAn!m{Y$8A zSe`czQD9Zfkhu>RO+r$Mws8Bm!Cqus2PreePXy7i_bNmmql!rs8~q8FtqGc_p9yV~ zoOVflOGV^Ex`+q+24W%9xg_h`&nPO%9Fek}{=N3~PNmpjW$bE&9+pf+)S2bf=}jHg zU4~`k+ZBMTHAT!#1!sIZ@lEl6skOwZ)o{O(C+9aHFD24!DkIWc+o3|m_NyW&(??D_4SyY8*ghs`x5bO z|1Ev@J1P`ms{RRm`3`*w#S*MZk|?$QuqR~F6~bQZw^vG*EPoJ+qD$6~mZ!3Vw1tYa zZTi8teFLFxGxpuF>uHY&k@bTlpG=Khv&U~($Fym_>xk~Pl;}d7;}0Jhu%ue-RxAE6 z#gndu}cp487Lf~KxpPSfeShcmHF3H^>rwf_i6tk&Z zBFXlP)NR1HB;qldPo=%bB}+UM)~}uPXW@UTVYCA~tgS{#Qavqp*lw27{b;8{0gV$Ot^jo&I_9!e5(I+r;Ob%P|;(;fXU{hG?9|C8i&jGvVKmBBsZZYBFUShb%> zWShDmlj?yIh|nD(9#0Z+YKAP5CPefv*}f=(^!NYR{w}BQTd^@eX@9~`+Hd+s3E`Rl z_u8M~v|sXb?Qh$gsS%2Qr+sl^L?iwm^55AXO#8HQ={=gaB1-60KNmjv0 zs|Xhqj36Zo3a(+XIOXikbG)o8!ceRgV_{E}O0vLXeZe;xct60`#paTJe0oTvQ-$+nq`iy4@p>n$)Br(_)3poIji{4%&PC+BzTta zAn%rHnMs8NBRW6dzCX?lI4*&IVz0kY7CGV%%4Vy)9kQS1jYSFD19=mnf<+B>cRn5( z+gF_FqNswW!T$=oCIH)>``Pl81yV#BunJD&OY>Cjryk*aVaT-9gE*1Gcz2=7WY5cU zsERvPcYp@njqDfQso<7OWAG@4ll)JlN14?Xx;~WjL)7-B_(8RKyrN) zE9X__1HM)U-WE@Sy-@jQn0fVN80KcRROV>4mV-8W&j}vg4(fIoR}J3RQq%R~emDR%!Y97DFtFA=E19=Yd{2bPoQJ zq-Ut-A$tl>5#&SXD8>E5uVAPzB&k(jYI!6dIGDbErF{3Ca@arLaZF2BD9yVAQ$YDN9cqj}y^{QLa@Y>}=UD`}_hW917Eez>$-nTK0|Y$wsQ9eP z^L$0ECTC+5(eihcvU`d;+A_@kTSrPW|KYFO{>T=u6`X|qE2tyuH}!e%j`$U5p0yOo zo3I`oQ&x+ApHR@^|5hIMDlkE76tpZe30?L7HLrG5L^Zts<-Btp)KP$Iq~J3tz}=E} zk?&8G;S@^#kCfq$s`k*kzoauH`lr>2It8NFvWBlIVie~Gyz>i#C&0)r9eKEf5fPwt z;`{$WRKu?=Qvl~W03Y9(0k94L0lbkqa1d+sz2{)bP4^B!pd#9b{^}TH4KlFg$|M(k$QU2E<-tINynL z=G+vvS^%k)SK(AXJ)?3rsodiEbhx7?v1MuffH)D2y~4hEaYbls7i^l zEo=+w>G{+dNdNtK`a$XPl!CH+>H^tLYP9bM8N zbxH5)l8$vrf6*n~-X$HP|1$X*+a-N!m-P2t>UX98$u8ycefUiLfy}hpAB%bl7!p`3 z?hkYs|3&H}ArcMeq96LEv&F^nkvUxcCu}-<<%Q7^rNk02_M3tpd--6Qb}mrU&XC$A zIj-Po^4(;Dz-8oZ3ihz)CL#D#ipKIZpt~rpO@7=NF zbGz+Kq2A#|E+MEh%&~RkX4Fq+r}R(c$DUOmKOc9ldkq0`Kqh`+2fSW;IHc7r6Uo&c zUJyE^%52udyWLgpHaU=9S4#n(Pt2d~XO0RtW>xZ^&0hIrpr8z%L9Lm=)0Z^xyecFu z0oII&8WA0*Z|bWPNzl+crLFWJ_$kOqw&Am?e*iYeZ&v>h|EtW;-)Pt8k|T}r4dkPZ zeesnbsFnr``G!EQzsGw*OYC}tQ{FgzeW!Td(!H(Fn-1xjQCXU-70-xEUabCnX7q6q z_SJ(Bq!WGD>K^aGJeA;M*-LW8xP;n$mV)BM>(|VM*a7)E-t*!=a2|aG$NDS<=x6V& zOg1UCWy?VUfnWN(Uukz-MM8D}$e59%*ZxqX-QJHZK3VX(6FO-6B*z{q6j)X4*EGs4 zWUWpY6s2Do?r;2cpXufi9Dzbeb+zb4^3duY_6Qe#!tDP17Qcj~B)QAkH}*I1EF!%_ z4IG>cSm%dx+e%rxcD#Sz!hEs!B4)PKALq5Gs6Z!lqz#WFAWDnL89IO+; zD(I95UZnF9wj0DE1A7M(JnQ^)m1kC}*+$Q-0_S$yu4ILl(`EBLmopnedV0u-LnE6u zr8}6sHgXq%Ua%^PBq%$yo9dKY$j@a{i(34+&tha!o~SZE516wW{pP{)#uh(r0^bTS zL$B-R4~E4#4ix!bHq2`c>z78;ZjMOoxA&DQ_2HDh!n!CI8HjIIGnue#cYyEWYme*< z75oZD*etLYz@U7x!aX8Ki(Ew|65Zq*@ptm><9p33xs%Vj z>$PZzR(Ba1;Ry9R= zWPl_8GN1RbwjzsFVeR2u?e?AI)*kMrE&Gz34&zfo2N2;99KUpM5I^~zQ~d$AUCPtn z#=#|RId?rU1RLYi9RJ$8Lt9Y@9%(W)zHR)?)VTjZ`JQ=0K#oKA01BEp*01|eh@Dhc zy3KIE>)x&!;KYKA^^0(_9j;^uJj&i3O_ZSzQS{+4SeDVl%Qp3nS`&kDUBux2&d(?P{{ z@noasV&zj}3|MkA=ha5itpA-8h zX6B4g8ze;D1G-mu(yw#SlKgaD}l?IGv8_kl4)MDXL~AsgnM2B-hc`rO*^hC~;S0=<`L?OzQL1Y)!__059iV(tX*} z!F-gM7B)va`XkM3+j~^&jaZEu95U9o#Yr0gpITj!3?mcZR_syum!K!Z$46Jk8tFaWFT368Z~Ot5sAO6| zo}-~u4Jo^2XKLf2g&i`{4k26yAP6o5L7W@Msd054X~u}GG6YgAmOv^@8T8mUf;5&d zL^*giQ!jP`)F;#5OZq6%9jIFz)N`ECpV4KRc#jvn5{67#e68*PvSn_H%>)?)f3QqO z-^@%_PXnXF>IXYgtbTyfID64KFfG6OR3h>LK?w+AZ-dk+ehxq}9+b?YB>uSSjo5GK zn)FC;vZj*dyalP_Gxx<7@J#7j>@N_l;^XPv1jF*&_Yq3Rv2XuV2ol3M-WQ1a`S~ta zqPjwMye)D$1Nao~bLd8Hos5w$ShmjQz6IYoYOLQ_znRRyY;(fT7L21H@N+e)DHzwK zz-PABZzjK5#g}CXRUsyt>~sc0ps7*$cutq~*oIm}wD3cQUV|ubAR2m!)02(-1{>!zTKq4G%mP+Xm7Icj zPfze0Q0(Jh%f*hxHzBl_5T*D{M?;qk@blR()YeQ_-*9@4pr-PcHwJHEh${@ucmhcz z=K6)~N?epLSah>deHezD*!BmYFgZ`R-@Xe3n1=A)+O)$c@h|EiiO<7okQ`wkin_}{ z5&9h+obql`2jfjEm5RmJrtL|W^+!FGQtJ=U2GBok_1ALnn6Hz7T*B(?E2z0mMq*MV z_IK|j5*6p&QmS@_wD2Q>hTnr^wl<=R8byryT4fPruSxw_7RD!FmFS5{)ktuGT#Z?N z8?`c|_*z8TJ7gbX+l@8cA{FwTJ0K~>7QW98y!o}lmi};%gV5Y4(j40%O&Ohhq;5Hz zmK-(!sSiACdMw=_9H#{;9(eKu=H0g`iJn;ha}wmQ`_TS&;1JC^ATJUPbx9>f1SuioP8j<2lh%27&J1_KV zaH`J1FyF9SN^h#bC>>Py{&n?{ztonJBZiy#R@9=hmhKpH*~94^I(7UlX3w$~xq`!L zH2%KKXZ|v?jQ2O4^7MGCfS@ZNh=Ilx0gk39ms2>f=<13o=yvdIE}wkM7-*Mp_`>7l za3lTsE&9yF##}Rv<=9d5CbU!}_j7>$)^5S}QNgw*eJe*&`C*`~Y8KpYPnXF%3GM7U zDl5^k{_nj1r%u7hnMl9v_o+jPY~;lz_ea)_{|++Q+RM=YP9DN|X8CRi&9z9GnT_az-%*P_X8JRhg>PaS$<&KDEx> zgl0MuuV*kSrN+2;**9!WDkVI2)Jjg#&r>P>hNG;1%RGNad}VsKwT_nGo-!yV#q@m1vWP z|JJ%RR!-{oYB0J)Fefdhwp7(v08Vks!kdzo5o?IVM%auj|yyic0p8 zxQAhwem*kxk;jX zcXB>H7a`dzj!)6LL#y)wf;ngf>kqX_1#T2m_y=$k?3t9$pILouTIRd%KfFU z^n2aAflp9^OCi0Jmw=@v%svjAvKe%g!|5k{YBMrHVVJawAJfv7%_jkchjs7A+6wl# zC9y~J{?g;%k~l$S&FiXTd|Nm~RtJC{{xMg(Z7R0SM|6XQr+J{t3iNL0o^HW>&wQ{#(nD?v~otYX^An}np$j^)tT;b7;!iE**~M0^%4EPvluKZCyOPK8$c zOSVRsqnB1i786p&t)$LC?3(R-exW=`eE(|&M4&m5UW$}KlVbhwKaj>NB9a!Aoqw9f^c~I zCI#l&BvRDRt9US3(OS{^3Im=mOR8QjS+)@1(`lnQxFzT1$JR=HE_cxrVL zRjRr@k7{aGj;Xse(LDLx5GiF$D%KocJdN<8+Hx51QY|);hGgIiJy6)6wm2-LHv7(` z$nmlZc}vRUM2DCVsM3Arpxg60=+qDUh`sK5UPD_wioN7*0kdU9R%jGIemSDsP1mYV z)Y^9*n;fnD4on1!8K_mXg4J@qiD>VWJwWr9YFbF%*jtUG`J&5tr40VE9sYX2 zUr+Gc&ldcIzZ)T?gTMTr=kGX&-iLXl_>&Rp@OSHLKjH7sw<>uE?i9SV@4yEH{(t4~ zG)Vnl`O9(mI|lyb41@hv-=FYzAEb2fSEhD4f6{;Q`#;#2+jykt%}LYyr_Dd%ugMv= z7iYjr`wo9|1^$2KZw#a+`AeOLUb@#{Os8BRr80GRVZ@Q&!Qb=AuO#IufJKdHSb9=U z&@$;F9()#nFM_8gaIpbumbPOQ%F1#JAmR3GZTW}1Ffs7qxk+;C=M8=7CaKsJtva*o zOrOl0d_|{6n?lHk_(V?joeJ;5-_|Z_;xtOVLR!`6ZCdQ9_cxkN;X_PZx0CCOjw7zM zY4PH4EZc}q=BWCPw_<_lw2S1oTe!Vi81TO5ug~WeEVlsp5|M2F__zZ(gbAjP*~&K2 z!fyOJtt+@4Kz*a@eC}e@Y}%M}lzgyIgqAe);-L|5X^nrTI-qM|`6j&TO)`G0J6ma& zFSz!!mdZv5o^!7j^(OSN0*Nl&$BW_RLObVqKO^lD(R-KX@(8`10ULV>JN@(brSR9E z-hxW;8wA+Pl~UEHX-YZ>ITiet>1``PZ~wYaQf=1<$8a6JqI|1aW>3ORF`{D)t`%?! z+a5y_OOtRkZwJ0qr?b=tTf{IWPdZLt51-$r=DRNO2j|YxRB%1#;F_y&1(NF@_T`@h z*MZTwS@Jt#W95<)+n&Eang+x1YAC9(&r6bKm&=Rt@wpHZn-7f0Uk)&K^6!&BsNUtg zJQS2W6l`WjRf{hpdc!kvY>E&o2bQ=PgN!aW?Bf-4hwK}j=Imed)DQUWA}#WF?5y7k z^+MFXH;5Uu_;(>um%h<&;|?7lP@sPI-T8nOr0Vs4+x{)}ISoUfRB#r59%u0v&ymAS zeN_IK8CB6SQvzQ0e5NYwRXb!OGx98W{nqpk{CJI#M@Uq1EyRe9$*sa|tTZPzsI)ms zewcNNpgShrj8SB-Zk7((uP0Wi1KmOjC&3;%4O$t9w%Hus{S^f3^^@4KcmV8=@lUP&6D#JO8qvi|Us`|it;h-g4DIdiJfJSc2wrh14VUes0 zO9(0T@L3lR@^h%Shwj~UYYw|RZ&bno(CiG3gL<|C<=r&+e_?K{oSOQ}1hP`}?|>?y z<{YSS#0Y=?ZWTAdk*UG&44|}g1nA{c1xSQL6R3*GeU(WKa!{$V#oquXg3SI#dD@=> zsy_K6T|em=5tR%=mZi7A?7D4LSLGkv-L$70w}P_$&s?)r4u7+yh&%j@e$5uSDxF=` z!1dxye;jUBH7qWQ-sw7b7GaYLH*s|`wdIe2ZfVT5YUlzshqH7%K84k6J-A2pLerrE zO^3UcZVtER>*k~nVz06GO%zOcFiTkABeAIL@`Y-uILOqkzkI(4#k#ntlQU#ryFo<7 zeKO&v3Wp`Uxk&mo=H*>~nUG~7HkenDx{@}RF)FPwGekD#B{O1;v`V1Qd@Cl7Gv^i3 z>*I735kkIOpa>ZUA<40G^E0fDl4Iv(d_DZUt1AN0>kWJ7dcpXKU0#e4!Cx=s$*n^> zysLObQRox~PxsAYP!35Da%GzmIsu$g1=E^SKiZaBqgCxs?BP6>@`(rJ+~SQ^csN>r z(@?|8hO|FAq&>&Ki3}DF0L|g_BEv9dk2nQ&_0FH6)$N8ccs*g0EHp*M6uXX& zY4zVy%0(2V5ro^H;Zrw<1{~bO8R8izg~5#)b9?EV2EVUT_Xj}vHM8^X&vM0&t{pp! z)j0REyc-25xWt-J!pzd$8a;?iW^c z?2}Lg^*chrHT-HBCzGm`nk~3V^==6UGDE>ilDkU;t!xUA<6An-U!CQP9G&2R5q-8%1gH)+W6JDL2V#Y+`(*wU zo2Y(8j=q%Nt-_gF#C)AP{(NbZ&}!|H>P#p3ws8~$w1g!?{#jw0zihet-`48>mLvV} zwz|z}UnGEX!a>1mb^oG}gLGno0@1rgQ`tPJ^llAAN3{n}P1-+Tv3pwKR#b+=6ZEny*C{$UHXNIS;Fh~6#AV0iDASs%NyBgEH!!p_VeRx|&J zGO*8+`N&cf36MiQw2M$qLMYZnIZBK8nboH^x?R_tFP6&Wz~!ulgL_b`c4cLnx%}_m z?wGOCxA>w(_~Qhp=1l(v_72}hke>#XAcx$X7NmG|YM0XP-Y6tg@#8vQ%NM?OoGbFk zd)ujzMGa;bqMEXnMPe>{`zy}QV%>3KG{Z;O#(Q2SH`#2wMObH{J3G9v8@rBs)%eMK z!NIi}dzb3QyFem5?%`&g&$673XJ)(*Og<|tQswHq7CD|Ya&u%EPRf#4&DRd*=N-(` zz^sU4pbrzwmI7_@w*dw>bM|3$nJxT<&ZNPvshTwMDV0g1P@VznMdemSUzA>|^s>=f zY4xkL_$_pEe`WY9r|x7PQrEdE#SrIl06WSv;)XrLDP7bU`^hr%Rw(1!j- z7})XGElU_>B0a&nTSUNE=QpVRt;TRgKR;mxC4%7?FmUELcnW;v`eklJcNRmo9$w_) zyNuX8WsQf!fuD`l$je~!<0FJ)?jT0lzr$zwH^`(Jm0u!|X&LLhOPXxdIqG~Pk(+Xi zhZd1}iVfNJE1U(v?ED1UoKA5U`4Jtzj8s=_9L7%Q zyXQtl-&AmQ=TW#^DpW zRiOeKZwfwZ=>B{7lHR$1NPJq>C+7Ii(&rh~dPUDj|C~QyU0E%LIeK$7t3?&tG;nM= zdx#UZ-}cfVQwvJOG)0&=I^R$SkL5=$7oiHo8OCS)4kfk1!N=f+8JtZM0K-@%Gv>fGy*Hz z6`ZI!#Qnd2=g0>Q4%y?`YOCb?(?$00Urq+!JA91P{ANvXh@7KlTUfByc-_%Kt^&yMRYkT@C*UBoHoPqA(KgQK1c9TB4$f5Y50$ zI0Fd=HHr#K8;f{Hoe{i%gEIp;9>-!;)Yq!CUW(VEtq@Ql0nLC~3upzjRis|dI9@<4 zAOiFK*4}4s0sZ=apYM78JP(<3&R+Yr_S$Q$z4qE`1Da?C$NBpe+db8V%V2I7k zl=FcuXFg0SO`HEi2}<&6`jGvM=?t8+pRtdBrsZKQSo76YC`CB-QoAbtd;5h$kPS-s zsFkM@Kp^3C`e#Lv6qA`3fUY=rf5n; zr`5_Q`$AHk0B^y*@$fvp2{&SuyO!Bj3A0cqJ|owt0sNA=pGN#qOF_KA=0FO+x@?8; ztMbH+4ClQ3@zh#i;P7hPF0^eo%l0dL~=v+yqw-|c_UEg4#+_cLTjnYCGSl?Fq#{^g6pTqqphtLXXRg*AS^SGhSEl#&`|1 z)X-#xBt73~N8&2gjstVrF=q)}O`5t7JndQYitha#X?`YJ-#}w_$NglOlz3`jZagC3 zA5idkV>$q)0Ho^|{+FMBS=apMcgg=iUj8n22TdV{`K~MS2WdYlP~>TOu!;+%9JU#? ziH75NB5=2oCdRYJ`Ms>ZNOU=)03^D(|y6DldznsL1SE+xyNVz0))rIouS!2hay#yk06R(7yla z*_5qJ>zkq(?n2xoWedQo=;1O36Vp~Az~_1RoX(Dm^+R>d39$Oeoel+jaH;BH970eO zfEhrUZae=X?M(g_eUWjTiusymj=vl?sN*1uy!Bw_e5s)VK;e_x>BP?nlv>SOu_PTf zy#Fngfm2!i8>YVeN*xx}?Zy2-^RzXAPlxxP$tIg`YaW<2s;I{I-OP^UC#rv4{DHm@ z3napsT3r!Lm9+CJ@^5Nn6Zuy%7p&R~n6IJ|zv?&l1};df1*HxvvCoi8TRAw{+v*{T za)l5ly6VPVvg!_=F9*5IP2AtCIgdRVaPYA0GKIADj9PkJ=f5D5ag+VkPRXgyJLufO zyA8{w1}7qe$$aRS{4<4otP6=zNO}P^UKi3}er``eDx-Ry;<+55ye(ucAJbQjd&ye^>Z#2ZNo!St4TJ%0zswLe^ z3*=3f9ZCVQZ|*0`pRk>4ou`lNOVyLC0luVFQq(s4Y`$@T7#lnHSD2$F^Pgwc2fDJ6 zLY*F^HDJ@RHE7F&W4JMu;l@#&Z5P58gYxk#hCG_#GWuhnLDt4q?X1FQc%d%QNriW7 zo0(^YNJ{aH@X#V@ca8eRo+>S*%_eP@79YhsOW@?o+_+&E4M8@I?Q8F@WQVIG*M6Ce zw>y-f-|-v8Z2mI^8Z!SbTl<^^iT$aa{-t9X9Q>RfF~OH%%~f5G-6w--)T|VvW3Yd6 zMp}M5p8}T-pSF{ARvFRU)NO{WCLoRdFZsfMwkfR8-u$tyXoBh({?R+6!qGEitv1@Q z?h8qy#LY;vgGmG_koCGpci}|3kmH$X|N2=~S{6J}AmwIqqjDh6^7VIXJY)TaEp7^e z#1-tJ2ojg@3mr_gm-m$iy|8#eKPyJ{gnnK?1MOW>OU!DQ=R4(l*7SIw8r?~W_;&QI zAMr=i{HKC`nU|=cIgRcq;c3r%CaryE`A1qm?KvrNEv3$rl)9Yrbb0YtBrq-o-=Pcc z;D@DR)f&#HRWkB~0<0@nb6?5mqp1z?cEtzjg~a1z!K#!*QL$}n9K9EuH|PqMWCwNq~L6{#jW zP6O@bboz_o99?(+}aCi=O_nCs84WUlEY`m{0$7asI0NBnK}OypvC=k~zo(e@iZH9PD^c5|rqVO{OTYL<#w z6-`3T`I*!wJfIn_Dg_0WP`Tq9vR{3s$(lJ$4LV+^jpl1U^G$n=oMRJ#uqy7`O}S{p zKU12@P;cwBUf{#>p>AKn>7AAVb*(q|Hb)Vg&$kspJQl@m~&t zQfwKd`OWej^1eL#E?b4k=d$l;OsV9{_h^^ z;_~EES^0>05cmf&@YKgx*~6$3D|_;Gw%LU~&iu7vF-OqMmqb2i_Fxr#eD(zNaTcGa z%wscPXk!cUhGu=|-A9U5+?7o)z8U6>5+k;}oky=p zj_>V*Dbt!SRyY>3XBe^hPzYdL-eKuS6?XINGG#3{=jc?il49~hQJjHJ|uG*O0EVSN?xW`BlYOuq&W z9zLxy_*J~FTFS^t2!1A+e@SK*cA~J$)`<+&q{QV2r0n>lKf@hD6hRrqPd+IcP1=5& z&#xgjz29sFhgvh)d(f@-$kIs(%iWJCF6Q_b?@k3uJv&}y69_ZOS+tS8%|PEBo%(}E zKBVM>I$^=}etaOra2>3Dusn*1sg#FhO|(p*$^Iw9r#L*Tvr#0O)B1YNsW8;*L07rg zoLpkgDD#>#)L>b@I?hyAOTTdYsemIG{0_C_@Cd88qZj=&x5b)>3PF9AcZx z2=!d3N9bdQQai7!&B}LZ`ywq z=r=S=2U&IMb>vNj*eDKVB1%E!WUpHP?%{se%K>Vzi1tkN%1?gRJ9Pg-XF5;%*w_w9uaU8NFrMVBJt+)a(qdQ^-q~ ztLfpuecS8QtMsd^y{t0L`_(x8J>aEX*sr*g0R-aRw;7yHHE5U6squh^;e|a7g8rg$$d5H(G1DZGXM7} zFCYIIf4xk9*gWC%YRX+5?1oFo$AlKSQ9MHeerw_&B6;632=B2EgZ&axfpp5K`5`cU z`1NJMZydB^by5ruw6hQFY}m^_KMRIqkQ+D<@{D})vxiY)-;X{jR_ch9m(`$zh-m+9 zbS$5Ka`B<`CM^oreL{9eb6QMMIMOR&&rNtZ@Iv%{r9PFuFAIpH_`ydo;#!9dS}Go^ z{*I3-8hdp#9ES&x8m-mFjxAoZ-P5u2NTcKPf$XVxIHq{n`=R;w7wky*hiqc=$~$DG z?~0B~Jmz`_a!0~k*YQ2yJ3K>PceVPdn&VP<-OZ@-nrpRd?B_iBE_+}0Cn;ODz*hQV zgZiiaWY@DkDD;H?39??ePR4D!$9#|v3sZ;7gzLFDTDy+Okm`W;1zo_ zO8R_On25d>r)Vx1(v+ZCO_t^!;c<67r=UMls-<$?ZMZ$Q?R{vqlN`lzXa_?+gyqDwYe;=~VyN1>GtG^ViKn zLCKGE*ONoV^PU+n>>4nc?5E(<`og>B#<|6hB)K&Uo#FFP?OYxU0%!npi%lM>!ZDJ| z<-~o?=E_RRO00MtKP>$|Qa{Bbo8{x- zKVX0${N&19%c>C@_VG@E9sIA!gj2Nd6)ml{iel%*yQ}enlj?C}=;Nd4D=mnR60<)| zkof&uv)YK)vs);e)ap};vp4?^zR+3x$mfN`<8+e(ue*nZ#A5?-nSqfKV5A)s zl3XetcD`p)?wwb5E2!~36Bq_j>~2!_05_Dij5Q-WFZQ;(S-#yN6xfpzpun{EoL(qW z3F{k*Nc@I+vhr{L`+1?-7j2qqn2lRq5tO_F`!?x;%pz9C|KUSJY}hrw0NJq2(MKNLK}txz;cvlO@7vlCEAsof>a(%1(`TOUHLF>NbFpX9-=s#PnkZ=0vVN7@>xznus)&4JUub(8y}Kl>>toe5-xzXelHt)m3&fcFS$nl ztjyAH9=*^0qLm`jBp<51?lY>#=1hPuoM5E|#BJE<{BD-&c-NEAIYXZg>kt_vIb+^I ziea;>&38g7 zwJVRO-`g7`1Q_nhW;{7iD6Q6kNC*aZyuGIlc@WbC|wBSwEjDtbZ4Grd1o9U|D zAnP{=aEiQ{&@fl_Kwp`3(}~39`dMdT}XhW#Rw^0yO@v zQK9i|u<6JSd&O^MPJoa2C^bJ4pMp2RY8L-F{$QE)OsMvOj}>9R>5AZ+250O$$Zo;# zFNE?SA8J!Fw6PP;JeFRz5K-1M3xLe!Jt-@q*7zTQIHD&y=$>r#OwI-lQRs;;@h zZ4EreV63i)+Rn0!a$&APwP#1iu9Tb5Y6nUyT+umzXY_euFZ_#l7#A`7HiJ+AZ(+Cs z-0V#KGR#&(aY@QO_EH&veSiyh!on0X;&nr%pd=^hil6&8jTW_E%5FerLp!zCZWAtB zdlzZ&Fbs`&=ABFxpVBvW-N%*LU(1z0u_E1|j(_*ia|6+;<_5oNZWu!d=c1!fJi?$bIJ+JCV|>iHVIFqrj^og9IrK$$6wOdwEb0dpB#TSyAR`* zI4wJ0a!?Yhy>qJ?EJ33c=s6UAJOvTdsa&OR8l&jx?uP8Nye39jvb^eo>kYp_>PSR1 ziNBpEZzg1!rEd#(R0p0nX!ER`ifH`^Y(PoH9H|H8d%xDY?XbU5VuP7X4%~--5!8|_ z-r>VJw<|jByF5yWcvx2@jZeNMlb;FC+}G4_PBFyNynuyeF%q|Vp*&!PXPC5APk^Q9)ttHhZ!CoR?9=Bz7=jl zW}PBCXaB1)*7sl9W7)3KxK;Y;kK^}~%?iI9_mpE+;3y+rrW3F8@TY&KF#P+k91LG^ zi6~OF-|>??Jj)OE!FS;BhRpimT^<7$DztBK)(@P?#W*hl!RJt~&mmrYgop1A>G~Xj zU_-q5=&>*Tjy^V0ii};%y>qZMRga%x^<}W+g0O}%hOcpM|DWSmWA%@N{$F7A)nETF zuzD$2wQu`|LEfkY(2wJn%>lhX6smQ908SavGIIk8Kn2pB_t=?*`sm<*w~_gbbf=Pa zjQB#kkWb=AjUP4|EK0ND=wI+47LarJB|;;yk=vLX3>GITV}oPIFgCGab6A?OqWXy-U^EA5O-;DM%d^h`cY@r2Lp!G!R& zrQFjPGZchg^+ana=tb_te5ymFqCa`9N$@{^IoicSulb(e?7Nl?qebRnckxD~ZrEd@ zKjo$MKl>$GoCs#*Np3wQQV-|9btPkBMPhX-@T2$mhv2_dT){FA^mI$PXR(Z>MW@hh zPO_EJFh}!SPE{$p=UiBU)ws~!yB4&-bQwvtT(ZC9gECndc?>o?Uv+y@?pqj2-HzmZ zEXU7VjaX6wPtiJ7b7L)Eg*CIyvs7wB`&t-n_qzOz73TLCKvV8Tw2l=@2|-)uie{s? zSPn|Le@>yQh4F%7L8G9&YP$;Jn#Pa5pN!ES-6Q4Rp}RTED~K z3=QZg1S@&y*clbox4CU!jK0MhPGj_V7R!m%3`@#An=;v5T=dW0 z969*way}N)*~kW8jAi!GOB)Mp%hZONb08ot!gieA#}7 z_JH3-gbP*Y3bXjVfQ(?FTw~#6enkIsCae*UOOtKiZTxlb0Lu=mxQ=&OdBN9d{bH$H z=s;Ul66cVr@lVNj)hYbG$4?r++h=F-J4RqL_l;oxR+R|vNRNOlZ!-Jg;_qsCD!A{+ z;dXUbvdXHSgx`>~N9|9Nj&JHk#6mAKyUA&xZ22m*qWC+AOFWuU8s5X6ZGMpxq)6=_ zMR~;bVV6Cx&dCCh&fg_%YHoX!&w(?41wQZmQl5P{{Cz4giC{sDv)K^q>w(Q&xB-^P z6$<{s4v)nxHG#&)mUh((F)fXW9oCKAi4l0uY71XKPilMx>*EpNOdsu0?f@D5LRJ-) zaf?Lj3JDV0@O(%mH!@fec~$uE7LFvMr!-jO(<+^Ve3zVvoYSd(Y^-m{2*12qWeJ=l z4bd$sT&01^j=3n|2D4 zy)eG9-S}>rXFd*kM*Xfgb3CB*_PLzJbZV>zoMrx75CjL-!J_5rVRX+{|4SaAp@UZehXtdrl~>5JXTcaS{%8p zon}b;{IR0;O#5cH@-JQ~v#ogXk)NzD| z(~8u4>tNy>1))<7m&Ugq|72$TwL8%JnRlULs;$-4UVXh&t$3^3lcj2wZmHzc8ThQc zw2DLPAvd{L1z~?y1syw2QH`1luj{#Ro~+T0LP9#~X@Gwo(?BK!l@?N|SC}i(=AG-P zxrlxsZR}g{Prd$l)fIMOGDIx%uMIO{D*36JFUb#o+#bQKG#e}8zBefnrVo*fsgSmW zXI7vgdAp4e)!7x9$DA@+X3~Na1fLDDK`YS0E)_@*1_P!aksg2!NrWRo_gT%X=L=0ObVXM4B-t8bGvDa+y+M#Tk%k_nHi*#?OB{zERe`xh-2;@$ zCW+}h(irkMb?1UtJK)q%sLD%c5j|K}BiVAZY)LmPw+2x4BQ=PX&*NIoJ~^wrQL=|n zShI50WZc+1=7+ARgfJ!u=^|+}Va{{#mTs;gv4ye?Fgv-ZIad14X==U<?4ieR zLK}XbG8GZ!n$?Dt6yP7I0+6?KEB@RCKn6Td++sM(u1jTWWnbH4vugLPIDl6d6#tU&$N z1r`4A$`K8*2Zj9n78f<4F0o@f{dhlTJDHz@7=W?6BWq?I>OHL>aE>fL3p+%l5U`IA zql}u>!EZb&gx|_Ce|S};C;WXy@I?fwu%-ueyN|sp&6?_Hv6_gm9K9i1SJ2q9hPh%g zL2yfQVW3!SG?R3UwS4Hs8&e-^L zU&dXL?#pA-vwdOvKcoLPwyY;)BpOT6@AAgTKRMGU0Y}2?`qT1;@jpt}@%rUiPJO!6 zA`&7kbhNxhJ^}C1@Hgea_xmaM^ELdjIq)Cc@Dt@<>$K;xYc=u3 z$yx+Baaz$7ES8z=MX|e5d-v|$vF@nXXKxAdFJPPN#6M#VrLs#il*|PkiLxClLm_Hk zT7YPEd5N1~bi=u$!(3OePBmm{0d@@|ys>-35RSNS#Y|SXQH~0#19esFQ|>n#WSz^t zpDVJBBCXy;ZYqk+b}C;zSk;{{JE-ePsfxml*qCl+oNCt96~vA3dz8J!5Eom!aK=fl z#pm?rR=3{4L3;jn7Imk7B?nU6_8xOf{5;p<0o{NJYzgfu4g8BmRS)Twx+XvlM67Zx z**+V?m@Aanf;>vON7G2NldD8PR0UL<#_``*D;yi+(l~yZavU5-e@|A4&hZGpS$^*n z-7}P!E8pj(+@FtCd!0WMMbKkzql(pNBdQAJP0(39MM_nx^eOW+#Cu&Jyb9tZ+M2W9 zIU{Xr7JWhn$kQf&^?f97rT5(M@kqJvgf_&F#u_$=uBP4QcgEjPN9?|87Gl3yc31(V;MZ(>RL$&oK`DfK`uEjeVvxlrDkEwd=vGy7q$YW zmdwa(GU|qFQxjBplEn*t2T2HvE0%OOpm8}2pIqZ(f&g3-sT4Tp&ycW6s>|R6) z?v@f3OEo=uHi)32wJaNG!cn>j>*1@4?3RH|X~*nqQ8>hw!1Lo8^x;!gYyXr1b((yx zfPT$@%>(vE4f{t8dvgZXDfU=k+vGWMu#AVc4^^kf!YUrqNgbk%i`~BiHwWulZf{yn zhKAT#BmA>FM0=@vKUaS_)^Ca3CvY^9a{TVd`dJ4fC`X4sM}1kDl<8W?`>C9i4SuT( z^`g9VREB@32ri}nL(t3_f)|9ZNV~)(Bsz^o;uexho+088XH+?zdNEz{3LP3PY#tPc z$l(Nkz_L_iH<5|Ws3S+D++RZZG)OxvS1SXPUTJLwK@%vL(h{erdQYR2EZ(K^5~&;{ zrjjf7A0O2EbrTN97(e_iJ`_0)l_RU`4C^L>-A1CaS_n*ctRmQU#VX;Jd)92@UZbd3(F*>L&Rer>2Ba}IaS(Qs+tc*a zJ)?OYFQ(xEWL08|7>=*#X#2Gw?kjX;p#{xDkW^n*oVh%V5^ ziu5wriD@ut6+@8N!(7y(um${nwo~EvXS%{Qzs|?+Hv7J-()j(W(zi3SQC9z8)*$3> zpgBWPMNm}fx2uGrWbwY*D#6Y*JZ)#FWofNUZB_%T=(L^fR0wEYYMxkNX!KZzdT1=R zwI_5-zf|jY8lFmS$=DOXlXKV$w2Z$M0Z)n;e+szpP6uMZ*>!{=tUT zJycy3Od3|djH&H|G=!Y0sQDrIzNo%xnuw0g`Q`lk$yu0d6q|TO6v2Ls7DU_$_pTJe z9k7`H=jt87&#m5Ic{+xdD~;I24Gpm+V()|cLp5AE86*sH{Bkg>h98BVs1FLLD!rIByWzf@Xd6dl)Hx)T+oTmOeeHMa2`I&2awt|w4*c#G&@FT^-$L~po2~KEp$1eg+tK_gw5urClgru^;}5rk zrw$p{GD6dbc6ASKHd>lWs=XfLnY4)3HVu3#CTyWZ_`zDW)#SpI-`N0r)N|3!LK zACMk}W({G~<~#;{25PI`#~+h<)i4i#3FS(4sJ&8vHGmN>Dpy$0udc=C4$*F!B{dsv z`I}_KZMwsrr;1laYUn#7lrB}5*#VscGVZomGZrQ=h@XL@bLL#wkZS*3zAv=h6OeIDU8#P+Bk3a|1FRlMq}$r;T+)CK#LsREWQ z>fP1owyNh&zND5Ii@W68i|0gczK6*tTrvk=`TkZ@(|Qy$4EI@%OUuQ2_)pX^z?d}K z?LHKN+I?pjLbjUgs@@kTyc>k^5K};mp2-1XdYe?|nnPm>1atzwTp%1Py-&AtDhZ9T zTV6{mKOWbL(LDqS9;>J7?r56LF88fH3Ic!OMu@55uNcI2I9IKUR3X^}498G4|JpjI?ifkKn-MRg#kTxu!>8f*eMI39HP(e^I)9 zn<}}n-M*0roVaQ4nR+zZF3v~}JVs z!t~jq05*B8ng68f!+#++U#~_v4PPWA*kD~(p{@&3x`pcdQ@DqRXRbcd73oHsU2{(0 zFImDnZ*)c6JlFo4`OC>G9viK3SNga|(A=VUmM3+WSZ7)ML{aJq@aG*=jRl$opQw3f zP&M`TpxFxT^Qp#@+tj(goP^v%os-=TX{}Po z?H!i@J_Yb88s6#bP?}DS50Iy8Pt&V6`(?83zZ=BRR-W=yUakvjqM%IEi=^qZq~bah z2Y~tjlsJ@Ukj3nOibkyVC^rf(R1x`Fh>n2(@>jaJ!koS+9-%s;!YbQ?rQpvX0l)`p z@b%a!GPMf}wF?ADT%7@W2HQV zmlrMe#||UfgQd1Il!zGrtgzv*e2{+qztYRR*aIX{6q;yzV{F7besiwCxgxfP ztS>@@aX-dfAux5XcHly7-&BmJpGMIc7eXB!n~VM3>&vRv;DSYDrEY#p71cVRT!K6* z3_71&i;IxMs|pp_|K-@Px>L<#4dh}>=$9$pZ*TCTDi1=6ZD(v0Sev{d)} z+C6_ILSj@2`wBSDr{+mz;hof7E{u*$EoSD_Z(TEUy>c6S0*#+ z+>ZwtuvxLYf~)ix15fxh4omJqZ-yJo?CR9nSCCyzQsMKrku@zNaw{dW)b7fV#T*&Y-^Kzv&~)n^U4VWi*sohaaPLacs_HDIMY)Vh|8?AAcA z#G2KHtDbWs8*LYB5NvguwYyi&0Y&z!!Br~xRc1Y+7q!`VT+aT=Q0g3ikxKNNTp+nV zQ0~FL#Z8NYxGcE?EUs^)qHz>P^Sj2|Wbq@dv`qCQ=dbncKdvQpWmC+N5{Fbb4gY~0 z`#F558&QG17?YL${d;wx72!MyO`YIZCOf*+h(7@o zAEk8j!db*P+f4g%*25fu7RceFjOqRmdyGfQg%=+_AtkG7(!~W%-v%he+QNy;wM}}*(qNP=; zlEwv|PVZqU0&Bp04`?kKC^+HBVo~sGBfPihhM{;fA5blZjEk|*?Df2S424SnT+935 zyg6bbVHI8#+1NUYC@~+%`QV)l%)a(KPiSW0F|Mc_0tGd^b?0q3Z%QqiGOvpnaGtTg;LG^4k3U8(PFd>W;(*}9XjJH0-m9(HT~GicJX-EIrh6VFzqhcXaJ6gs zm{ep<(00Pkb6D1E4SOH2dkpY9wwr6s4Z>)JM1L!aO!wli|BO~Fhmq7ZU*-?qnqi9o zcZL0u9xIKLPKY>v$0tR0av99f{Gy@z;H7-U>c+7T)SGhqy2nt6Rl)*EfOC|9Q}T@% zBumnl9+jeuLi={-;o=IKQ)sWCZp9ta zK@39Ky^ zUHgUeQNOKWf8iK_xswR3*5HlLAq{@;#K!IQnLBoD^TsYO^bPrXWUOeo`JQ*k=iZv6 zYxK&RxVg#|c^x*zD2V(j+-#NAYzUl(+2b7$c`4<&Zd*b+4fu4BYCumKpzN56zEM+8 zp>7s9M?(TSI7#>73#nW=ZmNNaTuK4T(VT-}*rtlFr6lQPbUhncYwfH4sMj4AQ-ZlM zu?c9sex_78dr#fB>$*E)O&1z=jP$eiXh|1yak zN2|m!k|=7t)E$)KLGn=EgDv{w>-(XM%f2C(mEzUqn`K{1^AwYf@xuw5*)iF3qc zbcjVAF0dNKH1&lZw0p-eb|6YG!0hGcz#167#Sc@5L_6bT{~>JiQmUfI8`Q*B*h~z9 zwHPtgoE!)*5Q#_8RwapSIZ0JHndJ=bOF*R(t^5t20VT6CPtCeb4&in4L6xQ)0uHvv z^<_z3^MknW9ePVURwZ3wE(_Bq!;G3!XPxC*+@CHjJxbBxN`w^qLzuypUTlBP?rmsz zLGX<*cWEWpK=i8r8u(s-bNdf$;tN{jwVK%`qX|}!IM_%=ISEXBo3%KF299#dn5@ef zpI^pJl;P0B$hdb=2}meV2T7{dsNkQr`GMGVAWkuIh!J${k-{$P1Bjwx%2Gl=G#I7O zA19m7ZZ~p1ypxs9`51+&-Vg6AcHO%wHu2Cs34;%mv73=6|7%7z|4VAIk|b+N_x8lcoRM_%~mxcFM1kRBi4p3&x@>KRxKK!q_@w>u}1HX_0xy@W{BdIcj&nO)# zcZumi>$oN11yKmGWB;8k~e*OtChK4cSYZV6%>xRf{#}zPE zdl}C{*dNILFs(XK?E@a678jt%ZPz^rPA&Jfl0WV}(P2}fbs9Arr(@hG9Y>PAW|0tB z=@?aw>@}1~zIgF4KFB}x()3n=*dwy>)$3C3SB8j=J83hjQD3M|G(`;b=W(c>|Hk39CL&$76tR<7BTmCPBZ5wO8gd?RI$N(5Gv>ii?0WAcIN^zpqB7& zZ9~nc0pbkQS0+ER@27PfJU1Q}Hf0T)O=*F%pfhQLIF4AQ$C8wCZ(XQ1FB^4dtkQD% zDm_8ImiFO=%w95c^JKhu$733s@#2K@WS1$1So#1Q*!KRJY2~IRkk-b-)!ciaJ|oKQ z;F-={O_cmR`MEb0EF|xnw{N`1(hjmy^GIE@v#2?lr5A(rtfXOVvJO8X6?qwUA);v6 ztN9r&Q5lZV8NNO&w@C?|;l2C}$Ege_=nTvAGHlctcIRjK2J&`AM(7N&ybN)j!Nn8@ zS?NwMRT;+W3={J*EY=yS@-u`~h6{9tL}`1_ zO$YvOIq*!4LsT0k>ug=p_Coirs8@22&9v_v=35TEuU9bQP)J++`Du$)nko7Fr1O_v zJCNz;KKp1#ddFSSzkCnC=Ri%NKc(YU`bjzIZ%F#<>GUd<-ajY(pOP+AsPZ46(!V__ zTmF}lE+eSYw;d$)znzo5SJE#}r>|4#f5}OA?IL|lI{kT-es@lKg`^*wPQOc~U!Rj+ zCF#A>>DQ|Cvvbl%O8V!h!@B<}{iK}qvnBoYbb6Ia@1K)CNz$K6ryrowzm?D$;9rvKUW$P!6^h(D_Sbt?TYIq6qPx->$iKd;j7&ZbB2ko05I<=>^!uTQ6U zx}s8aqPLUoHVzj0$#B}+9}yax4+!*gMt<7WD(xo8{sw>a{5ZcnOMkBDI>wHSnU9Hf zKIHM!sd?~1OTb^2{+L*n2mfRHtN-zSST9+J_am>$D2F^7+f!>T-st zJZ(L*Z{?o0!?JG`=`&{vveMJ$%BBtF?%eEKwWke9oG!D@(^ipvGdyiv@0d<&(z`TH z?Grq0rP;K}p0)$CZ&N*O2V~!-dD^fYr%RdPX)DjXSs@-hZHHt(w5kvNvmeCw#G`_L z>x!-W)dyL>I3E_M4+m#IEL0!*ray#lo`5#c4hsEN(RN1cB|Tzus)+>AT{Ht{-1M4w zAWJ=*^a_pHs~7;ZhP~Zg(HjsDYGs(e8x1Y~35ErIV8`d>Y5gJ*S@nnKGaqow6Nu~w z6;&C5n}OiGoItF|e5lkP)@D8o)gRu;e5lqRKFEBi(;v2EJ{bDLXPFO8`h%VMFhPI# zPv*m9{h=E(Mi~l5P3`(&n*LCjftaB`6s13eLtsvSJ23N24Xx^8|I9Zvy6T&oZ(JQF zqwAnk#*Hrv_~MF+O$vV#HGTrhWbHhK8K-T6jwjK?k;KqsDq$0mAX_4jmJg75KkSc( zs+E^EWJUYH&7p&5Nu!)uQjX-}Qj)5aJ&;1k_!@~BHW3vm&&NgbQI1#<;|y>Ym+V<&ZvK%VTk zMEnJg=LkWQ93eP{BLn9;M+gqgkq`PX!3cGjz{8xCU3Nddp&rab!Dm7H?+O*#A03uK z`$zUE_z)=#K5;4|0g$_=rUQUv3)kTWvS(6h_X618f_bEIkrPpD!lp z3c4#XpuMrWZuX>SAreBv7!oAM#L8|pw~G+>ZRTyO^5HR?ck;WIcktG{k>3(m>y0!c zH0%5VtNs#^60TM;>(Q=Bnr1#dnZ{#j!0>3_bcXElGZI({x8gdQZG_hvcZnLF25U|T zV1uqyiV1M+`^hjV()NNk5S zs7aJKl^XPg87J_x&wgko{#AojWgWs17*DKe4?**MX54SxfNMh`Hli}dw@oCwLMRt=(SV0u9VSOmZx^SnQl?j}W`?zayfu|-O#MIb#kolfHYpn8`cn^%7-Ct4kI|^fLK5Ck_ zN7RDf7H-%&d5$$ld({R{ks8$t!INu&oE{@wi$`bY{@@Tvtr8;PCg!wO{p`Oll(EEb5am<&jPM=Bjlgy@2vXb!1WBy@ zW@fhR3N}}|TKCc_zZDrI+m5)V;7<~jQmxUK#HJN`V>c8ka`3mjWgi};K_Uw~Ky9@v z@+vt)GusdvUp1Q77_R6SDeebQ*|VZ(c*vCY0Q!gmQ;;96V= zx>gPqoRp3_AT#A<+gwy>d-`e8FJBqapsNYVx|@@lpc=LW>tz3QKsVVxjfy`^%00Zl z!+uKq=(5)oh0DnFp>V1?kE*h4$S#-SnW59T3`$5%u_1`e75Rc9nd|oUaF&4Z z3{J?-k>3CCv{6Zc-TbHj9p)ps=xXXKJ418eRo3)N5)ppI-}X$$%l^9DHZ<=R&`nfb z)$XtPhwCQ_?)3@FxS|tZUYr&N1~qQ$$YTphR6YKf9+DZ{Q*Z}=TIIbQm0%WmQ?4DA5M=s z<9EP;YWyN~(s9+X=+8B~ks-TY7yB5+Dk`)ur!e(|q0hIQZWjmw!YOh)^Y3Xid`9`& zOqNs0Ldk7ADK_ygfH)$2z>gLQJ^89df}Gk?TsNz4bkV2s_*weo(7mGOHds^H?|KJn z;OHBkwkr&CCQNn2c_>q(@06HGpAi#@Tbu^U$O+XL)+>^cBSXT68e+kQCd!i0+GfWN*RpVW1-~6<~sK~SMUY3YPUywh!%QlHoNZpT)?az4E@ukY8;p19O_V% zcoeHu^>0oQEcBo_DczGguY_%vyP52_bV#3I8oG#?x`-PnLeUI@I8(+^x(ugzrV@nG zyz|PXZEx#lWNJt^I*Q26u~$%Kuly=6*Hw1kUzN`d6T^xWklC*a`&K&##Deg!Qbolx z+fdC{@P9PK)B6sXmD2hnJ!P3ITJj8scG&(?XSmCMCGb2v-SwDJQUsD zS7G^VTuk>t(cY73uP9HVhg zpy@sCn~-=}+;5Bjrso1rXlM87P5dpq{^tZ`Ys$oUvg%-g5|}NdW@H!-PC`DZ_U#`` z7O`wDC@{(^Qb9Jj2N-AwcLWN6!e!dm(JMp?OFI2{_FJDk34Q}kGoGS(=ZSQCD~RUB z$x?4@d^YMnbjgq{Ia(i^;ejz>4nAt(k_~nN^Z*1%TMyZo6?@>tSPzKl5<5B zFq<}dEh_RNQTTEkSGgY&&d{I^1`ji3d0DiA_+a@5gK@@U_80$$h1vhN1tpjGp{?vx zh~?&$GC0dz#JpbSGmGs%f^v40eY;())zS{O@V}Rz;wOJD{6$7cVZ!cpB16-{1;FXW zp6Ft%1htaosAD}x*uQ!NIJ`gL#H-=E?ZnD0=Y2E0SY&TT^J;{)PRFtZVD>wIeW zY%dx#IoQ_|x@AydFEkZCDRfx#Lqb_fkkcTZ*;C)9uq2DSh8RH>Me|XM(gA}wompHa z+{#qB;Q#40-ZbE30VnG_S-;6E^{e$=Ilr_N>7dtlmHbv(zTK^(Bs|%EQ~+Sxgae3# z#$#-^KQ<1_AWOUg`{i#0tFGvsyikOSrbK+jUKu4U2tmPgK7L6dOCsHRZDEdDV`b}d4eY!@oq}LiH|HHS3%++fV3DN#Z&se zVztWqfe#5;<$*D&_W)h*vcZtNs0x08ken?%cvL` za6M$*6>BarISi~E86>`7nla#xqWM|4wq2COz#S0KR_%mPwO+1L{HCX~Vc^@TB`NL+ zD92luNr(%pbS}BLkEB)m7Al`+YuH7!c-bZ34V3Imy{iK2;*N2wc*gkDH}~BX8~&m2 z;PxGB!8jEi85Z)WjxozDI>Ye(O+`?PlgIl=X5IP|K=*9h`A4!N?VF< zBk)9un1*!)%O(1eT6CxH3kuzMe!+|$+dX*nZo!MF$r{exj8q3d#4!{Jv~0U#ZO=jL z%Z0M{J=1p#Gb0Z#jy&JreSsY6&_|+Z!hX*~y?cYKkGhhoO`I>lvgRciOm@$}UK!?{@xMgWLM6mpjNE3wHYMEa~+9 z_TEn4U9&rVzoP<o-gk;PY&CkYbn;0T)}5zpVf}d9e_`HMuP*HcDNUMi2SUAFY7ezb z1eTiBH}vpxpv2_-C~n)0A#>&RLl+hWA+$gr*45ircJs6r25)Wy9e6ywDyW>aYN_x} zwUd+>popV6Y#h=tGB%*3VaS^BmYv~UCD$$Hm*XmC zN4ULYoHd|V&Dt}~0VUUcm3&CkkHuxYh2~o8oI+OV{7FVl?oB_Za4%8Y`J1?&`ljUi zyPeGdPoPz4D-p+Qi1WmS><4jx$W!iG;+NajSxGgn#r@lH9Yr+STTn;a%E;O2YiEo* zj+$cn2teX%>-4?Kx7Qf^&ZGIZ+90@IcxSI0`f{^tFX_1a(dcRiT}Oki%NXqpy1EB1 zPoqm3#!Y5Ob4(unvk2-Bg18k@A!ro{DsLFF$wAPoKZc;E)yh)v(;YN}9dG~L$@w|h z>Ap8PSNn72+s&fu&36N*qUy(HK9lT?LC|V^hF}kanKtI@Xf`SL#kVO(Gzlx4k=`Ob zyn@zAV#W5fh3GVljyT;4IQX`#03Uu6)*u$5&cG_X@$3)&#yh7bSJ_3^WBCyGZD%c^ zwiqa{i#}*TN$HWpukHoR5Jv2wwW_XInIxL`maCtrp2fv?3rIX#0cPbNt>6t&qTk}` z4r!ebMP5@{@ufOPbrxoUh;RNGW>g3O7&iijHx({4R{WV#Eu!~}E*UFM=(mNurQCO73b8m{T(ra#QG(Y8?@{87o!V!7D<9`+hL!lzs=L%IE#tMlkaEn zJ%iMUcpQaiRu>1@sjnvPenr^s!TGF8BNm7cP3t#~e{o;CyOgPS7V(%Zk)RpGAem_t z1kSL0BdGb8{7{P8!Q#>{3PHzq;&7ZYM0z3$GI&mBwi*rl*=y1*Vrt3c$uqUFeobwt zmHp|!P?VrW$}u;MvKRI$kv>*=F=F7*$3THCu+JNe#)XH5`{7v_nmB%d@x?De4X|f& z2*DNI4zFx9_duv&MO6q9UsH*uu;IRH*KKD3koZv0X8D?gmMo0B=i_U@Y!;%*5(tu- zsyJ22y^7Q(i;osO4TKKRJ2~hXmEQ`Q<>PR>ob1MUg&{ZPKEMJ0w2y$lvROcsQ>`qt zDtQyKQQ#c$=Kimls`O|tcJ)*4OZG@0x0_titsu>cNoJ)`auCpNy_&2tdlhZEB3G63 zZmAca-0Ulb#tX;?bwkXV%2YMi>uMq`q&t~7A6Ntzv_o<5p~_uAURSgXBxOnXk9s_Q zP##otP|>l_tiAde8T||$Cp_fK&==)aX37nY~SiVB3a$JwTtiB*UQ|^{q z1igXM@GFv+5)bRg@U5|jvk&JO&{PkYtefFJnSK}dro*bQO1Zb+=TMn&OKN6N_0O~MmJv$4A%O*{zx*)hCG^4N}_?0?~XINp8Cv@i? zx&!a|1{KjUedwMXKu@$2hzJ$s19GWoN3n<6Rf~%k&~rK02`R>-A-(~|&fm*2PtCNH6G&w)1y*XS74!xRCG116XDPRyv_7IY>!7$+`j#l1YTh zt*!`1UclWny&)qsddC%f5E_kx=V`78#zNuY4RXe@!#+q-t>zhG|G52f2NIq?2`Ja% zmqfP9-8^bj+W7}uLr`3Q!S0txYuW@ z*ZepAp6s=LGr^8iRrr+<#dUW@<_mXdiOL(+%!w4oDk6jhqnJ3~J>lPwtsZ;E<`6xp z&Mg;{3@45N!`QKfGqh{fSQ%EN_BofSbRNzP->lINwmeX(?hU_P| zE5pyqz!9K<0k#(&%BYH%y$8V=-L5kQx$itp@PFQ;D5Qc`(8Ezu;h03BQ%DC8H$F zQia#*ZU-)v8j4S#25|Qz^}$lU#(N`=V3r@wB0E@}9WphNDvG#gsd&$cddB7rI(&C} zfIgP6*ralFJmHG5x`__U#C$4rotU%?b9$NUj=cz?@b}$Zcizkpguf@O(iePLCMR1p z`j3!a3z^TYWD>$h4uZec6^mN9fJ)?F!bjCP^CK251NHEGkx6I?!ert~UWMcdw92pc zGZaN(sG8b}{fp$npCqWc{Vj+-^aTW(WI9;1ZN@^VB5f1__+EfTvxO78B2mEyMWW%o zSO*}5f^W#<)SWcN?9k0f_`R|>q^Wjy0Q@+w^uk*tUPq92rPYts|C1s$p_HTO`EVud+sU5FwRQ<(rn zZKzs<@1fG?VH|g%Zbzm2Q{u18N*}Wj~4xRLHw6d_1duBW9hZMAO8*8li2sff} zG+Y^|o|HKnTUvAh2*@E2p}#~0W;shKJKPv&Dm=L&PcWeyqhGor5Aoo)eC)?uR2Cw{ zRrFjw;3nWJkF*Cbbk-8)i=s%ZfVhZ#%&yNiyM3#}=m`k0$zJKES7)ANv-t<3)sX4^Xg0ZUjfr=J(qA2e*?Yr zOs{OYu%W~*(oEGA87TEw59y@tiBrE7p90^NsvAFp02061MZ11PV>?Vxm8Y?Zh*mQq z<$j(kIPx^Mj~PjZ&wMO1d}#r;9ATKD)#3?wJ>+O?Lk^}Dk6^c_rvEmcHG0T8v!kE` ziy?>hh-s|_^G8L-koSl{YQ$pgC}TWzM!KzI^Q|B;4K@JXLbZ@Agqw2zVH*dByMsAb z(B3{$)w+cp{F>U_9LFzc_ZYVWMSs9=gYN4ZMG=0sG+Y|za3oI5B|LC5FFsX6(V zE01b7x#((KeUI1CGI&+p0I9rOzOijT>q=612) zuY8F$+TIYhlcDLyHO#wd82cHL6T?s;voLpkrOJ5$7@;CD^(YE;DEcPJ;RE&gv+3-w zGPCJmI100AHrrU)Qp38`5tQ0>HdRWAAJc{~rYw{X^tBlls$9pG?)G0VqR(8%s7UoI z-2I^|BT>O*w$$oT)|{pA4lORy{AMrR%v4=$<57^qZGSD?d~SHC)7v{P`qVv_JrH9=k85TV6w+U~DDkit6bZ4)I|@OAnpU^Mnj-PlF!;pc?IQ^RbJrNxOKWRlfa zBAtieS{K_)woWxK4(yy0V@~icU)`>=)YANR%L#3Vdj;HdjJI1Ii-ngP#$>SA%B=xpcbL%_@5-JXhw>^d|(I zFj^!o7gwAGUSsU;RE$WR1|MWGq*uQzYJSd(z2rg}-RJ`P3KpN&-CvJ6LU>kN%or$7_p;fT67m~31@m1Y?5gR?!h}}0- zk;zcSdf~U<<+gu&LbYlhfi2x*ur2HHN5wrAKd7pfB|lhIyw55fb|HD74Idzas}oU=<~HrgYdPt@T4(i|>5` z`sIFt)^jgHlI1!h~4`pKNy`RV0K9Ti9cfPNH zM)3dc2LTZkNm?K)q79^Ys$X-3-{Qd^XZYo(9=Z}VE#Bja*O#g1&iVlbQ)d62y^6*4 zlRQhA2-w0t=5L5NHnGpu>nHz*y*H1Ks>mAtJ3vENLZcGJg|XE{76}9uC6Q{^t4gNZFI(&VO+*_6gM_e0fB%kBCfdLe%rVpItr-t`#n{4 zyE_f|%=7-<_w)PXeb7$bTUF=OsZ*y;ojSE#{&w`NNhPQVKJz(2)aWS+?qN9WD@ldo zKwjGe<0sg(Tk?eR7eM<`c@#|%Nlp1eO%j`EU4}wU_}n|B4eT1$Ymr&!G~=Q2E~;u; zy{Mu37)C?RNsAngQd}<6@wQCHmjxH6CA)6S*UXXvBdK#g=K$oYrUz*Hikt{um`{1a z<2Wp7=}0=nN+l9a_Yuf#oPUwmYl8Ad_X|jf_eb`Lwu~IWnelW%utUp>)SP}&Y|`@7mILm3Ue&)U3Bo$x0;Hh$|F)8@u=IaF%t}uR%a4MygN$~}tCNX9f=Q@+ZZ(ssqHx}GRiDY2< zZ`*T^&^syNQA&_W0ir-CdhKgAui9K@Lm88TiJ#hAclyH#2(ABG!PWz->aT&{u^tCB z{4Itwo39;+ykd-YE47RVe{@XI?i^RsN@XQCEtkTh2KBJ8!rmlxkC8P|a6d|Z^z^9i z73V2E=V}^;BzhMAKBb+1p%_F0AFgc}?w3v!r7jT3xvV4o^e4X<@fzPY@dQx=oD zak4R$?BUCZL)nN*4_9N!^DKmhXXs~PV|XIZP#Dk@u4HLLRYn{s`;)1PoE9g&x8YBG z`a7f>eHi{XH6DSrQPNzDmb)IL>{MPx0erH{^=!}MnyLF<#8CEElZZgl_J#-xhsp$VHO;3=1r5(gZ^Qjm$y=Nw z^^J>_#1{lrZ{%F5Frn*5s!U;5OyHl_9KVN!5z`_fCcaMO-?dxv+osN5UGu-#87&Wa zw5db;N5cPVllvB(drma>G30LD&T5V~FQ^VQSV=--6#dPgDQ0yO#;X4CaYv@4A(fSl zIbMiHec#Ssk$+hN2%krZv{LwwkSVQXW)bIV1vyrVHp)ROmt|noDClKu3j7ebmZs&P zlz%bg;g3nN_X8$;ze;^amUXk1{N(~fc)tqUZax1$_x%xdtSi**Z+zP~P2H@eKSDC$ zVPyy1jp#X^>_un|P%SpPg zM+;B&b;91VN#*wSz-HU(m&x8G2W0QH>~?ltC#E9Cf3X^+tW#c7?%DiquB9(h4LabL zFDjXu{IkpfMg8fFOFPi;W%=yaA_^4Ln2YifHeh!gX6>FU@-K&O^AX&@+t_WpDR>rf zdt@}pFZN;|i%Cput=5`&;FivzbQErfwBW{ukEiRsf{PEh)s^UX>hWds0VA9&L8vXH z*7wYqprhEj(62U5F4-h)k+6Lum+Jm$F%+Z1{b}reUzAKiroio z?f)IzJ4%!KAiLO&8DNbTB4wjDH>1-M5%9RKyPallh+z9HhhW(b(s&){KyZvkPzi!K zHLLcES{=X?mgPn0#m&!FnPE=Xb-To3YEJEg@?h2z-Du06@NRriggxP6&|3Gi+`v~{ z^3`#+R6z9E$89_nB>2(=|}(M z@ZZpS%izad@WWiMlq-T%$OV?JRe5P0@C<||6SsD8A?e~eo76JL5vUxehGXa4l) zIRGy6Wk-)b2f$QOodcLoD7o+#t8)Oggl^s!5cZ|n)H#6g34(VSd|=OQh`c(NKv z!WSWC_WTEN%jbIkl=8QkU8z0)`bwqnX(|)2*9j#Ga7%8oBh1_lk%zC%laj2{FT|9Q zgC5cOl5JP-cGorj0L7};e2k<)+4~y72oN07 zYhK|1LHJEfrD*v8oTRl}yI6_OV&g}we~=mB3BLrRy`ifnlQr_GBJL+VM8-h0t{@j% znDV4o%R2Fi2vXB}n)%tk3P+l{Q`>NvE;3K|59MD&=xWTiBTgbhb!K9l zKEbY13m>v9#FYdcL<4orAiUfySnj!CT~ry@GLpdxr6_hk!%jWupJ&L z?r}(hiXDN^8rHYt8=6U?|ELz`M!2Jvj!8z>uQQJKCNd#bN-34$NXgWnDcz)QOWJ~_}?JI&4F4&Uq=|VG%Pdip}o*=u?9i6u1CONm{wrjT~w>_DPJ8a4A z*u|T56{7;TLUSwm$g4QvyU#jl6ykXxyoZXzoZCKD%=tThaho}(aoANer;^4~3Z|DX z49(etr$UI7QA^CtdE3$GTf)T}Teik_aU8ZcIKiQ@od`DgOH-*Y4V|<@K_06iU;aqZ zaa2bxfXK9E?_$(<~?+@pEu{U@H zqvVL(u-wh{+#h8)cCFeB(iB~j$smol&#VKgvA+&njrzhd%>5X_BDeJz>PNY&HoF>& zXe_3oj53^!Bg+=df}o_^qq1>AaZ@z@tD>MK70e7CK!hWyxv%R{nau}|P{7^9y}M$* zdIcx@f-1oi?g^=(A_n`HtgN_l-=L;;xso@PG}VI$gAIG=ARMVv zjHSt`q2;1tIQ`t}TgK1bD&w%6M`HMJHGI+%_ZcHGAm672u~XkTH!SDHHv zF6g(1vjE~(z2<6kJI`3F!511fB##N5)FW%dnBYlA)qNA5A-F-?t13jV2a-IsvNItMhuj)5a! z-8mqE4|nOj;#acGN0*d#2Q@AXUOv<|?ZZzaES^wua7;4yB0GMe_P>O0Cr*uGVe1El z?Wqq`Eiw{H*0or*54_KjaWzfo2){+!;RM=FpazX_FS?LDpKJR)fUN*T=R4dpOnbBM z_%$Xl&8dGusPIp4=dks;2Osny7YDzHLngpN{VnE)Ty%Hm z^<{Vm`9yJO$jtz;S06vCvN0%teKS&^+&IiuefDh&QEd!=@~=6DnsKE(`#brjKz9HN zf?uv|r%FDEpl^M|DuPEVs}2I;oChk%ZMqolaU=3Mh2+DO)q}XOs9guBPdSlz?xPx` zyRA4LHLF7@PD$Z&-GN11T)gihnRpHv{HnxpCGw}d%fA-qo94;-^&aUVDc5e`ob=#{ z^rVcvrL>IN6;!DNGaPv{T*4C!YuMM(b)5t5!arBzH^R~bF4whJ6GQd-Baz`p1qOVZ z6idz(zf$lcr68?SIoGb6IFxc3<+E>srdJ=I5k5n~;2l=R1k|y&L=p9Zh- zyh|5xHKu8hg0>*HXpoi!kiRRC!5ZX6662)m_Zp=8?zYu0S0GnwklWjWEY%=A5FD~anUU>9SwHzZ6@*5*TR&YUuB1rnZ7*t7^=A|i zrsH<@;I4M`xOXS>S5Y0pZ}e_*nAD#zfm1$TXO>#ziZ!>a&^vb#Wqt4+`XzP63$h;5 zB!x1%V2DRj-zRGDHqrEb+Dj4K&LY>o$i(VLzNDnaLG>r#V&20?xL)7QoTq7{pN~(c zEZ4;cp(gHjDCR#7YYqi6e?s-@L*QR;Q$rj(gFf8e||BSjcUM)i( zPS{B5HY%^QmvbgrDNlshKS&WNPLXZUPP(h{*RDp9V>+n8vhlB)KdUr>))%pn!=nro z>*YO+^qUyi?fE?8p*=JvjE1tM!HkBZ00@7LaU}P}3^|HAh4&H#Y0bK%tED7{8hFYO zWzD1%#*f0M_4vVKf&JK!vqTna{qmifMH+Z;9GTVt0c}p1Kql1tXs*@wtp1f&@vM31 z!3Q72-@!>y*R{ilp;0_Pee~Lw%^k*ivex_iuOZIS+I8>_5`OxQ30bd(4egjPJi3A8 z`BpSO(9y#TwsmD*(AmQHk|#DD#B|Zb-1B*C3by=P8DsAvliK0l;{1~uk5~leGgePz zAvZF{I3LTCPF0M!V`sph?^@u`mttn(8oXAo7C5KEG}}X}#y7-;`)c{SRgILLJ;9dw zV+)&~S}t5%uiB(A_!Dh{xx7_D;G;CAN|R&~Yb7uE%sm8=R43@g5Xit%_ON})(-7$r zSPf=|-iCcH*L9rjQlsy6?3;F|PxRgTXCOCx)S>fhdCi^`!IX{c`GC7UUDt7=8;8UA zbg=U>RQH&&ZcB@jwt6DFt>+f1Mqlur>V82SE!rX`zp+lNs&AMsD%VGNnx6Sw@+R4u zokawm#RrlKU8A(Mp945q}}2?Nic=i0w9XQFb!T^sbM9sVXsoKn4uc}b3}5B z^F1OR;YGl!z7h_z?v$5xRfqbndBLkXwB$ps2*1{TO4Pkvn-ba1mwb~&P!X!m^T!@4 zoVxiBC!F_#Fp@fJiwI|+XH+oPg=gRtQuA9%PDV`g@P&*g4omHKR3m;gITcmlYMMq1 zlh`96(Ww%1b@MOVrFi(=$M7L0l3E(A*IUtiFEGae%Te)ITuql~++Ewojv%)60dlY2 z8Ap(-DWV!Ibw%6QFtJLe02myP2nDfS6og$$dP3q8DsdQvg|iSGz#omr4EXUX#}~TT zdlM3W86mh|kkXkPtNZKENGQRh;DtvZPb@x7C7ve5uQl)wBoxtEWqDbbe^)}{SE~FK zQvMYgCr+HGE>?ohtE7fzLMZ$0yJ~S7rHJ!>1)Aj#r7>1pWZ>gZ+@2n~|A8b7frWQb|qHssB>27saLiBB|p0r`$0rH6t$dAxV`jFr>~^ zsjj%x)7h6AzE7u)Q>ouQ7pu`50vpt+LsaVPajCrp_HvzioJxHvF7-@FEz+s`RgL}> zmpV#P2kF%QuSN5&r;5~bb_nK^ z<5Fiy>MEW3xJpfmOI;zUcj(juuLa0 z`s|>&N@*;++aV=i6?RJ;x(5W^0MKDB+=4R2E=U27J*HX7pa?HRwe`^(+l;H@kSVwX1UCMXDTz$}=*kB|da?YyhygTPglGq}ws6AJL!uCAYvnUTpq z-uk+3*~mq8uEu5tZ*SQiCh zN~uo+rSVbV1$V2~`-zPhX8NQG>7xp1l3IkG5&Xdg1JvCy$yBBikGH9UIKw<7#}5sVH^L9lWb0{|DgN|GWiY+~&UZkOv+$sobwKzW`ua_&|oo=BoTY0EP4EkX{9e&lM&#|?;-Q`mi(Ub#_df# zRa20Oog%5bQQBrd2KC&UrR?_tzK7Y(vt)k+fcePwRc<)4k(_IfA_j{kl6p0=fLK3A zBxw#cRzkCpZRz#aMZ0D6hx*xI4dwp;1DirLZ9#L9oDBabpw{pE3BC>1-`Po_Sh9)3 z!m5l7Ry}FL1Gz}Ixx?au&@C;ElEj366ux8YBGTEqbqPKZu41y@<5i+}N;HS-IwL>v zN4r^XVvZY0O@kUa-W?WF8uoQsgOeJT<#c|C;#{LyFaF${we9L4BRi+V-miwp9|5*!TCN~yOJOAh}E*{TL7KzUKq zr>@44kQUC=eP_sQ=?0>yQXX8bn0+&SM>Sz=N9^toWK{`P_ZbSSC;T953vNs$zEfcR zP?^~IUU)@!zVOv#iRyd$={Cu#%j&*HmDT6aviy`4o)3juxb-DD*8m-gL2pGnAQoW; zyaYBzbs_?l2F$xGn;$ynHVlKqm zq);-+$GoAVR?xOlfailNzCcisb* zHpRjPR?WI&>)~?$?%?&Y?{mt#x-8e+PjwSN zjZ{GLwT+AjC8dl0_V>oC7joVr5zVr@D;M8MYLmR;1L2A)fsOH> z>q`}eA+O64N~j}uBXHqozouP&mue~Qaq79Hp*1P+Bc|ewLI((@Tox|pQQhactF>M5 z`Q~xl7&YuoYP3D@UF*g;{2}LTRxlx}H+NP=>rXk`jZ?of5D|lHEw^ua662=QqSi#vyZfXmLJ&Zjz&O2gmvr=QBJ><4~iGJd(9F zU*5RFHssu+ANNI4UlBCTDX(HTMpF0l5=njWG2GOGgn^U$R*19QrvWOqT+n%ykkFiu zC_0bkQF*FV1B>)E9BA+7)_eakYQ;lIXjJ|!IZ+#nUuMgzvpqAChN12J9b0545WeMh z>~}nn9%ZCT*4ycxxe* zK{#)sm_ll;Kai)#=kwhph1j5LjaQlAN$_2+!?Na_%otxw>av9KNv^v!8fdb&EMv(K z+Fiw3Np%h&4%^8 zvc3#(F8Up759?>DJ7ZpcB6yms=5Uq&XYJV1;KD( z`;>L$_N>koG+-R6MlSRYfWY-_aQ;cOwAw1oMPcuVoBFI6@PRx{xNa5btzR8w+uZ@TklvVz&btbRN_#V(iVX>Uj zP#5t}5A{ACXvUvZZ}6+=TvM!p#Sn|K`Vsw+#FHi0;;|^IZjkS=8KO|YyZ2aY;S#Qc zW0<|7LQj&Q-zIb%VDe8y$Bi0#S~L<$ydT5qzD`%)#NV!0pPm;wQQd(dYlL~BaUIxj z>S`LQUM@<`=Mcw<=!|Y$@FYHfrjtnsUDN>wKvPe79G9$i zr9Vl>V{7U5f@g&YVI6>>_O6xVkdWPlNgp*F=usGA?uu8@;kvdRe;W?CU5!_$hg?_F zWjqx0Td(fBV;9kSZ+n)BWyQqHJlmQemai_d?w=v&yJsSfy9WOVkvBXApCO>0hTNh=HWN^Dn%IdZ3lxmk-7pi3=X^M0O%s zuEwJw2cZj)tB47yI%QGBN=*kow(&;m15y30cpyy;2`lK4%wD#un(MOw>~^PkSnyH% zB&kO;b|N5k@2L-QaiMUa(zWua!r-?B!5sxlUJ%AL?kI41cX<14ys)`LJH1w<_O=2& z2I%m=Da^Gh4hA6h$F>2I5yJ*LL4ejvy>ZLQ#G)miIUw@&N8FkrgQuwT-UJjfd$m!# zMb7Y5f}(xzG8PoUG+qq!&na9BI!6`CjJ#&J_iMPh@XKt$oNdHqRF|s3y zGuM%GD{y{a&TRso3%Kyby4rxd8kh1as%W7~5OUPe5S5Rd-U8o}bG-z=i;lz3D}AkL z84NOOr%XF^RcsoMkJ0FAnv7(`!Tfr>tYU{bei2cdDHRWNx+3s>o&FJRrehT+TXgJ; zB0=W7byWMaf3*`;32qKKmk(0@h;(n$*M2u`J(THAi}PAyVY|axNE1nwd)l>eYt^aj zU&hCUnIa*nb>v?odK^Ea+`r1&eegrp+t;{-Wx=-!`hBH#M7-5Ha7(AodBK?-$6;qEQmycdsTlg zU@L8N%8!&CNqzf%439~|I4QFAQyITyI^gzVW&~dhwF_=o!jZ#>d&&M0BSyLPc_SsN zuIn0sP~z%p5a*5(S^t^ybCsz2`zbLE6 z#*pAtGVuXgrq4h)21l{MWhin_Q6FDfOdf}k=O!MFJo_KkvfN_J$#=)ug|8x);CWcf z@%Gjw%YGc*f%8*+sAYIAf0ikEb~XBVRx-`v36Hj1|I?uIdqLxBEG5avby%E=*hhAu zSDKuG8{?#MCXxE{KGE}jaWYvTsb95~$RQH%Cb;bKDEm2TkJXwbVpeHozYqd)^{?CoWcRX zU4i$&tLHx z<|&W`v0|h8lkX?=@CJ)}SnZFcHq9x8D(7f&wsO^}eAATAd88goZ0mc`{v=jG<25j% z&dppW&^_e*HA7SgU(zNrrY7K5$oa8JLN_}?&Yir`aRTq+gILcq6#9?yhA!!0U6U&8 z+(nn*qe#su&r4#9^L7IH*W$d*JVjEI?}3^-G`~X5Ylw#d$EspmoHe`(i0*^Tms1uJ z6G^QXpk2$Xhs5i53Bs-6t-r{-%>K2&dCNS*_=L&e^-HpfF;o5RzJGr3`idnBdv$Gx zy8=(clB}Xj{hgUcY53Mxge!6Oy@uy1f3ES*OOpHiJ5t4de4D}B+$~txT)4GwUMRO) zK^C{5ZJ3|j-ivwtLS0wv=)Q$nTLYgAUjKc(Kf}l)lWA+)F;c62$@5S0hEmVQv&B@p zVo5gSoFMj-=n)Yw|4N z56Ay{bW|C1`Msp2r+gvh&$|U2E_UaLBFJth8a?^g=zQH=#lu0Wk(${+e^uZ5La4U5@udO`2 zV@-+@c+s%Jq<2C~mQgYk@8UBWi1zrS>~8l$wA+n;0g0ldJnlH6pYdf!X{*T7 zM*7~4z$bAnV9Qfs(%XS!T0ch^bp7PBCe){A$jdY-&9`7bH)ADmwC(H z^aTIyN&2Cn`J~rO|KjSq;FnjQQy6MLc$;W4PjE+G^GVsBeqUyB`eTR3HRg3T>=u^o z$l5vvsG`s@MZxxkLH=$Jye@a($aE(^>$AX0Z4`Q@J?{zr(t54UFRi~a84PdQCcVw} zZ}9y9@pLFB2hM9!@M1_98fq==LC)sX4O=AePM70-O)j1p?t5C7t3-+2gRjGC?2hp; zNyQaUU&EeJ=F#LuFX47Z9oolhj2!_TD+hxrlySEN!Ryn6gWljRX}1%u&EZc`a7!Wa z_w$$+x+iS~Ar2YF_b_)J@iZ*xtOwQ_OUY{Z#~a0mVZ{#QE?x3?`+X~po6Mrn`9*Tu z_#To9nlE#EosaBmI(rDO1qt;dW1iIeJqp)k>17`kFN1~DN1*;Khu4u^%Umr|78 z{XjmZzLjTh7H7m|4n>OwHhLOD9amA3uL$ev3n^U%I7Jsb8QSJfg$`_)!`d2 zA0wwO1xZ`@$Xzm{&LS^ISu-8}x=_k5gW$)uKxRS1)jb@p#u-$p#kq?}`4>mFK4_%q z3s0fsxFkOP(wwqslU<`r(Uz?%YdF=btett6dmGj%k#P9AT&ht$ z1~b`XkBNoh%q$oO(ZpWC9!%22?MrKi z%-jE=GU2?(E^;+8hZSQ9pXyW1vgc|(6)6nC3X!WO76Lis)H)FKJN(!Lu_kkYb_5j^ zv{!)EFiR#OEzU;(kbgEnL&n|2@cn>nHsw+L>TD9jeRzWVy~4jU4?*WbvZ>Q@GVy6* z`)34q9GS{cSN4_-M;yfEP z^3UJ1#W_{*^N)2O^OP5QII1i}X?PkwYv*bBG%0)yFW8^X?i+=|uhFx(=>`DhY8nY@ z5s^l|9Zw~ObSKu+a1g>Drl`D7&VFv=MiU2FmWx; z%RnOkvRZ>5xSEIY!soaPLua>m7N4I{7#y;QT&||G!Opc5S0^b1DoJWB|JVre0AvK&-}MnSQO!`2z7f7YMjf)L6T zusNULP4)(JI#HzZbs@Mvvt2_3w-8|g`G*ZZXCpJ85z8T0&^G)GO=!oc++Y-}(%vGz z79&-N)o7D62Y4P_`M98kn>h>GmK|#4m$rJ#oYLSM5kWEGwqtI zNOYF-hT2slrKlBqr0n(_X2c{StacpNum!2bIh6boEo!!LGzj(3bQ0|#Wd}MnI8P!= zQYc0Cr!XF$Xu}HT?uhK(XK3Dct%q=w1bcto*T(QJ)YE(9zHUJqSKDjk^}Mq`bTuk( zFd9KD{vi(ns&-7MuGD%%u=n*6Q^7cauJc|8l+X!L{^23#Qqth}5Ta?H5zru3kaI54 zxYdI>Qw4S+H0aLE$8FLJh$;yF814(kWs4WI%MLk*6Xk!-Fm(tot{ZQl5ZL+MI)b1x zmAH`eWd34)98&dFy6Unk-sVcM_m_P%H=7=ZhkDR@Me1<7H`IY|8aOwS{u{DqFSc9n z%3kBe)WBPYi>N0)xzthDGHj*L8$&~C!IIZJf_bTPB&2f4X&y14FC$PIJC{OLx6Wf* zR1q7W^ZI?>Z%8r8;dGMVOFOs$Uj|FmG5E^ctOquHHI!)w)KGU2N6Gr0Zh>VrRC!rr z_8RjyhFlg11wxuiEreT}?c8nBoze7r?R3_qmV9MNynIAm7XFxp%5H&3s^?~L%|!fF ztaN3{Rmf_4M)26+$PQw9dnB7XlG=rA-ZjzBy|$Ni;@Ib4nf04bzXp%7KmBTd^%e13 zvPsHj4c4}|^nI!=BRdf7X#LZ&=zbO{%oId+{ay%;aJT5yxKT%yE-#g0R)FD{-vPeeTHX`)?uZ!6dJUse415aJJt%W{g$k@v|i87f;))_SHMM?pWxq@*9&;H zP6lobenN-UL|%31$-0?1>rEk}IrUq?q-JcE^$~F#oOxVSQ2bP)gP57<}UohcX6Fz9dKb!CmCR}8~*(SWygcq7H+l2j1c!CMr znQ-roy8Mq#xWj}SP58J8?=s;ZOt{E|vrTxZ35T2TOcS1G-J`>0Lb)hvdIGv}X+I?p^C z2>avWirAENreB3>6H*$GYO&8+BPNY4-_}D+Ej;TO4;-xxbdIl9fulKPGt(RH-?V-u zHRyb(7bD6HMwABUF&&wmg(vdtSx4y(bvYhzPXf0VikTWUlbdv=MtthaJk5fH8K~@Vp+S#6*432DYkl;1`1M4qx*h#(?qvvt{WAQLhBNnud?ZlKciyN_0 zc;FJHPQ&`U8f(EJ{(?R|q@lMpyuc3d{k9Xrc1l>EQ!TMIZ%+MWP<@McD0L~%*q`z@)z9Ce z<^@Tnei}j;@H8$0>L=?4h7ea{L|2HLs~9L7w&FFCb=bxG`}WJOub|> z!*>*QedI;e!%6;-^JgTts zyBjz@I~DG#(mKhsz#BeD*My##QiQ-eZ)GD^*pk@hlwu&cCBfPt6V>LFvAkMO@r;Ln z-msw?0xvGA_8@G?`MD?b2Rh{ibN2E?7AN zN$p%W9xr+587j}C^P#cf7jA*N4D1lrolJ_Ym&$v?f?Rw+R#(BABJ+OhbRjL|{31!% z?9F5Y_)u&1lTr{DK_Yady(no73q(GCp>0@H?7>$NbB_ka*Mg#z`7+t=A=}^`By3bj#r6!q(FI`JF z5&@2BC@Je|4SoUOxD}3r)}hu8&VNJa((`pyPZK)1=acN1*#E#OOwL|bp@wuCNIV_6 zy%hNKPiydxG&|NxT~1b+Q{JY(%G$?@n{}4uWRV*M>B!pD)NfTU5qqV%uzChcJ}Zi{n_a+x8!Y0}Bq(2Z}# zx0CJdkbsj|Yd6x0Ol2gt!O=n7oVi|CYs#CDD zjRl6c!SWc8;c|^-tzc;f79o5E85`I8*Zt4f2T$Y}b53t{ruk#MyIvYU|axo_|nqtNbDYUBdJ_*0edPyk;kW82WkXg928>ap5V#) z(RIz)s4hBD2bKruTe>H<*H2t^e7>ZLU6I;JNt$I*8E1mHLrLP7J{MWpNzYyivoU-P0s9d$6hilcW zqpd0cVNiym-1La`tAw}29w)I&&!et(yQBE6*SJ($I*e2EU@PdX4234;^IvuAJiF{5 zmda149t1%0-m7qE(RZzUQcHec+7Noa1A#|Y2{&4wa{@T7^%enb%R1jIxmLc)Fsutc zhUS#3`cUelWQWXJO0@~JzNcs@@f5m&wuP3ERr4z|%CCO`*@n@ZG^+G?RFmODc!N^S zS~0FgKv=iDm+0-7C$KskLGwjY&&P)so{R!k><-@rqxI8nk|ofjpQsO`U*mah_&!hMdRq6h2Sd6Lu{nlli`% z*mKr;`es8;l4N!*osFP1#)R{}D))h>%Tb%ckL=^V|{f(#adQtezDc__4&<}tu#!SUr6}2V*h!RC7q3A5> zE`8F;eqfJkw5NX-qAhe=wCT3uotLKT1IaY&9pv~iw;fmLok}jihYI-98vIHUqkxaH zLxuRCfR77 ztb1z}rtX3n(i-0o()9RugFH5;vG|Yuc;2kB6x>t z-8W8!t!Il-!1p+i*x+7I@JH*7Z)uE`h@f;<^?g3+x#1I~)k4ns;7#CR6E9#Q=HM!jo3+T6B+>ki7+*(ICy!PPbk&#qNZrhQ3dMHVVTcCc3{4{aBo zQ1Sl&S;cvCdthQvnrl^~5m#KET`JD=9PMh_E>uuEFHIN%k0|~I!M9{xnnid*l7GHf z)zUFUJ-=G2m=bJ7ltqU)tj{>xFAcw*7tiXI#H~%bj`$onpsb^%r$x&MOlaH{xLEvI zQ=zUs)Nx0tN&Bgs zAbcG5p#B8mss)mF;iGDEtX*-k+(?#+EWDL`3nNmYrhvbKPIK)Op2C~?Ln~&TN*(Ut zJ_Fk5Qh-!%xEMpsv?AuBSc$Y`qnwOXf_M@vh#&qtf+PHp7E@48LB6&2#6B{kO${Zq z(Vo{55nhSL73HE@Rw82lG&IFlUl+3w{JQ$MdbD1jQB^J4CO{ zPoVyFH`Kppr=FaU`m!|kvvz8)gwzEByWCD)kdV3r^CNtXoytoauH6h9!{wy9R!%-n zSEVA#^0%$2uq%8N$=2Q~#msR;s0vWuHi-5jpy3mBF_=qF(bm##7|_pK$7&$v8)i?@ zuV2!`M}om>Z{uS|+y>uN5QJaELT5ipC(;;$L(bQD3ZI1*S0waE06AakayuX@HBmlF z-J~wEQL4%jf>fiRKJrEH4XUE54{^#lcMGl~RfAe4Rhi&D?&OFOJq#PlAqDfCZ zLi#+D-unpYRVMw^Bc%IG`iF05`jX7M9psybeg-}ImiA z=_8H+Uuod?90A@=FFFEzsezyTU!+exLi#uZ|L-G|?>FgXM}VJT(%Zjzc>Z5%(q|t5 zKF_4rn{@LU4aSW_xv=xuSQFC|-|c+=FNYnd{QBJC|1Yzk zP2G>;t>u6C5#@^$+|q{`~@n)&ta3DxDkippxA zJ?_Nk`M>#mB)XzyuG9M4eoxeYiSUV)Y-a&KE^;1mE5mlx2^}fV$ zc0zsWOkcLUydsbh@K;v3r_|K?D{HFjr@03X9N5L}&Y0!S$e87;s_oplb8%f|wcqWZ zRax(r8221sy+BK@iR7B+tE&ezE~C$F;@s7NIWv59l5?KUIisfD7tKj7d3TrlW&~!s z>;0vE-yC1Hzh3fJk-v%xkhze+T^6XTBduzoyVUP5Et};lcjt|q;4UkzEuB#%DCSj` z`Rb!)Fc^GbDECQTaOA0n{}c<*`B7+)RFy7t*Zaz9s>|y;kFT8LbNg%D^GhrJ?is#{ znmV7m&R0|GtFEk`=`J;txJxVGJugze)TdnG6C&Ni=J`-2b?0XftF5ak50v@OpEAJ2 zmCzuuc=a}|3*>hmSL-XQtXSxts6Yo5Ye08FUf=qD?wSh43(W&5td_!ROZ~Il!)65P zGiqz<`~#(3-2>(E{3tS&g{lZ6W58tqmsQMk52L;nl`~7K>&}mr@1Ny!k5KV}x>Avt zLkq729)YQF50k%#f=g)y)o`bx6lTOEWE^nyzPifND)%rQmel(Zy_v$EHW7#6%Qy`< zP5~TBQz^JhtNiX^{7I;dr^;XN^ZTXo;G@*94S|aLGZwn5OKJ9+I=4J(p;jFhX8XbI zuPd#tukh7n)K@N|f#q+E&4N?INC`6*`hE58T7+Z5xZ&>c22fgU0*C^&RW+sM?qL;` zRbc2m*2halW!;?lrHENYUCkU@zTj<*$tJLuMqv#Js+hJk_!b~UemagRMA2GVttk>D zc_3kwt8PQWq`FE!MYo|rljl}6!~|z7;B`KjiM$rn*9Uy6hGQkhU0*q~y0ofFak-ji zpYQ7<6{@VRtfwnW;q_8@MWEi7QCeOOntB>bKTwPD?!1b?IG=k?O}TG?yWVsLe`(!J zaNGImimJ8hO6P-Fl!9Fs+D+GapnG%;0JXJMm1RnA*f1Ksg6caEGWtb41!`ahF%ltn}BDUn*J?sHP#M{SKdh*2H;L zzWnU+?Aq+I?8@xY>~Y!t>gO@_@ z7?fI3&E++8*Rp|K;!zCF1jXQU+~aHNXcG6tnyPYNwSpPv_f?cek#-p`qXuejW?ktV zH;*Ihd_MQMnhL)XXene?X}#MseB7AA3FGq%FL93^WpiMyRL+qCg(H#)Km`{aG2+TBlgy%p%vh3M zZc`&FNA!IxZIQ38#(@>!s{_3hUsh2V9D=B- zuRA_nU~YikDs|UI>3HhVmhSnLG^K%&&INvDEeW7f#A=*_w=qmgW2@+RlSMR0{@Af& z#tv|o(FaC|5O<*3@jd;FJp-g*6y;b|z&j zjm;mIKVIe+^6&pAxp&0NyAnYq4@%||CG$U!NQYybF)gq%e09|rxNbYP;SZ~sAN{| zDW6T;AqddJf+IcJ(c`t28uiob8KmnN*wNN7AYVFkwtJ+Q5%KCQrWxj_5yMDu->ANm zF(vxa&v0D#NXLZg`arFWWzZ)~fkgq`{B1j@8murb7?Ea_mR&Bdbw&*en1E<4a7f=Z z29Lur`qfBe5I@ID|GnR-z^r>k!~BErHuG%bS(xx{$4fZKq;)6E=RG^2?3B27XWX;E z-V{e`6VH|AeIRM!9s2jT*CLSz&2Mttv&6~!(fnkB>M#N(q0BEGGLLkaHqZ^`kg1PD zPjJjc#u4jnj2v`CB?mk@^w4SSD~D}VIu!Gz_ry$A)0hNeEJ=4PFZGvdV?rd~NDJ** zJi;+SnfhAN+~onKVzmwD=rR%;z*jChyUbTP4{<3)2>i^9uv^kAjm0jdO{k7q_4d$i zPcbwuVB@9@hoP%@gveKnI!B%@M5+(iltrtp>v-6-_yN#ep{k&i6Cg_Q_f5yHjvo`F z5q9@B+z<^V+%p8Md?vimwRZEISAL`L9hLL(!`)u+Y1=aJg z(aLF|`m(ypT0gy5NsZA48q3OC19hchHdD(rugIBs{7C9b?31V9BfUI>QDGoI zGCPcICzwX636kjNDN)#IGE(Ho>j1%veCMPG7^W&_s*tv*P!H0Vb52dKKNZ8Q%CDki zwr-+y?^Q2RDU<$LR~M-Dn`xys^i5rq;G~zEiMnbe`zYONu?C@*PElAq-PFYfO{?4?y441w|72u60xq8{AP?6ID0Ox;Rl#>ChE#Ki6V}+gga^v z*^sq0s*{OQ(nwU^(KXc>vB6V~_w+QeL&VIrxnuViqfHaDiHt<&^}5Dw^w?qZ#~Jm2 z{HJ|cztaIKy`aepc*wtf*QuRBG2f8k@@&wRCOFt&8`P2 zA-T4+j_#oQxEp6FH8J=SdRrgA9BUm zhH!>rUB&>n>MU*?#Hir;K0NYn8@C>fE9XeRsi~+CgJ1PD;0^!eHADU|bBr3lFH}rC((5Y%OifKQ z>OB4$oG5d|TOg)#X`J$OrP#j3_FoJDY7CMdFCAY_XeN4vE{ z8RDY;80_jLS)dfF5PFd@sZBIa(LP?e0AmFkmtb7Ux(1rzitOl2%-DF~8Q^yGr8u9S z>N90`XlqOHUzpU-R#?&Tu|Tz8)K8#i17?vzh9NVBGi3~n`LeL&V~#`9h20sYI8fAN z$|j0Nvzr9}5AvsKa7vU7hE`4dq0Q@vlCCLNZQQo~Yz&f!fzC!D^QHf2yqmFih&Q%oEBhz>E(=r z%+f^p0HXYuv_ibl4^ZMe$5)C;Dv~9BXS>Y|n;c`Lrn)yM={8dn_uzqpOGN?2gkMAS zwGqvztS-f$XX6_nyi&g7L@&9P8%`Igf2iwvUx^Ln(9@F=tsG4j6|jxe=cse!rcb$S z(6sbw?4bazU+IpjRmFZnN7TcL3SweLh^|W13|7k`*=`xrw44>2Ug}?1>vLD)6!t4K z$1T1CGjJ$g8MTi1+D$$ZSCvu~iar_dwJMo|cCW-=&w@#x^s+t!v<;4%LuS#a*Tj-g z9jJ5LQ27l!Q74{SDv47eLb^0Vlt$ckMaq7SM#Tn^^s~y{3*6~vm&?RvNV&UjdcFLI z!bmUgpI)9`28RbI77xOlSuhA*_Z)jLa_4{XTV&EN{V($US9lWBcV2uja-?6pd?Y^G zj!we7{PCUd9@)V5E zP|iS!o=~iC+bEPz65{quI2dtEJQ(T0&&@BBUoO95e$)BY@>|Sr8NY(j6Fr3md8$g< z4zlN$;CCy}88WUMtZfY_oz%tvjE%#HHX>PB&M>UaJVrDHAd=)$(>8{(a%D?NPe)=Y z*0zh3J|5X zlLOra80ESmT4yTa?Uj$d)#x=%aA=w-qMbZ9?}R9q%#WWhPu;!rM)_-h|2D>HM=y zxY~r43486;>0T2qHKCC|sIHM_u!R-j(l)p;j~prK^_{1rvrQ)btg5Q=^mKRn;4^v9 z#*?E9Gc&Q921Z@Yv2j)RwshOhLadcRz|>XsZDpIyl66k$;$r012P!Hm7exIAv8Xt^ zIxcd=*by;dR_3T9L;M`}xE`%qRB~rf0EXUJag<^G>WvA?-%;Z6Tp#Ni}iquxtA*>+XQeB?0rg%k0d`R{OrV#YB=%kC`ZCG1fB^6=$|w$*IX?Cx@; z`o?vE-xLJO9zG(^=zU$wvnO|vQC;?}u`(8m(>v4JLK(boK83XFuQihy=CFMZ!Q1ZnM-$dzi0J(3x5}WWB1Z` zcKqp#!j+w$x$?2AJ7ui?;*Y(bTUOp!2K7{oq5-5pSB-1YG;Rwer-zGarskS?mck-Q$wn5e|-3x+n(N)yMNuopH#hlW?<@v z`LCwD`Q9ZtuRZi|<~yfnJ3hF0@x^a#J+^fFb5H&7fawk0jx^|9-&tQmAv;jGCI^)B6zlTop9ndiNE9p~;!TIb$zd;cD9d>d?f zZ0^ZVt?YR3r_cTUtevZ^yS8;&aQ1$O>xTO~-`4B)?jJp!GW+)#IdhW#R8{`Rq^V_} z|8Vi;m(M7zI_d39U(;yEjJ;pq+Og`2dy`Jw@I&%7lQy~jz2%)1zT)tzqrY7JZ0O3R zYkv8#_xm#nGTu%7{>s;{_Z9B^d2;FFMXy}^RJPx-?(UB>pWf-Y_rnX{y7ldxIh$U) z=jR{Ze0_Gfa>Ot1RG&R^>CAs^Up@WZ`iu^FpY?8kR!L!(2e)0B^8T>7&f*6>?fUfS z(e>GD-QBjOKQ(L86HPVl&O0mC{Qc9?SGw>2;IiAdz0>d1+qbWH^8UA4j>~!Ck|ilm z4m@w_GpqhpwRXL`VfEK5pLp)i-9BE~{?9ue^Jk5EAN~K9Q$7V(Ot_v zX*{p|mh)%NNxA>h*^9cq+WphNMmpcz=MhJj$Ntvos=S+Bdv@HNeBG?QNxwU|v18@5 zNi%+Wai(wa+;ggq|DxmN)$>l=d2sg`uLmz(^lp!rE_{Dx&4+9D@BjAM8%8|4>bN&< zSTWtY`^`76zWKF(Y})wt(6M_z9P{1Gr(c^nY282H@A%XO7oGFC_uVs6-Yz_`%cDPD z*#4a9i#m9o|91L^6F!`I|F<_(4_^3e<;d%wD1GsShKhB|chsbx^YN^)x6beOQu|R| zpI&opyHf|9?ws)Kd22WK?fT5)H(mPV869RnG4;O4TN?+zy8Wrp-`*L}`;iZ(tk_uo zm(%x_eRb#Evjbgjp40Auj-Btk;GFKQO*1>y9W%+{yyn8^Ztb~f^~aB#@z@nZPh8pU zFE{MCDdpKWK3nzedsm+F;jXSbcf5Y>@Q-(Xx9^GfXH_@6d-BW2KD%Vf>1%%cX#R?t z`J-0#`ux)5rM0tNkr&SESTVJ0(ovDW`EIOyWX8VNBbS%vzgl(df{(i_|7J(ZTjLu# zjNbS}`>fK_XWsYIvD3E~jjAlzHNX1&3unLf$a|N*`A$XG4|DgN_x8Et9$ELm=D$7t z!S7#vd{j8{ROU&0pLymF8`r*&dGizF{(1M4Y0h)Duf4hBTQB#U^uhS&X1;UUz(o~L ztiG^xQ@ayqO}picn*QfL+x5wR+|cd$6F+ob+Wc+1jLPbY8pnLSh~-eTD~H-O>@W(? zQCPsFb9hN!{_qK-&?QsEWsVg(r*@iqihq_E83lRMn6;EuR#o~JvcNXa$FAq-e5DNY zXqtPN+1h-5R3ByhAO2?}o|1lM`M~tdbIKu4e7)0Ro5Sjf!N6qI+UypyBm7eiMp~yb z*X7rK+QG= zJTq@$qn%9X%c|HmfM;@+Z2yR^uQ9=4s;{j=V=sxH+*f|c1PPYtj8s~7*ntb!ic*~B zvL4`;F`RD(rPu0}4FQUg zFKg%&SXL@-4b#qs#{g(HD~uKNKdFhm-$iUQ7D1VZsj~(SC9ishq8pF0vB%5&b*zq= zZLk+0eHuzPzIcvhTOO_4RtAaC(rE8tCnDz3On4DzzU`DJ2?vW>p>(G&a3H?E(m9Ax z!0oG5(qw`ub+n9;@V@DQ_nbbD6 zxPT8wwE->|Jsv716pznOC$K4!c(f2@sqJX@8=jm#g* zsye$R4~Z3m^Gf1Kj^-cX89gGuurP)^nlf&@r?Bu4Ooy;8nm<~9n%q=)+yupZ_aL{4 zh-Mx!rl`0uU+UDq|Af&OjUF>;bpQSihr8}zWcmO6{;%+$2Yhw#+rz~~yZLSBx1Qe$ ze#`kS%he8-M=N5vl{8E zDk-mHAg)sxqAEeoCmlJx4Pc4ZqVez*Z0DC#I-&*-TfX?y4wu1{ul$uITHPEDUhguV zCA;u``=7ywqArPQ@)E#GjOtE=j+U?7Covd1pGj9c%nwa<7~@Q^%YL1heU$(&YX^r- zFRv+4qhCV)Xq+iuDPYONxq(U`*oj>tgZLrrQ0dxMI&21mFHntV={NW-^v)?=P*Pc6 zQ=)g=m8j)myS{dMn>3-%;FokU5lf7TC`syHT)J-U61Ba~PS*9SFO{B)IMToxXe77QM zphpF^p4CGVqzD@jtD&wm-gcI)fjXO_L(_d|t~k2uFR!ev)y6}#TCxT$))mnQ-XuLnL3Z1<6t;B9ZV=Az%9I?h zvp{OR?Arcc?7azKoK?9ue%_gPCNpi?rgWh+1*V}bDKzagP1~fjki7|HnP%w%#mP2V zAj^c3>fC|XfT=W8>7b6!H5j85_i(Iwe?|IHS@B7Z1 zNsE5>e&7H8Kc+o-mh+tF?ECUM+&R6_;UX+2uft;%IpXv^Lxm*AxSM7EtSFJ(BjKZ1`%#T*@Vih7q6Bb?P?jnM&g#N2@=Sx+Jy z@spz<<;oQ-%bi0WMGWgFQwb^;dJY>}Dqk#e)w`ZPOayTzvz6w|trzmlwzqE+s;T

h6}@b&4Nclp?DXzfoPsf2i6ATXe47;m%uWF)P^8wOM4Xqie$Ek z&c1t)dD0Xr|1-Bj=>x!}e2t@hF8=#V(oZ)bRfT|>1VHDziUK*2ZtTSQ%ofhtJ z)m@8nXG+Uw@QfN^+zagH!pgB}56QLzXH0a(a`as; zV6ucGaE^6VRVv6QXKCVXcl*$#YM)i1ck*@mINCR=W_HC_0^GjKl)!|51hh*D*&eB< zEgkwOyQ3<*g|2t9?GT!lsqIjy+$(Wut(EA?ilSuwlsrA+5k+cEnlmYTRuq+5`%}z+ z9rj4lXy1j}1LYotDoPEu)UO*yE#!cl9y+pWJrjMqy)^8QO@*d*FE4OMAaeMr8-3f~ zqiiubH;`P-3qVFI6% zZ~zmntgfc4 zYE3R3=EIgoWgmFkXuE_K|1}RMq-cksa#gL)I^OxvIvcHb6J*A+ARo$;yDzv%gly#I zD!GYP3ixC>4FoWAs@oQ&OHOnn7wERS%7!v*S>d>*zJ!Ydd+i}yRzbgjkqnw;IbtCB zRogIGp`*vmy||Z?=tdVI7w<#rJTi`XU|_=mp|M5+2c}gIw~~Tl?}N4B@HHRpQ`Q`P zof@GWBn~(Gc$@<#zHz~`m+p^QLBxq;KH{hvJUwl(no}(B#d`R#O{BJ}sJ*z=V#IaUvsAkr7BMx$1;SV1JfR+Ax;` zY}ZuX^s0WrI-kunZ|uqNF-_SZNjXoDDIcXs%Tf{T>QnX_Aejc^s==IWE8n&!S^ch= zcK3dvKA4I_<8(yI9`@y^fu!!2?dLu?%9MTFjq_tij;$ox*s*h&($QggW?1mbBU0FQ z%mjQCi|THI!|2TJ{EfNUq+iiyl+!<1^@%LfpDIslX93a1XAb4%lYM-LYr3_ZICj;-Zr>8}o` z+G`{4N8M4%E7~1f7j3bCL9^EPrS>R#U0W^3P&ak@qoDD2Ow3w^I#wMxdimfjnNvxI zepCBPP029=ecsYRoa^DAo~_AonH-M}hO*1~ie$As^q`I}D9h#65!fU*Qk|%e4V2No zkX~Y-riDiGxS@hQ6*)WAcg@Mk=GcJtMK!Iq3pwYN(o^eIhxu7d`lRN{I4v#T&LDrv zy9X2eY#PR66?jMmw`{OLExmMxhg)ZKcUJqn6#bQ4MzEV_^ng?K!y6D!xz%Ect34>e z=eTJIYT3}xzla{piD2o-8JIeHtIo}&Xb9V_ese~5(DJ-B(y2tgP+6q!euBlTIgZHU zR8=3I$m2c7NnJbpWA}4T*`%Oj0Y0Ix`w6~`L%o$;h2TXfT(Ct+NYI5eyq&;m<-D2X zc;Ic#3uOwUK&cs#zH;1VuP0eK!go4sej?V>9LKH=jt)6yjOB8L3%x7#Yjl5<9zT=U zXs~p{ofEPdl||lwK^buPr8QZLS(co3Y5PwRku_myn_ZHq8OJOS3rKirPtBw0pc-Ca zM0Y%C(S(P$dc_2ln+|4SB}osO_--MOyX^5iFXZ56C_Vq<942sYPPxD-Zp+hJ77~LR zB@7kyYX1f+>@t6_Zl-;u2@<~+h$?IsI}U{q+5NHQ7=z+s^`y#zG@m3cq$;f%1p>7S zgV#xd$r6-S(j{c+451}2LyPyOUiH(* zW)_Q$HH}qOXQGZ^X}J}14|zR3oA0ddO7PuPUEx?}fCtW4h@&g=v>%4Nqr;AJ*RbP)xiz)M`}g+V&k zrtkak(3WJ?G9YRn&1&fZsZe%`l!Xr}bJXOKv)ZLkFDYV^*GgT~;N?~YwB#tF1JOo~UR5DTD=CNeR3~4n#MKCXYk_B7*q>7OB;E7J4Iw_+NGn#j9>};-Tv>{o z)pP8ndg(BP1k^bUot(OMVBkit)KRyOgT*xGqo3`HCh1%jlR9mrDD~T-v#X6?ke-}1 zVlt~J1#g?hgZ$>ft~NJqJ5mC+i=-T~+$C{s*GX)pgI*U+;!7oy*h4*K_@~!ZX>*4%B2jTV+IEnsI4M;@XOm*tU*(e&)D_A0T!qnrvljn{3A_t#VCq zvj}!(QOa)&X5ecj)x=`1hzXePDA!Je91e3mn3LK zH-=+nYT!to;3tOz&d^dfiyo0~jbh-b);_DcTF#+He5<@mYDJHv&=t`r6q{u7Ki(FS z!l;9->VjV?9=5mbaT5AEM<6)*IA&o@GBl$^uGcrHk*Q{L=Fz;vVxS?@ID%c2Nc6RK z(Z+VAe(Y98-yt)_^urtxcc@nmkL zHU7|YD5(8=OZnVGB`)sJvp=-Op?qaqDeWXqlSB7a34$DL#TDVg^u|3bRWSk;27@;vAh70m_5p@aGX6RV0 zvV3z+L6T5`LL zNq##XamQCR&_?5G*&uER(PeP?V)HhPD$D!&>rv>tW3??8V2Ga-zTrRr?MMrZN12It z|8|7Bj2iq|BP#hXrAvH@aWZ_B6H+`QiB1Ch!CaLvK*k=hb^4N04B0$@SIMnWvWlNI z3u;%zi24b2ZgS9?zD#y!*F7$Lsa+-2BRS=9xyx=F?CIG{vxHQ>9yQ+TjB`(-t#@Tl zS8IP?0?+5K#B_F5tT$&cu?qc8Kc0$O)st9XkXsO5y|OtG-$R`?f24qSBa_0XpSW;^ z&>6Coj`E>;W0!Qc+_0ZALiT(^AL_Q}p*ZovyJ7tK5%QKM+LZbD+3u*tQB{E7zQ*IM zmIKO6Jo6M{BI)0&V-QOHcz!p#7qP5~Z_R)Ozvt ziw(}`s)2|cP^BIQb)hulT@^gnwM%q~R=`TpD+c)au6EJPoXw&U+)|-uiBp%S4YKmm zn$G4%nl7rJo$jNuYJ0Q;Gq?>r&WZK*;Rv337)4w{b4$EZm}mXT-A-*QSQ2r= z%jl>Rj!8y>nlEQ(dJY2NZC(n4ziF!ERW4G2p zX?RIV5y$!g6esIaHS4U&+OSS%9pU7MMpPP6r9;cf&#Iiabo=?(m*pi#>%EdG^=j){BTuc^<-UQn+GsD}YrP-o=0(SAJ6MXbyD_%A+tH zG-bd^9(m719|%!dfCWTduBYlxHXxXKz9Cn1b^bZEA`~1dJGQ*4hCm?iT}7q?U3o7p zuBkkx6)w7vq6WWQE*w!}*La_g2g&ScZS_KQ$k{X5b<1)7eM*=7=8xO?)cwtrdeq9E?g?Dw<(T1j_C!_$ z-hcSr&SeB-X`3?0I;l*4XsDErP^+P(e!4JsLql76a1LXSda z0(#iV)aiy*Yi{)|->55+rG&htfXH-WJ(kpYOYszhKKV@30$Srvh-7>0=&6L$@uFP~ zya9l&!II>bM#paIa8mlnCP%(1z*+?DKhm}WeCGj}tyQlvi%n7oowZ zZ>YnUX&em7Lt8;z8Qt-AFd`K@>MKi%s?fJv2eh2H3ch@4K+nLZPUlYC@=-0EDnqo} zgoHwxVN5FlCf9oZF=?(%BP-Fv#!)eVi)&;2)R6_w5}?qh^gBf8@xQ=Hfdh3yvHK!$e>T!Fy%Vkt2W1 zJaVLFA-)-Mf~1M}f6{yn{$B_)3;x$Mh_lWTt5?$&Cyns>1-`4cR;&&a%#GINiu{$U z85j8g;e2APXH0Cx$g`QyHDY^&AU@(?x2Nj3s=E;ZqsB5-ekdNzNAAYEJ>y;!FoJ@N5g6*sz^&%(Uy3ryrorHS|n<#%96up z+gZ+S7Bp1VSC*FJ+kR?Crk>8CVy#d{G1(Fdk{R3R=+0ogv4{XDv|UPl+HxD}p&dCLG-X?gFQayK%gfpCLrx1G zOP>`JEOyi5LfY5%zADrf9h{VwR$NlrT8e9N&I?-cdEIkjd$qzOrllx}OQ|tAJ>*w< z`}aoV+lzarisvLbCFo9%NpjL#S2%GWu~Kg&sE8D`?Lv`N<=zUXios-gS2(AX+a{o& z7yNnnTefF1qiB){%aqU?Oq9fpIB~7Q1znoWt~9aDah|Qni6;@;LFr*z9(j<^kvpd1t>F zFTi38f}~YLo3v@q+i>(f0ZcXV262o|&P?tB_%xW-V9$D0|B$56p0sme#UEQfL1R)r zQK-)O>A>ODd}h-%F^om95JKlB@Rk^kUE$J=)I|Lb#wr+API>+S&qUD^*3^OTbu1r9 z_ZU&6PEtfY`4E?V#Ksy&THOVZH+M@;_kq!_8$dEih-p{B$wKGWa>d=U!)4$Ka~47MKt% zg1+cP6EL|g8K$*542;mh$g^XLjnP|A3+?e?`x4JzqnKUd@S_iHotmw{N|&MJa8LnN z-#1Mfw{wc=VmsA-R+#pO)bqM18@x@0>6<*3NPBzr#j<|b<;Ss4Wlc6h??(>@-%da2 zm#xBiiZJP%ZywTcFr%L51%!)&seh-r+d^y+tzUc z+u>c3zDXy*A?Va+pES2MIPFow;bR*QkZg%$%qgGhM18XKWGaPw=L!F$@GAXSoSFLW zn^PYzMAChI5?5YNw%1#VvY~a_Prji+^-#^b)uTM_CyH$Q)TuGaJ}I_BpcioDG2TVc z2Q()q9djn>n<8~~;{%_G7Ci8ST1yT!?Jnb*4>j)7^z2`9_^?im_B|1m4S-W`s!&A?+^KKJYpSwq`6n;5Cf)vU1&v9U{G`;?_Oh(mWr=40?zAO^#6Mcv zkp0opLb|u(&hkfzOOymC)8uM_V46H|(qwP140F7xwUq&7()vT9yntbsQp=7IM|dWs zm9|e+uR3wIHY$fEtPkl*^GIiTW!icGjiqqE7U8k$fYquiTWL>WnrtIQ(7of0j?Pwo zUMj_N9lXv7s!&4OUR~^V+1l=tE`B>a(C%?N2e<2y3N!{imVH!?Trm!8w3qhiRF9}= zEM{1un{}qP@c<;Jy9?iff)tL?VbO}jr~a*KEKX@zc!iuXH7Pjui$azgQE*7Xh=L&n zCw?yFMim@Zut~wNfCVQ1>*`D?3)m0sql?{TZU(b;{V?cpGSpbvkKomDttQJ zg+Gz;iYORwl;NM4ko>V%C2Ugm!wQZnc<|q({lqfqZtQhQ3k4(ZDSIU!{#QxI74!=E zYgFMIR^ik9_&ljMuJU&xAnAj@lX^0KDq-Pn$uIn^q{mgb$KRIp*eTL}XrY8Uf5);V zouSLmucdta#}b-C{@PXe;_mRJOZO4wKJ1lrNQF0F5mhcSRQ_eCc#i#5#y6s%mJchriN8qu(UnqPlj4v3S@MSzeNaK| zUc->ezfol$*7WbC`=%VJclcBZNBlr&;+DCknvrkpPh!z++^Iu;3@~ws@ z=N|dvpBF!Hu;QAfL$kkd@9H1zn|aOe)1Mxjy>Fg4_?-WVS2CXb$=%`Di?fGM7NfOa z+wz;7z9%<4bJ1z#*L>=v&gNe{cxuzvWxF`^h=he7k^XD_Mg1K(+KbbPZGAm-aYWwi z$}X*~E~>0qE-Y)>b;3I(*i+aW%C5)Vb2&W}bc~g@HRZRUv~zvMXF0xWD=(s9Q3+=& z=&L?>5rn=!g>C;(Hoh@dU(cEv_$%9~r5Y?L!Qa)u*pj|HiiK}F5GOy3iAgMfGA2#~ zPb{%v7Z}eP%lC<0H#j-!cx{soL-%L%2^4JNVV<46v;%v@9m_*BIUc|$YZC}O9KUG! zkt03XM~;la`~>E0n7_cJgI|qw*`2d{U7q!&c(u}xFL=;TonyxHVzi1u8#Meq$()3| ziz7mztzG@}1Pia#siS*x3a{TH#8;m5CbD{@40z{DZ<1YG57cC;m?lWBU0v8>2(IHp*MO@)Kcx`fehOSDcg-bp%k{rK?D}CR5 zD%t(Gi!OAzf5T;8;j(|nW&gH|&UeX&UG%#y`3V;tcEvBQ`bk|V7P#!^y66lS9Xd5R zzp{hL>2=r@zU?mB{Z8`cl9COf?7G;l)hj~9gE*f-&-hi>@2JnE%?dj1y*#vb<(ieW z>P$aNKKBFp57Os@^6OdR+K;8$TT1wIP6a=s8(0S^Pd1#>O%3BZNN3$Y(~2=J)|LOc$93{Wf*;)lQq zJ`M9W@d5v^M2L5Yzf_1Hz@*=RumN7N45Gk?0Dle>20j7!;Zud!2z(guF_E?9&l`;9Rtd2k1K4|jHvxV# z7jnSI0N-3I#2D}i!1LCDCKA1*WB~7jsRBL%_&b;e;1htWFpS>`JPi06OdIfVz(u9V7vLel-7tHA4*@<7 zGX#7T@Y7|8Bk+TOkHcI`e8S67Ob7>jXtNM^5f1n>n1_K+06tg&Ip8CJAB_m{0`OtL zpVbL5PBMV=8-$nu9s+y><}biU0jnF47N16501m*U10MnmZWUqy@C?9%FxkKfZpNXh zjU*5F5=<5Falp4=nt)FLz6a9@Tx=I&8cZB`2H--NJ-|bN%VCCqhXHrO>;v8ecmd3f zz~g{7!yEv95b*0TcL5&-T(ARW9e4=vsq>Hyz{dc85AyDg~SK+wFnUbo&neo(+PYC z@Fkc5;NyUowjqwh2Rt)|@(sKYu&5K^2Oa^urAvrsfFA_>CCm?jPXK=G0wLZ2J`8x$ zg($bcLx4YpNxupD0jqI9ViE8N;QcTwfR6y?_rL%z1pE$674R{@%{UpeljH%v1Jg}> zz|DA|^-|&k{;eNn4>*=?#I8Z4Iq)ICU+qE}13m%xSD0r=X15Sugn0q@2;lNP2s7|7 zV8&jw6~GC`KY}y|PH@vz$iL4ZY=EDDSps|*@MBk_ei07%%104q;NyVzeGF*}d<3v~ zAJP+e1n^@p!z2%Q^~X_82nW0cW(4>_z;|H|0~gl_@$2h_coz5s;G>^JIDwA>J`eK_ z@G-!fhY?QT2LbPcNxvEX0`9&6?J)2mz-wTZ03QYvpGKMkC)fZ}3cLyMO_(a+6M!8z zBF%xv0Ux{>aREL8_~reG3-D3ExwoLq0}lZnxE*;3{2<`HFwc-Y;MZVYAbCJ>2g(U> zf|W3D0*?TO4dwx&bkwR0M7vIg$V(V1O5ai41650`!1Ai;sbsGCIWl} z@Ru;#flmO=`aJ45@C?8OFmd1^z$N#fUIPyUeh%hZ;0FPl?n8Wl6YPO`7{P8;2HO${sJ!q-1Q~I|Fg&oz)w7YZ~z|$JpMtr2Oa{f zfXN3Q0c?RO1s(@{UiUM zR5zF~@d3wRHUcMj+T(~1@G#(BmI=C_li%fR}#{;R8Md`0Dr3-vA#6 zEcs`oGsy$q`6AK<_y}O{ODOZe zlMLYcpJ3btyb!Pg=0@NV!0j*xfHwi|gSiX%FyLXB`+<)Fz6tX%@Cm@v{}o{Z9tOM+ z<{98|z%RnQ0DJ^cyoS01oZxPlao|IMGk=P@13Uxp-Jc=vNal4Rz6CS)R>TYNrhh|P z0Y3zmR-~>nBLRlqw!0-PW<={5R1CGCqwgNc8!rvl}zzK$ahxP$D!CPS>zz+icW&-0k z;1ht4{2qAFJSvTL;R3%z?_AKcmsGCa5v0ffDZva zaH1gs2N4&*BPYQ>;NoOMeDf4TYy>_A_|`H*YzIC8IDD!h27nXH%{IhUzzYGt4Kqyg zfKQ!nhy#QJ?#MC3Vc<=GUtej6XMv9b)~rIffkyzBtTx01@G#(6xdKuccp>2W-G=BS9MHG|VFR84xB%uL@DSkXF!ult1D*jh zLh^tWFo%Ih0Jp=80&fEBgn1Tt9B>cJ81Ny$Q-=)k3h*#sCCoVR2;kK)Zvr0%{5i}7 z@Cm^54fFT*c1J@!Afgc3iay`-wcoX3BFwX)X13deaNGsqGz_(%E06qcu z{4i*e0sI}zJH!X{++c`zfoA|V!u$nz6X4%q#GNRgpEAVfVA6pf1bh`{F7R={3qOtc z1CIlK9%c#f5x}Aw4Y2}v1aRR^h%@jezy+T{8Uhai9)zg^PVnqoP!32QFz*he3GhO| z7MOj&BR*0{#l-Vc-*hr`%6Kv{r!19%2tCd`{8bB`gee9RDcVV*t=I0myHb3KBu!n{pxKluG$O#zfrVVJ1b z#R|3n&I*WG#vBm{r#1QGzKA*M84D_zcR!E%3pa1fMgI*$b%~(ce(pT7#S=D~AU9{4m}8tQ(!}~SIIeh79BK?pv6`-5KRjk4_ z%`c`s$+0uBE1?X*%w{1 z6t*iJVWT*ruKaSlb?PPm{HD+E<@n07S*Ob8G@lQ7 zsB9oNBh5D>H|SL;f_-(KS`#}5%2dyJJV@)&^NnohF6u|QQw$%oWmyl zYC$Q87*3qz`%}ov@ax(q!@pqK)eF2UN zdYx(EOs{{${jt(g#!t6gcKoJFQ+N3wx!e?K=`N?*UFP(wGre<+6Ld|sd_;M7<`IS4 zoyUJj;g8ZcJC(kv;zqjr9eL+WV_62SR5eF9PtemeUXxBcHsJIjR=cgJn2v~`BniMzw;)cyYjT&I&WEL3LuU1J|v&R$RIbKGr{ zlu7QFrfQF68p*L;s=7N>J#+i%ZXewCGQXaB-*sUse~F)}U7-A(YAix&s{0z9&Z**> zD&1tbTPB5DwFTD9*6PtQ{+cR`?lel3ziyeS%DJ(1 zug?^IxGa8a@vpg3j=;V6Nu0nSJAspmqO9~h?MbJ2rN@x?W zzfhj)yq%FIW*BD+JJ;aez24!Bt13faS-(iwYvJ)iuZZM%#e!U$H(UgIomUisuYU)@ zE6lfP%_kU9{GAG3py0&{?o)8Tg7+)Bl>g3A=#s9>FfEeh^Y@LB~A zDfqC0-&1g0!3hPYZIJ#fR4`A$QU#k7+@s(=1rI6sgo4j2_^N`xRq!tg9(RWHXPJV9 z3N|R%q~IO}KcnDn3f`mOsDeLK@D~ccqhQ8H<&T0J6|7P4LkjLu@OlMxUf!bUhZKBV z!RHlxRl#2<_>O|+Ch6~d1y55jPr+gZ8x;JIf}INXD|oSjS1EYCg10DmNWuFR{HlUa zDEMs!UsUil1>aWi-xc(nDZ`tt;Cuy_D7aF=bqb!TV1{sw&1wX3b zu!6TJc$b0?D0o=Grxbia!5=F469s>v;DmzjDQKQ0<26&k1qx;=%AJl)D?jO{DnGPS+f0+*duhjoCQ9@VayDR%}K1=XBixv1tVRuY? zRFvR}zJVBjZny}iaui*T2mXq1eni?<<7& z@%_oX$~N%>2UmVW2TU>B1NT+UiGi~I{=R-8mJnUt*EZN4qo~&4Y2|G=wr+D}2;uYD z#GCwGE#gu@)Kz?(+0q<*iJ?fn^jO`TxDY45$fkY(Zx#&3=`q(L@p0zt#iu5E8tA2) zPbAYt2?`V2e4cC?x>_$Rp|3sRM3L{=$xqNA?oW960f7i!V<3-Egg6+ne(~fa8|yJl@rt(&uRc-~ zaH0t~e;}EQ5KhBu+A2cmv&=erla7lZ&P|(j1Kmi~^1)vIuxJB)*g^P-Thbh-PdHL} z!skcC4B}Pw^<6j^*TN`H{WwoNmu%D%2#vk;x)9DWn)Q|+*AXrYM^aYZN&LoM`Akt; z*`8LsMUO8(ASx)OV#KWPj>Y2QD-xFN5s#VmRwg#|S(zrDFdJh1Jze;o9zI~nkADjB zq|K8)i*K0?-3iJx`mmpP(VWs_@pBUyi=ZLqZK!2^yklF!HcfA{=!oN=km3U^UF_SnU7x==L}shqS2Blz6sDu?``0z zHflvspUT0<^9Z|yr~%f7Z;15rqh4D;b;Jhf6%be_aC<+>uYbjQcZqt!`&y#(&ZZFO zg6hVTT)WikU`?PC{LWTfy|dLKIrvHx6?%GSgASobn_GL@x_iaNzPh{{)$#?568 zPRucz2l~2j(%D2a3>RqSOc~?#X1nsP0NCI_tJuIWAvT%q9M&@lBCeawb}M9+!0B~( z@?ZnGoHD*Yw5hCcWU&+>Mj2WglSaI0?ru$Rj3x~Au5fW5 zo;b#j=HvfAHs_Sp)s$6P&qa&5i0cQ&PJ^DruGanmegR%&BW)V%%j)dZ(zCArde}6( zFs0Ir49U;wi)TG?j2@n-pC1STWOuu6J7gCq?Oluuhc% zIAaVen4x3|dFC^mf=_Z4Fx%r^@k!HmwehSyJ=Viqo3d7~3}@l(bUf^Z_r^A5H8zyz z9w2gRZG}hCCPu{_OZ(>u{V1Mt11in|()11h$zG9h! zCtEi(Cwf-yTAhU#t=)WRGcKi zP@n6GwMFo~A&lBOVhL^Mv@P2Mhcs%gitUPZhq~$SrmW^fW$&)O3uFCRtF)tytESYr zah22ejjOCkklT&)RxMsXYw7Bym+X$2MoHq7S~36|@!@8k9wVq$kQV3U&{rt&RA~#| zSlf*^<=S`#jYq?5Y5heOe&S8Ngor2LkdvXD97~n;{iE9YP-WYutV?3}D$VM=wd-?M zugzPRleeaIZBFyr_E-)+Ow$&N#n!Z~X%AoKNS=Q@EbEUNjx}pnugPyIXwF&NR)BD{ zx3uNt$8y_pnsf8=!nwI?+Y8n-|JQ^g|ES@}YtC)Y&5y0gS-YmCASW*`Z*@*fb3toP z+q#0byym>-b+I-1|3%?gx%#LfS>3*F{kqom>vHnLvDG=H%Yq2mi#WZcnrINeD3bz8N(SR~~io9>jd zaVbx8H5I;7r98b)k?JSqA3UJt#U?3#!4&bA^1r@I%g2kQeAN`;m+AGlhqU}?xs=~J zL-21{y$2|{lIQ#@{d?|t?LO2XC2w*HIdCcesTZ{TsFL55>^gayzuVTTI$_c28w5{af0j?e)Aa&8@*y=3#41I~ zpOn8Zq2Q3)a63}*xl+r!?WMlAEqguBywfeHXsPdxj~`v%&QECjQ8jO^nj(DC z|Np!}%V%6I^XKUCf9g|OKBVMvMJnY_>fd{_mM>KD&rMN3Wc(K1qvhR7rM?#}`;2R3 zc#EdcC*^=fMURr&kGx3#=mK!&g6J5$+9|7xGr_G81+zq5}TzQP}C z`KFtsd?elNv!tc|lDD<|$Q@F?z(_4G!`uD`E$^0+`ZoMg+fN*l`p|%+{7Lz1-?ilL zlJZkDUqZ_N^Ltued_l@*rqupl&pf;onU~H~w43!iV$oDuyIX!q3I;UpTHb(ZVl!@($t!%}!356UU=Lp1O_**-h`-PXjdKw)N-cufjj3D`I<)I<4<+Kjzf?vU<53h<6{P{f*xPAYo9=wKG&g8wBS5;Mr7?Y<78fGxj>n&obXk3&V|hOYm}N4cJ0@=g|CIa0JdX z{569;EwO&QZ7#p_3IzvP!2;WjbH~rTH8>qZ=#U5m%)mN$5u~r>Hk55|5M!o!h5r;N z^+#4$;4^H(9P;16L5$=|`ol~I{E;=1zLMz-e**@&tH!Z{UJ8{{Aa>8pU6^>A7^p{k!2vSVR9ppuPYGdZH$ll>+s=N^L8el1%cQc zWMT{iVsi%*uYf>o4lywfB2SoiGVvyewZgoMi3xvQ7XouP6Yowt97KUNrf+^t+M3PL zNJE|QujYn|)na$f{}hvvt+n_9hWQ?~4(TNoMRmfQZ%~_*P7Z~+z*qwR&A>O{QF>Jb zAF&o@rSURR6-70rRb|4w-eAWhFWvl`@e(OuuO;UVgFH)jv`e*(4V5);{FrCGUx*o$ z5{*D+Qd2XNT9uj9_An;WBPkp{;fX^YEhql^qSdQ&^NU1=x!HFJw7&`;mNzSW(}4?r zMOQ~B0_}SbS_2|oikfHpcENTQiI2i$(1t>$E-_YD489jaqlq39msl|aG+`=%!^ny-O`yW%zkFg^q1lT2DQp{f?a1Y&vrb( zl5;J`sMLeZny=f_UF>dwB%^!=z}(HeMgDRs*t#O4h1}yGK@x}j+k1K(+`WFvrGwLT zq|sJf?5B)6h{rJ8scT;1pO3Vkd(bfN_1}Yb!C!%GZE7a&V-f`<*3sO$SD0V4JwuCi zzn_Z3LGl`j`X#1Dh(dBaz|<&Fh~I-ujS+>Aj4(A$6q>CsGc_?C6x!#9m_myM5-s#s zn9N`jjpxHmhL}YA`3RF?CaDSiD$|9MMvxw5IwENV>M+wyl18w;#&lfL2-w$|9+EVI z_88N6XN1c=HKknc4KWV|^7Gt;&M)sCsK*f-VSa%NC}`x5cS!HV1<>aA^j}y>mPhsjb97p{^cP z{gL2jU@3dpX0V}zS?yV=JPXoXy%L7G(;OJi$%Wq^vqwujXk8| zFG-uv$beIm(RyKVGtMcP-(pn($*St=!RZk5+sw=G*AKSnlRquO{0?&$oIt@2`HTAT zDU<%@{=M|6<47O+52`XRuuL`vFx~CK{3i|sie`W!kgft}evjjm9?|soXUhZ_y`Yj zfMdLftYbZ0D4pM7`z4BjZ6#qo%dBP63F`NA^Y$W@vO&X>-WWQy=jT0-blNCpQF4(b z*DkN5Kd$MZNS~DE=6C1KMV_QbQrSEXmu7(Mb#9ecR+Z`Onrkkb|H+xio$BV+&aPe* zu~X;E?2;q@+IDqz64A_N8+2DV1cZ_uL%GDM7IXQ0D$b@~6|086dj8>sF837Syn~aUt?^0sM=HCk) z+KXDAiWODq)Eqav=0BIgsmVqELYbCnKSB97yXRBq?n&!F!)W#};Z4IMf#~C&Q(%6LbC4F4VTmh9<$h1!;##V1S85X>CLdG7(Cf ziPqcP#l(`dKakSh9K`Ij%gAOA6Q`wphlssQtVp|%h>Mw6nRb}mT*5>+ZID!7%0zD3 zBP4bitIkV1jchJwB0ud7a&rX}8`G$9HHVleph*t&kL4$wYZt3Aywj0Wn0&gQH%>ao7 zRquwLPj+tgP!TZ97w1RjAh+x3cp#nq73L2(6v9u(QFROULvB}1zq@7o7cMIctYVj> z-F#_&H*}kUKOhvkJ+~!<`E&ML+cZ?wM@x#Ts)~zB&cW<%;XUm30sLL~H2!e+&Vvoc zp!PX%XHYlu3R%-AOJr75*3>r?)s&P)F$waG{RK9Q2JsDNe8ki@M$;k8N-Y_%W?+Td z43GkEq@gwvtt#7ER^?cjLX(VfoJgBZLBM?WXfnsmfwIgf{I6?hj8xW?*A|J+z{&I$ z{G!$t5eV@}X;F7vPYy(2@xLPY0kBGAi3f_Q;A+d_I#q8x}JmxWD_?`Qcmu2;^u*iEblHF80hb6 z!F>b~IF0!E#OLLaXmw*%LuEq+=DDS1r6?9BZ^fLqrmPW*5iPkh$RSAQbmAS&hFi&_1)}cN!%ojd_B|C(lAiCT#kw#cCtw{u! zS6Lq^YAC4?L88j)>T2u6G!~)dmg$5cER{ty4I-V0#+q|#YPZ#h8AOzpm0)00C1w&) zxmskf1d!Ph$rZ;*Bu~s?k$f>%GV;YdW&-Km@JEEF`49 zsJyJGuC8c@$Rx5v;)@8UgPNsf8P(x*PnJ6TxxT>~T6cGkJWkuDZSmL#H7^jO8+oG&AT3dWJeWS2cOW3S3Vv#B> zQ%;PMaBpNGQ-G)> zVgar0EHS+>6m`|8&H=XMUln2Tl#mrpGS3B66G`a9f^x} z(;U|GoQK!x_QIp3Y8eJRS`=J{uX1X8acZ=otXO2%43rG^_v4G74KYmbz7VUI~Ek14@qz2#S&1YMVy8^2J-e* zG#i%i=W+l7oS&(QMFw z*5+ZLVze0F#UMhgLJXp<@&b!-IVGk(sa>QZYaIB}_ zfZdwQ@P~eDJ_&>-A#3gg5@%lCpmO=_5+T;Y-CCp0$Q5}XR_q^uT`k$3;1RLzLB)R! z{Ja+&ZZA@9SBv#4W*4&VUqL3{s6#$-RN`?Jna}B?=#?yn5FhvrT(7@NxqF9#V&JKd z&`2>$tTna-y$dX2d(fMq3D53O(97ROVaZj|DBlk%scXP2moCW(<26dV5v6;j+SWG? zWQT+(=#D2YMtwn!;-(s9|2VO4g02n9J?)YS<7dyHIC^gwyS$*Qx0IKdw+!M&lrUbW zow0GqpHYZE^FyQ))j7&HV2nRfWx*TKqM)6Ym9WHMyhE(L#Og(5M$2RTiNg0F%*HFw zCcL2niekY(J(e+uMMAcfy02Srr(tL78}MWVqNCB`pE{xb0KO1C((AIL9(tR~wv`#_zDG+lEe zka|LH19BUX;z6Y)hg9J=1~qH$CD*WBce%1XLIvp>MPw|+=LsN&-1iKiL>yB5Eb!MF z+leREH#vk!@G??fG82l2=N1w!thAeB%sv@GE{EMT6H#0bM3l}wu8^d}GT1?ZciNj? zQMy|(OC-|>qtF?-@YD#4b(bp3)d)xF#}&~GNh;p!_AACl*yi1(h|M6ble$nqRYei& z?p4-xuwFN+VsbtazfnXl5g95bmw?D?R>ZX+UQxlT6?s=E_RU~V$gt!aTSVS-4t^lS zVI=;#*A)K{@>;6*_RJlbtUE6bN{WdwuP=^a`t^aCieU=2;N$WBt#ad5S1Z&-Z zP70mPIV5Vg7sN%svxWK)yW!Y?OJ`^f>LgdUAe$k}k!U0x8z_`aZj~z2RYL;{ZuGg$ z-zMz>+792%j<)iyjj>%?nc9lSDm+p#cF=IfZmcSBnX$XCh1WovyU`ZV{*stcMG9co z)f11ZOM^zvI_BY<^j+O;t<4yN7}KT37|2VI#%c=etox80cS6V6B)+FB+ANF>`$0?UVqu&?)GV5tJa37$lGw&4l~`*O zVw)7zwzoGr(4FAON9opL3zpx7QRq7bdw$o>Va4)xCEw;0M)Aq8F$3fQ{FGKP44aG+ zvZ#_x)iHnT7`(-b`D-S%6kgY?s!R$>Sija zn+bY{rV{O?c_*ZWQAra~l$y~ZR*HbiaP@V!#rCwu2drze#<}Y-Q#?o7##?E$D~xtZ zWK;}wm&dY=$EAG-MLy^aDEo?Nb!E-wZJ4%T5?WP-8CY@S=4f?MLj|U8!swzDsM13+ zOxgz$ZMYa5#f5H)|27^9x$KcC%6fYW>%?H6w%*~k#yA*vbN2}2T(+rx3JE}F`WLG4 zc^mpHkC^^I^?BfsnZB1qS&$YgxH`V-)gF_zaLJ5UO6nV5l5Rl|_~Ouw#1-4a${c0u(@C?GTa zqt$d?jf}CbmM_-wpNw3i`bUTunb`xPISU08vjr@i$g^9kS6gSdj(KcLq*E|(-l}B7 z&Yr~H#JaqlojAXmwQN-GBLsdlB-UNsIHoUYv;%-a^8KkJ@f@0m55E!3p@< zvHpV-AU^?-;lr#$cuUA)0m6$9ItV`n-F3VpjgFq>UCtf>`QRU z^qO3vvtI}84ZMWE0oO7P+4ycc356hdlx3W0)-n#s`-SHoWMU9=aJ7s>s9eS&jFxd2 zVi|`ZE#ol6G7dpn#vv$|aR`&kILxz_afnjOI4r`;ID}ctI7C>>I7C>>I7HAg4olE7 zjzqAGBM~g)un3lMBm>Jh%%Ei)$)RN&!sIdzVb(GZ5xk5;h+`RtNWF|hc+xTsG1M}S zMCCFL;d&W|aJ_J|ln8qnhbVg)hbXy>LzrI1k+@pMu`TR1n^G-dv&x8-w2VUxTE<~0 zmvIQ4yo@uQTsoFI;pmjuo6N37-jr9>ZWDWw`H{*Pt2ivrddiPYASlYwN*TI#LEtyiFJ`99Lv8~76ceFA??N^G?K{7go) zEtY8Q?~2oDqhMOr?~&@hma159$3Uk@I|W|>AsQ=AN~U3NJSNhX5Z~~%^jK@>36Zvx zm>%Em(il!Wbka66R=GvmX;dn_zTFL2j7qfQ(Gl9HO*@^qK3_{~TWNWtK3kEtg1BiS zK!KA3QIi_Av@Hv8vLy&f+G}ViqcxXGI^yQym6kOWVU^i%NJ0}!dXjmiHC44mSoYje zQ-XHTRt)jd8qQzS&1DCy%a?3bT~t$9URIC1AZ`BCmLe@RKf0}`64kE0K?ITo8Y8xc z!DK7d@?y7JB@<>0>4DmdkVd|idO3p#M5q%2y*tv^-A$R%M_UkEC^=0jh5e2?5(@ab z>Ur%>1nP+nO2u96q9U;MKoCl3&5R0+2yBa>dVs~Xb<<~SHYHu%&WdwE* zneJkDK);Gzo$837_l3V=e7n9fSRH zZ8Pv8DpB+4Y&MzGjR$V*^+O?GS+`VlChv8zE{Y>I7d)b@QGG2L5;@ z3B@gp&%F?TAvwf^2OWQ)m3rKe4+mp<04L0-SkR%wCLz4Ec{+``f3KqfXWEt=!sNw`?AA&y_zV04!-Q3nj3!EZ2=S4(s zk@8T^RD$z}7xK03E~zUK!39JuQ58-EPoMiqsku2@O1>WZ$O+_LAG`+S0OU4R$j$uDV4u2W(Y^Gh-P0Fs>R3 zucTyE!#GIVVdsgep74p;Sc=Dd7Ec4Uc1AG@#G6XSCdxeHCHQz8CKI43w~lLzwKwDG zqa>j@{kY7I%hfomWt>GNYmQP;$faX0ze*F`CEwQ)#;7q{^@FYP!RSC=v^%zXo$%a2 zDepZ42Y`;-1BwQB^E{qASAsFWC0}^%BCGi=BziZAiaA*Oj0?}_Gr$+eQ+}NTY{4HW z*y4oF7!Gk6hxB#MUU2DW9LU0iec|`is){EeGJmD;nh=)!pkWcM#fHa=cKy83+k`w&w?KXE=*;;z}hN zhYt|*1mNLGGNaJyV0~2>*HZ$AmE6~X)6Y1t5GO}Y=1jYuvg0-+<;lH0Es!VjuORVs zK^tz52xFKyo*T9=rm??q!}FjjF#}&%?g;ZvgwT_FA>^%xsO=07Vo#d8Ki&T%al3tzSMh*PNKPbkJ|LjH^cyCA;g zW?0>gFfTa-5x>OaD*K;%Ve5T>rG8I7SfEbK(8$I zTd35}p@khR#MCPSXRU?Nz^#{ZEL&G$TyFf#a(X#e1?6;z2yrUUl#SOZ+uRq6jRS*N z3O-q`@Ug@uw8BJVZSVEh5sWG{z>BffgA>!(j^S3)c!N|uik5OQ&Q0>LLs|TsI=}^J ztrp8Asb5gL^Fz?|NChpu8NZ~lhWCbv%R{XLSax``6yAAn7{5Fu_lbT*?Y#Gfp)07Y z2;(h^fcJ(sFJIhFryJ=+A+3e}n*6^Tsu%Mz;@d=~p*k!^tBn=~y$aqj6vl6ezZiMG zxE;EFOVm6ZR#H-O!ipgMj?(mIw&1Z9+;=zc6~+WPc$fJ7c*+lbJX#a(YmMJiQ?Mh$ zVWYcU;}2x@(b;JIDJ;C&XB;v9_COJIVaZP>L$tYr7Bq|u&uQb}K86LA#aLl|k39U! zaY!v0HmtH?{YmjD%}%GHxAQ)!3&)v-G1s^R@=LA*e;is?5Hn{#sFt}v?gnxd)*)9? zL4HNK3whwK>kI^u%WlbhRhlmYvVtsEQAy6BV*C}bPMr2d=^xc^swG!&LB>9n(z{UE zM@a7l6m{0S{&=N#1jq`qwDr!!f>>6)L$6YGuVM|8s=cphRjVP+6|Muw3bM3S(c0RH zuR2u8AnL%qu52bqd=~scgkuFUbAABo z2~a2gT8X+;t$?b`XYZ9EeiPpKP!!0kU7S_aYGONY^k1aFB4Y;@D@PT9y*>00B6E$3 z19enOr1PM6LOBtcdCF(9F45L+Th=?2_0#aYnXR`_t(EO`=B*CLL)x+TB^d&d+4v=i zk?z~I^-s0#6R&evBT_-{pR|<-(?H>{vd4BS|BQ0uI28WO?kL%G*lSa1Ik?V zkPHSz`!`U>aeMX^mDpKfWj$*#WNQ_X31T+d36)>1ihU~BVP+%Mm;Feo$n00v1+cDQ z>n&7-vi2)}DfpT9IdojCbqp&V@Q1b;Gk>InD6F5=LR(%{9%cPTS=W-nIbV@%8v2ZB z*&!us517ItbBU6q9{-n855p zI)|;d^9E<;KRMi8pxp^8LO)a16ojnbE8-#|W<4Uqa~Tn5C}JOo%oasZNWY;~R{U6s zi>zJB`qL!)yGJFPWPhb)PqDl|qO5O+?3&vSOWD~dL=^iQ_FsOZiCx;0MCPBA6(#is zW$k@S#a<`1ahAyRe@*J3l-?o*DW$h4_7~w#=5|HIAv36C!s5gmzb>5)gAJ8I?{8HR zrLuw2Bo>~f8Z_)ZXVxqHQE2=&E7{_?l#6Q~nlqpxGfg#M6zB;Z=mjrJUv!{7fh8hq zo|2@2d*%#P&A$uH^U;?eDQGw%vQ{e#nF)%Zge{g*LGN}IVq}7{=1jO-5mbA6wd{3T zHuJj<>+7`jLCbpDgEGYA)BW1I#merJlr>l1QbmwYuV~r*mhAb;Iuq8J7dd22bb4Ii z?K(ZAtP3E!h^=LvzD@DDPLDWr)My>fI(-E^dQS;a1bVcPU8iS`$oO%cE>r}`epbth zpGXOj)u60jrU-o0A^R;Ydxj-@i?V*5Wbai3CCu-&Y^^2x4Q0(?_@N>w=JV0XqNs3( zxLCE$q+>1f(FpF>Ix<@v*5_*LQDsd!u-l(`pAw=%eudN>^xpliMS^}*(5c`)ri7>x zeMV}c3Cgz=o9fL2lI;ncEwcVi@u{3=)~Yt`Hwfepqz9hB5s^8e_xs$n7PGqiQU3i}prz~5Fv)DSkXkZK6$eYFTt z#L)s+^f)b+D+|i{m;Bsn&PH0kn?P)KIt8 zs>HG(R>@*~k|y&q#m@(yj%vwbphE@M<_-HU_oH|!xf00T?3CjPu9n(zSSBH5^r-X& z1<=j_ULi0xqK8m|RDfQVf>eM$q1cpx|E}E^zATlB%x^l>pN!K_oc*cPzvxiEP70Fx z#j0JWvV9)2(TEQ#^@ua2R8~w0)gY#smpfcsr(Go(O7?Vu3etq3YMi!m=onqZwF z^Hs&Bs8%u?QN7Zt>)U-;89lO4Wd2&oQARW==a>Ne$)Ob*J%Mtp9F-eFTn!msIhw~a zK1@ZQquIDUI?uyAkoQe9UlM4Au$a|C&tMxlG}=Q4qz~xPVr73{A7;j@Xx%jEjc6OW zxQ4e5JB6{DlmxvM$#!~9n=5s``;;soYn4m2TxqP4*6$=+OUJx;ZRAObiDU^iF_t20 zrO4aKB63+;Pj=TynKzSVx@dt~i>#L-Z=@2TC1^Em&X;22Q;G3PwNY>_aw6z0OimTO zw6a0k=BKiiaXLdvgq6fP^#pe`+A@e&=y7;OF=hybthY}hOwTpeW5sL$FE%JJ{Q+aW ze&1Td^u5M9`3Sf}DL)DhoeZTCypzpZ0H==_`M~K7ZUttZQSc)#&OE?)tJlF59%8qG z$m9&cU<1vD$#|N48`eUcjHlDLUOn@zK>Ec-K{4haWCFVjjzEY^;KKz=0LTRPZfF4@ z<7x2~9D*R3zy%v#0E>+0JYT^Uu*gh1xu6Yz%(Rm>Y=tcu&$+%0w*Zpybo(}Z6V_xr z3w-PKTjUz12R$1efE*dm@xFpNkRubgtRM$~OyDCME`co>&k4SQYXQjw*A!d=TQakJ z>-kA|{*zH@6nq`_WM-M`OJdCjH7^aNeoyyj^Mu)V?LZC>+q z;`)Ng+q~uq;--mdRA}T1q)G8Lw@@vbZtuog+q}sX1?Z}VEa;k3=`tHl##$f|m|TJ4Ka5dodF&FkC3 z$tk5`_&y{F1%i5;*H=$;P;Rr+Hm`5%Nhn7_Yn#`%?M2qAwt0QqDZi!#)i$qh2a)MP zwax20m&lnx)lK`(BQhhX*PDGii9RmH@=Mz3Rn7qyF`w*3=`9XV|*B2$u@j=Hn zudj(%3xaeoDuX4!P|&%}>uV!kHicjKVlTi!m~g$# z>udiuSouNT=Jj<@$`qm!QnJrT_s`ftDJ8dg{WHG{MFLUfZC?K@BF&)M=JjU~8IY+g zw|V_(>DWvNa<}deeiq&!(e*a3e>zzPg1mv@pZ&kcd-M3JsskBkbBKN0-uvEvZa$E#^-Swo&wAE8?0!h6FfV(XH`?_K@RVtSW}7!! zL|A#A+2)OwGS*KkoD=OvgIDDF+q}{41PlV8PRC8r9)t{$@`;u)%xzwpu_G!KoAmls zP4&3vgOKA6W}a;0eJzOiT@FGh z>`;u3JBvN*SDe&>_ZZw^B)S0LE^XvFluhINq~doy+~F4^)uS;8?JPShBS?HbqFr&m zLGN44O_Zhpg{K{W(>;bRtuxLxy5mXu0Z5B3FG&&YjKF$s66j)#dAH;DTz7b}%nOP! zF2_uKQzeH`QJ@_zC10bmQa-Lxa>6#ZIRW`Jd#uq?*<5Cv}D zQOtopW*sGOC=o{eMPF)o9vFUT(|9PhoT4KYe=%S$ zYpzZK{5XYQ4fy9afnAz_Q?yCZ%wr#P!w{F1M@&$tzzAHXRI`$DNjsE5YxrTOXppi! z3^pE?ptWIyqGpBf1N<^8?!`>TxyVs;ni5g@`z_J4R{4_eDH^mzH)@!MeBY9Oo{=Yp z48;$1N^TBtJ*Z(?vLoEsShMtT1^)qHD$FTSw?Kthg%9YkLL5t{dR~c#qmAH?ySof* zra~Oc3UN#?TOowLwwyIUuALoA%3BfdEZ&dL`{40Gx1Lfz1GI}&n`Mli+}l=x<*Wkt zAZjYeiu-}>*az+2s%G%6WGCvi?b%@}$SU$)4=gK)<33*BBLx7alDO6bk$SPmPm&XNzdmnMM!=k+ z&(s^3;#$jCVN)zB(`+#-7g=;5D`*o;eJguaDe2HfA83Sr`ha0WtuOja!SvH-4Va5? zMKx+L7R~zt$AJXui{*l%l>uw^!5Xtl^t?jZ#u^scP$;@ifh^&L29YV@ zvilV)=G~_eG4I?Wi|Q={seYDO&7wgGOkl*9tySfpTPN&y)!1zBpzSm3WXZSxl zrWcM4VW5M5o65g!q8+mn?eg{~&A`i~xz{rg$^X%DG@9bG{ z-pMY`M&J^N{EClsdwmRn{2y80s~7a-|HzhJN8=CwN6zS#k3ak$IZdvDhMjNFnEuz3 zLf$X-L%C1B zMg|f3Ki*2nnJ&uvwdN9m@Mk?4$*H7XBKR3JjpC7362)?^4SY-oyz~`d;{W2>K%ReX zfb_UF&;Xx^<3zV!8(`2}8(@gn2IMcU4e&3o4ai?y8{l7F8{l7aZGa(jZ9riDwE@O- zRwE>GZGa*F+5jW|wE;%_YXgk%+JI2-+JFh*+JFh*+JKPY+JFJz+JFFfZNNZyZGa(j zZGa*F+5jVRZGeHmwE;%$wE>2+t_={N*9J_`TpM86UK?Q8zc#=~=Gp*bnQH@#nQH?K z*=qwPtk(uIh|C>$Kp^H{8z3xrZ6MDc|HnZyzHL{(s&Ny}a`D!Fn7$dB>^?-_v`7DEPm{+6 zVOMA8K|r3t$E-?4VsQZ<9@?~u2TfaXxl#qzyQ?|XQi1cT=Pu;&?HScHe0ssc`3K{s z*5W;odOQlUVBx%K$IWG(4_1rx+C!$NO@oc*qq4M<=(OtjQ|Hy-r5(Hln~SI906vzB zr_y-eaeB>+h2}v-yxp9W1Vv<%jtFFZhDb0)PG-`a+V417au8p)Up0A@Kq^zL7|xpmEmn4XxM`;0sfmuKzLjeXfW=Iu$g|mlNpby*@Ou0xm3A0RSFF&YXrvX7UBs*|!%@W||7)U(ayLLtR7b z&|e#i6$yu0th+>Dv1;YBZ|H@}1rth~#vD{i#4Fg6b%fpt4GGb}Fl7yo=ujbz z7T_r)3_qIJI-yYli51{2OT66dCoo39@dBKj-?ZEbRfYONRAJ&47UZPRA5f^Jey;pw zpr9jEgsMa5VK`v2HABQ{wrVAUY>8gng|W7rBN(_unjhQcr*r4)rGd~qL3v_kYYtd= zk$`O;DNEgDi6G!Eej*uHI#zJ7f{)91({jPVfqa}3S|u7m~L^Yo2vto>F6; zCNWPry4yD7Kf>Bz>r115FQPEi8u~rW^A5&sp{){j3UC~{KCpxq+9sm-Eb1RAif&>> z=?+)mE>K12jLyE}@1^v)p-+ zoTd+5EXYVfV;0g0T_*6T@yIJB5-XrXHf>>bx<(-JL@OQWI?>a&-i<-)-QrvCIpigB z8S^b}9Dkj04){9$fHu3sI{-i@hCALyz@wgvX;UYLJ6_6Up7y#Bz;HMoMKBzH8!X{C zAFD0=*0uInpSwZZnGIO1ue4vC*?z_PG3<6`m5cRfIMgL)Nj)}*ntENbm(*i}35|5g zUQ&+@AvER`a!H*_y75JKWAf9P=f2}dRYC)&i+^c{q#e5Wmv$IU;0A+U+F`U~7hTPb zAI)fCmyNnw7(a&bE}hxd#gAn;*~R!y=F$!`Q{0(F6R&5uq%*xTzKr40E@lBYzMQdc zo!QF9S1{bYGgr&vD?fm$<(+#IzKY=rYKH4LeUXRZ4BK_u`05gX#&yx_ILvMer9o?V z#aV1DTV`5CcPQH!cRVJ0NrLOw;XzXDQVW1#T(-bzXQ3*(0BO6!s8bS+8nz&@>NxBN zHfqk752L(d+@u)JKuIx$iik0c(<=@~S`o>z_HJBn38)l$J4#aTPSAB@76D*}x-6SL?)UfZs1!#1KBaNOCf z6B|H2bmeNibvEZ}aC>c6Y#WA-13q2H9^+}ChqZF$elA=4c@+@Ois;U}Ua0TdHiUK2 zov+bThe1|-BR*E)E}+kS0tS(1U<(ObSP2-nV1#TDL9Y@d3-(7bx_l6#ymK#lE+*(L zfDT>V)XIuW<@a3HGX=2Y^t}st{c9I6ux&H9HXbHNdN5i9R-aSLQzUdc%Wo)K1FUA0bjXTBVRKj z#B;-KdrpozmB%ZlQx7O+#DwBAoys38ygT4aGvb{QzgENmAS!!n4n`odGeA{2MiG;M zxH5>CsfZdN?llN(Kv0wV0OlEs5gkwJZL&h`-?bRwc}g)$AuR?|!>J`-{jrQ2|H`TS zB7pC2@K_{MY{k4jMlL{=Yc;$Yl8zBdoJ89CX4>Ho#G+D>4eS3E$15q>wrZGFW{0q` z+EhH!F9kLf465Rb8fI0z&yeJKSNf8*Do%1LUJfw5t6|E0(U;rrBL$xfEm7dIx<7In zoZ{%dCc*M3+~~p$UExL70NiN^0v91Lih&&nEMcG-fm0b+gTS>2^t)R5&k@0ML-Cz# zAI2cdUI(Xle_4OU?}~8S&TUZyhP&hOdz>t#IwR@Ke^v>+XzPCeYHC0~{yC(NB20Yu z1H|wo6zKEB{WWcT2~lrgsr2MiD0T4+(wc zEUl84Aa@f$nW-!BwqKomiHkF4;yLGRgCAa?#Oyp43Nd^Nxpqbr^+_>#XAi_w#x=hr zJK2!&Ew9R>6wZ42{j9W1y}VuVtd|u()d>CMWew9$UNww3h?di2hvJi+idO<$*6ef? z2Q4461_!LP*1HX=_A+1`akMMXl`GVEL{GNpmwfbw0Qy*q4!xO{+&h)l^yEIpqRTD1 z-}M1*sDpEH7KP!(Y7|X4{svm`o~J|HePEX!`YY!!4m8Ypy8iA5Osap1zn$O8Z{sBBIhhdm?yp27ISmhxqavwCW0zK+s8+xyE1XU7MuE$YSmi8*zX#)7;M3Evs1yB`DVC!xBS|q%<1urf#5zY`*57|objs~n=vxkfOR)!-q>)4yHmLud>fut3Tv3* zMUBhx1tpEc2?!2X1aK?>BW_a01dxrM=eGc+3{A>uuTRuuJo{Jnz8w z@b@K$hu`s#Bc}%<-%hvT8V&9)l{nZ}_zE zAZuRfK?oVw$*s@4ZtWuFbW2|Mmob`DjrFK%UXO!dMz1o$r5W4ST`P1~X9BHZCSQHs z69C8AZG9(gV)jd2lfG@At%KcXo7Db38}PEvHn|A(ng4N^b8-v*@;{D#9?p}gxJ$2p z3dW?C$1rxq|NL>2=im?jhx$cQ{D2kzC%R3(0<8QWnje|G18Dva%@R>~ESIAAr(ose zdqBkh*q%z;bF}tv$CKQ2X49_INOv+XA@hIeSJBBu5Xt|cp^?e21IGWM5s^vlZ4q`b zTZEGzhIafPniEMk>kgs)+i{yac_ifVf2cAtc_`%Zf2ce%`564=|4^SuI@CNRC%eu>jON468Sw4@cH^*_--!IT-YgrKk}8-&J?GC^1yIV3^4&Nr zr<$)bw)2U`+%HG|+uMX*d8Vnt zCUHGg`mShBmT1nVpY-G!&S>X~>vv8VZSQ8ZzW>8ZzQ<8ZzQ<8ZyF7L!scNp$TBq z&;+n)C?wc4GyrTG3V@r22Et84hRmiRL;j{ABeH48Kw#65QM+l#aMq?F0lH~uf@af@ zVY_L_u)k@@NM_TJvCO6+V`kHkA-id4!n$dgL1cCar&)>&sG6XxO+x~vV$)FmnoUCn z58gDCSIPpLhUP^wezgY+hm6=wLm|{nLxuyJhKy!54FfTM(~z*>reR!{y6hr)aMO^! z8JXxyej6Q`Qw^ym@Q$4&2gCfQSUPV@)_>%Iss36ar7Jc414h}f%D@0 zvPI%s7s{i39tJ~!J(M2pTaU&F@oD}tuDm@K?MFDadxCF|Mf(#ND#%$uj}F=fFt)O? z-X4n%CKP))S#OU;hY%Wbq8yv)p>&pgbnY85z}q>Lo(;2y(gRRPGKbQ$VOfXLb5Z6{ zdM-3@C_NjMb11!iq!Vi&9ypYqO^|gcJsV{Yr6;VJcqlzKrwYZ4O+RxeJyypa2Jx&z z>9M&qC-#9zg%{xFkq8^9^Ud31vH6VS`)Cx*9gNtb2Fz{?{6p!nqq@OAoC4j(h%IJ$ zbtuqnjMx%J69t&OU;^jFmNMG0KnKvVqZutMu-h21V;Jw!k!r_|WjI-oy)YX)jviH9 zklAC4)e}-u5ZFJd>!%gYiFc#HD>9qv@$Li+3hb%Jdk`{2$|qjNFb}2EjI5q` zKu4Yr+JJBM(Wmmd-wq{XJXm1QSvaxkdH56#-hsq-Q`{K3k@*-z@Z&h47(al6@j~6a zIScp!6%Q}uHmq-MShJojYH5eEJj{m+&;o429nGGU?{KRYm%fbuZp1s+VvY{I#Fho% zmQR6qC}%uj%BVwciYbKF)UEKu*5#{4a?s|uBPhl_6xhz#KN@irGKKfUBv(4Gai4Yf z4om^;I9%J|kGs1+#?oEofbX*|d5T9M&Nq8OP25(-@!}ZcZ-C=3g6ETQ08lY}t=dWc zP368(VNQ`2VYM5}1Vvbw#ez$5=ZX|4(UP_}$$=U^0MZYjZ4nn>hQE~-0y5xOF4k!< zM=q`mu#MGlxDwfhUPu88X(dw>+!tVgct#brVMaTb+q z9;EVLMH;hHnMy;3%iY}zi-vK1j__q9W09^ODa>M7$xxO z7}C&aM#4jiT?A~Ek9Crr1{p3&KGuhm>s0WH;PFaA)>c1pr}#*PBbDTF8fNj`AT%hx zHG$%5LBTBxFl^8;3+@+2C<-pQRlzK{H#992Uh!#`6|QoLhM5-Eam7`x4WxyooZ`ze z49+2@K<%xP)_t(k9>t#{Hlquy!ZKG6xmD821}}6NPpcx}wwA(gW;6Ol4AISWqpKMG zZJbfgdfr2{C%bVTZ{JG!y~m(MY6L+G#NvAZe@#n5$yW!ZB(Me<{F_le6#pSDJre#M z``BH=o7zQKv`0-@jK9MHo2xLa+@I6cDgIbx(C`I=jXWA-2$B+G?9CV>lQgRjOQDl; zkh`abSqgK6TdGfmf`iqkH%DL0OrOsXNZ>t5gw?Y6NPu2Y_})Gshb#Lz2=m9?y|>WX z_ItGLQ813N?e}Qg>lhW=o=@8zU{q{-K5aW`Y{0e`QvPN@#J0~vEFO}#wq393(zZtc zCBEOAwjJ?r+x85VLF@cL!?f)=MqZxxUeLBSX=~eS0^GN2n6|xDxW%>)Dfl4UGBaY^ zj!u~N>TA5V886N8%~0D1x!2PKdsPZABlE}IJqMc)#(l4+iEo3Ade{d$-Rs%TJTML* zU(An|biht;6`CuPjv~yM!M%~cq}+Ut~N7nC_KK*J|^oaD=jrK-1BRe%2{qpFjf zq}jR(=wDd$Ll#|pl%nZ=$7`6{|5Hez{Rc|QOrtg@PgWv&S?8`|8MdQmDwtkYX~66R zlP@cr+RZfZJntd3h*Ml-ZGq$~0>(Q@NRj-w?BoZGRiXzWZ$OPk9!DhEpb@6@s7-0D z&&~@iXx-$3T5+?|GS_Emn7KY+lilU>Nv?|@2{1etVCW4ul@>6b!|-Z`q2xe-L5TMU zJfamY*PHz`JzlD#=k(@Wp~=R>wq}}3S@m*R$#K7;=Q@WP_gM@E{71Er$5E^8Wg&nl!Eh6H&s zc#;EE54!REBJm2TB6HE1ESAp1UECS{%5X$+b!qsp3fC#_8fYY)WW9=@m!B9EA#Qh@ zV(G@a3>G!(9qZ)}2hev~^a&O{;Ae^!ulc=3#A`m%2)*VXmhoG>CNw-n8*{sUKu--n z1HR-?jj&GihyBr7uuhCsFzdu517@8lPG#gcm8LNa+(GRtR$Znv%l*M$XKWI5mEl5P zmnHjW*nLnD0V+i0Ghu<3RV5^^+(}RgrZOb$}%FAmL`Df@5R+X1hC3 z5EG{WA&qf`jL08He6aMAm4eTo3cUEiAc^lnd`N=&G`n+0Aa(ro9}a){WeEu}lAkAZ zFM}@WDZ$@innvI`cHGXIf^SuXDR!lS3`pj$%4jZpC~*u5Go-NPuC{lj5c?;3D{%83j@&NUO=ze1FSX`8NI%v$U?A<@{vw*=}2P}dfH+GM@y(K3Jtk&TD(Dt*f5=@VKz+X z3Ip21D|`mi9JeVEU2l((O4qwe!F0WcR0+D?^%?mkk7}4Mj2z^7Exv4=Hi4zwStzM9 z)e(CjJ0WZVGOx{mU!rhMWV$Py{li{`Gn`w${lX7B$qvfK!g*fBVe2{BU*Rm#4}3Uv819seQzTnt zThzu;>8(rfmX|YBtFeqq>l@ZJ$ZXr)CLaI1@|XH!r=Rq+b$OfAgx4G}4 z-n`2AgK$ju6p717uG}>M8%q&7QFUXW;^HPL(0su*kPDW+aUB($9}IQED;_rVW~*- z5p64t?!XI!GFUNXlZ=lx%CPGGOo-)yx#VtzGo5#XLNpzC-#Y=4a9JiDam~nKMlM~D zkCjOsst#ll7lhd;or8Px$#NxT|5ay+H!87Hyjjt3{N%YBX1za6NKx9-BpYE_?Am$YRI-^PQ?LY?Z zFpA*$u0RH;`a2m0zos_TufW?-_MZDI;=2cw?gZ2g{V5#G;N&HpDrH;QY@ya6*mpZ;*>Ub^UrW(H? z%AJb1>0du_>&B!+!DK%Tu(iDx$%_vbzUOz3Xl+eJbCQ#ll;eok45{?9?05`~)WB1) z2s~R!>8v7gqDsUxE6&B(%%~;U?m6xkqUkbapC1+_VaE6RSu=hiW_${HF=jLzM;_^$ z@tW`?(-?ojOok-L(zN<(mXwyLtV|a^RGT z#`Rd#bnp!LJ}C4yL|6DNv=bt%sTQym3q&#&R9pf6Sb*u=%QbFDu-(u(R;=1GdquTr z?7`*35BQo-B>ExJ1>baOe5I`jwpSr912xDedL1M--+_X9*PTcXZ?$ykY+ zjToO2tFe`c_BCZKJ!@7g5pIjKh^m#C`90JSx1Zn3m5_FuZ3y$cd789Se66Bkn*skv z!!ogYMkDOmwrc|D*~=V_Q}UuDxiD>v<#PVxB}rs6AX7{iL&G)#lMA_8ELJ-z_@h-UE}86KxM_oUds z%EAPWcr(ssb<}6@lFqIHbOS&LV!@8Vz91v5)m{~v3W;~2OZdY;+a(+uYRE%m`TJwf*BVVc3dz@{gJhXC-$-EtC+JwU;;p{-g*_ z=8}~YOi|MvUo}+N`+48g1SdIO(Ht0lW6&slR6CiRVz{4Np%fg)_Z?triBM=QLG>N5 zQE5gq#jP6Qykn-%;3O{&B-P-<(Wr9W?*>J3l>5B^GJEb({G^hx_UzZN)Sd$xp+`Sr z`0087R4_g7cPf@kb=@W!t2n(-=E3ALnMw{<8k(j%N)Yx9nr0M6fJ#BzjyDu}-acE^ zlT#JV#On+iSuL(rFoYFv41_NUgdfU;lfTt4^LdL+PZ<9w!!~9;zE2|W4OMcr05?GN z@ljpc_Ge0i3~Ng^TCcUagAI0LHda3*J7k}vx-J{Jt^s2J#~o^rYqOE98*l)i1!tUb zq0bPk$|hKkOXDVQ*r7EP%amfYef`B9NW@{fSF3;U{3#DAuf~Z|^Edw_K9kzovNG_9 zsfl;gQ>SAxCp;4)b00%3m@o!MMO&HzFQz8Ui>bV22o(Pmj2-`V%yIZX@~ddo#c{{s z{|*DjWFN@PKiRE16A1o~Z5i9%Inj>#wCah;$H!NFfezYEC^KYIZbtajbeLR{?{!H(JwVeOeGo)uAmH+tk=>PMBqgf|K!!VG4 z?jcn67`m>AIrk9i`6rqo!hQ45AqeyhI?|VIUiE(QlszhIj4!L$vzeX3#ERxyb*C|UIij5&QYO~J!e0j> z{`cq_);DcB$!}ukl5@Y(eK%~iz7_0U*e1!XW2pE#FwY=?uIuroy2g#`8gY}}T|h_l z+CJN!XN%K-hAaS~pUH*HB<5q=yEdcsY}$mm+#(jb*Y+hqa>zvEJ9n7pE#0G-+=q~o zM<+px#g8=_=;Vcf%EI_!3Ta_;kzIxjkB7R^E$dE6b-~k&oMQiFmC~JQp`8@s@tk@<8%$`jVYa zjltv}3?$ztVs(_{ulpb^>Pzx_Gs%}8o)S1UUYE^sagb$~u!QmTlxP9B_fB>2rvfum z{23nFfqB|4mBeAp^%{<&0lrS8!UE6xnOe-H;&J`r;|4gzHw4)3({LHso-)c{BvtfU zKpIbfN`|Inw8PBUDf%eD8;Y75ib2Pml*u2pTB%`bHC{-dRcS^}K&yrTTeF6#6>l-H z?nA4Bw2}OCc*v;+Oy7ZW*dSq%ou>pW+1-X9&s(O+IYmEFG#%2G)#>RrhICS@?xrKl~r7Z1*#+U!2)9bj{b?9;daX&w?s~MyV>!S{Tn&S?a}_Y%D$TCbn3{l!{wd-`?15n zIcnIb#;8TD=Fk7>`oBGDI2Eb<$D@YuUF7Y^m=;taHIHNDxUFXKVpmz2^{r~D2{fsSKz|$UItj&{foL@xn;$88(!?&K%5BGT!_@)fi86<`cmH%*jzCELFAC4EnJfk03bUymFeE*Do zP*U5DrV3&HxVszBS$7upp=AF#2FIO6#4r(Y6o&r%9;__E97@nEfV%!@N{Z~xg9TV| zGbg{3SbUH7PI5ghDW_fKFj5i&MSIE>;R+!6Rt0~X6R)bIf68j5hHBcio*F`WEe63#n&JpX*CAT8iVq&SN1lN=cJYhPBzBhA zu&(Q0rlcgTb~7}>WJr$h=4QxiD~~cu_ViUw#_Yl5)lBDrCX&e(4;GkgNs<4ET8s79 zQ0vza^|Q5>kikoAwi+4Til}Dm_^fQL(`*fz+J3fv$Z{I_-)AfMDo0xV)#pT_YM>(5@N^w^eKSddEM7HG&jpq^XKF_7m7JO*`$)JwK*uXM#fots#7AbOn%cr z1|@JdUL3i`rO-!?#jjp|vrG|9KJg5o7JtR3}t?*Sf9;CI6?7n;$%F zEDXzI3agr0SD?Cl`}5`F(a>eh5#?!feZKrrYR2nu@-9KRB2MCi-%1ZBA_ad2Dq^lS zMmoL#J}3G(oFvkT;c!InHAV^zjN~!wMErY=k^CP45Rb^( zWu)_iNTe{5eXlXn^%6kKqSrCCB8JN&=00Pjl(BvhGdXc0-Ofa`BH}+19O+KLAOPz0 zt(Hg+LWT&3j%CXT8HU%I_dt=nE2w>ZEkGSij`(7=gSUB*cCQaWkw1G*{rrW~r`KR` zkw3e-dfI#&b@OMXmrTJ$bb}2!9n8_6fQ0^sqDoRi-Ms3c1dUn=8VxxK=Gi1Z_$0C} zt)3TPuARl(&^~i*-BiXG&aR$4b>5P?1$b4!msCLab3(uSC-UcA0Z|?67Z?a5$TATH zEVT8@*R5;98R#pX0m9|4j%H!`iaj9dw6O&vj_(tUC*V7;+_Vy&!*lpp!DeB&ZWs*9 zSFXg}Ujym5s$m@mjtgj1lLY;uUN)@iA;59>2|nh<^ih>tQ}87&mJpV`LXs5Y=!16Lwx;mWVeaYpCf9n9-T0hUm@E!S?$Ml#?hen+6U@~D`Xt`zp({UFL zpeF8ufw^2oOugb*mF1wbE^gEa>&ht_W?gv`ib!2)^KEUeE^iMoToPdD291Q_iU30^ zK<4h{WdXM9HOwkDQP`x4-Kk)|iXDNhc1tTXAKJ2D#EIw@*rk()UhM(QC2TC*t0AwW zIS0Fh;YxO5?$PXp&rkJXRzZW?vUZo{l^_Zya`81?PuGbBw3dxXvGFGU6Vo-{=#fN{Y(57 z2R|G5VT6g7KY>`ukxEG~=NuEp^imW1Io7*^QEAXmhO3*^OCRCFw2pTO$NcFsY^h-Aubt;7xR^OFej&q9{8lDh@@atiX3PAZU+RYW z^9)0Av@XS*N>;mQm}Y)iwPRw*08JkaGh<&G8f2`vUx4Ir4bx)$`k@r&06zn!a=0^` z;&g_|8OdHGa->nF91iVHa+|=MJPYu*;UvQd?0XSnLpM=jX#sXC18a->&M!&N;m~GK z3?ochfZGr&xn3#R0^Dzu;&YeX&Qcw0KL;3U#4hkQbi@fuvoJW-WgGe?a%iT-mh=rJwO&dyC6$oa!?hD! zCH0yqzT$bFh%n7l$yP=1vfk}Rwsamiw1|cYhbK!e2v9tCFa<7L{ZuJ#gNzRX6yifA zFDUk5U?ZKx4oJZ%`9q*al^Hl4|7``+@kc8;rv4RuHE+@%A8Iq&g10<0%v!KX7*Gp> z?He6)Mu1^yfZ;mJusGoPwB9-;lH|5pZWP9O0q!>}cQ83_QlB4SxJkn-z2ZXkgI#`d z>f}c{#kXXbDjw0WB)>0%D0xN0%SW*lGgfQQY+joCU2v7@C#oO73qzTZcGY-> z(}ptL>ty0*+c+MnZeH88MaO9M_%fMa$TzwNRNMea;E%g|DFmyh-zc8`=gla_{qs|T zA0fYSA*u+TDRYV2r6Y6~lzglt?C0` zo()W%w_o+hW0_Xj^HPx!FQ5=7*pp56Z}cR0V*88RdAhhgA!~7aLiVAl=*jK`T}#tH zvAyo3JM$ce|2x!7FekRn@Aw>d0uE^{U*(wJ(Wl%Ah{{Tw{Tq7>`WW(hyvN*#v!fg8 z6#$J4Ml^2DIqQy7yP|P3GKs^nOat%!J?c(q+K9$We#L9t3G1308cuM`@AwQ+V3i|E z#gA|&tX$XB+~Ans@xxu`N!UB=tU~+nU!4p$Clmh7h5Ygbrm9@3m2F`un*RUAW8weX z%k$r|9v>QTFESYBwx%B3a7$}o=G^SNyCZs5!{DFag7GC5J65&wMuo7HZN>UL*Tu~$ zw*k6~V^(f=%DoXpj`Q4cEXWr#1v!3v`C-FG4I5rQbbU+fhK5ON8aCk5cqy! zNn6K_89HWk`Or1xL+6YvAKKiqYSNkwtza6udPCFDCOphBboD0eFAbG%;x%jnd~;)S z16JxmBAvi%~z z_?%#fyC_&3$A(YjND&o^p_kdzQr^0uxp55+OP7-@9FFLp3};}kD6);hL%LTK`R-1{ zB5|r8iLYm}Ir~P?m-@@`f8a!BR(g^6CuGY#bQpb$P=BK*91gF>iWk(&-c^dkdt<;C zi&G!Iw&fH?m&^wwuVph%*spY=OD}>PiEfbi(JhF_9bw>?3FEO2X9VbD3F3twk4LU_ zVg-zcopA8oY!s9l%sd@#pV*G~qtaq$*}aMnILgLl_bOg-8{!?}kvQq{Yv;_K;pCON zOd)?J-UhC%cJeN8pM^RJ61bQH7d(Q1(=q1>ZV_|oSl~PTizm1X@$7Z=?1i(OFzNH1 z&|?uW;B{nuf}26}1UEx`f?NKMc0B&&6WsC_PjK@upWxkeK{a)!MybB`O~ZCiAMaq?Sgr8YBPytqiguN*?Dtj&%vjCU7K_^ z$&`h)N202zuGu(wEqmU=x&^31?GljLmVMZlRlj}PbK zay~wsi{`tx{>O*gL)u4iBe_T>8u++yG#5|F0embMPyXyL3&(RwC?cCAFPDT;G7pk> z$VF2^2AzKpI{5M7gOK2rj}Kdf2+R8Ta2NGr9OT4TZ-QTF?2>rZ{RPI%UH^z*iPzn0 z(1bf(zra#-;%$kzNsM&(@!`aK?j1mel35=gPP{KvVGH%Y7@PRJAR-n~XFooi_*f9p zWbX0Q#HWIYCH*r7i7zC{I3Qq`5m@3&0d=5OI{r$0BcMbw`*XyJ5Wb*_4k+n=jyMq! zNT+1>=ZF(=0T(9Q`5bW~UvQmq*0B)>d{@-tvf#m=BTjS;U4sQ%W5XihP#boa2y9rL z^Eu)~xnM$F-=^IwCE_J>K1ZAw5~9gr+#35i;>4js3hUX=5hq3oB$mwn9C2cdfa6K? zIpRbWzA}wt1zmS1klv&a2Rx;It}twB*u*aZ2VJ8gQ62g*9KmF3hKSQ_)k*}}61@VS zBTmc_44mYk7gG}R1m%gDtvT?n`XT|_JZ3&eoLC|VIFO%6#<`9a9IW8uGXAw(aBw3Z zhnK(w7VkQUj=fg0RcI}GDaVlTQIJMiHEhv0S|j1f=hjddcI7vl8Zh+itS=EKb_q4iIW_nVPV*(=#KnS)By+w*oVZNjQR9qPN+g!_zeJq4Mj)t$ zz6BE3iMGBCZw%V-7T<R4Nl_w0x5K&tT~bRcc=l! z_(k1d|HK{MWdIa2T<&`Rh!$eNysBYE>l(-VlvP4wSexC7ZD8*+nHS_WU`B|~%{6Xp zaJ+wh2eYGip4=Yc2h_YTBLEco0PJqBJi+n4dJD;yCprJ;x5hx{x+JW~fRr-il5|{h zZBxs}b**daSFQkYM2J&Cppr+0ye_$V-AUXFwSx%oB!p-2K^SE$5XQC1)vNd>72Y*i zxx(=Z-4U3ZZX^(o4mIIrApv)GPXKr;!7EqPV>+>^UN)k@i5}@qE$;40fM`#QhdfzY=psZ;0@{=L7NW)yCD0Ec~H@ z`Kwzmg=>Tr>Ipac&WZ(P^V0)qvLV3Z)SOfU^q*_$9S9EL7>8_~q0UKhAqH-?va zHEz$&aDU@0wUQ%#iFvi?G)qhtPx3Q<-W>M@I#?3jPrW|i?#-2+vJ^^h!c`9Qs=GH& zfZdX~QcQP+c^q%P`wE!Lt*z``XK#VfR&;GZMer6%q%w(FDD%C@y%VYp=_+|xEO{87 zY{n@oR9tm~CGI{LJ7vWN+A;5F8Tn01E^ldBj^h-NcZ}p_ak8lyOTk!Z_l|Qvg2x}@ z6xGlyPka2xY&V97dut?ZHA|zKW#zi%m?N*kcigm>LNOdK8pMr~>x`kPj^nM@EH7`x zac6VGr2d44O&c24)vrSG4VxTqgJ^`RXf1G9alGO+JuHM%&L<(Bzz$j z{e2A%$J*JS9!;Gy ztFE@1Vh_fd1%q~`TQI@2dK%&2>DJWr?5WkYwUBr4ObZ`cg1>|h(jikY{`|(*&$nyT z?`9jDoA7MS$`i7`#-2!A8GZseOzL%{#8r}Sr|S^(iHWNv5>A@y22SFK;&pK+Uq`;a z&CnyP#vN+}mG|UyGyritVB_5Ypha^|Yc+o5IlqoA;&F4hTLO)Nxkvfw!d3sSIrOB08 z?Oy?VIEh!p0_Dj}pO$zn%yp{@G_Z2zC-Fx3dBlfzoyNi4pG3mAWR68K8w$UN>`X*{ z*^npbIiCSwR=sR3Ub%eZaAL!v>G@d1sY_3(sjXRni%7Y+ znR6D@)h?XjxSh4STc(+)+FFaVky;Jrqbe^*Pn}tRWc9q+)wT80=GCAA;t;W43)VHQ zsb7ble4Q%SDZ;^kRiJjxjQZN@Mc|x0XLfaa@EqsQFdUVhH@gNagud@*P&Kos&&l|G z20pEN3Njh?z0GvmnUP9jbgT}_MdFL_y9Y-nWo#SExB^`~D}!xV{7nPRq3L?NZfNPe-MPqTfZOio`j>#HY>hniOB8 zbPBy$Bhew}VdEQJ)og|xy!x^g0}+XEw!mRx9OKJIe0%}hr!DpP#!w%Qh4OUpIvhkBLxFx9EvsE45w32ISzygTIx~+4&jol>%@(5op{Ho91!KN#K zd(uf`P~#7rrZoP)M{BgS__Lo8fQIq?>~H!gHB2szti?C?+z;7XI+%QMNEJu0sy^ka~f z`y+Pxx#OKB#HhUNlY*FG92i?PYJt`##S*V_iV#R0ljJPyR^vRCX~3e++T!&_7V zA2ras6R5Sw5Jt(FF|y-T31TB=6}ViA*S!7Vv*R5psI4N-2L~4~yraEmA$2FD@?z>* ztZO)4qxT+Q=RhFUFqU_`Q#=}US5h|AdG8VR69u@#OO)d)!Ab6iXP{?zg8|)>%o>pU zQ^ku!t()LWoIB)>+OHMtT{^SK#ojB}hrkOJnojc7d&HZF6!#{ZTUTKB)Ss+5-Y>l= zK9n-8v+l54T-jf*zgK6-9=3&8s=*k{tlPRg)H zm>@!(+eQ0 z1Q~Zt6=(e^<3tiwoRv=M{p}W5#t<-kJUSA805v@lztU1YODg^XkW)1*jUm#5^~Qq# zfUrnpZ7E~LFXI@h>;`r!k@))-&1w=re+{gq=>U|7U|lgZ926QkLBe5{ur-@dqM9HR zkHn9%l&m|Vs!i-Pi(%C<80r5a@vAI`?w`TPU;`rWw`kS`gXU-znBQ3p-QHl>f*Ji) z_}?rID}kXAGby?YpgriVl6}Y=fp8?w9;pYt&Nk6A5f)R?=cG`}*pHWS0mLf0#L~2p zh6$801aW=DHm4%eTbg8!0#Rig_y5G*mjLa@y_xOQ}0PJ!Qli5jd1(Y!v0d{tx6f@*!EZjXt?(4qX zJy~+E_2pidk^6TLliA2+OypwGm10c6nU1^3OZLr_T$3q|Olee_(pV1~QyP_l(x?oS zMx~U-u)+0MrflKihtObQJygnPNQj41oZ<4&q1~Zz+?PCVU)a+v=aU3K?(UWSa4+CE z8uew5;g7cBDRk}(ATFmD=8kHV&5*`bs0puNMG1C32}8{{7o+Dlp1-GA9weD1jh~n>J(6q9fQFA3`{}bZwL$qPYNeowLt|H9*eVk<_(nzJlyJpC*W`^F1tKACO7&B|I%>pT!z0=}_J0RJ2WV`~vO z<`f7$oXyNLN*c4NJQCUl^3*`!ob(SBTZT+r3@|bhYAJW7SgwJ9Pt9AD66TST)49CS zh%DmM6wWlsniSE76-NoFpV%%hCsc&LLB-w#L|;Bfk{wm5ky0CcLWL`+VZ&@?YqoL*D1jq5HuSC z98L!X?t-SbDw1V?o{w~VA6tq}u|3u=?B7XQw?~ z_~Y(=7xJnlOY1%9@#kfU2<}O^J4MEUgJcY@v@&+KD?_$0F!B(jvp6M5XH+=eXEzkM zh8)a=sjit%uj~^o3J(%wXdmjSVFmMwBFEFqhf$-UAjJ7DB z8D;QVABGj-w*5{NZQ>8g@kuu&!2X;3xKr~^gYeY7z>R$rzs5k!*k2-W4COtoKX*~Vc-~uCGIm%Q*CBAkNF~MH%&J)$zQV}Ea}R0+cC_e^@o53b6-_Pa zKuHIwy84&20EzkR{mCA=5(Ckk+RnvVE0;}%O2>DGz1i?P*J@0vyiUOA(T<$;AR?O*n9QE}&$5zbgd7NY}W?U-fj66=X z+7S0ErU5+-(6E`NX4d4Hnz^>>eNBqZ1WhC3I1cCLW=5=tErI6cq0PhL>IcojHsY)X zs?s_$>pCVSD*wu8jy9zMW5N*^v&~p96yCW|&2)p(lYa+sbA_x)#&{FH>o|vTiPYUF z@iP&x<*cj~f^c0XK1D=Nei7D5Yij%Hpr?c`f_`Ja1pHy}jQtRSPUqouLt4nPkJj(ABFtFHK@Oy6b)UBiX^{sQN_9+Did6a?F6+Y6caN98fW`-`i6yXnDT0$d{N0E3pC0-Gb*b^8kLy6b7Be80d0_jyC zbcfT$N23%oHbXO!=Y6hDsZL0%$}F_liL$87@V$9C){pt@l6D zX}e@JQ>Q81ZBm4nH;%G)*d?QxCy~<;hcoAG9&x?TM|@Pi#5r2{4dT4Cd9lcwaRFj7 z54yx-^?m?xvC|H);_(@4rxyY_n*kJaH&SwENhEh`ZSJZ*RE7h_m9<{Sn;rAnSFUSu zuqx{uOiPSV;zXMeKFA0gm$$6N@I*8&JkFGi@4LGX84U|a9&YitC-@EWU_9d%vBf_3STi!0DFRK?JS*ux#_#9c?2#2}45o%kEl?BI*gt;2>LtyFGQIY;L z#H4)YL1>=0Ov|TEo>VOfH)`VPnHunp!&?Zjk7-R%YN5?>C%sIuT*mp*$2#c~72XM4 zNhDynoT|$eZfdyoYn!-~{5iJdO_5SPDbnsvl=;s!Twr(J7;lVZZ;vK)k#D@~##rNx z5#trKS>ufr6B7-zOj;a zK&2e%oAZHja7gZ#1IzH)u-&9!DWL6MA}!Y!z|=&SnUX$41?&L}o8x*RslEg;8KNxn zxaQV~_>>;XLVGwO*L7N_u+P2FOlL?lI--Ec+#%I8YC)%=VW3887o)V=db0L3$YFfv# zDD^%Zj{z9Nv&RD2@p6n_mMg^oxCUJ}UI%Vjm%LdqXm91m?cj6ZK><_?Q1(Bn331+_o%%i|eIZlPrZ>mnvNY>D@<~s_7LFDHsnAzm2pXBP0 zE1-dB-j+#l9i_57q%%_ z@RV}hsL9H3nd{h9?<>LcUIG2EXiT#=Ftu8`k!jBM@qNM`2m%mi!Jx>K|DGayO81*QdW+fsuNU>Y3MoD z%#5ULVq$~mtqo9iW0h%~`0d=#mL`lzxZ*u#H=xh07LWG6k({jPx%3rpADA#0uYbR#V(|{g_M;er|LPC(_YqWVv@Db16jLH znWpAu%?=pkKEC_7bW8h{c(>mcbxqm6>~ZPK?uN>f%(lDZJ`pB*{P*F~(p)_$`(%$X zZXd^Yp9*uIyu($PEy!yB&t(t(dx*1%+9%1rfS5Ewl@N!|4yoZ}5%~C(fZ@ll?JtK< znGEZHR_-`Q?S^x0QUX?cjDU}iVvK}GCjGxlEiMoQyu%E^!>yD6_A z;G{<>8Lj=QksGW}R!K2<={ISxkgHa?*aH4Twb_mxh!qOw_C%M%ZM#I*1oCP{&IZ$A z7CA(a@I!pS-C1zGlGIo<(y|$0&X+43xlF&Qw9NTQ0r;?0DN&L+dceTHHAj6lM_3#f zE^W~mWoBFVY(VH_g>y9Uj>6Hnrl%{M&EeM>c-7hfTpMS!C|pC8nF>8Xh6?#kv>U=f zFVz`q{g%d-we_1D@r(+$AskuK-Kk=KDmj$qCvAICH^NEF*C^FV<{bl`mBZZ=j!nn@ z08o9)AOOA$;F;*GF|_a^>{Izgu~Dn>u`+OmBW(Kq0TR=aM8ByrH=$lPK2kkO!#Ij7MubMtFVH zYumG<>aR+5>~R4w(iX!SJqln}knMmsDhF%ykpcMm3TKVJ(7=N=+Ug-~)J6wp#g8oap;tta zOU2&5CM9sncuHlTV#;5ZAF_m`{D#h5n_>GZi_NTBWU)PD*{UW6*qFO-O{q}TRh!+V zIo(N{Er`sYhQgrD_Q9x5`dKZrM%0KCfHIPu^y>N%PZ{`v_Z0qx!Z1Xe@}a`mgr>jH2;0p=;A2!7L{+X9 zhaE<8Z0Dr6YerZ|#~bQkL0bowg7yb@>B|DyKV8!}71DmHa4P-%0Q@P1(~S2hoSDyC zW6GMDe>y;4rf|x6GXq~TTH!R}HwGTta@US%d~KPNUZ+TotV&S*w5+Q3DtsE?3NuXu z>!>sh2`9=rZ@UC;&YGj8_TZ=cfYk0f^|2#d+Kx>{)l9VVGV6Olnu-tLHRia>gOM9R z)q0(2ntv?(Um+&Lkt4vC=k2n!`7Ze0gEP<~OY62b!sRuL`_hjEd^!d^v=0`J<(I^J7X+)%Ex%#^DuL1Oi2dm73cmB z2}j*2LQ8?+&8J)vcB*y-*rmOf`ktlkeygsNJ~@!f5B`V5d>34Bk#fagN|vgbU!dkx z4arLV+bz~h71sd*%S61P)QPfKtv4Ke4A>1v+0pLNbfB{QxVyX6SZ@eNIq;n6z)kpShSz1+$ZTblDv! z3LQ{h%sw?U6-U_243x|?Lgf+f<-_YMgkvA#9CZwm*uWb!LuAYI>NG=UATl9ZcYI33 zrpq-z&wAtF3|c6HGDW7$oQ)boZ=d>NuK% z)6@Lc?oP>AxypFdH_X|!)-XH8Fy|xd#xSP|$Ap`J$6-BO4CNPle0c`@dtjweyc}XM zZ?{$9XibNP=>imV4jRVNiD703Jq0a+9fGV?8MMzJBSZFx&Q&<=GbIB*<`#uF7+9bd zp#?*1u`}h#0BhAtfe3AiT4=f!=0zHla-9D}*fu7CBmVA9Vx0XdV!dz9#j~tAZxVB! zcr(l?n+`Y2b5~y=E(RkZCbd!1{-!&wGlffoO#~{(V3tk{))+Jx+m12H3?|Jrc24HX z&WRjgwHe5|kKjHjS*TOqWBe@q)6c?_l7+>$sLDiO7;9DD7Et-UgH^V4qO#xgFWr-^ zD{3^?eyxVtcO%@lM8&(5Wbh*YzcB7+B$MwlE}8sBB%FSSW|EBP zu52c^s$^#JPM~r!Y3U@BXJ=>9S$c~yx0}11LT&dBi+hNiV|rfYZ1J;qIaY_wsO%6q zMAh?7WJkKLUc&JZ;!R8Dp*on$Agb3!MybkK(O3QOAqCM4}a z4<}0Pth2Uz`^HU+mUSvHldmRp<|bch$=Ce5Y`&%l$KMc_e31}+j?LGpDv9}81XNDG zEM5Egy5(E)m6Z?k0zu9_A$O%IpM&x-7W+3QA1fsv=iY7eu}V1l-J|&+A&vsse0&wi z$00!FNqYCE#{SB1hi4qi-F?GR&>Q19o*Tn~$r$60LRYg| zvp2@on?vqJTyB}V2C#+zIrsHgjOV`YVO&-d9*=RsqxXFn_~ScLxVCCie?n5n-rW;v zNtk1bp9yRiNTqylL&7+f5iu=)9Ud^KZ`~m8Tet(_!#A0X3Rv0$Nv$wG@5BH?uLjo3 zH9xl?o>JuDpY*}n!$w0H7X{GP9f+-)kBM=#FQzp211MCha;ZLyU1X`Q@ToTDQhgMA z$Wr};RB{r1k5cU~Kx$va-XaCpPG19stetjvfTUEe@Wd2?_}dYrpT!~zRI#B#!K2Y9 zC`F1CCGmlz;GBL5DGn#a^GeZ6B!Q|dKFd<=AXR#cmOfABtpf_a7C4!gK1>`GTNJs& zB2QH$O>vn)qKo%U@iRqV0rdR`p%=WY=wGPVX4w8+gPZTbTD}`FOIB?vSAxf7joQp0OD||b0QXYWc z8lbNTz@Jd~4$#}W%SD=36i$mwRC?3ebIn|q;Qw#--aJ04>i!!)_uiSw zoh&d3dk_eS5Rhd8kxiBa5+EiaF#!bu69@sK2uMK04P2^Jt%cSFTk2A^T36K8U7>2- zTesS}wPLF+R$H;|t;_HI{+x5}+?j;hKF{;}KL0%Pddb3Dn_tYu+rSDHjH&V2rOmIOr zve3WS%DInn$|oBcESaZ($}p1ENSbu2r8XKa*5r3ISGc%W88mByj~Sr!O{s#jIV1N_ zi%zuzn=NwB?1=t2r19w*jdcynTkpT7sodM0u8mXPbG1NYYVj+Kuw5w@-mEYSp2J}Cr`A0u{9^=;juoHK>zACcwrS0}wiRu-Aux*<3gVva>YC*SL`KTWDd*%Z?%iXO)Ku2t zf-~WINvhZ=9`%2Wc#JL@VmlF9vaxOTvNao19vZwE5mGd#93L=$@ZAP?Cg^zRZv=zt zL)r`-sptpKsnXfAEq&=rxi}5P*DZ8g*5RMuyqPU32W5b7-mI3Zv99H}>(R?v^vziF zmw3o&c>py0=2a|{r;+3*vD;aO{qfe-Cn@unSmD57+?qBeKZ#?UWqjE{yK&U-{?chZ zkhA}8*4cl{ZAgaS{NXJFP#^fso43r|`K9ZAxwV`4g|oCj^1!e6wzK?%))VMPPuc&1 ziA(Uis3w_~Y06 zjkEM(VEOf4a$24NjNh(vm);K$zqyGl^;euqMAU+Q=;obSbLJJz_#bg;pK`bHUpTf` z8+8L$2k91GI0zLl<88!|gI@yj-@Lup&u~UBuk_W<=p)s_+o>~pS39G}U*L>B{Nm!s zsqZ6M`{Lrr`IFFBMEs%n{jcAT5bgPoNw9!GaCDh8LVTe~%8y z2dl)z`FpgunW6%Z_OA74@1}dSkN8FCq+(g@z4%0|AIs)DjeP6SK6ezvNK_ou$MP7D zD52LL@UxCNE5wksu*Nco2mGu>WbjqokN8wS+jyS$FLKD1L)Z-nbq&Rh|DTZeuS5t7|6XcfDBe&>=XPpP2vk3NL1Wd7@*2G9Ev5GCdDGRfP+U9< z8pne`4G*Ilo2;VnUtL>YKBuZ~j!LSo#&q^7J#Lz<1) zR1;DK-tV0uSbXG{Vu|9t;XJ^mmVX%|Z%M={F#f{5ea_23x&>+e!o7EeDq^95OK0zW zK}0Pg@aK#TWhN3U$n+QPeIkggg1}$6_qinL17iJ!dtV4Bn_5-q_qBLm3n;fB-Cwxp zx=g1_LEtakiwdM`LAt+i&lhl_fUcKkguN`o?NN^4@&g}xsV0>27ggkSbN?CGu!nFM z8x~3gHmuC>7w#1a#?9wuls8NwUO|SxaBqZ5lf$@Gbd}0J*c&aRuwFweCQI!rl{Z!( zSq16-!o6_<_VX7ofl2Om2ukEnX2DKzIWF}M@{~G?3ssC_uhK2RY(`g%St872szxHn zlxP+57Vgyv234fop2RhpgFUZ7P@Wjs8Uyw{O29UUDR1H40zshq1c{`o)?&fI1_3Tr zyOszJl_xZ8&Y#RV_UJZEzRU zF6FfA$r4rtJk&|K3Q^vvBFcxT7K&o+u%h%?Jst-P{EZcRXS;`EHl|JeEm78(`h1Bv z`7biD??`Qcbx}`)+`)$1gea0<#q51wBGG~jm*C!|0*~qXcDY2d3Idnlxaq{kf|eF! z)VoHMGKRW7Y^WOpL-C!%(SFFH%^lv|9yAd;%ffvIIpS;JaFRuZsvz<lSj3lyN42wi_n%+)02Q5)vZ&gX z`^9De5&=Lv)^xu-AG7YFf|Rp+*KtT#oB|n2*CFYIg0QoDH!8$sVW1(833+`%2WR(g zuJFw7fH91D!nm>^?Cjo6I4+c0OJK-5tefvl2KZ!xTf)xn-2z!wY$?!>(;CS=MDkV* z%yf3|_I7B*Z3dg>?A|>{ICo^=P<56mx1aMKbhygkQqJz(B4OIYb}TJLUKHpKb~tN( zq9AZ~?+zDxJXc_y-Mfc6RXyRo#RA0Hy*onq_65Me*}XebFz*FrAkOaHq)6T0Gv%|@ zKGBT2FjkPt=_&g`?%@(mII8;)_JzB>k*III7;bi}oZ0!4S#S65T%j$NQCAPA z<{?VtVxHiJ6=*Ln?orNb&~ya+S7SJF=S!ZF1=bUgyad5r;G72Qm)T@OgO$5b)-e?Y zf%kiNk>qZEf%P@-9_w6=Ca_3#zn*4#%A1SydNG`IS4iTwG9sJ=fzzuDxq;2_xJ7^QE5c5?$fr=OTA~k#RaLAnO;ZQm!Jg;Xbl$k z_ranfs#zyG-P0s9(ItitfcDd~2{}nLfAa=&FWFc-?KpJI|(@wR_l$ zcCd^GDJeLZRnDJVIj4~e++aly>;XjtYkUx4tv0v3Y7Sn+g-$pUn92C)XN&jxN1D5* zG;Fj!`g@yoxwy&}AN?7SbRYfcNb93N9h!0le_AFY@X?=+&_4RpVb)#orgU)NOaA0^ zxc1SX4omaVpN_IV`ZJ+vKKj#=9?89wMNcj)fKFT}7jgRt< zh`>jAN0jza-VttnlxLgmkxU=uUTM}qD2Hu4{Py9XQpmbd_%wgGL!~k}L!*#ambF-T zTgclU@CsYRzZPS7#ODZ}#h%GH6L)KG2B9y`#N9azD_>3?b%e_a4#Qb;SipfsoQcN= zajfyJGx7Kk(tt7KOguhR#(C@khMbAVhus0f9A>F2x>=ceI4a9J6VIN(0mp|k@$3rH zC_R&CSJ{;`K*V2XuBBwpWIP54#YB8gQX)P_i*(1_s@^@{Ij9%L4X&0_SNzdwUm!gg z-!i~n`aQRMR=*%?dd)aQdPj|a|@6GP=*?Op_$WP!f;^i7592HwUKy^_`IWi$dgz0VN&;O?`=S@D(Lhg9rTXWXt6DFJw|1qVzaXWVYz2ov1Lniq1$?H&?260G}80}46g zc1K6p*gorN>Uald+-|85U^*P6mvYAKP7MoYDoRQv&uGslR(36VZ*Hx_&`!XlBarH~E3@EkPJ!eh{eL4Tb^vzdg@%$}ur z)Y7o6Xc~5bT27d7pCuffPAE~6AQO-H`5+Lj*mgu!o7mwN!=|G#GJZt-c^1R!pTfwf z3Xy9pnk_-2c?1N^MHa(quQBYwwEjl;4VH$DK+}ks4Eh;B`>?i3_963Kgd_6$kv^<- zwx4zpmVB|!Nud^U94zE)#VXp((o~a%2^2B}aXcT3_~Q}jryIB341)^~=M;eZa}UyK zVi1JfVjLiSci?;4y@*o;?*R}L(f72D_uql;+r5ZIHIUv$-EA_F7+_{DEo(P4;q6$f zT1&>^jR@R4@VfSg0K9JOYHlkGaqx2wHt|lF_mj7%lx#%| z0EL+k3^qyV@gUgG^4^Lu-`=^PJcJ7s061etxV=SB^}V-atYkwLb6upvhsc5p5thu5 zUuuLDP&gU%F}(E}8Y;Yh>eN06Qv0W*re*(2(m7<+lGQ74H`@DGjJYyN{VSBzzeI={ z`VlPRjPjVS!#6Y>B2Ryf^4Nk8!AeCrqvg#FL$YY zVNJq3#-ls>V(t?;V?FM}4Z}6+Qehn)hseu-rVgk8q>T7v&e;tBF=F?)ik^q?p}G?oe^Q#J=ldFOH7&Ilz4E}gLKA=jbhhin0LlISS zNjMhqxmg_XxgkDAXD)344`+PNF2k@%CyX3=1Mvvn-)PSh9ESVdi;O&D$Vv^_$55{n z`CcpYzwd#h zk;@P(VTC*Fe#GE4+X%7ah0NcyI}lSArzHx;GolY6onzbuy7fak!Aq-DO$ z%!l-g&MRc-FIIh(!GXxd>k<$JelJ0&^alw@3B!DEXi|INVc)yx z>=n3V`c39}isbo^T)7OChVmyilz}EcZ&3}M;agCg`8a$EkBFRiNPT#*^!t@E z20*5?b`nbNvEj?yPJWd1txVqOJJ{yFmEDpaHkQi>BDr6l%KZv5=-f+C>)S?sr||I4 zIgYee-{U1>ZLmu6DpopyLCL_ONSmr?Eg2InyQnC&n!0YuMrj`$adhKV&WBRQiA`nT z!c-c49zV{`*GJ+xS1H5~r9Rf7>P{0EyB|qCIQv1gZ0TA*5(xtzLR<<`$9FR>b@*e4 zvOYvFS#}yT^{Le9iN8Saijw_IxXanQ{sUyVm(q2*s4$()^eCg(RjgfKI>SMcbOtFk z_+bP-2Emd?5O@cH?T;exdjyXBB?8YQF!eEb)gog>9ys1atfChJm!f7=3`F2w1S&@& z;BDWsxnd#$!=J!2uMG%1drFz;P+5rx9xya2&B6x1S~db}nuUPRUV)$K7vkseQ#JWE zpq;%=!=cdN3BWf%Uh+W%s-HyQ4g{t>g~0U)%zPRF@$!Sf3^G={2=IM~RlJVCS;j21La!#GDt9tF4B7 z6GoC9Ag+;{)~a^bnL1H+*aoK5ti9lUU>Nw9BgygLpME|98&B7?Nlc-gdgpo&Bp(C( z1P~OHhf7mCqwaCnXiHBXA4A6@NkCPYis7z&XD~ zak*#$m3jDyd;7agSNv4}+@u~yeOWhDYkN9$J~Hk-V;;_|5mz`hycMsiKM&FWB%Quz zj+ROK(;#9&bmI*k?z>knJwxa4JFv#)MMa^=HtsM`n z+5MqZCTRM|#%*4V36-QJq^i4ZNohpa_9&wR(27!PttD`A);Ua7Ums$B@SEB9WgEl5 z1%SI*)lkY9GzlYx8T`Ox(3n2&K&Dh@rW7whO$jSLCM}bqct*;qI$`*CpeU*|KX2t$ zk2LTb0dEudk&%thIWXRQ;%irg(*1@so2~B5EqK8_!&Dlk%H}|5^}VL;F#GQrRZRBZ zw<5wd?^M%}Nq^9AEvS>4x}G(UHPtqJ*1Fl6KBJ6nU!baULkcz<*&CqaPy?q~&JZ{q z!O!$kR!t1Z7Ndg zH#Q@9rHZPKhl*8UxDRJh*9x0ORr^th_TSJU<5fl@Ho@sys_Pf4YGqm>OX6Fdrj|4# zrWE-O+cMF(qZ_xn%xv6<;9z&96~V037Ka*0SUuf1(gZ&d63mjqLW|2KnQU@eB-6M8 z75yW^b7Zw+cE4KqYVWi~PqsYbv-a#VNP*KJ`Nb%@^Tg4ZesI0-WV@SsU$ZM4jTUcu~v zKw+pvOsR$+8Df-|w1OkO_D4|%=erwM!SZQ4D)JaWc-c5iELnC=86}}^>5sFsThdy7 zm{@)#l0r$)z1nb>$e#fqGvHx}z)OIsa<#`9QLLR%DBKfS8mX3_o7%%_!>4zp+EA8M zn}bxe55i&P54dOVlt~`8nS?(L^02?e=AlgTpkB4p`*N4l`zFNeWO_ft<&vCJ(neW{ zRk-Bk9J^GO50x(0F%OYm>f207(cAvT8LW-7BsTpuW01rc8l>46WbX4uubz;|654=Y z(_1+cVG8NwJ}^Y=vC0jh>9PK4n;8o9Boxt?hLqjHf`C-b?fI=T$@%8AblAsnK423n zHB?E=DX$gEBc&e{8V>)bBZ;Yoh~2{jM%;RIxhEUAE?YZCvpJPwEwlYAXG{}Otg@#H zi%7BJ$+6u~k`|Kq!78c{4i|IBLl@^nUA`vq*^Vw?+@-{3jP4yyl=6KPB{0qK<1$h! zE?KUV2iXpO-4^^hDfl&r>w;fz3Vw?z_zkAu_n)B){v;{*Uz1)6exoV)_oU!YmRQ5@ zO~F$i+{Lo<^w&bx8alQ^Yp`@;wy$gp34mFW~8^wz#lzOdU_VD6Fkchvl6`{3`a_}mLZi| zod&HgG(@aK4lJX!QngPRczPvDvqokm(tUvpA>0@a7jf#$&H15}#$F@-DP2o2h_oJN ztH}>to@e|9`#!?aQu0?Txkty;HFGv_2rC{GTi{xYY#Sr zo%Ewt2dOz(xv7;(^bAf|OkYZUrIGblQJO$n;`tUB{r8P7WY%Ab^1F;W-wVuo+c<01 zUrOs6vDcbaKRNq2YZRmFxVwF>wp#=7$(zx_tA9s=ud$=cIb`#xNrubp?JdM<>lI^IHeGFm}s^i5X25b>kJJ!H^ zpf9qbWf7(3nbA{@K0E1}-g4^=?|4a)mFf@#b;jRzIU#x;S*ER_*o6BU!%#jm?3xO|_EkPHrOve!@;xY^P0hsZM4%_$r z)@Z{nsV7j@su`;b-IHPE*X7$~qBpyxk(%Bar>aL7FvT35E~dfOds#ZxHW^COTriBu ztQ{32r4^?d=RiutpP6kM3DuTHa;S=)k8oOfXFOEx-0NLsQkfqZxd+C$X>t&AuN=gb zyrnyj`^8+>AXf66VPX*<^_NftM(J4InTc){LF#;MpLZiVWoKt(8WOhNrMG%K4RhbN zx_nzsl+H)IQJ)fBAV)@=;MBzlM^Bp;Rdg#xvwG4I_dEG%I6YlSd z7BBzBl=d*dF~u>ZJ)H-5eT{~R0i%RXx>s z!AL<1mydJ3_l{L%57VP6?=V1B2EJodsbqkvv>{L%x!}K1C9?4b?7GnTv*={BnamOk_I1hcoz}cu*X?SGgRb+$f25H(h!$>;r`Bu8^?{EH&)`a{weKUXBZcUl0 z{%wf;tqgX(tWQfmX_8mfZy3fa(W8828DSty-b0w4s13SbRMo>SN@==C!-Jf5lGGEn z1a(f?Ah^kSSx5@~Rzvy$q^R0IhiDH>CwARuQbTpEKHs!27VdtN0h!07RR?e5UR$kx zW*AroL#B#O;WeS{LnNVXHlgZY8ZK7G8Jdf&i~GW=`j4hsutQy}ky5#_CmJfT9fAoK zDW+veI`c#3i=yUoOQa#h`rLoU3XN24bDAAHO>S)}ITn+C=z(3Uj64w)FN`q#J@B;}=LPAY_Zwv%M^W+P?7XH7V}eWqUX&*eeuK_ptUN668;=)wn*I)a z2hqxT$s^~dz?RBgo3sl(%K4r5Q=pG}-wqWo>!CuX0=t2UdquV@8t`4j@nPfk5kzIf zt1+s}444&Zf(Gjn#({!u$C%Xx`;Y4lJ?qgLp|`fSDM``RTV6JaF{<|35SvsV={C|> zLfuBOgQ;1>XWkt7^{)u^oUVt#B}q zW9|m|5ubO+q;QxaDV$L%T7z)7a4=!-^kS7WQwn64Nj_B|56!RzGE)j<8*HcxWR?_2 z-+v%plZS>iJ3`t!5ijL>G)M-XO(Ks1Q}Cg+es#$DuL2YIuCmsD!ze)O9}E}M*C%uFv-(5yH|HDt zfmchJ4|6pwX>V!cVivi}u9vmynGs6EdwfslLjq?By0jgM>)^>)nw2gKqP;&s)I3Gz zoE_nVH@5>+&u85B7(LM&$;a6qxup_@cni3{fGGJp1adz`;0XjO8F;`3b|KIPNbRRa z$iJCTdzd-c2{qPYoWuHGvcsxNx{g%IkI z{TcMAGXf5zNBnf|T4XD4Am=fhTxRN__bz6_xKh`?QVTI+wFQr#yHg^|fs6P{@EhfG z>d}P=EfV)W@{_aMS!8|g*#DegIE&j+kNI_PUX<=cCufgyEd1oOtldO+Is9w-Hp;vS zuQ+d81>e!QbSe&fauvbNKY|Q?y=P+01n`^lkfX*N0kzbngJ8w~L2oy0YyKNAH{aLA zduu;kzE>B+92s72yn}xQhOTWQgTGDrox8S)42c7oa%~eSo=@Wcz_m>tdX8u;aBUOK zo(e#gacvXL9Re{D71uV=JjNqR=(TH`*fDED46%h3mO)(G#1@gk$6ecqPxa%*wN2JV z4%xErhV)Aj$XN+w9&Ff!P*UE6KrW$y!<*pwbA5r18N|lgS}%2NYHmaMoW_~B&Ng>J zeWl!PYpAO^5W0$%kMf@7V^@>*ET z-up5KjiH0C0{{1TaTksrme#bcUV%5b`foTtWxf+|Fk+uGp1WyntMcCxgp)9yNc?>c z-#6%zkjG~;RxN4An`7S;eJiTGdo$wQUVCQqPJM!2@Xzr7JojnFPrH^QmW zh+s@HH^OBsdDc5Ko*FFv|Gp7!-ME>{)>19{N8Z5t!d}q*f0wPBYAb8ihV=W?bL#$+ z%huMqw*BHw6HC@_Xjc&_>4wN|>|t0t2g5d9#nn{Kt;CwH11{sfb-=^><`qr!1=n$& zFr$3VjLMoC$O|sr2Yiil%WG;>;94($r*6Rq9`*uUaEUz@)ZZX~`bw|P-rC4g>_K$M zLgQ@s*=wTx>Z&`L@yu+ftZbS-ZzkqXo#aKZR+CQjhTFNOV=5c!n(E7ER9DW$l+SjI zsSD2Gm3FRwdE`!LnZPsmGU@rD=&pKBWmj>9L?S&~(8u~$ORIo;M6-eq@{HkY`D*3g z7I_|mBL462+vkt?DdZ0T`|xMAuuQ7VzdQ0g7DVhr%y_2!dj+I0yz*kS|3HNOq@M^b zt@*nn-v%U}kg2Etu*9-^eiuEk|Cs2St95-=bWH@gdLhDw-CgJEcM|EH;0lcwl$HOQ z*r2HA18&BfA`SvRU$f z1|WUv9P&0G4WMiEEX)CH4f((0ZNQd{y=U(a$l`nj^AhC`%%a&;&pouu(5!n9i3H`Z z8JaNS!Fx!{QstLsy#U6D|1y62aB@>f?m}`E(xjQ3q1ljMmemDmMEvgf?K2oZnpfER z>gLpzbt>T2ShMTq*4NCN)l_*@CO;j z3X|y!;duzlrU6GmfUL_LbET8O3DW0s98wAGb27v-1J}2c7 zpR;joPxoZ!HXypde@Ru-jGDR`)lIcnh0U#-Q-yuDFc?dx8uqUWvn~v3eF;kSc}zAC(a^>I$6X8*L*XaMLY^7V$g4wnAXKvj`e=TcU%rh<|~2My41O|2x51cB~V9a z5yajD-b`l^ha$y2iB6nFlmPJrs&WTs5kx#^vTi%Az*)p}AYbnJ8@3=PvK*1U3FF2g zAWe4>L23I~-_l(~oD1-N(`?dRM6f}9*4-@1J97~sZP4i+q?hI*LYkwadjqzbLN0sJ z8?dQK7qQa<3mF3D$M}o*>=+{cR!j9DsrUmRSCSF`Rz&)+wOH_z2#Z9vkwP~2Le8NI z8_;q=|Efi^afHxR(9(QvY1l$E4ZD6VCrsE6cu8wnI-x{Of=nFef|imkMpU(lt+g1| z6pfLgEaIPUF|70{jLc3T@>+{#{nuztP=R^GVp!QVhW(b--w6M`rD4_AG-4)$b^z_e zIx5+R%p!#0KoP~!hjq>N=Hn3-3$V^fp%!w2P&l9I8CkO}%@)!SSjZ5>ai2NjuR`RY z&(YBr<;;2*VZ9%xa;iAz;*K3RHdRgy%hK=15k99*Pg{z}mD6w`mAUOMQBX`iv0uvQ`kD=amP9=LvG~yBMmR zT`^|KITJ|jJz-aD2NE5EQ?@$#`PYjoeMg(Sx%zRDqJhF1A6^x zGySIZrhsF9mNPxzn6EjsE%j))#%l&zTYZg~XP8Wbu*ZlQXWR0&mL=k4-RYLCzF!8N z@m#n3BDXt#3D)8AAV{}t_6#FGgTsfeu$9w8=Ap|GA2HXk^{oPdeL8WJ$)xV+ZRdka z!x63kn+?m>Af?ayBBj&{s$Ds6%ChPTrnru#|C4ZjiTDsq49o!1b_zTjycJ>N9})(= zEucgDQ`L7OoZ=LHj&oTSbNnEDy{mdom$Z|Y8dZiu`*WZKa)8H$k~bOfM1X&+!Cw0w zVEH1jSXEmTixOAnP# zql^h3j;HJxi|#kcYz%A|#cAAFu~jTeD}N7J)+X?yG(o?A8WZ#YA)auxCOG8cGLb=r zZ$a`jK}cy!*QwH_6Ag16n3FS2WHBNyYDu)3O4fxC?^(nXs62~9>_``nW;gitAdurH z>M6G9uJW0=!wU0Jo;OLwaMl7aPI7yb6fhh1ErJ@-vSHo2*468qcyy+mTO;hx#($TU z=r&n5N^|EmaLUt3F(ygnt9(kHfG&&P1I&KE_!o2Pqtc~Ba7e9Ft{1y9J$TlTuui5i z%9FDp(sJfT*>b4eJYgRqFFC~fktH^9%?9}0I5|3L{Bf+S#|a~n*9+mM}> z4ze}tPN`XEp(g2?^>a!6O~fZ_m6db12wC_qf|PTQ#O_B-S|26Fy=GJOrbzDhMO!Z` zla!_w!t~FZf3sTRBpLTt6hg956=rl=b!9(|GaY5An8KWEw}G@JS@h>cyMWhJmoah{IeQUsOg zG$89sPWk~Xza6o9#L6E;;9LftMBuLsyoA8muMl_xf$t+w@izoojmW7S8LLdBp7J+F z`%``|j2CZ!dRi_5?$=PIatqLNfh+$60uBLaCYigLjP4@yn&>Pt3R4rA)YM;r=G(@~ zdr7k>x*0;Iy#x4JAer_D1b#x=WPhW_N;KljKm)ts9*-(H!NA)AH!!SY*cgs6iO&W* zKhAs6BL+g|FyNkq%&JU+^2306511p$5hy<_8Wrr5V$R5a3Af%q!oI}^e zS!>mU%i9pU5wYp*2yi?( z;#>sEFU8MZfGf9vXdKweuOZ%Z)J&Rk*5zf)z1l^&Ph?Gd2(T$YmJv|?6k_d&mH!rj zml2r07lF9V9N$&uZR^Jh1wsnwR|5klQv7n3}_l3g_=)x}qPH0fM`5QTapLeqe+(_20$R z10#+a&X>$(7q_%Ql-{$)8<9Czdm9+( zVIGDKc=M?-{zU95uW6DUKj$!iimq*FC_nO_`cawWw|=k5KgLS=+%yzZ9&Uv?{rtxv z?D9CoSMEho4<3%0&IzsU?Mqf*wmH-P6|fHgtNXoKK3hy#HZ-JHL}#`eqmz)2v&ipKY(~694w8^Daj&6j?t%1|`bkT%m=wvW2FnVw94K1@%%a0)T58T- zQ*$s^H(b*HX)ZiCuaY}L(th?0(kABX%8Xk`#%`=m&!nWy=xgA64Gfhvd8mOg<JOl(PeoDtA-6{cr-X$F~ZvLJo% zW^iX4ZfbX_;ieWp2uXcL!^8b^n$UiMUG58Uxu_`ru56U$D$To6=Rij1*(P!|6k_Y; z)FxSLswcIatmR7SZ8UJ^ecd;tS7z%%=~lxfi@4iOge&6fw1}LIAE}EYxnJW`NIOnI z_4%Pzky<@y6kwq&HE>phmqLm?Y2Z|>&!PX`5Zl7t+ZhT)!zX-I@?|6A7RZ>UWkfc9 zreaVDciPcS3f1SKlurAGl|CAnv8Rx=JW zh5KUX#O{X8LJ7?mg{nb5`UhQ(2dI+UGOFZ}Pa1BNaPpraNejP8(qkFfYZziYj?prebQ&6Y{O630ansZ} za;{7?N@Q9YS+{HRmCDXmgH(9t6G~;8aPI1m(j`GkWhNypdwN*5Y?|3=$+{)0+wmZP z+=5=!s`t<8WlFopNH2qqIv-Dt#*|oetrvNhpwAx5rzcRa_)JlDE`|!pXQQNkI^vUc zLfA5haaa9mg7k5vb5!i7%zmDp<{T}F$_V!g(t+PQGl!nab=e<{GTS(8EQmcZ3eARV zvLWCuBT&|1ix87_*gUSo^nmlJ;oL*cE2CGFlZ&w1K&z4#%g*Ospjewx`lUmzDw9mJ zMqnkp$3!&{n~>0O^12hnmE$r|{5KF+@{u89&ydkQ+T6&{wa0dkDmluqP=QI1Y7|J$ z2r1AIf}ayg;=39i?z_{Hc{|+t(Cf_jo?*Vm2m~y7rGa%h2)A%k@Y0_eI6H1VwPmr$ z)OLW%XH^*0c}0?QrB!At_DnI3x>_4fj0thh&hI4c>gr6XN`tzX+0BoDz=mRv=^%r4 z;|wP)%2{BBRV|%Z)hW=khA`DwcB@JAv?$JC^ zu#hW-o*DS|7$n>P)Lf)jek=m-Gq4hYf_$zX5P(x7QwsH$7?A^vfEkv3Hi)Y-u}4te z5tNl7r{p#xr<3+!(~^=bvLy-Kk2XBC#X_WO8%V2xGn?%xc*zC>e;RO>efw5e)b`q` zg9^;JUyVIyXs0RtfeTeg(#Hg^${EY?$Y9Ao3>j7EAToTG0io~264#W8v}3hQSi60! z75a_{eH=oQ(+nB)F9m@WoSbD4Osz&EWIohr;J*dD)iPY=sH2vKBn2afK8=yim+rmS z;BDf$vW{45s8)qKc+5!FFuy=ddgVDFi+gKr%iJDP^TUvuSBA97 z0gEZGl7|hvld`umGs<2XEK`*R+gs&R(W5U#z1nMJT^QtH>|vP7IBY$RS+1XhxGEES1jS^CC^^E2=p-99nT%{;f5z~zMEfI2Ymy!Y z&MIJF>gc^lbge;*5At^=HT4Ry{)VOv=Y|BfYk@p&ICuwY!}TGYI+{mtyE;gFmeLLb zYEE}Zd(7ae#xF9Y{UwA8Hrsh(*R*`iI=evKC>3kJA?0F~A7|&=<7~y+C>85bq$bPk zjk3%h+rv?F z-b608YoynHl>@Zbz5{=HM*Uku^&Y5h??9zW{GVv?rg-(F*(|oK4pP3egDy(Ww(NvW zKXKG#*9 zB;sl*&d%8rt)cH0A-#GUL*EnUzSiFn)$_9Z;#|W2vX`S4;G{?P$nKAGkBp9P4wZA8 z2jbi#+Xs@#>4`rmh*%%pIXon)3@tRJG#?sZ*tR=D^+rY3_{0QVyH7_U-Du#fYQ-t| zj3*4dT*G8WgR?{|u&+;*$G1XAvmsy;lp=ZE6p1;74Axq+jSMFGqg0~Fr6Jjm9ay$X zUJxSu;=qKW#6z}TB(rZwsXi9wVGBPEzjp1Orh9NgQ_|b8*-imw)6*}SSbD-@ zOvn0hv+T$ujfCTM^*|;22;_QHyV++YTa03phIq5j`f(|va(;D-#QXQP4f8g+D(7ym zXT#hj(tiSENtH>0wHNu~1dHwPB&29tf>~h5IE2^H>5W{w%-~k;Ya;F{BWX|2Yur8A zD*Ku!`#KU7WnUNNZafH!jz+eW*L^+!liN>M$Ulg<2N9d=68naz&U%e4vi0jWDQBNA z9m?a7kJW|gP^K(dg&VQUHZ?6SCM9j`&%lU42hT{MdhYlIexZ`a5ti zV34fjYASo$*9>GE$-ndq4>#THl_W1Rf?2Sd{Cop>j^wfUv6lQRl3y1hFDbcED`hGL zdo;8rtKDK0?`dFW4dW_*KDR}a;>H0QyQMOf-r`W+T6R_bV$G_ zIo)t^K1n|~IxUsl9Fo=>mIeHP(&__gHs>6O#%V6y)r#g18kt<$&k3+_9v@2UoNq|$ z|Az|2UAw>Iy5BX15%p@O4s}Vq9aZ)Tx_P$!L%m)9f`8ULmHi@t(;OxbFJYn4${0YNV8PZ z{1}NW;P&=7>B8OZ%_ZOKG)ecQwf`=~aO*un(!Q!g+OwzH{2n1`k1DdwwK~q`x&m?0 zr8dyz;eVqGjc|bc2WLXdM3v`^ltqCVx?)QB~60U|EN4y|SwiZW-x`f_ZSM zbsc61(d?w*!KRgboShd2S%_w{p zTL#Vovs&k~AUbK~43Y<*noXjw1&Mx8X6-ge9+i3(i4Nz}7n)(>Ae1Pd$w&Mil;{q` z_4&x)Y@UxikGOQSPB}Z;U1m-o>)$s`Vnw~cJ|cTOQj+!W=!4Dr_cR1l@?1mqX%#vE z(7=GsY?Zv%fZ20>&wxWu_t=!A=h|rc8kr1i&>OGp6`wUS*lDwPSvIEu9=#b6eE5jj z!(~C4CG!lNJ@2aq4*J?d44nKBuX_{Sb1>i1b97btw58rBXR*)+BEknVl(MAJB`*Fit9!C3a2w7v0r(5LZA!M6D>iHBNW4p#6<453e6@!#w z;WKWxggCD;$n{pNV=UGkoc9}KyN??h2F@n?e~Ik`(<~#+c2}?wrFN) zxJ9>?NzT}CPc?9wu-L%aaK9g-PZ~H6h;B0Qc5E%x8TcLzlYu9>+5oBXml|id~RTm{5GLLB)}Thc(@kBZ->ON-VIrZrs1n1!=)TC#5dLy@5?4suVZ8O>!V zoLX$EA>UYleJN87OUeuTPmqy_t@zuj&^Q^kcj^?{O0qlM;A%>dDTF_ z3$p7?3Rp?Y2W@H=bPG{XSNLC3Bbq|lHOkncHtQp~ceHwSYYRq(%d*!R`l&&4eQ7pC z+cT8QvU!H`2qaII2Q@Fx=5l_}FvR(KDA{?(qmcrg52!R#O28hNu}|{WkbRzn-cT!C zr7fLUsJmfOrH>gdw!Wmlt4uP^$ltXHX^Q;~oJ}rR(4)yZfNph>)L&@HsqAmHUftxb~ zvlE2%iabuXNX`wGwJu+>VU=7>T91tyhXt&?gZXR z!idIi)PLbA%KeWWL-{WHg#Y7?pCTLZ;1V4_d3enWIf?e( z)HyEXy{U78bni_$X1p;s;6nE?3*6tsuOjxktoJ7O4QCZinVado$$d)@POkCZgm;f) z1XnHzQ{J20cZDiqp^Y1sYPU}A`+|sCMBu&2{ZJ6G+)VFH?k9rC$_>0Xxt~jtJ|Nb6 zllz5$vZA-oMWNXS^`6R6VZHU2f!y2oaPoPS|A<8mRz%4 z%yU{5?IDu4YG9^YsAzA8M%-qw<`$XJ=^)|Uk%6P%0u}A&OopYeGPsmmsA!Qe?a4Lm zPv4Y|4tCg!Jdqo?g^CUrdpwtGCw$REoy#F{uLX!(sOSjc+ZO->w@}fMf_X0}191x# zO^Ve0`6-tIwlhPqjTNMF^5ynU^l*vd#NJkLt+Hy4Ryp-Px&>{&8p)8#HGZL@wPG

l?WXrpr-n2W5bu&ad2(a>|Q&=%)* z;uk79PjJI>wKt^bQO=*B>4;pNqxq7fWNw;csOSP`JZxWPlL_^R(S_2hSL6ncp`wc< zck^?t8>Z;7&hy}gW2knv^QXK;NUs~i$><76+?c7&n5h%TP|@Q=1K()5O52_KsOSmC z1_$;G6k7|&2_N^bwiBiSJh=FON<+1LojGIk(tXsByws;X0)Gaz%0 zDzB-kfK#3Zcp*F^9a*l0oSqI%IUqVM6EU}GX5G9w73$P<1f~KD)G6sO;|oGoTwvE&$NU)&B$BV^R}~Z_@T@@RbF34 zu8>G1*EsWXua;Kf(_Iew%B7*F#Kbd{dt2n^5ajvya10tf-jK znRy|?#@tUgMT! z-7CDi$;;`O<`uSH9O0V8K|mr}`vs5*akCVi!!X>yaMGwFK9VPQFWEuhbVb}O#RhT4 zlCT%$V?#&-#x?8Z@;sjJQn8_gB~&EDsba%;5}w6uG$GKNt1n0O(m96<(ixn#&=poz z1!3lB#}9eD|RHlUG2Yve*#1gTg4? z-|oe=ty%>q)T@pUnxS&zF>ePb2ehzS$75`L1Eh6j$Jo*aNNdW*TT>90+MW}mYx4op z^mAg&`T%JkIWcw#1EhK6##nd*q`BqBSbJ5P4(Uq@_ui;ifaJCOd!r&>mKXO$nUevs zx-el`T-+CBrU%H{!h~gMalgQe^h(8jFiNQ~Ggp6|rXO@H?q8$cB~(Go@NP6^hIgZ4 z2Fdz+S~bb;d(l*O-;1WQ`?n~wYgKq(s{ls~()-zb+jN__c`FX$-Sb7Z$2Y@iB`y#p z)F5uH1m#6%YR(~c`(zSw$B(n~SoA{&Q+MYOs{UPUUk<*K(V=(}Og(|}UWeU0t@B9g{56y;#);i%R;lXYHUp!Xfz^l>%X3~y&bzlGD)~7J zBH&HI?5}_w)@UNk`r8>Qo{MB9X#h)o8nF3i}WxK}16m)_i*E1A2sM#^yr^W*H~g|36y?3^oaLI!_^ z3?9su=Ul~xH)aH)tbxu|Y#YZj%J%16MQI-*I^uEiUQJuM+lxl9;W<~cBD&j)N6HxJ zTun*t_T*rxCfCs9r;c>gD5)mbQjoX(fz2#|>ljIlGB#cd)o?;!Y&@FX%8f?jKIGbXh&eyXarUu(9Xa@1TICOqz-}P4E)?n@OT7XM?ej`%*cHk z)_nm|rB140e=y(=0RF26vp|Ra-N0pq0xek}g!j9nOw9Tv=nF&e3qtTQDfo~l4O}+^ zyd6qvfX%VgfI^dfQ`)qNly(o*g+*tdO~`ED%2`NT?llS2U@MIuXXnSgZFw(b_fn8V ziL%FY7OevPiHx$-)6p9lWxwYvVz>7vL`Sge(@~W7Nd1n9#jG4C@Dc0_oyDX@dF#rs zSXYJ#y7Ze^`h82##-vs?lkt2+b!AwhE5prF8J04#4>)OXQ5;9cz5TW_aO7yXvrIDe z94o^KHTX?_3h*ssP_*wN@Fxb|Kp-|2MgJlKC6D7Lc|U%J0W_A3r5;pnLhP{HQT-Pf zkqTCF_eA&O*e3ZL;5U+-z)}u`zd{VYK*+GrFeJ(FaFl+ZO2{yl03r5DNj#3ks}1oM z68|D9l52n-OMnos5n>#%_l8zC8S*{AI_rMR{G9^uJ)lXhM&S1hEJa}0VF(e!2#lqG(sL1e2r<#*S9faDDOlD0RBQ4kNeK{5BIXH)Vf_s$o5tUugJ~Mm z4LFWn|2X6W9NT`wW?WKJ!>%{DzQ7%3arY319x<~02~2zNCN)y4VP6?qHnCbwOJ5Je zy8KLQ$R^erg3mT^HnGz~@cTpXOG5B>44h5uF@f7=X6sUVGaDBDxlWkM@701tWi@1w z!7ypIc&MqnVAf4(l)Y3JwlCW#GkV}JS)r3g$S5%L23_#irVAc2-=ue5H&L4Bswf2W0#XzM0P|r1 z{4E&DgShQQG5i-twijOVvZj22e}3JAqEi;34)W_h9-T4_|NOeYj83Tmo?rK| z=#)F~&#(JLbZYuJn!m@Hmi|%}MYnYkwct=Jy#5D|%FK@Pe{ov2%@}w^R9Du&jzI?h z`_nRc^~l=wcyL{L)sI5de|&uQf8gNk8((vB;CHGV!xj}jT9b^((OP5(mSi{`j+!I0 z=ta&G0K~|$58teb_))%TIA&`)v=Lem`@J*CL)U4KhGK6xJINByJQ|9Oj)r3U z96rA1k}!2N6nj^wA{H7P4aMFUMARaJqakzwOfVMDJQ|99B8aSba5NPAT$1zwu}4F( zF9eiLt+XC0_O*a=TY|=*MEW zdNX0W9EOYVHjleeJ+ZmFbi)eee$tax)Un`g9)v~A$$=c(xc?l7d5E7I9NV~G+=acp zL;%nS67H8zfwL%{I<|2ghlIr`kfC%Pl1_++k8Rwj5SN94hCC+Z_3;kJHg2x)%UJZ zJhpLrJ2c`pgH1cOaSsyC9T_<8gDAJ3b1*D@mBBH2laV4}+7mZzLm%6?gB>i!)D!XG z*v1_$_INICk8RvTozo$4uLan*d5~{k01S?8+>s*jy`T*2+dNo|`|~RLk^c{!co~bvGVQq9zlKU!f>-&<@_OrMk@z5ZjEF~#Zxczpw0X^*N<+Ub2ijQ z?M@xsxJOD$>kX|_2RCkm0Qmw*v&sV9j;GF(qU<*BFvy*o6P`=~XpVa~E{P z&DIX{l~Z7f!7|Op!IZIXIub=(k5^SRHdR#4EuS&Fsk*XZPGwC~1%2!{C@1yKozNz> zDAzU0KGG_e+F+hjHwTYEc7&Tv?2d?F6T2fyZ(?_Z+fD4KnGa-cV#i9edZDN8=J&&I zcXrx6SZ90O#2?NpR0e0LmyeZYH45(n^0o!MX>7r$gh$o*gqwZ2MQmOc6Y8nUZ&B8Z zV7Ka0!^-*2)J_?R=MWI3yk<+;TY08w6EW!in0cAFwC_l0$D?3 zoXHKJ2xJW-l; z9wX4l0sc(JW6+E;@GBYPSk`v|#~I!oNdId?-cwh1sBq4`(>H zum{5<8BUlpuy~SHr@JH^A4~i7&c%*#d|V5HMTHGyn8?amTzDIWPG$KkJo7{ z9z>>iLn(Ori9v1kJYmWDmX)%neJPW59sxyv+2_5KS?>>_c(9ie2QV$?GNv`)YX*0a z7WSi3MN%b<7wCPIfs+?pT6E8oDxuN5yklKT_r`ILr8%86{k03~GlYI%F|zCY+BuU{ zqRp>U+Wb1D&9l^I&{{l+M<)TMe4Xc+lR<$Wuoo!h;HIXT^XAN$TU9rwsYzW12$O*J zG-K=m1PPN0)kh6J58*>hA7w4ItaV-M3d|YkY{s-9<&-+|qB!kewp3;|Ls`boVU85C z7;3y&)z}C|PeTF0POBfdqZTGPtKR|Tslc3vTQf)@&oJXsW;_z1io-`Rmr6Ucp z5IYKdAlN*+UD{;ehXB4Q1Yc|5H1stFuJ1u<_f@>Mvw(ZqrKg4@bH~(3KI{quPeSsz zM?%SfAWClr_1GX`HGj_FvY{tG&Q5OM3?B^CNzi@xXat5&L0}RBcOo#p5`khoLqC2Y z0?i0aI1T|k1m9a98;xZP8*z7;h}%YU>|KH_m*F{}dI03ZzXCpc8q%A%AJ|ujV=83; zNh+HdpaORwa42aeG0jO#FC(pSubOnGBA=;hVlE_DjpT9rBBLJED*f1Gx(ZyMAboIZ zUk84XD(z)Nvaon4Mw4zpWu9-~EUe)gZf~7TzSH0qYBhLCQ4QM(efJu~ZDI|Ym!1Cb zCxH5j+58OxJIk=iwikhkMc9sei+F+umjh42wFn$a)OZrzi&$y*d&)#0b-W{`W9g9w zP92|0!N)B(aF)1S2QxQO)#R^@f-AJG8_Gb>$ z?sT*)=GXZPTUIrqqxHiW&R;kX-AFt~FJ~X+Et~;IJ{-Vw6uYETIfU6*@iZ)tF)wi5 zX`$@x$*CNpoOd`zx!Wg9m7eXdQ~__vW}Dp@>I&a02K+uGP-d=%wBgFt-~;mgS8nr<>EaJ4z!5JzHG`O5-aK+<}0axDDuE05=^zC;P|}>m|Uai_a<@ z{~Yld=w)#Ew9pwPTHUa@^!G+QU!1WH{H$E!JI=#KyDH7QPp8g?e@O_9dvR>>xCK{Q zWJoqc!p%Ygp9gC4aR$svr-g#{QBy)J+?TaD(3TE1O0fEWY{9%`>DQ~$HiKl<%7fYz zwjMjM*BCgfmVt4ALNRvpIVI`lvoozo8^1%N5(XvZ)H+*?nj6L9F!9c>kVd6+&b2Z^ zjmF}3ru4saWMsM?@#(q))`0y0%wm`Oh>?ZTk&n~p`~t$H->sR6QYyXDP%tmAn7nMj zX~*vjTzbb(O~ho(_Kve9Cmk=La0IEEj(W*&*37CC@yBo0tRqr4NV0c3RRaLz*S+}& z4#~KCV*aupa;nb;f?r%vslEjN{Koo5t9PJE^BXIQR{s|N{Kf`F)vwXFN7RbZm^=Ls z?nSR@AH9AhJvg*CZERb;Y|X~@|6*HO-Crif@&Fd}{G50gvg>E9TC;jZk^F2}ZQhcN z6N}J>bu>jmL}*(&QvEpO{KwnUUXysn7+1hQQ#thZAP$}F>29lOZ66w#>v zR|4meM3cSc&*NI{=_gavu>=#*=vLq5AUEE!gMwcC?%Q190 zP4jBX8)jAFBFNmzSy-g|v55Oa@a5*?CvSs_Z@Mnqh)h&0S>HOBZ(@kPA^8AwcH4@T zDezu`BgzZdqi;S9-MTb2E@+%vSt}9~StYkq;>HDdw}HwUvx6FT-B^q311nY5SVrBh zNNQ8v@}pZ@k5^fx1Vsd-vJPV;)^+3THF#4));Pv|Ft@GVu)bAgjb}W&>&C`b*)+|X zz<4h4tFXWjARgzMNN5-3g_O#g)E7E+p_`VImaIaNWPeB<%^TYNTo$`TIwXbxG-m)yB+*qb>2r!$Q+tPHtZxGI zpts3vSJOE|G=F$CoimiMjMa3`Feb_y8f{G{!2T!e9cgFcK&0Y~!h$&eSE%UD#Lp2g zz!UPgE2x}FQgy;y+J&5QrVHQvfNwhaR5!5^mp$Hk?`$Bu>!qQ$o;K<(%RU`8q+CUM z=XpO4k)9{!?2$4Z%8l7o&N)oe8-Ts%{3odEIT94Lzs2OcThBf8QGG5|FIc+@Z60Fj8V?Fg_K30gD5>3IqI*#Z_lPG+?83!&F1h881E{R+ z`P&iX$JzM>SPLcJ1DNl1sIYypM~zGs-G_MIEWDudU^8Cy(*#mz29u8x-U?bo)y%9&tUfC17#wmDvO}o(LEiiKAP5`V zXk%Mo9rdX<{Nn?C-VgMtqdt)%0x9ffjbD#>63Gwd*zuGh=p!0~=!)A( zbP`Z^gQ%ztfmZ|Sg?q|`E};Iw8G9{HS4IvVC?($Q4UGC<4y1A#%A^do4t5j5EdT5JTZHG-DH z+HapR0lTdqLoRv(x?veP+N8M~)pNIoJ0-98WoN&KQr>~N(kf2eA0VAWOa zc2>1sjkc=Y!K!v8qJ5Vvm6x61<$oj|Iv1N2%iI1x-rhXE%HsMTpXWX|$-N;Y0d643 z79m7L)W{}_OF|ML5VG6^2yRJ$08vOVAp$B(-S>hk0xGrEt+wv1TC1q2sIB5ww<@^f zQnfCvYx%w3XJ(%JJXvf%zdycty|_Gc=FFKhXU?42&dl%{Z;Vl$dpL0A8z6&QHQ-(j zmbU_F@Cx*9*?TGtxP2L%734*8{l zKQFK<-rI5TW&@*cf0V#I_-Ml$n^7|UfkvVk9cv;-n21iz=+H9_MxbdNa=6idULj!` z%)nv;(_uE$QxKaJX~FMks@)hF-SG&5j5J@`-@$dahCCXn{NX95#^o*8q|sVD=r$(i z>}FhIF$C9Xj0>)S;1Uk?;2=(Na!3C^U(w)x-2ac|jP0i6(~Z(hnTV;R@v?K<@W3Sf z=7zlvsdT@{;kH@CgIx$S6zQ zt(;R)iYL>*XWmg+JBegF%qnV@SR$7=j0;Cj!*6O`S!s0*F2tyb&r_L^<3l?D>@js| zQ}anGa)N|Zk10A>C&36(ZV=jugpv9XL8*1|nzFj0cxg>(QDIqKb&1~F(;f!-k>duv zj3&~fW;O06h#WsC2PssKA}qA6Xlb2-jsKd~h6RnK%?le>A!~^aA-V}e`-Y`heURHc zB6Wk>&`2Xa;Ow^m=fle|-)k%56g^Tu=xI>Q>`}s9&LUhd23W(OQGn(2DB?v5&7@!= z=1W8_O3G7`kp&VQ(KR<*k5Q3@!qKQ6)%1OmC9g=MfDY-V+-gK*r7+v0nC^e2&5K%8 zWYwV6U?1-SgKxvi>OsxmG14R6h(53_!Q!a`PwP>!vKc$6HF{Mda@rtPTc!}GZd}%| zd`U|y#Cf`av%y`HE#jI%l`K1|i(-#f{!HCO77e-vY=t9lB1N<-L={;pwU;!#v>XS0 z%Zo~|WgAZ3^&XNXw>Lwh7pml4)L^KfhXc?zLU%iU-RZL`if5OVsN}yfRazw4Zyb7z zm6bSe zofGZD5ka!71>pS!6^&5{34o@XMPMY8*=Hs%DWMO7ifRce*GDconAy5zl>yjJz`_xU z>8R@}dhxGW)cGwfc9!_L;XE~f!6N-Vkl(YbOX9^PQ%lPs!$Aa; zRkECe_2*oE58-#bq=;+Sx%|fBuh1UOz-$}JW5`=|EnsL$S;Z7p$S=?-!Oa9y^mj$P za9W8fN<@?t*HuiJ0sE(lEk*)VLJ&z=oT&s9O;yw6|FUY>@9F%6URT380x3;)r7@;N zKy$J$gW);IrXmhaW+8sS4`});+GH+gfM1aa-#g;km7Kj?!*xo#8&WHSZ{N z`mD9!Cs~$z)64m-l4ZG92iS9w;Uw#ulu`5$@!^}4Q7on_*|@7@lst~|g_Es&QpQw< zlac-`BuJGJqIb-sGW`PQY^(6Ziv^zD zgX0F?n4W%#^A2(w(Zl9|=lE3mFNIcqkHm{j=^LCEfH$^>-ds-K===e}2|Z+`FMYGa zexg7}>ZP&tYXvr4^=e&NC&MMNL>V*g2lu_>bKy-#cSC;B2*Ix4Yc6{85*1Rez6vmL zx+bG)7m{VMgnX!}FMlAQ9TYIO%^=kLjOt04_=|jNL=ye>$G&UEY;qRq_Yu~HGv*K@ zvtO9-xg?R@FP-1D1za*nZe6J|=25sKK$@0493iu56P%gnlC&(5E2r#PM5*MK)~3Zx ze09fOZdlHoMkMPMeR)f(f;~#U%03jCI88AGTzb{@A0c5fx!>Qx*LJ{&q6X~14?_bn zH&#(Kh}eU>TWjVp%T2;8VMt=FS%ThLvy1`5ksiRw;rIS^aDc}FckDA_t-k>)e|n+z z4zgkg-&cSK{yAH@4LcN~btL{VOxK2CEB-DbPdFBY!s-Cd zQR-Sw!D4yC^5wiX|HXQPGFK8aqmMyg1Z&87ku}r|;s;)8ur9|O<|Um0T$18yU0QFoI~fkl#1lO`SVVMQ_xt0ZsY69vKxt7ye^tOWC_+JuOA*PHm8JrVy7 zQ*Da)ZHl-Rr4kXZGI$#(;&)F+HX`CH5icTsfI>TrCS%f*I>+tA{A3`gO}Gl+i42dw z9$$C|bw4ejN#7e>2toe#g05hX?HJP`CF*>)NgEK;Xc3d8FJju65R<6D+a{f-0zb~+ z;sO=s16!KZ6HuDmt4)~~Al@(3+!2PvN*zH#=N@KYJdsXew@p{MZ3cFog~8qHbOWQI zQAbEeCx?=pB!{Vb63oCkOzJ1m6R zW9>tD3Og-?*=x~*3x%H|$fq>GA8IADEs|{AjqBHGVHArnK0tgidz=&S5APov)tkK6 zuqW~v{d56Y#Gp_Y3yW*HB?iW`pDZe1qiPL|#pf-)gs%boX#=M&-m2lc*=l{XnTkF} z`fKG^lixI{DB0ZdXEY1XB(f{H$H2l^h)phe$REo6*n|e4SZwU4;}^%OanKsMgf>ne zj`O_W0jGIkxAjrpgM0l&=MiW!+Oh;#++bPMW}1={Go7vmu@0w-&$jMSm2;-!oDJYK z>EO?lI#JrmNxDJS%qAz_VTBJJ^m%i=NeD$VQFxZ@x|O6;h1t7~3H= z8bO0e9}wfuTb{`$|FuB!l4d{ocvGfK=+WdXLyl^I;TPKuo}lKKMUV2FTSc+g8#Jyo z^UvA3D2tW>^1W3g)_0*c3b#pU3qrbG{LX6^xnCL@`ABJWI#)ecAoPlTurdRyO~59< zY+%Bsc_Gxtii+6{5OaBed&#QQxgVX`no7S#34`X`2Z|E)koA*P(th`KwCDIfKz z5f?|YS!mR#jYzwrpNr<$X@VNH&xbO>qNoJQST*_X7j+KOCL3SU0aj4%ttPNcCycI~ zkQ|vXc&!?$Mm=SsXbP^>(SE~kSyZE5Fo>4}@pg^qt{jo9M!oBc*l8p3lU45Ymo*C^ z6jtjO%EB~u6yA5`Hs|tibf5ee$;r(hIl@tW`>0W`nv`VfAf38PrgDEYh*LF^uV9mp zHu9!4^qkCe^GjRW&{3}x6G&I2q&~yom(vlUP5>#ymL;K(7I6< z`Eq$&Ga+-E$#0~p~7zs*I_dYw)X!Y@w`@H2Ag6dqBPi-vK?x0t7!9MH?_25%YY@ie33@wqf z3^!^G8)nKy-lQ*2RfAY!U90rPRnDCvnGJ^UD$h8s#mHSGbElN^Nt9Dd=FSlJIgV^i zNajwF%yoch$=od|vf9|ZvAHc7oQ#k(W73VfHyZ|L$YXXdhtglu#h(12VT5&=`>6?h z44ygMfrnG>!3Hw|I-O-%W@4!qqb@W7N^7P@_csa4gGlUbE3t!L_oYGxI)#>TAVosP zvU*X*1*itR{f(^xz1T4O1}W+ncWAB6;eJFG*GB#fcwdf%``(iTl`30aB=13#wv?>G zB~GtPs=X#vIC2ZZvr5gGFu=7>X)2y-&>&Q_7J-X&6wv z`S>r*$N-+7IMRnGGefMHD5vsZjcFR%tR`HCi!O>s&bXQ2RDS@5qwaf#xmldV)M0^c zJ~j@V8Wu3>?lF<&iA~$ghn@1^rfud!PDOSM>r(iaew#W7M|r|()p#sm{lE1{H=gLY zDPjKq!5cmEb*-&SeuL`6-xEh+e$rw4HazS##QYE2x8Z|BXmp*nZ(VH1=nGWBM-d_5 zx=zyWO76OHgLFQ}0{`=NZ_txnNOK55LKiFrp>X6eP!C7wIPrhp6b?uBFj>c~;iTsP zO^)boRh5)|4}xx`Y_h7P{vqg1IPxK3vx}w|##Pcl;sZg41`QL02!35O0NK|~T1Wo$ z9&gf_@?EJT&Z!dY1BpFl9#&bCE);6Uxt_A}oa@O)C~TbT-AawV;Zh+mmjucTY$IWA zrE$u?>K?)1du_llz)b|Y+~-h9*KHzUC)u1y(A(qw?d@`SM7|2{HI5pm&oH!Dz|14zksFppL#b9Gb>j&V}f^++0y zoQmHhex{UF7Req?$_Qr#!<8C+nsbdH^4u^C5q^{SiD+*4;IW8bGh{ZvQ!a6Y3A?wH zvel_(G|MC#<|*&WElfwCr$NA3SVAnlxcp#GUrE@Bh^!N|>NNZOq-%Bn%=k^ETADuS<1$%)cDL+Xj$So;! zkC$6=$j4EN1cak#=v5CV)sNG|;G}js2$2#F^@I)Wu>lFmQkrC=SxOImDlBz41Cf#; z*`(J^n~g23%t)V;Kp+E085#~#kr-82heoSN7PUJpabr}ZFGI-^8jGC)CX1*{D&A@M z?8Vi;6y*xlNOmqjP-Y#Pb_GIkWsu)r;Wvq&Zjo%FMUIgGbVdh{e^k(J#BaCfG|;>e z-8)5J@K7gPU@8BOQmmQ$NlP{ig;XY0Y@iL3jfnvCsjH|q8+Y8hDpZ%J{B7U`z>5Bp zwfV|GT|--_Gp|Y@99_zo*CY^$&dNgIbqSyee6$tpNr1`A+1d_Mz{3hUcD<8e`v(0BE{d z1V;KZ`^*gEo{>7}K>)J@?is0rnJsG9mqqH}n*a+(7}E#Eo>e_f<@dPMVH-$~y5MNeg5!;rHZFPT;ie}S~2bTLkxiRzi!j#zu7sb?CyKnaSA zSkImehgIfdfSv=y{bU~m7n+a*&&edckd{)+o{_?)nx&%A=`)q{S<=ftfj zE0G>GqnO<-L|X(1`_PQ3`;Zow%3(;JL^6Xt_Y{)ur9ziuCNl`W1;#yvpV~czUvy8A z|KXm(|LLA0|HD0n|Io(nK@s;9etGUG40!G-40!G-4A4DA zFzBA5Kj5CCKj5AsC~!~F0Jx_JfbJ<8LiZGYY4;R<*&#%K2E;vuA3paK2CaJvzXR?m z1Q_=e{i)qk_-)-&_-!3hhBM#|#PS$QxTi3r-Bb8w{6(hdZ{wblh)DRN6kCi0sDz+^ zdkO(`Pm%w%dkQ~0yQd6cN}qcQ!=8Hz1J*r75RH2ZzkTj03?|%Dd?C+0g)qN+O3L)& zk~!ih(tCrWyWr|dRJ_2bQH3g}_oWUmV2FN)aa-@p^q4Fr4^&NS$APlmmpd|qh!r=U zQrZk}jow!XPAqy9I^f<{IO{BcCH1YW^A)zOzh(#ctiR)++sM?9*e!V`uV%21Am?K>3yv;4%v8&c8T$}a7?^z zIL5VBrMS-u60IwQ>)5T%IP8dO)_-eQhX7>^fP<&KZ*w?Wf{SaH#Sakc{X6Hw?)mG8 zdI7SOZyzN7G_C;ay+!pv9zUl4FR)Ndh*7Gy-XWw->Qq{$~1>T zxkEFSC(|#6#kV&$f>thZI5jqs^MQfJF)DExo$;$7a@Mz{*ryz1u9PaKDVkGSRH7Uo zsHmcRYAN2F@PW{L_zZ>X19>_Fo0%YIAF+c0O#r7cu{h-cin0pZIKH(SFo=OWp(O7yB$p>o?`Ei!!GHJC`=0ef34mNF6GnCJsl(ZlVJ( z_H|8xkM1QZF-To1FFw1nCQ+q91SYlyJM75?rwE%DHnj56%#+)3{8NQRDs@f<7NRT{ z@sg_9=$-4PmC)oD*37Q%99L8ZSIIi~OV-Se`;^ZntwvHC>FJz563^hkI#(yO%tkWP z;*x5(z*f@#Fu5aBr0k1N=@`%STK{L`o;GSlq$3JR1W}?LQAj1xK2keIlR_f8N2lm{ z<+!JBDju0CQE8nbk+!;|Oy%1MAy!?16vZWFa6UcEt1VMWevRAc+}uS?$rF)upe`pRIZ0*Jj}IO|6NrIIV%->Iy90!oVoFBr}Wg;<#Mn0LW& zR+2z6V!;cBvmye{jLk1^Uxw2Pi<%ap%&(v6ZtLR&fsBxS|@z zYE;&!5Je8*meTE>CtI=(6;wzs-iWpHwk0ZSj6hOi^Q-YN%Mvex@dA#-aPYUaL1j$} zJ%x@jGg`>}j>MI&98_8FVldX&%0Z7`HAZBWg!(}dbg`xhIa91M2{_U3(9E(bBoK<` zLaVdl5^$rl_d{Tg1j5mY49t^2QuIPHaJ&SPqkKIet3d)O(cug%lt3i990JW+A`E2O zGAxxcWa~1tNEvc47#YL`1S)Z-;;785_RxHm;U$bEvsTHsiqTuRVd)C&R;-{qVb*Cv ziayFqNQ!l7N#SrO^dTsgGeZZU3|cH_3%f=v7f8T~o=HhuEOi%(-prggNK81ofJMAa z0!h)Ol-`vRNY;9AwFFY4<&@EN5`gmC%28RrmYh9#+~k+Xt)4s%M(U)YC`mXnfuEeh z;>tnq!5{ssY3Q5#!C8jAA6wQhbjZ6Oo3OCHY@^QHkNw;*jN~$~69SRorm4`66#!&< z0PR8>`iTn$IkCX~*hCzW02$1XL(~beCFV}O1@l2P$suxqA862%1-&xX)&1B^Q`;%V zBTWH)GC4(bhsazi`VO8+Ev|9&JxP! zX`4GsaFT~er!_xV*i9Ay&dr(%Q2Fr za`3nm22Hpho4A=c>^%m$nDwyxIP`58zw2>7_Veg(VzLK{`>|Oh6-(TYO_@bvyrT>E zV-Eq_FwTMdv1!?}qy5pEa4$9k{iA1tIxfT>4(uE&9aJ@JBv`8vq!H5cb(8i?JTAm0 zfdgaSh1d(Rzd0(V3sEbD$d7fr5SuIN1vZ<+97N$lZ1(QOG5>|wEKY6AcOmv>EaDue zhThIT_i6V{{5Oo>`Ju%QGdFT+GICk4v;li>yqLmRX%y&0ha5x*l~X&=pq?BOsMYoakZ!<6-? zgi@ooGT9TtUz+CcIpHr;7vqI6n{iAR;}r>H$LQ-ZA7fpW^@fx{>Ee)kgrJm*lP9`;O6x#%CmP z1Ym2m<1xC<@DA#pNZ=i#>zqa(qw5T}$LMSo>Yh3=JjoiH@^3H~j{Jn*;T)3WQH*)- zh44f1c$IHb`o=I>1u0{Y0QHaG;iX<$Nrr=5kfi^zw$QB8fub*K3zhR*>C4)5fFon} z<-W_>c+pzlp&X-l7p?WpBMuV!9y0BFfQ$iD;M(%O2c7}MOcrK0K4g#CQR%uA*n=+O zKqUjNM*WJ3qx1;0P4z2b(Zd<`Xkfpo4D)Cp$%G?EVz3*IaFlU?sA6c9vj~(1&90tO zT31w7Q8cq|Rz-P5O+|TWQ4owXcQ^oyg$PIWkuwWk%cu-p;Pe{~ji>U3E|h)~{j&^k zE|Ojs;}ke`;g%Nk&>DWRz_X=Qgf4MP(6f$+S&DR=4gFH+U{tXJ{&hIH2+#)SGqkd? zrqP8q%AjO|83}BbkwAftG^59B1vXs`4lrEjGkBq2Im7a7L9LCdOIT({OU8?-sK&z# z<;B=^5+rTBMR*>HG2L7x4R=UwmOG0}t9c$A=cjQKLI;%U*;8hf*3>X{W{0TKa=a#h z2hMA-_|hRutX$&uMvyD$5M#Po!*sD)uST4PDU}$AexqJO(R1MmR9rC^k4==QwO#=4 zk(*P>>jqhb+2x7OQ+d$ZN>$|rM(5{`QE@Lg2X`U-g*)N;|5Nc9gXPhOysl4z?p%qcNuIH-{LRS-UZJ?l+etvNOzCQ}iMI zYR?BGCj$pT`^}>?c@UI)$l(at?6a_`Z2?{Bq4zQu%nW6PUPDBTcM^yChMoaO3TA$J z!vekq66zjaOF-?Afa9i*;*^5r(qznZ26A^tAgUe{mQGOzxKj|dBzgi( z*(3=pkB&jzhh|D(RdgjMRL8mvK*K9g=+r|^?r8{|7oAVE(_KnrLrg9g#?X<*3pKFL zy$(2=Vsfg-gP!R=1n9QdNpje;Zec4#(pslQqe7QTjyFRYRy5!;p8%2yT`#eBm`PN} z*t;e6KBPrvEvu=0Sk=UP>+W;NaeJ(-ef}~WL9iBAg`RO=M#Ro28&2p&3G70(;=)!B zsct#=Q=#4N2f%zaX721ZXVODXIQ3x8oekJhhU~@iW2sPu285Z(UaAWoQbEnoVN!*L zhesmm7e?zPn>yZ^qe6#N*tV(kd7LPt zak8Zdu)qTI_=T9M_%9s!C0bfIGRk5#5Q{$mawdxFH4qq1Ww+pE_!f#(@jSNHJdVin zE@kf=j;yuO)NNn%Gl;b~*H|1XxW?hAQq%DxK4K9gkfsk&f+j;|9*%r$F{$vvs?970 zfbdIw*D+!M!;wR53{^Z4BLgdtoNlA3^g5cuUBoQ5F;sOOL$jm#H^hHoaj5tjN5o{J ze*@@nYN(V7G@pGD*3u467svIg^e zeH-A*vo3==yT9P~s;s+FHunsEug_?h&xh5(0n7(3*FBTa^9!C%e05XWj__OEFBw(uNZti3o4!S>@=OldVDN26J5Z$;qQ(Ax@!* z*h#rza>(zeq_VPj(W(2it|M3l-@>H(jIJTf<=Y@$;k^m#(e7VJFale#ynTg@kbcnp zD{00uaLA`q)U%B0o3RMDS+ut{29rI`{nOGM0xZHPA$FLk&r$$K@a2C0!y;*KtYmhhe z+;_=*4jNk$5R>v@*>Nxc>2s`oHvQ?u{UK3+ysKK<@PhH z7w%+yTz*AQLlk@p4k`Kr`R>Kpy2mk|eS}7ujWf9^DDA zy>kaU4}%ttp=ADqGVt4!L)JTG{CK@1(t8j}yRZF+HgB^~zrmKTY zcfPcx<)rrIm}j|%Ih&ccOp@Hu4n1Vm{&?ih!zuwmz5883`=WWazm6ApD- ztu;lxOm_ZCGAoee2uB7cdLv7@N17T*sjFLvTQTKyz|_{3W!2J*QK@dB^ADsAN4~=E z$Y;<_Q^up``3(8y-HpkdGAT>j=C-UHKNfxga!Ujf7CU*s#K;!EBiUvOn2@vGykdlG z!s^Bq?aPasrZuiG{lqD4h0J%F(g zGZ0=gNJ`V4+lA7-q(nxZB_)!S^m%>LJ8|PDVmEn6s?_;jNU6gOsbTogq)0`xN2c-~ z?o1R#w2T>=#h7h1EtTTVbZS5<9682PKEtC-Qh9YS3Yy&;Nxlo7(fxAzWwTh+QifGA zGCj+=T}a<+N$;?vJJdl1hKEQVZ(KaH5koBHmOCFw%Fmgy9|YcS0`eBgNpYp5iJ!x% zp26Di$_%1lr*$!GUO#qS2!X|0M;zp6t9A}v%Xk!9u??xs# zknK;J0R8pz_+!&o;#m_vfw|7_g}^IqxLJpXiVcy zYitH+DG@Nf!NAdwXu$AkVFlJpa4l)8c#fHv@|G1P%`NSVmsGZ_gxOE(2%ZAZ#g$D9 z(eo#psOjzV%h6C97uK|Z<;LYpSF02gRoYzExVT}#YM@|TJd|a0f90G;sTk`#s}9Oh zhoczafoge+b3O`>B?SDAYy#rV_{b~9N8Ta)p>B6bT(qQVDXuJ0?yZtGNV&RczMLCI z^l!U}*3zgeEf&SR%}G9jnWy1bG9QT#o$oK%CK3&+4+n0Z)0}_o7IpvPJc?xEyyO1W zk@=6fySdLwK>IYg&q+Z0G`YJZpnaO$=Ov(hn%oy8pnaO$7bT#5n%tKppnaO$mnDGB zy2@@DbN}YNC#7SdhL!XMi|(sV{gIZ{*Mx-jGjd;-fc7(T-;g^zw4agtcZtz{M(&#u z(0)elTN2QIMlSsPFoM&5M(!R7KmnMm`?m8jIMAF1{6GC-1lFZs4QnvKjYQlJoPUth z1G7QkLm{W4eAUCW72WIB2V z)$)Dq;vU^Q5P?sfP0U;k`!EZ0O7~r7BJkinaj(f(=jw@q^~dGRk-oty&Hdha*(<{j{xXC@ zC5V83zNkdPSJzAHhC|;FBSL0}JrTo?TNHZiXe*IoeUy}^CeRNhrozfC32~4ejumO! z0SlGzXf)L@HN^Vw8>?Q9hjuaakzhYVtF(;&C0Igf0TPkJlAH&QX2l^`( zu`jH|34cuSW(Z3IV#X$7RkRwf!?Yu2W{5^}h#JarxU)h(piGglTNN5wpwywW+vXp3 zSUx&EeIV8uA|PzHD7V^x1`B8mK{W<6NageCQ+Kuw4}#^vNm?{~JCUwdVYebQ6FH={ zW0j{;@OnH43E~B@0G>Nn7y(DehTb4YTBxOMC>$+z^Wwr4)$RBec~!LXs2m5~#~D_@ zuuYLbE5gPHhVKdN;|=y;!}tk0JlJEL-4}hX%gyE8+>U694SFlG?gCqs@ccVRv3= zXrU?AF}hd{U|SdKf2HEqOIiDf%>HX44C?2HUO=Y0JuZ-3Rm?Wqg}N*;6rWSg#)YU; zjJz;6YFUcXxS8WxX5H7b&tzGP&!%7 z3qniV@Kiu+3%X2PkQBh5(!TU0^uvAu^_GLaNUU!qW5-}l<4IHd)2{QWwY(I)BmR9n3l2_eW=n8#> z46(q*{3Gr)q3K1mSu}swN@^A5n;0&fMA4F+80cbS$lWG+g|HdMtK8jRNiZy481D6& z51jMYnPPEjc4b{Qt6c@Yx zn?u{deK_(2eq~7cIzI9i@<%%06qCr*VNGj8a~o#0OnO`B2TAG_o1_QgLnoy~^0Gqs zk)Ho+u$OlkwkJ^t&BN5C?QKge5BCTUUKHb-INKUugoOUuNPto%@^z;NKWUP9A9(q?&eq>XoObetG ziO~jm$>X@0$)^4$v_H_pkpu86C9DXh{<&6yI)}tfOZ_R(N>H?)(OJi3tF}S`Zm{~3 z+?F_B&t8n{f`g|Pd9}diVt7)3!wmwxxCNI7OA&O*;qEE zw7QO2Vf(pk|AXsh(h5&4$9{yK&WVgV+4iAWR}79o)^?2DuA@y8_v;}WI-)4c@64rUbdy+mA4yztOTLGAr*)whLI}O7m0Mi$R55(pS*F(D?u^QLRC*6xEhjL;1fo=FOI_KY>08>GC>s! zAI**MElNPTZmT$f-T|dkv&Y%=1PaTqN7EgRH%_i6&?t#+&|*F`ui@jAdm=Gw#8_v6PqJpddVvUkvrCW|As@6Tm{S7R2gcCE4k?r_O zxyQO3iDhD3ZbnL&)3_XAWyi$6xyQT32<603ysp}wdxFaW(+I|Qr}=K3%W+XYaeM~L zt#>)bnLuzS9dH|5j$;ZK=~I1ozRO|AbO9$i3FR(uIku?85ZekuxeHwm6KZ49+B!FH zx6$P=pkBv&<`=DyV=~NH7P-Gb{1P2cCX~C_Wq-ar<~0L%iOYU^6(DVzQ{^_f?0nb9 ze#U0FC%PvB=RD&0i+7THCBPd5>@VI@mwo4^SfZJ^%Ut$?+jPddbjodZj|A{$jMA|I zjiEiZo(tpE@WYq;4)ESEhwzb9ccr_9Y9nV1-Bog@ii+tom)wzG?do+7DD=X1SYv=r z6;LveL`_Xoc25&9CNjvcxUR4U=jW%)t|_U8$A&u%SqLK?BmRPja73bKSM%`}cbz6v z;I4Q7PzAaFC?2xn^^0@UMN!5?K%gsUm-D^}o@tA^!> zK2M?#@kh(ri;g{CV)Om6ys8U}Vpz*T>I)=(w29Yc@>9Q1;>QN!edI5a=<$K*0R4*v zVS+(0GVy0{i6Bf0BKUInrNkc*j1Oe7K`@R|nbf5xP^+>HnklMM$x9KSBpcm5R!I_| zPk@UX0ueE|PSjXCQ0NtUJvzJ0ogBwtY&wnwV_*h-umLS849g_SluLz7rhY>1Rqj8L zQ6$s7-3?V+okK@~M@h8WX)VNj-aBgos zt(e->xD*}VHM)?oU~|QKiNKQuZY;}nLO+rKRf@scCg4fl1Q0heH z5%(@3bDt&iB*`#oAT7!}tD(6aC-3Rs)T)(?Y&`0IDe1qp>3hw!Y;dM4Bgl@FOn03i z@|Y0u^NRd%Qy_+lx&u$3?&yG8$*N#qMP?p%*CF?C6+((4Mlcd1m=^LaVQswNuBL!o)nfH?&7!w`w#qaDY-l}tAxJgn^b%p91 zP7vqmPB~h8cgU9A@EA#VmAXxE8k;3C-^wz?b9ub`v z9a0)?{N%Npk^9L)z+C=}S%_1^?kDv80@Imea0M~!dDR?Celp}o^mFB z{J&VV?L8=5U9?AfuxOL;(!`@eK{6Z&Dx|72WJogXqmoE}tT#2}Q4#BIsGL_d3v0-N zi0xIOJx=m`P4XPaH>{o4de9Y+dA=b@CY@-%)ZyRm2ZZvd6y_69nz&%;Nm2j}n+RVo zMAO%6JU1qs$|ya_CMDi4uZr^O%}M6*@_3Xt+)je7R?7viQoJ8Pm-*=8F(k#yQc2A5 z@Fk?XRM*Yn$64K2>Z_aPMBNa933Od}8nS?^biO&XvpYqKw1M=bes-s@e#Tvlv?h{V zzAb3FYTilFT35FOT@4i-4G80QzoVlwu&0py5M(E^eE~q9#&O)3#y2No<96t8;!J`j z4DLz4QZzw2=ZzKOD;Kmag$KRUM^hVgJg7+n@6)px-2iJUOQH-unL&?+VMBnK$93|x zOfJkk?qlY0A2W~lw9Gu&li18)XHW8@ontQnOsZs`I=qGgN=cVuMozGlQ_`iFSpy`J z7Jg#l{v(4vQJk5bh@>6&CANg^w@4?Fo{&x?oeYU`Fc0Rbb$#*y6kbh|b2qc*O%Vvt z>3-Z(RMeUz!pBvxRn1PipEzi6{N@poarDeJ-;<2;N>fIv(M zr{OFCzQ?i#dC`9xrVqGIAJ2DV2ZDCuw9q}s$XQ*dCEdiE5&>lQIdLh@DS@lgLc$*g zG<4UYQVP-1!~{V#-|=Jb5Pgwu6u zERQ|4v|)|C4!(6z&jWgi7JLj8Em{rG?dgDCY)`u79N0^Y8rsuHNy1DH>P4e7K8e+K za4*u(?%Lnm3|)2jx$Fc^)4Fzjy_Nt030*raU35((rS(d5=`_(LF;1taGo@~Hr;A#R z;~7Zj^mHDA95InML5V;gi*dC9O5g& zp}GjI*flaGFp!{cuw(I*lP{E{gk+cn&}GrK36>PEv)L>1oX2$03g_FRJ?1OgV^Xwn z+`cx5IfY2qhc}Mcyq0k0mp>J)2e?1QLIe!10jTc@b$Q$zw*vdXd)ame}kU1a?@Q z2Xx0YWC4^@I;ID7$HcQ2h@>6Ujp{+&9UcBhMx5@9T8RJnqpjlUa(|AtifhDLYOA=$ z5v#bESFk#39QrwH$*&RK$Gu2>T_fYj@fV8ekjqlXe?z;wPBPH8a=o}UiJDA7uH@pV zONq48IeOBPli=8Ex<_wxf>%==y0RWUNuM0buWMVqY(Dpmmtv*OoZWy#rOkfiO6Xp z-X&!uZLJjP5+E>vrp1uZ>YfL^<)2Wax%dHMKYX zQ`0Oft$MT3KgMxn%v5h^4e@CG3bZt9PJ~7}bp@VRl!1>0eDeJmowaBRj z$CwCuEa;=POB$ArKKOFYla1Ht&e!eLeH$ff%IVQqN~z-l;n8ZQbOZjJzZJ z(0h2g#nv7Q7`9u45SMKliF=zGj)a!c9kJ4ffaO@N0*%;dVKmcsOx4s zM5ycWq>fa@%zL{b-@_Bh*MOGXi62z$pZQ;vnue}+8AbrsHuz6VI-kpEe3zkv1|@&a z*4o9`BatDF#&F`(MgKmJvXY&u=~Bfeu2z+zK(LIfV9RBj+OIh`%RFF@$>Llui;s{+ zp=6;k&Vlf>CfzL4n+F+|Y;=6&6bM)58@KxAIKP#7$c(~laCKV`cHlL@lZq6Ex;T01 zB*|EI`5OhoOPa^gtR=S48Uuxvsbf-4P90I`W7&}>_2j`tr&dkl*u9GaZ_nURX1yVg z5t;lsTX%xIF0jT}2}ZS4w`XXn>f-9yJG|mPnvs~&J(eN!hEkoiUq>I8!$EsYu5-Oy z3z}@M8skUM)na};letb`X~p_vCi9sgdq8`>YGeM+eNhi%+2#45QSwzVS@ zJ#5ne-ER!)B}Z6`$wI;33xuVFid_e2$#M9BsxIMwRetjNX}+PF{7yt`@*1FunYgkO z$xi?+`4efyMeWT9v(tp_L?K&m(vR?DwdzDGD~+)S<=3)0QAVKsS6P+R@o|K;aa$^* z(kbT|lG*}SX|q-fbxaI*S!Z51=D$MHIa#>c(21+zCt0pE#)afUTI0#W)ees<9sd)< zysXkt9KYIf*`~R?uS+hAoO!Up&;TE^U1;|z;c|N?F7NTU)EF(uRdcyYxV)KRY0f(S zZI7!{HCKDP zbrHhj`?76++3WgxJ0|){vvts$1wz zO_TSj$K;^i6x;CAEt7+LC&V_SH!akZ-v*gXv;^Dr>1p4MGD5w>AXj=-IIbDIiH_eW zBc27!OBSAPmJ!cPnXccGLId+E;>x&|#zav!QZq%!%zDjGO#wJKFe?AXM9n+`FU0ck zdGMD=iIxy`>&=^Yn6PkGEylk4w)>LUeD#*rm6cvOl3T2dHAd|k$W+SplGywQ7?xI{ z;|Jo}d);<*crC)Ztbfa3S@$3;WhLRLyQ@lhsKz&&X(gQDaU4pr5rl`JA`#-eT%R6x>b5F;hzMf?j4r@y#fC57$R$B ztkjCdkwQFg3Q>dys6#8jo~&AO*k*cr?O_%e<7CJHBy+c}o4p}jC}->Ut+sA7M(uiA zrVJT?oc#-1CLRAg!n#bod;^f)z5z%d8Gxjo;iw86y@d~}a$-F=5_LEJc3mZJxO1|4 za7yBCylveKSugD?>!owfL^Wd}qo1&PDncTp)HVvKvQk%a)oZ2*pDq`L4zJv)k|8I^ z0fKVIKtK=~1QTAlT_vlk+&#L){ZH-+9V$N$dQUm7Q>v=kAW!WQ88zWYKF1)pb%{JK zh-qt1Z=pb^++nVRU1d*u^{t~k4;|CdB>U zl6cR+DWWr0>Ef685})~B65rf0@twZJ+y6`AB^?r%zvWB(bLAb;A)%goQlDh*IY1>* z`>TD!5`EzjuSB%{nR1?!?o7R->*R3}0(5xmScqSbWHrVoP*~k_JSW{*?pd}w+a=xE zIS6Yj_Ph)UzeHHKq!)T6#D^O zitbUL=pOTlZbw3N>yTO0-QXA9hlZnF6x|cO3V|V_n+>`?(J@*?w+e6(-R<~*=<44s zz<;<2BhYi&EV>dMnGn$p#=}?m_6;xnllc*xdDcqrmT_e< z!!qgL-HWF7MufG%-WGu!a=sPVJ3fKE>l4^}34!fIW>I&!UtqsC9I3(J=7V0Xzz~70 z0bQTK7%c+Z2Dk|96@0)-je4&@%0hwt8i^Cb4V#S!t={U}loL$?SUjvt)XKVqtU{4F z5oAmyQ7Y5go7?PJDa`IW-7w^QDwF%=hF)U*XFbLzy7_91F&9`J{4~me-%^HU;P+{i z1Ha!OEKQLK(H|M{lwayAT1R7KaHMS8Y}t$g`1#gDdTVm9-TIL*y{!||!&h0RHO5;W z(;o@b{Vp_25;5xLTP7dvo=J-%On#AIlBO{r+z#`O5A>o*Cl+^lENYBOu%z4e2g2g{ zmc>_v#Z1fMm))~yafHPQg9A2+R74;8t0ZO}VA)(?heaQ{>-r4SyTZJBUu$JTDb8MP z<*P9s^_YKGnE$~te+3Zn`f|DErF^KNqzyu#2evrE{Q4mCq$11@Q%TIaE9Qfp(H>zu zzZ2s}ooX4^7-O*yrKP?{7+;34Xm2?X@jA6-Jl;Ly7DpK06=a-Lgz+INiCK5Wc!$2= zP2s%06X)N0oNJ65JD2nL^$Y3YHcK37O=OynPlSjg`?DM$S7<)YKpBL`?|I%`=JEy8H~Kj>XMM|YkO7_H0$#T0Y$CO<3Dt*Q>-5_j8h-v|j;b4P z*a@|(yM7^)^+Yxp6T7Jj*LGkL?l-2mC_88QRWF%zyLBSq;W$8*EC|TL$2>s7n3?B0 z`KoU7-U2BsGURI=C5S1F+ zry6W!LGu$g{MM~lLZ1q{U=EFLLe=G%4AAuC&)NEivy_?-uN=H@44n4?e;7iYAs!I9 zQN|9w9IH-Cn$VByYvkxdFg(g<>D`U%*Hz%{9p&Uj`Hr%?al<-kIu9ZldIvoD$iJ#% zOs=J8isW?BM9?B)Y!7Hj=TOp%3^MAVLF3DobJb-AeqI+uoG>cYO$~)r{7HkxQR71z z)xUOQd6EXOcBp1hRsF-HdchD!mm1IixIox{alKL>SxPEiVZh8_2+HYocY3KekU_1@ zAbzZm*m#>t#ZUDSTWZ17LcKy6Af`NG=lY19X;Z248-2unj;nl22%ZR=$6=+DlV{oZ z3ygeZW9|+^bBL!fXPslM(kp^d2=&lr{uSBwJC$KQ@{y;fKSfwin_tW1Li4p(*lF|Y zvMs0=-`~jO;{JHqBK*5-5$ffdHzf~Is>_ja)cwLN>@MJP%}0j2X;M+J?rayAxe zxMY)VwkeRO}8l}%o4N`FHsiA_jXNvtYw1HIFH_|`P; z-t02@WO@}`be^qXjZu9iDpWSPZcXDP{(OY>Cf99g#rrF@7hzq&ze{5U$FH&#{QERn zgOd%g+taSEw;N!0q)BDV*7}`k+z*~1d%<@JN9Q5ER5%&Ihg4|cAvcFvR9(M|Du;X-O=JTgX8 zG}{N#6es>e%f3|UKj-4KvhzDP#g1sw6dwQ|(iGps2kP+}LyJxEOc3d$|0d%OP4QV@ zvL|&izv;K^N-BR-46Rkrf)VJJRMlsO#v78p3Q;QF|1(`QR`HjXt}35sz~u60Ih^WM zv9wSMPg-bimBbqKT4?tZpnMU1fyr$w+N1<)81H(LeB7X@fxSccp>{&|LF z0;I!ZwpfK2Eedf3!g~39j87rPib7~lm~o;I&j3#pfec{IVd^9PiBBX)Ac|s<5s%pi zwTQantXSgT`2<|8lVK!K-v9FgDW?^1x0KdfN_zRBkv=SD25?zMj-i4Hnfy6h-HWW$ zE|X2k+^tq>m&umn@d)c)=?d9a)DpQ;wi{{>7D-Kn&`_j_6IPGyT7agD8jw^I}Q7w@FfUe4gT7U$hmW}S4c&iXx} zq6!k*EvDQvdwuamft2@gU2JH}K^NO{&ybcbAMz)*0|LK*y=n@Qa<#0i6 zghz?~it;R>I9@cUFI&{S$m~kM58dXdg&iZO9*3CPMfll>=%%+#+Bruckp88Xh6D=y zf#dvvGyH+8d;#P?c|7a)K-ake-0Gu62fFNVwZFze?)CNf7VnZ#E<4`wvMO+}%g52Q zjvgWhpm-$YP`NQeyhKTkq_w+&&nvX^6C=)nk?n@5p`Ok@wgGA*{r`b-nq?;nZ&-?u zCFz)VnPkh^F&`8e^h?t*$9@GmHI%>lssKN@7JwM}k!wJ8b|v7417j|MQ;$Qab_sr# z15~>LAHT=P)b#{kgr9#SbmEoxh`OtcD~9B4DSsh(yI0%15569G$A_AH7owW(L=^QD z8hTQlfwus@OT*#zkXIy3s`wHUeJY~&nq+NCHMJS|Ie^DEn*c4;K`0Pt`+FSArI@>& z)<~Unt1ssnI+Z`?7kot5{}-Y+TB7sb@eu_ZK7x?J$6ppmu`UIl_iB=y0ylkY;M7_* zxfk_sSHwx*X!UQGRQR~mz7oNi_&C|U*%jfp*2NbR$C{XsMD$Q*@{xm(?8b<5jz{lC zAH5rehNh>#HNBgKp0-1`h_kD9pT1RmS0~}#WVyD{(P7bWX28t!ZUy^OIk;yI2%2|t zoOgx57hh>nM8YBwn8m?Y!8nN5&$|(hUn`+D^Z86IQt)k){9hy7Yyg}@|55;WrkQhV zcw%V6n{L3cScbaqOS5^zXY^+H4 zqX?Hp#FIlLufw&7mp+&LqI&%;;Qp_5p>nXy<@^xYa;a&3e?=Nq!v?(Q8;wynm7%wt^j?cBBfSZL zUjqEuqws<2c-8D2d{p6MF41a>5jq#4sg?MsJq|yQAym5r9~rkIn^pM0rn1Qm=}Ubj zi2Jg*%a;YmwOsfLS;ro0{N|voO=b!!;*BS^pQ{IBFSC8gcBuU zz#0bFc-FE}{*^CP2m2XFah^>97H=@xN7cAiv*^Iz2W7p(Xpd+`WVqG}OvnC}sD;Fo zE`VHOkwJgBX;17kKGY=%uiOLIr}+6MhB*(qvXfHo@@N08HO}!HeDn_2slw1w(EE>x zVJ}n_h)FSJWXwr6MtB(MEB*C4CNRGYFi~%d6`$@S_@E^yOjzS^3$l92BdFr{`%-*n zQ;>zK=S@uXDvF>syz*5#jLqYy{UZ}aVy3UvM`XPt5ICCEw7A(j0}MlZk30{rzSWfk z^D2MN)_zxG=pmz=dqNx@m%vQu`HW6+1H&?((P3QFEjITLLa%}$jD>XQ_Xz1;<&Pnb zB`cp{cXwZidAJ*IUN^I85yp^h3zTzzXnwX*-!Zjx3lD_YElj!1*xx}&5Os5`nJP3~ z-;45QZ%Q=(S{Fi5P3ugw3=FrLz$3to5Be^llPx---!j+?M3eWLS`?em4zh=u#4mzU z)f5xhYO>b`VhwACL!J1^zMNkBFF9>bCawGnY%q^H zEz3r?EL*I$Tkd|E`-S$|wWZNofFAk>PYu2hpWRic3ath@h5DUU10AkIm=*t}(EAV} zUGZOuhi}uzCIePURp0M*Exd(1SUfE|F4xqGiJiwKfO%yGYnbSJoGa2mz<;$Ez`oKS zinLi&&S~C^F_LK3X3?yPjW~L~Ii!!SH?LTP(u58G{v>$nTYbAm^o=vgYlR38?3yne z?A2c~&LMGTX1p>IlfG_!GSc(_dFWs2#TQ?Jxj7M9XvwJb8i-A2umLbj&em+5X z=5m+;T#_Jw>38Z1)1gZdl9A2^q>Z}DtS;104X!jr$;?49F6}j8E5;q!5X)ysGdm3* zz3;+sgR!;45IP>A+I)Q6#*ZoZ_%}bw@G;J~8ONFUgdYnaC+&!GUm-`a`q!S0amH<2I08{YzDwB*hZ~!We4T-BYwV_i+sCcVS zEVVk;Z|DLvmv`W(>N=BnsU(ylHho}VG=4BKylYuj)~GMCvbMiUT90q9$Dzrwr_|)$ zT;=>lY{M6Z(y>z8Y#B4JwO!6%^!Wg2N1+^R)hV_jtgXqj`n&+_%yU9(FJj7%_(@BD zH&}xdw4uY?#0@U$93Y|t#nMSP0MlaUO8t- zZj~mZl^*AZU1t|L&Pd@R$B=t4Z_%Z;$5zisp&?p}h{Cl4P}(z6_y*(`M3k!>&PaI% z?2r|h+#=rC>5*Sq6R$DK z{|E_)iT_t7SCuw1Ec4BOWpXzE9m3k=|2vbbOIO`zP5!sCZ|B?(iOKx-yUgqBVH#2O z-%H+`5HoW@3m$_>Jmcm3AVfKJRnv>Vki z_U;LD^~4UkJ5(An<@n~Gv-QdA;qIXCqu9Y$#{L10k85qg)AGw(8y7XRJ~rZCn&?5Op<_*Asi7FI4m{FmWSh!AWQ3#o_EGV{Azdo!@pT&C z-+$WDi$WKh%> z%~%&i&$BJ9e2_^+=^%wqGP)OMor?NJRT9-oJQK91)c0~%M!q5NK$6wI4{x=$PGg(~ z{m}Eq@6$PNOn!vQ#Cv#tOy^u~Bf{Fc{**3T(Q^9xKk3|Zfvd~Hx(4r}Kjo+lUPz0^ zytV?(8?G|A(yVSFU)pt?3|@JL+2h)Z1$tjsRMszP<+hNjYB5piH|Z828+2lXt}roF*_k@ludgG;S@efQCHS;YU-K})a^K_+mBvHJ3@uffEzo*~UQ9LV6`WMkM+jV-h z&G>J8Wbf8s-KBS>`L&65CUsr@zArUL58Z0F1UWAWqGbU!FN;@2RoP4`2oG~K}F?HhFNAi8#m2_3JkriT2>fk-G$6psMOFifW3i2 zHEl3RGN$>X2^@mfdxK`o*S$9F^x>*TyB?=6#F&|~$HchM`m;GM0+?`o6p_!4f z9|phWDfB<+{Uo}jr?U~RNa5{{9O{aEnFNPo%@{i#?V&|75e!ZKok&VMghbuck;V{L z4KYY3XoSQNf?7O}v&Fgz1_k5#)BI$xT&JoQo5-vEG13Cqe=Reyzw=^M)ddFjh!1w3 zfxT>Cpxm_6z-EE{sxM5yK@m~0bT?)1i37x3_pS=1>7r)oXmYl+uYqAy*pzR+i%>7| zBTRr5HA@oscWmRwnrIrSGj+7zNLlfUGUZq~)-SU;Q0t6R$zgnbqskjHcv^0d{uQyc zeAoT91!|0D)UDnReM1IIHzB-ieU4I>-VW`<9N^9L1Ce+Sz;zo8H54$0SZICJoo*Sb zyWPgNsR=q(FDAiP-QrZ;mZ8NqFNme6ZL5@tLZkYss{}(Jweu|1`9ld zR}I1;L47R$FXVRX-YD9ta}b z=^?)6si82ZkR0qv$O8e%)TegHa`PqKQkP?(3#ofbS;;!f?18W zSyi2Gc!`0mPYsUt5H=ZvaY2Mx7NP#n-7vcz%zkf}eP5XUg3Jyv9Ieyz{AzHxiP{#- z>R6jq)q{qYM}i1#9>S{z;hiADMHZp{&2E_84rXtr;adJ%mDoa6}N{TZ>RXD5fV6;QwRqy~C@jvcK_t zZsXo0K1H(16psL`=t$BrE=BaUUT zcV*O38Fj>hBDUXWt-bcS=Y%%z`~Kng_df4^o_p_FYp=ET+HLK9b~`ZEdQcntIUBqD zMHqX7Sag=w=d1>gO3=;js6u0;d4!J>TQ<8HM%oN3gkhVTA=NOH%-D;u?J)LEF?Jgp zyOWH4T`Zb_Ab0x0UrA7*4l>o?I1^QPwM5mhyX=sDI?FoTvW-TzWSlTKO5{uvh_L~T zU9>^x?7!LA6JLU{zl%j%caLy@bo~~j96GNuI>X0{u|qV2vs7}#mKko@yNql}>F&lp zV**v3!edVmgESg@eZj{5LdG5<7G1D=glQ6Vr#r%Tjn42|Ddm5-8NRR?HVDIZH^VQ6 zq2%g4SAzwqFqRDck_}z+4;Xr^STh-E=u!omBxr#S!Y~pe>yWqm5vIOACebwQF8iJY zUE-DCy30eokzZf_ThlM#qIun$fZ5=(EL)j+gTDXbx~n zZ(SS>if5l&BQ+kK7*8-+MW2uHJYaY>$9Sw+D*ASeF6SZ1oIcYrQ*l+H}U^0|X0O+|afSSk$5b_YwQiVlsjoNZWk zI#_0_XiALbHp9}61HdMC=cs5}jO8W6a<+pdT}2}?mTwG8hl3?cMayC=eIJ)ZU*TYx zs-i71mMMm%)4`IB`V?b1*08K|upEV5c)~*Mr9<=VwY|(AXPVxBMCxuWp(po3-iu6o z3I8q(uecdHZHB}oU1Z<686LD5h6zL8Cph^gip@5|cww02W_ZnJNEe3rZibyUL!mIV zxfuqfm}FK6!xe6Zu{OhUVR*>RFvn*2lQ6vFW{BDhR|vz;ZiZHy;TB;SveA_ff3g`K z7KRyah8t~$=Y`<}H^Wml!+XMTiksmzo8c>A=yWrDVl!9+b!l#LGwie(`U%5FZiYd2 zjXFdayqjFf9BVVo5QdR%hD^f{X%Pmh$%}-E7ZPNNz}3?<8nI}Hh{3h3)KVdDtoM4z zp>(}VDV9mFBiN-h-*jK$Cq?Xeqw!1=6n!%m-?rUCBfmM~OGYk<=3;qy!yG@+1>ki<3)<-oW+{)tgyECQ)aZHIp$$Npf`Qo$D2OR z0R6QNYohl|YV%TRr zn8+JAzDJ;A{$DmHcDcG}E+1)Z7x5#!ItkX=-<~lk&>RC^Hz}CQr;o1$u2V3NPalta z1LGlH+Rf!7jPC>2DauQTr6}KVoH6V;&KTk2jD6mO4u17PK?04{CIi=JUJKdEytXAc zwo#NY`d}KMwdNYC0)1@)CwWEjwCHfj-6e3;rk^TZv;)LOpTN zVfE|5QAGC(K0^TAG5Bu)3y6(R$o75JzYLs*N#+b!p zHv7iG$g>WykF=PxD{)CVPRNd?J+P7QM7S7p)&V3QaeCXRYsK_8t=-as)cheayN=R4 zdySyeH1KeTNad4+XzF`_*7RySP7E4NDl$>Xl<;dbdG86o+r$u=A!2j@>On2$ZCj6B zG$%OpePyD-XhAMuaOKEFMqSBeA|=M^cQ?!`ZEb15xl_EuNm)Pgww3k5mq&$$kG1yp zXHmWR4BwBQjA7V`fbvZHdN6{1^jr+C?Z6k)>$mh8zgCm?wyEPk@mBOZf$MdzU7pw} z(O-C5yKbewa`aEVL-kr&zcH5Zt~?w(3L8S+VzWl`yBJBEW?uQ5u1l*?-UlA2OMv!i z{M$iq5_%cxfd{H+Y}E|@ONCBFa}3j6$3IMbTqU0PGLEQuOk==fGrLHdOTcw2a&HCry^sA=@fi{6fDv#fwpy4U<7>BLJ6bPU7^GFYUJ5c%ei5-U^7jd2;a+s z#r$}<(A)MU^jHgXO*(V0bO`Pza~%6i=?sj$C&GOx;uaodY!S7C?6J@@FBu1;Id-Ay>uqgY_f?paW8TW;fxLA>0U+FNhlov8!n;LpR5-;RgdXHr)KnsLtAlIZQ(;k z>9}eogko4KG-?pnYr3;W7(2PG|7?mayi%kdaA-P1Xw(E=G@4Z8E=L4Dq#dQ~+RfpL zA#s9qM&V~fEJ;LQYxo199Uh}aessi|uIV&*8h%i$qMx|GSQ|~Ok()(~(y+$XmivlB z+dl12HJaq|-`KGtcP+K}Z4cW;ZKu*7Yi+|nOfA(M6FxDu)ap%}FKdD8&6Zw%gF_yA z79Z=f@@X@Rzc(F9cphB(iitq)BgfOBgVfw}57rrS5IP=8g5F<}=&a%l=lft-K$I+E@4{M7Z-u=@q9G>h z%3#qB&<^=bq>3#_wF1lP4uC#|^k&#QM5di&t`0U)Y{!899LW)}crLJhpF?f|fO#(n z|3WZQO8FET9Uf6Lzmp(083*$Y9v!PL+>7wzu1O_V{@9t;jP-~nRV2>RmSQ-%{AC!n z2|?8`rRYTf50Xvq0m%9sKgHkUXW%yE;cozN8)8J)_3|4<)i6=TN{#{}D_IO+H2$;a|2AW{|HNk?k@o}Fk~rXBarcr*HAhfL<9MvFr(qbKo% zLv(dOTjG!PP5fV9LFv-$rM5Ai=LH8X{Zue@6f1_$;hL9XHjh5_I6Rtm8XYIQ> zwYt!;91+{uc8PHO%pBPGM%OLsV9#=Nad${~PZ&cFgTZnY*(Ee8nM|g;TC_<7SErPT z(t$?0jfoZWaYjl-4iYjcJJXP3F3%`axpN)zCCzdxoXP21Cjp=^{eo_ zZ(vS^Pem={TR8L`B#ZbClIc9HbR1s_qTBcJ!Rt%VzWJK86Zmctx@#xOs??MN`$O*p zt#^^FcY;IjB!}L~4!u(xdZ*fYr-|N6hCpwY)_bq5H_M@SwnJ~WL+>1i-nq8k9IZD) z9f#bJ96Q#omxsQM%G3)%&wPzO^Z)>_qhZt>0wCl~HI;8WD%l-x3TNnBR6C+%5qlTb zD$3$JB^oTd^T%2dEb0sTF_0|p8d#i+kh2j|d^mu20Ax)Ckd=X-;(Yx43KILgdql0c zb!ANnUIL@$lh0En&r2v3ygt_5tYa^v(s@}zlMh1fo*10-77|kndh&Nj3=xZ00ILR8 zd03tOby@6+qUP_$l6rpC>?KV<(Dg zdCI_iLGW4I*l<`v|0#yr`Ig%vA(RZA1abo7U|{YY5=8AY)+|k3={gcQ3Uy?oNL*;r zxAt|acBKf~0Yi)G0Ic4D)T{*X9)PUV0o3KASZ*Um3h(m+7)c@+Wi<<$=hm@LSzo?zg9XXGY-o-DIOc|#W($kLqTSTufGrNo5l&*fp z(1qVcd{_5>fomG!d}Qb@eq;KX!1FMFeRuaO#!~ECR_C?U;cWgr{1$cZnystz`=GD3N5;v6%O3~Z4m3wV3UJr%L`Q!wQD93B-uCmMVxp$E{p{P=yAljmV z08)Q}`#2bYcg+hY7atAaeo%_%0Qil9N;zoD$;I^mX8(!}BP&H~1$0rlaEYMo!Z%64 z85}^Q9^G)y?sIGR1qj1(A1P?`=N zS-+jQ)l&X17QvYKBpB1jq6t0gZrhkX4rBT{jOok9OiCXD?!Fcs($H^B?#s4tJfwt_ z>MOp-(;Jqfn6);ybhn?63S@l)rV0Ax%kA{;zBi07#`(U z*}um#&ejTqPb+W2ZWwfv@A1)1{i=H%PIC_LGw1Z?ibj3I_y?Y|AvC?E0assq$P&|0 zTXmS=Tury~5eRJtN$^}QvW=o#W{x&EZy4llKHjgrFMweJ-393Vnl2Zdfy)KA(;2`S zxLfd>g-E`d(jPfzJ?|sLdhi3ej1UAmRX^#>!5ql&z(Igt@X_<@q=Sk6f{!wgE-%!t zw|~J$B|MpLZhXl{CnxlKssF+B={TKVk2%{V4Y+sB_tY^+w@ryIAFr&JeXpdM@y07Y zKB<^ZQEFI^PhR!W^9W}WrOJAZ&19V3p8dM-K3GIK{f6%fKwJwbQItsiqUb3XP%W#_ z={@&DlimteG_49{s&7&w9!i2vY6T}%C#O;;hmJ1m1E|nyxKn6T-DHobIx_XX-89bXd>wT{aRiD3X@X^%+oFuZF(xLdW znJL%wMUt{~l76t0l*LJ!%y~Fl=O>TlG_3P8TjwWUmaeQh+Q`Nj%yE%Iia@{XY|0hn zF*fo%!(_pQeyS4Mf{WOK$-EZT!Q5;OMM);; zJN@jt_2_O2XJ~>G(Oyvyc6kcE@-Ncs@I~PyG7m>-J^&c~p1*<^K)gxPHEA z4!;8aQ$M|9eu?tv)4bZ1edb>UUxov;%knf~o1cusf^I74oYJB6z+_CELfsSLiq#3FDmNRxv07QMyjV5d(0`gsBE!}`& zvQ=ZB1c8;-m*F~7y5&O?gCQhA-v;oVe`S=+Z*R_nCq`4jK+up{=5o{D!4=^G$jo6c zrSYHQfpazgfr~h=2XJlz8XunsoU7)KTzQgu!w~4hk>aS1dMDE_=nKBt)UJN=lTV57 z?~$X)yZn09sB>9?jCt88kC)+0TJwr*J-xyI7kTKM$R7Tl9-LT+C+cWDK# zQ~cRK06Qrwp`FV~`le_b4sZJ_xxm&p(Pdq_5P$VwhEiP*?zzbK-~0t|PzeKowbtV< zhN!NbD$oYOsu)>&DJwwL|E?sPyQ~$KdYGC&(4*(RS3?p{-32qbLKk*F0k5N&kj6+m zJvv++==c;voDgLYe1$zzw z{S*il4Fd2GfCUsz-o>GfKz+Rit_+W8|qQTivX-6U@3rLG7eU^OxJp8-Rhf9 z^jM5{=+cVS#S-`h22cGEqZz2lWq~x9id-W+XF`VNLYSVYlH7SkBB8qs^_>?BX=JHapz$}F zjuqoS1t)ubi0%oIqo3;K!RIr|IfJYIr?+nb=CgnfnnwUWBpqma3CL z(_F_HDV6)NkoEJ`-mSNG@a`F(J=Ef-(Nq2ne^aL1Acy#xF5g*3eBR& z2!4e40wjKfARvn#A+qT4A-7$0(L<6R(ovmvS8}L*7G=3I>Ub6*&cMTfodkkz@R`WRk%!WuRA}@;8%TY5Ag-XO3@?Lhd z)CpV^*Y*Oxp`>lAPv!0sW+_d*sv$ezj7F|h8$0l-7z zvf}vwf`=lg7Qnp#YEA-xS!a{#v0@Lohq!H=YHO;Bydh*t-y9~REw=l3FTAAE(_0|21pxwf$fI5|)1uqgU)Rb=4 znuxqX$Yk7SCW5^im)OO)NPez1j?(P=w{{9x?5C>`RCt2~=I8+SBQDEnpWs5;uS8A< z2zd*}+_wK9ddSEXMwb|=cf*(*R1r^}Hi+D1hvwzWSnm&OI;UR@MfyJwGN*r^s=08s zbWMLkM5`tFgHZw5(eBYSmhb2)pW%?N)bdWJYSP8RD`v!MhJUr9_mxJ7bd6H6Gmc{aJXU325?z$Hr)z!U z9CV?#OT**L*>Gemb9`+b=&+*iioCDw3UA;Vhe0Z`U{&VjvKoV1(8kwMwotWD57PvmI~P$G27i3>D+ujYPk+^n~4qtZDM zF`km-pW2W7RxwM3KNH{ZwwBPtfbd1qz=r;(O9>w*?ucfm7Fwy?rg=Ounh|%|zA0MB zqNvv7a{R6m*z70)NzsG(I;W^PFW2(q&OR10seNF7YFF%50MYFtk665cmmMj@_CJTG z2!8D>TfMU8vUsKGsv>VX8u&3Tu{~7cskYdU4zcC?6H~U>vVvH)T%g4$Tdo!|Wy^~$ zZF{hNgTu{8ZVxDmsr|%Oo0}?RQcHsi-j5(Xw<|kNFm(z&_k7Hjt(d6wsYB3nrw4|7 zgP!|x(EA^T4*NU+^9VQvz)Av|0o+AEC4jF1EFi&}zXHP@dg2Abw}{e=rZXn6BTAg) za2F?GUE?&7ryM#NzE>5}obb~^O`$B97+CZ@vLGG_I^=Mq^EWW0j{)#4fNKf(6u|T& z0K5a>9RLeRux0=x=$WZ_1c0is7?X@;%9dqKvjMD;fpX1}KyaO_$*S!V`C~dcU2`Km zbc)W6ZO(A=ICOt9Qfazu_@;2K@DBP`w+a0?L61dd#nkBuP#IT<01X+Yh>%s2PCyARh8#Ro4$CJdT znv5#%EL)RjT(-DMl8a;W_^rq<*;Rhb#z?WxMR)V4dT45~KWkjb8rsKC3o3|BH;Ed$BS9p>=X`;kqS zoTuhP&qy8eJh`5l&uxKC)O_d}DJ=zUgqB;*1F(QXW6wyNK;ma40vyjsmy0g_j6?_H z@F_b6^N(tVPPdOJ_*m};KBJh55!QX22ev$bhIO)VsYAhWZXjz1I9>)l1sn^ASo1zN zzvR1h?aBR81n3qZq&ws_A*i<4Q#4hxAwD)DPil8On}8_p57bf=WJCcOQFZ~IPe)~H zQ|~uiF9q%)t~(L799-pH8L}QiNb!^Sxt)}#!nDPhca#!Mp`^SSIP3>#SOWSMuoNu< zFk?Kq9)uPz1J(vC^0dgjh}86f0Qos?f!*8g^Iq!Hw~|g6sdE2Os7;jRC12ZS9*Y+K zjK`=~W#rUI5fAHj?T?6fuPnC2>V`PB?xt&c!KAW2*Rpd;^6X>@(1(aA1g!!bGnhYP}n7@8mHbkydt zupjxbS1oVFw2Ve(;qgrJhMH297VhGRTvjxSyvlvdA-H=RatWmxAr$sPA;@||<6df=Q`ZHnXyLfLnp z*6PfAmr6(8n@&VZu);A++O;1oXFCj&u1E$;FF3TMB2T;2ga6W&!=zlPmpnnV(1W!% zF4?Pcm+rIFT~Q=C4AmB*)4pMX&b)iHW{liaZ0s+Eb}+mkPk8y4iU1NQDTJPe?O@=;tx)a)c~0A>7c`I6_)Y2tDyt zzvu|5j*~$SJ*GuQ2tx7PVr0nwM7GF?<8Rkteolw*Ty1cwPBA6P`gy-e>X0O{UqBBM z87=apcc7Lhz2Q5AK3`~hyd*34!;wASw)^O9J;~m-NBONiIC_PLYiuLLSo9eYezhHr zP%EJ9-{G+JuKnA(L3$X9MJnw&=>us#;90SZ{L()i^R|IscB{;;Qe6?7^fhWPmpSP7 zuE$0qEiMt>EFlzOsvW{3FLsFklyJ)a)%%G!)$x4D!g@)c5@ETKSsw;r9)&q z&UJ!s$=41BHKL;%$_$ew?NlYWI-M?}Yxf|E2+TyyIFj=x48#(k3U3mbH${e@+d|&0 zQ^ePr&5S(4PDV5&%oQ;Ff{1=$i>k=4LZhM@`J20?zyzE*c2$!^Gro!ZB9l%3oMEY> zSda%_;pj}A9V@glS9avMTF8doT1cD7QVY3A%To)vS;%DL%Ux{L-Hyw~*(NJuE#w}@ z;5qJhcPjUwAt)MDBwj{l6!k1E=`&`3FZmDaHLoHc`=h#B^f)Rz57ZMUV~lo1A9kN$6CEq6!%k`QXzmPP5{6KvL8 zU5QCxFq3KLH1%wKCFBc)9H~R})QJwSKGY!@X%~d7J=dt&M=tN~gKuzXc&dwrJv7f$ zyLnEN881rMhgy&h@^R`;bj*eg^X#|qIvw>|r!x0H`y9f!T1BHsW0w_ezoJEN-rjVK zN-V+hHmzkdelYIir9Dji=ID%bqSy;wqzmD7r9al%BfZ#$cO!yc!r-*%ZUEh;V$Av& zfa2%ya}luOR{^{Opyqu5IC)c-c$iYjkjx}WAI_m%%c9e!Vem^~ET2X4StOf9atkx( z>&O?~$lk&}#1e)rxra(%@7r`B`(SF)YNEXZQeIZ#+yps^H$hrI!xp`jW)kmtoW%Pb zC-HvANxau_67O}KUXRx@R@9d_HsJkA*bgwJ`%{R4c2zB@uEa(+>^q3^_OYqF%aL|T zDQjAHQjfhx%9`GNz?HN)2jG$2<9(o30X(XEF9It7&geb>;N+A+c!W5bb?7Z<#LHze z8f8*20GSq~-Il)K>i*6Y>OFL>ZJzBqg?B=MPGP%F;kSJeg$~rIJ=KxgQ*~J!rIdMN=nq(-D!WE>##HO2Jg?UjkYwE);BMqje4K*J@olfVA~QP zfRD8{vp2@9ycb4uoQc|?&&+(kwd>c>Z_h~W~O5XwDN8F|KZ#6FFzU^L-<05uX~y^ zG5XBRcD5S}wI|Qv7xrlUQ}F8>^uOu(Jkmio=+l0mZ<)KtF|y5r5{EZQM6}c9!_7-2 z2WW$mwXNqjezYXoS$=RT1{H^GfVmf_>4r1rF#P=Zh71&7qR`;mG|q%dZq$6FQ2UYN#O$c^8jg@Y$qdRj)j z`6^){tG?Qg{tq1b{W!IaRmku?B0nw2DWVZ07O30WJ$Ub^nKSmcok6I!ibtb{fM=Vn z9#E$8LhZK>Tb65mI*0U_!j(hYW44T@(QxFDV|7}oYyGnpHuutVUW}7)dJMc%jHNs} zZBb0_rLJ;#d>nh64yO$Ap)z%Orgs@-pK*?4muM*(iw-tYc$Kn{NmR0NUah4#NoyS1I)%>pFAFg)bsLSk+=9ii6zwZDcbiIx>6~5Y)jA}n)>F&+ zN00gOC1_RC@$(dFdki=pl%e^cgaN!uKqi1WVE{(}*i66(0BI2b0{}b>U;!yDt_F5g z0oqV2fXRhuL#G0u=2dek0NgQS8q)@`g);K0xZO&{@O5cS9!FWexgV+B8q?>F+)j$$ zca+YS5?IaeIa86}MFB0?r)ULOO;M4drLh{AFZ9)P@fp`&6`n2Omq?g?Jf(ToVm^v( zugUQ0h}lNrYFU+{f@;uhCJIE|CUi3CDThgyI86H3=C@6XY?5%w{t*X&;?$2yi&>HzSJ1BkKT!iz0mVK2zt?f@N)`kbJ0ft@`?bw0bu=n0M7xK zu>inr0ICSM7C>?_S_G-7*##`*O_ge2cmRe*S4kyqq-gr}=+gr|Z8hj`L8$0>0I3TB zgaNz@V16cm1;kt23MlVbw60SDyiULc0HTY~%q|B&&8+OJS&(bpN$G zA_>5jSHWH0m7%ydS$UiX?77QC_zM&UYK5mY4%9LldS4|WKN+>XdVET@uR_>T2p2T~ zSOZ{w8G!Px?8Scq^*#g_UkyMV533&lzruJq3zJEPZgaF&$?uUxiFY8UW<|BCjZ_rf zdra$z65jy&o_>n9AmBq-QuH){aVMaJNv!5QV3Y{7#v+G%YJe`gRq5Wr)B<*DX~sE+ zD@5uXErFf^Erz>9Q&XswKCvHty^Ov{hm;dZ?bwf$vZd~j3?r$-68CL;iY@hyNYSyX zxh!SQL*s%}EHM4-(0b~Av<|nm_LX9x623`GNeNRiqJ&BHBw-?h-`kJsuVo@#pp;iN<433z-!)<7jLND7Kiq$BO)B%oD}w7C5qGSKz&{8+wrC)#Gg#o8t?;bl_`x+vJJ3 zs!qep8(Z+8Gv9kYT*vg~{M@^MZuC*p>q=|rkU_Ec3JR*Lu6JS-7OhyuCvFyczw{c8 zF0?j0UmxqmtbtPF>2OuFytWpk|15+`Yj|HvHIL|n?EttNc{^Q=teVFQ`i(}@1pQW{ z`GS6@(Wsz1G+Hm{4;o!9=#LsbU(lTz{fnSKY4lb>cWLw?L4VfhWUG_%Rgb(JiPgYdD| zo_7e&$M6B74PJU64n^@mj6#2y`Kt&+!D;MXV0ooWmXJmqoOr}L8fAs!r6=W;x7O7; zC>wF$#{MyA(R9hWg(u88Ks4s))zSkuHn z$H~Pf1L#qPZtH9SKN4^$fGHIKt^?4#1i+mD-X!2r0LhgA{th6WfDZt45b!O4%>be! z%F{SE@qG2ye%vlS%drg5Amq0+E#$3wR`XHU5nK*efJ@smX0j+A&r;}dBRp=Y=J_(F zD0)$?reRtZuj%WrW8ify_7ON85q?)#Qg#c)?o10uA6}}{Iw~~79*wDv8N+M9;fL$B z&~^I|YKaLYhrES?sqik5ePbW8i(;~z`sl<4M@n~UN&R$6GpR^u$qM110fo*23ekx~ zH$YD7tqQGVBUOcuyq*zwpHMO;$KFSsC?1FwbygJ$ZJThR(4q){zL578V|_HVMC(8t zr|VGN<%hfv7@qL$V#*C}hNo?Y=Y-)IH^Zxjp`@-w$KsA$)s?{7Gm~KLXjmJp#)}9? zh&^$jy1BzgNzh?B$k_Rji6uOvQOAC=iA^H^Z-nq2#>1*x3m?#|(s>Q())0 zWM`fjbI~R@nJE z*_j196KY`RDlz6*t;$jK;Y%fGl{=Q{CYJCWV#ZoG!+e|J@51nyo1xk;l-#lxJCo5V zuO0+Di(u!4Waph?j0aRM_Z*`n{Hz3x&_O0QPO=&5#f%I$!<9C}dBRZPX1LWblz3Ym z_0x_S^%HiE8VozjVQ1n}*!fQ}=2m0p`9?{2mjpfUj^z=XVazfe%a?A3EjGg(Vd#!1 z9p(P1VJP{RGe7N^Rb40Se39&IhMgCaoqa2HToJ7*DWYX2>)QC9C#gXD95eI}mo>1v{@IJGY84-|lYbPZHDz z0*>4$GqHrnh#3>z3@dDgIl@rnX1LHWlw7$NJGa8lenVmBR^`mk z!zJhucP#5nEa5sa<2^US7MtN*VffX}u+uP<10y`^`Vds0WGZ}}O!z;y@ ze;Yf~jFRxh5)=;sN4Z~RGmL50WpTKh;WnFLjxfw~GdyM(N_s8V8aRjSnBhNRXZK;S z^9$H{J=uA?7;~{!74q8L;b$c1UUw}2FtLQclI(iT&G4zs5GQu-a5H>o7)s{t#m=p; z^M0~(7wjC_2s=L%W2S@3se0Ea3GbAkMLNioyUI4@{*{<k9N27FbVQPz)|i8nOMR%i=89g3=?dIr-dQY z&5&joN*;99&zPMHN?>Pkf7m#B8EniHL(bA_LSCCQe1Zhs?2aMN#1I}MS+&{Cu-Imp zBMjTz49g8e$=W^Vr7E0NjtO6RTIz(s)`7m^kYegh{e|d>i~v%!yAN|rh(RhlZu3AH2KZ1G0i*= z6gPJ!Ki1)nAQAH)ZK)TuSnL(KG{c0=Qz`QBMyfqX0#rK}Esf2r`Cwb~JdvVx$AK(G z`|NTzOMa2EecCwNXhPynEYsDHcFZ?x3p}!GE%x5r4q^JU(?tDT2GhW=qIU=jW=8LI zs=?k26@FU+Uv`FY?jaMxA4urG>`*LK$P+ZBW$>uoGR8~?aK@B8tCN7$T!&OdOSwwQ zCDv{pa>Boh*fJK`?R~rb zmrL-=V%=&K!JR^*v<44ymYrViaanD@gg3lV#0Ikn?;UzoNL1yH(VAkB>nc}mo{hn%W0(N1BynXMM zrW<}o#8+!^UIq+PxktPXUvRU8I(>o30u`xtaDL#_Ba6|7ldJI7ITCesn#|VF(p{un z5Xzq6qn$N_8eeQyjCE`@`4jn7W*@ z+H@_YWOntQuCj_Vn&h=P`t5rw^!qq4=h{-yw4}5Q*UcQmH|wT~-c6WEr;oKZV}jY; zq&eP2H={3GKPH~8v2JVze!&p1>hMQfFcr%awP}1KaLRJ*cH$jQGx_FUy~8P;ZwH=R z-5hOguCA}d@8YtuN^CmIh^LwJGuto``#k3DtxUcE_B6Hqg!6?-+3|E?(y=E(8()w#CthEWwEbkh*@v$6iPksB z6*_a{X@OwqDlorFw<+bsKi;mF=jJYHXss`gE~&0X_9<%~+Z;GawoFluVars$ZX|_6 z%dmoRqAsrFiO^FO|Lj=w;Dw-XfJ{*xfX3ATN(nd_z-$2D5^xlNO{V}z0Z`hG?w&N% ztOSNzolYq}6TsM0v7otzDH~31x)s3olXPq~R|CO8GO?ufEwSPOE?QiFb2x^0_kzcB znn$(nlF&;f^iqV@yux}PJ-KEF0~=4Si9?2Z*F1f4@c{s)LNGjal_U-VR2O-96fd&R z(HTG!qICSy+x8mm?!oSLto86l@+}ZvEW%kL%yVT{8as^sq5&tfgo~>C>6+8&%1sK{ zvy3+J%EqUX3q@GlhNDVfNlJ;(^_Z&cjmJ!;Fuf~=InHNb=c)%&)%n8FV~kF>p5`Ub z9`cqPYZ6Zb4oWt%MTJiikyNJ$XPEPlEH0Ad9702{Jy#?!bLR5L1+!AEc&_}Vsj90#IZ<>ETs z3jZ4ZNz{(jvM34_nX+2fC5kFb(gw6vTA`)oA zk$(w&@X_dR9rW*oPD}p_O$^}w#X(;d;}0*FR&|Ha*rEDxWy?@<#5fCLjso$WE&c@L zL@Ek81$8XER%D+OS@z_5<5}bZ2_rlH>98Zg(U^YGbbs4=Z1KclCr5)gYP`FC=pmuW zR<0k7j{1Sw4i%Ypa;zm3XnAT0Q6W=lU9x|*IbGFuIMm)6Q~QWR?N?pY?x8ksb*Pm} z7kR;<*@sa8+8GSa{n4R$_onB{gU@ArOHEI->SGLfjp;cB*%?_)4Rr-AO&BsMZ<_Vu zB<9x^2Y4u1r6Bfkl)mR>k^xlH^b^S8Lc<3v4D1tXH?IsXi29#8Z&UkWSa8M zvQiNo@}`Ocn=cc`1;A5XR*_AYuzF`(=P={ceKE>N647Q`FEM*cS9Zj2)CzY-MN4UQ zEo_-zZcX&&T2C`y zQdd6P7H~pi(@Nx8V?|R7nzuL48ZecNN$e^l$~j{s1ty}fbrQ=2Z5f1wTPvDY&M&QP zt;k%lKzSq9%gm#kJn6L!%@u5Gft5UsqTP9)F3`M27 mSz1{EtL9r_4&H7D=T}rL zjfF3;)^PaevG9iGmcpv0iqi5JSF!abb8R(T>GPt9CYoQ`L^~n8w^&P$BqQFE@aYns zUR7ONuDrKe>kw>+1=Wjdxh~#jJp*!{@an>fW@o_a+pSMn-xd?!?CSCiiZQJP^>}e> zO9g7og) zoPYCP$(&~k=XB0uaAsAMQZkhHS?{~x&~!v#(>Hs620hOdNq*JJ=IXN2TC};crs_tz zaMk;qcW^N!sokXIz-ynpv*fy<6KueAjRn!xA1H3-zPWYxAdSD{(7!m1a% z7qRLUjudhRaEsBo@S^u==4lk3GvO(;cuF!9J@yjN@>42X~fIg~pR5S`Thh zUT6`=Y~e`!JqNdXPL;z+9(CM;>iVLBnZ?R#z5-OJx<|LcwpD%Ukxff)73me(x%1O< zvNNI!vU9UC)PO}_K*mp}ZdMxe7MGSS#epkjofGOkjTELX)C&EdgYCpwMUc+OoS&Ur zm>J1ROV5lV_UP=qg2HHeUT$F|FDEB60`GMl&bi@PQl2LEB1U@BGnF^2x!d>6J-cY8 z@)l~=#=W!VWY2_2DbcL#9GIxQ3$%oJut`k8e${PA8K3U*sg-zwr#sH0cEW!Q#ZRY% zwQiiB)(fW3zKZ)so+OQW7`Hq@ysjRF^GnrW@GN5-efaY* z%0`YPUlQUcZ70$jNBM=L(b|SGT$o-<94E4=N_#uB@0^U&SjiNkh*aqWkMD12rgZYo~?9oEm&HovVug3VP#cI>EbB9 z6!w}m{z%HEpalAY6BeQ#F-u!hbxTFG4nA@PZY;+pHHt{NwCEdq->~lE>iw2vkrv1N zL@gc8GokNEXd>;1yb-Z-*(D${+-0t>qvtds%fAa<##U|on{H7o@|F>SeX+Npxdp!u zZDzrBB1jDaRbxdL{X0TB*E$Rv<(OO355m$YEUUJmCDPY(`$^c4SE2YP=?QDqw*Cmf zw|~~E%kf9w{-oT1{W_+w z=<7-FtiBaA`t}>+KdBB^GB=bd`Agbpt^OWd^zAp!zq(^E7GCh}_d?+0x{A88#+6F` zPQjRhwwB7@z$quev63eFOM2WQmNJ~Ql)r(KSM`Qn^zEO0Qgb6lc`Zwn`5&~(TGftN z={ul&)ik7xz5^;&&qDn4?N{Po^;eWEeFs#pZa_BB*Awrdi0I7$@;9*fq~_+b(t0S@ ze}hi9R^I|v`g-2BR(qgC- z*Yl>;ZiTMtHer17Vr=SMwFrzOg_)`wK{E>qBPz(W?1KEX!t~iHL|A4d zk{3~N%#xRvqv8pIE!kuQyhz%tOqCuB$jpf5&76~&UZ^q*M~sw7BvNH~ zvWSqLrDpLzJ-4da1kTTl6lCWiB__J;IFdx%+LGUU5-tXY)`8NlW_`V=f2;^u1%rp1G zhV3;ay>KjPO_l2TZ{eu{PtTtnNMb^J8Yiq3A*=1^dJhvaVy9Jdv^Q#@eegB{ctYhX zw8%H42ou~nf2_41LW5+@R1z3?x<~b$CTuMrKp(%eQ}v5VHcOTzQTE`%85x(@!JKyk zb>Qa`*q?IlP#8Rb0F@MtR^$CQcCigP20^~yVEhhTfF6{-{`G_O08oa3{RXyyN?&X6 zz)Jkl*MH}rXlp%>6V1QXU)=!1eCp++|L~5evaGDGw7MSsP`>2oqmuC*c;xxt=!d*G z{8C=MWC{8GV(Qa8|HC?_eRMuoq2&F6E}c(b5IvW@jNfki=zM~9=R^GHd={Z%c7x}T z&WAwV`4B{%5C5a{p?~Up_#d4Q{Zr>d|GM)bNOwL=vpXNcr1N1G?tBQcJ0C*q&W8}Y z^C5&fALgLWM+4}5G=R>BSu3G^jftf=%Z`u<33_5fbZs2#a+-gz3(QAk+D1SUR6rK&+?9FdQ*bCXrm74-u&I z;eXxv5V(8i6Cz1R=R>&N`4D0{A7+%!hhRtNLujn?abR}mLo`?CL%m3pkD$e0inGI|b1r!N>T4SNBx&r{+FMayAp8z}sZcfudz97|Pmy$BAB)LO8 zMv<+gAGzv!#Em$HW1ΜHwjGjA{fScLM4Df(X&;V|vg|RAUM{k!X~Bk+LRj7bZN5 z@W)!44)(-^Q?*gJq7KH=;U`RbVeE=$(D4=`z_g0YeD)%vmqMnu>JyDpe;>`s#^gs- zSqUW|gP7qYb|+$A>51geUx*h+g6vb{gVoZyyfWZ#!V(_bAUq)BqpahB#mXwF4%I95DaG0nfJ5_*f@%7cV-@WdV9RdygP+AKKMTHgcvu@5R>bTV&L2bk+pwloR@zh!uX$rByaIYc zLsC}q{gfzgvRLiaQzhzMtPQ@+$zoG~51{=w#Z$~lg zbx`i_(iwOm;koQ-{08>X8FaHd1LDVMJQsyZ?NmAg0(ED=4H}&R|D!XYf9eeQADsdH zQ)fW`x-%e1cLq$eI|IU`Ghi0(3<$D2148W1fDpSgAcQ&t=Ah0%1LzDifX;wf&>3g~ zIs+z9XP_z684#p91A^?%fDrBs2yk=;gqqHPU{_~A1nCSks5=9KO=m!`-5C%P>kJ5s zbq0j#&VV4(8E9BKgIGY!^Jf^27%7uTuFil6)EV%^r^{~UIrl&eVRAgjBP1MJ8o{G!t0uTYppt?2bI#YKfaVI zo1@LGjkE}lf=ZEsdKYzwK3D$FFR0i`gS}|sUUHC5D4JQEo|#{W*<<70uJBwQ8iaLK zf98s^ipCaP2b11Vjune5LI-1Py>)=Hbak;&_PaXF>UEi-X# zZCO=e1IM$8L)JS(Xd@wqJ;`AkbeP?gMDQsN+}I`1mVKIoH~Uol%!OEm^PV>ajVgWt ztwVXwe;=mDXK3Vt;Rx8*YGk}UH1UnShXjjq@^WYKsK_@iM!+RbzDVnUx}G@pl6 zo?YY+5=c~elB``&#E2$*Y`s7P)~qR?SR~v%==l!sj7Iy+X=p=($GYkF7WCe9?L1#!pRCiJn>h%O!T@neBg=MEtX>E31?z+fNFDDnYY) z=J=O_vlp@7k8kh($o_5`f5zZFRWEW%uNyoHmsLD(9tNQEGcnf6Oq(zsiTBh5CgPSV zb}guU3mTg6_`8%Fyz&>|LAMoqPKj2_G>^Zqv{Do5*ys8Dk&5PursWmoXfXBK4f->i zni`t&8q3&UH?Uwph)b5B?^T{gb|LW3#92^L%Pm8BmN9RFtrP98iAg>DwEZtnq?=hf zk!dmE7Ut}03!|O3GO53Dk;_>wNu$wurOiu~r;TYt{8_Z3ZrUcC-ipAD$hl;Hab2B* zx-vld-5F;Rjpl!1fU+DbjR{?I*Rv`>x!1=~qcBUA5SY&~JfjyoCKNEp(07h_upgC*-3+e#Qb(cO$~j{^pmdk_GM=w-7`1`%5{<*GhZt|vI1GE3 z@pg^Fv_}~4zy>8sD0xS&!MJk-74jzbiiugZEd`~^(V5=N6%;tiM^n}@rDqP^uErW3 zG8zVAPYAZxQLpTICP3YELcW7A1O#6+Qj|+8Un`_Xq@@GY4*Gr$c18W@Eus#s|3xl94IHYhf3IO z$m6*tL{H=i`MZa7hAwACB=2(!mh!Pp1N-+1;6CmTeTYCk{&^s@8nABG7%@aD%D53f z7d-wgS(F(AALX7kh3DdOw&Rk6k_GZE&1OYegY#$@6~5z7tgPO)>ITBBQIY zA3MGO+y#B{xrGIVX@x}vSd=9{J0NHcJri1!mb65%I||egGP){oauKQ_?*AXMN(R{R&~X4(wZWwh{HqW_01r+KMltb5 zBl2iv^AhXjj^wKJ(xUe@9 z&Zk(aq>5T~H0JfJnLXrCvGQA;K2U;~GO@eyCB1&pAe#4&SRR_@dJ~iZY3C_{M zRto6EgM$n)Ex<;5mao8Hif4Hv{-%=X-$gWPMAeWtg><4OVMn!W@Ki&-kf4h>C>-c@ z&e`qlC#hlEh2DloGu4aAmGVv;$8gH*!LtgY_6SF+yfuniOvqdE@Juck;*nvr;W&ug zM=T94E&2391$sKLMh`>0F*`?4TN~-9mZn4xC(FPm(*e7)pzhW+)>hQl_j=(T zRl1nATkBtcDqe02qkSrhxr0A=!(6n!qOA`7Ii5nFE=OH5xU#xY z^Oi(PskbUs{(*x&Ch_=K5AFyY#DT$hTP(Z29Q&~SgPEQfqo-q2>`Zv^X5}BkVM*}? zSoF?Ya%@FYLl*X6EB^t5$k^ogbSxR*XbE<&qO&Q3z=0evQU&&$0RPZIl-@msD*t#+ zo9tz?2K4}A0`?NDtdF8f%M50Ora7!zkO$o#!?TPPc@22?`xqpXx^HIie1JU~_4c+x z;_gBF?u*_=<{;l^gMhVvqnY+7DCBERX6nNt)d)a0se*5#mY}O0})^A!zN>h@b_K=(7sIM+BS&pzcrDZMFtL z-)r#GuTf+V5?NY2zV)CiMnSXe9TSoa%v4XnWF-zEG z(|QAz>Ha6~M>j4im`>Rj%*L-jFd4tc;@gcjk0U=(9jd8r#?1ka(v)J?bkxmwO;2&q z%ZNWg)0K-3{_dKdD0KA~xEG&l`QwWYM~|9NY#YUA}#md<>)}yT|;q5x9744@cZBG8X|ry6sN+m(q@wXw`<6;P|O=`^z!Hsf?W&6 zMEHNZhG@;%u~1BCY@yhJ*$c%)b1oEji&mI*CNX<(&~wYCb~Z%-JjtRAGve-6$c z=);RW$lM6wrQ;BK147SZY`kF40!wUauEjW`Cxv>}B=@2LNiQ-1^9sFx5kJ;PW(3=*9Zab_8~A`_B6$kLOyvZ_j82A~64fOThJ8&od z=<6>Wv_y{fnScLEyl@E-`_zY7fB49PhIC6B$EDB%@tL~7Fx2DEm6a%R1Y)5SbM#iI zYdF@$??w83Dm3d4Plg@@R#ntu60aF)NtU$qm9+G(LR$Vuce38#f7i{%#tdB^sk`jV z3ZcGwF584(|2}qR1?-(!#E%YlE=tr7Unm_efqG{aL9|Vm|FJWR{%L0x|6^ws{nO4Y z`qw+N2+}*Vm}c+HB20E>F$?d^BFNsEMTosKix7Kf79q4Vi#cd#mIkmhO9R-M#VpvF zr3u)X#RS@!r75&Ciy*x-iy(Vv79qSdivUN5OQ_kIMX;;GC4zLg8q_WuMV?BS-kC*^*_owb*_jm!h;75lFdQ*bCXrk_vxq=Dv-n@{%p!32omqUs z!m%?;pQezVS%jFKSYG{fyZ-D%<*8Uk_JRL{Fqj!S#2BnRSQQaX7{Q+D!voC&HU7bj7>#jfE zZ8bJmw3auFX{x}sV0f)mN!D|cu20BoMWZ<0Tozqk8pTXMCK;2SL}I*nP+HuI3kk7F z*o3?Ty3hDHL-Y*29b^w3DaH(?cf{|+wAaT*-)_g4k@IqV%v(GV<>A}o@iCv?tcyQB zK1>IWeO=}?5vhHy8DYC0q4sq>*X$2^c%Omqyvq==hqo5^&Oef1J+0}xpq(r-)0&=q z&E7$?e1YIPV$2cR8lnN?M(?}wCgzC8yab*{U5BQ9&O_6l*z~7=9Oay+Ap2NMS1SJ{ zqao|j>H@n+ozHg6KDT2IM(1VD!vrN>Z(op|4nL5U7nzsFD~&0E7Lo;OONEHN8B+u3nx9(#va5 z_wodrUY=mPmnS6F%M%vs*XDo-OCfr*~|9{T1Q@o%GbBFyqxE(k0KYL z`qKVeddQeTs1MtGTI*?f9`^xJ2Z;rCG|(ufKvJGnv31Mcq`9HCJlZIp+qzAw$94vNo=91@zd^?KttxHCYxC|PZ-bMUcG~nERk*sRA=( zDn%`#kF~Y|EAd0>nkx}V;FR+`>VN}Ly^d{WlG(H=F zJ8YKH<`vpS%mt~hg}Tq$2$qq$4Db6989QpRvL2wp!6;ON2dNs2!ol4QVFamz9!0*a zmnfn{!N*#gh^dx?UqetG(tPkg0enlqR{+}1_o&e)B8o>vs$(J~x?5jj^UJ|kfW8e3 zhY<158-USm(}&#wAoBu`I_v=e_W?*wJS&Z(YDB8?Ac>qpn$^%$p|1k{@M=NYm?2E6 zC|80h>hS9&=sXSrEmb9dBsAJ}ajVuD@~)8FSINISf}btRD;my%abTf2CKM|E!Y~Ve#V8d_abT4bvuX_(>{eHln-aou--lKqvX%1wpOp7h zEFW>PpczvuR@TQ{UB^ZnE2<|W;( zub`e`q~lGMXOwYu1r=B^#(iN#{~ftMnp*i1(X)k$Z>zPVhf?GFAnoIa(a#wC96~{d zO$RjmLXSFhE&wjgMF1vVgwkvTkkJPmP7$tBbr6MF|ZKa4CEl$DLCel6^OQe$l zj2W@V6d>;;4U;51aWYgrZq*`YR=1F}P}^E<)OC`&(mkrf3#vFn?v~JeQueguV{+s&cV1i=t;4>gjZ9c0KhYXvId zAp{>b9)V*J_n}7up!_^EgMsr;Is7S+nFVIMthqh^OF|ZL$U?f(d(1Bm3)womvBFX0 zNiDmK+~R?lDW-;oTE4y$8gN~sRQ^DaI?4la+7gX`JSAA}*6kxhSSCg7jhp!enME0S z7?#7WCsSr_2Hig}P8h4v!&l%sL(Hv%I-aPLXQ0=mZ>Vs}67FMi&}wU%bKh2csx^5w==8O2n(W0NeXX0PyKj)2JPK6$S~sfu5W7#^GzSBL zKlWm@6)h`TWS^H>ioP?tgfL|V*26+v79pi!c6t5Um+ap1$JDMBX(akNRFk{SqfDxvz66rs}z&BPgia|47PMW{X{Md;Cl>QhpL zrV^@8NfA0T7&|3JF=YhhloZ)E8wj?~cLWH@2Z9IhHH;Jk!N&QE87Tq6r=*Cj3J9N) zBBU`Wr=$p35tLI>gtQ0cloTOn2j!F$Ass;2*JUmt2mxcgzzaT3RwpQd`gOt z^+A0~ir@`FeM*YpjX^mjMaX6#NKGf}+5!ZrxsH*yfFL#3GqM%PM1@mQB=b2CJ|#uS z_Mn`SB4lR*4RodUla-=wS{_(UK1%=D^gukn9oL#p(IP zBH?b16G;}kFDwJE*nw0V4T> zSc-QZRU*NF5bdK%)Q;gKyB<{{-UM4GDt{BZiylGRd>T8dMAC^&a~@S9;l8#o8cQn+ z_cwlOd4S}SG-@AJBHEDP?njk+B1@BlINIYnsze3R+1(@>ZSceZl|?6BJHLmcO2r83 z)k#N{{*8thj2%@X6m`Hps$@sTN0q3=J1J^p>Ky^X))R*8xRbGsgdu%*F}8&;ShAk6 zt%UJWC6e3T9T*=~A`G4YC?8cKG?7t0szhiqqkL3}&=f}XQ6<7tH4c*= zObN-o2{?czptjXE!LfaqAlg=IaOh|g9ICAawbOe~P-|c9E7;afHmL1;eed=6U3)lZ z-2sE5KZJC8y!*jf zmQAxwH{B1;a*+q{26jIqyyr_S(E)bP~zi+WFLPE&skroU z3MtIpbdh{u=$ojBo$O+D(x|iSIM+rdZ5ekp;uM;55!c2r*R?_QVdMQToQiW`bylto zdX%mWdLq|`_zTwt{Uz6i_zTwt{Uz51{gti_dXlaUk>|QLD5YE*qKa^B(39)hpoHt% zpoHt%pai)#L=AFn$OpJKJuSuw5+%2*25hWIO88}!)UwK1Gp8mA5zH zlneF3w(MN7Gg!=o%^sTy&_?MX!*$D7RS6TjK1EyhHFWaSC+U0fOh5L~ z`-j3(L&rz^8ah3;z=kwtIh+Zx?bF@x%y zX4#vCl6p7n&3JbPc(UxRH1uzfGxi|0-bSc>`yM2#DOpXWU%1z?#%)mN{O4hY_&iKZ z<8iNY;doe3XIK;Vsao~NpRSCze?^R01j8`b};vM*KDtxqo&_(%pe zXw*xsahItq0%o$x7QN53CKjo(e?{52HAcm?X2luSxSdAXF0*W=HSW_!*{yn9f@h{R z>3*Zk#llQufyFBu)yhO-*|Q0UkE=#>NTDD5Xj>X!CnGi12UedsR4b8fS5}`~WX=65 zD&~F8v2yX%DfpZ&qy2LqrK?KFq9#HY?0JQt$w!ep@fkJ7&uHeqREf8dD92EM6klPw zdWjevlfO+O^*t0<%VKh_Olep7qWX;|W%cp!F*Kv$C<>SHf_FXoeJ&BeA5%@Az%%{W zM}z2mjEp2DmyGmfJx95J0=$yozC#3e+ZT&LXXt!uYKh8PF0(`c?6?+{NquZqbv0eyuF4`h-x~LvQN3MdYr1?@l|7*I zt#Q9Ksz0N9kz_p1{)~i>M*fLe267u?l>JF}C&_KxY@;k4Z4Htex6&vpP-U7A%2XNg z0h9|;4u_C_yAElg;Ek~+SMQEiHOOTtSc-hSnyZ$42uafeaaH%psx$V;s=bmrrfIGk+S|LjTAyYYwq*%PLJ z8h_}YJ<<9aP6R$HwH&I*Kh|)ISGn-P8@g$6lfv;1h+O))X1A~<{Ga>+5%*!!6tA&5 z2j2n6K4Cp^ZX=_-Pg+l$+sApStXJjCxjoOrC;1{ zEF1bZIh6H*){Q{bd&$d-dD_FJ2$_I7_nm1mzXc53B2uq&$B%yELs2>A-D}mrvpzI&@Rlvv- z@ZNq@=u;~HT9KcUu%-pKyw=L^;aR@xMm>w#siK2*)w?%0Y=^(s@?9^oa{yhPp5hIo zj?>(+j)Zpq+JRt%K2K}os~PnkVU^DT2K@t7w0sA|>iObV*Ye-~7twSsd=iP|m`Eam z!$QgX0>QjhJFE9Yle9;MQL66|RQU)d8AES5q@a#v=hA9fDe@K7u``g*Q}8_-v>iv4 zQUM{ob~1>D(JyRJM{re(LDV(mTkM~q!Vq+cScz?-a0LqG z;Kx2%jom%%c@!PP7MR|y1kM;)EH3R%`w>c?M`^|*sx%X^0}<57imHrqbb?I0PVw{- z*)sb@udb0zAA_jE*L^%hA#B2(hhQ0;&~H==J06%I2`Y1G)thD(2~7PdEf|{ zwUn|}b>Y>R8&qds>j!Jr~t`{)dGG;I5_UAyFI#IpAjU%m(k5lJL2JGQT-sr~4f$dPwRS@v~Ae`oGTC=XGf zzkRXj?pg9;-_rqW+Gu(lLnJuz>#C4w89Er%&sACPQ2oR7vHQ{VDC>VWrhfW-m0T%C zz*+&|;gTh8C1k#F9QXxiiNwSQ9Bbri)k5HCpGw5xDC5My`MCzWlOuds4u?7^1lzH*-OIA)p1iciUv*A8b6vhZ22|Ks5{Bl+_vP#-gxR!=iN|Pyb1g#gT>0LP{h5Qz9>k@;2{Nc~6VH6y!DG!jxx3YA~fR z%(EhuiqzJo=x)pZZIMnx8rN(3pA)GJQEK_07pW|ycGYYaKz&E#)?B5RUtGRyLx&b$v;nu0V2f%0JaU(9?5 zcq+0I2whYtkj!NIgia^wJ6;T&`(MhWMbUTS#Fo5?mVQpvp`YVEHF!$>q|oDY$V|{wbowN&W>6tp2H4*8xmllIv_(w}1DR`d#ZqP^y2LDCJ3R zC!!Fjxe0z=$!)`)9`an6$O zoWMu^j{j&@Irh|~a!Kp=Ddd%J-cjEOC(6$1MrE?K{GD0EJx)@2-JX7BU80OBw1~hP z|1k-w$}7P&9_kx8L%99@;@L7Q#ze`$6bD)xJ=&A%+0gl5cZZT{sV&y_LSgd-<~i^&#e-w4}glJG10 zmt@o1gAh0LTAP1GHhJE;lyfUZKU%WtH`e^CM0Tntr`?hgQIcVl7|vvWsVL3yN==ur zKO{;=dh}s7Ez71IB-bsBX<04`$4L>tT6BX;%?5TL``2W5V(xxU*aTV^4S$8qykd7K z#%GR!$~BF3xM_9st`&8SO_BB6qp+^|7mFenqb22Q*WjvxWy{yWk^*P)<#@q+;qc{f zHl)%E3zpo^mWoEcq!smzE%?q1oJ!m23ugZ1A|E>$y;kU7AyO%zC2zQuA}>|begEP7 zs|4J7k^@vI8GbXsK@1Uo53Pd4se>uH+LOa}&U#GNCJ%aAGB!0krvvHq2JG~TqV3@? zU_;FKBiWKi%m%vB8$jE-aO9n!SoFLCSIw?nt}T0Z9#NJ(A4Y81YaaEQ+1R|Cmc7)ThSX3pbtt`Sws>)d|`+%k3 zuhfZ+Ul-_*oq`AZ6T`FdXZnNabQ~U<=phdecjEz$pBTg}*)JB`UP`mwq$gm3$c}{4p9%l(w-+zg77^MLy*<;rAzCHJgZcE%17T zpZ^J!Cw~!>avirTt0Rgszymr)#oj`ITSp|)|H(zd8;F${4O`!q2QiUXFcFD>ZG?a+ zf`Y1vg6zx11bwRgCYs>(&!erJAf@9cI91gZ3v5lL70y#x$Ef)(xuAFx2g^5(vc%F} z_C>X{mGnSM+m45U=O@j*b_1Quj;X#ExKrCY1T-#|vyo;anV^Z5b1E&?gQ~%s1WdD> z2R+Bn<5bK%;%RL8K5}`s5^~>E6+i7lkdX@HRUgVFJjm zkkoZE^^^W3O*?X!HhE z3q~;UV;{X0&`R)*Qw1?*MAh0vV?L-Bdw?I3MCDfFT$JDE;u0f)2sH``s`8Tpj=KK&aNFt?7L8N`i67nbWAw{I~@PHqe3F&ol zdP$Nlh2B-SrEzoPeta};HwAAzOR{F|or}f1Uvy{x4RHAAIusK%Uxn`Eyq}|aOHuSZ zk;;Ff19A3sc)(9S zec9Q3^(Ku@$puZ3MtW~m{Rvz~8GE+ky;J=+P;UJdH0!grd;;3jKh9{m8%kUO-d(P5 zAdA2@M43i9Whu(zo(*WF+mWr}j~C%(apltM^86#=(88I?qm$ z!{Z~oZk|KPC%=F7wp`&JkGTxQ&sU@SSq7+lyC`GCtz}HZ5grZN^ zt0+Z!lu?S}d-jM@6n_z=NPj6xQT#=eBK@T(MfxkF6zNGuDT+KdN|913N>Nl1QHu2B zMk!LljZ&n98>L7Iic%CcC`wU2AWBg_AWBhGL6oA*K$N1$peRL|Ls5$KB%>7R$&FH^ zgosk42O~<6k~&I}o@1gEDMLjm%10TcNY6S-k)GWsMM`*4ij?xA6e%U66zNGvDavOR zrRWuSA&JX$4KHgsWyM4(QU*mSioY^SkskX;DGs8RMwB9@-6%y$=qN=|QAH`zvk|38 zNiRy#NV!pplxIdM4zAsb%XU9S%wul?5e~sIL8OM@#b)u4ifu*QvSST}l?*dDBCE_{(k^dXYr^;Sd=_7C&=hJbd zi~6&}8CwxQ*a#on{nXRlD9+frf9o!M76!3^BJT&3hwV}%{z!=(DpA#q3k>&&>MAE= zj|2}h5Y?YXjSPZUXAC}pjD~uhyoQoZEt{biA199g64IH(uT5IE)4us|7Wu1RL|N7{ zJj{O-w+*hP4fIN+T9Lw!pMMea5n^LlRWlBxdvKFt)c!Ftht%xG{Guf6hR{gSpHhRN zs?LGjyBAa1x>5WlOg{mqWtwPofExW9Mi@SVTHZ)4ai>A%Bj|RrZbu-tX1#!{X^#QK zUObfJVPu7>uoqkBsGTZtJrdi{|7aVRBIc^_yU~cJi^826HCr4~iFUO3tZacp2~~wF zf8-~Ps$=d|iKD1G8WEACn&%=01n<|<-A`3g`~vCE(;^>JwZDwLpMLD4-+;O^R#3(B zL=|m-erzQX$@4V-9!jpHVApuSCIpt@7k>8P(Dv3d8Fy4q-c6w?ry zpQTLPUbz)_Hi!)NRk*DGM@_C5sQ50<@IVJb6@hJs2dz=t?pZ9R{4z>^9aD;rjmSk9 z)u8J940UYGmwGq|7~WO+L{jwb3Gx%!EwGpfFDuN;P|ZqQY49I)!Esw$0E zuSTOTR)5ax;!fQ~vC#!8jroF6Nr3ZaYz1(|Nwnop1Bc_J-UPok?#QR0JA0{3xLx~s zInX)4NeGO?r9!qVak8xi|TF}Qbn+W7aq$dah zS!NT3fFvf6PJxA6CWdr6rcA8gg~eTA6K#AG^(TTvg&JV56ji2w!?7j_s*>sNAw3y# zqi)}>{rHLp=nGeI*{eidyc(@M)l-x#tF=cp{*#;*$=%nWsM9JQ!0%6BEoqsElfuMw zqf(B_nnW>wmNi*NYCw=o9!SP0&W1{kj?Cg`Rq;D$Jy#YdvWaRLtWm}Hd0^1jbO;P0 zM-zZyogM%OV@BWyEk17opEt=GwL(=Q+0?B%B7(!69|UU!>&U^MFzd(-Sff5?^!QRt zkC-=ZXz7vz5_!HOiy@1ySt8b7%zJ}1Dr!{91Vsq?+GNld_0(|8>uG_mWcEarUQm?? z^xd+O;FSSDAMLc{B7l5M`u!f-2xZsPOdKK-mTwdhawE;M5VH1E66j1kZjJgM0#*CDprjK}}y{l{lO(puV4=62f4*fckYx3mi@t zP^W)OL!Bp}E<;*Eo##UR$ln9?9GEg2b|L!GvTI0cB(hD4>qo?@M0GR~d;=n`ROmoE zWZ8OEHjPeU=P|=ecA(8zYXrm!HZ3WLcH1y(d3?cNK|NIg=VI~g`aKgw6)kl|718H> z z%ZArhZEK29ZOivxl!fc?VglHysHp*6r}`@=fG_mO{*BXQ2hCM`Xk`CYG&08v>@rj- za2ugeg(?MZ7xG%$X5u1|5=3ZGLXJ&6By3o^YVqY(LazNL+J9gayU#md^T5BoM1aM9 zDKPM}S;(Z^m@fqe-lS|?m*Aey13&*XR<2o1-+=WlckNEh z%tr)@e@WfuCMz*(1FDKosP5SY&!liXC1z6vAAMIt@R4BdPgA7T<FF@G*c5!0WoR)H=a3jgF;;fE zAo0Q6&Ugh-4B68(bH)tI&ip!h7*Ydyn?+<}rB?014HI_u*HMRc96OM@9-~)+b>Qd1KFN4sXyjVx?Zb$QmiFKr_(LUnreJ9Lr~s;18Skr1k#Xz*P45Eck;I92X_DRy zlco`rYmYCciCHD$H_h;?G(${q&PEKpA0yEO=MV?JibN{S{W9v)>DZLHMYZ0Hsu&Vk z=~7{XyAw=b+fo%Xr0=gZ&0dvC3k%&y&&TQZmXE)$ zxuL9ch?GBIe~8(TK6ppq-RQ$la0RLqqAYuYM$~MDDEsIkh?|5qC{FeSy1n#a&^L!S ze;4#>kul;VWl#hPGUyia+mVroJ3hBW@i~!6>B#vla*}FbADm2`v5sf2OT-I3bXD1u zjVRvulw&2QKCl>|Sk_ZusMTQG6bOeTtJoS8Rt2PGBGaCcf|Feoj}5r0DtopyI7wxXKz8ydm6(J?v#5h%EEgzYLmE6@RieSHA+)Y{p=#<>KnpYlsw6L1 zcG?V8@fk5E5}rrVL@sd}JwAx_&`T^b-VqsciPLC_i=L(>w(JaA-6l$4sYT*pNZWe%_gx=-);F=SaPYa%WwNZ(_AwZR&ln$;nE1gw|C(w1XsuUrdlaV6% zXR355#`%m}Y7PB^kq_UTctzzQOg&9XJnusUDFkx*ZW-#V{`j7?GxmY@>0d$y%WT=& zw6$TsrT+L2q??xs`ikvL@c|%9{tg7w@vbw%2IX(xY&&Z=`k{Xb>oab{ANrSY!O4t0 zO!zNL_g(<;J!4yoL6bh~xhwynyF^oDTU~uYbJHIA#T*i<3bR1C_<3|6gi^deHSgOf z8_1vf8uI)5Q+GasY|o$iKUC=h<#WF;BK!^hR5AR={tQ9@$I_-M7b%u+xU&dU6ptDE zXdad@0ZLX9y;^YXGY(v;NW6pTeU%dUEF!jE*@{vP$Ciz`MNzgn$_W+ zZG3=rH%`rs`W^t#l=Y>>035~$@f*78evrf8u~B;;{$-)((3iV&vn_+L0v~zj{`h;g z?_+*D$S5K#fzC?1G0x{2>_>f2xoyjI>R6-;(C^Spi|T;-=mBc& zBvBD6da^rMX10;Y@&*JY5E!5eRB)#=On`>2htu#h_y~8t$&?(adH^nHzN35s8zt$4 zCn_I31^5_=k}*b!z*Md%!8FGLJQ`5cABSp#39~w5Jdi*b6v&>CZ!a1q7Qs&w%@s{> zb(YK`=qDjSixx@XY;rmhML@)qd@Hscd|PwGY^UV|V5&cPnC$J6WH7~am76?y7!g8o z&OJ-SoQ#jZ;i?th<8ylC)m)<0wamW!0r{< zv>-(U1_7qQ2pSn!jfH*%$D(9Fkp^ch>{~SEVgr7$fJU62u2W2di0Mg@f`Dj@y z+{FW0BX!%O!K+=?s#jlWAL`zVnGO*sVZaFP=(Xc&(CDp*Jpfb2v zXHeprm<&vLt(SozToEvWUy(i3ju!%&?|rd+;E&~lfaJUcQ)F<10|WsiYTkfFgJg&x zdV$(x%^M^Fl>C4Q067mPd<+)Fa1;;0sERp=`%+C#8fsFar0q11d?6e>R3gqiU$PBW zCKnx%kZ@U23kku2*;?r2XrVLA8|M}~mR*KRioJuVcZ4QcqKT0PS&z~M5Efonnm+E9 zjE5K3&*w;@M=nWb-`D-}y!bK?Vg<00{Y@7*h}dE ziYlFHkfH>Y9Bfk05KTRhd`b%wgAR=)inLf_O7|FEZ`&CjH9-1#w19>5Fbfrll!F}A z+)zPq$*<;6s7k82P(enRlGIR^pekueI$BH8G5v&9t`=61a8f%MM>(WVjn`y1!K0{& z2GLE@(qpm|FH;O6oT{4;>1YioUe~$ALkY3Kbb|#zkq~Dt`yiQbBvH9Q(c9e6ypNZVZh{@=&4I za?vpAs>ov)yyD{}v}9eVvZUMuLoJG}16?Yn29|MgOpTAggRcG|+0JkBWWZoCfwct9 ze5URpm`v&(7%$1>r)14fDY5*dc@Qc9=^2A#*=vX?b5mXX3N26Ws6#zkf-v>?CkFrN zvCEiY5^1JE*;xi9lV}ynvS3T8*t&E9t_0Iy-G-Ym#f%9@i%Z5Jj*$i#qunSYiBhO1 z>J-smfh7gS*da(k8C;TnsUVxNn$yQ=PKR33zb7U7Cs0$OD5>g9)OjAi}9EuUV}mPSp7w)G#{eDpi!&_0~-Fw8cZxF#OwJklKPWG zLM%yeB$fGq@RFz&O)YbhcbH062vj909*GY!xFANiiJ|Es9-*Yl$GescBV`yTf)AuR z<7hyHVH^$!*bD?)!^ac=*STg`GjX$nM02x#J zQ`oeaEYvYcZXh#&x$VLf;GLG^1w<@;B*apeum_UROq7&+kz)=BFUBr5$VIWS&%!dO zX#vIoj~PLBQavBYC@=}Lg-RT^c|s$WVmedmj|1+yv zBOjD(8(@#sDl?3RdTxpYv8NJA67&eJkUGL-tuHG@nFQukkC%j=>`BiUioQf?yC55J z*r$H;48j$vSiV$j3nbK3MQ@Z!&Wnwb`h{UmZj?qBA_FEulXH}zP#}Q%i&2qd031L; zCJ~`{%v6xUa(|109M3g|f=n6=$!@JCyS4{kJV9|20Z~zEGgqh#13X07! zIzn=osO;MRhl}B1X&j;L|B$FO1sM8GgQa(d_1qM>0%F(kFxFH1<+g~UtOf*v9tjuX zfzABhsa>`Q>x%Z^AG~Ji^{&tKQ!W#bLLHXXJdeRNk36IftWYNm|6pEB zltX*n0#5)J8gjYFtFLfF6kExdaL2nOG|Gl~i74 zj;l?&Y8K0lk%5gBS`e=^+elcI*w%glCAUgEDPAf85ISf`A1lZ;;GV(CrTAT~H-$9@ zk}>*PEyC&K^9eZz^hT4r+=NHZK|!?6#15jtWkYIph1@l-1Z^m4l0>_KEJzjlOcyq= zMXf5`G~y%WGon`AOsaA<$y~`dFSuk)iD`D&ez0dSyru=@c|Ople8b;T2+=sDR$#kCnd&|VxB0)E?F~NW=_^( zH${rwL56S@qEPx#Fu@^4iJ)@No+zcTAtX^<+Y^=WP1m|~hADP4W5uraqEH(!YIdxg z&Czmpn3l7!B9dGaa#y-}N5;xisN-6$Nz&3fxR8g?z;&sXhg$I#w+4=71GnMOw>p;A$8 z;)();5yjHZ&@yr+xJSvRS>9w~Mw#tRf=1Ei2of_$&XFA`i3VxxX@OcAcyd|dT%KL9 z%x)6>Kt>Bx&|DyK7HEkhe6wU*l#;^G=7S1(VvQDhz{d@{NR6Z5E%s1O;4jvAra_m) zi}$5cEH2Yxak<`6RwQ9ZAz`>u%PL4;(uqrqE(E4a3DfY*N+~7X)@8=tQ?3ih6|0fg z{{$H?kc|ZuEcgk%Jzg&R!xw2VGeu4`H&ghUkq=7>SZ1?zyVXpCNSXPxv43?y_2O7pEH%oBN-zz+&)C>rr;renZ z9!2dDq$lcl6jN#@X{nj4#o7SkQ!I%mKHWj2@Kl2+@i|ac zEWsv9Nr_e16{54hDj6$0J=%frBw8ekF)5i-`ctA-W8)P#vgm3q0K3OqbYti}&tOZ$ zt_-M02x+QeA-5>!zFNwc-y z?nnwPRzRr7N_@IjgLNMMg%tHxfRaLurQS$zq6;lJ`-#O0gACCw?7>3aRQ8{j+B21w zi+%|~SE**;CMiv?_WF?-T6nt3surNqehlQticf&P*^{@#s2?s*^|9Zl#G>GBVGMww z!4#DVT2ykWV19s$8$%A@;#NyV!bcmCmB1V<1t#2T@M*g;GF3@cKtpZF#jU%*tOt;; z?jb%yE0>vCxy+KvB}q~lyC|gaKp{O^c_gPc4JUAM5vR7dfL=HcM3y9P?IgoIVZZa1 zmO>Hw>6znH7DR1~bkUXqKtg;S?=C~H?xBxt!b)0AHbkHHm#H3Nz2Tm)GL%v+S`^Wm zYAL8YJ}Qtvkf!V6-#4Ey@o~R{UGg=bUB(!1Awc-Wil@#s!cKOioeSbL1nVcpfOJLzMIW3?$ zEkSacXM+4?nrhVUKBZ@9jgsfT5V57mVk|6r+e=ZcPMC_+|Dos3q1JkwG z$k1E{&kPZIR;(V9?P(f0vHa)xWMXv_3b{2jmytk>t8y5pK+URj4s=;nvz*}DT#uzB zLxSy;j^ZgaCI^qFgjPx>NU=20q$$~rw!{g(p6pSMbWOV(I#d{Kh*yjRA(^3Jn^OdB2ov}ja= zc;NxouW}4EjGY1+xrG6abfZKJC^biLtk4{#8B*(xv3nE+MT$+yJJ})pN{cgud5~Dq zJIM&Wn~&5chEZ}+ya+3U{AmlLWfbI}E6HE$i~WVD_9~Io1SN|dOeteXs_+3Kl$c;i z%@f*<HE_lF(a9RKU)m&k>BtDrhSrF%J&3Uw~DZY(y zD8(t3@h&AbD=Z(OZV?fJTun+AyI_bFmphXJWU)fJYPrNnVgm6SoF*`u9KCa*54?Eo zM3Rp_h2V6qA;7yP=J;}SLY!&k6r50Mnh!$Wlt@_VcTi}(F?hKuMN)cPV&6akH|aM} zTy6UAlPQvC0#bNfd`naqCt;Hmy9Yw1kf_jVv0yUeJPK#^#WzIF%0o3P>vzxGW>S)< zeH8r@5Zb~A98nT3YEP17o05#&)9!Zay^SUY113k%1L8If!6jH?l-AQn8zlmeFU5 zAVtXf2ic)HTXL=vknwWE70wVEhRy?(IPN$CRago~D8VEG;fmG+#L2i-9wvz8OZrz- zG7OeJjU^IyhUB1Rtc%)(lO)h;nIbR@!yXN`*60#R<*lYR%C;wWnsxnQqB`phjZ4tM z6=Ko==1M8|;i0CZScTp(Odqvp$ul-yHPel1iAf5gyMa^4zxHYanY}Yu2DOyDsM3hEA`K*M)D0sR7}1z^h?d z2fYNXyk*^J&&A8E=J}6S`(<;e2(2OI!t>N#c=dJj|w zQ@eUZzhG)lvH06C4Lrvq*o&JsN(8HU?~=Gv1%hLkE!hK|@R?#HfzLq(2Lagz7Kilj zQ7u?pXuDQJ(#C?kjOcYq>v+AD9`?A#Ne?ga)Mrdi(3MYX5`LpZOgo@833}%(W}oNg zK5qp2%Y{vnN0?+y+9~vQa~wb(eqpoU)2*6k}L!+ z)@M+$1t)p02J1}_{)~74FAf!s9UBB7NO!x40^FY+)b>H=Yo)r;b~wUFg5T(+QAjD0Q888@Eu*}6eK4;3 z7Pso!h#R7=$D)zi0>?>89xo3fmKW%lbZ$C zdU~Q1q#t5dF_ElQ-$6>@6Jr|N0X73~zt;SrMU>Zu5I59ATw1^FKV55Kc-2O12j0$} zr8Svst&+jmG9W+E`jXW}69QJ=qzfbsx{zx$Qm)-7b1i6V8LigN-C8^bkC&JOuZF~Y ztlx(2DBK6AIxtERuZ$^mW0q+o zNN|k;0h>1r5ZBUcIBFMAFXG5k=U9Wj$4L&u%dUDLx!$;fLw64|tVi17Dh_=lSDO#K ziPCU6#XLZfpfg#9z?aAgbHD5 zMd-dKoyD8#%DoQ)hoM!^O{$*y0uGleFY@}Ttb<Kf<;JB>nm#nl;+tfUP{SOYrsCtC=spX%Ps)yL+-e8X{Y}&(ulz(a?!2} zurDQb$csu+47Ontp=)d0qvUvlk4&e9$986Li$?-P0Q3eMIx^i9MA>krd88>gCPqI4 zMy7x8rtfYT{kH*A=gZOOh1l#Yzd0sV&n=1P+oqC-!AI z8EqvQ;>`|li0YaE*%;Cg~pks!bRKWMG_Lc2xSZx?uov1DowdR^HURu+*mB zh2#ixZOtoO45=n&J6c-b#z-yDBp590MJ{al=#t>0*Bofg&BfM%I(jFKRlPMoi`Y2Y zCKF@H!90kelzf|pB#{?TxFX~tTddd4^l`?nl-zgdeQL#TF*bsj_uD}T=Jo`Kye1;G zIl>qti3sKx(!j8@O7#RwE(>U}u{Wx%2AioY_uii#SZB!mdz+Q(AHFQ3@I$MY(gnES1mgTpy^bZ$b&AC!#1l=D8@A~ za`!8U7cqao%0@!|L!#N`#1MsPULYv186pZZNC|#*wlxD`FA5L~jOSo}}tnq@@2=j>h(1S^$9*(}uV;u>0 zQ^1&lXS6{O>OE>A8Y3($?gR@ub798dIwZ6I0YwL8lGcQZTEkOHl-BW7Dc#YiSe+`z z-)7>Ow-GS*f#=+5TE1MO^@ZskMkVnXuM5fZLVo=I7E7Mk`Det`K*r2i0;V^bXT@fj z`q+m`OjiU70@Q{qwY3fC$<@Y1=4^5fz?$W`TVsPnJRA}snWtE+ zlsd(dGLdeOlDCCwVuMHb1AsHJ^}l&1BAn0Rx(RvxTlMc zDPLW@^=EOyoFTBdM24D6qJa%lThT98%8c@^= z$)2JmyLWAdn4y%R`q~W0C)o3(f|=Ui>-OHg9S*R9=987FuqJ*6rGck4zQpZra~8_flC2fA`IsTZNveH_`9xSp{`_ zw(g2V4JtGy|rNZvo>&mU*~md{_Q# zRo65j0d%$0?b#ENkC*~dD3Zx7n{g|7(>9sFXCK9t=0L*chB}$o&{)5ZV&F`x~m&X!^Uv=m2-6i;n@zzP3^&`ADC$l27=;3dYmV+jiA$k@B+ZADN+h?Lr z^Gz?ZI}h;oZ?k{1Bgfc-2b}SCXg^^yRP9};f{O7Z;V z{rPNPWaeGSI1^|^#_|2FEUAJ;BP==p@duB6{czV~sAjXByqy*I z)nEN6OX_@-&$^@zqkccoj*=t$`&d@rE4A#X-O0KSwz4-4be0c49j=_k5_!ISa{S-{ zsIFLc`tasJT%kyMd;RX}f=F|{r1jY@9RumnrY(6h^JfrEeq{Q`7jrh(?V)djSeEPp zs|5&fPdz>cif7OveVj(n9?_&pG)TKdgJ+CiwXG(KM))xws%r2>D>u6;8mS`+#}9gz z#G*#2mjf0NA4l@)_AHc@6m_8zdc}8rHxserr%u&JZjnlQNDxSf6!TIvy>VZsbMMkEKudq`GBI~-kx>ye=YbqtZK%dppJB5r*y>VtX%P$6R0cQj+t_8O zy^3mI%JbR%b~is!#n1Ef;C*aJ50A376>NISPC z7ue%AKi9^tsNfxJQUz6uRPb7sTG7TTDtJ2k^1+Jp?2z4a{H`M{Y;fo4yn?!yUwq(Q zmeSpeZ@Gg50<8f)o|l8{yADJ^_CL4t#WQi@n|3Rn?-%($v-59e?^rwyjeO`hiKq4Q z$JvlGY;UB4|EZVPIa4yv4$9ZtY@kUy1UrJPIqtH zi8hwf`cxA?4oqbCG`)DCdDWp^m0!7$FRXl*CAqjQ4e+t-_ZB}Ty7>G-UO^9^Wp~)^ zEYTTfN1bumy%+ez3(=d}HiGgh_%SgqZw=IbK|U1)o?$gS!uEIaC>HM-{y>xs7TvJk zgTQrOH|jAqn4c5%opEUa_U!}b&}$eoQ6oQngLA3vPNfxO`xP6+_Rs-jvqulo?_LLp z{l)=)>NKE>unecfW^W&GmfGysfS=uU5WnuAU*jQWpJyBRneaaL5(aQ)rLq&(^HabK z>t@$dsWTePhi`O23cUgDyNFm6+xkU!dP6LJ1R3f{8X+285eQgZG5HZiUc59@A`d-@ zuYN(4;gRH4Zgw#}SZum|A&)PqY-|p*Y+l5+w6f7f*tJd+UUL`Q!;4BTlvGY%SimxA zEyk9$y~r1_2ru3Aho3m**=$H3+nc`(8{eLdhu;is4D;gJyZHH%%3BJ9_n%nveX+Q$ z;y1%L1VKe7LTm)qf3Gve{u;ZI*RbSL+6D7#_@P_)I1ohIbL*(yGps&x;$~-lmeIu` zmfXYE@^igxwlmLW-#7?jn90xZP#zYrkL~CA__Bv>9})WAC79<$mhdC2%HOuL(Pkm` zntr>Rr&+0u=i_Z}-i8*t)&zjJ_3e$;HSQ$+3O}yK6ua@6`=QX6Mix_TqKK<6+j(hd z_190V{uFB{x{+m8u*MoT*qLu*6?s-(sJ1ZJHk;36L$CsSOWBZaCqMl#U-?*=v=}=8 zLBLXa_(BM#_bG!VLR{wt_>7Vbq5BT~in4wgXctv!bF`ZtZ+`n|+3WQ9E5uphPk>|( z3xw$RXG0L%`TS{qD<8}6=3`&HSJXHc;1iBDF68gF-E=r%$yYFBpONAi0w&KA$ zmLvg_0JI4J+E_g&fo0dxFE)jXD))u?1lGjQIFqti^c4MG0D3-opn|<%L*}16$cvoC z>FoA{LhgNykE7Yx{Ek3ppsQ(n^ZV}}X1mXY3d`D9dh4x#@wF7*ir&B61o4IBnG~7I z4>35iZb-2H7`*vHDkMFuEh#g|D&F|buCFkkaO-GynIPoM@ zd&e4aajyJ-La;(v>nBxX6ia~QDwcTuTP3cc4~oaC-POA_-{CupQsTP2h5=l5#B(eQ z3w?63;=&&=yQ{F{s$gNk*@(Om8eeLeH3m^hJP%3_hSz-lS!AsvG>ap2`?jucYEV(m^ouCi;LVK^M)gCw= zYwTp>c)K$x$C;PO){^c!7V0T$p{H5Sbo-Xe7XM{&IIjS@VOJ$JzYipR z;%3p2+<6MPfU{78B4tUp08 z=Cg)UmKqVii)zc)hc@oy&5f_}mw9$uQ$b#+5~AhN#xQSVpSk`N`!nlfw_YD%??Ykz z)b;I1w<2AHzq~Yj)+x*&X=6W)0}&e@!K1@!`c9u^|9u^1eXFmN{rS2G{yLZ0c*@69 zPx#f!>K*r=<=+Mqe4>)I^so$~CWozr$ezvf51(W^@*yCxo@*VrQldl}%{T>3$Z@7* zvF}*UOuJ?N;es|=B$m|I^?L8S7oKK`=T08N@?aOM=)dX&JtoyJ(UPP<-2=a?`y{2j*B!pPI6+}(Z)jm`^!+7>6;u*r zj9pXL6};&&zUN3ei}tbPqLC#E z?PQHTpy|pJ>@p`0tcJ5j1#4*Mudzk^99zQEoV?6K!TH5(P&=P_@HJ4#xen)&ESOQk zPF^~@<_t@$VcD&06VKh%HuatDYFJISsBRW$fBIvi-Bad1g61de3H>&W58oJK*TR(fB-tC5 zsC6l@L(a_MEWNuNGIp-b(reVipc=t_XBICEv3;dW_M!L^n+>X9kw~*CvY~yHb!R4ji%p8KtJ~j;9*O_2fK5M>(NuZ1PMj*=vd-Xd5&Mnh zOtWu3y?P(9BslWeX8zAk@gQd`Fh86T!9V%2F)t1`LNOH>jnwTX>j{?C(~AYIE3*%t zV+q`#d=sO3XN||XGT)#Z!g+h|VtTOHJ+{50q1c&$i6Q&h6~!|950-rjlH{C4wzDrD z?0)Q*y!`#9mKp#0MSf#5-?*Ld!glwtwC=8(_^gUxcq4!5=6T1F&DawMd8c^zp~Z8r zdi`N%Qw~e&3D$-;un6pWMQnd5B>d7A)?5MByLw;a5k8Au&d+qQg7y$Uv>|wckA;59 zd)Hlk*&J+g`EQHfUOylX#f&{{^W2T)dkF;SW?f&nmG+CBQx}7~-fApsd#h~0!kte* zfTgoRJ*=sS4Ju_19H?3S%&*xiHjIEgjU7ICicBYOO`lQ6iwoJ;4;Hntm#p?Oeidwz zWSNBKFu&)1_V9sIWiX+%AEB}M44&~^2md77-@}d^sOXADf5Yo9MA;ueGvjbTEQ;{c z>~ja5SrE`xgbi_K*lceP`!uxbWM_%Z{$$bq^2vkPRh*LH&e|dD=a#e9W)B@CV*Zik ztg+cH2y18jAeM>^$eEZ9af?oJkl9*1@2U$>9N516O>A;a3BT$v=5<3j9A?pqP#gVx z0%ot!t@~zuzIbXV)N!P_4FcpGROq`%>NHhAD6yuRyTez(_V88wV~ItqCBHbdk5xkg zVoR@?w1Dyf^66!4=Q$wA*<<5?bH|;BqvtQ+=lrp4l_Wm* z^P=3HGuR#9!#FB{P6v(0KN|^zo5Q}thJ4Xs;v}XDKyD9fS=~g z%EbT>W4K>C18_jCA_0LByP>|R zprL-(E+Z2)x7SA+c16jpfFD!ND0wB0&YoAFxf*j#Wkl+DQMU|yJw%fC>v z=&DtP(Mq?|=X|Yre)_tiV4E1Ck9{3|{#f<-hqEVdWVvTvUU5|$r-P!ytN$?fF#C6> zuPwyxxuKQ4YxRUeP*3rz2){mszlp7(Ap4ZvekK?W9b(^d&LHpCtTps<-onpc#YT3A zPDBgX%XVw1@=7==aIpB)FQ@(*9vD6u2k=f2e2zP6lMHPLZD+?Cc_|MT zFW)(b(~8_B48Ff%-SRnH7{ow7O2}uOP-_33m4-v?zUy0IR(yk<1FAak9D>0fwQq-e z$Y!T}eVxVO@=)EzP{9HIO_<|P*u3b~vU$ZcseqVT;CR=~LD(;FJle34wX}2WA&C`V z<{7N9on`Wh(z?(XnEH8I=j`Q+!)u$bY`eO=t$;PO!Yehsy>kw>nx#5>XIsI~Sp7Ma zOyi~ZgFM2)!rDrfTFUmeI@2u!wOfNYsFt!_`5iMtB~;l7@ch8(M;DY8>|;Ytv2f2d z?Dr0@`N`(R4Xdx2y6Z121$zTh&raR-X*LoEKAyc|bz^h=&VO%)8U5xC9Co{4V`&BI z|HEp%Jrs>r*5(z=#rU6XIR*6h@rn?wMN5%Ll;XLgrJXq754<8=Rsai51lB8TEG#h} z2Y^W1=h)0Myl5^ou;QCvbMiAzNRvoS;JV&haCpA<6l*vG`mN#n<`r+}M_5wpg$s|d z$DmIA*s9nFEu!@>&vfQx)v-a?eM(sijrl@z>j@gPH?b9|?=}-OJ&CQ+Yn-W>tJhZ^ zLgqJ`Tao#)sPMIB$)ztQ_EnzlXk#;44?T7`_(#GQtW@~p3-sW(IOvTNxqB!L2cpQW z2=MSp_9RyHSS`azahlB@K8V%*FUu*g@Bf#&-V2A|Y+23rwDOWr*tsmDys~<(Gbxkp zL#1nhaDE!WS+yv9Ucb{maaii+VSPHnap;a}5v`{u;<{fA{&kf&%QQY;vEh z5!^5{SbJp{z62^hBZ^0NU-(wAsh}iya%0;Qy@j(XdF72n)~OZfAk41qZewFwyZ#!y z@E9*>It}OLS)Lb+KE~6lgE*3(-cb8Wu)5$F3LpRc{HjOT&~wyX?MYc2uX%(GkIxtupYda>k4F|hQ@^l4)WZy{76$&C^)C_X3hy5*K%1}Ctnqf zvI(7RQajJ$(~76RdUeC&FvgrZi2Thv2>mkqm<@ zZYPOc(axqsSYUhi#-FMbeh<_df|p`EAJ3C1z`#fkdKE2;CE}MOvc`}+JA`$hc&liyH5+Z zuzRuj^$8y?oi>NS*2OE;_OiJ%q%1U|rb{vGx zm91)a#-(E_Uph!q;58f>>A8sf3O~2n%d1x{Y&-w`XYcyKEi1s1JB}4D;d7rWr54ExF-MnA}c^tquu-cZgQSH2J0}J!g6NRB2uU}DK7Cp2e7}^O#+OY%O&eR+p zdgl8_I{2-j!rHt~@Fky=faWd4OgqpafALE8SEx;2w)^14hM}v+nUHywbsp$sPutFH zdktG!#DeYOcTtcnDPsR(_1y^%S{g!JI@$l&-RzDVARhjWDzmc(`r10!7wz_2$o`jH zT1bCVN?D}nJe=&MUC!i;E7{O9{AX+~ESQfLhIgK4R|9`fJJ>JI1FdI)k8j*S2kD<$ zMREm;F^HKJj1H9BJM36+^@7Qw|*&si0iXFCFoeAmeO-$wU@Wc#) zeo#-rE3hRV=BuVedzm^S%l;r!9XHTY zz3ZGqz1we~Jr@P59|^)_)zkG#Eqwee?HnJ5qh0BamRHNJ;kCWch~3C5rgpy2tqq6Il#FYs%a*+@|Fq}==&Ogd z)ZEXHg<$38+q&4bHMML+=kbQ^hYNd;mBFvoicPSi?C{xxu=4E(+L3ny#KbkK@*-rx9NIts1;+DI42s$HAFC-o6 z`9KY_pWhEB!G<<=+rd(t35w|NE?)c0)3%gu!_${*8vlx4Ed} zE*^g72S4Bih2b4+8??AKGIYcJA1b>f#O4-t6u|rsZ6K2jjw=BM+X;wUVc{-iE3`EaBv*P*hUI{%6M&K_a8R_I*8xRC=?)?=z)?Q1_5ndiFV7t1( z6Hhr4GM<5-tLxqjO4F;MEPCU zIVk9jFLwS-c!Jmoiq3(1;OOvp(S(TgGV{8vl>lhG0n( z)`ys*`p4RG%)RTQZ$BS+1mE1$RNYA7VZaa_wXHjf>A_-mWY}wfS%*BT_v67g4Zi{i zqPuYa81@33H^&-hEauSgW>pu2YfCEm*&y53%0~9Qx?tfuwT_LaJA&1axpp7F zmQO8N5)G{i<2cZFLpM9(Ks|luh6;9%!_yEd1uNInPw^Z`w`0wm7X1ChQY1dvTpB7P z_5M?k>fg0mah_QihVyynEuXyQ5JmsAewt^Y-kr_7HH2!v7p;yomx@MjB(-m2$=!$8 ziG!zZMy=mP>D>6aq*grtGAa)O_aybPI}UW7UCRqT8#=aaVL|Px-r90VSNJ+U<6t}K zyP<}C#epV<^U1~@w0tt!O+%d*L*3Ub3<=-k?F-m*PAgx`rzYgxFIO)iBO>NpP{=Cf85uUO6M+CRgFmA?G?%~7_Y zB3Kd(=LKiNi2|cw6ykeIz6b>1>sVDE9VFltgvJ(O!)w|u@FTt9CwRu`!st#c0OL5G z_!#+w*ljH3RKsyR!D=FkiUJq-OsRu)2drq#;shRk`}>cQWlnQiPXs|L=38hFUg zzY@G~_C;@EN8CWgzAYL9k2#?5l zNWtScUd?0ar}&%H3ERQX@$t@-baq)MTLv@7+o*E)L7}s=nHA)N2ME~UrZ|&rc2#E^ zyXSh|zBEE9>n7SVK9@q||0~tzu9QePcoR0M_vSB}b-uQ3 zO>e=5nOy~}xf?s3Fm$jzJvc04pDXAUZos{4@F~dZ8T(<|?z+0IH`s*X;Bu;9-N_<(?9Z@JeUcR+Bf`GK$Us1w(EaSq>wDS|rq}}j+Syyz!!8cF@ereE z%(K^bBO&=Z(975C1v=-ywiEaJN@p;7s=hvM0y>QGEu$?y6EEE#xJ%DxPMZpbW7?tX< z&4(Ljv^`2(`pT}-M}e5f)8R>>;LEeS=rI1}^ho$n$6KuN9D6d-!&@#{1gp>9;s!+j zbakyowZr>}Hs4QZ#q+23QIkIQXwY`Ufg~2D-;8KJ{{FvNJO{G`!Y-fCCTW{NG5z_tN*dHD1>)07T-f>o% z^PBeX*=i~Vu4&voeHw?%7~P@&mX8zZfL3?R5*$l4@H`WP#2-$u$O7Esjsnq=|js43k<?#Mr$c zvc@X-u<(gO5$r)Qd2gX81(}~OAQG!UVx`r$yG?w_cccwVzEd{iuXH5az-QC=5g7Pc z2mt$IpTIeckO(C-!xspyGh!Krq@(>=KM99{7=kbRjy2Mpb;gMJPUx0?c$mN2CWr#HOH{ z1@)abv6B}rH@-?{^{@o3mX&LE3U*>W# zwxV}eBK(ula<5e&Mn>&pr2l1oZxveM6S@8WDW><~fQgvg`2mIA-Y^b)I3KEH;%6bA z+hATSqmaNUGYBn1C5G1!n`ses6MfXiMP}lbf5ZgpJnN zqgx7(O>TY8N;uJ0*fCiyc5IS`6TW4QeHWti(P<>mUu-RCoRM-2&mW#fGoQO!GndQ3 z|5*uq&WW~VljVMiZ^`Ge?`@%_$8$(?*7QlhA1RVfyr$%rgc^H=&qV|TDPi^MxbdYJ zuqi{VKww=aE~dq90WFnJ%SqS7lKsl_Xz9Zfb{Jcu-?gx#E_rt1p|ZkYcG*gK0D@Lb zeAbu~cNA8?EuBbgzoQIsRUgLuFD)n( zXKfbC`o*Pi3`+W-ZdG4Psg%)>)fE6D%W-+a zWvM;qw<9FU%r^MY-b${8qc{zUSln=j$GycrRo`d)PiE6c?X&aZKjuYpR{_nWOxhA` z5=Il-3dOdK?Y-7i9RB#5kzCnvtXFK=*t2hoH5R}A@HC4ek>7{s_wfd3&Ry78Z?!fo zsKV%M`9oV~5)LchYO7pU*)eTq`mvdT@3iI2fZu%$e({NA2s>Qd-zHW!iD}sT{BV7h zIc03s`x#l;Z@!PY29-819A_m~-rLn7&h0s6CXNvcEj1f!#s(&A3TWCm3$c-w+p}kw zQ^!<_1_VE$o52**KjDj3M>ah5PHWc9v#L78>$h#T7T^rrE;QvnbBa}Ibzm>mKJnYz z+E0ml%)LLyN`A7a!S+=sS52}==odAaVoZ~HUBdTdEK0QWi(lT>kAq;=kHwP+>Y%A> zs;oPR%;&61bbd!t$_#Vnm`d}yaiYPJTY$_NXJH9cK|UN7jdIf&#|nzJV;_=OVwi{aonOOveNWWk#e?1$y5uxECL{JvfwJEw87i*E3w|$zx&X#t=1uH^3fUA(fbHFop_?}E%awu+rL>)@4ok8Im}`O3^x5h*TVXi zWmZTIY=~r!rpW&D)-iDgc1<67fxfCS?MG0&;4gPaFyACl)Swj(` zL}$UZuLC1SHx=%CpbJhKX5`kYedZaoRymPu@Vo!24R#$&`$U_&V1CK7!6vFAoV-=@ zLXTndfJhhKvBx0XZFTYJSY14@)kU&0R9&WAD3x!g!_2Yz4O^+n9;=7Oa@xOzw9DAz z$+p@AC9Sl!=y(pZ;`Z+f3l6%68q|Sx{Ngh2_PBy<=7BQxkq#To`yd7%2;8SZ2(jKb zN1k2$PxUzP%vrvi`LhmAY|Z&WV&bz)YeY%`o=;6&kZpw~`m@t#9-N5f?QHRe*qbe$ z6MHEzCJ?PLFB%X%CfT&(A~WSdtmm`E@L|QQ6N6> zWzsClw00Gy94%di`SNC3H_ZNiws^(Zn{B=O`KRnZI9lJc@TP2R)}FXce`CQ%rV>6c zwyoXVmUI8UrPHma#3S)NTf29zOcYH=KKwm)#b6s$djIZ{s_Y!=j@?_Vqc~w$hwV>2 z_2PJQyVY`IYU7No0JdR#Nj62fisr@RNL4HfpZa7-PDbiN<_+U4|Ls}Wf^H^Gn4g1h zqF+=}{5o-;IW<9i4vUb9e>W$`iFLH&baEVFfGxj>me#~~aH#*-La_~pus=kgW=B)s zAw&z7(tPkAv4{&i^(U*hT$COG%$ERj0x+E}nBO@t3E15G_h6>j0)_uL*hy#}Cp6p7 zAT-tt>qJm&YG`k>I{y8W{L8YkCYGRpc)j+>Ti8E$U6u8-E7oD5w7|UV?BKmSs(#ho z2%EfgD{WzF!OA%CYlOLoM%)n@_#MVW_`+GB^6m6)|iY!E9EFw?5^^`uwm6) z>^`gWuUPBMs72T=Ah45q3bA4avEq(V{Z?0tl``XK#>(Fy&e1O7a9%w@Jm0d}nwgG8 zee_)W8j7yHKbHKL2iDL;ozvv*o*XNun{-C)Sm7FL%T3F&t#g!!*ISto`#lzx;Sfcg z(`1cK2_Qb35|BKoFcWdi_{SSSOq*3s#5{u~pRN{+=QEb4XIoEcBz(!4W$#5&QeCy-NyHe!MDcSJv*g#Y$Wm(IXN%#Vco6 z1*bCn*dj&~bCdQ&X*^C@hjz8jXHrJ^mzoN|u+yspQ*aDx5xjaVGi#M!3IxAuwi<&bHL(oSn8bnvcu z{^x=D(9JTI@?0GC?SY$#jOVbNN@;Q0Gw1AB)_aE~V*-iOtKIy!KN`5vtq!N7if6t+$!r0>M( z17bVYDYJjPrFo&1xARA0>zH;cA*UW|`Peat-RaWb5D%AF?QoXFKhICDTwxu>DSfHA zSf?XOOzUm=7ZLX(R#&0O?XwDT2&<$MUQ$(;IqmEnJ5Vj{t@!2nn{i^K%Q^}P=@MH@ z4p8Rr&TsD!->d0-I4@`Vw5jH_bFyY(_u_#gk5o(Y_Qu?Qw5=N!yXQlk^WIvRH){nh zc35&G$NKYCE#l9kDdhQPF$vAnpC_StvzQ`I-~0UDLkDSd-x}%Ki3!Oc%)~mwXzX4{ zt691K#;u|Sdz({mqAoKZyG+noK{^E9L19_(T2a58#HTz(6i705QfeOkA*Rvd?tK|D z^k+#25*uHTEl4Ltkf3&3vmUB?`3rEK6bGA0S$uT14Mt3yKZO8AHMxuI>hpL^0PI zotTkmy^bvhICY7+&B7bjT9?8GUc2`Fz(MP%Shlx*r8u`wUai=D$W1qNt0yfda zS)DC7mALS(CrQB1%zUrXyy#qDHUDW{fL%GK(+`plWoEV;A9w9Xe7^qpwi zdJr24@$X*z6In;F38oUW6xy%uvvBLi0nm2@{Oc4uHqzdVLk5LleD}pP#aJH_mGgV8 zQ_Cqh--`8U3q!((SKWVqrYp+K3~sy<98%voc$V19S46~LUU-NL-B3`{;x297Wa%JJhE5fOZHnUz2|Es5?Y3s3cS7t$_R z47UAoR^}=EHZsQQfh#peC2=_hc^%07%u+O&Quv&dQ-_o1q?})$oZOAlr(u3K3Evh- z1+iibS&7qNen{LYlOAKB^Z$<@Nd-@fk-P;J;ZIBx>8~cy7b6-~Y#AGnk^QgzeOF@m zFZoxc2`9**Aed$IAASCUI?D`8lcbtf!V}g+3U1=yELI68bt+|9t(L0~;s@W?=nqMYPtGm> zKl&)GuG7E)AA`gQ`Kuf^^60U(l?K4{z1U4q33V^Hz7PiqD(RoqEzZDJGV$mcbTIIq zlFb-AK02Sqw>wM7Df;02y$f2}o=6m5Xz8=Mk^Sd2405We&J55n=pu!%uLtTB^md=TxmxO>Te1ukUCtRzDVk2LrC6LivVQU&ID zNpgSx8Y}tU=X+0J2g@$8mUdBFh?L-<+)L-e2|@$@SR!`@?mQo-z%#K@H4AyaE1^bq zo=;xeuS&>k+X;_iRC`r(#_cn2GOv<06dw5@@j-L{RBDs-uXmi@Z}sjnFHD&A;C<%x z)TFgm(pn6op|$DFYq5*`Da;nELs*o%_oo6qBT;!DPq<_?U) z&u#2%CinVht=49%YY{w?&?4Z+UgQ`vXIxf!iaBR&TbuQjYph>hPZS-+{;~(&N6Lhw zJ_$P_FByYP9n;30ur9_qi7L8tXi_KSY26iBUDIHRWsqG|(-HP7HjAa1;#;E*oXVI@ z2(Wn(vHOkBJYI+M5qrDD?X?wK;R+#Mlqq+n^@*B-#%zqe6-dlcw{J`_uNbpTJP03T zOO93ZnzS*`;_eSDVpm`T5nR^ph3j#UiiGbcYsty~P6Cl2+jCKZdEJyuu%bL2Y9ts^i7@Rrz{)d){MLk_vr?8FLylg`6(!{AN9uZ?YMKK1__b`uq zL{xR|7WZthdS079%X)^w3{3|_D*65Gav#x$XH2>64%`$a&Y6O%2`{>(=DE@Id^{MwFo-drS6KBC0jH`&f7Pz3)hnOiFiK)0VYWT8BjTk$iD& zC)Q=nTe1Cpt(CrIcYapZg85llS=k-?tV6#Nd#la0v=D_UIChm!d3|~o=67e|oGqBJ z6W6FsZNoAV&ck7XZS4}1n?#`LoujxVP2?q8OOJ{xd&H6+aYfV7V@KCK*n;W2IKF}Q zW$(hlqK|R6)$JRa<|2&Tk5k_l`QEXlEu*Q>k3*elA<@zlvf46I)^>>}N72sN%f`Tj zpi^>4fFZx^9;peRjBv+LV3~Fg9;_!knw(o-U|fkC~VtM)jE&ofEpJQoMFLZfZ)L5vs)I zg(KKHC@KqZc~eu{j1c_B@-8~Vj19VGO2R?$!`tXChcgg(ZZmHf`x2%wjZYz1gVV#C zZvl7zdj!ni)>}H~=ZL?L=n;Qgf8-cUB*G9teiVcALDJ7I@xVx{iJBlDGtH1sHpiqH zg?R)0Nu@uz;vF0nc@#L0wN!{FvG)qGi+!zqm}t|sE;>-WV`RJaJyDLefLG~SpUz(K z6<_kcdlKPYiZd(BDdT!GaGy#A<`iFSqUq1Cai0|qV$Zbtt(CZ_r%fE*P=IBbHT%Rr zaMW?j8K~o3>=9zFFjivyDeG#q6Lcg(I_l+2=Qza4KlCA_SA_B4`2siMWXng zZwd}IKN&iBQ`Rx;?^}0*uCbsK<~`!nhCVB!%S?n4jLAr;vL5d`)X~-r6Ndvv%R9wZ zC~ZA$vL8=ZH*KFQAbw-wh+_JzQ0S%{T(@>%P%VzPX5e1eXUeCJB6dd(TUn}k#QDI$hpJZ=0PG3KYF^#$oC&|P% zT!8dmi&;yntY_2W!JlaMLekiK8{*lMLzRdIq&Hg={&SakX?&G=$%IoBLFpCNq&KaD zV8J(=toE$lwzg2{v4vM>|D@M?FW4N)`YysKawpfQPV*}C(neSbx^3cq%o|Ztdn~Gg zNbZ&9%Fb z$g@k3zm1gx$>rqAicwZGdNSde8T< zwbmLt0~;~V+)PHVvQJDXz|Lk2eM?1Y!JXE)_vgN`WMN6`##_a@id!)8J^*`X9m3g^ z`{YTGv#h;`tg*Q2rkY|TxQ`$+Woe2vVZn{d^H)w^A=dS!cAHn8d+-Nznq_VQj@Ufv z>#Waet-i^+pu4*~^xbMRY1}~^h}=uuT-PV=!M~Fuu^4zz{L{2HcQ9s0NNt+f zX}vzr8i(3?m);B4%1VB2-*>Fz*dL5A(9zJ0-i22z{Ig|NA~ z*-C*riNYRnBL#>Kny^jJ+|~y{Iux>KD1G&ee(?DT>R~f!jQF+a!-)&gizU2M8L1J0 zIT^fqysi~Iozhjab)(pI8*M%Qd8zcMzHy%RsAe}J^PN%}-1eMDF4f^ua;Y9YZ}Z}+ zPzILxt|H%`Zs9tVv296qWA>V(&hUNVn8{XX4GuVE(kbCF1$!{JZ4&LbL9|Yq$w*{& z&HU+y;yTg7#q|>@YpjVWRzgb7^aZ$t zVXALWuX#y=Kd-hUBedrG;t;Ox!O@aaw{(g>;2#5~8WBf~Q&d(MHA?>(QEx$R@p#on}0Rd+6r!8hUMM^VzZB2sM8B}cC^fdmF+V+;p*;zoLtg$yI6r(WHKEA ztjH9f!^SFnL{X-=C^<{4%@pI4=ZNA=oC?g!&LW73Q>Ke@IL*nTG*iSSi_w|OL`8)- zH*@7oEHY5xtOZX^PoeKSa1a17gN`n&6EklKs5+5cgdm__0*H2~Pj#t$Pn9<d+89cUP}Uz4AyZE+Q(UG4GMvfX%=?Zdu|HA2@(M?}TV~ zI_O)iBU$3_xO(a55Pk7i1+-&BXIHb>RRimY%bhaQuqz&w)mnGa&6rcHF@-5OD28+B zja4^QhMvJ;tWGf*#?0zCifLs5SXwULGzyMVlmtpfe}A%wf+H_9V_z`(;5@YH;&$}W zUW~O*<2tN&M92C9TzE$}_u&6)5)k_t&i~@;Bh6G=q!u88;&S3^FIX34?fc1$=I@18 zT5Xf5?ilh-d@*m*&j#6Msi`Vc>9)~E^GHYqNW0OI?WJcJA11_)=$5+i(HV^72;0Ox6?X^>jj^yw8p$G z&gr)=tb4GdE`&Vn=Z2fKwma7h$*CwRTtVRS7 z5mjuH65p*kBCaCK^30g_Ua_Z!lI3zZil+lBKN*9|=kBSY)xt62H)HUFc(#UqcyA2m z7DV@=PW&}*_hA`+7M5&HVwnLUT*2(Kxu(VC9)SEV@Qo;}y_zF^=PhXbQwJ%t>?3HE9@@K+N zqW@Fqih$U?zs@=(w}-|_7QT!k|Klt)DoacCmE=S4z}d(E=C~O`EC_7UEJ*O>yqox~ zoSRqvxpLQyQ%O{>A&Ye{{mEY$D#zguDZf*&Z^mjL^TDoo(*zej1}{wGuLE%8|CwlL zQT$hgDol*PQhQe%(sjj6!KPvy-ICK`NFkSUvy?J_SkC80;#kDJv~*EK@RW zi~$v<@zG~n$^VG*mR1!v))u!8t-BsJ)2@=+Q^5e}YrHSvY`MJ?i~?Jh;qPatkVaWe zO>tvovt~Uip2QW8@g^$a^U%#RxUhYvtl6btI zd3=^Hd;j)@d4-jgl_^&0nC7$Zx0WN!d0rEO>4hHiiW94EYz@gTeTdV?i(*V`Au2z)A;)t8oW=-f4t15rKqaBrlGtsICMu4&y%=4 z6YwUZnI^fV*;Z}V2e=IwTOXQmc!M?$(TwTyP30nV1gCcQ(jolO)_7W0s4v>^VjON!YQu_I4t6Bql`q(+c>yNtC7r2q&tB#Y6qUdh8RSyD-~d)L z`d+vNYX?)Tqz`Zz=U?eoO>6d#5CuITrgSc^!U7;7=?AJXnHr5@h2x7Vb%T^0XdQM1;j)+X23@gcg|G;l)ae}Mo(#ERs5sjxR#%AZ@5hC7x- zyxWRo*M04zR}QNy)wBrta`3q;l@bPGH@=0~p}Ozu_l3l)DRj*q-Da~dBjq~bPsVAB zf~g@|C3Vy>7{P6A#{wv$pAk znA5j=i=0n%#w^Fe%jY@^MO9xYxVrwTN?hNXd}m5vURTPiSm=^K*hUtA;1u40VD;f$ z3CXjqB6BjxT8@oKd+|Dz9zplm?wgs9ZS|d)?|0HqFKq1m3nZ*yU+sM&zHeU@iJUx3 zaJ7~Et~m;wT_!vJZM5`%-txd{zz%Hf?GMwogl#HE-+9f(>K#r$-g(IC4kdNmi+CDB zcA?v0Dh{-iE~mQ{8*vCMWolyfp_ayAP9-+YVZYsh6(!RUVieVVuQe}2sADvaY-4BK zA>8}2r3h!Sa6w}-T?`XItB+9EI^Ny7E#Eg$&n3xXg;Z zi(hO1;dU)G=OBRXYo2`P6;I(^4CAqsWZijAb4SLX_iapHo%m+c9Ff;UOToFgs0({r zduRt-&`Qn$h;?E53aj-k>|Dr{qt5zdBynEc*!+8ul_{oY;`LjzmRf{KTwCB5IsG_J z{yG#nQyjw}_2|Ya^d>nv&9kuM8C->$3C+hsRx*;wxCnAHF1N~QS!(TsGrT@CJr6aT z7mgSIjb*QGSZ)5>hAHAs-)5Y_#|FlJWZsWVyyC7O_k%v@!>v{QViQnq_GO|7=)f^5 zBIIME;M%2a*fIVK6nPv)5TpMEioA*|mx@3ppGJ@X0c>eL&qX`YE~+7F7e3PfJJXgGky z%UiqiX?qDa!8R9I2eDfpA=hN_ZxDjG{t~)WKE7Wx6kwOPOGJ(GJAag+<&JX zOG{^{JXH5(+&W|>SQkFDTLkEWA-t6&#+r$NbF|z}WXbi{rMP2Q?mUuvYTv|#KfQS4 z$TS~z>YkwWRocRR%1YdZ1vCuQQUWu(>-3RdkHQc}UB)wQ`eMMFp&R{ymKYE>#V-V-EfT! zUJru`tw-!#9W8V4>3I5{U0To2#?XP825m!0I+eX62@5iXPn@tSKco?&Qk>OUFw06P zyeIM9?Z35C(r{MFVZ8XW8(5{`q&OI6suT&ZLk7kI+5H2(F7H!BGX51C-J&mwlSX>5 zd8XUPa~s{D%ZGQ(E6Mtv+^u`%V&8$vr70`a?cJ4fmvYAm>t1Yfd&6p8wOrI3`R`xh z<%(GM>JqJZ`yt(tx%o*rhbMxxcBS5lbxc;K4LMa7sA*PG7j*!|g279^ni00NPiZRpcX30XB#(DVr8BG&D zy`Y5MEAlB8SFm(}_Y+i?6*Uw$7T1EJ>V^=~hw|ko-Y>s&wsEz} zHR5$XHYdnWT3nLZJ1WjfjWrwOmxen}f3H57!#=Uf92GY`^~JcP)R*EePklLV zQtB&l<7dAf7eD)rI4dhwA?EszC-`N?g}Oe_yAstK{Cm89Q?d8=f%rq^CZX;8hT}So zH#IK44Gl|5*1so>^UGiMI=^oOp?0;6NQ(=Y3rB(U7vsjG8S!X_HJ?Z)J`?_v zy8M++`7KnwO`vEo3cZLzFU46k46k2~eD7#g0DQcM__#yNj+=D%h}m(MZzn!(BR+0D zEj7-+#Y&A!Z##W{+r}y&In2R7u!w!E$i0r z34KvgV;C$CX67h#)QiNv+w9cMDvLm=9aR3XE`K3plRm@c+x)oh7_o5Vu-mZ$xFx-p z_^BF$MppWO-fbjbTS-2*klwY8Op9A>J~IkB_96uJCCJ>%p!*eS%7VyDg~rIkH{n07 z@ptL`!S$MY-@I#Jtu~BnHQr5^`X$D4jTdy=df_)$IEtZv&&D^=b5fV<(D|TeJGFNk zwRbDEcMIu9TZ|-S6I9?uwDBc0{AJ*L1uF15nGNG&jj#POzr=Kv{Ok00neN(w^n~bH zJredqm*1?*4?<6%WmI%>NF%8p!WX#QFEL%9@lm{r@;B*xS_`2M>e)ed;cl`E+o|2# zsNGx1E^HyY&}OB@HHa!`q8}`n4i+SV1($;blfZ)Uun6(62-+H`exZ80uk=g&cgnw# zA9la2Hd9AA9i!|B^(U1}y6Tga<96-W<*q~D(q~xh+T#-!4b`x@(!3aHz)AEOiGKVs zi~?=XqU%Y6c~=xY$pk9WZ^E-W$xmpEVy7R5X{R>%%#*`V?=(d>*LQfDs&Bl*pJCRw z--qq-!>Ca8Bg^y2>r{Pfsgd{$BG0SMWzprC$}#<`ulLiVkvl?ueFA&9X#~#e4}*Ti zFtXp&Kl^X;%ZmKEf6&k2+(_;DWS zEEt9M%=Sx)Z<2ov1Kv!C{W1D|kN$m@^ZR=D?CkMseZEkpW+-WdFws#?a8K@tK{^Kwe{0>OJgU7bll(z!^2##M0 z+3&zb^%M3-v43f?g#-Et)E&Jx z_XPsNCkp;$qqu_9*dk66zo>kCzMqO2?eecK&+}2YpGcHeN=z@$ex1m@Tuwc+QI7C* zYdqg{nlx4aCOZ^hlHaEV3=qd`MYYufK^YOUG z1Jffv%*VN!j|_Kmm~cjcU*Z`GU;HrPCTTbfS@Og5rD^)49Rz=qG#owChx?i4$9{0t zTJa*WP;h%z4^cnkZP0L+DYUkn<&Gi(GGga>_|&c8&-K7B(QvlhYq$arT%E+58XM5x zxw>2);7E=p75Zg~-EKP&=D&x>N4if>KO?5ws%8n8{RXk&4qt}WXXeM@GkN%H_IsxqAmL7qH8v$J+MHU!>^z`hexu+QkrqTf_E@?cqsX zK5M}8&35^@v2(e&oX1nY_*bj?Uv|ciZBgP%?)f9QCNA|!tT2tU-u*X17iWbH5_+mRV-=0r4( zhfAApo67u>!WZ0h4yd;jbb#K*o9zx}*?QdyEUy8N?2mGV*Qe)o((VE8Jv5)+L2aSeF$tW(A8H)p>^)%fPdn*SLk8@1bdR;B9Abn`DY*f+rbSet&AVaQbGad;fva{N0)cSZ={}YkH+8C!1Yop`#p2GN!kyR z{AND+YZYC0cjPdpo)%^;q#d7! zd9&_*+qS32zNG8f6jJq6yX^#YvP}9n>9OhmTfZSAG>^Dgx8r29YR8#)rjN8YXh*t+ zOF&+<^)r%t|L5?h#g9LR@woi!*qOokZSM4PmhtV;_}01c!9IlRk(y5|aP-KxP>t#K zeBx@9C;F0F{Swo0`PXS50-4mp*|FwA*;0}pf{$P4myoNqqtEttsBve0T)PSR#Ny8T zVWOl2^lW>4OVjl#Y=e&P0XYq+p^UD&w2-e$!Dmw(OuX56Lf`RxcX@$XUW{+SuE+;1m$DEzM~^a_83-B5l?xM!jYFhBO+qwoyG53cX9hWl6R z>uw)jeS0+Azgpj>j=}3I13RQ#Xt)NC9!H-K&yU+A&`X<4F~w#5NCGcPi(MQplNU(| z9B5o2yZz-0@aH~7C)q3d@VHc@;|FW?_(XP);8$z-FuyKLKFwQf0R;sl*HrGLF6Z@+ z96MZyVq|^OwW5wBa-=gNX&OJjQttkyjU6!3ICo46n>viR%7c; z^nSpSCOk~jyfd8TzSLOKL&CTJ%L-qf2j5V7XwR!AM58w?wn^ik^i_rbR>dZp-l6gD zAw5qLSC4RLXMT*tjQ^P^*;xD`y`^?_cd2>@il;H$o+03v@B1~J-@~WD`Tidckt8#S zM%nVbOVO7Bdg&wO**zYF)F{C92Q>U~3GKi~^Mmv>P}Vp<)+~^|m3%S`#+S6)FEMou z1K%Rm3W*^#){T93EbH50jc=9*pFIyN1ri$8^mxPN;ve?Q601DrT=SZ_vU(a{(Z5`- zL6@r;xLmHg9Jl+pF1OuNE(#xA(^qsH#aA%*lT1Kt=4zCe`u>PtVhS7A;V%lW<{Bbi9#fJ-G=y?^r&Cfw^mha>xCl^sx*ni{8$yJptKe% z<5rZD`mgcqck>PO5AM&3u`c>`{0=dqIS#>gP>({XG8SM@1|=kxL=khxup-w z$r35o^X>6ywTAnd0#k5<$cd8F=N#r~tHR@vzsD~zUGM3)p~nk_`3(oN8ZESJlmRQr z#im|`Kh}ePd$f4Z3ye(0)6&@V>3EM08*?~Fl5P7D?N6wB?oiowKiKwAu6~h040rgM z|C63n%q3 zvd52%?3(h=D{RXv4C+TJ-|&=QmR#d$$Kd*Hev?~d zYwes^lZK{nRZf%s5!G}2X;n|Q#|{oHkJ^7(8fH<{1a{;+X^#ni(z6Qx6xkYwU)3)C zC%Dx^zzx(dG+rKqu<+|r*LvzHm2#31d$atWW3Tg(K2ka3JAPT>Mfq3L2mKzp{YoDn zbg`Bi4|SB7^6;1NAJ+IsdHQjCG<^(lM@fCm!PaYyT|P^^*&6Th@A~EQlk%^oJ3_t! zwBlmcDYViOA#UV)N|$mV`S+Z{_j?bWL-RrV_2);C1Nh;j4}^cyUWMN~?}*};m~!!6 zN464BKAJuf-oqqR`h}oDB`Q9jgDZF2BrO9`@;0DQ~H<1zOG-KIwVCgbeeG0beQM=i2bsYW$lte4z(F&kGA= zxiq^R$p_JOT$fwpE*D)s*0}^CEjHgaMp6=(?!fo`5|h^t%$N1gi_Q16vt7f_ch^tj zzJ$-P;mO`fdNq8H8ys;B)0zs%U6vWFbc zm4!}KEOM=KD>m5~(qAV0@jp=bz3t{WIrE9zy;{S6)1!9-&ASvmw@1?B$&s5w&_=E& z{@)Z`T^>6>_;?~-3e#$0?{xIFQqudnC*$*kul<<9*XrhH#Q3Xp`!$?yzTF=8 zzC3F8VGT!P34LTg!>{1@4%uabJFejdo}aQis7@9#9SuM86I#PNe$ChIV*Hyl+$ss} z(19Z{1eq19Ca9@A;ox$|b-AVPa^Z3|-xe+CKhx#^55FuiP`eo}Fig1B8qPcaF81_a z`!M154-@XBhMVDTKl-o9Q*YAGReOhmYZwBK^FT`0<>>&n>WR2hWmBRlrp6SE( z(4H5W+d&pNCUawpRYJmX`NO~R%jZv9zWcva`9l(mQ@_iesy%Vw`}p+Oa<<1T#|?d| zyw`43dHSh)m~e-O31^%bUcE`fgj+pKxb|Vf?H?xG$zj4xdUts34Ga@*(=g%oXgKdU z!}FtyAve$@xU>GM{u9rKh%8v8K!Q*O_X4 zfa*DUQqk+Rli_hK)vtFel;_#aZ_+w>1E?`BDaT%=Px(4N_n9hpuj zxt_q^R6P%R?9mYQgzeUnND}Ls{YF4BY1T$9`E8-O)rJN!K8DTiM0P{Rc3Vol-OtvqZX;FV z-{R@lq2*u4TjC?+AJYX#K9hvPzjvgp#%{+@`02h6>?gq??`Q`B&f#Ii9_LP4svf$k zh(64(A>`9uG4z;y+kW{+DZF9&6=8pr{kl`KnuN?}({)^zzsEyYRC)LUca|K+Gh)>a zah4C+W*+An&QNsySx=x?PomgWF-9o7k}@0%neBSyfqeydM)KP*R^k2r2+2m9k3;nr z@6QxD(fxSVx1@6w{`m^M!Vi5jXDfwcIyPxIzHf*7b0|9I#~r7ANUKG96gpyO%Qzsl zbIx$^9mucwG0II+~PsqHU+!FH?ASyYZm^ zLvr3aKX$dAzi!a>m*>0w%T>8;o^qxt5Xlz}-~S2in!}f0L>RWwr#bw${nx7$U0?7i z!dMSo<5js-HyW_`1PZ0oV$Ch~51ICOzIw94=Z(8=k1~D)l^)y2S#WKDHulnfV5EK8 z{VWM&{n|f8)e|<)A7p${J?q*;Lsh`eJ5Gblkn2XIUx7r0|Hp2=IGgNoUIS)wqBHI% zO;zw`x#1ySZ2~)pNh41BWWW=puAt6l{`;q?a$j}Jg-0&gCb%|;je&nS&oe+^AL8&tN(i|eE4?d>M(0n^>EMA7||LFndFsw&XSj_gXCY*Kl)1A%;n z@BK4ADcy&OyST1wYZQ5(z}Iuw{(`?$)$I>Lh2aKsgA$kZ&CRF z?X*vdpWA^efwa^+6-;2a$M*Z;^^32Dia$=$a6JE&?S;Ma#&MH|3FjYXy@6rEtsW*^ z!w_%@V0W~A3FKc_EyR8YUH+S@Td3dZ9v45llkW`+IJbqVd+VrN(k9iP6LdLTJ(oxK zlMGbfd4M~Ha{N}V>zr~8RF3GO-`h3bCHi;JPB(_YpPJ4sgE~mTz#UVN$f4!0hwB zSL^!XH>>{myRJ{lGwh`^Ua21j;tTn4t&6~yHiaiq<3YbJ#=VM}xN=RZRGNnKYq)9+ z7uHYZu6~*m>+UssJSRG+zC9X`c5?>o2kO`Hi@{qBuc*X2dEDw-S?=if_$}%eZ7!w1 zPx+H{{_mpD+wKcIFzUiqC>-vaKTeP zzdpvDA5CwmpC;vEKC1B)YdmiLL;R#&C%8QtuE?hVhq`A5_u&2ap!dk=`ttBi_~Y+T z{Qj%Q9~*prW^aVCr)NX0Cnlr5@u)QZE>+)`b$cM6*f$u5n=#BRd|{LDQh5z1Zd!sD z(<=WG$=SO6o-eBMEC++=W#E(+6~U?i0feMPb)}!rFLm1cm%lI|*Ol z9@Wl=BsPgpwiCu79tO%vhu@`>(lT?ole*kbJ>@DjFlyy{Ddkw60Jvy!Px<3<=>osQ zf#dO^D z4fiQJu6N)I0GJlLBpmM^4cFm?liHOUo2}_(Is!WtUS2ozwr`z=AE-a`P|vTILf-WY z6rR)d4sM^!her)??=BB4WG4vkq%SG@Hfg*O{Tnbt-o7Ky8vLX3-Mai^dSC)w!@R!` zM~$)9c)0hva(#iXDth~36v4x<4{k47?MIb<>UwQQ zxc?cxdzkP8(VLBW?_37IQscSCrwAT!ya4$l&F2RgF;eAz8^V|Lh-$|Voc2e(SM7-b z?E66UQvP%V*H3EvIxIV=|58Q4_-`tDq>;fR;i3F^ozL?lWPhfg+)znyU9hRV)|gXO zUb;3nRBIF!sh1f9%bP;Ma=b}ZzSF?StzKWgup*PD2RZ(L`SLvM*JD%Yi=hpascypc z_O-gk+@|8vwT#rMW=?%=EudwKqmd$uX&_ZOgCIsBn)nT|v zEJ{O-)lKVUPZgEc*RQQEH)^U&Lcx-v(wgGxTKoXa6~(1ac0F=hn;5FBytx`bmQ{pM zpuD(IHY60}pOxfj6h*}~O(aXiR0gPTD6iu*^r9T%8d)b{DJw4tRmys5(9EI=bc0h) z0Z2+T^&}t!ErHAGi$V>Q;u57b^-v4-x}~C;dXNK9)a(G3l$NDAO_RM-)Krhw;nfU^ zjN%f!?AIw*RwpYUMi6u;=mAG%%$qX2N2)%#KDZj7 z@$2R(Nd4Xj0z+A7R}~r<1XeuT9cTB2)JgiOwz#IIzEqY%y_KXmMJ2_JMtGac>RX&9 zY4%a+XuNPWE-HcLtqo{xd09~q8e+6o;FT9L#rVRw6^21lNu6EP0zoY=Ds3z^ni`Ai zf>0;2h#DCDj3Sl#N1~42%v@9_wbf=wsIIZRLNncfY_e!pgz8F(ha@0HH;1Yl*9MJ} zoZ{91%vX66DR~mtE5#R961J$Q4lncId@8B?h8gsA6=bZcS4dz%OR%)Dx&fm_QE{-ey4uy(8jU0Y z^i@>5p^cL4^18~VDx)OL#*jy2h^z9*LarY*WlsHE(#3k0Op=9=e6+=v;i)mOOS%s^ zH(U>3ml}(UY81s~EpuziX)L7`PHva7u|v|Mx{jF=*%^?g>QdZmZfa;mbfG75t4lGml&&?xERTdyuZb!uZze}i zX^#QZgz=ZOFGOBPeVuKk2#JCvzoDX@yiHYCb-nVlB+{z-riPkOWl>#yQ*}jksl>q) zDvwYjk?$fSNiVM}lb(ZJ(*P#G)vgdm1T<+NonVY%Z6h8FjZ&q9%wY zs05%ws8d^uDl`j&oU3z4b1_o@#{n#fHdSC{Pw6Ges5mKkQ1<{%H7 zVf|Aw$F1PXD<@%ruU1wr&6DG`k?=Lofzc_cu7TN+V=j6VU22rTsDY~kjL3=rHd}U! zb&o_ymiG0--6u?;r0rrEZ>X<<&q7KCvjK;_j9dySM?s_7_GMhS*}Q7Q!$lUomL)25R+(+erQam88>-=;s1yh{ zG@&wstt4zHoMo96W{tzTSj&)I29}>@_Og_$n%Y&?QjD2~%9DczF{{EJ9AxGEemAW| zE)4F%G<#CYX|q&Q5ay_cF;kLJ(uk=|X|ZErT)veIb=)R z23u1SE?p4F(ohX1uC{Q<>J%on%wZNmqX~veFy(jLU~hxN$b$`FX+iZY*|Mf^St?mv zesc%|JL{qx&urA3XoS?YDCKj+sU<_IAZb_$hA5*&+XhXqoQ)~RG)zLm&7B68TIy<> z)|--AO`gna?dE~SpoZDVq)@8}`YCx?5tRou0E5Ay{^pBE9?&5Gt$}meH z^GyCp5GGeS7NsRLODzjw)`}mgClDbB>Y zIbn**Z7U8Ik!z-`Bx6+V;V0;boEws^7*aNk^yaC3tAsoWe@}jCzGK3UMa1YH@O~r`gNCJ!{xwDHFEKHkQG-u(01#{IbBV)n5g^P1i z<&0x)fzu$}l9CMeh!)6+bJ*z1>V#=Rb+b{DS_9_^F|G1k9p9lhjbh3z1CG`8rA;+Z zW5hzsT4sl;Ysxf2c(8I5mz>f{ZzI-fPqX~6@fyYhvCL}fqoOLjM$={pcQ|PTI@>do zrCb{nT!J4`6Et)aB-diauF;E)ifDP zXe0>GXrN75NvLM6qw|p+OY9#Ay8)!O602UoOdcT%Ign)6wcF5xO&^dvmh#s zBrOJOxups-BapE`s5fF`_#sF^dhk2Kxnrd;)D$B^y0sZrLyxXjn@HE#6)dk+gBZdE zH0x==x`iQih#JOn1!7?VwKhua)|kTF5OOE9$uZ!!HKIpdLKPOW3Uh)fj#l3S|8-HQ zxJ(K*t6~V#(qtu{yhe~Wj-p(xnOYL3=N_*rqQrmk9ltJ>{Q_?z*r|Xo#FIe1xbyi*_f(6RB zvCYs@XZtN0PyrQ(5DnDh0QHjgmh?==RytR(fYEB|BQ)8eC~cz^l1MMb-5sMHIp@isqL$1?D;nszI#Rl4&rSu^&5fn5C-Pz8s@f^ml_xw$-C8S zjo|>Z*Datm2``uIRpbVZ$jF0cV;!|Tx2d?c!Dv{Jhvi?2+<4b58yptoS2t3qhv~0o zRJ01*?C>QBO9?NqzTTi^HajFuP^AV3sKc1#@GDr?!raZ#bMFc}$BA8iri=YikR8=| z8z1Pt1#=sbTMm{IAUCiS2SM3V(pU_F>DN2SBfCp~f z@41zR70LGmP2hPhLcNH*Fj3l@t=qIue~&W6_&u{FqAn)!h$h+no3|=29vp!77FTDY z!wS}VYWEpSB1`cOdAlT+3hC0+`<(uo&hr_$UQE%1gu9fBL+Cll96<+pF#*aZMkhAw zdLOsz&+~$`Yc{elM5Cuq!~9);3&Z-jiyutA*C|T%3Hqn2^tUX>57P!Nmo&~V$(*ad zp{bnwf}OR5lXvN?5ymOs;x2yrjRWXyawPgijDD3}Dvy(lh|n*JFf#mxgex!3zH76^da|7~IyUqn5Cu6_o2IQwp zbuIuoIdiWYke^oQTxzvWekBZ$pI&qTIXPyZ8zVnmu5*Erlbgc;BSb4g92T)SoNbFk z9w%7f1Ad&U7TKJH*p0g*Xbm4xzpMJ@9NRbs*bJU&^DDqf zHitmZ$;%z6NVAy72C&mMfO%inNj8MQ<>d_XeyWyX(lkzUU&k0hI6~)kafkoH1OipG zK2OwqTB^TcG&xyiXXPpJ2!Zn$YRY%$%Jvb(5c|d8~A~39xC9ZtAZ~_RPcLkBY0rP+=&NtRvTn_ zH3nH@^uW%R1zFy48(H2F8d*FRZ?}!i5>_`9m#b#E1B(owsSQLz8R)kjys7Pi-c$$FnGV6f$d46oqIs)(Or?I^`VHOmgNZq{tL#U9v;?$OCdoh%k}mhmVQ zd{tBMZM$y*oE)i%f`vM~fget{DJ|gS0yo^<`r-4o+ZLro1>P3PDp)1BZBd#j;keCh zPD3Nx9$+@GzyKS|3=0ghA~{sx?W1QkXAU|X;^Z+qtB{j_)LAqnJg9l`w9T^sClA?K zg^?Xz=%t;Id5NbyFZGn?C7%g9SJx(V=XtTFMjEaL+)ND&qfRnDeKhU&Zr1ja+riegZ zWW|Nvim8vh4fGj>UgXiba=GT;tqyCw+~22vddCJ?^o(xYi*_S%p+xwHOa00&RTNn& zqNf@9Pj;yQCr4}TN6($q-1BO;>nG+lE41q;CYrTa^|x0SqKdDV76<{;P-C+qz)9{B z)cre6F_X2yf##%(Qigt8LoubOZh;O=Irb((U?PbuWFna&2nSQb)gsGV9m$KgzGyNu zM)!TiR>dHi)mrg8^sj-RwMdAe}g5Q{JYM=DwMB_A5M3ifk^BT zWInCEvKO7{Zn#t%#$Nr?D>g`k=v#U+I6;4dMlY6l{nL3iNCcLf^iT5!21(OD726;I zo&=4sr@Rq$H)?nL0Xv=+U};)qhdm=oaSP-fp?E;#myw zB)62>U1+zP@kfbVaeZaFKGH8vH|jhr9kuA>HFlM`T-6#U%S-cM$iHkO&*x;1omI%m z>uu!uT%XgJ2tWNgjUdHF6yW5wHln;pL=hpF-)RK=jy@OyPI74|l~;zMm?dlZ$LzMVw^9sTqs9 z_=#(X(tDBU3mE;GHaqh;$%qJjL6=RVPW(la$k3!{oPN$mwuE~j-d;9c^1e={+bvqc zNp1s#k&`z&P(zX6GgdMMOgknc4{h|8>(`_&w`p3zG|jSWTM5(oY}Z-Jity832auC5h5_n_h%ZL#GZt}@aViDpr#*HJ zi#X}7Vc?PaLc3rAC%GoHl#^VIQhR>lwg8Zm?n)!=17Ejtv96Tt1E=RXgfRXuxxjSN z{z}j(E)H4ZOZ{f+pOD24AGZTpjC_{^#mOJqS-G6#_Mo8t(f*3WZA-yc4Wy*NE};{V z1?|pt7mVyPF33>W?{Ptd4Q3#x$#yStIn|2;k;PD^abpDX!@AHUZPC#4ob15V!WW0RiGL~eDmeyx*2-@yr2n3JdJtkduw@tBZtVOJy_5thoQD;=f3 zPd6IlV>MAEb38=9VJHa#miIbCPP7!5`<$l>SDY4%`9i=;4OIrYCh zvO&ttz5KS87Yx0xufIrBa+S@jCCoRjM#6c;=n0L4kx>PlKI&9(U_Ec8<1rmmAx?64 zqJjhK+cg3E^*15pwA1zo$2nei0pp@#oOb#km-`^YZe}hcKkTZI(-ZA}$z?9=wfT>$ zD8oNFy1gs(H$;AiPJYSBdS#?4^|t;7)L(VdAvEA+1E4HTj6+m}`AhdyM_k};{>_+Bm9+&CwSmS0|3!ZibEeLbwv-(HVnA-Jot<@ju@2~=#dA-et zm7JWXvj~S>yH4DuaqZCGBaBh;z6hxM^sisj-(a5?(Q@6;NA-6!)9Qs8VRUrg5>c5K zia0z}ZBd5_M)WmJ5)`8S7B8m1>K|jZAc6r#Bm>6iUoW-AHG%<`>7P;uMdVd*aFX@* zuZ~c&X(}m(JJU7y>zYgPoPf$r*OmVovVY zS;{%!r&n#jJWjqH2I%dZ3-zyz7R=&gk&SB!qd#P41vvTdc2>l~>0MC^ke!r z3%fH~jPn+r7a@PgHN-#c3Kny6<0#dP=#G)lzsBirG>Mbz?W~BA(OZgCf{QJ;i{)~1 zwayYoaAOxglsj-m5oUMTn?Be8HJ1d`) zZqf>E(zsHT^;WfCXRzOgPU7U*wzbaVH!6lb@B!$ zYlTj-OMvJvCvUc)7ITt=f>E{x{YJOur2dBO;ba0+V&rlwxCy9krT(?lh6-@}uPJX1bqBE6oJz^JJ#K|6=MNH+i8(Ab%8CjQ&tbmh@fSAf@H?l~kGBSn+Q#t7_ z7|GP9bnQR1sR(eA3r1n8q5bxt?Y}SPNCz(%x;^gHH z6es7~S-G5iO=l@O_~{Q0ASao}3Xq?e&1ftqnd1u3YuqB4UcgMh)^7X~PBKpkS3wjG z7chsJfpA$k$qa-~!AWKypg7441QaKkfq>%VWSbuaoMa9Fij&L%;Nm1R15jR0)Oi$< zW*y9mE?YSlE%C?@?Xmr*&f`W<9*3EjzGyT2ZjJVbHu?Z3kJ(wd?{U)ZkAP1nol|zX zoa8QoUa)N6>J;SU{dSfud3iQZ1GPHY>|}BBb~`JVCGqce7W;}eYco6zBqn%UNb?77 z?Vq@*MxLG2loHrTo#r-D9;dmnayWVi!wMnvE+WX64tGwZgWri#hqGot4YU zqdJQ;d2ts%>Gw*&Gt1@Vjh5<71;|f+oeMxtwuAxl(*_5SlV1)4v}HvnxEVz@&5Jnc zE*R+qaKSvg;QwLo&Ew>#s{a3;C1F68uTc+PnIsBmWYIu? z1PDx2_C3L3#07}TCZfg-0}2K~3Ec%MC0r1spzIuQ~!}uEDST(r743nn9d7h$++>esH z=vTk>D*+O*grhtA^R&&QHM{)S1OBMbcprt=dn!yfw+!=@Yfq9Thg>ZjbCURrCX?%c zziAQcKqAWx+`0V-52{{nyNY(fVpr;yDb=)|MJMA&HTrLD<|V)zEQv#jM?EDgWF6I} zkL{Hmtf$ACr(WP`M)d%{q*O;`Mt>9GTc+0=_c{7*>QdFd)vP80t%OPvJBnrqRqSn! z5+D`G7nGOiUc$=Z1>dJz%O{2d|B_lUU}D9XaeGfF#_Tq86rI$D>7w7o4lEh)%2ixc zS=PX7lyV0pq%r!CgD8f1;-0_KCzrawA6mpJuuC1~?$ajHYUaKQB%)IsEa)dKLIa4Q ze8L>|{$@QTW;|qR)-yB;Mda%U{GesfyUohZ;zzobFG_*0DkaNucK>Iz#aCGOd+GDf zJ!R1qtfMZ7B7^^|YQJn&36Rc~EWtxGt~56_!LaL5|X0$Ln^r%1LWo-q|&LRM+s)Cw0m5 zAK@6Bsfrhy&*Uo#XBkxmlAj!1LPv8{d&p{TkKEx0-n=^01mJB-xru@FW&M+davlL* zXjBG#&8X;XLlQr+)KefmAF|vVK=Q~FZ8VWcMebDq@$VG9Z-ZY=Y>{Ee78z!bJFYYG%YvCYT4(uz1Qwz`5_RHEozL_#_XX}YUwy!j zD3uQ_82@rgjGNdORwP>CWD<($&s@*b2+L;B=(#+aa$SF<^%EV5ie@SuTo6^w&h=DD zT)jRca#dN=rLeAU<-h}c*{CXTsZ#F1gVdo4BGPxfBJk$} z6p?=86@mX4posK_R|Jk*+m-He3`c^-Y-n9bf&Vb74x|;iue6Cogpxb3vHJ$@Z!q^Y zAP#f)4Re2l)l>scDiq&nBKbUO?_XvQd0>?XjZe*__Fc<10ls2X4M+iU>F9+Ig0Mltys-h_<&JW;KN2`z{iZL0v8&U z{aWGUo>F9+d5Z4zDnP=PT>mdt?N#l&`wX~|-8QavE8NRdz+;puA7Xxcz*7zR5g7cY zeS1CuI8?vfl&AWRZmz1rhW3r;1mNhRUbhP4i{x|_E-aD={CGmH+wRow1b7o+*(qWh z?M=7!C;?uhl$;OdoJp5xNsH9}+U7X5ILSK$`i4jMcy?B89*vcy0we`lpFD{1u=l;5 zHkqc2AtnDnOBagjKV;*ZP|R+g0#aYeCDv?>55}h=aTr;G(m*7dV?|&Kf`*lvJY;V-*-Rz;JWnEMQV7QeQ@jfeSc*i+(_M5cCzGJ=>XM{lOFIOrOGE= zqI-|=hQOa2RRumaz!%bQy&`ZWJ!!k3NUPhGNfo&D07ax7ydsbnl$V!rqo(jZ(m+x+*8GdwE;_qaK(ORYQJXpnJlV75b15Kx47K#IlJ# zw9L}i0DVKZGOoadM%BV#3-%k=q88~^tbiAM!tIi4JmAGjxy~Zp;uV3n8{6p;UooXLMe zqy_22W7;a~thxOMR~608y0>jvSw*+`EPzz>zmP>ZMqQfCFv}_do^MnY$XI2SlPf!n zlAnRmz`ZsNqBGDVdhC8iw`Er!3)K8E?*{k>qpH9~O1bk5(lcH$%={O+Yq6qFzmwXEfg2RzuQ8Zc4HWq|ZuuNY>4`*u@Ffm<6@-B#fax?QDmq8ucrS4Ldk zIkmDy6Z#-;0VD;vWdl6QYYmpo2By*gjx#C+QdVAU{NaN6*B`bAyAM7xp$7_E&KS(oC6p>~eY>L41lyZtlv%MnlxdDnu|MH5!bw25W zIFCsCDl4~`ffENPB2D#*!0!%FMEa>$1im*w5ozclRyA-drCg3kyHtNgnO+fi z&j3ZF`@ACX$pMN;&v-@PI|CF=O01Yph5PB&6@%2{6@h0AP((V%D^`O4n4GKHP@|;;N&2>2cK!sy^7tITT2xdG{Mu_hc*bP#}xYDI)b-0fz!9*C`_TVTyjbG()qx z*s@E23yrD+{gCvr=2%j4;04}gt1AKe#@1=n;x{H9r+3DDZ3LwLb!0sZ4V4=<$40cmuSotn1Zf3Tc&`={d-8=r8$xnE~*QlK(`GlGsr+`L0x}+bpA! z<4^P(lN%zdgrmXPc3zBP?Vz(^iXG(>PFKhJ<-xh>4Nrw_oTV|Yvsf8$uXJ2XTY3h( zN-1}uN4h;TMc^|^ImN+(&b6Q^aJB`l0|}G+N}EVmTF^SM7&N|{My21epbg-a7W7ac zVcaPYi3lZ6dCyk2kLtE{s6cquVy4e2Jk(+)hbcVIQv{r=RLdK}T2^|xuELFsN`R*+ z)iOmm!|MURWK;^I%+kZ%Jwc&zIHk<5TLCo+_@+?_kSKCc1fFX-B*3p36`cx)=`Jd5 zuZ)WhVMA1BWpk4NY2Wshsl(*+?0Ry(9Qp1F9>3R7#PXzXx4T)o+vq6DLF&E7qBMZh zlv<%Ob)(BWci((a+s~P80>pMTpW#$_=r}&DFIC%hs;s~ac!5z>;4G!wqC~pFD+0eh zKoRL?Q_O&O8C3<|XH*9KgHcuBD@J9&b!ya54UZSdT)fFgRNzG2=W0T_LRnG7Hr%p9 zzTyR9?G7|Z$CdX(IKjqBBSGsia{F$io!mr)Th)%E{^qJ>_bchTApF zECXJwlt|uo)X<^ALvdg@)?^JVi+KeUwZRn_+ zR*Sr2$wPm+cks#TO};ZxWSavNu|rx6JW_YHS58|Q%%F=J5a+p?xm7Srx3}q5rXcVx zrOHPF!)whj1r`lUPHa)cMp?x8j@be={F6n@fV??U&iz21Z*bWo?QP%6SApY=N`d<; zRbKfoH9pT($cX{>`=n(g0^FZ!Dk<^X5J} z`(LZOcp@b~%!7FnMFty4P?<Eff!7!n&syE} z4^zp2Z+R*VKdI9(7wA^PuRFw1yXsab;2uiJU*wsue^mbc9j5r6Z82&lI!z7%kCD$&$QlCq_Z{Ukc$&b6gG`)$$`+7=zF#+j( ze)t753Uas&J1-Q2aEOM?Ey0Y01OzfDVo3w2UZ}A7LWK<%Dr_?ERXWHwB2>9UcYV)P zdVu#RC9`yKXjX~s8lhduy;Q7ly-H=JO6QDx3d=8%<68rv`Y?Ihz0T3k@&T;ve#oMrc>$QMy z7*zwlV^jj{>T-is@&yMOOgF0(_=r(;Aep#Hhs1li=~RbM#OvASHXhE%4kwBx8I z;H17EcJQ2`A&ha7?lA3rIcGlNNbt< z1V}PY5vkiN0!h&+BKd@)PfjGUJ}5T5tgumM8h6t;WOY-O65I>&uq_WH<|5`Fw}et43CWFO{ZQ@wEz`nRGqYqfh1(ld#W|kjJPAC; zw4$+_sk^>rDjD#0qpHBWlyYN-w8@8Dt`ZSA%BT#uxl+#7SLYCaDZ}1tS*hXv70V+! zgLSLV{e3v#@kZ5vCmNLjrz+)=Lh|oXi*6}l%br% zEnYTJ;ZdFnyE#*LUFlVTzcs1`d_pPL1f&)9izivS4=P;bDd3n@T4(||Uu zZ=QNdiMGk*Ja9v8LT(8ru&5E6Vsf=`Z1)bT$#p2_3`-*V*fBaVlWSzGzGGHpsgoYL zm0VnZL&xoI8^7o{^MdYrUAJX(y{>uqDxwemsC>>+j#L=Z^Hin1a>|&nhp|p~6a6c_ zYap)`Z2d_ggl~Gi(EUGj7b9HqktNZIaEz^r40w)FRp5C_xfP0ZhgS?Un5Mh>O(ntV zW>1AysN7;IQFj;Ut|v_;1HNih75KVRE^nlDR&{|(+VZR#{M~#dSgmSS(d0sfH;tA! z9+k#=fMSP|AK|ffM*UX zuAI;}hEJMd3jB;3%IO7oT)|h`L?S}Tc?kC;BOj-M$C&#*AP)02(AO(gHW8oGCiVFbs9H7(V|*U{1MsGJ->kTy%F&pcaM8SojS zYQSfea%&gq7f@JGue8LP4OvX}{Qf2HyjNyIr`4S0j8oiYP_mseY;kX%cjreCZ| z9cwcJ8E~XgHQ;EYGT;_Uxp4}cf%`5qOo1bessiyTm%YHE`}jU)xB583d}Y8nM%92f zD&sg&y%(gd#<7KHnMoBI^Fn_1O?ICT9&^6u-Q`!VWc2lG{} zD)d%KXf;VyzGhY#@HwNZz!!|lfG;ZL+JN+yDOQ2+4p1~{T^gHpD%{kl=;%SVmz(<( z_*bK9KvI+i10+A!RiwAQEzt679RZPiYPG={d5-yN0G~Ii4kVxaDqHuGOrBb!iS!?D z3nUq*h~!g?X2x)B=)Tt240xhZHQ>ocWx!LEa$}5ip()mY7Y|SjTSOlFm|+S$!Kf;b z;4*r^qWk!8H%ond&wORTKN(d8{@JJuxL7GyCen+hSOvZ`Krt+HsqWo$J)7FV9;2$j zNk(PBPbuZ{KsweGtH2WmC?ZYwii4##+Eh~D;YQVfhB$+(5w25?_w*``nQ$+Hq zMeB#It!BO&z&@jTf#f6W2S_q`#D=Bz1#b%^8K;QkQ;R+_klH%ts|R?5QFS2s$k(92 zVro5>+VS2NNHTe9JxwH^TC}uhs*mrOuMGH{QB~jzMrFVkmC7S#O{BL>u?l>5fFjZg z>odorV>PMWX}(h6^G4NyU%rZ`o(Sqm8NpKW9`1JVq(kHKfx_u?jq6fFjblUNM?$x@)Ydq`=P@RRfYwKG$?F z$+%`9o$hUcB;yp3d}>kGW~q-m%vT2N+?Z+52fRcn*CM2kZeogI<^SHuF*};CY$t{L z8Px|o(5NhQL*7gI!vd~cDj|H zp~epijMEwPIh#ot@X}40@ztvp{@GJ6DE!`V({jN7dw}lxvTo(;)Uyo)J6!eMO=$hQo@b(C^VK-$790=FEXs19xOn4-sZo0koK zUO73u0{@{@>yZwGx4oVs+jML2{VcB(xU&9wG%p}+BJq}YIiH&o1+lM2nXg8PuSV!= zrzo!sU)Ncx3Gh2g$&zYoBHZis?pOG*r+~llrZbud6e|Zkpszbx>*Pu{@?ivcvw5H1 z)#5GT;#X*{=M~Yi1h)KR1?foY{u3ram~@QJFTY17R&s zKGKG;wkH>~A*|!c`E3a6d2(JG!Umq4+lH`_C+D;wY~sn;Z3vrsa#kC{a8I7shA>5+ zqiR(Ywx6Dj*X1V*4fq$Ms=%iUPp+m-q%rz5nj9E_3zc%K8EGf~uosZzoZ|au*C4w; zTXuCI`Q*MDCE3->vTHQs?CNFN#gDtkz3U-6rkKpP*=6%>cG-NJTQ=Vom(90DW%F%e z*?fDXY`!fhn{V^W=G(lo`8Ky~zRf9{Z*z6o`EjLZG)VqN!f-H4P#&@w4&F#T7Vx8cmiBg7k5h!fwd){^;l5v7WGW9V?ffOkk!`m=ZkdcP_2i=-+x6F%9z`M z@TAR|{C+A;?$n?1&@NE~o}rzSKXErx;jcVJCy&!J zk7)fue+fu)g}Nl@Z2sr+l=`J^g*r~B8oy!?Dr~dl6}D5Tu$e-ItrRNNmeELYKUlwZ zv;wQADWvwH^5fMLPP0#oh1D5|nbl|QvAd*hO-aY@yq~GG8~B(S(4(cj*=8-=~VEu>P_u5 zf%A`3U>1>tc*)M4ETa|~E~FM2FQqz@jHT4l3l~$143|KQ^yxZ8VjME%vMyBlzSi}S zZoBfA7QDB?PNSMIkLn)z)C#0W;I3Ol%--rIz#BLysl*k@nCd z)m{4P2Y2NBzDm~f0cV7%x_q53iJa!sg~AOnK(k>;hvhLkambx*bAXJHPQ&7!Y)X}umz$O)-P08yij4~LWN}u6;28Y z^nd2F54f`xSOxk5`{Dxo;sX2P0;_R>eH3_~T_^SZQXyk5e?Od>e`p_-`hXmAWSPZn z=!@IX7q%fB`qn}SlW&n9z;aeciDi6XJ8r1+^>y9m2R85mJ^xF{v)bv{LHg^<7TK%9 zDY})D^Q{V5JuSVvwUNHJ^{}@sy^rc~goV>0!_KwHumcb3Jo$}ohgQz0OqIV3(x!Fo zq+9rK(DJ%NpSMISDms3KLzcT?He)U~C7GvmRw!Vh$urv#ICzO3^ZE1s!UO2na6KIB zJP$_f5I^d1e@7jGQno*Y06KDaHLxgmxe%YXton|TXF?) zv!0y%Y@ZM|Ku#$1f;PyJ6nMV*o&cmTlGD;Q1mBMd^y3&?6L!YpNYpYdnb%9(N+$8r zwvy?&w2i*iZQ@N}F5c#;c;Zb6dn*knnRrXvN+#Y?y;bT*f>Zrh{FyLraFuTEYTc~T zC1#BbUYu)mM4O@Gd8uyYV+NCIo~`ici^lUJs|2g>npNV9a%g`|_EVO00_5;m@_oTH z)n;N0ylPuh4{(khuF{?Z*yB{<9OZPwIpElE;2axPLQX5|DN`Q*&)+Z)ni-_PDS&*+pQz6P5e z2?X}DwjQ=US0iUXL+bRL%yTs`<4|&0ldFX# zh*~%V-0ZtXuXp9cHE;v_sdp8)ky81gCu<^Y?G=F^9-xS{hgSsdIY2SY?pn?2e#%Iem@$nna$i(Z$U`o^isB<}@yzEL&cg-W@36OJ;zjyA&- z$cqo;1OhDjDtS&{eJnIz8SoSK+wD5=5T#sRNauRRFx6S=_Azsx0uMB+J|GTr_h}Q! zyN}K+-%z(5>MLKw;I++v0vu;l4d?v@OYqsImH>SY(FN46HHW2EVzPlc*wH%z?qXCG zxTjGG&?j0Y(P>^QYO?Nn$W$`m*YwxaG9Q4~E9J%zX^~eP%>A#-eF~gxRy81w+!zk# z>wfdq0A6LjdVwUD`)V|ih){C6zD3<0puY0?06xi)C3?7-F!gu?xQb&aKDQAY5>nrN-ixHv>{N3kV`5E{a$l%1%aRL zi{_#V!k4_}!V1D!o_wT&Kt*}<3c`7+nSZ|wKHqcQU<%K_Uk1~JRypAyj#MY(%vpC6 ze5!KtnczBw_$v9BfK_5v$*~H(qXb7cc&#v{dAjRwrjh|av^rC*23$ocH?NS^GsO(J zn^8639s_KV_V$YJpIS<4Sh)!}nBntQQvx=ZKrF%{uNS(ntm&8|bt`8} z;5XKCyJW0@%hq<3%O0s_KMd{#w(H~4P7&$v%9e~ic^qVUq`+-7kNm{djdDz{2(Nl_RvW_Wo;ns<~n zZ|CTXv{2^*xrx7z3*EF=J~n757GGfDb-?6rNLE&QPu_4FP8AfH3v$x~ zh;3_R2D3vcAF21(iOVBCeoAWDL~CH|@=#1ACQR8x$+>%Ue*CB~p?<8GiBgt2F?lJA z4DckrcrIw8#%o#`_%P3kRn~?Ij1NMeQYd zFKREzdr^By-iz8x@?I2utxEf8uPi8FA;CFiN6$HJBsj)~HvtxUJ*TZC=Q(X9InQY; z$$3t6RGh9;`)j(DoPmX$=a=O?KMGrN+mu;_vwX#Y-?W&$z;~3AS0DB_5g1T8Kma-M zGSA)C`GDmeFndEsjEHCfA9=hLLeSFM(CBS`+ zs@ zN`RXiRl88(6-FgM?>idZd8+-SS!KXg`6af@!mNq3qp~s$fO`y3L^{$d0;dg73`dt# zp0-p{;7aDJ3M3ylx=7oZVhSW588_fWuLUHvlF^OxYLM5;=BN%N6F0g@-hDK>yqMxW zD?0%WG557&6`pKV0`$J4(VeN<=bKdqyg;cu&-l-c@ScM=ydm%j`}ub-@F}I7FQhlT zBJiyNibxgx$#%&lDtYi$09o-stlR_$CliKCtbhja_m)=`NXl-|kY4qQKvH&!NTgCS zdC220mPZfpadTe-5;=F@(?ojBD*}n^6p?%$(M&i-eO#{F_R0=T@Kwrn$*&wvscbZI zTodM+V9(x7-Vg9VuxDHo=AmHE-pw$*Ja#xQePj>UOQlwAb7ZTgQ%?_Ud3iab2Lp{ibd^_>Vl2y=Hc55P)~y5t{>7*o@HwSi4oFM9q9WV;K+&H}g>p>g z8bvpoN&>vws45Ug^2P>vVJ{gxZ;A=fCly6ps@lW#(~Hy$+|#Hk@Gzy^TXB(kjXhCb zwTskeY(7RvpEakMMz+mvx{F}0EF^--Q5Hxf$r(tP74nJEmBfEbbBYG}w$B6jd;QQU z-wFW#sFWLHr0;gRoJG-+SI|_q3(Z#z_-m!)UBTm;2n6b^oFPMqL?EjI!bfHvTLMJB zU&G`R9J77(cS<=2KG?YJo7XGGec9r;Q2p{-GC8IK2`RTQc2ZBf>sBZN5=5w@wSgz< zRvt;dwux}2bvOF5_66oR5B?a>|y?ZRpWIMIm$-*b0RUCc- z;TM{t2{<~$97S~u)m|R2Tgi~2qJcu4uMViEqz=CyZ&nr7me+iwvD_sydGtH4j{gYun~ljXF9lquU$IistIz~8fW=K-YKRkh^8|BsphUgaVQ zh)+4>&+m^S*dad-5`A{uQsZxDc_hGtjj90;Gb#c40-_`20@Z%btTN#4_F#1t_^MK! zm6PW7H<8{n_Kewb$5Ew~>|yZ?xQ0H}YUo2>z%4+Hcx1tDK zeuTBu%~raV(;dDr6e`T?qpH2gtfC99M0fF18TsOPOp{+TJgz%iWau2rns@$Xh1iwM z#L&uJx?y;MI&dt~r4}Ir62U3He`*QO++S_J5}@zS#L&@j9k1~=BQl`>yM0yQ6#aFL zTb4*8?djSoa0jC@;EqZ;TO^*YE@>pG9b~Dcz-jjTqB?Mmg8Q_Iw4vou2Oc~?5$Pna z2t0FuBGN3c2&9I*viR|n7c|#pmU9BU&K~ri0K8GDj>?(+O@yDAUJvk*q8`Gdrk4Q! zpj3W{=O=!<``<_bk1#3$^5+}nkuwIGuF6#d-Q3#RF@YharJ@zKQmC+LC08I%=zv$O zW6@cCtg0NYDtUR}PbnvBdPy58lW(p_f@GI-;qc~MxK=)3(8d2FLI0=~w|-3+R?s5D z5?W+f!&kI9*H~}sK>q6Thx2KCdFM(?IyMn7vh(uJuHmD)hL2wPw+DZE*d|@WH{WHn z@`sGxXhajUKicne>Z|E&+RSEEohj65^TihA=AL3iC`HcV@qCF+%WG@o*}Bcg4*Uz_ zwr_%26Y_oS(h7@$oLeNqN3?+4BNg0V;HZXK)-n#)L5mE>f#H1D4sOvLAEl|^Y$bFz z!IU7Mh{FPe`XH%_T9|0b$Lqx!`xV`GRQe}35q7Y{%|w!T$5Ua&l(S*shy>os%#y7Y z?p{#Cdz;Ot1jtAgj#9+|3X`CJcW6CwNddgqN}Rf^4S^{m7pKFb<3ZRQ$${3asM$-u z){E>G=!AdOCVmE-XTLJ20{QEia@8z%ERg1_qC1-+RqVO@=rV|)Z&=V2_&p2ShogUZ z3dkR?bZ0pvBIcjs!e;+jLy@zrW*~8f=C_STCQW4AmE7aR+g+AgZ)_Fa)2yrZ$-0%3 z!lE$G3a%Li`4|KAzpIKmiWO}fQkju|*g_nt5#@qfF2<2IH}*tf!%W`Pj&0_%jX!k# zRCoSOxAG+o@HM5@uS|Wea(U<2jar+jPs)As?k&f(Rn}QE3Q5Pex2cl>_c5vp9B)(x z++Qg-6T^xU-FvDx1U_t34fqSCL|MgnX5WKwv?yN zY;V4+(hy571Fof1d*!6zVG^M;IU3?=L-Q1U<|4iErjh~upJc59zp7fY45SVGq0=9l zZ57BLJavlqtHPtEm;rxfRJ0^d)?F8wN|b${?&2@f%8`bo?lr6E5(Aa*no1OVq3(L# zR5F9ZT<2xVbtvRFFLI~>uI9DEff}Z}Mwm(lJi@3duvaPRF_oS)#SHi-qoS_j>t}xzTwS*-%=`n9ccL9Jl(gzn*kqG%0)$b$k;q8(lg#1_`FhO zQTdU?diIci2IP;4%CODVz4v-8;8R9b`QgH9Yr5LRFf5XATbor1ywRu{kg)Em2Rf0(UV-H6Vq! z_9GqR6@e7u6p_B^6@fP^tsM}fbjOfNi>BuOzz_0Sp&y8IbjPNx0Mo{l+)Fr7 zUIunqCyE!S!N|c4axZe{L5%3#vq4&6cXraQGNH_qwZOuQgu5Z?$8}W z^BwieI+6daeBL0TnLXn*6CVMF7WzFfJe#ks!fCTYD_MyVP9E=x`d8JZp`H+#THYXR z&?8#S)4G*I20oW)MI}d(ZVflyR%8a`k>-3Q#LtUhxR)8Gz|R_01s&iE+rPj1Xqc}A_tQNUTJgtZ z`E#psNdnCLuQq^nqcY%OMpc1F8kGTmVpR1pg=^Yl{nd>Xj`h^u3J)?W15PrkI#@No zw1QJ04&4MmO3haa#Jy7-EW)D}p#l7<)mQ^ks~be5wJc~2NC%uE(r#W6Na9WriJVKm z(EXz(`d3Rh0nW07dx2LPm5}YamP9X*{A4);$)xP#Ch_=Lq0BKLKNWOWd!y#E&t=6*KtH2G7%7B|HCX1n!z$D42u}h1 zC`L81>o~K@fX6G9&xrUa85^c$hVeH}Q`GIHJ|b}TawE>sz5LilMhy7K2QvJwMNEM> zkYg*b=qt{Cq5AlX`O1Jp)^j5)ldDVN#-19ka4VxS;5J4@#~s4)Qx>_K2E<`LJZTfj z`%1(4_D@auJxe_y&vh+>=-RDYcO7mj8L-z=VXR5IYlc?=^2-Nl6L2Se+TG1Gq&@5z z_^2(oKik}=Kz>3YcTRvfbe%%-?(2hPk58E$K&*0K@m~bFNb{L*c_qMCjj91VwLrO_ zIK3IC6%ECc>SBqxN`Xt2lKW`Gz!mH2)P-%)Ek2x~RdNM2P92TXb zYnw{4zQPSX1?2Z4@}&vBclBC8A8uk8jz2njuk|h(&IfeYZw6O+LU;XbaFthd*MA0A znW>rIU=?J*{q6bpI`BZHIx90|9Fcei-1Qr2x;F=&HozRI-`MSE+MV$6@lvxPz);{u6sXbh8b}Dat#yRJHZqlv@=|MDaXklLIg5~-9tvJ&UfLmtyDk6s{=bN4-#$KSjnkjPFE z$>-6l{j$x=idHaR3Gl;4Wx$h+s*=*Po+2FMCx?3A<~EcG&?glwzirhgKk|`d#?eZB z!NS$Z;9R9zPm-|^Zt~=tO$6q&X#S^(@UYih)Rn&Up*(STZFFV* zmbP|F3vlTo>pK9Y4ZPBEO@z&rlq`Ta%MY#iV2dww^1qBcZ(M8d`zBZNv%k|NZo!|rFmF*`r<37tg;ZMq3WmI*6!iRO+TCE6w@Z_@Q zb1FQqTRGqW-}HL#H4#?wsR4&6)hb~(6+UWY$+Es)i~g?lqY8Y^s6I+&ifI^#~(&2=>tmf*Sq8+7!KL~PF0>X z#|eL-(C3&i;a0H$kFM^1rVf5%j-p2YB2q~S`=VK;#9GN>MMV# z2>c3C1`>#~_DX+rgvS>;%R9n{x-!Hxn{BKT{mw2{iH;el@YB(fK=g2%!F#!d?%K{& zqM@Cs%kn1O%6S9$9i`kEfcn_RhH05$e7KJd8)b&^;XXF(DKqSe&ddB(?GL_2;M2>k zF*Z!g4C5MO!$z55Tw`q5Q)U>~$gmu#K*kYxlu~XSk&g9>*oIpi$e{&@wL6m|d0)|T z#wQNsb}ta?+*hNC3o;7@vEd+H zeSgD2hBh>uqQq?7%A5dl=__~gfm`Usq}-d7r_GUeF!n@Yk#;n;?Cv0Oud%o(aBI6_ zod7KQidRzXtAQ_nsoMuE`id9VjhfG0mRA+{fKfHz5KFZRT*attRfQWGRRfMRD*6yM zPs7~r!vP;QDgmxzj%q++$hl4RZ9^$o%atgfeqZ#yf!OM`Qy__4;!1`&qjL0*nG+%?Pb>%HQ@e6WxxZJa!0_y za^{5=a<~J|u$=3_bCi+e2ZOCNbE8ujas=&vUa_a->uU--O!T?1iUYH<*3w&>Yq8|%~$nNtN zAqD=*s2Y%b-0DJl-YWvh$0;I_O35A1sp^ABq5>q$f7#bBEw3t&cg@K8H%=-#M_i;1 zzHW|^s};`k)LjY}cq;62rNc3!bt~b4J9oNWGGcoveA!cjIr4wGJq3QutR@0+=sJhw z-ACse^2DcHQ32OA_kF;xDwVr$G?C_dMc_RH6p6u88EB|x84^qKW#okZ{H z)?E}Jtzf=VAUA{Z=la2`TBq|Xig20{09*{|bg=F_RJY=WEF!)m4 zwUWN>LKX{~!Y zw6iH@!2OJ>0*jY|@dKcI7q+n)mOVTY>d4v(OXfQ3WQ(5x&sC~?e$3Ln4|+r3AO4Gm zX_;Ys)qJhGo$Dip)v&8@6%?v0R_k}X7vNfU;>wRVNdD$&2Ar&l^76nbO@!kHSRHE-6&`L>4LH%L1o#=FqVa!O+pv|Y2_g?V zc7Z=@-fL7%iDe6DS5>DfnUp}jsFG%dZQ%>62P{|y{F_mAAlC_Q>LPX7xxEhLLZW<* z-=Lm}l$Qg3+M?FNTzQ}2uS})-dxd}XRA@C!v)jV5%z%d}Ri5R@z)(Knb~Q2GUU#~8 zDa4PCahcTbqXPeJR4?!yrCcIN8|XP-u4sXqDCHE9Rv7AvF8S6w&Lbs{w=Iu8Adz$T zX%lH9%cBoSWT%Ma^N23or)e;P%cTyG;PQn$kjVcVd1U0lU`Q8%#XK_W2ZQn785jPb z{J(4vs&sK@Yj+jM+wJ7a0O)%i9eemp!G*P0ouod$WWJM&6)y5rxOC3bT^D&3;0s1Y z%k*q5=?*I`0s4$;w04L&N`PFL%khz(Z0ogvBqv%V<9iY%MFxBxDLG}ci%)4Kt0`8A zntz05O2_5qRoK>8CGv8Gdb!K$j#Sw73sZ>##VV1P->UVW%}ey5I97>Pcc{{Ob}1}- zm>#9Jx1&`C{ENMisRsPJQtn8Hv_cn0x*BkpQce-+yIygyJa(}>QsA?eM;%CHcPK*Y zGWT^Lk)0xv&m$Tg`ay8H`2u{@QtJicFn8Z*B5h)M^a6?K6vN_ARL^Hv1U|!==5*b4 zxo%gj9C2CajIP$p$u^Xq@4}PWYLyxCd)$HoJBDaC*UVGCtW*9O>Ai#%L|&+88!fTa zizTgq+~;WSn^#V)y!mk3$}_(R(ICLmhd;fJdes=!dC?9oRDJfP1lA z^Rli&AEXCy7yhmp|3kNO&IVR&p+tuZc0Fk-^$)yiD2_Q?a`24Z*Kp4fLCy$3x|}bD ztQotH&J&wz);{|xR{Ppos{(oZp`2lXKK1BW8>XIL_L4h^<{SZWRd%(1n&$Zx>vD3H z!s|U1PL3;d*Oguc=nL+>QVS)1$%$}fb?^!A2p$K45P6AJA}zUeKC8R{(0AI~TJ!OBc7 z&~kWCxMU9S-RFn(Hb7YxPpF$`tUKFB)r30B%XBlnYS>b@WidmY<@rn0&#AhVB?shP z?($O8g%t!o2)0+IjREuab>W7C578@o;noAEo*M?Pdaesx_gn?cmlfh~I=JEWrht1q zHyM1Ca#9=c9Hm;d*)maZllJ2Kg&u>)o3Dw-DD3xC=;^G$lT0EU(I~lWh#l4Nd6xN3 zfTS*lVYpeU{gPRwz^CnMsu%dYQu$FNZ6a}wmD4Y9BRj#Qz)#z8KDrW%lW33x4)chO zCK5j7lL&Atjo5mi9D$h5`u%I~DGS?E61Jx#?7aT6u<>J<2Wb;$TYqa9@^W<eCBPZ^a0pEW87c?VQwYM>2OvX!VOBwX%o2R>IFT7tvvZi1z~GXE~p@Eqoka~ z$AY)@TsOGeb7R0ecy2g&C(o@1-q~}*z`J;^3;dlm3Z*#c|BYLfhOLsD1aYHM8nvQE z6fGcu-CRKOZxpQq=c}z#MEbPmD;|NA;1qrK4#hPz!Wv|_<*$0{Fq68RhJlQ5OAmn& z7IIP9a4(F8TQnc3gySvbf=bDNk1ZMS?veo?Q!?PgO9p&BI!(7)#e~hO>zeqoZu65P z_y@LLs=!B-lJ__CHxX#0oO5p0o-+1Ak;d&dGpY>jUN*EB*Q&0y zf|IbI^VGu}?YAtj8Qcp?U3;pLqAyBIR|E$ z3pWYOaa_0tm~|~&0%lnYHy+Hg7H%AvWi3l`em?^1TF80*2rO(N=k_BoQ2C1PN1)ph zXAJl--%y}$=(I869NbU4#%z)a2P|~2yQF*FCEc4`(!EI~-D{L|FDdEX_^^9~>Li`k2TvwwkLZc)?g9y|jbydK{sPPXscr)+=*3ASs#QIjn z*F;a9rtoZ|qLEstyIwYx40!6=#gRg~P+1u%;B2L2!fyl~Z?C+}XK6T6an!UdYTAsW zrbI19h({`p&?t-0D2dP@0<}n8!@$L;@ksqgySS<~DFJ@Us4BkR^3-T;*Uq{vx#(D| zzCWo}t#dfS6mwOlWn|jY3kLvM4{7%oiH!pnkdqW@&BrjmmSDY7n=a{by zc#Baf@K&YD`?XN_u4~^UWV)L;=25vv3U{*14}n ziLXZJiz-H$uPjvIkA9!#Re--#s=QMe@_R%XF5veHhK(i??nE(6Vxb!R(k^A~tN48OBH5nHuRli?C^H;9RkY=`0Kj6z z_{RS{O>w@ZngJInRbC^8JXbGARAA9Ct}!-jlo`e~F4lbh?o$PBs9#-{r;6bQ_MCGH zEE>kCKBtk;?yQ_3e+C)}+x#i!bYv1;j11RsTU*!+c*Jt^#qe-5Oo2tiINwoffVRsQ z3ERQ)out;sTG$MDwNmB%#qcUKOo2tiIN#W?QDzuVg`+eQ+OAL}f(};b9JT(j<(mN? zF)9WAOet48(l1Og11=q)7#@#r)xAH`ZF}W}VPK*UshpVqJw8M-7*aVQrwP5d-~s%c za$Wg{x6;3$PIhbPce!%P0IsK$s}Si3uL%6?0L8GvI6_($A#Di*TSt=m8cZ#0T7EI#RgR!3}$&G<}(H&#edMPf_Rh9orC|R>l0ri^3(kZRrixtjnxfDe$*y z=f)KYZ?cr%-&X@)Sh+zA4foXG`&beQ5C3C!RL*8nqk!X;n^Pq^`522Z$gU%rq5KoQ+VDY)Zqu;bh7mUA7Q>dlu-pPFe(8Kx8$l}5hW{rscNrp4?bkT zyOqjkMtqwGL;tX63cRRbm^P8_vIr@#7$H8>ysN3<)?HvA;g$;wWPCeqBqE_5_I*`N zu3xw9m8rw=p)6BRn1-$4d@vz{>7Z8f2fTVmZ!@Ob4` zl5hJ?mp|sa(a5&u!OCSN`$FFfRObcV$|VZ$Y<-}ld_G`!pgney0(%RFX%p!zuLvwg zi08vEH6`4-5k|r-BaDo1r;S7;w8J($t+5W#B=h-z$1fH*Fn*UaA8@&o)g9e?K!uLy z^8xJ5qWSQyCcBm;*4+fJr(AJ9Y^>afl6_$#W~t71bu04$$Wuk-^8v$k{nJ9gEtSd* z(k+HA@X{Gs6scuTtfyVt9)grof_MoazEK zc*+bj;LFR6h~Xd2Fa;J3M{0aww7A!FQ1r`nCR52WFh7DlRaPU+&HNzfY(J;QpF-{Ho z%rFBUuT=SPV0eTXrof_MTqA~unqdQ2G>mJUq6Qb6VFtWbsq$1YywD6&V9_v66~lAP zumLO@#;MLxgYTPR2E1RX@>DUr#|%?o(J)SRff_tzh8ghXjAJaSccDd5URnyjp>Ea0(5)qulRE82#a6c1>yUs=%PKK1dS`AR~o6?E6C zy6vc((BDMZXE}Bng;FJRU}9Fay26I1CMcwIdB%_W&NrM|%8QpuOjl<2V8ajSO9d}sn-A(Wc%H^K{ zPSyJg^l4bhzR>pq)!ETM^fp=H*E}_t)!)=wh7|Z2v+4ulFmGGhL|W(-L-)T^xA=7T z2#|2wSvf<#aYVu`cMgyV0sn4P{WXQ{`Vf;W7htzh(YnL;63Z|JzHGjGfy8h_i{#x$ zziYw$O!L(MUS!naz{{0#3l8a9rq}@9Yt-Su=Zu;FBtPd4iKfVn1)wj0C!uVVUe&(5 zXzpt`@>bC*-%_MHM3?$agvLf>T8XXBpDQFx=L z2DAFIsiZ)x-MAy&;}wC!^dUK?I9LQ8nv@{`;?s>45^hBiSd0)~7*hFHEwvsXKJy4Y zO{9mtBCr@CzM$V<4X!i8D!wo*xxe49+9V^3lY$;MM;Y)*rB=_+Q0~VfJB^ZqseHE+ zwv?Fr+0%&`@Z!Q)#9ti5hH05$d|f(O-Olh4!=z^EuE)Fz@C~DChw6iv-?9fXYj-QW z*Qo4Kg-;n(8!X)Y<~s$xV^kgZ33Vhd{(bE9CKAcGiHmfT1+4>bGxIa$i7_M+cjidG zj1)*YE;^Dgt{xV*zQ)_aQpvVbxR<9$c(SKXPhU==9TwDPAjj98`Sn!oLk(yo+c!NfJoK=CxDkVP{YqLBq_IhD|=IO47O(g>!y`EE+PaeSQl#)N2@Sl^KNZ&BFtdR@; z$0ID&2qP`w`e6!5Jnvdmy6XJi%rf9A>r;9a$lv=epDhd2$8Wr^FdTp29fxu_1}@+C zikb}C@`7}^;zYtWzv9eB#?QE+_X%IpAqv0hsjCz|>ZvgQhVJ^bsU%q4;Hl7xswtx6 zB(zwqSKff8XTZ_=9J*Zn0>>z|f;<2)v}^1}O^B`hjz((-#5R6M(%J#Bt=}=ewF6>1 zzhhi$2Sm5-=*piAXzhVnvN6d=hf3;O%j!#kq$nSffjD%BY$WeKx(tuqH*h~v)0M{) z7Pldc^5n7#!seb_T0x-YV!ot;K)Z9F6$FwOQhutdzG$p)7P&a$jYcPRO-&!199!W|wPm^5+ib(KG##giuX| zFMG=8=Mc_!DmVvkYR;>~JJ(Y{QfU1q7~xv4M_x3mWXWBw!3kKb5Ks9pKtoq$zY4u6 z@Fj00AbDH~6?zgX?99itgrjtuC-pnUi>$l^c&_$X=E9Q7FIDK&WtiKJP)r|Mieb=i zYxY0Vt>pDng}?PwXmx0iYG*$0hd!a~+9cCrk;qqGZb7yknxQi%-wDc!;+&uaq24c* zymAsDQAc$kb`d|8>O@D&% z{I4~gpp?;SFagN>1J6OcarBUG;)~i#8jKY=XoIy%49lCgxAx!@x^1uQ)Vx|Tb1q-& z3zU1%^mdFcqpBM52;IspXVm|qW+iu_m+G#~HgN+gpFDwkZVJ^0+(#*Q@r87mR}5zb z?zc4eDR4KlssnN8&bdh5eRN94{o3Zf0i0k|6^NtUeSB}=E;aa}Zu4mae%hSXfU9Ww z9hH;%n+WSzP0^>&?bXFT<|;W_wa+oD1bC5opY~YT)5@XhVh6LEK(BBq=RjOgwNRm_ z(duZNiKk&uw8@ONBd`$pSn44QjyLd$)waGmzU@?z)Uf!!5k*C$-INtY;2#GlIwSvYoJvY6zZ>qOAs8< z6gg31b(J~lCDmPQ3iSfXSH20J+2#{;=zLA@65Zx&0Q?8#BqFIFXPQ-Vsitz7rIY}DmTBnwBy~VH+bc8l=O11Z zoeL~j2HZk}$vY3m5ap)@&O334Fz>0Wj>@Uin+Tn1DCFcO-fr{c^k(Spc6IZHW!4LP z+ak}e*hUTWM8P|nvm{JmobIZbN(Ma7sKbHRDCNpQy2mRH=Kg3?Nr7h> z)d1qq9jlRUGQ||=BQ^$$*f6UGkSb(+fW*inHkwG@eKweT9LNuYfmr9hdP;otgubR~ zia3zdOsMijRk^~dsfH>Gbk{#kB?B%~$_>|GhA*073dBKM_5H^HD4)kwox_UwS~OWCX#m_eU!lc4D;0hV(n%<(ygXg2R>g2 z+Grw;u$t;X%5@%*e0KG)_&wD#6}!t3B#L&IBS<95X2ty4 z%>4og-*lp|i#BYcZ7A#t3oq;n8<1&C#w0&pgRj{1QE((DJmOG>J9!PB_S(IEn?x|ksT*={b zoO=0!&Cm?^o>6_kv7=p`Zp9)UudLkV2Yz9IBGOm9V%V=gYp`c@n>PpiswI*FS5{B? zjUDiC<%U+KR!**L)I=Vs{0hPjpIR9ajn(Puf40S`0*6}0HL9IpR5h+EI@jPEt32V* zEa$?09Id(BuG_pH;2&6?32+BXstzPyng2kaM0ZIN@gydR%L_?>uQP6^Cith8SnvPW zkh8RqA6h{f@cUc1Cdmg$-~&pz`H1x77*hoP&8Q5x)|RFfHvbI`{vnH)0%sUiC)}mx zyAHhGs1!&hCChX>)jrm&`fgX~t)dS_?V1Uh$>IjC?UMxFX;hWGcd&4E;J!vxfd?Cv z0I5>Gc%eG-mFj>#^=jPmXr0W}mOr4|&dN$d)@~xbYO^81Ek2!MID*WX->Bh=@<3PD z*il_$M>iKK^?bZ5^g>eeEqn(2xlt+bcS^OMxkh-_>xG$@T;L4XIeClC%?x<#hh27V zsw17OtoQ=ny=_qu>F3IdBJjxpiec?>Drs3NX){hGElVYBlFB2NN(wBd5??BRR=e@i zRxU|7Rj;|VgSYEeC?NUBcNXWhBao5k0guo$T6zd1B6?v%?%l>Qzt^oCSAi?pDD(nX zQz}1h6Y&|ZX3%<(v?(N&k`!nJ1JU|@Ji>o$&Lrl(he_Ipb7M(mDl{4F#2+S4v_7g}y zTYAhN@+tY2G%T`9rrl+o`Tr^PW-WiE%Cwp7mvv4%Oa6hoyJR2SpG)?^(Y_Vr4+yp# z(nK;X1`F5IVr}%=+qpe*WV&17{hk`kY7bLMfmr89NIBX>zEa$7((SxDMWoG@ExAa3 zM^nAsg7)FwTSX`63sw6Dvr5R|K~IGRQq8warH0inJOzA5DfxIm224REH{1`>8b77m z{OAO}+Uk!^&TDV)vfM(qa_9qo+NkPeh5ep7Tj9hVoP&}_H74nEs+WxXug{;C)8b&)wMte?+%(WpnRXM?I!nX#?=LM%95&8z|^QZk+1a`;By=A8@QuUb>K&hiZUR~r!8Cp{E|_1B0uFbz~@2U zH?V3{9XP?LC!Cqw2sjjfyfL%mWrK0X}C`oydJY z1AJcOeFHBust&x)s3-%%{L8{6z_oX>f{A>s&j6pddf&i1jj99hGb+k}FrzJ80^HB2 zI+3698Q}9V?;H4Aqw2t?jfyfL%wZNT0ZuWhPUO{WS=aITlJ^aK&8Rx?U8AB52=he? zmjJIas!rsO`3&&6^6rdP0$kImI&c%Cq6`Rgi-k*oKR2pQ^#rR?(AO6@)`z#h&G$!k1*X_ZMJi1iUP*;@90TRCR4+}JgU-Kfrr+52*@VmT>Z z5cZZnCZ0mZuW2>p7qvl zGw|#6OJPU-74=uHj2-XAaZf8t5h4pBxti(U#%PPxZn7|r3-q!`tAa(+w?3p9Q z1D#^M*tlZ)c)v9jByHa(Q%kyfM=Te-4x@H~bhX^n+Ie{t5`W}TcoVM=!gob^NzkY= zs=~+c`Y>~!Ixp;5LT6 z;l4H|+^>s$X+J@uUnjf7K@DOr+TTfuo#&tiu~$22v=#S%6~X&;GE^`2Ip?lPtRk_C zsagsK9TclzFh9jA7)Xiraiw;Liy4oCu@$G5;<4|ws-<{ThiWS*YeOx?Wo@XX(5$Rl z3N-t@-Rl_Z3ocYp1%?R0LRjq$|!E)vwb>{2EuIIFhVr9@yE494& zVmb34IP=Y7H+AO6ij_fQzPY59H$OHs{}Ro<=FAtw%1uRXdbRkq>C$}bO8hz=YZJe& z$0mwb3ZUC6URej$EPf-eTM)mA$3}`*pP^ePei-HOuEe5QYA6i=yJo4OoS2@JONx4f z=WbHloelu)K~|PBp3W(|16=s{kTm%el8giL+=IW!uAqU!S zVWSay)gczLwXN2TL?I~lj)Y*C9(ibT9_qy|8Y!nmvA-i^D_$)*$MH$5oMXijt2iHaAd9q-qCQ?e*h24-W^8iOYNpnzxfw6z z=H&;quWxQ^gpTG_a}MRD(ESAZnC^TP_GVHJC&f0r6+8M}-{H{E@90ax-x=T=xFsW>CFYB@DqWt58E31K6Ec zLn$-e$g8280qn}Fp`-y^kXJ)l1K62YLumszKd*-J2CyTqhVlk*c3utT4Pbj-4do5s zvI;enIjm-4m9I!H%-H+Plmf*Y?6NPtjQ89RXLauChN5^p*(nZckRipEu>-$PLtl}a zWkdWr&QeR-QcKv8UP^!Lv>L>=A8v*1k)@pChLl3)#QwlRMX@KxY}J?4l81~QDu}Nb zSJXrDE76$w9<2CP9kxSByy7vs^}OCpiW8&Q7DCYvv!p{ytz(M%dS|LZ?EMa^7yAGq zn?<$$-~=1QzTu#Hv2P}H)f(`9I~JJmVuumR9;(?iqbRF#Q*km=OM%+6mRbtboY%~c zm#D31tqrvlu(hF<3z#-s+eK^Q2>T$9VZmJy^a9-vyMP)D|4Uo{O?Jb+hS^46 z!&IZMVV<-58ru4AMlOu6mLqtOFGaD9ger4W4=bs0j~nsKFIw>G9A~Xw>}4^<`jT1; zyr9^)hxC(G#UZm94{v1q_L#@?M>ixTw-^Pnam925-86gQ5pME|eS{B^@Gi+?WdG=( z2C>KU&<828lO5C`_D%<-9ych0yR6?UJs-b*RR!yZhk`1%F3R9?V;c>29OE2RI zZyUAlU_Wrz7Dfgr3?Sp)?p_+YpLEUK%%yp~%dykuGt9q~rE8B;#=eOXT?%`nT2Zes z8$yw8A}_mH+aPv0Z{X~ju2wTq><3~G;rS$c@t23!orij{TRK~fV&%q8dbN&pg7sqO zI;c_Xwy`+sOKK^)j0bcdDEpn}+?4r&zpZwD2`Rx(=|c`5MHc}}E3>?ICr6g!uY9e%ZLb%G6I zmpZ6X?1u?mwQ_uy2sI{leFrs){f>hg#7=Thqu4nPY7l#!gBr!&OenjAM>9$#!Jc2# zy2SOt{Pdn$%7f05YTxRl&B;@(r4BVV)KWfVLv1C+#-Wz-Vt)cqEv3fFs-^5$S+$fP zE31}rWM$P-#uS^MGL{Sbi?LK^f6LBhRNmFRB+;1GeNL-h>^CrEyCkzRU^ia1WX^Up z?9f8`msG|+@Nh~bwVs4S7%TDBTv^tO)gWeMDm0X=1sSj%R7>WvJ2;U3C6&>^At{km z2c@k_LkGpy`3{Ozuk+Q|!w-OE7@V)sty`UotiIF`6L>cwv8Y&D9laZrocxcT%A z#G^Djgo@^&hIj>-aa*Gv?&AH4^;+DCeUGH2WFUcJz19lmrH-C2IMUk3Zv%+EjF1_O zQ6;s0=LN;Smk?BI=uyt158ZNddL9)ka+lV~{w*;~rap;bp{)WtFvewmL`nRy4%?w5 z{sf2ZSQ3At!*(i(pX{)mOX8tBU+p{G8I*09562HJacxE;=3GHR}#O_Vf&TDFLK!aCGiguLp6(ij8J8+ zEniaONe@<()Ogl|l_fQv^I%m;jlX(urIH$NcyK^Tjdwh_a!HM)9voOw<6j;eR8r#; z4-PK51`7^7TD4Tk#voGkTHN)Y#C2l_fPc^PcyK^T zjh#HWa!HNdJvgwW#@-$rR8nJq4-PJ=G17ypl+-xVgWoEtF~);=w>n%$up+l>>W!%y zE(iy>g`q+0cbe_A&OT#GaSx|hFLtzpju9KTm0qZ2tIjDli+#jFjba}oWa4TrsU;5? zJ98~NQcsF4{wT7?c}VO;2i2cJ_A&?Yw#2V@Y1{R3bF$NF5-Woy^!k!o3%sD%Cka_W z@6K}f^6LFgu^{&M4r&xDTNzuO+}+`{3Su8{P?K00GW%#4(*6`z=c6|eh&4G=jbfGm z=x2Y`P?j==u!kl#8)Y412*uX$4H`Tj=@_EMrXE~ep~f%|c2}senFkkDsIi3yyDHS! z%7Y6k)Y!&@ofT?q=fU|EYHaVpjtVut?ZMdGlJr)U3jplhGI8@ivLSyF0!b`X_IU`Mo|2E zC&gk^<0^tiQ2g67VuEU{9m|Y(Wi4{8#y?|%;$xFxL6tS`|0=KB$MU)d^Et=ob$->a zII>-&CT8VzAfK-rY}ezg@dHQ=_WpQ_eL)(13T56Y7QB`e;3uW5e!O-%!*!Dyf`lA7 zfFX<`In}D#Bn- z{=hoa;71q>VAYd-Fjux&{&rF$HzUZE!K{@38)hJyT44&XF@y<-05e^zH z_C^Pd)hJA4;-M&3s}MXs84L@g!qUV%dABkg6v&0kmVvl1X;I3m;On`@YqTnIJD0?3 znBa0zr3UI;t}zj)#!7CtX%Z{vk(?SnlATN9V@u_t%CN8$N^DuYvPz8wTq{k?3h(Ev zBe=aXwSHnVR3#~*NG>CkD^shsLQxT$Y>wdyeg-L?b&1tRZN#)`DsYHB$JpO@eW)#k z8@f@|a<6iSs@PcNznE3|FS^RtatdWtzE)E}=`wFonQJYDlr~jg(=DoLt*($t7jR2P z0l%10z#KPU02_1t-G(%)dX<89w*!qRiT@cfya6b7zT1@W!|iHl&48R%hzY)&bxc!6 zGTu&9L1+s%fu7A_)f6(AO7yDOE-3y+VyIBD+SK7uE12Rk*2K^8v1)9!UKug*6L{=| zHL<@Ygefq)O8wOE8r_}~?P&am6v2sIof|96iQU6N1+gj+NQu>AXY7kt(HOB{0W@M8 zaHHOjG>Z2cHeMiwZgGkY_Z?C|=W$0<4FVDy-|7!!i5*6Yj*8Vv3r(>)Jek-!d2-b1 z3o)@eGa9jvPPL(JcbcUTtK|u+l@!oV$>z>*QkL<5ziF+h$W0L9uW=KjAXbMkBPL!& zhiyr$=7$jzzrU-$f>_ldG{ve6ji&gQT}h5s_4!#gT5P-^#jBXij>)Q1Eg1*mRZJNh zs}WOORk(T?trAj^KvQhIUc{>+ASO0m9O8d4RpUAO)9IF7opl4vbP0{lDj}7VHZEum znQ4tpAqAvDJK7c6=(%LI&qB)AljXi?Rec;=!IqKt%T-b3q9w{CTYQ@Zg-1BQLGjT<8vP_7=DQPB-#)3HyvWF0>->}4RN#pYmg7+fEvL9 z`QzLm7sP60BV9GJhFN1939iT@5DBixGGGNWHW-zRMm-W#Lv!8qPrN33B&bHb2*hjT zBSAGZlZ{33n$?k@j-&T+)FV*itueNsAK-}7eV7iM#)bGvJd!}Mvr3I8V^3_ve@YCy zpje$kBV9G(PawqWq!|gSp{>G1BmQ!hNF=C+>cR+$*FiNBR6|ErBPf1Nf1K&8TAPgx zNR6O)9cm+sYUp@t1jXxIYdgcj(dJ?V#n0d|BN9|Y%Zd>cuL6n$)zB(p1jVaXB0)7& zEJjd#tZ+K3)KCE#LGfB}B8zHh=P-iewU|VLYN+arU{G^86a>lgO3(6-k2 zQM~8J6ROksII)Wq<0V#48Z+Jqk%1GPp@LXFFMyUJ`I$e4i`9afVOv3ZL&duo-2FaC zu|CM6+$6X9KWzsv3IF2H=ZR)zEu30DGpYq4#V6E}p7}ZbbohPgNsUkBckS(E9`Ex!8yO zwzRl1V_O0kytG2-5ej}9wJz%^(?a)@=@zcG2ykJg8n+X~r$fam%t%fR&6~)L8nH>V zu-^d9G*z&=g@=m=Tzs!`YDJ(L@45MQv{;>v@vqfBP&uz^vwTTN-c5z0#cBnKjH+>$ z>-5oLbzcLyWtD2E^O3R|>b&WXcpV@kK{Ygtkx4aTDSIH5vbVWl>k$kzJBH|4O6>V- z#}KW)I_*W0=||O256@hYWKc`F(D8uWhrj-+B9{w&3lH534 zy8jtdf-t;?T--xB%|2@4%S0+T>1F(K%{7$1o74<}_>Y~X7O@H|g`nRBnnbayr>+=*46aO@JR2$0S`_ds9PBhVQpb13Z|PC6jh zmOBgou87*l5rVpxo-YP6VDl*&5W7oe0#KF6OwSN(b+qdDf03JK4~d z8G+g>b)OW0x?5n#FL=u2N$w zJ~fWsdsjmdMUu)$uP^P{RciRshNE<815|0x=KBh>g`3 zl{(XfQ3RKu4!Q$?}!303B1 z$)MX73N~e$EFLkNQIEsLCj`j;f4$=}1kB40E%y%+1a+m!4&zIbxUMGJWyKXR9--FAR!NhB(;j;p1kEzc9450PFq&UZjjpe#MD>?01 z$w_Z<>dQ0ELvaDSqAo?N?%&xLAAj+gnYQNsOd833!A9P#q!}Na+mX)3IH&bblJ#+n zem~_hwWTRPN`{#T%Kkwv`}mnh@&!`lQS65f8Y@Lfl^B=&Q4HCGU;Edx^F zd{n3^B4fOZzLi}30_LjD;}tHg0F_QTh$KT7ryXq(eFO(JCN}P;2Q5!u#`zeV}7Vs2qWz=6#$}`eZIr5 zq-W-byN|=Qh&{?d1+n_19B$O~4877lFK-dMnu7{r^|3f8ik;%5TE52zUG?sPSBuyd z2NlHX@fd9B8T+a{`=CQ&s~uD*mzj;-yIsX}W{T>d;>D(^IDG`EO;cHaoY}X}LDceN z(HMHPf*KBe_!$+YIP?YupmZFK%7nJ8j8ar+3PL3pMj||nMR*vH@GvUjVQ9k34U6K7 zsyYlV0>j86FbpdK!ZokpehX7=qly|Iji7wL6sVs zS4J@Ghrz;b7)-tRCvUK^u!~g@L_WffP3L0_eOS)?!j|}p-6M{so5meacOngG zt%h=1deUP0qPO$(xe$Zt(*XJ)fWbmrde*K_rDU93F5$!WSKUMR)ERCcz9Fs8Gi2OA zuEjUc^zk+%TdY2Rkl}j_we;3oRu^vJ0;jh%R>_@`TlH(a*57gSl0ZG_U(LKHGOx;C zKiy_T@5_YO!+govV|0oFSzM_%0%RltL(PTMP$Woz^d4dmfI_WDc=w{4Hkj_L(lZ#{ zQ$?UY3pb0#B2b@-lcxym&j&^?^Z+Qd4=A*rG3*)fcMJ)wBdU%eq5TL9Jw#v_|KFIS zuSiXih*#dQ_sHv>ZeL67Ju~^irtk4lG4=p``asWi0qLH;=ss)Is3%zJM8@V3+D2E} zt3vA$7}}4(&_e`Ml`oH8 z?i$1nJwHBdYHdsuUjr7q&4qEnurTD|YUiO|?9)H8!svk5rG)Iauhq(*#Xgh}RO@LkDE7;QpjzY4&P6X+6sw$B*J>$k_yma9pT<&M zUsCHAF4aY`@l>Zv_!y>G`L(}zqn1)^e~?}+rC2{ssJ8NKrPWfNC9SrSZKc&xvL&sy zGH#{SQpP2%w$jeHnS7;P(rPRBR$49PUeao70Bokz(f~+WZHjEh04XQ0G7EshjspsN2Po_UARnRS(s8yZ&PF%?TGDa0q~mN+ zoX@#9Thej1%;c2$)J>h1bm%SV&|B`{%y`Gmkd~GUY%h)_#RHW4$Uf?!w`W_a)wpCq z$^!oHZXA<6N%6yqf2i<3tT^5Lu%fOVNE!RXiqR!+$Z|v3x2;LdyW8d;76|3S>|^`+ zs-%*6(bY+lhGf%rYaxv~_=}cXjpey6X=Uz5=dMytNVPmDcV^YR ziov)&EvXJKVb@}p%30Agz(eBox#wsQ04e#J8Gw|Pt$u7x0t%NKK+1?O*|D3jWFIGm zRJw}C_7^7}%Jo!~!cZ+5Mr+Y9V2g$^TQm&YqG99~4THC6fAQl+E({(}7&)LYY(Qbm zfWm+Qh0y{ELj_bW&NbW$Srn@h!HvW0iZJ*H48xDWumceob|C`8PDEhXjR*`o5`pEq zqPSPar*NX_5ytK=gz>uzVISOuupjP1*cW#p?2o$;_Q_o+*RLPAA*$DezlIY&*(Ri@Qk~-N|i* zP2?ef43DjX~XnOO_OrHw_9qOMv^_;Lk(n4@X$SE{TkJz;i+;vZBv+raH8Pk ztTgQ7(ohtu<#hnca?rBPOJVWF&fQ9rMAiP(rL8Dd%dte2P8~XgD}g$B2v_?am+PWf z9X}+h_QP%riefbe64gK``{g|C&;M01rgM_2g>;|3;rT^#3CEBy?ByS6G*cjzjx%+B3FEYl%4cF2NQzjC`LP`-*%J0A8F#o6kX>7rPjAt&@dexn<9z+hny z3>J1lzT^lCjH=mh)s5l)3#s((n_8LDwu`c@6BepY>`^>H=vbtag-#B_)z--iCd4XY ziH2bdPsg6B{dDYO6}tk(HmDfo7*OaFP}<$t{)WMBNufuJhE6RS`n722+M@k=$E2KH z5ju~+(02ret|Kt?9Dys~_}nbV{+y{y!`!(Q8II4b$Z(wA7&N@G+c5Qa`8QZ{`G3B3 zQUsrJ(woVt5OmTunE2J)0lOg97vgA*i_YFgQ~Zy;rdZ7(oWjK_u|`v!oa^onM~nSA zAtNSUr*c>elW)YrK@TT9Ca}U+Fn|<;H=dfKdW5d$(zdvDKX~uC*0Dv^dV(mPn~MD` zA*fd6c~%|o-HX+eZEH~p(<*CGg{wqZRJV3|Olr|EF=2nOO{g==iHYQtmp5J6HHlq=#S_V? zq5Pq@N?xz4yC$*9XQZlhZsMOzh*gFox&9LD9ylq@>WI6b&L~KCL7^%xcR{f!5O<+m zFum>eig^cOw=JT_b>&1==ve&bS1RTMSO*cP;R1V)hh(ovvZQ zTJ#mxstVzoOnCXx{KXUyE7#?wiri{`Kvk?F`9Dn+g{C-M8HZVL7Zj1)y9+BkBjoc7 zrr&HH;#*m}c+ML}V8lY_29sYc4F(gh*_rX!SW)aok48=W9>i9{T*c>X)bzm>zG-j@ z#CQqI@DAqTkyt*&Kj*L!CGr1s*bc7q>vD-SZ|jLy60&?M-#hwzOI)F57xW%tv78AS{Ks64!*n;@H$tbetkVbN9-0kJWHZqP#PK{+A z{G_DD@JnN!)!36DJd2$Ympgo}RcawMDG>kfc`<{z%WUJSD`Vh;Y^=__BgjumYHZ-a zt4eD45gKFd_`hLVO(+^zCDLHxl}Su}vC5+n6R$)JW#%C!c8P-uVl@D$UNiCx1 zv&OF^#XX83yVT<@89ITp$V8bnxLM<&tZx4^TT@1NEcqER zO#Fky@NwcN$)3lGH>%=qA_lR0$S(1a#%KJ^)a|=iAaOUsd>u82RYv0C%0`JuB3jpf>PqFnBj4E(s-4@+SdB2e8|e`ghBGN~G3a#ebuKB(+ySH@cD+li zFb?5Lz!NSv#Up-UueOk4oW&mJprY8x4l0BZ$jx@nT|w-D4l34MZuRO(5tMA6?rn=b z+d)OKmpCXDf!rMB+!e&0;-KP(?7JdC1UJ*>J>It12OU%tyVyag2;}A*=dK|3ItLXy z*!O3B4%Dmp-nQ71gNkAmFUBey1-ZG$xhsf$!9hi3Uy&dOf2W%dox6hA&m2?~TlGup zI3ohNS>oIk#18(6w2G_$+_FcIA_C?0Ip?k*_7w*e#VX#62;^o%=dK`jF9#KseMN!@ zhOt+}eecBX?4Y99ItQgjL2iz4?h0bt98^@_=lC2buhrhR*mWFK6sveMav(Q9cJ2yd zuXRvSo}cv*s8@$McLlMH4l0TrACojZ9x!bc#Rv%PJxa~xC@`wIu9B9NO6oV$Y9Jsnh(=Q%!tMYQ>- zw=MQ52NlIW@1Rr!a`S!Xt{`@bgNpL}tdBr8-|)7@E^$y%?8gpDMIbk4J9h=Kzj9D< z^((j@kYYB4R+EOhP)V*lcxqWZ2#5J4?%?&)od-QPh)vASW( zn2mDtj&oNKJCKhv;O+_beRaRusaG32cLlLqIH)LA@n%FIH|slh1+jZLsCW@0P$URS z)qR5>VX?P4s3=x-n-PKB9PZo|#Ol!w+^O$6mH?W?j$Z6KTo60gK}E5;zs`t2H}b#c z^OLIF;4dpnY7KRV&t|ck5E_)Ld~wVDqXN~LSw~U4GinRh|CJlvq2XCpTB}8IKIpp8 z;!Rjiku7nLfSS{WQtqYoM`~5%b}WhamKs7!Ml1}VmJfg)A;o=|*cn$_VSEVYVX{N1 z4`>Ur!yVKh_A&=GE+qT9hfcfBn*A3kY?TXYjti<@?469nobRjDxXXhb6>2Q>;Oq)D z?)G4Ng&OyIa9LiB-*~Vuug3izd^fMggC6Y7tMQNrU(BnaG$Qz(yc!>L+U`d^Qe((9 z0^1hn)!2&QfZWWj2W+-DueLH7Styswg)W!PVwFDVb!O#qepW6!vT`{)E0^sR8M$1R zmCL@YT)vx?%igS9zUXqPqKtZ^hRPE2Sgg_<$*G|<(4flU&XV zVoxVjk(*U5J~j@ED%4OJSL9~aidPi_+giMe7+8&XQ25gly)C;6|_huN^ zxvkxLR}kCepr$aYKhyJHT?7TON-VP6m6hezFw4<;F|fv^Su1d4;BLlnzl)_HHZ~kx zso{8?i_yoVSjMkm9(+DhE4v191`})^#cBYxxfo1?r>(?b+Dp!&M}sMfH(eABV&8Jm zXt6^XpwU#Y*So=M5PO4zMvGk%(_DvRtFboLG~OC)gK2b?MuUaJ9OeUW&U~FpNCbu% zi9n@9|5$JYen~HWWX7z{@Ra}*uUPdAZ$7DGst-V7)rZJIf1NNL{icJe9vIylIdTi# z2o}V?U}q#j(!&+24w|1EaB zgBr#1eT|&`M2%WEctNo@60(A9I3jbCoMJ&N-^t8jO%N+L=(Dpxri*luGt?mV2}0Qs z6nXV1r&thsjDs4_Bzvxd3SxawskKXn)Jt?l>_i%>%uSnBQsaltddieKtS2yd&Lg&! zTC3(}@V6t+%xzT?Du-*it8J9p%82Rm$u#1{rpLu}`BaK+?5sJlAI9Z7D0e3*?mooc zO9;=oIv4L7H3U89rNur^XmvRJVQ#Bx^V^tTf4xuow_tiH__4FmAoi8K#WFs?whk|C z>O=}+8yqyMo9v?wDv0&AN6~SLZ0;ix`yE2rB`FJ%#)l)t#ud}QWtCQJ&Qfen9sX;n z*+7c9FLn$e8>(8f6N^@3L(gT$4Y(tiZhSbPPQAw!C?NC-m7V&sWtklft zr=yb8*{&KI#cBb-`gUqrhZCrW6L@oB|EN(CCIcBqLebPtRCuT_q3G? zU0zYFR!Xa=)?s-o2@h0pWInkMNzEuxdJriFHFpee@q}&YueIr#uqPk*gO z*Muob_`5;ZT$};3r3<$~>^KKC2EzEpfqh-$L>k1N!GO?jvFAIeLF@&DY+BX&sTUOc ztb@u1!DoWVa=q9yomP`rd4`l&xivx5m(-GH2#WPVH1(f}=4&YPBNs$btUO~K5i7SQ zh-Mdr_o!2tb9_EIxj_wzJ=u9|lv#BFQewUBR7!QG_?kX&oD}PAx5&`L&RvVxXB<=z z>)mM*mhFl;`>QXDT?qAIUyPWuL1y&|%dAD3aS(oqmtOZGVlg43mw6kJ>>yG+63>ZW zo7lH<({lQ?@iTM7-Y2|Pm9rvtLqdVZmV^)W8e;3SHI5-X*=tN8`x6g|oku8eYs2$@ z8<~kGeMXd|_1P!X&5dLqbx=X<^MqE*O{VL~lMPB@jq6Q=vQ+et z(r~PY#40mkEK1XSukrxd#SYTe;c{~xQ*x_IO`}+43mf?Kl1x3}Or<83^fq^$ZB%Ek zF0Z9JP>-{YC!tKnO|e8`Idpv_qpIG3@m1t@OHHp(Cc~3NVwDqmQYEQ8ut$h}lg^`4 zks3-<#!2Tj%1g8&w^J(UPzE1j2qTh6tPn#HO<`4|`Sx0WG8yTSnOJ>?Ry1o>6 zWimWTBv$aDr)`F>tT)}V$~fh zs8)}+C|2FEf@-NpuqamDv4U#t>^fI3Hr~1Nr}TqdD9vKyoojZTM(Wwj};ihm9zS*XU*)^$up3t)w{W{fg|Z9um9I zLG>?_{ilNp8ksG9_y>_a+C%Em1P`4=_H+-aKOG*TBS$oHS)(+EQl`t|uXET4H%bcG z$cfk8ph>mLYI!NVnIXPPYHTefzXeY`1`~e?v5XBsB6Uura17ZWc*tdd%$;<$h!kTe zc8P?(xJ>e5hBYZoslb~gt#h}}J*tJc2dPjK%s zq_16Qg$cBArZZo-lkDRjdX;RShyG1=HRrA{laKhnUGYASj3c6Tm1`x=Fw$e4g_ls?~S zHHhU0?y+MR#qyKSe8jAlwmcll#J=Io6~(?u$j%2ta z_-89<fTHUd8SS5Uc`dOI5wf{bOHY~*m)P~W%vnLTwj~NdvHK(h z)jHSpjzrW1jWX)kiJPt*Ftkv7Me4%(43Wp=8P;fXJw%|BMZ%0 zS!gb$v(TKCh2~N^3(Z+sNZ-x$vh4lQsNn-b|8|q4QS6rvO1(KD0}{>Hgj9zslfhgO zy9psXsU#>`LuLdi6vgg9=zpwON3*&ifJd?CE!U%@v@1YStQ6NYC&bP6)W6h%#<0|V zm{zWH=qzI`lc(b;lC|P?@Y>bROoP~m9n>WDw}fmi)q2_sihVXAsMhwbIGV%`CzL%p z+5#(_Vm%EzvXtC*PNY$+Y-gk^5$pZ5TmzHwV>=EfTUlR_m8uFbrHGXFHL? z`DDG8ir6V1K#}7}vjXqswPmE3Kw`fnWTRATg=*xn+nG}#nfW99xv$z z&AfRNytbvtSZ5{G-Ox%_ciX9cg)`G2_8LOA7iwMS1;s9KP_x)C6S@O=x3dnZwWyZf z9?IzCLYjHXd1w$Tt<`d8xTWljTzVyw?;-R(Aa@4d_8L}F`#|Cub$%bcsxuG~E34H> z@0)exbw&1}Bvv7(m4dO&J(TubPDJ@Yor+bE{iR0t<&sAQm-F%p1Ij8P>5L+SNW|Vn z$PTz#i@cz8L%OyTsTZrKUbw9iD}%;-eMv2EUOQiCJ*W6ka$==zY&B=tN=-n0i0&E} z>S(by6T&~QH7m8XYTuN@jKY(MVl!D6ug?Jt$o(icJ-1;=ZTTK(@y+rjA&N#CVK&r} zlX$^+6R&$(jH%eUu5(joxz9E!3dn`#*C6m~(tPenu}Z-}Gk!RSY?zVv)MK$Bv~!!Y zR}>q!*9?=86*Ib8)nDLPoJ~ z;;9!KQyUoSN$o19)-3i~cPtqrc46#T(p*yOD=#Q^A{TMH#Hpnd0KRS|_TGe`S|1UG zpxDRRcWY6tSKO95Myz^k1^e&sDD_v0$nLtK+GwWd7T47y)qAO7u?e+qpjPb6EA}3j z@1j^`sWNwI=PWg5x=a+r%3&lIx|Fe-U7$q;DwBAQc?PX&6fiZ#%6i7z{P#2Fzml5O zTl^u;Uz6B+LY2Acvr1~r^Ky#oV-JPBQQGCjc-))fN0OR%Yt%J$!pMcSWU#Po4A!5| z=oz_UeZa@6u;m+v1+fYvQdL9oKu)Y`JCajFF+xtPN;{HM!w*zy;pyY7Xj#d24oisG z@2)K9NU_H_s6p(r4mwh7HJ1*%8mjf&D$ZP(M+LF33!+}EJfp_MHaU;=V!w7!QLNmW zAnHqMeaO&YPV85)XzNRA%^j?0i(+pgWG$-YyOrAL)GZ|x=Q^?K3l@-S@nc;ln#Ibv z5i6IpEnLz@iH)hHmZvIuSs-Rx2$t6mT$wdKOIGQ?@BMu{HHSMH z#qUVXJQx2qG4%Zq`jYRg<)D}TzHlKlh^<)FCcsXKFg=L@_feI!9vO_ISlt=nm@0NQrEC?dr75wTXVV)y^Yvmca8Q$28MF(eTHbtW z^Vx(phC5q@v{vc?QYWQ#e}z7a?RAD4#r}^o8RyQX$ zRJC?=aiqpo9yPv5q1Y##`9^uvjSl)O_6thc4yolmrtXB&9-HM+590APMX~a1%r}?R z^5$D)PIOB$yOLr<5c{-)j+7x~2*-S}>H-wSdUvUtfkm__gE6g~%X&ehKiEUmb40gn zdg~iQFZMr9>qxO*6SCv%jF3s&s+X{kv-Ju{M_izs5w0OBumYNNznL8vl!TE5i9#=S9J@sD|3 zu}{Qx!!)SPqdQ8XK`hULWxmjuR@A4}b8*G=c%>Davpl9ZwzT4?EXDN3R!zt=g>1JaF17u{y@*KW7; z1Jbweu|YE0Ur2fh>BhHOy%qI;4*k#h zKgRPS{jYyZw*N4G$!$dWZAgzHJ%#a{K^p4cM7dv+-bs2l>HVZ{kS?H|+eq&seWZ+i z>Ag+;e~}Jhel>n!oXTey?{n09iS$*{9m>>?>}Xs_gZxkwEjAl_ARh>eq3gLY5&pNC!=X_DQQUbS%XDfkMtIP z1=pVer243|K770n*CXxer<7TrwEgMLmktK-U>FG7J1~x`Xzx1G+esIaK1SM0TFqxS z`;eYTde=Z}SkKWyw|YQ$HJ|z1K)Qf5lwU&pU!<}?@=C+2D1O(COw$+Dbf!}L;bbomvj@-OG!_q-}W;8AEVrsfn1(X zn?iqci2sK4G1Be%?BlznCw$9l-bOlbwa}7n|88|l|3vx{>EB4-BmI!{6Vkyd)WGcT zi2s4~&!jJrzDD{E=~B{9NSBf3)(8x<`QO?ZOna-6u3N@_k@NRB(i2EKNW-Xx9a0xT zZ;<}wFxy^2T6ef@A51!%^hwgUNIxKrjK%)!OS?^^{mCnimA+^FK0(?;`WMn=q+y(= z9bxqv3YNw~iCEd)DX_B=`+Ewh@(}7@Nxj=he?&j$m+`j)?X{Ag6!=kIXEJ~1kSfp0 z>)PMX?oanY7GJx`(hlwuJ!STbCG60@NcAjeV4grg*5UfR3F$D>y+{M`+_hYfZX>;u z^j^|Xehk;8@uX8oe^O?>I-Be7C8QmsSCQtp&aPT!y_H-i<*y^XTlztO^H#CI6{J^^ z-c1^a=RRG{B43bJu5Q~alU9>%L>lUU%=P0l(gB?3`>tsvR~lkzfpi?{*`%Spqp1HU z(r>CilX`PWFC)E*H1yX;d>QHIq-!(&Q2tHEeF$&d+DTv5ja;D6yMYDXA^m{#YtleG zSJ==ZN0E*rZ6gikZz290(r(hX%E&L`ljq-)K27>B($K!%^nID@vA#}T#d@tHEs_3) z^efieK<yvIw`qElfvT1EgcU;HP6G?9) zy_fVKq@n#ka^KZgaF?+CAJSiO9v{MbIf8UN>Gh<#UkdFH;68masqXi7qTLGvJE6Wl z3v)R2^)Z<7W%hsBU&8DEA(g+-{t(8o0qG{B<>VEw=FesQ#6OkxPAB~l>3q^Ko_D!E zEG7Mz^bO9FYRa--pKW$m$aJea~tV2 z(st5r(kjl!HA#0QJ)AU*x0n9jA^m`KP?`1W4ce*T{2oBMWtsW@DdoQ=mHeh<pId~NPkQE5$S(Ozap*R`D-Q84a%Iyp5;7$p7d?fe~})_`QJ(!=Ia&8y+*n!B{k$y&+(;M_b2bS`!jy}>4N&ijy8R^h6 z=db_Jp57L$;<~mv=@8OwNCWq|Uvd3-j`Ri6w@5?zn~3Xkj(4&BP#Jm2-OlSzlRiuO zC(_XW%fv(f^7AOKKS5f~Zm9n`<%e>8()UufVq0HjIi$?`wGr`9e)}@=dY`0~fs7+P zJ`9ZQKGJ2RpOX$MGk#YRzn1hyQhm(xOSY@n?}4PNlCDm=F)7_SqTij^gVzrvJ+zGc zG~ybUKeDZTtB>uk%joMvj-NB1mE3>yiwrI>GWsomxs-d7^i9%GzK{9%gmgW|u~C_L zc4ZuUlkQ9UebUhW>GZ2l0qQN*HMq~!kgm*qDAd1``gfBqB2~Xa`O9eUO447EE+h@* zbKF;7Cha55bHA%4y`41FKbZ1|k{(W~&n|}YdJcR&q&2yT$%p7#^)1n zkiJ9u57K{*oIX2N&iGz&fZ7#_a*6| zGV(WZzrKyMi}V4~M@aun8u~ku`~1127m&^)eTnp4(xs$-;q#N1NZ;Kkv~1gNmeKE| zUJvPt+B?6-+MPps`lhyBJIvBf(x*u+>i_Pwx#jCf4rPoXSUh38C66o#jb>f`#*4WXa(rcxDj(Rm^^rg2S^`+NIed*Pe(U;yd z>PxSe`qFDHqc6Sds4u;mU2T7)*Iq_ndVf*>rAI2g&NBMa8?Y1oQLj^!dfjF8rMD~f zrPoV+>GhV;m)MQPU#;-U!6;BX=^rlkZ$(8Z9b)7Y^ z9qG=b`;ywL{_h;(b4jlx?IgX9^j6Yb@Op>%d!!rgYXzo|2I9F@4z$Q>q&1|QlWs-& z9nw($io-2(73uY)3rR!yQ0_OBdxf-@^vyE*hc;M?50mzg9?}?kvh8-_=aJ4O{cRa} z;cxT$hom)4+4eUtTKwCjyOZus8fv{Y$|CQOE*)drlgC-wOM3FLw!PBvmaa#7`3biD z3h9*-ZF|rpORsFR^mbC)@_&Cf*77fq{*Clw(u!7l{WDUhd&>>rp3J4_A?f;}-gF=X|(;^g_~$Nv|Qjmh>jlTS!BDlaI5=*`$|{zDgR( zU&A;TklsT2B3GLOK zX_2i-Ye{z|4dss^K8AEA=^3PFk)BT)>aTp3MFx|uM*3UQnpyVxrtOy2lGc%qKilG4 z{n*l)^DXTl?IeBl0*h}l+tSBL-zHt{LW_rg5B)FWX=hwH#?@bZcQ8)H*TA^KctX3< zQ~#v5qW!C8ewF7}+v$<!8rF>$wA|b5SKCFlJ?dgh&mlc&j%}Y#svj=c^HPiJpOxSKXSO|- zH2eqM=Uis5uYQ%KTant9|GPNwE4?SE{~>AN3afJw>G!X+?OCMy2kpIO%gO$rOKdx| zU-*T^CzFQy(%YH(HJ4in{fkl3yQGZ1^u|$N{gIuUskgX{zVzl%zk~jJNaa^{!uX~4 zIQ12`?EIa6t9}`3+P3umL;dQXTf9K3xMe4_BE4__#9mR{vNMc+>&p0-UMuzGw}bu_ zx9o)erS~)HORtCe@;j!Cf9d^R@l&sQzV#%%Gt1~p?=$L4uRwk2{i2M%^tS)0^(Va! z>Mx?+^JVm!H5%J}#p#y}8t{=KRxql-`=0hhhGu_Zao%S9WTtr}-S}OK+L< z>A#wFE5EW6>Pv4su4h_5dT2*^R~|!s>1kb*U#%Pctv^$Obu(NiwQfCFCVva4zl8Mg zxi&(r!=b$}e*JsJXI*2jEF~TKE8AX3x`edmT8rO7+Dkg@I*T`vo|MyI?+#YjW zHgb9&LI0?c{&^&?X}K*cEZvDzpTp4mfL)dLdiZa2=pUj9?dkVFx@m8lDl4%)=>epN zlh%_SLmJx4(Z9YouqxYYlIjQi^!biZ|53{QiS&6={ev!{{1bt^{^gc(@}E$C8L570 zd|mcuLsESXFZ6c`uTLkvfV6{j9;xyl>i0KJq5SoEi`+$8;5fCChVtE%dxlhU`aRuH z{(1tplHN{w4`~nSi=-jhiGKDV-Iw$b(t6TSq@lik5N8~(>)%qijcxVkkuv(v5r2hL zKdkc>+j{?WSs8tOA8!NZb5qR&(h;P)lZNqMM_iv9xQ*?*Nj0w)m(hQV_&-SXezSfz zQ}byc>oxSR`Bly9nqQ;K$e&C6V$w@V!ym4^sf_**2Cz5jU8IY`z}SAA^cm8(N#7-X zpLDk}BeMW9UH!%V><)sT#hfJWmfa9M1;oz zsp&`S0?5?%BV*PfvlaPx?gi4>PsUz@Om#n&&CcH2kDbjR)3Y3zlgCY(Jas(&CG13m z`$4O%AMeeOY3)a5GGsdXkumFFdp|P2fQh33=e?X>ZIWohsu<@}lV#Zv}?*Jc% z8}sfp{P=Ox$FXJlRGBwbl6(z6cG@%{QT^mMSJTnqr+Pzh0y`7&cd)x|nBi?+#(1gB zkHp_K&85W4d}hk5Hs=3u6_wz(AXC$ijD8f^R8?jEfh}^m+okTP{=t}UMKb!dmb)A= zBTTS(t%3h5^X4RHM?V7jXHUwQkIh!*Yw5@!NwOSV;re9{6H5K4rs#Vi( zTdV$>IMu2d0b8rO;;CwNA|SYfuMPc0a;nvlXqz-uMm0YuAvb)guV)MtWQHZKt6|2X zV>x3n{KVs?8d;x1W&S3hHuGkMOrB9Djz6g_(qazFol<@a@3lyU-}TIINc1_xST=V0 z=I0|BTet5(rrO19#=#Gxk(kmpJz5iLz(-@@MzGtB;L%W76W9GqBUl3{(#pRIvX&PB zmmb0G6W2{cnKz?sGk+9{SZ7cxu2DW0O*_gp_CoBhM)@RQ=y2vJ8}Tnq#-jWfnYrlH zP@fJXfY&N;aviAkWzGlb*ZR2F0oeMA)}@q?S+&es6loLc4y3}2TV?*HR6jHe%v}cpg^U^RK&GxAnHL~a(~ry-km>42W;L8iSQ znNg7G!{FKq&z^&)K&G=FJLVhXt^LT{44K+~WS)Uc$8uyQjGsQXZQS&UW?S=j3g-7U zdK1VOKnlyTV+M6?%#HT7<95v4>PsNI0O`Q$o?L%y{g}CYKc-MaR3ZBFzg~ap*3js@ zld4v&KTF{pMT2-IDhx-p{wxGyW=v(i34fEP0wZkJpIwgB`m;M$ke3adc$xL*YZQrH zfAn-KArh@WPi?04=X*vp^)l;EC(!=ZA2Sc_`eUAmq+e$JF+T!q*PqK##Az|J{#*q+ zcKumDy>-H@S$}GNraYHle`?{uu0OS~W4!v8)}I3rf?I#4r5=6d%y%QYSy5Sgld*Ud zWD3|Oe1(q#(w;zO05SKUDD-Id=5pr%F{cNQ%mHF5!Xv)~a(n{01xRZGc>qXT0(k;R z=lbz@o(HlnY6Jsz;sBPAf+81Cfkwxfd}@^zRdc#Ii)rDr!vCwQe# z7d3%I?2J8xIm~~8SduTz?j}?e3K;P$P70u<*=?Rznn)`1Sj=;qr{v7+o-$RlyAFN+ zB{Y&RGrP~hu4iYrevLjUV@?-qkI?LXs3v*Uw#@AA0o&i~Hg`#Oc2{T4N;A99M=*AF zccYaGIXd^=i#oHjdtzDuahTa%Sb^EyiX_|F{VwVclP&hr>^2@^vwQ5x<4;Z;FQRWo zeVY}P8BH#CKSsJuGLetPKspnM`NmDJLv-%VMTi;Y6A|loV)3C8c)M)gn~3I4hIdtF zJ2ayimnFkzP3AWfZPnE#{FsKS4mWMAIwOP9iM`xiq*j2udG`m?FL;^Cy!}d5=AP*H zp@D=w_x=Mz^DSJd%-@<3wLSMfSFg(a2v*ZCQ<JCC#+Nzrg>9jkur_b?qxqbt7TNR$Vn5q5H9ys%{>xxT;Ikn-%^5YUaBy(K?n6Hxl{`GF_61 zkOA=Amq5&K?bq%|JCRHcklq9`0!YnHahZL9v?q{5fOIF2(Lg$Pj%!UdGQ%*Q@MHeR z+G7wWqnfwd*hW=FPt?YHR*5xo}i9zZm&NAc)88TN}IUhEdJ80*?9> z-JfE^3tpz?|8bpaeh5mfA&{^&|8t!EY|ZPNvq>?t8b6LR8^jRL(->i-FnF1ouSLwu ztNG~JDOA^t?4;+rF=^(-gF`egPKQPO7re~8H~@C+ycio?wM{cGx>jIbG!NFim<>lm z6Sg!jevd0|UW_%5CX$omGQ`qxi+%D|?yPkqWV&~WSLPzq1FfRDV`rQ&eCM5Z8PSdi zqBS#$CXknnon7O0-UiZ_K+Nw9_HNDEi0o9MmtDKXwblgEQ5Q!x1=6>l5X}o4 zvl;gzQ6eT5|4Ppblt%DM?*#}fc&VQ2Hd8%!q6g{MZYJg^&nBKa2$)%vd>ss#`EGtC z_XLX%p9ymcI_POgLHZx znmM>D&ZKs4+89RA$>3$?;I*)0=U{rjHR5It_O8Gj>_xzKZyE_l#;bp64!(g%?HoL1 z#-yn~n3kM@_zVEXwB`U-Zz?lbGxIaDk zUaFsYu71*WXjDx7Jn^LJ=Lz%-$I#$q>gRY=7T56Ls%@J3>6xke8J3ZuT+Y-_C$21S z4L7w>MD^L)mMQcTI&f7sTJ`*BmI2J5ad zJQd^KeSjVJtno53?T{%PNErj-uI)O|CQj_ky*;9@S<0;DG)a|#giT~04^E|9|EaXVK6X-~-94y5|~ahXSf)FzPEfwU&HJ_OR4 zkTJhfR+o_3+#pB9E$;@TCLv>lc z1c>?0u+Pu)21&@g0i-7(^NF$36!&GG{?`@b$S@%0bm1-U45TZ8j093>j%$qr(vgsv z4y1EbT;?Z0+7dFIK>89g_W~&-WS#`ladh0yn?Pz4GXDlrb4*-j9kZw;WVQv;n~>QP zNDt0qzNbe3DYV4x90#N;A@f6nBxEiI(vgt48b}?!S?A~Soj}?WGLHf2NywPrGA<-! zJ~qghxSeWjwzUbF&4BbIWcC44osek&QozZ<$1}!gAw_;JPXn@S=Xf^G2U3INn03zN zD3|*=kmo?X)~|u&j*DBq56HU-J5K{?A0L-_9Z25^apXfF)w|2Pc51t-1I_O>3{%1{ z$8eh7sj-~|uk=p6bszyd`os&mXis{7&|>dowNrQEit&PzC%6uG-7q@A_HNH!1Q`L zr@}x``GT)wx#aJ{u{*raIs&~v=YdVfaDTL2avwK<674OX`2@J)eWR(E@jGm?(|j2 z)J>0TeFmf>;cHb4W=BG%7D#JCW`83yBW|Y^NKYcdX+U~^7?&}hndnN$TyKz>aha!p z6i}IdwOInBBY~`i`}_8Uovnd%oEFzA0_jX3Z9sCT$7L=8(weYy6_Ak$qzg#jS#hlw zfz%{q{sE+WR$ON2P-G*4><^@OulNWa38b?*P|6XJ!#$Q_Xn&ocJ(_oC8gD`7qb`t z!Ph{@><7-jwEER)4bPu!T&7-T^&7uko}Y^O;GkU2e4aM>GOORHjkNmhRd)4Tcac`V zwd#@2h2 z#$ab|S^&6N{o3Z?dL*-L%8voeJy9JV?Lb-+GCu=Smq2a+ z(se;x>p>tj37H-s-Lu(?C?50P`-=y}Bm4+R?ObJbAf$ZqZLhHBt_{l<#qDeXS_j5seiexM%z(H21rXB7 z-;vPT5=c)%W_KXfKZ|R9A4ppQnP8BFozsDsXENT`b`+&41kY|B(CXf$+^dykM>%sdk<94qsE& zSH+P@KspjyXBy<{xXgt>YD#hBN+4|st=oYV5;Bh%nFR8(k#SmXPdUd}M%MDb#tLiJ zasT>X?B5GB{}4~F>0at( z_LOUIGlH!LG9$5UC59rBHz(>pK)~)P?WsN)A+x7+uE3r$e^c!#3vfms8QIq#?J1jL zD%m|{+G&%IOYbW0qoTSxZDp3*Q@(;s&%qq8$iW)xW0jCrgzN~UGa+*jkhW`RIg)8H zNJ3@`kltTe8Jmg=fS6}!eg*giklO3xGPeV1b%X2BeM;S4twh^G|+rwcE7mjQ5pv%q|w&CY_(ba}&mbYF>snVkiBSWJtV zS#TJFv9sW?v;gdwSwgz0<&KDmuA7CZWc_OGQI7j854qu@B}KVgB4Y7 z7Q7Cb+zs(MG{2|alR#F*2o*4tzIrzS(tBfEYd;_z3*yLeK-`%>3Vs@p_M0W63bzrO z5uAX+!tF!sm9B84FL-^Edxu9|^(NPEV^Y=IyPWFPI$xt~j3$>WnW~dal(Rd5^dykSfYjcq$}~cMF!5r) z63CW7dK1WQM&{RXt;2v+-yTOs18GelCmESL;xg?(%;`Ovm1Um5`~osvcS%b#&SuP1 z-2(%0j)-!iKbmoMFpCm^jIMb4O=eu}VC@%w@CL|f#%+x#Owm;4v4G^ZP05+rRQG{q z)1Od$II0FOGn*!SN3%)4ZJiV{vuWx5s@} zI+12JEgquTlo?Jmn`&2JHuVhGZ0dn8QyTuI{o)Q>v8SfCDJPv2OeKil2(@ljOV+p> ziw{Dkb)l^&n8WL7qm@8j2U2sls?NwP1=0s<4#igM3n1?%kb&lK^F4dr%4`6n^`5w$ zt%1CYCD&ZHGJ622UKE!(5J=%Sam2hs_hLe;2{N@0#AU_-X~%;re@}EWklu&m$d8QW z-^P(kfpq;Yj{FkH;)E}A_tN(JxXf>ioyX(Iqd*oVv|a$xu{bXCHy{g~jOMZ(FJvP> z61xnx?bz$To6G4s)Y{&{b@?Z%=gW)TYW2%X)-QTFEigC!B+z9`S5exJ*UOYeD7O<`QD0pwe!6$ z)pz6A?4JAWuK9j0PBLjRGv8lz^L=zGUIUojvvmdLdnfw7I^-+!Tf^7J30s=)<~y-= zzH`?ci}$@_XT*<@+3F{4jg_146);^ZnaInAKw1;XE zav;49Icn16V&i_zxmJvhUpKlS)Akf&j^cR=NP7bLo3WEXJ_K?qvf=GiY=S)nTauaY zb|qN@NFjmL0BKDi-v!c%GjTgB)gXsw$7R+9(w>mn9!OV0W*;Ec&&KT>1EkO%w=)???oV-y*$zl&Lgru~wF#M{f%GI~rUR)? z$Xoy<_m{Y@TY&VQ74O$WKxz{*uL0>!$ovaPYeHttVaR+!W(y!437Nft6cRG^K)Mq$ z6M@twWX=H6myo#vNOeNyRvzxA10?rCJmzbFwC3aU^iCi(FIkxii05*D1oCcTF24?> zFM%utQhi>$?_UGydO7ZEwauY*c3fstAU&_dWp)Q*-v6qEU-Lii?}7Bb8kZSs?6k*a zrUI#ZEiUsjAl(U>8-Ucj9+&9?(wRUW0@BwTmw5(A_ut~k+Xi_fj^ww%T6bmPUL5(8v6INg+dz5} z^K==IzNK-kHMfMF_v1({ke&om1XBG$TxJ@Ox&(3&kggxc^K%uD!aw6$w*cwHfz|i) zZXg}!NNeJxi!d#c?w8x z0(lY0$d!4|h~DB;7)B=H>q{W-y3Cs#PMSPvdfOLq%hg+>o)cO%K-v??9zfbw;wRW6 zUn7BR-LBCw&@n)22ghZm7&{5%5+HSRs8!|;`X*y1FH1dO^5a07UB8U?mx1K) z56bzheq@k@%z$lBz4*uGyvznbsuRA31L<2kE^{D||F5@i0gvRU&h7QuVF3e*ae{a` z16h1GV2javM2wMEyK4#dG3>*;7;tMeGt!KAG&7zVtt5v80XD3G7{TSS5S%E4$2xI9 zNr3DP4p9gp3JEs~IIy2Xh;FV!lw2n$H%`0|0{1^vb*j7iw6yEK{^-wZO`kqh|EW`_ zPMvynFFY$uc|9m&cZSPe2W7B5%yTCwbqD{@5thWQU;ft z2lyzgrhyF?P0AIy|EZ|VCm)^L|`)B&;Tr>|b+sE?&-=T&lE}94Ue3Rz^?#0V6 zUM6^G9w4>-;_F0<&*ymndMARsXdd88H}X8d+kT4rw&+Fk00URUV(?)5wrij%c~RfK z@IKZL+*8a&J8)L|c^+W#Sz_mvc`wap!Kdc|a;;jGY%DYhfPAlpMa>(Fx=f0zkY4~E z+C~Z$LFOI!f53Pd?s7P>Qf|S*>$(+OX3wzboGI0xg74}07hG(abi|W#iJOIB%N*mD z8vxsk*fP&!s)tMx`=jhL{=t@c;c0A{m=IF7&K&wLS>3kRZZ}qUH!R9+Da55_n_tdW zcUz1^`t0p%-+Y;weR|9VF?VEj*^5{mS=51B*`kJlCE>`Tj>9swMZp!uTx3zpmtaw) zLu^rXZ?7u#Xm z)7cJpfZ0T!M|Aw>EYf0=Q0_ZR`=`rERR5YpFL_242hddbg9e*~D+~*?+b%<+a@6 zbDh?=@GX>r>Y{6s>!J_bWFPKDb@7kr$8=p_VJ_w(Jug{3r@$erjN1E0##qmB9ufOe z!Sfc|-ldHZG}Q&|Ueg|1_8_e1AAnEmd8S+`NxO$S`s}9zB;TtmofH zE+oBsk)H1uWIfAr5jW|X*1?{N-`lsP@c(!{e=Ns(E`mp1q{Hkb=#bvBr*)VwY4nL%g8>8zBjD<%1hC63=f|o!Ey$~hCDGm=Dn#s)<>xr z%n`g}`0&x4Cq{>Nfl93*8Wk`zwVfADah?7x?p)tXd{n0&9ppNN!ecI~(+yjvX>gDh z+>6@IQ^vVYF-(r=khrN%=eMX+;-ScDEX)0%#NxKoW9z+8snCm>L-p=Ai+Jtss|AZ4yC~9%jqrZl;l|g&!Vj_Y8}DFR=Wb8rHk>7;F>@n{7PnHv*bRUi{tPe*2YrKbGqU9XaCbV z{-ORW5(Ai(Vp|Fo&$H%&EXfXk9h(F72=O#>M5h?J$PRC}c8F~xF&B*xziVTp-vN(g zBU{bl-^Fb8gVt7YcqAqt>bq%|KpW)PzU|pD(r9~Ly99e)w)T7u`5@!a#XhQP?b)vu zXQpa}(7AN>KW!KtQ;B2!hKZvt#s83UwEuBsVX;&k^=7WG-y=kRWdBlq`NQltHt*l( z!FRF#{fheqpk&|0=;S2=t0P(_!`w1{)6?yma);-QSqgr5738yIbCz}bYv6I4>f>qe zZMIIyV%>||`!3twsV%z~xA%f=?>oWZj(2n{v4779o~V*WW*8_(!!ta%6_4>7OYHqN z&1cUoV@^J}30)d%&ydx8+}Hu8KuJ>gN2S3|4E!Gk6}pVfx1gDZ$`xY3Ps1~m*@_2P zJ8!u~$*i$ROYYS{JVQf6MBR*so>3co#J0iDpt-(;$j(J=@NU}%_@~=x8f59isek_&G*6fZba?r;xO~WGe%kuXZqDBMOKo{@i?&S66xYqZ zn&Y}fP$K<~nK4_o?LALRRL<90xP2`@K|V8O+ZRdbUfMQ>Z=seKw2N3CRqtE#jNU>u za1ov%YQdZF5Hi`%uini*{Bx);SBJzy_Ve7m?89F}Byo{#tm2=xjTD|EtH?#Ras33_ z28<-;qI$1yQSa=-|F^Bvsba%9f2}i}g%{Oz3jZucQB3!M$JUpkd>E9r7Ds59j%t;V zd&*Lzwa~c$vi0D4Jl@!%$9W_Z;SXAGyfXkXzt|g7tOUiO#Su@$8}oS(>qQ44vmCXN zCA zC;12KNuC!$(YIt#i(6O}agir!Kg^zF0Tj0tu+{y*S{;VV{zSbq9mEc}Z4@y|Y@0Ur zBgOR$i)VRkJg+HKgK)i(>+x7rdMp29EUI8F3dN3GY*F`Hi;{B%l!UD1Kk>0IZ7qKS zip-0wqw#;wPhUWPtEs@tIKb=flO)-owdb}zQfRco0$!Ql32l!7dC?gMO@zuKn1 z$mixomiZ}bnUAsB946|m`rpC5)u3!D;3n&xzlinH`y3W}cr`g4i$(Fz!`8y-Y;sVi zEEM%<+cBMk0-?Ufne6-}Uq`3ZFXrn~N4Q73fb?$b=2mdCZ3VNf+14iW33wGMNgCG* z9*_NG*}`MysHuQdr_VXdb$X5viR@fdryqYMdmGo5nUU&i$<|j2WT|JW3-2U*n<6K5 z{*s=@w$L-{@aL=!@m(vwl&cmh#c)Xa4z$xYrNhl*(T{;=>F2^e;d7wSd-tf`v>v_; z$~-#Ufbt+w9G-81viJthhdqEsry3kWncP{m$5Vr2jJ0i1SU9)tv$l1o9BtAKx9&%` zXx+S@r0o}Vxwmh7lE{Y$WG!E{*0Svbo#GX?4`Pi?(%76TG;{>K3-JI!d78)uY_H*FYhg2rjlvisE%7 zgXshux(qD_D&~JjQO15jTT5K)CZ?b0^t=@6E3mqs289Ma0i_d^Rg;g_%t26gI6OH} zvTtO|q@3Rb%7&$|t!jD5R_PnV*Ak<>9*?bB3Ds8uZ5HYW+veD zMD*rl6b(FM_`kf!R&SkR?^lYoRkFk7OR&QW)(%t1$L&Db4u1B}P2Mq~ACzSJ4$P`Bm)N&g}p4*v=3 z@JbXMgvdoU|Ij7qFnb9)d~uC+2xZ1xq{Gw)bxp>N{#b|KvpTF}sGbj-q003>XjSVl z6{{a&`XlmM%2v^vt5jbHrR_~&&-VAAj5(C=f#SV6%=4@+w0DQ{Qc%_$%5G5VZwaS5 z49b#2sezKclX;{iyb`)`J2h@imtqO^ryD;njoZG%?a{0BxKMwORjI`OkG<%K^`f(Q z=B`%~Gg;K36}G5NfYHDL8Tn z0!!FDovw@(xn)bN4PP$#1Vd^c30WsYy%Gr2~U ztTXji-I{d2@XJU=?_Q(3=&l$x!QTVVqD@t=Q;ceAM`>*+)Id2IBCM zkNTBgXCL)#cvyLnk6OG0AC(M%u#NMtVcS@O1ON_QY#X;)+t73GW(iIi2iNI_s%0vBCtgef0xh^*Y^3n7r&!M?BNFRd(sSE~v=m!Kxo@;OoXIttMQ60- z8V3|dCacY zjBRo4;Bl>v5>YL`?BBSS4`Y_6L*zv*?jBpqJuy1dE$+V0af_pO1j&n9T*_KP8Vs^w zQj2@t3|qosU`aUg*i+VH?~*{EkhKhMVJ(!1Jof2Z!mSd7(8aBC4vtDkR;QZPdZS!z zO$6>5{HNi2H`rRFxOR-Md8p+=&5?3FVfJHIIoGUhxMiZ^u{X|I+n{+JS!HA!@4Uda zu@{v^ZP>lYHokz!TzlhRavz#I>hbUR1GbHaV|mCnvX@{RpG1hNz414Yk5o3<#`~;o zNO=jIY=hoUOC^r;B*a6uk$ElKhO|}o3Eun2OHf{-2JI;u8^w7YW!iwav;Upw)=*eV zr768>_zj2BlZFHirH{UWVJKz{vLg}tX@O2}EpxDXb_w*`1bSN{^g9K5N}#6%`j|j( zPlP@%(Ax!iyFkBLpr;a{zd@k43G_CBzF(m4N`yWu(02&*9Rhu~Ku;$^ZwYjoE_JPr zfXU0-er-IP&zpP@s<_LN5vQb%9P_ z#C6eW=HF0^x5*|#F9`HCfxaftpDxf(Btjn(=;sCcd4YbpKp#tl{yKraD$wa{m(jEC z3;Mo?4$e@F=1YmtPYCoCfsRQ>#xm#|0==FH{ir}+7U;_Yo#q4Fvd<<$&kFQ&0{xso z|E55nPlQfyPBx`5{ri$YUlQmK3iQ*7&_@LNS%HqFV^_jHdgr;3*;w5|BJ@21eNmt< z3iK}s^fQUj2L(F4!P}He*G116flfQY+_EnwLcc+vF9`Gnf&NK>el`($MxdV-=%)qx zM+N#)BJ>`CJ}=Pc1^R~s`ng2tX@Nc~&}Rkuf^cVK<^XiZHdq?7w9R0o)YLC0=+#Ex+l=v1$w(c-zm^jiO|1~ z88g6<{g}9}O`x|4^q&;yyAq*a5a>Gu`VN79r9e+7LVr}ClPVl-^guB#rSCFiGTTMJfEh}M()S;jmNXO-(+(y=e?*{f2=ons{)j*yNrb*G(ANd}xs6m`jS9j66hZi=%*8*uLyM7 z59@fgp0fh|9)Z4)2>pu!eNmt<3iLalAoOK{enz055$N=Nch}FKNmTX+1p0zNUl8aG zfxegs{hUBQEznO3^pZe7n+W~W0)1Yf&kOWh1^QAV^d*5lE6`^J`cZ*?E)n|u0=+KK z>jHhZKwnOTepaBD1bRuJ_XzZrMCczC=wkwXOrXE`2|`~K=qCjF34#8T0(~`6**`4M zvjROU&@UJ0=M$ly5$GcVeMF!?ip6@@*R3T&f3H9v6zGEj{o4Y4JrVkXK+g#Dj6i?r z2||CTKu-(wv_Su|K;KAI_R|7=mq6bo&>s-!7ZRc0DbP~_Jtfe8`w2py7wGK*y3KS>V#oi)&XAZlfXQ8XSR9XByzlGbXY!8U7#_3l>vhmG7Skcm z=KH?>@_W3u=T_8#+$%$SdtQ$nt#Eh9=V#?+8_;QQ&#lY6x91Qjl8yHE%)@07!e-~T zXy4aebG)}_6q(3;Xx|QfMH-U~$R~ccA?@2K*?l`B-~=Ib@t&?vSo@jCouuvRp{rEQ zO%W-u!--aDx_T0nz*fzCLQ2^N$rH-J{N#FHL^Y8`#PXOkNAs8`LFVy1dakMKYCKn- zU%fwpv=CfoKB^~>nP;d%GMl#Zz!qiaeN8{Ya`j|TMY>!u_H5?aGI(?mp8f@%8{8&s zS(MARN?SX2zm}~Fp5^QRFz3va-a(d!DLsQ+3a0eU2fGN2=D)m!=Gp3keAwzjSjOto zKSHb91tYtd)de!M)rDj>WgkPO=v|bu#c}QY2+P$o!u1vR_90_+BV5ay^YkyWZERt6 zwp@?P>MEkI+!6R6En&|N(O2FR^p(b1GHfl63%w-J$w4VgU<>adx8_j#W(E3SBJ_el zzkp4%4pz?v_*{q5cdI}jNrXNo&^H7+o$zqc4+`{bB6RAzot%5u1^T)`zd@j%NQ8bu zpsxw^HGzJuKp#tlepH~J7wG2&dYeEmB|^^%bb9ZBQx`pS`p}{DJqpieD5k~L6QS=H z=qmz!MWBCMpwA{k9}(!w0)1JaKPb@W6QS=B=;s9bIf1?`&`&2q9~9{H1{J54dzJ+H zS%JQg2>k|uPG3lH(a#F>Ul!m*Nep;ZP7U)L>`ng2ty9D~YK%W=rg93dy5&BMnJ}b~?1^TrD zeI*fkN}$&TdR?GjCD2zBp+8TcmjrrApwkztU8_5v2)$jPj|ucKf&MQ7eJv6C)dKy5 zKtCbS9}?*6iO|~wdRCxk1^Sl-`bHx3D+T(9Kpzq4pBLyC5~1%9=z{`%P@sQApnGt~ zV52=S=56YiGJ?Kbpl1YnMxdV-=sOajdjdTz(9;5aR-m^fLjQg+4`9ZXy9D|!fll8+ zaNB!(BJ>LaJtfdn0)3A_PbETsRG_yD^mc*XBhYsxLf;VRZ34Ybpg%{TrxT$+BG7jT z^c@2IDFQu{2z_0kdjg#rvJ+?aZD5AVwYtGX=no5Y`kJSM)pLPomUup)Z%v?&Btl;k z=os}&^nE?I-p>p4 zcM9}UBJ@>(zADgH1^TQ&uO~wPbAi4h&{qWdxImvxguWusmj(K=KtC+d=M$lSQJ|j_ z=;s9b4FdgiB6NDcjbmfIO9FjKpkFJ{7ZRaAAkfbW^s@r}DuI3`5&AiSz9`Ta1v^K1^T%} z=w}7`yg;89==TfsF0=*>AO9K54 zfqp&_`Wb;fCeX(O`fUPzEfM;A1^NkrenOzXPN1(RLSGQ*S%IDv==63t+ufvA0%sl@FmjZEg^b(`vIG)F``cL_*Qf#sMAIQw>upyaE+2625*?ArI zM_8_&HeN&Ae2ulYjaMEw=jpGvv3_X3ihJ>{kN4WL=jSHr6OcrPBB=bDlN<$}?Mro0rCMPt31as%-=lvjbWWGVUu zQ+TVSIv1HT=*Ph`2&_QD3MljM4r}90pqvE*;b^Qg#A8PNn(`@7c%?>D{tOhJ715M+ zPzLYjoSUr%z5-Qi3_9{$08dKoKV%8FWh%B}%MM;2ZeD7>zBnKxCOnyQ^DdisPuqu&G`x)9cyvfm6!dLf+8wBi{I zS<9P2Yw^q`4%W+ zPR@^lGU7=1Lr{2DU*~frDnjpVPMNYl3zRY2Qb>*$QDu3l5Y{U|fysv`uLXtJf;yeT z?YvW8cY`u$B~+GB(BD)DQvDiuD1s&Fpl5tkz(?OPhP%M(R=`t#S6E};0)@|I>vH`Q zQEUw&x%U_-?f4sDJsB-v!^!6wP)bhOUkVBmhElx(lrg8h(;HGxJE>j|%Bqv|G$?ch zrI-ihtd$TgE?=Jm#ahd$Vq?74EUK@0B6Da1pZ+>EK0V>pEf3}Re&kbkZ2mq__{|Jj z8=oZ}t9eSb3JUMRGa3VB)wa|6bgM~xryZ>S1kZv~t{1!v+CY!5C8QKD1BK@$bk0XW z@f-_pfYN3uQ@IK}87$nvdJ}kfrUI5gpF=xv)El(6L0Ipjd~CV!LT2^K1C$E+1pUsRf->*$JOs+R(>MJCr9ylel=QoxtUC36`Oi}R%mc69s!dnCcBfod zf#+%`pBI9{J4m(0UQYS^QrN=BKv{MqoFN{^1H6lPoEG;HP!?^Sl4PF+Wz3cf8biMW z{Wx0vL-1ssRDT7^4#&p+4wNP27ii-#Ph*I`iBAalSo4ocR^`F2qF%XB)Qc~DLu*Py+>2NYfv(mcNj3a<}p$^*n> zQ&pNp`rwK;YrW{{STq$li=wC)EJ}IE{`CCv{tz{w$@4J+?$Owpnz_=SJ|%J8iH8O4_mKX;9p<-vvt6wm8b?UgB}ACO} zVh#EEKL$@gQ5If7-{4sIL*Pj}SdUREr=&k|BedaI)ODcn{Fv6^5GeDGW!?(PhSTCs zf^yc{Gf8#|lr;VZmiacy$7+>$-Ve%{Q}+8nLFq#!JqJqGYJ;AxfU?WM`Wh(wZUj^B zpsYBy@voqeg(IP{@c#nEZMn~U1$=^2(wBg;45BY^B)kfgbB=`9fZ~o*ZUAKjL@f`#j7e{m_4J!q zQbwMez{6|(TEZMC3l__#5q-7hEhu@o6gBXaoZ7h?lnt9oc|Q+Yb@X!vJZp{}-UkY* zJ>;X#fkI+c*!(qV+9xd_vYoSU~St3N-)El#i7MnR(v>h2O)eOS)qS zb>Z;*Bq(dn*lH*7IPJ6-l(eJyQBdg8GNVr^R}1*cxFd5OJas4P{&`SJPR{p$a-HKL zKLpANt3yPLWg4+k>n5$~Qv4=()~q&2j<0}{b}0Wu6bI`uP_71Vpyy}oM!T?Bl+SZP zp*VqXG*&k#?YIljhe26&QXL0n$w9A!l5*<(9#GCWwR|5aD^{y!z~L?L3)ktV!Sg&D zYcgn#1!Spe$Jl;peOQsk)c8 zSd_kP7=HDxaFmh)WyF?(c)CGJ0VvS(5GYy4683{qN2<%fPycWt3Y2qB`)Yx*X5}Fs z`rf!}t7kwt@7VLlK;iWQo%82Fc?3TLtgnEw=y;@m2BqZW^LU>_Z2leIf zWI$PWa()#kgSH<;?Wiz!*3sc>!L#9{s(|varQqY9>YIrt9RKqR;8}L+>mE>6FAwYa zW1!F#j1bR(l5w>9bx>ApKB_lIxU4Y)*^Nu`sfrqjT%6jEe{oK|qf zK3KS;jc0;FJ5|sSOsZ=@X?MI<29y(5u!K~KL!gW~Jb6%3uL`%y+d;`#EQ~Z^Q}92I z#@+xPs3)YccZ0Iak$I8w`LQti5-5XC?R*K8(~g9H1%gU1X5zj7>E$ql17Ir|h?Y=Yr)yQf~&7 zWk=?FK*>7weugNH%=9JLWh*o6hg_yN;$Zzgc+NUle+J4Lge7^k%>N6N6Hd+>pty6M zKLF*t)4q0$KprRO=Yn$1TDa;xbJ70mI`FJH-fuT3tB%dT8kCeR7wP9#P!=7m+dyfv zG6O45vwU>zz&~BCH-hJc&8KPNu`x$K?*|VB$3e^e6s2*MhR(pl3ii=h((gpq#gw zC-lRVkAt2EW$;O13%?zd9acY->P?_{j!$?GC`(SH_X$u|9M854%6UiThd^0(DBl5P z&5_W1CCX*{kOo18(u{ttMXD0+o~$T{{qP?sj#j(Dv+mgHD?sra z9Ucc|!;$bdP|iBqxC4}{ojQFtC@BZ)UQh;|RG$Q8-J$#eC`)e-d&qBqvI`=iI!w8~ zLp)Bq_%ZlYic&O>UoFlkD|6&|E_hDcTAnb2ndLx-^ev*k9xv@!%Zrd|$+3h^P}-e( zzY!EN%Rs^tL_ygD$^Hc1C&L};~SNou~>wB4m>9;4^h4d%9vx%Ujya5)gcT4qjlJ`qxm)Pq;1(LpML{o z!RAw|QyO?J2mP{xz_K0y6S?(zvEj9;oT;SLzn3s~nsu=L8&aLK@=&fX2c>S&$*E)0_c z%!+@~qKKiIY<*vUv#eY_m8+BsS-?$UnXxgVzXEolw7^; zx8~|aZz@*>ZvppFM&I~kg#Vj88ZS^*!~>mJg^Y2QW*O{`F1dW@{XRlHxQ&6F#Je6CUOe7`l7D_61N zb%fY42#qrP)m*E5s)&wHJ=YrnF2)3AOs$r3O+TM+)nH{23H$=;n-*ND1U^k3kLR$z zK(J|3s#OZb*?hg_^ILudpVDJ4KUJtm)oUdyBw8dFX)%1bBbJ(rq0*$F%%O|{$nkRZ zKtz)jt+W{!)RroqtWKj>$`>)4S*vbZNb~VPuLG5}^ThDbkoh%AzqCu(!UqKHJK{H7 zFB0|@%01|cyW8Ww_aQX%X%a?q3ndxE&D6NikRK*DNX|+{t&gw9RXg=5++^RPv*;|AQm0GRK&bEd9`u)y;^mmJUQJ!%cu#1 z)5Xy&usWD-6k2nXC-7n2i!unxm~K z-PDx=jelkU;~(lWQ<2m=nIfP%b1je(SZljbJXOw9N9Q^b%}q-ZUZLECzN`2KI_ga` zs}VnC;+H493Jg>KuEIb`?@bSnV2EZf#O>3$Lf16bYz$c&CM_?Z?hP$hC^U*qzSCWr z&ZJVzVFQ!?J&i94)>@E+0r2@rguv)_3;{voB#ErxjcNM+zGDZ6kB%NX==&X+f$q*O z^BkU9+hmlZD{VNM^Q7>YGMl6NXa+oQ4ZJ!>sb8%0)FRdxKbqpZHWg>s%qo3IRM4q-att!XQqdpp80zX$8@bywRrBl6>->TsU*6Suo zdXp@kNH(h>R35}sE>v``dSeOuFUkpaFi8f3n4_WVf+-!nJ$+r8M1yp??N;DscM7GZ zwLo7D>is-+Q{rEDm*2{b8#v|L)DB=RbPds%x^0$fGk$Y=Vxm0j!yX_-5kHOVL;zks zS**;l?+os>^R)M*vD>H1jgw974bk4~HEJHg2Q#fx?DnRc<7M)Rp#~UjtTS+gwHeYy z{v-uYDv4U8FfCS7L_^kO5=S>|e|!#R(`-^lSuUVqk0U2#0QkY(N{Cv=wuU%zu0e(! zVl>%vBbQIm(25oiN@ckPC+CWpZ$CE;8_^c*pDZ@2#fo2OAew?fXvv95^{Y%!F;lLd z8!uPNtvOx%N^R0V<&mktVi7Uc8fA(xiBC9KAw;~g&+(LT#fe6oG6SRhBz4M#%0 z5r{?V(@r&gM72}_5r>jacWSI=4iQ=Tjv_I`>k7WE0hW|1C8XY_V9lfjtMb+%jbVfj z*94P50|sa`i_Wgza2CW}Zq~L;(cQ->rmLY^iWIlA$7W2UE>l?Th(h8Sqfq`Sl0&*D zV-%*=M*Sk~g%$Gm8m(%VvCWwm|flC7mf_CH_ar3v(8*2ZH>6UK`q8%R6Jbm_O^@9fj%2^+gj03&Q0V=GEQJWYwqfg*c(L?hNw5z(oOMWy z$djmMGo3oQnd7tJDsh?;9*b_3A|I-^Yslu375T_}{zl7({CL3t=oKiABc%i10%3VyZLDo>R2 zdJJyTX%F4PoJMm3L6%$8{!EXxO(n$Ud{)@z^!OBJs5a&7?-wA5xr{W}zJlef%@b#O z5W`h5g77J}!;mf7sq_!@_Q$%6h`;4*RDdBf$yj6Ja!|)fqaJi*p)lG$C36j)!W_zG zR?3z|HN;9$&3{C+JOIxgpG2vnqAN@!a>FSr3N?6xW3<|$@gYtl>5xm7w$nx|VJ?$c zFF|lpLsV+hB}6dc*G@+3bfDXMln^g$KDN{D9|*#aKm>m#hwY|~CL2dslISyHrHSs? zsIq?mp{J3YHt$UonznY>jLc)IN30>je)WS$xiaaVemXnk@|d*7GPOx@23+kJ3Aq)B z25!To*pw`>^Dvee!iW`xR2q!L$dI)bj6)z5EAykd2mM6I3dgKi${4`Y0*1P2VCn($ z+?yon@3l!(I1|#asRV(Nv5r7_8)gf)jbOYhQX@!j&Q%el7-#0^$0I!b{RrP&9&0$E zX5&^=e?Nw0nD0^P#-}SMEkHE)OqVq?^45*o7M?6^J&c>B(UOYN8q=7;=hA3pmTIkf z1xs0aDh~zJx(QQVlH>E;f(@iGYsLm+atO^n+cky=i=Cdf48}ssG=NTH0P4sT$`O5y zel|6YU^!$+`W}5DbY@2Ingq{9#v4u*z1LnL%t4b><-88Xl_)wdLk{z!mI@&;)U6|h zqKr2%$DPO2paxMiv%gnmuLxvEq37g23W^q)gDuu;7-P_5%}vgvg%K%EFsj)x6)Ms+ zlq#oc1~eB@p-G4WCbf!KCh|iRwH!nZg$8vh)pnBk-|11a zRIOJI2=Uz1W4(;^JzY)>K4Ipflx(=sf@8W0zl|ken4s?iL8)+>rt%_*BO(o?(fl=# zT4q*1^(Gxx_JQ<3zh;C$QMWqKiGZEw&h+@6??~0CtI#?GKaoRfexk=rYB0V+wIMV-{^t-XsZ8zF8~*MF;czBwwq~*~agy7Y&vWFvDAN4>7ufVS`%HVHgz%*eXHDZa2uV12%b>pcHBtQ2q36ggn&iL6+F{(zfc3Y#E>{< zPT08XX6Q*w;aSsi%4eWA1Ir;bY$~T?Km&b!U5F#WA1!f|Ej?f>Dy|YE>|L1Y3kq%G zV48iiEhqx)JOM zSwjGB6-SwA<}bu-RAUTcQ}uLW@DY=2D~)z`$0BX1)6Q-e#%bTtlAwnVi?n$SbYfH= z=9KLtnsq0fT3AV&wKh(L&QMAi)IZ9TFp^nf9eK z{nj<>DJ*pO9)6kSq>h2!?%r<80`HA63%oY5-X48mJ&R+X2e6`n1-c=xep9h! zZ=y2w_L*iLKchL&*N?egcDNU@`0l<=%er~BcVn8IGrUx9)QzP{?TtvUoLcu?;l^&B zs#PHqrI>jON~FkIF!ncC$||3VR8((oMmaUb?hY-Y+Ux0xr0q+?{G(jjN2=_waEqz^ zP%r25_V!|8m?hm*IYEgp(M|NDKv5txzAz9wZ#|IaCqX_aUqy^bS*ZfeqzV(Z}a)Myo3 z7k6V3lLm7Upx*u-n>yPls@dJbo?I(O)GXyWoU5DM_F-)&p66!TZ4xjd)qz}f8ao48 z(|A3~5xpMFLLO0DBp?^|tVAAV_4W!wg(6iP6z48FF{P(e!XY_p-NY@`{B(mBB{6|V zYxVVPt=T%Nyu>CBp*I8X!Xo1DP16Xx`952kYhrG!vL~2&X5rL`H=@)|3<^sKA);P` z(-`A*d!EQxVD#Y4L;FYf_{T>N?%NZsweId7Pc4QjhaP#_+ly&5f{%rXhzc)9R&C-< zYIxdYBYF09_lJWEryFF=Z#h3V&^rJ-rFNtCKL!zF6sQZrvp|>F$h$*s#_1QLd8c(@ zl|M3hvpbBi_73!CY-<<2CMlPSg7!iS;xIwp+*EEhavfO5U=I2lJXYnWX}cyiLWLII z^*)CIZ}P4s?-x)ciCP% zPGe5FslBtu6=j$PlJq!Q`tHai^gwSP-h39}>W8<8kotNfYg(9Y7TsiT9~^GbjVad_ zYO5Cud;5AK>mmbvJ<+8SkkHgz;re>|R6AFuuUra1`8rMZ*bi%o^zH>J@73!D17qc83itZ|pKJKa5?a4M(1Oeliq_s_udj)s5LC zs}GAroU++sY)+EkJsUNDvQitzhOq)#G5u#uAZaU%* z>!s<##e5ChmqFOe8)sukS=zItV+h`GOvR>BhxQ*wS6KM{KiC^xX%r_-3aw?ekDul% zO9=FFF5?(>D;~hzUfl7HdGtxxT8PstnhB0Ck28Xpno`1eh$!8AE~gqqAQ!#s3mf^c z6OK2OVe88gY${aS5&e3x+@0z38`D)amcU@FhGj66YX&=lsERtU0)b@^VGDK?mT0B1ja!$W#&z zS}Q_0Naq!&utiQy1ktZq^~;an32l%tW}-4qqcH5|F!J$I1KY_Ph~1sT45wZ@RylPVt$*I*ryoc7KZAs8~q?zK{R z{%G@Htx7gWn+r#)!#WIA3>LJA9+~#hQ}BQZ^hOSAaC$c+dOwZ$*4sY-qiwS!BHxMWb)uZA!Yz~bW|JR){O<(#lFH)LXTTHf5Mr3DQwcBh;3Okuf#NJwwwG|fO~cDPl!xr|dZxyrFB z_3$2|&SO>W01LLG+E=bX`34_4ISQ-01wAw=g%m=&o;W_>y+I*c(@^AmaHd1wL=>sk z8aU;VIaKu&VH~Xixk$f|Or5@At?|h%AEj{)`+x!Gczi!_7XhoPViQ=Drm^WnZEQ9A z&`B_9uz$onTQp5sA&b(t%DL_x;{7t zCJhxT7X-|dMkeL#3IUQh% z8c;{-ESt6sN7ec@X5?%zkAOLYCKm3RFiJD1s8Q@fYX%61XoqcWf`r1PAZ&^@nb5Jc zu*F&JHLK=b65e6Gz;b|A97*WfxIZynWi!AGk2(Pr&7TIp4J>V|K09|CjpU}sn@Y_- zN7M8SJI!14&QvxFt(85%Y!!#mLC}N(_ff8>;j=78ms@)>PVR=6I;nmifN4l-7-VHD zTiJpPRL$x0bp{%{Gbi;iUoKObItf*N;yz5wJH&z>cq`TEt`Q!5KSnOo^?hhot2~Js(G0+mT)pqzK>3*!p@7Gb)kQdC-(iYsNUOBfoH)AwIQq2zOHRI?; zFdi5>&RD13q-fmJ7)Rilc86+Fr1S;wy3@#Qrs9ivbIy0>2 zV|PJp4YBexBk}QhUQP@%RC9Tzo?%=^%lVT!+U3-iSDqWyrhaid(4w3790rBfUW9R2 zb==kJL~5F5MD6RdwH=)sMfu=`vDGwiznrP+QKHqVb4FofJ4dAi8AHHyiw#jHTb(P` zFleFlHY$Ci-XWm>ju_nm6y()hX0_AM{VXH3Bw@ zNqL%sH{*OG1$*rRkl!YNu%~~ zXh{c@L1Uj{-e#rqrBGbGlttg73J#$z^~M(TFNiO^O(Q>P-CDu=ET=UZ1Ehyfh{1-A zI=z@Vx~RGI+hez~YageODZW-~Gpbk3;wU5qoS5FlLdosZn3o_=N2)>I>ZR=Z4z+@T zCVRxAA%6^0(X$rTAoyK1rm5%a+}bJIVPzpIdLau@k-OWZ97Sk!^J*J?qk0d#=h)nt zw^X}Pghn}1oXXWpI2WgF5$EiwHzos7Lsd*g;B;`zxFTloLowyZvE9`7>26-PZpxT? zB3%M_=JLcG{!ji{k8fBhL48MGh!76qEId8nX%LE8m5SC@O~9NisctsY+_g^g4$*QDz>#(J2u{W#xHfY& z^}LEgSP7fXJd)VfB6Q3Q;U?&GuGZ!Y@du&IVahlsmU z%}IGb+MP~dXx?fHKrJfklfhfTP!cnIw62jnn&`Hou?i(r>kQDS8az5-i=X9j$Tyw$D4O6(L!0ko=$lQuT>Th`7vb1s ze!xnInaUYDLaSdC9;~k=N8%9Jkr(lFIud5F?FFMPp2Ta1vgr~DqRhxsdq59O* z0r2bYi zLNb_3FcX0pi15H2p`Kn&(kn*cm7#Kz_xX|_#^%B!O@O#Pg@?1zI5Lfie%f_4i+L0z z2GjzC20*M?iD;k_}K2GdC* zqc7QD#muYJJ|}c=Yh0{rmOwEcLlO=b_CHciv_W*a25eMjq9WF^rfpZj;(I z1u=FaOb&CAS7cf$n7?ut-a*oXf2z}bK2I)2GNxBG&|G^ZH%XI$I&UD+8{G^L z35i!V>br1E7wvgqQLr7J0nq%|K%zD<;*B0Bo2`>rm_SDH(V7lKxkoIG;=MK${Zlt^ zBs?)6XP>MC?Y7h?B4}oIGRd8DC6hBnoZNC@BQh|6oSRNk>Ss~a8x(UKLf=J=Jvzuy zZY=5v(JpmioC&_oB6tnNua`AKP;h|RM15!8JgaXIIjI*BaoDHcT&v3-8aCH`XF`Y- zug2Q+_9>HktATv{oUImOvoSUqft`A{F!8BYSN2Raa02mk;8 literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util.exe b/hardware/esl_blaster/FW01/dfu-util-0.9-win64/dfu-util.exe new file mode 100644 index 0000000000000000000000000000000000000000..fff0d39420fac66f0ef8a60ba75969350922b400 GIT binary patch literal 290852 zcmeFad3+RA*7)5WXb4NJs6^rtZ8VGt0ww|u0itQ>U`3ln0*Z=C$O0K5!K9l-9SnB2 zQkIR3<2X7xqvJT6&OFZeIBYVSgeBk_gA3w@sAIK(8N?A0m;Qavt?JIA&hz~Kdf(6c zdHVx(w{y-t_uO;OJ$I?fv@6%S`nX)KzWh%lT&|6T@+(o#|NLm8__#ARALn{KiK8U%p%Mbq!M}9@id!nNqSr) ze`u6@T5EpfXn5z0RPN%+6~c?;aGyzhWr zbE4ZdUIhI;ztO?!6+z0z|CoocC~c=5-GB34Gv|-4st8t)X$h@${1@IL{O|TFam{ZY z-QWODpx`0?OSp#r-G0E8j9zNPsW$GTQ0i>$21K;PRZuc|g$=hy>N~`Lf!oRdZa)RL zps`W1<_(mmTOQx~H3@&UPQ4=QOyH!=FZKk5Ui0WFvt~=~B6)a$lWu-T5?#L%S4s2e z;9^y;f};-<+`cXtiP>^#Y^Wrz`j$Rc?bzQNuAuqcv3A}=9>SRpoYfmHbMm=`MJlsj zH8At}U&H@@eh1u`LX|nFfS{d5oJTlY8q@VFaY1kFIF<2d0nen91@6}GfE)Ki1($g; z!A#&zA>7y-u4MALKa>hxu6GCVSPC3t$<@&tj(W%2{9X4K%A0_Dg7BU1fGZM)s8af? z1Z6mZa2@d7e$tL^$^Sq4|6&Pj)z0vvw4=2%Y$KwF59H~l$FtStD(q-;q0BCl{Ya(~ z1G*=kZ|zp{cr&C{kDqpBa0N)erpUf(xtXyAx;9io2 z&6_d^^w@0BjMqQaAJfg^JY?rLwNhFW-Gb1ob+hkqF$21pa}(0j&86vu2LtBtm(tv> z&g1o>9a>~8aGPXO@g-i-4eOAu{dJ5UZ4T|%&2e+VDLiQQ3m`b5L-`V*=jne!`N9g#@Q@ZpY(3=N2Xp|k&4bP?{BF_Hw zaqy%g{@i))jWV}s(NB09o~Le-(&4WhaJfoji*w!6Di4;meAp*o#I5Ek@}eK;#&$a8 zF#xo+SD~zhZ|dgYcdf~k>anG6-T1`1N8*P6ZCW|x-7;$l60~rsoJref2icuB)!O_G;fe-_={YK7mz6Y4l)QKhX&-`Vs*2A7kvcKJiu( z4t?Y0MAl0Qmn(k0RU)xY238&etK{4E??WLDUw|I-@rZW8uj}!fqZ=P~mye{W)2oMzn^u7y zEI`YDe!FP-7vCUQl;~V6z)#7clM`77oXi1$%>*IQPGl&E@aDZb{^Js2G0#27yYp?~ z)UL0Kg>qGynNx*`61%~@3d(_)KHs--4^%cQ`CPQXDLmaw7FHs4yKqFZur`(~`~WPw zFoVKP@PPghL!M%K!UqblBPWp_%nm&BzCJA zpl|d@aD;C9bMub zpI>GiwSEn0$(%WVlMF=5AiasX0evF|)?9@Js9=En2ar2=+VmCs<9!>&eSvx5TQ{Dw zemNh^iSu&vH2)458h_O_TWuNpF85uQvbo^{I)m4ENw0ji)OfMXc;0VBavzeKLzq{D ze*vRLH+Gb28xB~H3dvZ;bh3OK-2fGKSkuoXuhPaTE!-v6ethTH!VaI&!l?HfpZMKh zT30};wCF4C&SsDTh-*A#`U~aC-PT|z__Yl$XzMQ@s+%*$ml~FC1arN|Fys9YweDg$u5m1Ho~Z@)cCqgE8V88FQ->78IJ;NS5tXu?0UDQ=S#O}Ytk5V z(<)!}yZ<%K{faZ6>&9W-c*FXw0$DLaTkp@+CwYR4CJhW$nSoq?bXV}LMAi?!gaaG$ zMg_U@HKewbToFvh@9#-U&6|>1`87SIR!Mr(#S~k$#25?_;<)-Z<(6Q5Wd-Js`HMwk z$3ji7e0^GFv-PWyE?3b_xszzmi`t!R5F}D9WU#m4s|XEiVV>PUQv_8hDtG8-wh~

m_r#=c4_Maxg}QT z2s@_xwe^d0OUjHL)=@;Ft)HE%Q}Oev;^u&iiBjg^kylf*Eyw$CZMte&b`Q{nG}Uqg z(s^0ZzcLO6jD7JjOd^!mL(O_`Ub61`WZl~OdATJFbnD06s=m~&+8&Pd>0iN9Lt<`^ zAwkD&_`>P9j=Pf`mqi0@llu$Mx~u!6q&qi&wOV2MHo}A&BMKZQebn2zlSnoZI~&oAgv?l1ZKcvZN1f)qn`++BRP&y? zs%P__Bi#*snz5TY!$$`^H2@TC`W~ZwYHV;He}1#S2oCpZfjxoBt=83G8GGy+8I@iB zNssZr`oJEBT+tooQ3k?a6LONxI8=^M`5-L|^MGNS=Q`DZw3zmeTw+L#b6;f2pUaU5nlWka?+B z=slz=Da*DR=rOSp$0*a*+uTj+uSG)rT&_v!+O2;eOj2xG+1I5-W=d5wU_KOjAz|f+-!M@Rsl@E|nEgTJv zcC6@I)EY98-w?$jP00ZJ@_{0>>(Mcvax_H@(wlnh?%cmnsr7^NZQ(B=Q(Iq}9>LOl zCRNd!?Er`^*2VMC^-Xi8Uow5h<nM6H->bJI+ZZqkLn%kqSm73sKq7%WF^^tO@`3dQ9Oe{@vO z|03L?x5WFXHJsi3$##|*{X`>n0_D zb}WOE1j~Y^V`)C^?(L$5!An*5g+O67@g^k96VSZ$qE;=Mp)x(UN~W5#e?kT{Yz_Pu zG~+ju)6L!}g{<*~Zyq>!<1Wl>=;5Yg?$9seCjmzNFgXBXI(r$>4p9&UXI*}otsoCV z4**>Ohz4oV&7j5G6mApEKx^*EZAUA$_3ge*G7IVkvMn=qN<)=CP8g$z-FcN@`g!QF zEw<7-5Ghpgh>e@5zrTa>m9*zW9$oFR&Y=u@vDhs=a6IN?F@_`h*)iy@-X`X>$7F_R zmW#GsOQ#g?JB(>(_Rl(FoiNTC#Q4N#?6D5bvGbF@<{r|iewy_ql%?edsG{@!WWH_T z>KO6?vm$d^^aCwYp%Q;m7PIgm_NjxJ+Hd;v(pj3Xnp2p-U>&cUzD%VyZFxoW^3qpb zK%=Mi>6_~_OM2KVpE=W8X6o6~49hxtR9Rl*RyeRHRY!?B|0*Ulyu)2|Xcc==zDzy5 zJ+sW%R^~nsx;5INMP5|1Y%gPUU!inJ=*r~Ok?bkoCf6`Dcq4Y)wYiB0CVRYWxeyk} zY)9xNP!=f9dIB;@RAa04m{5IFGv50`bS5YGi8IIkG_`8G094zBxO{fcId&mw;f8K; z?XXQte;IbE94T;V8|-uq`C`iPD3(FodavBZZX(adk{EO(P*@U4V#VhQgRzVo1@(7= z8q2s(;=i!tk4b#3BI(avN?|J*whdT{4Oj|6o=Iv}6_AA;HOAe!+o>e}C0#}9mmP9i z{~E~ldLe^iyY*Lq(%pfoC2g-4>WTGQFQ~n=@BvnY=@8Ik^JE|GMV+O}$E-l2%|@HH z_FhWF*`(wXJvMIB2ejbdvXYBsRZ%~VXfq`~yv=)NF?bU0;MK8pYB;b{h{Q3VfesY)~>SN4X{mBV4Wxph{E`G z-0@rgu@10VA6(DTjFLI<+3pV;AYaAA=wBbe$#V z1orXL8Acf%z^j!Ze(jriBGU81dT97-=;brP%Y^5b}1 zasrPjnR+ZIB)cg_Rqk9&vKLKWN?K?2IFlaSErwRP60Ag68qdou@EZuhk9;cfplwsvYP_f_qf$l!H)OgRA|AyZ7>=BO>{X$hUYi0OMmtGyY#(p%Rru@ z>v^5oUHu>SgaBehZuJ0(?-w}$*rW-;g{nRgb&HS{cZO|o#vfgbzQ^@g@ujy@kiSv9mz(`r>j5g2Luh~1~QfKGwGBP?Nsr5Ig0|Ul; zP)``WP=~j9p6)^&5D%aN>x98{7!1V5_K7bLr3fDzv}q7*LSjd65@)t~mUodD7$2Yz z)P9@V*!5krmDQFSvTs=TO@r*jU~XP$f#I1ATEO@;{<<3Q&ux^>i2p_W}mN1~U=?+=P0P1dr_mj5O#u9XM++PJt^zD=s)*fq{V7=D4Gr2#Z z>;nU7r?#PkAv&HhR1m;l%)|BFB@^hH6Q$2fhWgau=jLC-C&gZ?afCA8J67~Z%h{BY zh3SQgPtIXZ|B1~fl|QuxU15vsl3whNNwHf*3@wj9+2#7b;0Kj-Z63x$@$-KExA}QI zE+T@TRqImxlso)973e9x-;lP&_eWwWetL`_rc=*E@cl-cZoFXZR*p4!W5{D#lH^>H z=aQ88eBz^>_#zgXFdR*25tsrxO^ZBDMmW(&i#~?i$J|_SmzrRWJ%JdBHS=-{TdZ`o zjTv9#&pprB)6$vUVr5b=mh>2_9qo`6?Nrc(7D`*ij*mI&qu&uX$IY}@uAanp;#JfV zoL_i^%_zOE7JXDejr|NdD|V8S+E#7NmBQVTV5S3ez2Yq`cr7a~zt1dX?g{=48=QtN zSwFl4_nmw^?%x_O`x37~KlG5=FId{;zN(#n-0v&kCOke(yYuhVE6p6XnWefbK19Zw zkO?2F3OxYrHOLB;^KT@yp1T;3n*mWfXu*edGx*g^bnMNK?0(C-QzYw*g?|FveJs32 z+V0G^i0Nj=!4637(}*Lm2!6EdNXcNj013IwnK;*;|NgCT>Ard5=X;IUhP@+v`iybK z)##Ywwnm0xEaQV)rTxO&dGMy7RHwzKQZ5_b88-ldS^xZi9=0qE?4EvJ`~8*nFr=ri6ZGqBn0!C8-$Nds-!Jo67nHYatX z-T^@TU1dnd{Yn7DB>XvQS1v3EbdQ3{nUe(gDn;n1 zwMYO$0Ce*Q9RE*e3E?-IeX?|P1+>yuF)!MNb~zguzyb+JaJ#lfPMc)clH-r!pMHqk zverqn$2T4G1kZ0eHZWM&bgX|c;Ot$#jAat_zf1ZskUN$Qf|nDoClNv~sr9NLoQet+ zxI$;Lm9I<{Ze7>>5X<;AZM5d;R3|&D>m@avlypIX^;VW08!w$vAX}0j53xH#P7Q9Q z^~s)~Q>@d$Q=4s_KSNauXo6^E#!zV5UbGipZ7=#nK)b8#S)^^1%_j!-VcgEdZr?^2 zP{;}mVt=L1&gP`O?6Dt*pB<2MlNUHZL9(TAI|*eH57XElWOw8f>%ixn#uvZ#l5L7! zgtp)GJV#QF*rU5iQ^gPAmyOPu7pc^AQpppR!XwtlFr-(u`P6j-F>`sHrCsyCbJk+1 zvzBkHgJ`b5=u7QR8sjSZTwD8=v_`qTv5e1XiC+1dbuSe0g^Z)6u?jXyt^7lx9h~qM zZPjM%(KhV1E@RDOAG|y$R_ooVVuR&0L^A~5TLF|+0h^^Rb!nRO*G*Nw zjLETJTB3}FotbgV3$VCbPVU+%2(U4{htN1|RScv~F~5IdzCy5lwaD*?(Y({(IjLbB zXq6UzU`3D^S|<86o|UzbB3fV^&EG@FMBqt#2ngbf?5UPmi32DZdgt|ae{i5wV$MPC zY;a&+{IS64V#oVZrPxmlpx@YURnti1Z|n^)M$%aX2aIESpSu<7cJClh$~Zn8!G=np z&rP}G^RX&i?TBs>vh4DX^-p|6F{;HziXk&ImOoD=d#yzSNJ+!zk!{W#e5948%bho0 zZ0sbM7;6S|XT}DfUc^=u?Icy8P5V5&pZQ5<1v6tPbaZo6=7XZ0T67edv5}{nCFw

8QWMC&GQ+r`i*_V_7v?5o&^84l;J5?>_EmfVENsh zMQ<Fr$s=ubdJ|Cv!3QBM@XIs`}I49Ei1l>92S0rSGdy;v#5`%OS zkaASI92&BVyKP06cfsN3=X=bI2d;(~&5f5L6rA2I@1pWD!|h&;%+xs8W4%O0-B(x} zNZaG!@5JQ#NKQoXu+>@TP^XQ@j)P_0EvUOY#k;LYg6JvIhpeDo{+pCNwr>w{gzq!w zX8O*Vo6Y|rc#Aa01!;9g`ikFp)^EHdlkWi^d6mm$Mo2fxlMGY&RTAo2}o6!pNJnOR(v8Y;PK1}K{ zdtZ!QWW2us461QGQ^yNlDr30>B?%ygyM&uq@vjN2Cn12_lRMM5=>#xfPkFSgGla>0 z(16Kk81llxgMeu3@6P=dA%t#&g0_B3?n5M5OmE2*1K+YQ-QC{uQKsKG<~}N!zoxY1 zqipw4xb|~o?UO1wX$Kj-9z#k<-w%|K{skeW^C(r6B<}(8TJ~qU+a>W!mB@CtT1PLW zleG0yvwcNv!NDM12$HpzT*l5M48_{>fmI%TXO8mqq;ZA2tona(uWpB%HRL4iPH8r{ z5pXfCkAN-PKqbCS=`_Zchjjr6awL1bctx@qD9qF1*|`nk&n#1%`e0GAf_`_qDr;)FWd+`@of_ohAOGnSKW`)6ms ztUdcR0@Z!)43oBZISpc9&vLM{t^hkZ<5u^=nnt?wR-ki}b$z@lS(n@_w(IKO3u`E8 z+dkzG1N$F)g&E&QVNV!UXtd{>A7flERhBQORl$&{rE17d)$rS5WyUxP9QO->6AS4E zPWYzJw_1M^fY;(Hpw(l4)4q@7ofhRX&2wt|E0`WIc3F=c6m!c~;g>Rkm0M+OXCy?X z( z5!nEZn$@fFIQ)#r(BLkQ*vL1mwVWt$-e+cH0BRKoE9B}p8m8ytZB*1O-qrzPOzu)N z3d-HQEy=p_Q)tL7DKEOT6>s=&0?tHKh2WRGA##JyM^Zw)EG5*Lu-#on=99L&t%jIA z-#KhYe*;#E?TZxKaoKb9ZNy5l123GcW3*D$PpHazej>TMtQ-hQ|KmbQ|K|YPz5h?R zf&LFV{qMk>*9)cra`Blq%nf?hD|1!klTbAy6`k2g|H&IjDq)T?2udy|)_v~Ock zFM=-!!8e)po&9IoD|vBKHc-~1;s%;0aypwyk`CkKr<}Ektiq3DPc@`n5- zyi^YNLjTqcU#4;cWY0OZf8DQJRtc)eF>%rH%RLh>?YoTQz%o#Gh5lLC?A(9Tjh$O- zx~)&0{opGAdo$$e9L7ed)igmkWDDBf^gbY=s7HLE6d2ES{*? zfX({c=0>RID=xIPQ-lYn!a(d#xxaTRhVY-9T1uprCMPl1rpLyG5Tz*VE{F!$sAos9 zO6~!^5n%V;YwaA*YUXI#s<2*pw`xv!ySudTi0^~``)6vTNC?h)|Ez%Xwhe+l%v)a z>h!b-nzr40dWZESyhv_x^ZfzR7(}P4GhE<@rYEwhUsd#%I;i3q-XNG+0acL1zJ|Q` z7q+t-p;FA+)73m%9#MTU1Zu%2SQ>}l>)#nt>ysYk13TB1G<|bP@ME6Sg4=jbw#$Ru zala{dzGA=irf%$i_QRg+zfC%>Gmw-1sPflrBC0;--oL<*pHMmxUt2VWMH)*Cq+%cL z`?bfLS-7ybvktbyF|Tn21T zwn1E3c4pX!a9RV&51}LbP1@rv6nL%Z`BZB+S$o_Tf!iJ|O%q3I(IfcUa&QnY#$VvL z!14gEhmX2LTB){vY_6~An{&0OT!N5(Sfu*lQFyec{rEIvpLHD=-4&^vbo`$}7dL07 zHIk$d&K1INvQcESdYeVi!-cV-zZoY`IsfW_rYuU1tW4H*$V!un$V}?o$G~!n>6OxI#95Fkiu8<#auSM?TJy=03}QvJJOEZF*$wUj>!Yi zsNHRo`$_}kyh7nCesHLVCb^a7${IlR{VrCI;iLV6a!|p^=vMJ{OV*so6&ZJEoFt|g zFH11F<-JUf)CN2&JAb|b&l=@@CELHIJYB-lHRS^w3T;#RdZ6C9Pu+jl6}Q4sH+cyM zI5&j%LadU*4A(RgE*UO8lq?ru-)v-ekGo|Pyk z)3I&u0K2|d`nq1}%3kROz0&h~rLXFh?p;2&SNXNQ(${oP;|TQdZ{asYdH4(MW>(ss z3^DMPyL7Yf&QAd>afyF0KP5n=?RWs9c}P$ljwL0T>SeAR3{{FZlZlIE%Nkh$$+_xG znO#rCh;Z$$f<5WEX`$0F4zqDtjsqc($odtVc?`Y);-9asdLAT027AV7FljGQ&Jtx1 zjj-Aads>2hq;3E6AH=X9k1OnNyN!>pkexjM);a*a*A;aF@Ss?fdF8S8F?JhV-e_f`Cs^Q% zl`*e0Pm2Z8-85oHQ*wP^ym20_Y<9PFVq|vt#+! zF9#QitW(%u<;}J0&V?T{=Xu#0G`6c*Vwkjs1)c2GyhX9fJkiNicg2oc+noI5?C~ek zw$403Y~8wU?_%)6Nr&$#e2K)<@_0rbHOBQL(f=A_<>)pao7+s>#w%^UY>CzQjZ5?V z#&*IhMzr}(lRR8FO&BoC(ye?d(9J&1xxo(EpHV9|b6kHK!ID(o*YOkG>}tZ$kdXaT zI*T{OUmXpuYyqt6OT?Ix4!C&Z)TqD4Lg22z!mWU3(rJ-yE*={8NP2}rX%)7@&*EYIWw)b!kLh;PE3ICf$`WeN)) z)3mkU5b?>ofT}XRvXxGL4`-CqEcc<<@i^_&o)2j42TJ&yW+WP65w*E2#__cE;kd`^ug|Di&~BHTrFCu5T^EL^TyzQ$kcxBcCKSSk8@UIOv&?`X{>RB8iODo zv(8bRRWV9xST!h|(2N_iwY8@*C7G9G7QLk1c@U{Xf-4=D^;Mfekl?ar4G zA=?Adw+X{v1D^pG3^}F!>Rmad9kPxpgI~2;TJvWFFRz%0{3$503)-|bqv&3BtioU# zp>nn8E}#OH|1xgOl(UwbMnYZ`tKCs7MxM?l@h`;9jTJw?ObsSHQ@OBqF@>_vl(aOHopeS%lZ!o- zO%am9qvh!ZoJBhRH|jT9<7=P}TOMkC8dNmhXRxC>vmg5JA0Su!N^sOl`uhg7o8_mq z>^sgkpt*-w){KCYto?W~*v&B{SmX<5S%*TzmBHL&Jtjb8W-Oo;HhX8L*sF00lWkc> z+P0cENlZ+O)p3DzX3j*aQ8V`Ysb&sM(K%h{?CxBj$eL|)Bkv`#C)baZZnP<;u1Ya= z)H(@x-8@z04}`BIv)_Ogzm9H8WDT+j%~OPO{=P#9@m?UUJ0V5rko5w^imR{4v|D#- zimNrMFrK66Jp~2CG}xxMq#M1~V3L7D>b)FA@8>CcG8@>PIo_tH?lPJ=BOswbUrq^@ ziNFEPut6WDrxRHvcGW+@S4Jj>w@XuOnOu~r`lywrIGbo*m8ryXNvf4!$a%^KAjdC- z99{7jD5#nfDJCbTYW^vJQkd-0-;lQVcmJsB&uMV5vnD$=U>U5a!ipcpiKBuUNsw{2M?l8t{<9Y_7^%=;vP2Em1dT_Jo zgcf}bu>~rpV5u+3G(IWKZwd67lI}m}l5A@*=ZJEU^GhJOyE)poX)rOPm76hnb9m%W zZ|0 zcDBS%p!H|r=CoJ?5uIO1Ddxx?ZnTihZHZ^LSlJ>ZC5E%D6{-qa7XN{CUzXLXhIG+z zHLiX^DmkwHwUoFrfJd!IRk3Yrrl!W*9_udhWuzqs$_=D#+t);li*o+%{;$2?Yx+3y zd@g(x59@Ix7e30{PwZvLYAAX;Arn3e*hbj~j%9p8W!49|qCe%MNuPyMTd&yZk)+R- z^fo&^g7i6(e$q~(BN?M5{RnBZT;4Y=kmS!)GS?}!XM=bXnRc|>{U7sqfTX=v1;zH2 zPnGwhM)Ia9I;R2hs3b2CkPDG%*ZSJLo_%Yf@e2XS0YH2r()&oul#TConVPa&t;AWN z%ORG%S0hipm@zXaxU#UB$mK(VO9`4!3TZW~k6qW_r@pbk*A!aFef;#$n40jhKA};( z%yGT=lGUf&%wGLP`hd{eHLE|~mIk_e zd1noNpR&_jhu^v`c1!%fXioU3rrp!b)@l649_+143}3+R={mw$PB_^K&vU{vo$v%F zOmo7+PuqC=ov_0RTb=L;Cw$lm?{dOhoUp+O7dYW8C!Fkr=Q-h-Dopw>vR-2|kQI7{ z@gyB`he!JSD3|IPR>5WJaMU`RegI&R09+>kW=0ip1!G+)8LZa5GR$Pt+TL_2S2%JJ zofCqo3W-bi+$K6xsEi{+(I(?$$%x=Q=+1FHmj^t4Sp^wyBr;LJf~&geAKy=~E<)zw zgx)PZ@VUHpndiJ7FZ*eEpudV0cfRwH!zT<(&o;@3$(cz>x^86sO_H2hy>H`otw){n z7jxVgaTeuc5eZ{!FrRDhni{#rp2UzH;ZAqx2r7H0@S%L|cok8xPrUP!W^9d>vkaf~ z8ZBrKebU+5Z9XwQ&;C)yb+DhkU()7TPg;Ds&WPx@o)})JI!F@y*nhDj&NFqtzJ$s0 zPHDx)^B#V8)P4AWVsE_=V$HslMf~R+A?5s7Ai~>9>^)OXa`YHolE}*XI};Q)ScvZ3 z!u-?bggX*hX%q=m0juP!41pU{MdGlomSgfwwm{)Wdg1H3@r_>iPkq=9z381F9eYUs zyj?fOeTmCJr}phtaZ=y(jn7~0?WlPL!96|3VVrLvr0z@2p##(xE0(ftf{3601J*R_ z9(bg^8xWNoOvdKy5#7kTO|s=?e2W(OjWj$~x=*AqUZlW8sGD>4*k3g$pvY2+$v(;o zXe!-JWKC0qJ=Z{30LQ&eQJZJXpIxp2eO=9Mo>9c4b7;|dL{X$uRr^X05%t>9qlv8J zgiI{sjG!<(j6@>q#;5Svgos+Ee@)6-cZN_X&4$=PVIfwEDtc}qs?L#B4~za{wSv5R z8a&b78WQbJ*-z^!{DrRk)cY!)N){MgHVWbzr@=5Qq2P(wuV6_En5|st|C}$xM~#g; zEJ4wy!FSnXK#1H&YiCP8ovhHo?l@K%HFj=t&JTO*BmB-q6x;sI_tVvlDwcCOL8|DyU-rjh zIflgVOrEdCa^j@pH#zoz^1n)YaaVe!q~~>||0QYlG6fp&=KDRzyWZ>kRnpxJf|3tc zYyEPx^qd^+%$3&><_D1fBHI#gqA@7veyZucl6m?xin#BQXWgxUkcqLEV|Ocy0&5?S z-u_Cr{jRxs<)}{{g@DxiTEJ+NZ&Q3qr=SmSlh0mexEX_sNNMIVQlG~Tcd4FXq&^ENH=zR-y+UgFaEcu^T2LFhBefM%Idn(1pRr4arK zGH^9H^d0QmSRmkR*vLEt47GZ$6xPf@UV0+y!HtS=Fvwo9KQ^;Dy#E=#%4GEo@B1>C zTV})qeKJM@?b}!)WT43Lp)!-#fQVM-g+2W#=dLY#9lU%a$J?BY*dHT`SDZ>)55_0Z zqlv5sHb5bkaqxO^>aA87Z+m zl+PeyLT{2Fe;YOqH2I0@criogkQO7J&vbgU|Ejxq4qEjCzjrd_!wV|;(m+|LfWl-kPDOM)gm{lNQoA`hDcd{Gw%uo zjDN9JtoLy{?@St{?baMw1lm~D;Y>v!$Kw_Qjh((UA5e|v9I(7_jEAAw7-vA+7XilY|*C; zZ^eIzh{DIxL$%ua<7si3(NVVgSrJ^MqfFB~^!(O~V|~-?Lq_!i71%Stj(BBFT)AL^?%~^2*{ELF0|Z=>+U-iYDCl zCiN7CqeNQx%$_P9m?C9 zJ--?wC4cGaef|pKRvqbFD5yXhtUDisvNSZt(*&4YxW?#rHK{ayXptJq9 zANWl&ssgd$M;N|ba53KH;}e^_ z@VwzjTN=-xlq>A>-f*qxzURyvCICPmCeS%9*Paoj=)n+}^o*-I2+CvDjzR%D8;r zWS!DyEmBQf=`>$ZA)3_d3mj5GT@5q&B7&pW@iD~lkCK%RaUer?cGJqli3ofkfL;E7 zH=TS>N)PnZ$QLAUPbyE1%}wN4+t{*-KSM#%kT_xTe34EbraJjeHdvSk|BbfE%gkeV zPhinsB&+y6O4gZ!X zGo+SS#v%!f9G?oNWG1reDOQ7DUBOf;)A@j1ztUIJlLM^r993%$T+&~F+{u(BvUdL$ zL`}~DN0m-7GmCbI26bLy9?xfR@^Len=IpzGp!@@+m2p)oVly72_X z>lOw1B9NW0=;lnyT3Bx1N^a*{sqrLULF5*&8#ub@6FScHECE0~h+mS~WhRi9>6zse zVVk+7>L6$dpzcO<#T*XJ~iVs-<+z>ItxOiug}rb5K#%*WFU3(K@WnUcGWM zZEMvwOoq34Y4A3g53dGW!xp^tZQ=tHTk|@(^RqRN&q4&(C*3h|n60-oHAnDX#GY>C z)qS8mz6|P7?63lVmTfxuU@w=Zcgg_UN-M43Gp?!VKv`wUBp3?hx0La%FHY$C@hBOB zCld3!vV+fuKZcPZcOj(qJjWi2tO7+X+$(5Eml>ky<%ZKzvf`dfvYO=l#$G~KmR|%W z`$<{Vi$wKpX))ozS8~0Fe9~?9ERm14!JjEt9@LWE!KZ!0!Kb$GX`g&wC)qx`WxCU{ zU3SYlobG2|W@p}!lC!;-C0x-nb!jm@uha8Zx7Kv^|97g}4(hbx2a$$~C=A`kHA2tKAO)m`23kK#cloAV#KtFUKx+4kf+`YSWlU&{F8Z8b}B zKW}fb&T#5P%Dwr^`CE;WHzxwLabiz>dc(Rr#o#5A0`51=)$17WaQvpW;Zjt4_VLMK z_iSp|&3+b*q9(t2G5WNVEB)xx#pu&c(Wh3%UPtKtZat9Hr+|A;=)}%{U@YwR`DCz! zn}?V>%cM|$+!y+>jn&i5ANoyw@H97fer?6K?a8Gx^j92dS zef|~iz;T28FjqqJcS@S;39GK*-BX|Ona}<2ve;=aJNhrLDSy1`{D9e~aFvKni6&~Bs9lcI|qxrvW~Bm!2U+-*J^9w z&EOF0F;ytJhh)_~k^<}JDld6pvx_X*n^Iqa?Qvh7yMdfH3b zmvD12k7>pZd5QB6ME$0HkC_b_=Jz<)mWWN_yCC3N9}fgkrhj&$w8%E`1C2IR!>#B4 zOJz3M0m&}H4Cn-L|DrtuS)onsj%Es(7ni`T$LVk_G` zzW`8v8!zO6sP$y$tJjiIviJy^D*B{+h@$dCT68HnW=VF@6#K@U=7%9W3Y6*YG&3d((sAr;9MU5T~q{7X__Mdn9wOXPM4gNSo)Kvk3Sl5yGQ(ljEkVwdnIyZ-1KQY+^`1JAS$oF+6_+EPfwJS@=Xd ziLf2VPTSpT427H14A1R==#`9-fH|o(U=&{f+wmE~Cy<8cI*OII8{di0g}mV@7pkHg zwm;TuypEs7>HG`o9;W@$qzp|Ns#@f&G#Q{7L&2B3X^|61hl@MU#M#p#CzCL<+U^tC zXwgBWq`5NIwe_w^qqvep78?I|z}42*BcvytqeUJd3|r^?;cG2&Jke+eK4=g!@(T`W z^V|Uf%rXXUbz*+=Pbp&|YT*linC1(A;Evxy0{_z^FCFu)Aa<5*x_Mw}QTc+2s7Pce z5x+U^0&;!fZ(#gS=#1Yi&Q}?UMDT~ap2-UoWrn)#@lSRQ%yGFC@;LxA>mwxL&p*Uk zeVEOa@kxG*k#UF=mV~n$B1{8(m~q?(M7cS1L1_fdky`c2oVUnp^ZZK0$*-u>ct?v( za!b+HfH}6!*L1Xrht83h`Hn2iQD?bH;;a9F9_N^me*Mt#4HQTTJ#AL zw)(vQ8P3AkdS@Ch+HQC@6V>kgqhx12L7aYFccrlCxtkPbSIv|%3X(JBJX)~%ax$zm zZVDw8sm-$pc*zzstKJ#4r>4{B2dO*MKkNwr;x;ob7RtNiW2UyI31x1;W=y7H+V+^- z?a9dj$fmFt?ioF4^q;(n+O4&>NOI!XceRMx4aOpf$3Jdw4#HhXy=o|Rt~GMDNKOs& z1h#IC?0yNKFcq9^dgK*MU8>zDtJ{Bcbb$A?pdT+)yRa;cE4 z6WJ^8{yrw_vGFWB;3iMRp1K2Ieaf)Fvywm5(qn%CczIuGzF^S7up)zKdlFjcrOL5y zPWf+><%!_~A7onMe#^06+2O}dxYr4vb;8X~_^1>9!U=D8!W*3MM^1R96JG3u6P$2_ z6Q1IP1D){LFP-|GaIX_S>x7$~@KGoHg%jTHgf}?hkDTyIC%o7RCph5x7$~@L?ys%L#9B!UiW?;Di@D;RGif;e@9+VVV;jzTd8QuL@a^+=u<3 zm+keXY~0=ExmB{%0x~iDVF&&$C%nZ88=P=~6V7tN$xe8l6Q1dWCpcl66CTDl6Fu1P zgdI-U>V!`?;loaNmlNLNgbhx(zzJtL;bbQ~&k4^|VX}Qa{JYf$j-sJ_{zl%0jcv(o zR{Hvy@q+cUx8!(4eb+)awx~BOIXvL3?|G={u?N&kot(_EJ}hAP*oSX?5!C(&bMX#_ zDg$J$8URFe2usFnC!8mtyiPM;9-On^#7n_ER!C({l%>|wfmlWvoBh1ruz!T0%#*{` z!$zDJp8o=z{H#R`b7n9t@)7e+*z$*up11smEMQ$@z(~HDtC-FB>>Qybe@z9q-MJGi zx5-oWSvURyd%gt+&D9x3Ilf}j!1(`6DmOE&7brD6Hx9*;$j2JPp7&83clA! z$~*<8}Wlkm`K5gWoMah^1dcN)SOMEC+m|4AdX$WmyCzkPP5bo8$9vs}{s zBI(2jl0?_jEV0$%c_bA9fRg+&}=#e(E=jej5XK=bhulh z2-yi)I(X)T%10EKBKRH^al_jL(_$;!PWx;O5r7zId>7ewbDF3{5_W@hcNu#j z;hm83fZp`Qh~Sw`UyRx)US%-bX_pexKkl>JBMH@xSJ5H9JH|8UO||1j$f|Z+LqxU1 z`ZI{^F8~+6MW!Uv^W_|+0PFH>1$h2m0azsf^7pI)X7OGHV87SQ=5Lv)S!Wy*pi2Rg z>GBUS(KH?@6o61>_UG;ZC87~bV|UyFrJ<@SKLde3Ipb7RDHZWe5%uA7-xir_;_|(6 z^|GvQOJCAz+a{t$ZTuBg6v=HOU+JB#PpkpYqz3EnEL_y`;Ld(r7zS1LNes_7tA&au zL7+H%9=#|1k&}+D5~^(;`L>b#;&r5D7`r7=p{n%kWl+QSg0lrR(|YXZitoAc$*P!{ z(zivK0oh}6m_6GmS^-{(gVzY2&)5+kq{{lsw5rFy5oItv%cTmz_f*44+>%^gM*)++ zjbj}zZHr}`Nz(EVx8IOyVNXge@%lh8T>Kn|MR<9BqqvnAARaBU2fp-}?HyZBy(*io zd3X(EtS*OihEuP9*+WwHGQJI~RN z)-sv)P0t1aGj%Ra%^YuCtSZu?$Mu&?&;3#sULpGN6@9~|d?w!`E;#`be-{!HZ4yDi z3Ogw1Z?vep>2kU6aRAnEp3q@s*-+DgI#O~n#$Y7I$jtf&he|BKHyqQ}yajPH>t!e7 zV{J_<8PFJoMYLX2zOqLH9k-l6d83cFPO$l0bAjE|Pj6P>V*%&#+x4RrWVZEyjrl62 zf+;V@WGnQETv0?aYu>ZPal5poUIAzPK}g|BH?`Uz4*{aBPksu3FCqQK1@Pgms#~7| zu~fYyWfg!Ekt-fZWc;Z5Yq_mQv$V)Sp--G>rfX7rpvW%7&X${>qn zjLe7jJ2>&kUdmGKec0y4knIvC3*SaWrREBCqzb0Iq7r`;)h90VfpxDge()p(6bg;gqRhLq$tyRz9nnU~OkC~8H zuk3${Tf2K}DW5hP!#=-=8$F;|mezZ7s? zvM6I8nqtrGIfzpAnw3Lo=XNaqP^Jwvc@4)xVD#0b!Tt}a_(w8$Vj0G8xZJRUKU%Tq z1ZxWm2?X@@P2Kv|)gdA$_an(&Gm*9?`yIn?mA!2Dh{u+}y^ynhtjJ`n2SIvg?K9%3 ze2(cs0c3RiR?)CkU%mpOH2-L`;->`yd<9Sx;C#q*>%AMmPU`w3w|1+Xhff+9%A*m} zen71WJ~0HFCEc0dO4U;1FouB=WyYm|+VUz$$?G7PJp}!gP3p57yV`24Xh&!*$~4=? zb8`X$)}@l&&eVsf;|a!UBI|;6DEnLtuo8FtVFYc*_E9Wg>&Rh_S_b)eBYn~4Ip;WN zF`>74hC8wND*)4lC2lh-gFJC-!oc9xMEir^=J_Tf+DgKrl*cryct$Od-^O8R)WA^Rgf-q;jW6=k{?-Oqa+lYCBx-&0lye< zI?cR+Uf(ExMk1+O*1cQot~(o+fv5%INJ$#+x||6V=;^tj53L zKYU50^Q4OKSAF;-(sNbvqBFlO7E-$ zPUgQ?g*AKrTPx96##6%7vQHG)1_4XWe=xf-+d+<5c&p$c&#Vy=HnYf^IJv&VI_4;p2EXG;+2pI1|9r zzYTbf19+0SLa~g+GM*kkq{tpxp_(z?s(%3=hxfhC;IESo2p|1Yi@s?)PA?`QUH}66 z^8RR2j!9`-zov|xpw-)sBGn!TH`<0Lb3Z1thA-DfT3^RN^#A+s9&l|!P zwaH)iu+^2lyMZ+meJ5zqcHx57>2#q9od||MEcEzeP8Q)Q?%;Cqs@D(~^ZejCB@{!> z66`xQIjW_1iPP~JDuBHDJBm{3!1oyn2*f-lr~lWyF!-3QrjR@b{kE;Aj0tdnEK=e7VgHz)zj^?fNe4UEg#elasRW zZ=8|D;r58bf>AeK98jj+>pfsuBR@<{^ z_AYDBLAoPr|Lu4jy#GvsD_S=3$eA{AZn0R8N`d)+t!iq`p?@-x4u zyxJ*$_qQb~#+29NSL&ql9sJ(qRZe-q_mnSn%Ex_Ad8Jc+;Ct#%mQVQ}{8|V9(D&dc z%cp%0euaZS_kSp#_dVt14*qA~Q-9DYulyc-HnG&N&+kf9*jv6=+QqIPeGk6hDQ|Sj zon$JQ<-}Hg4}N0`@;^tC!NO|&Cu(Cu&OPnzIGHSB?1?O$gWcq&!7uPOWSoxz-h3Aj1TD;hG?ZwNk zomIWCwlP@UFlBK?V`Fu1InQaVSXe#5TU8Sp6$;ia_Fh%LG+0|-*Lbye^ytw8z1~ra zyrV`fs$RTwz<>cW8*1x<-r%CzMz7>}msB?jwm@A5)UxV^Mo_x}R(qX1Z(V4~g6al= zTxLTqsBf%JK>{UdZ&mez&_Zuxup(H!q`EHHDDaDcUrYl44iI=NLk$g-EnexZ2nH)E z7gbkz{Zr?7D=U^(ELbcgmep2PH>S)W6sn<6RV}d4@TaV*RM#)9uB)wE=&f)#@mACzdlFK=w5LkZ6DGZr zmQ~kP)i+!)Vbaou`l?W6@PeyGI(gU9Azk?@b@f2lA5gxuy0W%rrS~$0dhSdc(Oc%v zYs~l7*C<)oGLXuaQrXgq;3Ds&1);`KOY0kgqorTHqa}JlikJeSDI&-&%qe14Yfh4?!kl2o>%eEr8u)d zZ>UC?=xbSHW2joSaF*nF8*3NVRV-etq+Cb0FRwmZ8dO_X+sIIs${VHfnowi)sEVp8 z$TZSfc7#^U_WEl=<<;IL^;Oj)y^YRb2v#&Kgmx01p{RPRp<+3d#V91(LciH<9_^i8 z55m%=i)$;D-ALltX1OEkjIt7d}E_xukzb zjT#Qh^m=bq?ZVn%Bkj;kLe>2)T43Atg3(3FCQhkey0W2m;i91Tyn=#p zqj(f~FRyM4GJwk~7cHr+3Xb&Z6%7@OtH@qVhgZPw42;^e`s?Z$u9c$)b|+C-0Exo$ zy|e2Z=o0T`^^2>j>l99Tu)3xqMRee7nKdwT3mYnyc!^GJsIK;w*VhDlQwb7q$YuJBHu;l129YnE^N>?;P&TwGnj^w3Z(X3NVQ(I|#@Q82i4!nx-*)`uD@ z#r!U;9$i-*Ja_52$wr?WtgXDRI@owFEx)2Zhfr)g{UaD}0bJE`s6%eie?wXlXTvICQ>KIcp0XoPo4sLR45V=AP^N^YR2eRXQcp(6>{d1;Z;d)#N>#*?<%{Yx}n~M z7f{^*d8xo*M7)kr;{>nMV88Ms82s31X;$r$rHhqQ;>FT19|`bCFCJA$afu}<^9M>@ z)eQ~kO&5quIWyj3?{J`PEJ?_%a{K4h(@>4+J<7F%U^cUi=Ol+KzpW7bG-C8JQLVW%Aq z11i@M2s|)mrkWmGrR;oy3cIcE*8Qogp`US||Jdh39uv=_xy zo?|1f`r_W&GE68`EWkucCoOFNv_8}bRAs#=FI6Vz30GxB-Pz2=j&fb=n>=IIZ0Tvy zVLG~=p;i|XrAl?DbXvJHM9v=Gc=kY-NCnDELUl}`$^%py>9V23#>=>waS3LQ#kt_i zq@C<)Nq^V4PmPCQsG&~GwKKKhIAA!3*Cq!}(qFRkmxNHF1sFHw5Y$#zxqMYWBJW!S zu){)Qcxs?`w_0k}AKu6$-N3|-wMGD?GN31Tr-~cV-JEqBzP|q?r`EsI)ChyPUcH^ty6XZVTkmPdevRrEj_MVTyR^v z@%lI7_c`fnC_9-e1@iyJjznUw^M6gZxa3KCGXG_P>T(oJLRnwBWF6^p`oQimmn?l; z_5#OQ$hf*j8#4z3QRx9umpyel{*^1~RJxS#W%P8ptWIYVh_fWav8p0iVLKC|`Hr^G zpEIYp<|tR+)--QbNSRpMhjR^_iVsj-B{sXVx^@}rQh^c#SsCHC46k)OcBySnUCOIZ zPVLDhhD{6HZp()6;A`d-(XTGhjIsWFh`EY)ngjo(?;eFF5>s3s`m1d1~JdBgFm zyU&TKjO6fkq#+hcq~};LS!OO}AXEpjr+C@lCk*Q8^1Ec-QO%O7v4{5T)S9j zbCuOC!$+&4hZ-vzYL^BX#Y$@&yChDkh$y8aBbCD>*>$$?YC?6DVh!n|E*jXsY8LoP z5o``9G zuNuXyFq;1WyByz6C{0xhB(cv|rEss7nW9*dBZV&dT|7L*G*z=uh4e*@iu@n;-UPm? z;`|$*bMLuZHo}sy1mqGE3`ige5E2ATNCHH&k%Z0dk`)3WiCI`xP-|-yEx47oRH?hx z1s4>TDplL6wU(-Nt%}yR+SW?dwsz(HexI3hH=?!u|9lGwi%h*19dk1>@&9qVv^i5i%;$*j)iMkY$gGH(dTfH;! zL^s~2@bYLuPt(@4z73TS69ndxT8EKhZd)&AF>zkek9V|pwBZ#4zxXlbdU_DzYq+<& zGqkR66~=GoeaLs|r^tn0mC?c&N`*?x%Q2>EP!;v14Hcof(uEbOy0oDoB)F=tC@l{y zsi~{4ZLBD3)Y_G*gJBOAwqV}I?7X6lFt3HnT~c9U!Ft)$$7^~8iC}m<)jtcke`X$9E_cZmQIp{VXgs~JUG5X@_lNlYdiRmeB6=r)L$wMlHkZ@#12 zfr)oSG+4HJpldBMz8}%$U>gy~t5}CIB`A$02m>*?;0q6)HXJ7*i9bN!%O71Q-d}m;|Fj z)+x{#F3}Fp#LO5EdZq+b4uWgbQ+-U?l^$(L{xg#%IUQE`Jz6Ox7`7AW*??K3;A_ZC z;Y=7)BepDzwOCy}ujpU5s;K4GL$vSYKH_rb0Brq$DrO@VhSD8H)`C!h`{BUDFLsEGF|I;ZKmziBPrgP5hU^MMz!W1|ngsKw<~Okeid25>BgawH+|ktpd!D0j3iC>A$MIHjU2i6t0MT9d zwS^pCN>5Khx^r~mL>Jp)+ElM9$v*XrX{Tp*VLUVd(=VH&lq$zh=p*`&744uz1|d2r z;bE{Wi_8x4ou=zqooS{0n|j)U9WV;_%P=QM+kts;NM4z49o5$<@&zzeNmn7!NIt0o(aPG3w%EnwV29ms_PINme#3qTz9likT^w&7LQDq|_ObktY`>x_$}KL(X8PQSBIn_21D%(2EOUA~@7 zNxU6-ibU~b7TS)PHhL0tRhTew0VCJg!&-t^YSbZ`eib1`X2^OZVP(qYD#M(P-QVbLWPAo*r(vBIs#Cvr3>ySD}L_Bh8hn_)O5Rt+%y^7$h6dBo8tRdn> zh*7Swf|!*-EQr7~-xuVF8AC~QmOOq)?$Eew&D^pDP;Ym13Gi?8%VODHXdfX+8txo6a zOxmO6d%CeSiC3}qWb_ZV&Z+Z@@ACLOTZ>mPhN3JCtcf;ZCTr>$T0|$R2Uek?Lv$LM zlbKQO_D4$u+iToI#tk0O^it!VVcde&fDt+))Vj)ltN<`m#u6mf@(%rJcih zuZNQsuDQ(!00X^x8p<&G)f*GU-qF_&^P9ZTBmQN9Pe)ms$~jQL_(?}!atTd=$!P9a z6%}q@Tbo$0o3S6Mi?d3_Uqr8rH^SMX%`JU0U(gxAoLXS$kwwKWk;281- zWiAyPUlfZ=!|27Zh25FBgfkx92HHOcsjRgfy{ODsrGqVZfTNTk-W+;?y%)o1n0F>j z(5A$&6>c2{(U=~>^6X4nOmfVYAq?5cXu_;<0~cOVWg@Y|y8=Zo3)d1m#?R241vOEP z!7)~N5IkC@tn{E6qIl8g*LC;xb#P-;Vk6z?JzKOZ(v-|`J!X$ z@4z;yQr*$ch5u&Za9`7e{_lnPTeGQT3D!WYUvMgMc&6F(-{sQm1S~hnR+ZTS z$5h4n$RPTe6VW;IpX3UHX}}b1c7Vf6WQVlN!NXy1tFuXGcfzNoH>wGIW<@~Q^UKOj zzpqm{V|fDK>fE=6m9Yp-?@Ws!(JMlV$mn_C8K2Xt6~B;%m+bNsH#^KF>Yl=6oM z7YDvE`iXVEuYJ6xXXXtp?_GCg>(vDpzLs+R{$Ff5=DnXEy6~0fzJ7eweSz^k9$)Q+lmN>~28_smt-{_Gw1 zoP{sgC;#(;%GLgzH(Ogw4qh2mw$I$)A#4*w%@m-^cU;BXTD}V9DHuq2 z^XN6xU)cZdwNLpr&iJbua_P;1t48fgdF!F%HCuD%uJeDrvvsF+TFb9LUc7c~b5rNo zm-E^#s8P)yzJH~+bIT1@#`iz=pSSFZA%FVeD|_4O-n)O;Z}&fP@mUu>@Q*jgz201z z`)b-pXFb2Yt?GrpFK@cL`q{<%X7{UyuX{W1p%+STc=M!}u6%j!x+i{i{og-+@%c6H zb(H<%m97~JE?jl{!Tl>=?aQ^xe>KiMJyex&>r-bXzdq+oPu;DhuH#Zu6Ce3ymFiWzFWqpQgO??IVH9kGn%9+;z3@?DETp9DeRP|5sLjXdUyf$GjbVETqzy9@uM=mXU|3J?B$~R58tf)#wrbhKH@@!OcjC!~cQ1PN_~e(XG7|3m^GWW)m7DF- z$3Iy4=8`v8-Tc9&UHO|H=~%G+o~9plwW&$t&RKJ-AkD|6aJ z&yq(@c<=`~iQl{XvQzFo-d=OhX*V5t>9PEu9^7~F)vrt$cgGv2?tQHFTN6KQ`Tg$e z)(j+EzRq=vH?aG}!j#`#u*%mve3|l`chaL*j@Z2a?K_UYYfDkaeM#TC^tsEDANl#O z?*HHyXH9tXwZs>md;ZJw-+tkbpWO5M>aO!&9siT`N6tNU;sbwvYs22|4GZrd_3Kmo z7xt_fa^&d~yzQqYT0@Uq-S)MPJDNXv{>a*wxMg@No#&~$1hHK@s;+(H%ktm@bavNJ08B}2UkDz#@3(Sz3{yw z`|`$q_`UC4^w@(>=UskJ!;RP7o8>7y_~7Ni_Ou%x= zYpY8uYbL2Mn}1#=oI7lJ3hT8uK<@gCH33CDZw(u(>8Rkh0|VO<0-Myxn= z;=Rf#2Mvref8l1v9L!N08bnj0tkMoH)fkpi(l2AMPRq3!HEF{thJ`ZZK>y9zB3`07 zOKQrUSU4|1nO;h~Lm26;2AVU8D@h!pWcTG{uY$RJ)udoB2h$K(QRV_c5BtpaBS*&J z*@kC3p51tE!}BnnYUIm?+zo{@!aEH(!NW)gZvg(xi!PYmBU2+RdWt;~8+K*YQw4)d zJ9_&EnmQK`w83npXNNMB4G--wOTeH9>4It3IhGOehgS+$%p9NcR%+qK5n4?Yb z_$n4pP1F5^6KGBxUKfXNi^KQC;Rn32`hp3u_^3GCABU&L;VKyGKQ#^?6^G}=;U#hT zw>K_+JDTJ2!9&mzDja2McN z4Y&^OZFqVB?}d9Gp0fZSfIAiE`o9D?5AJXAYzKT8?igGzunTYy?qj2rdKmCQxC)me zya1T)<9L2gI@}Mll=_(TY^9#Zlk`W#4enOlzcLo^Hn_jSlLz=P+;fk^1wepzz~x;KOiFEd)*(xcAIf>Jz{R;HtUE%MZ2N33x2v9=KQF$pO3v z?u&S)06qkF&3vV1PzLU;c&Y&Jh5G@XM!<*RPAgODG{AXq-@wxf_z>K&SkCML9E7_8 z&ql!8;699J8{h+QFRwrv0q=qPFrMwC6JCJ)BMkTMg-Tsd817qm?ge}p?wyMu2Y4^s zFV|u22zUqFx9Sl-W#Fba!UY_JyARJl0QW3WYUEPn!AGFOEym*qTmp9hPb%PTaDR?x z6yQT}|A8k9FfVHM;mHA<3Kw<_H3e`G?w|4GQD(VPf5%focm?tYPaWVqxZl9D9Pl2v z*Wqaeycg~t@vNpi4znlW=>ePy_aAurNk3I7H=gaJ!ySQV2jC#wEId~L&V#!X&o01w z;2t>*`36{>uGC*cs3(M1g5QLCLK(Q*o0WPQ@D8}8t*A4A>)<|!=P=*{aA&u{-^WM~ z++W~H0(=PWgYAe1-~({q#50z3xF6yP0#>WA*AY(^;5xW}z>@>`Fx-n*qh0~t0rzP< za{wQNdnzs?C)`rvc|$AURJc3v^aG|ly9Z@R zdAL~{kY>PnaO?5x1-ugOHazYO#iuZCE|l|Rq7(%a*yvk$lq28>J&@}7R) z8G&|yhjo;0JbwiG`YCwGr)$|RkL|YVEWg|1FCY{}^SG3!z{<0Hw(`}x^IR*f9?R=i z-ey;xwGwi}6Vz~Pyh_STT$#`lsPiB29<&d+4qK@Km3m%074oECI|$tgNA#U~v_8K_ z`J3%L_exif#4pLGlCF);1?XnH=9_pWcvZsP-aOAryT@JUI$$~aNiT?^GmlgJDy2Rl zFR;?zUYAp8+9Q%pX1BLi3jQPqw<91 zH9xMr;{8VJb;7Ghc&2`b-FP`Ce$2<-sC-QDcoLrTx+TY?PMfwA@1OdaUg}8?sPqfH zDit5JNL+0z@7pGCoG|Fpf3u+vRu6{;JVWnJcAHvqz;n=jNVh2yetaGLv^rgnvp;8t`k?&&j9`6_c?N)E|oP>|2B@Z)P=)= z4~@`%4_Xnf7Cab5d*K*M`O_jYj(@rb(lz~6)#%(w5S;pOA+CL)}LkE*~UG|xMvu* z$GGPiceinGGwzedJ!IU!88>x|(Qn*&#;rGQk8w8|ce`=FY25pa`=oK5^t^2F!^Zua zas3%Oyivx@GH!u!=Nq@txT}rZYus(dy~wy%824)9-fY~vjr)jke`wr;#(mYeZyWcw z#{IK#)mRU-5ZnJSajl15s+l+gWaj!7$ZsXo) z+`Yzq(6~<+_gUkEGVq6#65r0X>O*gJnZeO$;oj+f+8=Vhdv>Tld|E}F6 z;E*;iM+wQD9-;671Eo?T9G>Ndq05mp=Omr;k7|s=!QQxjb&P|x%g&Tu%~`He`0^vP;f7)?J~p(=^y8--@YTg@MY7Zn**J_uhTqZ*?*yga}} zr%#<0&Cyq7MI|uQ)YsC1*?q4g#fxavSq{c+a_T$>!+t|}tFgbW zvuzO$8+Epo!Z1Y|m78r4u!WG)z;mqwJ(XSU-KFYcp=`q8lXZvk%%3Z}H#PMYHh+8&Rm}5&#*mWYxuzlBK*Y|fKUJJ|t^hP<# z=q0tRsfU|Y%g|78G*Km!R@L3TcA&=*Mwa4Kwi-c>*}$=+3!6caFW1=(ZT(BSaP<)K zptWLSOPd@}L#j{;YOmeU+1A#h9XMd^^b=Wq6 z!mpf{Rv$VPNv=|}R47yya?Ue^bZk&c3qZ%_i1kX<0K%Pz*h0%zzZlr6wtnsb0=rMu z182o=>sqfG2zNJ!cu0Z9z)+|Yt$4lgX}k-uYKCyaC8T$jHfst_WboV~ciG_luL?D_ ztZVJ;Qkwzch;~SVRohjlMMJv*VgC<$s;5*4e!9A0Ay*-83I+IgK>7}klPn1snYm8g zZ-ua%Wvw~@m;0raYH@{3idF$)TixagvC67zT#TmH@e<(v-qwL0HNqX@A>qOqYPvf# zfE(PP?Im|eHk~Wwwe`uAkv19>cuHm2I<~Xy_8wmE*sh8J4fMCD+2Z!8xi&gZgg1{a zQd4QS8*McPj1mMC@uCQD2XJ=js|; z-v|e*pWSCX+-&OuXIOQxk*t>0$nV<)TGs;$AtB@^+vvT7k)KN4PpGQ}0*?{u?}mNy zaSaW0s+a8bPVzWF;~eRK_|fm8TwI_a7jLQ&(Eq>voLo^~Q&Ba&K!*ssFT(u)g*VpD&BS{y6Bl$~ zV=nd!&&^!YxFEMEljmQ%TAMfoo13|*tuOP$c?olHy1H#$GY-GQe^=k!OkC?WyAMZ4 zaoRq2T}MlAcONbR&Bb~B*-d@xrmoM=#5sKIsK$BKrTV;=4s0H-hMm*ji#y#o%Kn_n zrf1R{JYsh;?$zqwq)`ye3BPBht>r1F}VX8AQ4_^kEA(N)i{?hE;`cC#Y=* zR<_Q~+|q_yU-M_ooRynDb4FqAjOi^ibDL(ix8>&L6}7gtwM}oG-kx`MRQCM$ahdg* z@t8g{e|k}KaZ~Qh)?&n?y}32FsI8zix2a&pjJ$$^neD~XoBn6wQS_Pdn9)?wUQpCF zJ$L5x=HlELGiK!HHa8Ww z_srMwRi6@nonQaD+mS!8K+7*pR`NTrUE}(%rbYkN;XU=V<3HG_C9jMYih{NLWzRVB zJxjFwQ&BR}pq9^g-jOd^s^uS!7K(z$0(Pm#Uv}i9SORMPUtj+;z7FrcH^O`~ukghy zGPst%@|TW$s*!hpru+%Na^!mU{{r?UvUCD{Ifp}^UXZxx;Qxp)%ptl z9+r0)#?|`X|A)ihYxGrpO8m6^b~jdBwT4qm#Qp5_H(+&K%cmN7Y|$C?r}ZZU9QiyW z|J0|{XPv(9ViohV@~Z`_j)uRoM8Ylo6n#4U)@hD>U8|N~qdTRe;;h3TTja>c3uyie zpUT(a9V&MGA86O%o%EUU`x%Nyr>AbMmaj{S4_V_T{L>xzcqtwJ&1X1#=X)+0@q+)C z@crn?b<+LT!kQ()vf^TW{v?>Y4u|@3*Y)H0`P@})UAT4yANW|;1oPV5jYWmIWUdP4 z))wFk4E?QhS9J{(7ptVQ*%;XNbWh_2S#m5e7nYb@e9vH7UvEo<8iB~4W**!|IJE_q zwh~Eu^c%=!d0SRD^(r@y-G%y<``CveGx#%b#I_TqRl=uJ(tVZCzoi%s&w+H`|E+JXae4_{k)79INQ4dC-KD; zAus4`g07Q z(!iSz14dxlzQv(7vUx$WpDF-N1|9) zpz(7B_j~K6Yy3RHQ@wRFG=9F|qr7!9HU1^RgWkGAjb9*mj@PV4m;`^>%Z$kLR&Olp z>s9tw1fAh+Xj@f=)LiJD2W}D3a-d%obT-inpce@`hv)*J7YjO%=t7{|1uY@k0Q3?; z=X)zmz?Vu$<=*n%JY|1P;> zAU)ptrj5$JQjm?_`W7Hp39`*w-wNdGf?VjWZw9hUkR9Ioz8)03AiKZ;@=ZbZfYYJu zZwYcU6ad*R$X;)K5eie_{oeXwWnV4u0dIXiQge+UPXa+|_6Twi2vYMML0$%e)Lbjb zAs{o9eVrih0-34o>jgRNt?xi&ZV=>?g#7_jSSxWUmgBm6osUZ?`w{PN$#5G6OBa{d zD*I9Kw#QB^=f|DG?qKyAXG|MlM+n#AVw! z72d@Dg8i7gs!sdbxe^$9Gt*Z|C*X2y@2uu}?~(M`e$)vJk%Q{~iKLs;X;%BD>OhiP)mj8h&%azSI)W zl-GWKX}w4V611kgV==I#sD7z-Nn>RVJU`@`~<%r3r@q-RNL=9nfA9C;z!uvIlq0(LZ?bhxAejvq_YD?#AP}`q?;pZ^hKNQaJ zPY{JbXnA#YsG)ReMW___9ZxS{iLUVuU<@Gr5NhhO?%q~qua(|Gd9k94yTUcCQ)n)4 zW78^4Sm$M=Y;Qe|=J(=KcC@Z8A$h#Ac3j)T1MAA}7LQ&-lsjIP-6Q=CI&-dIHDHCC z%}Cj2ifmF?CmLz5kW#$mIDlSjeD{g(RG~#Y_lx9+uxB*t0U@P3{pot~H%gZZQ6 z%HANfvEBu&*iJ)654q917g-$iE?>7Uin__mQreT~BpQ9iW-kkBkEN30bJyPDO-J63 z*kjqZcyC6(;9Z0zL@XEEw+f01(zdFpWs|bM8wm_O)@@!^hdm4$nR>fmdx;@C?hxz% zF{JNK!448bO!f+Ph#0!9y97I&2n_x6-GZUV0*W5`9zjzDMdx|1pg}>=f9?}BPf&KD z_X%F2aYX5U!Rs`RNbMJVrN$Ah2L$iYI3o6-;M+8gs68b34olZ_cBNA9EtQ4}d82fp z=?gmh8+d!TeUnsB;3ywWxmhS9FX7l#TF&1b4WrRWop-qX125a|kR7O{8FKoA1_XVy3Qx8$@3(Nql8xyt|;PyRf zPWJ~GK|k~~f<4M_-<5IzKza?gA=r1P{D}yzxLA*J5hNz8`ig~>=_RjpH7jXnI}}!7;3DXuZrx)Q{IE0$dIavpOdhk&=F^s(Xw_v?%-1P4@8w;ljMeK zW&coUsosWx<_5Dlq*>WN66&bYjCRml+Ka0wdU4(B5_Bwe`u=leKO-_Z7{GM4EBhxB z2~Mq~RwfRHCtS&d8IL*=y%p+&guy`o-~*!QP(z+~ZV z!^I)1I$BVZ(>TN;p{2PKulolCcM%8npkOw!-cCqAB)C_&O}(pIk=G9k$qy1H3woK~ z{+`ehNNd_?Xpaaj2{dfbu^$yIg&2Z4AXqA}7JOJq+20p@7;uh29usVYaFzYIVCld* z+nXd(PY7icDBbI^#lrr9;A4Q}vJsSkqC`| z$fX?M2n08@p<1LpjeMG;hA_Lxl-A|e_*We~ppuTtbNk0>BTyzub%SvphELm1zEfHY zDyu4-;u>L3O#fO6N~aoMk?iO~6+13n7ndIS*S4G8QAlQvaPYdqHW1Y8Hq=Y(im)f8 zvpU;eQ>_}i8#b+L?(WpPgzU+}^_z(V)Cm*Xju%Ffmp6~qw%5wmpQcWyH=iP5rFzRS z_iDl?1#!0=_G-aft}uoa<8i@McCtl-;URQ z`EqypR-t3G*9qeG{fwM09j5PDa=Hca`?eG55hTfXJ&`j7N%a-dPp=>&yzCch+jU3N zC$v$%{S@dIWUQ~1$bcY0UkZ9}d%Yl8z7MH%gG4dMcQ!d21)1#o5s^)TO!2KHvRRO+ zzWwyGMUXt-09BtQNP%x3#m*MhGklZDIY*Ep-#hfPRggJ8cCPj|K}y7wXP+wy%6%nN zaGoFwd}Z`=zKAXIZ6@+1L8^QoP{9R))cKZ@^JPIAeYa4-R|Hw^8%yLuK~D2sK|f!W zqFJeiuok?6Qj+#HB;0J`3KK&)`=a!}LC*Fk4f)hE$9Vg&y*vH8!y={rZApXDrG9mE zsb3Ra>U$(|wl4MW2x3b8T0u;yUnhtu_3H&0p-cFNbdG{Y=@PzCIHrVe62z47%@Q3` z!nX)wO88bmObLHi5L3dp31Uk4c0o)D-yy0^3EwG*DdD|>m=eBA5L3c;ivm-^_XuK2 z_+CkZDdByB)aeqwPmtxhgzpz*r7q$9qI$J1;Rgii)Fu3&lyHyJcH;^ZC1pR9u7*ZB z%0UHwkCL?g6bqQQ8{T~S<<2*4yCMAT0sDE0h4OMkrqhGHApNTCjqllh zE_G#8xZ1^Nw_i-}gl^maA!6b5=Mf2I|4PDkIE_^ep|aAds`;g5Cu4Ru=4SDG2mX$E z9Dn5XE`tq$p!O+Hllhu?nQV@-RK}vpnuf;GnzD)zCPAKq{{Uy~Ko|BTwkpp-PKPin z4a5 zwp6Y5kLO(gV_TY)KPV%mv7J56LgNUfQlmT zEbYfff$@1uggu$`BGSd&=0BeJoUt1kR(EgEi{Q#Xg)i6=q|ZrIf%4~)Ha{w%piOND zZPD1(4gIZ^UD)WT{L_91N}W*f)gvM0k+fV$GVxRXd{R~_cTA@G3r;~!N7IzQlG$wg z^H9X&`kPjjVE|s)IKQ-^LfLab3tTxoU8!RtaI3Mf|Q$MLDX)_@$Wh)-0*k z@(IfI?NRWsv@ujsUDvomgEdR4s+2`yWr1>uJ43nY)}uX&TckX6%T_2aUA%HDl#kGS z+9do!t8Az%ZN#1M0b=@!_5=~3xh0Vh;!=rkx~e21OKMK8sa;m1l8Ka8lwn|0rBaAg z=BreZ05DVo1!|ZEW~kvJQlv&`LXk=n0@S8!3ZRjM#I`bu5VE5I`JzS>p*3a-lk}vIwK1JXAaXB;GMs?np#P6(muWBeQ^n zvIT0PxK#}>EG;64+Y1|DjD}AWTxF0xf#{eV8A5!i48hPwiRhf*wR{jP z1UvCEUJo)BV{F;doOrqE)A(soZm#d(_&o87`yrIsz)=G$f8w`uMxz3Uu+y2FyY=UF zF_Z!&jAP{jH9Lxc9@C|crH;gF-hsNL5UMQfZb?6K--zat6_WkctNPB|z&WhzDVNyk zHX)#FV}=2ZM!|`=Rng(A<3f!U^Holba|EHW4b!`uf>*+u+xF9UR;ZE(7q}(6t+kB% zetO$r!^GrtRhu)}b2Zqs<+{8Yqp&dUF>>I2*pq;%N#ioQfb6m9n zMTfg8J6glb8P0UxI@4K8LRj*%cAt!ewp?6&j~N~>2UpgaiKtsveXjEb0%i3IWpOTd z-Yct5u;sb<1UayN)*@>~Zsg5n4g3bGT|0wns(j!8GuJMBqp6kW0hD#RB*WT|P$%|a zK5d2(R>-;*bDD`gbrlX}rPYfU>%^X#Moqy$)oQXhppDQlP_de=A7c=qrXdBP7JUT4 zI)|C*?9?qaiM4j0KNhbzCU`_@i6ozYtZm1DoKLV|4S3Vf#vlHse+>X9A=9q|&?B@N z1IFi*SxU`>znNCORiI{^Ysk-oT&>Bjz!6n=r=hci`2$8vE>+=o5Nf91Lf_yP zo@2O2SdlI=NNP6jZh{y}-_?&Aajl_ef5hLs3=B6v{XPI%X?$~PEdnI>9!sB~5V0=4o~;aP^6k9d@S z)gVofWc4oGWe9V?opHTE76Q3M>p}%J4Mi2+V%YUy7alMvIi1M+2I(S_YErTV$c!d~ zYzOkPiC(RmvDJ{j4)S3gmm+Jin(~g200xZB_ zw;D&Jq8reyte}UCe5Pa_+w51MyO=LL>oy8ZMFtoC*+}h07=?c~2phLrz=K!OT7O7S zsb+IoMC6NW1zcZJ$yHPU9zHK0G6%w}+(MyYCvHb)YfBTxAl3{m79JdR zMSGKemdCIX*YnNmXfwyt61Ol1K;%GTJK;wb895q51V@!DmO zu>GgwZ>8wQ+c4A&dln|5)^W6WIw4}eri|UJ0-XYVz|G2MWQW{}?6?j(PNMk6j!=`b zX72*7vCYalf!GkvO`Z;mwNPx%qeiSH1hKgWYu(fp>hJ86#D{pAjbF%CR*C0Wtodyp zE{gTZIr-p-vgVHm$M!P-gsEBhN)oy}G8XBf2MSyt`m-t+>yw=!364Utu7p-s;;Ujj zb*Zd{oPr13?*>YxjT|M~*;BU8yk-{hH4|_j`ZUol&O0HktV&KqQEPUTh*CsU$E&-u zwQXZdPk;E}qjgFlW{M|kZV$dJ%vWtYGZ_sdXrknBdoX$?e-#rSaQh8^QK-7IX5lhS zTQCW&s=^Fx{*r~E>e9wVn7S#egE>&8b*!s6G`GK8Y7rBli`bl)I~gh$x@L zuh*FKfW{dztJWM$G*0RPtIixyG)^`1ijQ?#^|f&LSdUj*P{$|rtJN2S!pE9agW^Cf zz;RG$^{LK2npLH?{aQ zY}`@@5Qg(h$NSmYkM$qy!1~-ftla+12+Hk$9Do16@33-37X6(q8S$(C`igQDbkC!4 z-osBADt8HC_E zJI(AY-mMd}+e3Kyg=9{=9bN^WUO+tOZQySIi}>r0Gvkosx$+oPg1~2(aT3C29Ljr@ z>t+;U0JCmm#v!Q9ID}}%5f^40x-{d63o{N~nsMlAGY%nb#t~ZBj6=+raYRJSIE2Dx z93o*e4w0}KhX~C$B0)2b24Kd~0L(Zd0yB;#z>FgVnsGFRW*kD=j6*1F#vvkR90E~h z9HNdHhj5G;hXiBB(V#Zt5O&NsgdM|8Hj#)KhgignLrj}-2svgP4I48~gb}gXlsgg; zQUysdW*ib|#t~PWaR?r5#z~~lC^HW6uo;JlW5y9dW5yvIWyT>IG2=vGVKWYC(PkX) zW2pB@KK2`TxF0|*OeUNp9m%8ar%523bO|8W)9%+uAe>+>?9hj|Z8kL5G4?!|e*#sN z_*CTlP{We4GJdICr5J)#zEEYY+8RgEpK`><%AS6fdn{jtnizOB`_x1w+PDe~Cuzg_-5g1&*1-ce5>zsG!JQu!N*2ejgjcD2aAbawzsXftDlQT}Chs2|G1 z58kcC>dJDKSAqw3;NS`z7k zHrmr%-L$a|1ApAXf_(vbxbBnmG4zND4_^HK7QS(V9&D(Ab=c5aNy}mUmA~yIq%@DP z8CxrVJG-PJ4?p9s{HvHVC1_X7_SB?6@=MGq`7F2!q_7WDNGd`r3wiSaQn;JXNmd3s0^2wm>EjNEz|d%)|E#Mg()8MS?rE)SslVC5VzG>b6I%SiwJQTCKJF}TEkk~+MDpL zrWm2&y*SK_le5^~Xr0KKHQcBuk=ijrZZ!$vyHeUfeZU&(TwK*N5bEy^b++XfD%W?I z^X?O{0chApU>w|~xm?#x1tGn;NV%>jE4`VbH&9d!hwZaRxo%7aU5#XUoeXHyhm5uw zy}AvXxU6fP<9uD9@@MVN#Dsm!v&O38>Qfo-8Mr10lOHsUr7bpZPYK0=EVlB;!WQR$ zS&jK!lrL|(7ND;e9bc*6(L~3WJE6s;#`ujW13Na#TQXuIfo;4l-W&F!jGJmidk_M| zTz&{0qYDbX4(zMSx|A85XXG9P%%8P;40eu;mqNRg#c?&Va(vgiX2=u$Cr}(+Z^h{m zW$hrvwR8Cdj{U8jPXnvO41COjs5qZy;B$gXJ)q+Z(y8G0%zWD z;2rRq@gsv=59Ci;k2PCm{LGM<&Sb<~(z-y6c{QR(9m|@3*bpWw{j+wjhj`Z4!MXu) z&bk)B9|2_F4*+q?eiE)#H!g8xiFkNCsFn9c#T}f9I#1bqv&)7d&AJDAb**2_T0fkI z9T;L741&GZ%4(F}%XrqktFq3q-U@p?N1B51x{ZiBPG-v1+bp*DgQeE)0hofvYYU%9 z%tbFu9Jal;-$pd5&;d_yzH%IrUebDps_sWmIl;O8%`kq&7vL!LRui;I>euXdUH~p1 z>BfuH`VGe#?wyCv3AXgZ?C@?mf^+XYbdG$sQ(5n^pLg%vwv}~7S-)ih+&kYrXF@x7 zH*!ZIZK1zo_%}fH1TiE2o~RGaVFG$>^eE;kHS2xSC!owHv_sb)h^1k(l9AFARz&Fo z=IPgkA!94}?`+znti$y13F*DKI1KN2^d|hix3d1ou3$xK6vuh(S|5`2<)P^P85bF3 zSx2m?+e)AdCO=YerCrl18Z@j_*W^Q>J_Lix1Xx)A#sKdbhTPI|gOv^TCqrkR9nY$_ zeM&}>o@^Xl)77% zZff({0H%;RjWs!!)%YHe#?3bV*uL3Hwn|0DI+f9TlHu1;?;0ju^v)V-^zH>Ph0KWF z6d1%Z&yUh;RJ~$IJE&^Y%Z{pih)aW81z-x95mmIUjY~LNCoK|1Cvw9K=P)&HK9+gK z20I6qSJC(ufGK1~G}gnKn^_j65uL~rCeL3A!fFL2k$mt^Q5nCA;)Y_mv(>mCm_*TU zl)u@C;_+ij%D$GLBDzK7e>kAu;!PV2=PBmtjQXR84{Jj88U~P>Xsu zh@lRu0)tvFMa5nd%XtTGC?Oxn3K%PQ7zAs3ctfa+7Lx|PsIs*8fcvoVqB2@devn<} zuzw$Bf7P%b4=U9p?8R)gx}VPYNtEYpj%W9cItD7^0+TB0zQ$p{>F6H!y(l&k6>$H_ zVW~V06y7y_EVs(fT3`)B<xIN72$=&;oB??UY_41WiU zwTz`v^{yVCaTPp zhCO5gWVae51ISSH6Q;Z_H{|0$&J!|nec~-fMaH#;T@3ajVJ~JC%6!t$%R$e0)gaWd z+0n7X=s-AJX3PkDN$X@>zu^cizSW8AIK!@`!ZL$!=yTAK-DYH+p^wX-r!pFiB;WYI z(UN%MXRbEnQ>g807wAA3GIw%GE-eZt@sTKYfy3S#X1{FM?ND{Hu$RjMXU0FH{H<~P zsc?dZep!dgC}d7B$eBb=G|1UR)*9qOAQ_h#gfab|qjJ%AwIY>yqhVi8+3{c1WXith z$Q~OGewtxl1KH`%8e}Lc5mUc&*Ev_%SfxEiWn^EZ)iA4P8@BtmCiPBMTPLcFLL1E?})nGTGRKI}w#)J-}RC(-qB@KDS}NdP9&S`O8nzU|&ke$w-{r_&;>c$FJ&Jva!`>5S&)%kE%p$za zVK;}1yT-7k`Su%xA-(L#?h4CZV%Tim8Q+PLwMUx@A8FHj4V!Ixtgv;Pe%8>XO&^NV zQRC={Zqr*4(ByL?30UU{McVW{!9(?o(_&FPsd9ZRYhKiiw&JRW(pmh;4Vi;#${3LQylgI z!={dN5RX@l5G(mstvlep;r0^6A1gX5?(fbkA*$GjuF{$~LHW~pB_Lu8QBbKnG}+}p zNo5W{zl3DPdY-Y>^l9%SlF#b^T>c{}BWU`ezk>c3?b+V>QJnFm2s*e4}rG? zyeyF&?gZ;A@aImr&q7~i_~XFO*Lg403(xVQdK$Sh$bCIpPA0gH)VZdEWa4I$Rry*hDj*HL6xHhCeq5tIdRCBu`*x$Vk{;B6-H7RtgzOJulqWmwR9t zJu*gRWEeRX#7g5G6M$?(rdBjEmwy2)M++>aE`W?!j?!ethpFgOoQ+3D=QA)5ly%dL z7ZHJ(FlIILYGW(+aiDkssZzLL&{)~q-Hn;?G}=uAZs&W#GqrIIcipX4Rz8&k+|IXw z4bPd=7HFN$mwp|e#$0Jl*X)lkD`AK##0xdFAi#T5&HX_~F&5*|Eq_ugt>Op4=QG5frSBEje^XDiipN2o&(L7;uOPu^=rP5;pzuklEasXZpM(i& zXbN6dYLX9e_-{6uuz}+|dh6%hXcB)NT&^DpHkbeW?`$?X4}HS_jcq1zyFzSdSBNW% zUs8(M6(T&@72=w>5784`c7?cd-U05Gk1x6X*TAEP@yAE{Kz-D`7X%++?^F_=c7LA) zf&Kdcy8YMVum4k*dF{+TG@pR8%xfRJ4C27!mU-(UFNl?km^$jtTbksm+7?^vlS%{vdkMxbC!9dsL-UBd1GlY%e?U{z04a= zjauf7WyLM?4$f4*!Rb-Uys-i?%e=8HXPGy=8qQ^2Pwhv@qkyx_>#1X{0v@x>>sc(> zsioSKr=CLofV0f&X&@fZ%j{g{^(;LG^(YWt=JhP&VxbC{WnRy6mRCZ+Ec1F+5KRi0 zWnRxIL{kFhHSIZ-XllT*H+xPaJ}l`ybTgjQ36BWGF7tZMV2w%-M3#9yAyP&LqLz6* zD@hs^;Kr;zuDx^3_a>4T~Es!NJuacz0B)rB`t^XSDvR3+>7VZDSj8i%DWt)o{B-}P+3{Yr||Vahhu+(Id8Ez zX;cZQsA-2$>AsIw+EDCmw2CSEK19>LKC*;tl@ELF2(Z&J<~;|07h8GhGA~HSxE!W} zw0n)<90)Gdf&uqEcWU2|_hVcg%<=~(!kfMG=B-|p_A}#UA-r^om*ubzQQ`Wn=^W@| z)-m!eBZN_Z+CL0j4-emQ!gw$ehLsQHR+$?4uZX8nP73?s39-j?N2Q%?_?LtBib>U3 zpr2vrSA+hE6Tl7=fJ*B%Y^E_2uVJW*Nh2mGj6gmPQ<`k0p+5=wRgSus?hI!xjT~v`8X-o0pCk0F5mFg0dnl@bV_~~_)w|+_;d>{AGAW$`WH}#NwZl=bn^tK2{f?@ z+znJWkmh~hrevbuYsI}YRtsOE?wxzK>ITwEzt@Ay2BNITLK!6>U@D1Yee&|~scGpK2+N0$J^0teEtB!L;V+`>Hr#TtL>Ny8FBkf{OI7m+1!|i#C z@d%nq`-`a!3~{yNF~B48v;NF5_*M_96=kY1bJd zOL&Q9L`rz%CIG$ zZZrt<=?yK5d>VOIq=eF5GBAT4f=817Zn$I@qXg8*Uqw9NeaN@|F^+Y^D=(e#=YYn? zTRi?{yl41$3&&&I5C%H<-y8h2iMG#~Xa@(MG=ndb=J7v)NrdJ*Z?7Y zY(Qw?V*|v@tVTrS*Z`sMu>m6CV*^CO#|DV-*nmjz*nkFbY(N7zHXtH6HlPVOHXsBZ z8_*OU8z7{Q4G;<+8z3Ub1_(qQ8zAZ&8z3BWY=8uFY(Rth*Z^VY*Z|@1u>m5HV*|t@ z#|DV$V*`YoV*?sC#|9#d$QglhMom_}Bmu z=h%P{tWXeg_%#7#T63pSol z%~5<`JfD%q{f-MN7cS8kBI54mxFDz^RwNKFLM?LqU_mL)K_tYpsUgBnJc_-drfgAY z0Zv?0U?2J*p*K`isXT`v${K3nqr9RDH>~8VL{nONS6uXggki4Nt*bC)N%|+s%k`#p zCOS3PKtOT5BZ!p@(-KaIDA&8zCG2pMVZ`ERO3OO&Q4r<&ok-aZ6_+d;#s|XiI1J2& z`@36U<#v4}3~!Q$A^uqqUvhZd-)F@uqnmE4Zc zeX*`-BI-@XRY(|q^sQE|=|b@(<1S0w+#C*|P{{sd?40jyQm)yqET~FNx|Ibv*Yzq2 zbyPT2VKY#4MaXegxGu(UKqqUVs58l`5(LSTcySfR$;(>dph}eTlcYH3+}2YEzT&P=Ufc+0!lA6U6IwC(`d>YjE02NBCSss%yaYBD3e$7`M4L3apZ`9hx81#qxuk zlyGekRlFAU7gWV+;;1q!T&#@NIGY^5NDwP|Lt}S;Q>QsA%@$ zfv%HyhI8+x=-j(CoO?e-T0B=V-BOMHZxZK#FXh|Jvpd{}K^Q_fGGpo<7Hd-X9Z#xfSgc9iH-%K6N~KAiCSCv1yD<3~%6;GdWs?vCH7tB+hoT9? z!iRQ_OkwF!efTgTIO$gA5jesoj`gk;T*;c$8nBD8uAD`c3OY? zNRWz#nd3N2ZV5_*xjh_vv0=81RAwueeT-F%$=(Q(^>@6jTp{o?+Bj^1-OeJFb}7QP zrZP?=(5Ybw5?05l-*!;FzkDk7rQ;+;9)XeRR4OV8iL+Lmh_F18Wb<~Ty(KD2u6Mi? zb>9iO(M%!;Owbqx@A{Qj@<-yT7mLFrUP=svi$bFj!{(j`MGf{gSAb-~G zsv#(~=fV0h>_WkJSQc3TjsUn8z=UIrw&?b_)T9b}xXVd>_XM9Zh9Ka!xTJ z!Hh9!z`!>kLX(ijY#K*P?kbT;WW!*bk7!y8RnCTpr>qMM{3A()7-u0r8EvQ;cR5AB z)RlG8K_g7lD}UDRU1`{N%^G2y#7h4%;t#YB7VMMA8gd-W^=#Kx727o|eOq!NjqMZF ztUvCZJGM;iK{ueR8n%fpi08Jnek!fIrl`xqWXpQbG#ZOJ6ixCA3&OG$d2Br(`8 zBib|>D9_wWJeQO7OOU3u;{)huxQzUstHzaptkki4kyc*oIhB2zKDF^6eUu)L9)Zp0 z>|hB6)lm71$fj9u1S@3=cp^5PV6Il6w4-N|T>0?U7+pou<*+BzJ*u7JEQMSxU zm0vhs^FIWC(sG0Ri--s>ws-E?>{XN27|xIkL`9r=EF#4xH_pmlw-$g}G%9+7 z{Xb_-l(&rrW|P?}-q>t%9?sGp*%V(gFq`7NS|s59Mp(0HigQ)YD^Z?)V_@oiDXcf^ zLqpz-Sfaqix?fO^N^$D3I>4Y8)#z(o!%>T_0eQ$20G9!nPGBp56$JVKoK0XAfNKF{ zU2XhdD2f-m{M*<+6e7v)1T`UB?63HnWAEIy#S0+MD#qU;F{P>kR_6DN1|GDvzIioc zz)InWqTQu~ zbh>Ppf1b*DEy|aZ?W`yYJs*;W3OLEhz1tAg@tTY+jz*c9)NC@3?0F9RQQ`sf_tDcv?DCOPXOviOv@`lN__=uMhc2y=i#}dkQ;hK@#e6*s@*B1cXSM87lLM%8Gub{LJvOCW4j%McNh zHLD~iK0-9IZZmSsI44!JsZO@T28J@exK@rQ%%ueehOx~WikXE4hO-?yQqKAO5m7`f zC?lspS`^*P+cYCRilK+0W+Q4~WE3ZQBWqyPQ4AT^$*Ir4=s}sXyCpE@6^tfLjLlZn zK*mut9j~#ZOEfDu2Npc7qhEWcxG2ALlfNW zD*cVboL;KpV-^hw>P16BTr?CHi-vT$Xecfg z4e4^xkgi@dB%~J&g%(~kBxV*3MMM@2356F8iG&voiG&voiEznq zf<;43z@niLxM-*;Tr?!47Yzx87Y&KXq9K8(MMI*_q9Ng!MMDzIqM-)$q9I{t(U5R> z(U3@F(U4eV(U6#4G$iCK8fw@q8b%nA6~b~yB0{PlDQ3}-gfc7|imMk52_C&@D7TbF zEgI?@$@tYC7!HXzi-sa-77YnUEgBMyEE+~(;YCBzq8APQ#?<8)(W4g)SvNiNtb18E z&1zId^rGQWM7?O}s5EPZdV8fU%63}S=;|DQ&VnK1!xh7t@=|;qa&UH8RVkMJf`fWp zidZ3+N(Nb~dGZj}4(S0$v_A;$XLpXxqHle zJgHdAiMe~sJB3uA@^WluHl?%dy^G)Sfj-El^jMm+DLsk`O?p#$EG=eJdOS;SN{^>T zZAy=2#cfI-oT+?+)1x+}#|p%3N{?kZo6?h1x^LNN)DM+xmN9(GSzZar zW*Nh`f@o4QCNG%4Dc>nXQ((vu@= zY`zdFBa@?6)O;&R8kMZqG<;3OMkmK_O7}IBK87CkrgUG+Ye+~iIeJsNua&eM#$Wl` zh9jkUgq_6>Uwbl0Mai<*;akO=DM5>3{D&m@llL&E^rm!w%9Bu}kW|@}?jJ(bPBxp; z{i#Ipu~p`>-jwe5HDLIitZzjNuqQ#LJDbw|iDdedW!1w!bS=V3O^)4^?jL?Jk~h`_ zsC!L+8fn2~y(!&4iddFuaLPZL8J-haRQHb|VRF=(x<7-IDN;WEv4puPo!Q9di3@b( z`k*d+tB-XmFy?kd(#MSj&OQs}tEk7PaBvUgLTuOY;Wg5LK?FaJ!i z11fIZklVJduWi*j_Nb#0#s)ASPDT&Vi!++zs9$lZ7Kgrc{q4a$*ODCx<0UVX;affh zo)9FSq{}E_0@b7<){I-~nFCF&1st>~E1zntY2XgU`ceM3kSN?ACaE&>8tYl>z;PuY zD@EH5f7b47jHQRm2H$5b`bp0R&O3V{P2NW0xN(g5Tk!E);q%Hk5EwChty+!vgVFoe z|6%V<;G?Y0{qgh8%sY7}30cTwl0bm4hfNYdKtLS`0irAc0)keDkPHybW)>D#TxxMG zv|4SAEmqt&tQ%U};#zFA(pKBs#fq(6Zx^~)tGCPV`+d%NmkH>#?eG5V|9?B5Wad1} zdCqh8?K$UEYAe!Wtaf9Wpco6YSa3-cRwluTmb6F3#~Sxxu>K0#7IOin>Osvw4=~Hc zN-pNeiE#mMGmJYj4$+2Q2muReCG!k=B+x+7Miptph?M3-c)cMHm*5%SrSL1yUt-N@ zkWLR?$UUNSBz zictcujv)^dO-tBksH;JpjR6ZLB z3rjhPPxv0xP@SRfsgm9UNT=O~zC+TCMW7kWT!ZCQNiQ3`(6O{ug~RGCMY&l@@a-&s zn^}x*B=}8-AZI;412}};IL+I)QvUGiXpvgL&;zk}58#QU1QdUDymo9v1b?lS4>>n8 zrKg~LXZ_w<%ahv0ShPn?S%cpy;FcR4R_=Ecsl@M%3?}@530fW#V_PZDmEvUnuG98kFG0Ekt_`wqDI zvHJEGxM_P8)Akf3j!xUFn6|eNl(fB?X?vKUr0vyA+v8^h()Od2zZn=w+k+5`i{#z3 zZ8PCAZBGJ8%KmVsZT0(3+e?fLrp`^q&9vR2<>99NVA{GtyJ`EGfbV;an`wKu_?EQY zXV6EaEh8goo2Md7uaUacc6Va@jjP_=KFHd`B-n4H@GvqzR^KvgKIr1Rhe>=7(rB=I zVW+i+?aU)Hf%3%Mx;7g-y|d6<>2M4|j~T4nDUNH*C*@p>?#6(ZB@&a^M$jTP)o9kVYbdky~ySTx(d_soZYd%)mL~ z4Xx6m3~wrNr|&_<*G<$ix1n&i>44BxAq3vRhalL{-eP!mLYXTAJiLNO#lK^yRP`=b z)o(ql#j5!6CR#Uw{Jcxv=aLhr7&43BnZ`}+-w{@5|0~1FNTW8#&oN9aWranOGHgdL zHE5QyaT?7|F#a8br*?}pJ{I0*QbZ++-LydPm4U?DCaeg4W@hkXW*DYNA#Y5b0iFU7 zPaA+CeaQ`JljofWTF|=50kuT8;bp8ZGj7KEup8`7&!5CP@kGGGO92nVQB0);bozOC z)%Q?xIN(8;4+Tm@uR`0+ewrm-s$*CU=Ukz~g(Ggw)Q7TCa#%@Oe__d0lXX6?fd_u9 zzLOGewfqaK<(nwlx~cmMo4O}X09D)gi2pYM>!$Co6gT%o?6?L`YAG38S*yoNMYAl{ zH0+*LN;M1#@f`Sxk2QL*7_TgrQXy4jIXaUy(wSIm3em4r0mRXzs$(iGl_&}{k}94u zB3R1L4vLUscaNd681K|n)T~F6j5NZ3JV3tRC7vTCh&cFlg3^<29OfB9ZjvsByY644gq7DXF^7 z@HBdZzd~#h6v=R5q{W>5InsT6F&vimu?Wf)@!Y8fZwEO3K?mefvVIbsi%ChwLDVr4 z(4)lbkqXSl+W20|SRu@r2ZA)ll`2jd0a33y^I_35^jSL>7- zU4`=U)exVz5~8^*f9JCNz(#4$Bq}UCRtT%XxIYE5!HC5VSERSeVQ>AE`C&t z2fu^6s^usgyy+vVB_|m#94%8W$Cb;Y-Ewfx6COS9LKaKpS0_~b1$M6{NcS++V*hX~ z*1N`BW8~Q50o-E%=^cJxfLG9K4u)4Z6dAq##1ISMZK_99@l&U0rCHL}Xgpd%Q$(R5 zH%=4nhKUW+MaIpB>2mRa_V5PJgKmy@873CJ-C8P(-i-#$qPNc|!J@avmtXQF<7N>? z3}WFPPd2PgkW$tX-6)WoccDyS&sSQ;lU*no75(WwvddD<%G*@n7nVojyOr zt;^?1UA_S2ZTuQm)^n|&Dj0SUeiQ}MI!|C6%24BFz^lk`O&|-p&g02z9zkpDQM>Vkk;SJ!@?Y)c?okxnvdwN(&&Y11ckE*F>m6|G_4G)?lZzH7tF=`44&cqG$_P` zgVOht086CY4@ZioeXN$tBFM|iqz=^vB8daSY?OB3+WN00~ z+_+iqFA`SN`+83iA;7x*ESO%AF5b_pg7j>Zd0~!T2cSU~Bszf|oK_uuoHUr=lyG zil1OuIga>&W|e-H9gpUb8h9QSftMOq7FLls$4JC9%i&_IKWYiKd&+uSG+k%BuZ)P2 zNXDOya+C3GNyg_87oCjS$H^yq$@q>W19TYyH`x2+WDjAIl5b(mgKWFV>%g zu=D(}rq$h)Zj?6({%XZW)63!WDqGsHsHt!b_yH*N21HkSEwl;|*RdG5^$j8!3o4c% z9~0!<{)cO!r7Q%WECQCj?LO+G<$&$ymxT_?8qam(3hj;zy zJe|K;;_ut=H&#|S9f8BUetBNy`URZPnuA6w8#nVQ)tHb+E=8-uwZ)5PBoPYcE@;uM z@u52_VCpa$_^*M%aLi1?i6wOh95X^+tuP#a@HjqcIChicxX`a$j;k%B}du_Yqp9HHma~R&en{v@Uy1um?2L5Ljk5Hm+6N-lfCPO^RA7kc(37O zsMow(sNw8^mWsa=5c!}hvf{BMl-ErYmXhMH2AKZCWttmc>IGA&NeIT^Etjd@Fsb-4 zhRlkQ7-1^MCXc+_kg4*Cn#>VGMmn+ej<*JaX?ErOJfKStm@W=T`>1A$?Am``w4Xp& zBgS71$a~0@_t$_t#_c}?Oy6;t3Lp1ViJDa(r(w1d(UCf@rDx4(B_g{VW>KwSW_%}W z=A*~=dc(+cTdEmj;T0xmmH4b7BW=cf!MJ5&^`ZgTvt3{UK+pDVgJ#e638SR5KqU_O za^k-?ZuV?n79RAXNiVi~TK{IiLwJ^sIm7ye7gi$AprKoQoN-gPVQ6-wZT#ClF9r3e zxlSb}1UwxVkULL%V((mI(2T>W8ZEu^V&7|`(|5ih0kw@WxZl#ZdkpsCSa!s+5;O}*D8oE~D&`X~^3LVHGt>m?^H zcl*b6;$bV``1egXoRvHPwU9$t)?TZ|{MZmUnTwB`ofIut9ADL3*!%gsMymL6hRlKC z-!vJyk7_5AQw}ND8xD@+M~>08L^w<>LG>NeX?UhF#H|M4ykn8)LB&5F2rBL2(Wr9W z?>0l^DEF!WF>~&bc-FA7_8c;9sXd1cz!Lq0_Ro^{jzP2Jy==sCsjh5}Nq}L<^I&j( zq~cYEhe#$29l$7i%mD z$C|xb^MmV8X{fvb7Nz<(XB)3c?d@p_TwJY#h_-M8?}oznj@)B&@n!&J1VBXDDC zuD&sqrwl>j&wv@n{WVJ|{@X7^XMNmJivQVTre_*t=A2{Ax)cQdXKk5rG&|8ebG7QT zkj4M3OJ>anH~+IPn(=N1wus7>t`-<`%;LC+|ITr<{(v9;JJV-<7n1m&J$_aNF#OND zaMrJZ;lDF;x^GgN`z34Elc4iIyHd@>PelDE7EAwe`_UBg=6%|bs^fLhJrm6)KMMw8 zE$4sKhV&AI@^@R0{_}>T8J40EB#>wK5Gv;-qPDhs2o3o$lfmY`d1xrz5!H2X<4QAaT49MlH>q3UhaantE4W$XV{i_m^JR2X zj_-$J(CFbh#x4G`kpxn=0!1Zhat_U{e3n2$&I}5hKt-Ma4_+WOOpl|~4ZtevB2Lpt zj>hiJrKIbVY46i|^cSXe2`fhk1$Tmq%9Ye*} zKzR`X6t&@{x|Yt?7M!HF8dwm+yWYAW=4PixO>6+87s*wOB<5om6m_HZ?C8Q=ZZ$JK zyz9?EiIItcw_m8Qx3o@SaKD9=7z+tntd@41K^5!?tALe-@ii3EL$C=aKhZ3&C8B&a z5Z!5*do&^}Wt~bLKMG_~cT*$Is9=hBnhyQa3*%C7KExylV<8FpnZkBD3l8@@i}O!N z!avSGAwimuJSYJuP%6K~;8`k)s}1l5fLlDK0knCU@r3q2Kn_J-5FMab-iwzSFMos= zdEAyu#G5?kL|hA@`XU~`~BccPtNsJ6R;9k2fL7^%w{GL6Ry@VPx(}@e%+->=j1qFbMzicdIc$(H%dRvG%-KH85DTv} z!KvcU8!`*jLz;}_REcjJJT?B6aZ}^}6dq{2!%s)1Kgto}pZHC{+h2^E8s|a0(KvUW z)|gE~rAC|56%SC7nnGQQX9e)527M%I428qe)y7RNuM{q5nG9&z1O3+c9&$GrH}%uH zsS1wI9^{4?$(? zXY`d%?X8~|pgGicI5o>dugaQ4ZnvYE1vfudUmBftp?IG}?_b8?xKKnKBO*@0(4X(Y z$`Z_EqLu(vbnCn%y{ktDV8u;ae#f!+?hKD}JuNQQu40T7$3W4wa)rARMBY`wZ*B2v zl=Q4j7gEi=^OE?+!lQgs%@Z(8&}uHEnxBLcTFph&=^IqjUF)eMX4o1qG%+boBG?MB zxS1CoSts*ed+g#TE+ut|q+xy0FXkmBtfNM#T1QCCcl$>uysIM0D7n^G{UYWXCU0Ok zhfN@Uv}jnMqa|5>E47x?-$<>00MLupCSoS6b)(fna4SF)tur&C)oP+OzUJuBx|#Vj z@D=svjlvHBiD)CP(X)g>&z4^VSS@=HiL?o@1k!sKZKr;Z{orR~l>O4<%wgVjGCfZji;YDD)bbW!oL%TYP*1U_x zlAOmLRbzOQq^L`tH<9_!;#s9;33$wER_#DvIia~AZ?rvFX{uBLN4#m_E zHmPL8W7Pqnbu!M{U7HknZ=t_%aIkaotNT&3&MiP#;DQlJW6X+qSTb45E zeL5UPYC%#$(#h;L$zJ*%r2!sQY`m~B;t3Qq=$O*6J>RuXjjlCRpvJ5-?x(>us?z{J z1~5%~!<=~3IR+iUyhCPqbm-uo<@A2JYdyw+FnBnKZ%Z{Q5Q?`^@^ijZ4-tv(s zen#<-8P<+QTb~0RmvB6#V;$j*N|n6dlmFotqT}9e#X0J(IFCE}BoK62bRX|8u4hfL z)R#**CCrZh<5NO8EcZU=g}h19{mdvvQE;+aJK8r^$X9QBcgsesVO8)jn7hUt<{Db6 zM}5%!zyV4`M_JE&*Wb31icHS%Sr=m}xkl6WjM{IMh z(Jmn9s4NyXeXh~Y`V{7aww!CUV{|LqJJ)FE+zNza%i5(~_$UG?urtp!+C|p_TOPfI zp%v3zVe9jZb}6Azww|0QyX;bcm9}?Dusw)~@j%p@yISnQ#7q<)W-MDy%rUsFc{db^ z-9YV~O+aPq81cqxg}ZqW_OM@pBWLNd)XG&07Sv&Ik+Zb6cK%8iv~rfrT{{m4(KR)s zvbE_?K*H$BsFIXWzoIrM!GNv=1BO&CzObpQ2_=Vi_*lVaW>{7P9vYjPaQ0VY@|x4F95^;GQFRb37b)4W zNlpu zSbe_+E&eb_*P?wdeiDwvHw+WnMvO6Ve`zC9u6_Rk&G$R4A9}>C=$r=Y3#{5% zJH7%v2RHTdvG#VhLMzq*ZfitzI|zOmpgwwZHhspz+uf~G*${SvQ&tzbW8ngKH(1D0 z46JVEHf$=4&wPd^4VJQcNE+fx>7|rEHUb9)HWPR)jUJq(@mnS;7$?Zb>f!YQ@hh0b z8_=o$z|fH#*g01v7c5K)-}jM3tDrjYSf}@rns%8;a6dw&*4px3HDweYkug70Mva&< z>a7bltG6x~{FW-^Dta%PgU&0Xc&JD#a{#q^A{TzWv?6jhaw(Mjba5jYzS;#`LX)iFae8Kfb;|e z#>c@icq1Is;JA~H6XAFhj*%zB(Xa_A{1QU1SdRUZC{Z%TENn?J;gvu{q*Rs@VMo?Nzap z5Y@7|2AczInK4p`SS+whCl|fC2AFHvSXiHiygY3OyO!>8?8L0o*bAW*WG6SCt)RTO zrrGY_YeM)IqRbEO?ZcY(U_+&lNl4_uO`Fn9c$x{5vKCa8`|oB|KFh2eV8;W0VA|8ns=7Rer)y zCxBYAKfpS-KWoYBi?uRrMAiuvjmYe0G*VSwXLM!RExFeKEUzEal49Xtd1WR3ieWlY zmmh3r8DXx9A!h`#WItkd0!GI}q+|Lmd#txRFmc}py!AU4i1toU+gk7nPWwi$82p}@ zv4<37QFjOKw*CX#_~hBJcx4SQJV|Tr)o^9a&M{T|axh61e-aK=a=&3^%ufZ6v~&mE zn3w$3BupdX(WS|(1tobVeymKFYdrd^k_mxmKj=zJKC89yqmJk9W(Nd(#S@UYc$wy9 z!*G*vGYxS7TC29>2w}5T;xhqX_Zl}f8>xL!vque@)qJ)_vo}rb4|x5iaWiLIg$KQM z%nNW0W1e`$_mKFJ?=Jac!1JB1=bw4Gu08+B_mGIz`%xWe+)U>080{EXJis%;xEZlO zYaT=_F)F}vqH#0D`1+w_<`^#mx^h?xRbsC1NljrdVxO#)sX&3Yj<-7CIer=NZ=jGI zL*&Sh0h-i>oX{;mpYg!jV*TW+v#qe+W6#&JNU3&SNEV+n-C)8^}9Mfnq@(>5>ava^fvRX2BY` zG%0?VOlw@$*A1&%N|{V?!^nQQGQUpy+74eODHAE);(4Wr(9KiHRzu)ny?eE6={#Vx zh=vKqlO@*#I9@uE0|&0YXgKbHj9&#fqzsk3VyKUUYUfKjAOuzN-9U{h*LW8EHw>Bu zf0|*()W341iJSDtlii5+;4Tm2W-aIv52yvf_KgK|VZg(w0S~vh9@Yd(K2xvNFiCJ* zUEj!zD+9h?cYOzg<0kdh0S|W=H*+shV9LQxFE~@kPgaS$d{3267`Fs}z$cV^&$t=e zbt0`_Y#IEk0S|vNZU%py8~nNbgP*Sw@A#e)&N5wgSo%g9HwAp#6>z9uCFMhwiP65V z${EHj5vXwq$gb7K%?J!HWODS20JH0ifQO!dhc&K;ydow^my_4d-%Hael16jab8(u7^OYWl%K% zWoNpc)VX7z)z&NE-R%?HL69aCBg3Xjce=)6f7(MBW1zL-?Q}$I^e;`gH%X|lp&y9L zex=L3(xL`9;azgd@}y8X@ZJnMS{pM6l;pAIsItogECF&ZQqP)(U>-2^4iikM2>VB^ zolQ&#SLa?gz^NFSZ59<@gNjpW0BUWM2!uDIu`FKUtK)~YE6K1x8C_xM>rGgl5>{I< zsP)zs9k;18{K8A3BE1FDb!Zy|zLlYEeUH#)qN#b%Bp_SAod^kKE}U&$!jV_@BNo~m zLucaMA#^65D%rJM$AV4Qeji`?Q4^jN?i&pNA0_u0Hw*V)bwEe9MGpo%JQwgV8PS#6 zpuVhwg??x0b zFr5jy5y4k1LR>Y`LG-DlBWaY z6I^noOD_9HfGkP2#U-iXqmW@|!i!}2-&8po7A|Twa&^=i`w>uL;X_7`81rYj#H`8ZY^B>a5wV-RbmMN`E^GMS*4|N;xN4vzuBwy3;LBb~N|$M1^=M--`8lu8ZqcZjH3oWVvz&QSR+vQtHD|X5_d1 zj6CkRierzNdQ4Ttq_*kP@YU1Xo<4qKx*hN1H34kwYT9)C)|t~Mk+`v9(y}QPle&AF zkKfqdd)#pzvoP3arAVHx#O)2!5@$t(Dz0qOzdK};dG zDQ2qtTLV1#j|6~%7YðsD|h2C0Rz(O-xG>#j{I|GS3gOz`CYX8ktOZQG_k-C6HK}BP`HE+Rhmk*v~{}jlvRErND*f+zRRA+ zpoahU-a%MAZ#qlqZ>zZM=fLvc8eH}r{P5qtZ&0ci$8O1HeyxPs1H~e0E+T106dzPa zw6UqFt+AyY{ZP`R=o2R4Cl30D1|DJTn!;pd1Ka&I&qLPxehdBo!bs%(bWHEj`FsjF zZ})$tAP!{cy07E={k>8^esn(Er{(4K|9+()(D}&4{-*PxJEQX<;@__n{L`-#gvByi zY!`C4)Rdh{;Uc?@tsU!ee`vElNEdf2`?037TYYz-yyoD#sstUlt>@!OO^S%cL52`> z8n0rzX)#uLLWV+_$o$w1mYM=|M6E?r_yM=mcu880$)ce?VemiHF#mt1 z9S-+Fy=P(w_|L=;@}G$zq@RhQ%Y7zByUjB(KEZzzX1>eeqiTuD zcqWDjJ`*Fq`k5Fyk9;O3N}qveVhFFs{rmDv3<39<7-2Ne#L(?Mgrc?+^q+|dK;APk z#08&;$$AsRJ}HHfo3^4Eili{`3pQ57c(5E%4kFN+g_I*QKEpB`OW|}#Ps?T;^yd2j zy`5r#oW>I)cas_}H3QgehIJ&fj6B16-xl5q!<*y03OLv2Zf`MPCv^Pw1kQ zRq-$*6;2wh!x5Y2vFdwB8C;`;M)m`4^0}r0TR7;hPDw&lj3?zAck44Q|JrMU?`I?) zb~@RpA4aU+bx>~i>kRlJc<8!k@Ev`R&LGR{49Jhs_)=sl>!}%y)2TZHsnF;QD+eP1LA_6K`d2YhozuM>6s{q*=@K%11AYLOY^U+0v7%L zmD}nwD@N=hOdEhvD_L=R!HjQnaN)SL4$8{YlzP*Q*u={VS`OML!mPMHTw&Kw*YJl0uC!}9@Eq~h9uwiqqD+V?d&$#AZiyFsL&L&Ifq8fU^kJ0=z=NIRqB~yi&ju2rdM8m4HctD*;|D;5@t51bmHz zG~b@zRi#2772OsAs8*q!0@MRQm%dAYH2|in(8mN=2VlAieO!P|0A{GrwE}e7D{$-} zbe#ZO?G;S`J|Vz%dqp#V>jl_huUHS@1_5^3E4n+8@dDfc3V=@uup5*X&!&%>w)f0L13A0vrM`O@(d| z;Aa4iRiQls9JW`qK$%+w_)}~PCM3$rUM=@1t-y9dH%goeeKC3`31LHE?sj#ws?e9j z+wMsA{PgICcNH|XlWp9wOpsS-zXio`kpQd?L$#{HP zi2M5yJ-^Qg`9MVF%v;+~tHM{#K&8q#Wf@++3}5vsRL_~OfvZP=(C=JW#%^SeH#CV% z{v187TD)xOLKziBs(r+CjQpMyPy`cvO2B#7YQwrT2eh_ z=3G?}T4-NyLRXXkn9iRe_#U1pQYhvT{vGA zvQc`)g;Qv<)+||q0qE*ljJ0a#PMw0tht7;nqouDYWv6s>VfuTPRCr~tl%uv9*DAP> z-O#vEBif|Ri`XmDxGw>BFr&h>>t@id?dt02TGrVl?RAHEj2fgqh!EIaj7z zrDmwm*}|La$wa;D5>%c&A6Eh_GrqgUcY)x1&ppB!_dKJX_6jQDHj$gfU#SLDOB%b+ zQlTw^E4LSLN8PQPX!N#5Z$-*g*lXI_0@!U)ruXh_H`1v7=R}$0*lEn|pSq!QqfGsx z-B#$%=tfj^dy&3|J9L+TC}`=8jZNEB=x#qSG(z`8nX$VWG!pe*f%XzYa@;4-enN=f z{Q?~%1Won|bchgIq6Y*zoDB#~?&kzTBLonQ?t=mr2#EIZApt7{M3eZifK>vrReVI? zq=uo=qXO4!7)tFEc%6o!)?)&9Y8Z+=F7S2@L$%KfywlPpmaU_dU|d>_0(qOXiUkW= zdw8|C3f(RR6fp8fW9|@4{$i9{E#Wa&LK$pAOs^bzHp*@~w?2R<2O^SMv1(~U-IChW zf>ldvIN(sZq35I1&=T15xYO&66uu%QL)o?M%^vQnf{WOz+PAc{H?vIgd3H7?sGRjj zNDjRiT?)Zr=ey9ba2?p10ZL@^RPGT&p3tXboRR0&A4%CAyIus*euQY=!-{m1RP0A%+&6`)egK|;(7xDB@Kfy18=deEX5kPb-n29P`a6)9v$O%vB{!^EiA`Cyvn7r-?87|Tv7sl0 zyTC99QPyxa(}L*f61$=i3>TsruyeulCuJ!N*>Q5PrDvN=-S7@u$5|~fwwvM(iN6JY zeyqOoT%3k<>C@^FR(0-r^Z91#Q zXuFXm;DK{_P|ILi_JRp_V*nwYe|?Rz&N>@h*2=*xZ5!v|*%5=_8%; zyB2WZYG_bv5Mojb5!;m2%Ch`ZhO)^NQLBw(-q5Z^<%5itzta(fnWCA{s`6?>DuhOi zYB#=@hc<5-!h2#=dAA|+q5zPsD&Wb3gOR=zK$W4*Tk%sB+T4ksne_U&@tShIs`4)z z6z>p#G)Q46Y>vuF*Jp{SliH_V-~t@7|N0h zD=UkYHx^zO)d}n_<34~Y6;W@0@S69uc4G$3Rot~nDFV01H*V=*JpTSwT)D#lTdXj! z2%UT%WWDc=Jy_R~{hz*%!FIwj$W`IeW6@oN=W(ese2Jpl9gvd{auUt zIn}TjwQ%m@#q;LYoUH7`plWu^&J27zi}4lXEuFE={Gtn6=)Sl4by)ty4$@jo4l3=^ zLA>uS2d!+E`yj}&4J#ViTQ%a6hCx4~_Z+_m4-f|l(aAA=`?3vn?ak?}${sBE0v}%k z+vs^{#k-YVF0|5|mDu!Nw&B!tSI2@DysK#s8AN3(a%!+B*w};y12epqCU_Vsgi$Jb z^a$9)1~I-zqbhrf#Ld{US%dPxmOwG-<28gTz6)F9HI4|E^@(C@AY1N_MNvWHRDo^(C;HSs+1O z!=P%;11P~=!{E*%C_!GsARh);INDS@-ZP{Iu0mK<2Gb%kDfKZ(E$Rg6*YHtvE*#s= zhvPChBDe=2z6*{xj~ExPGk(VyzubcppC1LE_&h)def|=TM1TGgiW+?(#vv4UIvgBB z233URSx;+MdZSJTBol_>h7KR{vHE_CV9RuRb~E|-V09|BwK;{`Cu)g^h1ZxBUyVOU zSqn6Noxu+_*~mg?jXNE|#KPy9MpV<#+4J(a$wfj_RdXe9O%oHkDot7EQBqr5slk+D zR-*7sFC^lj!BmZ}_wX!8cv>Cy8^?Z8x~&Q$s(d2iFeFv8q9L^egRmt`g~5Ii;nH>r zgSXc8s29p=`!Df)_=Tish*!&m8-c={vRwz7^a7ee`}a}6d^^_mFO5g;O@4G z>5$&a?)Lc#X|lQBfNi>Wy;aDu{riUGnxRk@P9AmjRAgR0q&HbZ5zQ@(|8#%kHc?Iu zlMlx`F!6{^$M>oD&x+s+>51CW!m^ot5@76_n{3y3l+7HCuL|Is$e*k6DgzJx0UBRm z@ajexZ@lrrXI)#ms|(q-*R&anCHgr3JRI5RcaMMnxZ`~fGyeGjhBt6{uc1Q!b^LxC z#o35==(ZmFscU+Hh=*UwSkvrd#223s$i`*py2fK&WDsuN8Pznf4QIUHH zlse`lK;&M66)NW31WDN(9OrCUg_Y7JjXj&N>WK!AS3t#_C-9xi5WWh>0Db|C1%~UFo+K{NEQr2iD(>Eb6 zAvt7?Wh{qXgh5@S@rl<(Rq2%mxIzNM0r)??m=uXcvUE`-*8vq_0VDEe$sP-i%E+6g z;;4$eS+)laQek&bMxNz<76IYbC^K{@TZ>@>|055Uorxd*+YN)u_Tzuc7PsD2n|amRV8HGK>7^a8E{# z+Gq<+hfAmKaOt9%uKdC>i@&tYl3!S6@t2la{MD9ObZN^h!FiThgp6gDu!vOMbOw7M(|0X7S)h&@zj#XPHI7wagMmW0^&Fpu;8Tcenw_>u`w+ zcDPO|-Oe4tRHt5JRaV)_D3Vq;n^-wMA+XA339T^I8&3IHeV>3chsV({_0H9;0bT$| z=?-DoAHfw1?=TN9vRW|Nc_mGlk><(zj-7Ar4o7!718t7jJar}|MMia6B0Xv$d%V2;Eq#SE@azZj6%~<}7gls)e zmbtLM{ApJ+O(m5rTID_bX4JS5K|h%VkquNjgA(UikRnTj37qE8t^ukijEbiQf0rZveC-IHVDjN zx-N#&xjk@XsR5B_P07W8^XfNk>u$j+kQb5pCDbZ!bqmbo8(XzjwSvR^U$20!#NsWD zycX5Yoe$fI%IMq@*5uey?q)^jmCS))6%h@Ep~M3e);~$Nn~;DTNkmpp_B zS9rt>pG$-|BG!LVIJ#6sj#AlXHN0P%M3GFDc0$wjq!0Y7+u$LDO_VU_+US2!U%L@y7d5u6XF9`PX8pB?mF5S!1<@NFeq?e~7 z(908adwIGudU+yDFRz`tm#5q9<>~f%c>;bfPss1(3F%&*F1MH0Zqv*A1iwq4?{fI4 zTB0&~c_P@$%dhU`={&NRA4s2p!#IS!UY>y4%L}9F<>?Oe@&x@}J^*>WJaNHZzR0m= z-;BZ+Z)|RsHS0NSB2=9Ax13}gPcQ;AA3Oz!OQKV{gTw|qDrgEzplzwm)yg`7<+mu; zTJRP{b#KFk&kHlF)*?WoJ3=j2#VV6?;VN3-}tverpJKoXCTc6A$w0CRqFlW%`iIjEEx2SA< zQ)BlgW!=lxus|i~-@5N?crQtr`>XL-Bc6a%mTg(@0AGp}?IOg^s1z5T&~38^kZZzh zInA$1aP~BqrplUXS+`@uyVUG1Ox6A+Z;X4rSRH7fjG^!-KDG#~@d&95S<@`fv-mKw z%FWN|nrZWt)Fx^-L&7S9Yo>KCLLF4rp{z~TgW|-NvRsVX?uU zgR!;1+6T9#R=Pu`MwB9ctiBE;Re4)CUYcA<=hrU6&c#p^FR1*nAA%#aYt67z%s^`_ z27(n`2ABe1I(!V5W3XRKQXGKgR`qb$Je;hCofq_Vr2!h?t5JL{hy4RMd5PJuU53ir z0-<{^7)Ee>HWGK(;HF;Kx1sb%M(SIl9Wt7gthu%WMj$W^sebjbiX9i@|6d z+}*bvBsJyf$afGZx-wQeRd4CP04PC2x1hll~SU zOTMl1^Np%uq5VAQ>~dmNtpkJImNXx%l^nu$-)mL_ zl9g%yI@6xn@*Q2tx@GFj=_$97kv2=eUV6|{r|Xn^8x@ittM4*g zV_CJO(cQWI2Fe*mI^o@Bj#AyWGL0Q$>t(@z0;ylgTE5!IS%;*s4q0#JDK(`CDK}*} zzb4^p97z*q!SxtCjXxO<$<5Q?`09s2>V)Gbm%(u%9MvCzV3wv|8o_%h_(|(D*w0A8 z*$4(HN>|ds!gU`UlP*goB_1rbNKIS>iNv&EK`O$k&d^k@{aFXBJ6vI3cZI#_3M<_K zVJ92*Okp!|=inhjIbH%oNke=mTmijj!{4|h#E-uY5FHfA(*|qmiqjPp`0d^wV?~3`!D;e z;8j*+--)J_@lI4V6f4E7Xei}-cSAxfe1|FgQHLGnP@J|zC16VlmIrkG*kf3ZO?if! z^($*v&0mIb$>L=--n9Z%Y;E6@sdnjn-ak-n7+cW8r}0t(*4BZYLhSVWQM&mbYk1f9 z&$Hd@?`B>DM*hdnw~h5l`?f9tmC>LwN7zkJkm#(U)`JnEj+1j(U$JlxGK^rUw6H-=mFEqsc4kkBTE3d!Asdw^&*SiVk zn456DW^0<8uWDTq>MAuCy(mA{7(~Ual=$!NJPFFb=8k&Ap*@Jb3186=zOdNPj-RZ6 z;jfv5@RU?3`WVMEd~{Dqjke*>M|-EFh>ygkqS?nODTd(qOmi{VGpD3(09%1`v{O

;+loWv*K*7PJPf0ktL6K8Zq}%}k za!QK8UPqsjqI;jCPf5|e-!Z482pj-_*z6Wr2LT{9Hw*9|01%tc3UCMj&H&sZz|R24 zDJcp#?3hzh1pbuE;f}Hf9C=D=B8n8QThIjNt~n(|Z@VJ{`k#^_`i{teqnwf=Wp9w; zopgFiwA-g?URCl=Nzvo}enijjGvXJgq{3$Paset;*sNaulB&C_m(?J6n?7N8^>Pt} zM;ulS*lB7JyNG));|py7DytfH^^;y0u!*#v5>T&HhTdV@kmnwl;+Bs9?t!WA!DpUt z#Tk0TqUWr@i6jeqrw+{j6;32Q4W*Rho=Ex}AV=kSCz4(PoKN;)_%9fZpt3YP*@g2} zK4Zz7+=QMA8pLF-q2?U@sM4cZ2-B1R_oxzUopQM7+1u?NRU$6r1db{(+=%0z+Ciyp zj}m1&*oqGxRiekJL3&4(SdY<2_CKmb-ds;63V)Y07kLhiPyM4x^j#ph;87)dj(eU_ zS$f5D!fmHEN9nIrgWgdk;>w*Pk1FLONh=&2?a4T*#EjTIz>PHO;5kv|#coUG9p$Lf z8juQi^Qh7}i7nmGXVvg@-&`8vKqlESnLUP{AbC4vP4%26eP6#~jpC4yA~>Z3}8lNyFfk4ixG8irE) z1YW0MsP&k@of?K>j|;qA!*W!K@^Dm1iZ+`lDY_Oew&GDGHcdr=qe?8GfCERBh>5?1 zFD+pXJcxucte*#tCh=fnmN&x9IGV)O8mIr!B$fp9?iojuh>JLxN0W#{Ej`-Fq$QA> zzZLX@u1&p#Ms1{gS##GyytQO_jd@g0On|G}Y&cch4ClK8BS9&J1li%ZyyRCvS;pG$-|!s);L5LzlCMwk^#NpGdiCYoOn{Y(==B^6YH!Q19Ev{W%yErf)#d3E8c66eJhro!Q?7esf zQdmj9t&L)K8P|1T7FzlqTN`EG)&}{p#`|Z?ic7KTY_>M&)LR>Lace_L)`sA`tqnqEYeQIMYlALtYlDEdwL!q!+91HK4dLL{hIU|ULp!jw zAuQP1& z>a7jB-K`C}y{!!b{?-N|e`|w~-rAtc-P+J@v$f$9{C$l1E{Bh*B`RZUgNPbzZOE_Q z+Mx5ut&KtS8Q9t&>}_ojaJM#u(QIwd9oX6+=x=QVAa84fxZu_X9$v*=U@aR{8*m~+ z#i~w0c^r&Va7rB(8o29=x%}XJvCdJxT5lfAZEx0-604kp4^@t>+18GYvQKIaA<8PR z>A*(FvJJWs=Tr_WAwx+DmCK1gw}Xc)GsLilksK~JbGKz1yy5F2Js(z9h4c(69MsJk zUI5jGxJHI6YZs+tiQSz=E9(rId9F)BQ%oEXIex6Zn+vg0!|9`S24|0XS75|fi_L`0 zbBQSqJpU84p=|E0b?n~`TnX0sE!~}sxK}6LW#(zhY9#NiSD_`t*%{enX=2b9UybFb z-=e{>nwhj0T?6pj1k`6yP{7aHxJ#xlgGu*5VH2NP$H#0qK^mevjJUKg)M+!$bg z-k@h1_Jyr?Ut_I|^CUbM8a{Kxu(VG2G)?5R~ zBakSnUQdfxf!HJ;MSwZdag0 zK1*R=1V$IZ=a?|}e+*Ij#rh=WD(3o-qRb+wnl!D-#jA108C0!Ci2>}0jRr{>jfU4P zm**Q=kBe6$J{Mr$Y0z%DJYZ2LnqJV4b*pBrYS*l$sE&6VHtgCUvpc=jL1jH&iXlcUyx(w6;9*GI-EMwjb0*fH zMDyP|ZQ|=tkpI@0i9>7g(ZF>66x>yab=N+;6NsM%IOh3LN*zT-}JKRx~We;kvqpI-G({x%NNvYv-+6 zsH!3#8Zs%2P{mFwa{7?f5QV$XaWyEmEO`*M0cT9p`m}1~3?YX=#%0W~#WMRRxFcf7 zS0Tj7!Wg3oOS+430e<&l97|P^bwgr^R6&+p7a-#e6=@u@9-&lZNuLZ$3|_W{fryH% z7s4nc0WaB#GznOFbZum1DAFt%P0U)^+1QoVt6*tC9fQ<8TD)=GVv8u7B`bMcPgaqw zL%t66RTlL&s%#tbAar!HaI(Kwj4=%U9Kq*iE!%=yUN<&ul4pb>=MLEq?gA08GTqkL ziNkPd6**7PrO>X$jpF%3KFhcxADQfS{n2#9c%FF^*)ZfyrmAx+QqVpcBhITz?nV0N zuClNGFY!7ZdlE5jOk}gbA*1wtfvCKxv(nozlC;X#g6iHQXz(y58OBo%x!_S&1#?T~ z>LaSdtAKZM@tzI*jv!M3G~}_90Sv}Hut7oCs+K^^HRS89*T9euk+79$7N7aB$mm5k z-@26{s6rli@ER0i@Ui;R=-mfC4bqH{W5T`NG&sXFSuX7!co5W6L5<&NsKu}y=mAF} zZ4gT!1V|jGh|SeLOCI-m186=5k;3afenP=)!i$Hp#<9uRZ@ivkl(70LqOewxSBzt7U4DFbW+4SV9r!M zKF*Lb(Z~qq!4VPYf-Mhj6h_c;CA_kdj6>4M==0+62QLmu#$m*D&>815HfyElG0QF@ z4mCofYKVFbs6?9)_RtZ!CUzUrOGl8(zhFprBKGmG7@%LA5F2f9jbr?1a?By%Z405` zA>)G$H$PTi6$F)Sn%~;0XCrvOkoB_h6JklEpD8|vQQLUEVDw#5$~u?juk8kmsaOKv zG-B(yi+%mBEcC>54r384zjZ@W!eUuA`~?QJo%|nulKgaP{)aR8i^dsnp$OrcE7DU} zi5*PL?oR?n%@W`V0OcnbACg9!4A3u);x`=~UlFM8+z2l#MG$^j&m@~e{)4)q5}vO& z)novRN`+f=w2`kQ9u=1WJDGC$ETTEqS4*rH#u%!YHtIJ6ue__(DFo444s zT@PhK-jVa%y@(|u^zo$Ri@V|MpjbrINgur4K}-HgxRQr4cur#At>PYOr(jGFvR;dsHwN~!dK2kvC~_6;j4a1ydIQ>ubv2kHz+k*df}a)2G(|( z=*hc!Wd%9kW1Je;(u-6xiF6pUychY>*Wf!U16RA$iV*O(?Qr>uPSQwoM=#%?>~}Of zi;B#|h{dUZBMTSF>xJL>%T~H}_(}WG;;S({$>u>**ug4$UvUSRiD+8i+Ntcv1P&1f z^teC~LS3!k{=C3Zp*D8W^wWMqP!3S&EOcvRe?f5B#5Ha;xGxGW7r1U*nDQlo@(3ZA z{Q?yLYU=K7Q}&Yr4+MnLf@iw-aEkb*ugiw&v#tl432yOFbl zVwxmGB_S%iS*z^|?dQ`@Cmw~zEczaX5u4;dz8B6ixmFnSEPdt#d*p}hzQhvrso6_( zS-;67-jc>MJG!uma#p&_EZHji(+Sp|Q1+6R_9JMY5n9+Jix}S6yS1tYSBGmn%o{n} z6;}4mLUs&!Rq$O3&G1=a$j$bbb9t+qBi%S81O|lJ6Drl87(*vblLcFv)B$NM(Oc!kV9r z0c{O>wT#Q29u(RFBNrA4O=p?ScV#~$S+XcdtLbQK!wvEF!$PX})#>znJtCwv0g~(K zQK78MUfj{xjLQIJc5d$zeK&dacg5yL>=UrkB6^Pru{E2;Y<^1@I&7XMupdwGme@|W zY8_cw?9V4ysoZAjs0`PjGTF|1u%RVQw1FwtbUjP4hb1S#R-!sOmi>)HVGQ+gC70rQ zc%h>GO;J}#Np%~Vm!;8*WcP1?UXj{d>gkvv-TqdBX41CvAi{TJ;d3ba#}f8{h+R{1 z2^fz!)@IKyVWXLGtj(?!oY%&k_gl^)OiWppKcJvKods)e+5qH~RY9d)r9P|pneCZvMgCr@Jb+zE8)yCEZEnVF` z4V!wgx@ON6l9!@&OX`>5s)G5oE3uM-&Eyq0;C;fNTJ#MCJg|Tpq}ff>h^I*Qf{v~& zcxMKiN}KqCnO!S*^kh6%XfF^b7iGy0ZlT}`+;V?paP}h6+l}N=80rRHMjad~RhUAH z(}JbwwBHU}r42|?i#zB8&&QWlx(jeoCwh8QqOC#Cp+k%}kvMoNlB=i_W!oi|UyBk8 z$qR7RY<;b}vS&?V$+C{aBDR(~iBgNZHa9A3(ra*Pag!-7zL=7$=plYRoz(?kP>HMH zcE{@Os*Tmx4Ur{xgY+6^xuuW5QFefyR+N1cKjE&@&uE{AHY6bg!OJ%o`u4d#OFxCl zGJP(Gqm;f&>38t&j2CLH5=;@bF)7|_<(oqOMj;lyu7Kb2TsW-dgG%u8G=+|UBl|`; zCc!ZY4s85nB+R^RlG#=bV_R>ef7+A&Tg?B5b{ZA}%ON8!*;2~{9448tfT{KyP=-m$ zEu^f0SdJMcskex!w+LVb6EJPU;5DSyvd8c}oQXGru%wPZ09X7kG)MIZ`NQIrh81uKpk-HcdhkQ{IHS6 z#Nx;5`#x+XhGMO6{T@W56%o-1(98s=loFI?39?p51pi?CA4Z_orcd$ofkcpS{|J_C zN=g_yg5#LOLky}49<5fLp*V?y>>ELpWbN0WgJkV*>0s85y-DPF8`FOL^m4D&$$8mM zBYT!GGipuP8q%@pVr+CJ=w^0~V`g1zJakf-%{m@*_m9WEjCk}fW3^kk<#{m^_n=|C z($gSbfW%EN#R0dA?*sB=L_{leDHR$oT3gy&~Aplt|cjYPWQCk0d2KcVhSl)(8$wt~Bj7wn+Q$LhPNkY%yKoCCdwN<>gy zwNCdDWQla?_v>=08??PlI4PogjMysVzV+bo5UI5$+&^m%WN0l#^aX?Jr1wWk*ye12 z4!V#MDTVZMprnxALkA1#OK{-h6;d7-=OIa63fK=j;Q46`9;|25IZC|@tWJq%nG%Mf z8zauHo)xR-D(gA+viZABBF#6U^URI){Cb3}6NzyDL~1d-I%_Ag9$#QkC%VdiLlWw8 zh?j(#)Sp2T?H-UN(SAb*6K&wlBH$Rl>>NCLGmx|7$=y9&Jhy6oqBDqSZ^F4#_cyvk z{S9R{qP{T!qo)sU(XtJLxXC!X+|kJuullo+603Sdke`N$m@FP~gU1&@Iob^#uK<6P z8$50Y+P}f$9WuTD8$90kg&nrT;B99%%E~`~c}L(n3~!IN->xT8jMhCBkrN^q4rj4~ zs7R7-m4(yKDKrHtGMDN&SsO5;QIUCUItsFQN;pzOLMimkh6hnS7U2bxk%cRO$ZqeT z|6ZBqs_d@x*}a(K;67FtXJzZ)@d&Sn3o-Gz@1Jh2kTuGT%Rp>rDa7aWvr=S`_H}nL z$oH^P%=N4k$sfgQs5U&nfXrAa(y6T!>7tdQ{K86+zqC@6Usx&fmsX1W)mDmhX)8s+ zc~**qjFqCWh?OE;o|Pg2&q|SiXQfDhR*J$wD@E;qm7;dQN>Nx~rKl0GQWONO6g7rc zigal!MY=pIMFL`_NJqd*k)Ug(NOy*nA`!+)Q9HGjBHgZ)BHf;qA_3n@k&thtNJv{L z(&btyYPYdc^a;L6;(V9GN7WLQVWmg}trX=~TPf0cq?O_T`V3ep685YV3Ak2@!f31% z=?+*a67;PU1CVE>NLhlNF5A6=mB(6#LYR+ff1t-Rkwhh`nrf)iRkQb!8ZwZZ)wE1__M6>C+xv=iuJY0wC#u3Z{C^Uesv>giTQ9G zgrkIn($#>I_m0nP)^4EaMXT#C5vrKAKp6leB(;UgXN(PMy}@bOXY1CtW6_JDO;fOXgo z1N4D)C``UMG_QaS2+r5?j;NGwev#-;Gn023?z_}ugWA$B|3&X+Z zn4_BG^t%8{>8P<-Jbp-6ibsvb^6}W+fTeuQw^%?*?!oOEQb6WgEFmZoqd2BO#?6-? zL%S+RceEmN7g#JCOTj-HMO20X)IO z5{gWh7DRFh5(ViTB=0rk!yr%Bh{&(YdS1UERI11Vm*Ec7iNUuT&SFx zqnw#z)R5_hiEYz8Mi2`e?);#xYr?xq@v}C(t0Jm~Tpp14)eMP^5JgmvF z@VY?JaZXV~(gCJoln5zby8{J~lGbhZCCze~f|AJeh+(4YZJJ5y%28Aw8ro6;1M*?v zEq<~w$5tVnWPn?cb3){}6NN|@)Tt##%#*s((Mp)9j4Mo-%DBP=p<7j2QG8cIT~`rlY*l0l!&+y=RCwBa z&C_O>Xw!huv^K*;o2vJy>*+4ETh)jkIqV?H?MeB*8^<9KT>q(;Zj{s|}CwW@m z_>X9PEb^zb71o!^+Q3!=hC8O#56&DCwJ;)hv!EYU#z1FkT92WPe+9YoW5jU6nea1Q z4MwwqPD?jLZB{71$>49^J00szI~LixUH_Rh|J@F7n!AMu=HEX>Zli9x5IG8 z0TkY}%R5#fCJ0_xo#zR!+haJZT;5$SZ(I$=>nC2Lc{Z)HaiPsiNhxm5MF0(ht83Rm zVR5?uj^CZUc$` z&iPjLhR)ueCgtDKsbO3fBKRptf~HMfT+QH5Y&H=Y>l?8pL{R_AYFoy1(O02$R=+R4{*m=7rj+gc2yW-EaK`#A zrI0Cd-B8r@_gYHH@s?7^Z>!K9k$*3xs6kv~_+Pt}l8eX(mr@9OODP20r4(T_ODS{* zmQo1%ODO@!TS_4=xRf#=RmXV?>}tfFK$q{uZ1?MMoCpUNNj$$11`-P&G?u9ef`<@7 z79G67QhNCRM$?=G`T<-8XnF_R`8p(&Qi3bsze%T}Q$)aCPXHft{$KpD3a!yjQBK$? zv<7Asl%Q`JrE+pk00QMSfendSIkR)>iqHt>15bxtWQCoa9N=vWV03_Hvg?XwqUdA+ z%p*;M4t*iV#EA01*<< z$&;B72!T9^ykas550PL3)>^ee#oAUGeAKoU6t%AlUZrYVz(>99Eo$4_Yb)B;+Xok{ z+S~T}t#!`&?|tT+2~cbA{eHjii!$fG*I9e*wbovH?S1w+bB12Wuze=Ab}5~(_ym22 z2t4$Vvddvvmy6}B8;QBXQ>4n|-ST1FA^EHZD+V>DdkEAUGkS_1SN0(-2GX^EgejI) z;L+ddz?m)s3!UYa!Gzhaf();6p=Hg{okwo^Mxlu#gR6?+wex^vgHibYYM-73R&?(?dyL{MykUt4v-1kTw z2R&2AL54f>dU;cZ?HK`10QAP#$n>0XT-yg@gHwRy4@v0p3V-V|$c{4#*j#Q7-DmH@`rh5lhO!5!ukF}`y>3{DtK zaua})A7o%UK|uMz9e|V}kkfc%U*tNB{dlo4+>QQAyaaa5r6#sHiLRk}?6MRR#sAb4 z0(Jl8LeOLAiWCA>@s1K!vfEMO9RNMuL6PB&>0XFwJ9RwuP90C)5#l(_9U-J^-_#+{ z&pQON(siVya(aZ<8&TO*l##?f9$@^)#er1xoE;?n-iL!=FnWFn0-1Yes3*dQx$)=> zgB&o?9k6uTNtg}yw9kVF4bsqYg>i7p$l>PBHvDcNoRiXHtSDur|!z3S~u zvjCD_b(c2u+m*Z=GV`~MB-h(>#)m53JRMt%WBod^U<&B>Hh#ty(vI=ve zV?b(93``BCL1w^X+8%78fwG^81?ouSSz03T;vh$=dzK*dPAQB~S}I9(X9;qqH)EI=_SQAm_dV+2ovd4LDdKvEt!t+suLkBA$ z|61ol;}RYM6FftJB9hXX9zIme^%RMD65^EyNHDRP5T4>sh8MZn@?y_|!s*dV^k8w^ z&N)Y?^h=HRS<}lz7xF)6z^R@hoxR*EC`F8C#pI5mX{P3tXRxSzGhi%hx+x&D&JdED zH)%j!naV?JsT2_dDkA!AamCq)Ly1{JoUkN z>YF;AFa~K{^Ex9db$Ipn=G<)UUuTu)&Zq-SEKxEw<0r-cgHpS3us2ADcp`hKCz3g} zI*VmzSh@>a9TzkzY0yx=4fpDl(&m{)F%F#(o-n3*XL*WrmX;@S6%ky(@&d&(L+}D6 zYu=!Xov;~&kvlHvp!w%l}29<~$HiIK@O*CU1$pcRZ;kFUV;Oo5e~>>1%slbH9bBYxVRZ3mKPz;~;3MO?V_}BT`Nx_ill^PN@6=nN?{nA@H zO}aVLTuk*52g;egCdB)BMnTHjCMBl(n?T8S;f|SS@Opu+2)d0r&!qtehUemdl^yI+ ziHfN!9k&fE*UTO*tU8ALPr1Tu8Nzc&t_lXIF!Ja_i)ru#s zc)bD{)K#7y;f~BfDmnwH$h*>{jz2T71{s0zdY0DQlUF1moGqG5BB7OxcfZ9oQc@7D zX>{_U2662sHAhPXagp>LE? zw+-N(c4;fXTrK+(L~4BWN{udOKai7VZ#QyJa+yPcm$EO`PrKMN&(h8yVu3aX%wVLj zbC>7oHU-9!wX`JmO`fzOc2}H3-1TGHS(iH@#}kWZm=OJ>=3M_m@Eo@Zx}b4^)tfhbJAZ28w2Dxh#r5xIJH<8ZsRfeZXHuN%~ z&u2}Or)&_*>z>$3&v3WWKh||^H`;S&_4O!B8us%jO!{YeigeaDqdN;;7Bavy^af&F z&`=KMUP;q>O-*ySX~Mm@8ES4Y40CTVh&bO4pJUVa`XHO&EUG~s+DuXrdq9$cJ z@rS#|I44i^z$IHx&l$(;4D6S1ET+r_wyb0*lcX#x-Hy$4?{xG*X!qsabkk9eLS6%S z-c{zdm*Gq|cp$U~#*0^N#~@d2T5)@akYkX$HALR&?H%)(W-A(-z;tKKui(kGV)wiK zpK_63heVdK;FWq~3baM|$+quQ(H8u4H zpR6LBCbNcNKg%i7K0kMDwvk1H-xGrF?Y}`JK`SuWd!KKJHpuA`&yGG@FwDD0l_PC9 zv6Qk!nKHoq%SO{b96r2BNm+_>)LEX3hTVd+?IhJ|N_ z^WLx^znj&7XZXqNFDvFDx>JLfbDm9ajwHE(!Eusu|H5~tHFY(RGV5tqdo!~R-qXp; z^vH$3Z+c>?^sXJ85$3KPNCR6N>A6axQ3==4{-+rlGK~7*lEAZSa1%_L(DC-B;;vRU zcViDTfA*9-fjH>J*IVXpm!mK4c1cFyJz1So`XHqHBBc9CzILkeUaaQr?{`r)Tr|LQ z#;G?Ds|lVp^u6A}slm(h2CX!BEze_pDCwn>(lE1)>uz)8h+CaZc!mr+r!bsvo6ydJ z>vd1Y7mw3bIy!{I?JNpl?;S19D}31}vw&RqxerK;^2GOOcZAXADjISXqg%cZPkRO? zA2_#ueR=Ub}%C%Cg3J7}T{d7$LFPzD=47Gf6VI_|j& zUj<74v7Pk0U%E)Ha5hWnmaoaq&Ycl?jD!L_<%Tb>(Q(69C(@H_m%2P81vh;4dKKHH zMDPyIzi+MR9V=!U#av03aLyE}v#ArN$fhzfc%XRJUYYLLa&I8&r4QXebk|8an*! zopd)(#AdGz5tr#koVoq%^cUZL=4#|puGY_8bJD!*Qt_Nv>h2mRINDqDB@=pVz)cZ@ z%=nc_m;%V-ao${$^|IX2qP*eU(mJhm7j>q0-9^RJr)@~O=S% z8=g9aoMehM^_&YbH%ffBR@`}q_wV&|>DePlxt~IT;GLd^njn(Nkv3yw74G&C&8$?W z-k~mcPjF{b|H@S3?$^_KvtOS+Z%B}HDxmI%rd%B9kCIWW17!?1SjL!mO5Kk4M6@?s zxYIK3Qp$zG`QA3%WP#j7y3^!}LC6YCU}g>verS=VSzMub9y@R^BPRJ%%*S7{agsL~ z#ThKfD3Tg%*D!jp#rwdE`&bJ{m?z)6nZ-kJLb4ww08e(o1)%5oB#JZR4kynb6{XAt z{@X<+`Z!wn7M`cahoriHD1wZhaN&niY3t98E!qJZ&C7cbtBr+y!l znkKxru+UQ+9^TcOw-5PT4)!t0&Hw-J|2Yo~q<3qCt^c6aTqyKsy0i|_A31@`v#yxb zT-UUAlJga!iS*kV6PGt9CN?xCCbcv#H&lc8{3QBkQO#wojjL+uyT_AO(|dX^z1U@< z`64!x-E*?gp>q2U4h z9Xnd7dhb)K66)R1k=AGIrH9qso9(XesGo-tyVS#*!(&248|Ao0Mo<>&E&;I*!Td ztu4zYPR`Bam^|(Hr*}@!YiTI}>CY8Gy+s<(7ux8%=Y%N^TM{&;1g8WIozp=>nA)$d zt#74D^ydZD_4HD2O|EWDG;)N~A4ztDMOsVfv~jF9SEuM+jDZ>~zjRNwr{o5Q`RH%REnjUx1yp^!a!n(Cjg)^?}?JMA&* z`&M{dNIlt}xal@U5%#ZEM_GAUxhl2?+AVu3?@}*Wb|QSJQ|5wjaqcC1sy zV)h{QXnX8!wKcTw!5w$5Q&~F?O`O#D(&2~RQ+;>ur&kBj2*~Kju*cX7DD0D)6BPEp z2<1AMN8+2I4#E#O^nVZK-mH#UHvLR>j~*mA(;m3r-mCf_QP(H7+aK(=8^hy=yrYh7 zvX7{H)baiH9{Uykc=-UGvLCZo{PEW$>#a@P#{G)hcxw~4ai8Kg-gf9;RJq&UucYEn zHx(x7+(RmN{&qFcj=ijM?SnMHW9qM)?VYMKWOt~CZ%7nPyL0+N^@H&4>x<^c?Rd*d zd;QaI-?J@z9w{=|&VRbaj)o@g7)kPgi^)u>%buT%-IhbLOZfS68{lMC(Uc7O4QhhbNdw=JiPSv;LpIht)$rHo& zwH!XtHh1f)$|twjGb-OxncBC78TKgkd&@rPi1xsLGPpK^X zsKXx~JupLkXY)~#8YfGnsdqPrXNA;nNPo4Xoj&g3k1>>HpH~a*Bk}d>MQR{CC0p&;WFI8YsNHHKpADZ) zgYQ{NM`7z{G@wtC7M*GRq%*xIEuKaWHJQdqjXDLAE;>z~X3FztGf8z_3?W@SMvIb{`86|b>j2Rht7IwgpP>Cm#w_G=$dcrx#m{Y zl)ps{iK*s#l@-1`M7?MaomkW`ZF=WL_GHzcdf@s()qi(5chENb>c``}iV0;}`AZzWG04_-lIZg$@~jD3qe%D%@Qb@*O~<7kFGc31NZ`@PPa-j2Ujv}=jl*bz@APjq(1Z|aOM z?2Jz^&o#aaow@s}+S~P8bryA683+ebqU%P{(KiWd+i;743 zx~1IsHYyFI;YTN%dD_Y9;Ay70gBGFdW72T`TO_x2!FdrsH#V}skKL_@=#nI zwT`Nx;RT^>U%j$(;-rS~1%ud_L;Mkr4pz z&f$E6uzQD$!XiGrcayn+Vt&e!*2D9P2strLH65!{F&OAKeHh@ZF=L0 zJu174uQF&MxzZlkN_o5UnnQGgW@vj)vWSv%k;0 zJBPygAazn?U8MV+Eo4SJrgHgH~;JRbe^Cf2xSyHpK;YYrsmj%f8^*1sj<87Z0S^e zcDB+?aGcf)UHcubu8aq#+hZ&19<+zWRr5|Y+U^RE%Lz{%qN2R^9YxDiwT{u0@PyE( zE-UzRL44vQS{o)Sx%&MS(tB=p1i3TMB*vAy7Tv4b?2&KmXE{v?wVv1C=Y-D>9siHY zD`rgUd|jP!{0$X5s>bK4;W4!$U**)RR(l}LgZ3~Q|M^$sHRsvWCr(!*a<}m!rk)vA z&;?$H%F5k7t+kPdMTiFX_6M(}_0>3gq&>PbNoWlv$z>hWTeg2AoZpYv@0Wy*({*TU zrrMaW$F(`Nx-uSmr}nVQ+N}n3P*#npl6`9YzCHFMFY;PG?iiw)V?T4-=*sxc+i$q_ zoKJfJA5>eubLgG#B-_b%+T~ZM-UsciFaGRF)l8G_nRe`uU8xGgV?!#JXVBT~$s-oc z#gC}<`&4GWYD=ihdJ;tVQ}&$;_D}hM5@W7vDpc7C=QF=yL0QqFm3CY6>-J0bu+ElA z6N@S-wLI1ww>#Axn+~cE)p2#pri6N*7Ob~!>Y{Q7mGkLn7sg);PaDkHCiDzl5UJq_ zf?-vE{LpLauQ!m@xAfSlKD;48$M9t#Lb-(Y#b2+iyY7M4?C;PZD6UlN_Nl=fO<{F4 zrRvAbUQh!Fnw7cBOq0vTHL1S~mf}yRna7hq+5g^& zXH@T_Pj98}p;;`pbH5rEo=t0x6?XoK{p^G+@=Kl{OZ+hHbbLRrpdR+C% ze`%02@G=TB7R_0*|HVbGS3Em?VX5kSl=?U`|Jf~vk5$r8TB(}%QA}6vQI~}$(omyo zjhJfcvfofw+DFw)dti9tkgd}%kEniK_T=_AC_;{I4_`Qxwo&5YiG$RVBdT}38rGqf z+9OwWo_}nG8lJ1_Dc&m7xZQ89Yi%!TZvE%*6@w3juRp_Hw4El(uGfA=BGvO&EV;Fl zW@9@)8J;jG+=E=*=D7WtzuWC*F?Sj(KW9H7Fln56Vo2=^Z_ek;-ZWGCWm2dpJbAbp zw0i;N*h@odP`!YD_0H%!QZS=PtuLIpo=#sFQvG5ok!WqSU+lb@Lvz^fqVPq-Deqt7 zr0Z+qZ>j;unRNFM`yDkdp%!=jvGq>>f0NXNBZFHiUu$%(D&Mh=&@o^AhZVjcbn~HW z*7K005xJ|z{$V)MFFcAoKU{IZfBWzDymN8mEKD7bCK^}s?g@3PSr(U2$NJkpDpME2d0x)Z)FfN7{Ek{wsUI z`z`D8{`C=iOPjrD1^Y#<-lqocPTpisiA|3$vR}M;>Vrg9>WOxHrvrXKKebo&ldp!C z=BUhl(;MOoRf6{Q^3{ey%J8$+skRsmy~XRB@3g0=68lI}P3kJLw=SH%#~wxNQ+t2u z;>#|fNiO$YN7_#|I~T=DeKll{T(sbNR)N-L$uHf)^To>Z3utt`(>%ZPo%vVHSos7c zutBQdKGl-1`W32&HrHSC>~GYML$nEK4^-RQ5AxQ@I}`F6?Z`CsjrROb^`g}^->#xP zN#2>HmBZ!x9#CK1d~iN(p>*BJZP|JD;ODm6pH>_8sXI5vlC7=(VXr;Ws{TMRGny_C z^Aq+V_4)Sj6iU!mLiG>lh1B)?)Msc_-6uRVq&}ecD}~gj+i6w_&l?_&_E*2K!qJfW zN;?Pht5*2hkXl8_Iy|PI%BBe@eC{Ahwg2y-+V(2CW&M;dM9wcN+J0wSCnb=hw1nQlS*ImNNlCTT-xIH*y@#jhpX!~j z*5yWu)~hYA-cf1>+Wr> zZ=ayQw|CW6a{An0=f7<~UG#Q%3Cjx3Wf%?S;?e)5L4 zU%f~>ivypYFk_o)b>@2K>gh3c-I4GR(&I`B`moiLKGW&+G434D2>su=Q&E#xOTXjZ z$iFN?)}*Y~=^9qA*4^t_y{YTDk3hN0Nx9|Xz)_)C!P9dq^OE~p;+5a4tgM(3U)ak3 zPp5#OZG~SKop5%=vm6(Gmn#3SyU=P_zFfA;PvHZTNPP}r7ep$=1%pEi-kJ2(1=lZr zzu|$)C-X?Zi1Q7Pc~!BvwN9<)OJ2V8qXlT!p!Xig4u{DLACWJ@)}OlZ$lrbs>|@@< zl2H5@L2Pb+d2d0HOLZ6#rk`7M-d9cmM?UlgQjOz+McugIW2nT&&^@+Qwe*JLS~te6 zL8L|4`tXx&gjPNOV?AX2Oz&}}-!(q<*!8)Yg4J3WAqUXSl_D#@Sc|%gI+o>`Wd-gOOvZt%M*q(4Ux#}M?JgVufoU7N?%I#|EevX6Z z|F7te#HtqR4~cJm+x!&0;psF^%T_!>wos(s5eh}s8C~{-O7*4o-7EL6sH7VuYWh97lI|!Sykd-Ny|4)%1YDsndu&8sJ7e z?$WZ4_rk~hL-P;Zc5PX_p`l^AT`;I^zz%zn{eT*g2+ta#>gyys;v*@Q>>zgL$nZ#o)if|ZMs&^>I>Eu_a5VoGA&rdMneO&+3gBJ8^+`3it zgGeo>?g;kzNZ4}*J!LZ^93m@nsAs~~P>QSneT$k}>RM~pPHg61{B;d#qaTiT9(y4z zQx;MuORb*4e2T>>;?aMZY92*kujRpOKcYufuB=xDG1_VwSxGn4Z{Zu6g>>n*k1k9S zbnLR{ciNXf>D;|<=-gF1qhh|jy68RHsZxiDp?4SW*W5!FV`nGoRO=D7jvht0BTO5= zIco4u+KVjQ6<2hLS+5=m9if}`KiRx*jT&0tK$~}&T?^C@I?;FEd^L*i1n#6u&0Mvv z@G^QsC2jc5Ch9?T4gLG~%}1ZPfi_2T?Y#HsLh(<0#b?j_;WcXGL6y66(F!%@Z1&0u6K1yWxcv3%)jkdBhPs`lh4u!bWHoa4y;dDAaZk$ig4AU3&G^=EpQ$~m(CON&}n)$t#yA6c|N9(yOQhUC&B zfVfxuN)66cSH)C5Jtaam_vucCbJ08QPa%wdN?gTskop2^aSFO|WKO#&2_cISI8t9ogS?!-@ zZgJUoQAayw+>f3on7ALKwGr+{ryp-QZ0~B#+kPi)9I8IC)|)6*99*}2k;*QlTPSZ& zn?8Bc{KM;-TNX4-Qi%?7cGa>eYIvb)Jo;i=B|Wn=P_@t=f9x=AbZo6wtw+@bc79wn z9#@wfQAG#U$Rm$GT~vN+^PZ$yOE(gBs)m?4W2dT5gfAf9E+rj4`9(T;Y&8uRnJcez z+Nh<^Pp~g7?|d+ERbvZU8$sRFU8_6b)ngjI_ z1{N(VY1Pp-@s{(Sp!|C)O|$$Efv@26UG8|soAcEdLmi49f!snOJ3@t2h4cuI z9?FV*WW_FC*lEvFKc^~Rqblq23FfQsQ-Oj7l^@rl#zMc1n{3-7eIO_=eRJ)z*Ti`r(Wb@g9V z{bQ=EOEn#&Cx>B2ITa`<;B2(peZ;~O5?$5m5|o(#&Jf5l-t zZ~DCHRkUw>F1+IAjNm2^*W@^N*3$DZV&2Gx?d+YxjmgLc^$ zlUkXypvtF_vS)`w-^S>`J?UnZdz>cfy4Nb-qpQl^ z_2kk|Q8@qmX3Fwok0%#4sMWbosB@j0%CsyTX1meN4|jwQW+ao&=3s{NxK_qr?+K3` ztj>+Srk1)k*olnobjOeH+>#cFjKjO^6?N`y=|Xn*O|DP7GN^AF9Ife=_@USMam27H z+)1~u?3?H2(Y?W3^+Rj-p8cv%qV;QP!9MjA4cV8ie0BcuqPj`;Alywq^!iN=YGv21 zL-cST-Hd#kANtx@U)0jNVf$fq))87D(4FnfLSDa8gxD+S2?P3cuHhOe$%U;N`uv2Z z3}=w?o(o+SnO}UOBw$@dA7N_*eSVTneXI%N@BNYi?S6Li6D;l&M7wsB3cCB|KuT(% zB&nC7vLlb*Z&6vH!K#fPpMTxv2b&&Ux6`>;Bwv2ge}hTjNAyS6qU%TY?Pc%c4x>M& zJAd*$0U=uxKo)v|oS2=J7v7VZWf$}bH#rC48zIM~10oKZC*|2$k?`y++p3cCUOAuZ zxWck#W@Xs&(7KvQrjq! z{!Y8Ozn!+_Inn1GZRmB^5)a|ROzNoT*?l)^biGSrRH6*JtX&!E z+McIvM-|C-^gTDi%~*UL$bY2o%^Y9bI6k-Xxa;gWJ8Nn9sZ1JU&r_hjKr#1S())XC z$~8fvE5<6LBg=nNRL z+`)O_cFqg8vE4Vb-P<@XY~{SrY0u7TQY&aAM#u$I$pv}jg7M^nk>r9L$_Uw%5hNS9 z{le|Rm#8%YUb3*WQpCb1K8G za?*=6n`E+n)}#o1SXNB(S^9C(6uvdhI4LAiJib}Z(!2l`-$N1+o+dB|aYfnEfBA$<3;e_EO%~i`jF=i*)IM| z%~w&+xR~2#o*5+0xaRszQh%&l-B}+neV5QL6*|dv)*tmU$w(MG{$&0)h5y#S*`IsE zDzC?B1mMZn2O~(&SSHysGva7`h4ablv1lvSV|;$EoWIhX-{?Jmtef*ZUb%kWtcX+d zG3PVY-%a64kG~80w5OEZ3efXSk;DDSf28L+)`Ru_=Wx#hpOkDrf{oXT{vgDi%Zu3O-dC9&npwKNEV-(W$~^gb zv4`WB?d*!W`W2gel-BQmO=BltNI=f95?9VRGk=+W4&UV&0ax{z?J4ox#edz!5!1(K z(KwK&@pd@e-Sb~e=VQd*R333SzbyRH-;wYgy2GPpb?jcJalMfhZoM<49$jjc@p$Y` zKOQ#+sUDv6y2R9L;(DwPpWh;K%jJAZeqQTw$UN5}+#c6^Q|fU${Kxd}uBZ8j)$tII zgxg8^w-CR6_J)PiUw86(UfE0hc#h?W!+p~Ew`p}Z>&aQpHGJBYFT%meL)@Mfi#RR) zS=uANIq@mix3l_XxF@>PoAc0$Z2FML5hjTo>emw5M<}FA4C*B}j+rk{_!@;TrJw3N z{WPnOx7XZBiR!Q(EN7Rb+0blvygC(WDEUYW?Z7DpV)pS*c7xX*DAQ-Hc0K%Uvw;x|X@}o)CSgADnex zI3f9SP9GW#&W?jKX1j}z*(C4Rq#y27jY!rXXH6{QgU#No7*QmN1&6LQSVKu_Y+^e24SXF zu@B>HBz5N>rrSfvuKI{0=^T*<`kO+hq2c_2ZZ$-l@>MR`85b-kD)gN~CqMiALo4?b z{}lA0t)mpm%szDGltOXWg)IM=$p50qr#P*0f-y{TDOwBNbn2{MnZIjA#NjmS@Vqi& zoJ&hKC+|+6v&{FZ@O>sAm)VN~a+fx`a&cWkdc=rvcAxT8xx0jKyOHbiIistf&wSAr zdPJ^s{YJZEh0D2 zztM23zwelJ75(G-T~hzizxjHd_DvVk((*L-G0|S6DZa^P% zL2a;odFvwFoHg3{?yVWKlxYMx{O}Xm8e^7&00~nd}V3tYOA{1y@^NfvZ60z($ngR74%G%Rob|*?%Mi! zt7{tSteN!G&9(Kj=m})2x~Z=5B6_J;bL$%Z_FA>`^dNmjrP-<`0sJ7jRZ352G_GA! zu!^3vT3xp$VJ&D}v$k2cTtUxI(rJqx{%oeFITF_Fnnca)#%8Luwt0hAho8i)u5(_g zRo84edaxRFp6XQBG&NQ83$a8^N3{ht*R5@y-?(OFT{GHnjhIWX+A5)@n%k&4*Y5VN z9!aNX1NfUJWJ!xvU9-BSp_;#ZV^N*PM1tHSEtV!~mal|R)6A^3t5*}ZV{tlFoNB`4 z)+%4ak{fGQk-ux%6;?rQEjgy;+WM>L?&5~%TDr+-Ikp8{D1GFsueGTqPrEg*rH58) z5_GS&)aiV8;t*e*SHD6m_(pFQjrk16&SXZrIUf0CESyH!rZF8+Pd)2C0 z^p%F1<>U%_La1>$IjOpizA@6+R#)wOYoxV_kBK_h2Ts4CImavAs6s-PQ+!o7vANXY z^XXkvbsIFO+;8e2)a5QnhW$PHk+zxZ?+UnLOMyRoT)mj=B z?jtSqiY`)zSgB>hxNLdtY-5_!JJpG`WF0@o;;2!xjJ{A|>ea4s8em5-cWaA}of?C0 zYUx>>wQJVU;3cbA=@yG#KDUgTmlCx?>4frw#{iKp=DD2mB&efKEoGABE6BhWl1fVG zj?;bNj7dJVx@HwUzU8XUO=N9dZFLKc z5NmyX9mNSF$V>57iUfy+zx`Xijsmr=dU^A5E74rDriF$RXGCEpf2N5_Imxc)Z@*Np zaYn0lNb8#Bx_WWCMX`y{tZ!YjoPEdvQtf`f(pt8lW_^^>S6zY!c^=wz!k4ln<)Z2} zHLLX~;hNG%+#_ITHJjJ2s&*_OFMwX(T!-GTPT_arblK{H1jXI5)&xaLZC%T9H;sF& zlcs9iEC{J?$Z^1uE-lNO8=GjhsIF;Q-q`5rYZ2q9K>F1;dbzD-^Xt|$Bvx3Woz+s;;7sDF z11gY2prA}%G%L(0zh+k1ylbziu134AfsXoacXDd6>gkP|lu6xI*nPecLL@Sb-ib&< zgt$4ngxd|TG$Sb0lPohOH;7ZoL)9$KH-;snq_ja_z@^2A+Xe17BE8cH>~eGLDfMwv zDx4DR42q`4_3p6nCeN1EdZJTy<CV<*e3d2~|t-+!bTl{L1 zHPF`DRkiqzfmJ<+LM?igv~bn>I(o{~&9$<+NoAP1;Tq0@elO{DYm*4F%4i`>E4RAR zM9u0ZtLd6DT5!_hg_hWerZ|3sXnoGt;G|&9t6y_ z+`^FXIO&wvG_MIqj_f0atms7oiw(&y<}F_>Wi{m_{q-E8zviFP)$}txD=ohun|om^ zFA03PTo{w0SM+czz9L6v>rT|m9#O!r2`yxm{9NFNh6MOuLh5O)w-g;Tf-6EQ9E)#h#GGyA>&asC9uyGH|{2OvN~n0Er>10&u>^S-@Y=4OToR5I&`v zDGE>l*8L7vT6WOygGE99t^og~bAg{HjlJ{5ru}lHAD+#z3LJ?^sCYzF_MUS%JRg2J zA*;$?ok*Sv4qWYPJ!F*!Yn69bt5s^V>A?33Eo7DYC8hHax)jwZ=mFso>L9-);_~a% zA?%hjk)Ul0@lU!{{nuK7-aAWzlx`C$F#>)rg%PFY+q8~=YlP(L zh*GCv1pL#@-lkCse@aUP{M@I#j3^xtD(MI~?N%=%N)p*5hcU`F#;k0Tt<`-1H=f3eiez*yXabC1cY;4MwH-RVg&TM zIymx*WW;@6j-0H4|K*UH*{-)0n!2$2#FAX;$vd|hdstbqfY(V0sCzpF`6z@Kzz zu0IO=i42;MwFK~(CY1s1(}QTqKMOpfN5PW8628!$WLdtylj*+Y2542aP2kV8YpQ-B z@Go)2B6ZHwuUWNJ0IG^zswBx1){XlpC~j zqLXCUT&5#+&#tc_5EtVkxzM>Og*^dPx5t1ywXAn#^9TDdgk2GNP zb%xbK3!&jjbaEF zUp6EDmdz;qP>3WR5Ejyazh$$>ItL=GA(T@X@TW}!_ijc3Igc6u^fYj9pnp6 zuAMNUW7rVMKVpb9O9l@z3z7WuHj(@@G?6eDKdqBYIR+ZmXT*i^^pws!C-1TZoSk^BoSA|aDtW+#$=MkkWLH*y2c(u-l^tcsws0xMx&{YfUqvW7@OXH^89 zRRL!q3sFTl>+9NC6+veORS<3am7V%kQiYWzEw=Pvy}w1YV{|)xVY? ze%}lXz#aP9q}so93|ZB-EcUV5BNChi4-pAYf`^FY&!$8|L?KZU$)6jEJhFFF#5qMQn2}&RkuX&wc8K(VgwfaZ#9sZZz}F24VU8G2 zqrqX(;Hd7KDBvZc6lJJaH=}U5)-(pV*~|COQn*IeXlX5q`7Lsqz>t7#Y0Px^VDnSP z(4g&6xB&q}(hxHU7$OBd6!Z7d+v1r&84m&4+8J@cbA-fG!i$1`soA1{|D{RsV28*3 zy0b99@=Wt<&osaKP^?f|R95eg^s)y*<`7R+Gi_G}LK^MFwS`f@4k7in)Q5LQoaTao zK-wVy(9s@#zr{VQNdDM>&He^yRy=7#kLXB>0(#nhPjoGn@oYv@U?VTsaNOT8_mSVg zkQMg}PuG>75&!KruJ!lXf563h_!Yk;#+}ec7I#-`psrONtQF{KaF5cpqJT4nL_K#* zyyqX?o>TBO2DIlCl*TA_``bSj(uS{J7YYLCaG!QX6cAlPZU0s@hFXsqZa|Nw;8rp* zK~rjOvye=_2?R_~$vBjRMid;-1kDo3-yFw_zrA!ZG)sEMLrpttj-icW6dNFc%hK!E>tLq!sUi9C_SL&FXb}#gt^@HEAXzIdS9~yLVs#U z#Hlq;j?`^V+4B*RQ}Z=TK+1J;s;zsLgq+&0S)#ZIx>#TG2HJj5mfPRg`)N@`(;a%- zGf>NtzZ^NzEi}MqHK`o%%8*OrO|Oz9O8i<7{-gCUAl??>GPeu;X!td3>D*$(EQXKG7ExZEl8Dj$L^h-p*bS)?fc(E2#78DfN zg88ion4xP`1EMw!Dt`>6Nf&Tso6!gmR#UBS%Gm>k3lN$R7h0ZWloEb@*ej=A(kvx_ zyTUFP^&BAXM!T_((wRLpBVdV;Tt<}Qh7s_V6h@RjYZw8)n!@>C3P!-|4cDnu2w97v0d%K}k^9>H^^S|`i?mKv(CJFuT2)YiD)cL) zr@7&M;3RIDrQH$-G@e=#^wbh)^=GYU9MCAbB&g^Tzr}N<<+#=$x>8`mkah@sz>vQVlQHvW6TaJdBYIaFFUZm9^mr2=j-KB#~OCRzf? z^c<0$tF5ax4X2_kDbkz_7}umqz%C)VSp=nhh7s`j6h51e z314!ZDW`~p1t07n5`;fsxB#Eiq*6fGLlxzuJ_Kd!DA*=UZWQPm0)iEF=Xxs!`wSJq zMbCST3glog8IyG{qMqA}-KhnxuyuJr_^VQBq+~SedBEegdydw3e#us_S~054$Z)x7 zW&*rYNN$9q1o>&Eu!M4DY?C8(7T|4~R08;-PBlxO5}l3gK$b*?m=cDb6_*Rl(5hEJ z$!&)8Yk{g4D#ieN38|O0$;xQ8Mkj-M1Ts}f8qJhrZ>u>wWBY-P8KaXR8GWjP`cyq4 z`b^RKQ~^#EQij!JwUIg~pDFI4DJ`gBm1~yyd`lpDmIpWRk0f4b>V0YB7}4ZH?W}V6 z4b3=wMzo6_6Cn`B4FJDp8aTKSkJ4dIr%NF~bSE`%aATJ!a6pbM5ZKrrSU6`(7eE$Q z12%n7iawa9%`AoRS3L~^pQHPw6kgb;{U5mMSRnRR$&o_-4uSU=()W70p8Js;iR(`S zjiOP%8;HvmWsFjR^f%Yn9D4!X2s^zF{fl-(F{GAglaaJ^msg07YvtI-x}NU^PdT4& z2!r?yIT^MlC;v@G^&jP!QUSzEwI3D(&JhyJ(5(x&QDogA#~xN@b|}Dgmz=#{j^sYS zphaTnSLB#3wfcE_Slf5q5NOQL#U4IYYiXwm2)bWXq5;u$gJ060PThG@4L&DlAL?F^)!X&b zS#qQ)5b!chDg&IRNhN>>gyb#`Q2M@RECc*e3ZuVoM$1`{^niK{6z9y9d z{y>uggXv~D1%YfZ@RxP9lIH~)Nr749n6UJdg*nACU__Hj0dEpg`p!$r*?p#>-<2p& z6hO@Z&J~g?8zq=djDQ^}jF9L*juQf1Hv!Jpq;fzs!;KavQ9?^p7Z8o6dBy-OpRdKo z0B31Z86eu=7Gt`_YYihHTBZ$DKq%qXMZ5kZ97oP#RA&Ue}le3+gtMqY!-!i0k0mE)PRB@uf%M7VXAeIEQ`wMuz z<|+ZireK;!gWeTuj>(a758z;EVwJ)Qm_W@fmb1$>R}}CGO=hQgh=#EKT38Ga0!Y|gV6U*?h6aRz zn?@a=w_-dnM~;%#r)VvrfT)-zNSlOvi>_4y_<2o=0)8l@^iGAWhjqnbz}-S(rviJ0 z1)U0ENi8e}2m$O=V6U*CQy~o8Sz!92M z0(glg1y)i)PZYxwX3Mq|5Z664i~->ec202;C3u7~!iJEIs7ej+Zw@rDcVYE3Eyd{IcQ9w`0ZFapBIE+a~CGZ_mAkGqWid;^iMI^c?=9-PJHz8K~mUt6!3LTD*Y9p?vH3l zp!t?vDImIt#sy+~lc@-}Lz8smm1&v9-$K5A zfVKY#Q>`)$MN?+$DHt{~4H(8c7mLF8sHZN%5Ce_*fahxq%3wN19ybAu;7Qk&uS!$D zlOwqw)qbR<2mJGnaKEQ(6$5@Kq#m^ObWRdcG+WCG>{&%5v)1bjTLSosCY1udCL|uo zB}tUzJ!`ZwD+RpVc6-xhL@6RvVgy{5!idsl!w7h93Zsq{0WhOl>s$=ztr%PcpkkS> z7z2bKs8ayFvVv;>$g0w^;(*?Y!8O22sc@^V7)=V?Ye?`S_M=EI_^Vy}D+-7f(>yi3 zOSu0@*D3-0ir)TM47f)~Zdald(pSuj{e1!P&uj6;fDdT#r4Y1RU;LM9=(%PO_E=DS z4C1lPLsvL}XvUp;P%_#Ft}lY(;}AbUYhMNkfh<0rMCn3pQyJhEA-RkweaSEa{xpRV zC8Ka)XMeA_d7Nm+xd(WL(Rh}?2Mx)uF4y$yOKVRk3murv-{(-`m!b^w06(N#EC)o( zw1NATb`-uVd|bDmctN*qmER?#r1n{0GCnM=|42t(6!2lKLAVe4BLA|LZ9u?f&!CTwha19bz&(2{Cq#RRT|cS z_X){ON+|K$$N7&KU0^;T9&fFtr7qxp-C`-AErM8laT2BeT6`%WT67srb1p)o*XR~v zfT&1UnAxYU7EeRlmZ?X5)I3H+v~-}JGA$! z;O7?&Nw+RwsE9x-)cJ1-_wRJAC?GtWW(Zy@8sDHbj|Pp2&XwkNYGa~%q?vD+=Fm*G z?!Z9!`DKT#CVR0@IMdM3Ueh4p^O{r)2#3-GUGUvbqZS}E?m@S*&k3Yfv}k0NLKZ60 zddlAqetU@J3egYB5eX2ospIc!hji1+-AXsTTn6bIwHL|(5lJ+cK(^7m4A3-Jj)+0O zrP%<FE-eAPSCc9LzbGU(UHE+kS#e#l81M_4R0Zgj6r68);I zk$LYXIkGCiP=yA*zkxKlphAqP)NYFc!ZwO+K#!(B+cYew>CZO#HGNm)8m+3~9^;AX zprV1rQl^-iB}eifAS@?E0nr?J?`hp1XwV`0n{1*BIug*+>cM~~ zo|1TmFIg6Fo|d&3FkeXAwZM>1Q)1AGi~SZ6mp_<@gz!hKvl@Q0(P{8GJ({w!J;3#x z^n@jvk_Qh2tj5V4VIooQZ3>982DvH>lOrV_z~5<7Dc~_7xrqlQB~OUb)C_oqkX%NT zZZ(X6Uru2}=`q6y_+knpN zwYE{f-)mACAPk_~;a4@yYzQSKa_P#b1TZG&D4_!4@mseaQCevj0apphWke%54i!)$ zN74%rGQ;#FC~%!&14KJvD`5enO+`+GIJ9V8DhM*kPJK>5lN>wbNGyPN8*d^#& za->?{7WjfDl>&ZWlS%+z(xg(rS2d~RUj!a8BtiPHSI|?21rW`qS^vK&+*$hGeF@+Q zy=`2YC$PYf0Iw5L`Yy(I5Aak2XJFtD^xg9%fEjXglb-6UOJ+&oOnt|53E(&{U!D}^ zdWq|$@EI==1$=pe)@@J8JpsIlFx?a}L41>^eG~<}Pe?Q$?Ai=3!6gn+{HqVEq(;IB z12hf~?D1S8+;}vWh6*55pz(8?A-uuc|-*U4j96Wd*MTBO+simQ?}>>(g6= zimke0F(3r6MZjKRL5m=)NehbsLI4R{3hWhjIwr-_RSZs+Tcq`W(pr=NJ}ad3zCguq z=!(UF5Wv0w_6iI70>bucVKG1mU|#@xg#~>9Vc@2?0Q6Q2`r?4JeoSjo0ytV{iZZ}4 zLUP@MQmtVGtV>};X^ml&=Jer!pg+oy_ErH$=~|_LXqojWPNKBjFan}wmk}kSN2yjo zK$FOLM9V4x+%2T^v4M)_8_dOk5Wukk>=hP_jlI&;uZ$Ley(DR;*8&xPt}7M;LI7zI z0rmh zz?V{Fq4Xoe2$(68w%aI51N6$I6!5|nMwF%)MnJrvJiQrT5*5CqRfz(APe>GhRnYif z4I6YDsGAIoigMwGV{EH=*xe!iQV%H2!a?6JkTd>~<(EMhKvPlsvs#MoYlac<2~8>nd@`kOcY6Gr)}t8k zGg?+TAX;WUijyeqHjIGYMuXV{#-kg%c=lGGd0}km=J9W(Enq$;ExE!p3=ne zA#3QM$*0dsoTKt`om$$WJw^*aSoA-jg};w%(I#7K6$SjXCY1uBuS%>|Ysy&q8mJtm zj2->K<~Hkt&1ZgK&FlV@$CU#<4=$bj)B~!-I$LLGWHqz4(PbwGk(A8n? zR3n!P|ImJSeeyrw*2PJp^LXPQH9|xrROGXUfYnoIF__~nX`39w57)HP5FUzSnHA`TMJ|?I7 z%#Ap;X~qLwph;zbQ6ae+p!B$5^lJd|Va-wuc%deh<_er5$9`5bCCT;H=(~HgSmz}{ zo^NUZLIv8g0jxD#-Dxviv%~-+np6x3v)I_+#V0Hqq$|b&uhFD(Kq$wu;z^XyLYmF_ zkECCqA4d=Hc#+TF;J@AqekIe-M~`1vr~_XTt=;b))I0s2@k@YVC+UN|qI~AOh*O&a z4zREYq*A~VA-MsEQr&#b2zb4aTt<{OEzpdBw+P8)MCo3`2zWGw5v4yGM!=!hxQ)0H zQMyW~w8acqox+Gxi(v$OJcSXZ=M5v^M=6XbWn8PR2E0H>u8t^G8AiYjDU2v>F^quU zN?}Cl8N&$plN3gjeqk5^|C++6OHpl14}o*!=o*7k+%N*(n8JwC&4$tP{UJEBbZ`~} z{!){w0RK}+{E#C;^A|dXt9~pY`5PUrRe;BY#5E%lQCI88szOx0WJrj=-y0Gl4c$)9 zqoHHbZ$t`OUF9>{3R)e5)eE#a6@ajmy&uzduh2$T0Adijj3~8h11bPvuFHs$>88L} zmo|x3w`=X9fUjy&IiTs1#TauKQj~ZBzph7D6wo-f9F8r}VOtJpe7!j6>vF%Zmy3Su zw4PBwqh}eq_DrJ`;02mg25Z_33D$hikf8but$JBd&%l*%kHUzf`T#ld`~!T3(CBjB zYO(L`5uAapmyxkm51J_80U`Bp-U*D-5yKc94^f1~VTm2LuHUrWFU$@9t zm(~-g_&Xi2fyEON0UYDJ;TDAv;w2I_Mqq~_{aE@Ro$gfir-!s}%tg=i))7>O5Jb*Q za~}$-q89h3Uk9c^pPo8HO-}mNVm@Rr^cFv<;#Y(Dpi+q>UFP$5oWD&Pm45L=@=Hpy zXoBkzptM(H0izFy7FhV8o~O(FI`$NAU#z`e`k_F$ie`EwIi&tH_m|NDMo{!G0YTBA zpg{0_UTW>p8l}lUf$x|+9H4_4}2>1&jxs2U4`W4-1G2p$r(Q-gE!?KE#D1BZxS`O%K zG`O1vOCQsX#sELB8?69DGwu|K5?V;}l=r&7q`*{|EvH~<*op*FSWn^UtHneC;l9aMOEz84=FogO=D&Lx{E_lv zdeS$~-7LL)T%eWtB0a8Ki2<$?QZK7z#N9ovIJeunjk<0W5Ow<-4O{4;iUm3LAQ7TQQJ*4D6P`6iUIMaF8Xfj3q6x4wF{$L z9VMemv0nw0vjy<<47^!rG`jqfm$O1*J&s{Vi*CxEF_mv3i<$X zjk;nK@NP{i1w=Dsk(MA}uN?6_8g(1sAvu*^gK{~$P>v)UaFHgJZW6dvlcIn|sX)*{ z5UiwW5O9SEa$aJELYtNz5CwzrbRt~^0xp$Wed#tt-;d~T_$Jz50~HMp(Px{4>pW(| z>D3~{uqC`~IK5uj&eqa2Tbq}^OZc9YBPD7;JUmFh_i*5@h;tsKe>L2IcowifHP~jI zm(BKl^wE{W1L6Co)O}COC;|MbzU^NoC-q^NoWk=M)cb%Xx>o#vz!x+r3TR} zrF#q`;OA2qrJxT%RdjMi}V5+$@xUIIkpE+a~4pBMqXss!B`R3%m-dZKY|A(lp! zSUOc=$)GB+bgBe92<<^^w|>`t^eKv#d3UNi9wWRP_5Br5;U+mj`3(>Wfb!e=ZX0Zn zdi3x|Y-E8`NP-3dX)d>*#%SGa3E(s#@l_(QE7+pfwD5ZxP}zS3H$?}aw_-3lAOPGU zYdIh)_Oed&_~W35gD>0+)~!ujcW|1zQK`I0juZ-j*ab{)=~Ah%*Hi>VrgST!G(Y5W zQVUW=AMO=&T#npJ!rfbr)Txn|BhL9GXd}$Iy*LNj1as~doC7W2oLh=>pg~J&?;V^I ztpbN}LLrL)Yc#3U&)y`22Q*6w;0>Y>*$sHJCY1nwN=U9-QM$u00{%dgx>e$Stwb^4 zCS9ux5G_*_1EN`0qBw~XS|&z7qeNhu40LD;P+ zy!eJK2ek^tep}M5(fiAjbVKBrW+D8Bocede0%+++t73q7eIMUW1Rg4E{pcCzeL0E@?meilSEzFiZxrUupmex5WffyEO!{+19)2oIVg0N)blIIAKQ;HESy zou3OoSowF?{muD#((Ivw#S@5rDHy_t#&mo7ex5Y$0gETT{VieCA}Z3^@m`@EIimujljy<}iXh0-+-ZU2nF45@0mQYtJIAAhRXs5RJ}q@!MwEVRBm#br z!iZ9io^wh7@iS+xM3k;DjDYtF$z>Grfx~pIN--eJ;flpcl(rj2K$zn)qV%d^1cW&* zBTBG{RwIBg$7MtbUlAilK(BG#uhQpeRbqfJhg*ng)+pFW0m@ZQD0AZE_MA=J3b|KIY*AhBeFwjMqYQyTHrz*op#T z`Oj>?9m2-qfVXSfk0e~fr6h^crG^o3swR~HUY=4HrGoBPaPNvrA8FO14I*Qc79V|5 z;P(ybX9ABI()$9lbaTXM>a4!S*lt!F8lW@+BLS#nZb}u6e z2R)3yFMAnL=r7u_L|_=>G>yU-4Y@TPbx>de<-t(ubgG#Zc`wU8@Wb%CKt1NtAYI#$v!)|uSBpZ@3PZwP7=))AFJpbuDKkSj7R_W2AQmjd1!z<#feNd%3MGCO(##E* zKc6zS0G|<(>noJ7(?og!4wp3NGNN>WP>B)n$`nSFt~QK-`1J@^B1&b35wJ2vB1-t> z4r&_kx)es;y#j(>C{E{v;$+YZ#p%3IoD6!QIGq=YlkmcPZCo)R>}D?%CsBgwbnO8M zyIn?YG+v0M^Fl0*7h>tW5KH5QSUNAn(s&`3&I_?*&zyeVOCmPRGN7ZSd$P16bBU(LAj2NeW>HO(Z1D!l|yzyh8lBzFja5yz1NCd-j3 z0!|UqCtNWiVsSx0Edp*kX^Y^(tUwh3QE?!z5Xa=>WrS1+zKk#`jdaQ}O)f)AwZf7v z<95lpomxx@;Io=k2KXHzxxPf{Wy1*ggA_)TCg|WO1I!gt`rg457}gbwMX)~nR?vl- zr4$gd)40YjIGtVaA~Z1NdSJqgGnLb#nI8x`mjZ1=p@fJY>ta zg&VTdnCBOq&OE#h;e4HFOC}4Ps!7Fw-q0+dz0%0SzF)ze+V%OO$#kS3dO%AQsi>!)~ZlsMQq%cUsSoQ@B8*%^_`sfD44B zT1yF->z9(w+$~c5^IA*^-~&Q(tw8Bv!wC2lO^N~jHKndCS3ASx=t@Khw};Xg`E?QV zqHduC5Vf+b8+0nWfqn(o?X^!53~~-b90G0uL+HmKqE1`JsxC%83W zT+>pY0^X^OYi`%iHbD#G^NSxKgvaDa&%gu11vd8|twTnn@q1ufY>>#=qve$Ydgaku zEQ-^~E0=2e;5VOcJHh&P-9&MxKsYnaSb<}VFDi8-0-*bOT5vhwMVb@^yjYWp0cU7Z z6^u3E9xyG~Tm@ufLx!R+C@A3bv!q$5LDmBrK~;dWwUWg_*?|;uK)659wMqb|hg=%1 z2m_Wf;K2(0Zpw^e=RhN?FFg@_^wPK^mZM8Eeq9}wLZmw zo@%zg9;)51tHl5xk~Iju;1Tfao@GfaiPC=?M!*%4#N8B!5>@~t5%60nj3}KDDlr0n zUu<_JqV!Wer7i)4wJzhS?Ty1;R3z`__^T}z_k2y8S^?`(EzK8h9+6s}H80>dwZF>& z;U#|KWjhM%v?ro~Xwc#FD+*zcYDLSTC`8f?{2N3ndVz)}Af%_c&A(rC{x>;t_6DA( z+baVs7Lu|O?MW2wHhj?QJwx(a1Gl3UZgGaN;|JjRZVgO>5zOb0C8qhqhH0m2)7c}3 zu1_0Xp*Gs4#R4GIaH^sJeTWYbvF-4o03C@B5TWhxpJv@QPj_ zRRH3L-iZtF2ZjqUTT+Lc4N>~nK3bgLk5B^dxTQo6h?XhF0P#Cu#0B_~R-zmb&9V~3 zNtBL@Y9tQuzdhRipZ2~6Jg%!a`zoTu2?5lQ1cwCJ1d}?D2-%Sx1t`eaPV8VOitP|3 z4P32OD{14^?y|eGWqyiCfVw0U!53NsX%Qt*LugScq%MS_wt+e{P<@bs$p=9Vp%}>5 zit^{ADfFE)Gxy$eXLsdnd3e6>d3qjOXYbrO=bbY%XU@<4yXt*<^v;u2+N<^FhlRv7 z>QUS*Gtg?f8gec%mk~_Z7%E1?s#I&s6eIip%j}TT|_`ZJ;#h(--=;yn> z9+7r_TYfIZB>npOa0H3k)`)xUj@)eLKgv&42i|ggq3Of=U9rCvX{ev;@9#w3GO$&! z6uVJ4SQNa+A`y1z&l65z1#p*0tH&0+s!>6^TWbprHY#X0IJ-oi=ShwZtv`EOifRj9 z)u^Bq)fOCVRPcC2y|z(7d)J0G8Wpr{v;_wn6|`-%1+Q&X(6&*d z!ZXCBV8^s`rCD%u`oc*Y9GB?~>9YTG{QrOkP7@h)t-m108JSyMB)M+MrbT{8&YvMe zeUIe&z1lfBen9ec`D0T4QOQq}iOt!Pr}_28rk|FX&(+$Z^)-o(eZNd5VwJ@&_gVj^sa({8Z7$5vk{!l7CzBA2q38%bhOe&yjqi4bGu|GPI&wNPogOaEDzbEt`O8$uCPZFFo|7(P-W9&OWgX!@^pFqNbH${|7^+i1FBPktKUOSm)Gyz zo|od&@6x9E-~J?~{FUVTO;7y@qke%=KewnKR@AR3rtACLr!wWsl7C(Df0q3FlK;Ep zKapI&sAcLC2fkPGuSouN$sdsXyOKXF`A;N2Cb@oYD_wuP^_(nw@TW+wpYcl9udnFN zNq-)dd`9v#|G8WH9qB>I^=(P|o+*8&l)hpp{rWF`Gnc+^C|!U0MPSSEs~q}{r+Z$` z^63lY^gUVn!l$&H`ra#j$5mP$tyf?9r1j{FqtY*XN|(P)Y@-?%mGkZ<1W~ta{bA(536w7lrF9RPl0(YCCBOd0>RgD z>=ZdZRdT&@f0i7l%ik^ZFH8Pa$@NLDH2*y*etl%C8UIg&|Cr=@i}6Znk3NW{&vT{m zblj~A|L;gXBl)e8tNzpFm$Orv|AVrQ(f#!SvD1*`Y5sZP*W25aPj944^M6nXAC>%L zlHV!$g5*aePiMV?_aezRNS?kC=USns%j-^fR?h1~6n`qm+Md5_QvN=n{~yV9M_t#E zOG4LmVH#i8hi8dC&(VG$x!!SeNfUkFE_A(s@~3kANy)We>9;`A_zwx+4L@x;du}|{mbyIK-FE#@SIQZYg)^58SyMr z4}F)4T0@Hn?syeYW|yh?X7J1`!*h_(*S40B?h)@_rk?x3GuP9)o+rWtL*R?;^)yg= zTA=4kdn%C6S()3Ot&Z&>%1Zo?D9(2>5d}Yj=Zm>xjjaP^X_;2g=sD*}I1EZQ9=Q-fXwBVV@7E0ATUODDT_%f85Z&8Z$ zJP4k-Wq3;9SzLyP#+`*_c-}+xK#Al(Pz=&XL3zkgNVDC=Fkc$k8$1?Ki04l5bm6ih zmjX|%o~_nTbCkGL5L^&ZsMP1ER141}o*#fG(}JfPfvrxANN_5|v9-Y1?vC|O_ei#$ zl>=&1X9szSpSp)@HKjQJ=~$(QQQkcjR|F8$GmgKq=ohZ;O3XtjogG{7_f$C>XPr1n z(T4t~qo{H{89bR~c=Ya5@~X~`yPg{aI(yVwfVY|7V+1nYlY`2IMvxfvn8^epYp=f1#)MH&d7Y83V13}RDYg- zQjT6L^*q(plK~KEDo#39z7`}IEBB2}6iQ#gIG&GyXHIzn_0@hyp>|Q2B@c*``YN@XeKkI(ztmUB0_>}LCeGDY$3X%du+EN8 z$}jcREjT7MbvmDy%`fGt#{P`vgXdg1<7Z@x*%r3wz9Cno60r_d^B)G4HBS-JpQDWD zixnz0FFI^COZgk1_dpf#s7Ke3mLdw(O!Z_i<%uKPcfmt*;8vfeI*UQLO4h(asKC2mAFXDE`#_5$MC0iFe%lJQ-}T&|f~x`;My z=IZ3H_5xBi>8VlA)m|`!^G)NJ^nw|vg6!7W@nO>r?FF>zfS}+Zd;3Xy!EGQzSn%lV z*5@P7JZFn~=IJo@l+S=8^33z0RrbuU8hNMydFI6kx$K#@g4-tY%nHcMji*cCW6zwi zm4HH?c_FOBo=LkjRwVMwFXBIY=0d}I$TNdp)pK*t?1MqsGmoJF6^fHa^`}6D*fS^V zg`)47BV;Iae;2W>xURx!@;c>llv_a=SgR5?_SHMVGrbJY*T6Hh49{cWSz3nYY`E>* zGCaQtp7~{Xt_4s3GCZ#a&*CyXZv)TlGCUsvPh}aNFM(&F1J}Kbs*!6n|=F>npe%9yKo>)o5&@8m|G*0EUU! z!?U1Fdz48~>fnW=JO2oRn?Rx2Lri%)DC7|_<-MScc$7Op8S*H1fl~1(_kc2s8~0*) zz6#1p_y`mt=ya{V=d2{pF;G@`JapZD-s3q36dLDZ2`>PJs&r#Feg?sB66M*+ng>7` z$|Na6pe&r5q)dXc^xP!ncd68QNy_^`na6PB_inZhgy`r;H^DY$BH7*z*GVNiyU3(C zf*_h>KTUMl@e|16C+*$4;8Ad3$aC0dz>)TD+OH%@Iy+|Yca`Cz-d(P0@9syN--{A{ zqTYQIMm_G`dfUIxL$ixB)@bkk>x_SvkEnOkIKN!)rd1O6?k+O6Nz}XF0%5p!&*R95 z?B>0H2|wfBt?x7OtD@dLbR4~V2ukMOeH8wO&X!2py9puDyTgh6gg3qT7+LW`@hB^< ztMSv|sVI-590q09qudY5Vnor^AJ~F61E|xK1KP9@4HGp^G76>N#vR2M6EoNyzWxCC41doa9cPUQ|MkD_PXa993qg{ z%^Ziq5p_IM2UFR=eb>E z_ifN<#&PPOU$)QFOI+CJw<$!FtIr>Xejy0tp>gY3(RuozK0gGqYnNM}V!%r!^7$X! zu0H=XxY~{s2mAaVVD860UxQ>eQ8fO0%-O&OdALxrhCKHmeGTlu`(J4Mk`T|KtH zQ&__ zei72vgx@*dMIQA!_PSL@j`Lr1H*ScyhFRUGMre(>QW5(@F9V;Fr0k86_lC&B;_1XmR_b5?H4RF+5Hu85t1cN zwqL+CQpt`55G<9{pZlMq_L@ZtZ0duAtY?y^9}Lus{B#+34n+OSA1joT?z`*<4_pNG z5D$4toODJ+_g!#59gI)PFYTw)m${xTI76Q8C+dSg|G4(Sf1nw;acG(moebCGK6srk zj8sQ`@K(4w_rVuq+VCk;5B0$zP`MBGqol2h`d|;V%YASO+_oQ5AG{cIQtpG#LM3Qq zDp4Q&0P5jBXvbS(r#`rJ9DQ&R0`u6k1we!vC+&liIKzGL)suzl?wa2NaSs4&n%N}Y zYczwHse5{khwT2Y7({-lKWC)Hjry|s^Bl@7H@A5VGPD0c5vip9b1Qi0Y$HFUBIG~! zd_n!^9<&V8&{QJ-8G&a>3{RcqL-L=6z3M;bHqcNIkpIl$Osg19zHv3YkA34-RBo#x zyJs-MlJ|9XJg=cVblqw-Dq*{m4?+=%r1qNM#0Z_y%rml1U~Ca|7ifCA>f$<7L3%I`2)$ENy>Bi?*w0{tDaG zdkpR1c40D*O4^DZokzL*v3(}txp+!_ql4BIe$rLs$D_7q>*Z2@s!;dWkyWfBx$T*z z_q@FUJOgXk0_i&&X$_NwZxrfS0bMGq(Wt-2TD=E+sdcXGt7l+Xs^!1C_9O@SHCIm; z{`yJRp0fagVu7_1f64#+L~GA?-m7cR-vxudRU_u3wddEOwWq#vHa<_kXzls$7z}vt z;%ELzIij`a0(!`DYtQdNR9<^-1h?%{v@dZ_v@dZ%Lo8aK4jjk&bTC?F+-QDPZW4XT575O3gn4i=S={a@MZln7% zsRa4qSzl2SISEA1h_+?#}Z#YN<_w%UFtraYJHDPZV1kL|Pe%<^k`# z#Wu+aMz;97BWjEFu!XIQY;i60LsshSc!w*O{zH1EyBk=~8JxC&wAb_!T-IPcH)>hn zuFU=<>hIRa2$yUz*TNR6=SL$w?=2KZa@lI)Zo|i;=l)2~08SIgOvAabK}|SM0P56Rafu# z5RuqdGw=-yW%W$)$!F9UHSoCf+`twRqgJCH9xEI0$ny?#k29TZv`^c;amTJzgIhPQ z#(C-u=~)3tE>YjP^8vN#w{YagUScAfo(7-izVrKBF!h&gT8V6mLBY)!d?xBUABt@H zbSTi*A#syUyKqg4Jge0{?EofJP4{VKR!Ol%u8|ds^ng{u?qMyD$7RO$bh#MScxI(` zXC9J=r1F#6eF&$}eDL_^=}7z60)98^UwVD#0@Smd-6{4$O~A6(i3pEu`mS%QP3fhj z#O)`t=|>`)UhJQgBeLo2aoF@T&(wZ8g_2eQWYhlRu<7)1*mMy3VVjQC!rEk|Qm%UQ z<)5K1XIj{ln)Va~`1#0Q{#Zdaq;wv57M9`JN(03fYBBuBmAW33Mf`GBc9aRif zpTkmq??ibdaUEZMBiPC{iOY!-lsqw+GxGQbBS%65bB!FC4^^Ve=8n&u4GB0U+PJA z6b-nZP1g;1_0X9(3D1T|^Nn_3;0jbCga0Ste`m*P{G}GgNo2lm03>I@M)kOP)V2+M zt$2X7>bmQk%#1~~`KglngO5ag@SPprNjadH zxe@pO@czcNu&!mJn3=&DI4JZ3S8ou*sh@r>>ZeaYCAJ=lne-km^1#lHi$nrHqrSY* zqAwFSU4I`(B|NX21%;wjoV35+1({_&Unmu@wbdYI&bb~(^2Fu!*W>A5(^3D@(s9oI zv++7=cWeLIxPeNw=Gl53SzsBS4b+31@el_2&)WY`|M@gp@9U6w$bW8zO*w{NOC*!X zHz;nfZ)9-ZDw2HT9-LZkjTT^fiK<`=J6@X)DzwZH^7!?Dv>8V6nVn#hI*w)a@!j; zlF)k-{n3i5ByXue81@$OV;)13aO5rB=cu=w2rLUnk>uJal3=OWAW{L>Z+65ju+iJ~t3xcIvQFi=2IBi|zEmy*V%gy~}fwi0`tUFgd zVIQ!pYRSq&$6@6Ik(I62sg+MhU2J7~$-v%_o^a1s2|F=}vz7l6N477MmG?zf{*d1& zIdZG5CL8E)b zf{kVc)U(fYyY|5V!v{8waF-vV?Wn7sN!R*0{?IJh zPa1!wBF|g}27g4O66BdDpQN7o{w{u#mR}cn=Ck2Z9DjbMYV(+AwEEH;b+qcYT?O3a zz2rnsLe^~FOZOyaz`*w;(^UbRXhfTSj>a*1YACj;a?^-58I5SeO7?P!b#(tc`-X2% zWuy_U3&QY-b_`^=S0ZUIp!XzmFPN%N)tl@m46vk)dcouIpE>pL7W)ZzoT)ZF1Zk;- zej=Nm@m#fO(~ z{T}sqr^DuR(M~w&>{TQw%{(cc3CdyBn4{2rD~p)8ktJC(Yl-6V&>dAXJG35+0E~`O z9UCC4zpM6mEI6-N9ka&6wRbN-H16FQCw20V_U_xj13@6qD*W|(w?>kI7pUg#T$Spi z2#|Y*dP~RYZfliJBocW`f8;IwMrLBA2=J7*Y6Ljn7e?wLj~c-LRuO7eOJPh?9Eedr=pACbkpmlolCKfL&VsUOme!6x#;)Qob+S6LSLS@RSMyP34t&dvGQ+5c^*oY9n!j+`e;Kv>m3x44jYC{=kxbPIy?oMhH$AwI=uWibhrS%<#hP@NQb2q z3LlaV>DfTCWUF1HpMsBdSiw>~mvlo{(TOk=>oC($Kg4tncovPX#7=Dj8v**1bQ z;8Ey4tR;^!3Chf1veer^S@0;cpbTNdEuIz3fimk+z6eVHb;@Hs;c~PY=1e5*O~>O2 z3y~)zDv+NVMb8ETkN8^*lSWaBv|xi)r|{RmUP*3kqr`g z?_vw@r6O*`#~g>}^K_S?zk{H5@A@s40`J%~NWV0@>%HF*mVt`y9RBb67}ZSr>AD2^ z!|ztT`+0Ce?%jCz5nc?K7-XD){{}-1IGHo3$C120d$ZLNd1u%4+?xn52p&VJt~H8I z<6B%*U2rALG82`m6tlTJ_@+?-adZaRiQ&Q+el6*oHYk;GHwh^75d{aq^HI;VN9hA4 zgNcW0JFx_tLFpe#N_aIWk)9pTZcyqGI+6B(LThT4hbT9JGUV0#d!Wp|K(SbdSV=+5 zIR3nwN_mtIf-)UZ)DKzDsHX|cz2bD|dhNipin&)1m)-C1iB#i;e~ z*BJFL6h2I%7?nYzmWxq~&_2)fDy9x1&`fU^Cbt};J_rx+^-Mezqh_NR^-?04M18Qo zMIWRB6r+xup)rb{%l4b5GnqRvx8;7y`>S%9#dTNppIPToq-P^a6kBH1pBwBa9FPA{ z&1BR2@NosU>3yJ}(o`aweyCe*+I%)hZ<=L$Wl)0^oNVz3e2i_eJB7lBq~}TtJsbT* z+L%*q*uJAr5MR6i=o0~i`-tS3V%n4OD7_RVJj(hrFb)buBLBfLZXfEA`$>)m{a%Ak zs~iujm*SX5S$~Q_pKA-9?o#$@UN>vd=~|n|v;G8weyA<KZa54VMWmqFie&<70qg9d$}E%ZYMecGUJG3ZAO`jNKKKVi_P z40^vo|B^vpYzv)M3nzO0y<*V&4Eo&${b*b0A2sOX2EE6if6AaQwS|7rpbr^zx@+3g z&-yuoeylC@+YS1lLC+ZU4;gfNDItv{k1x{B8uS5!zS5xIX3$r(g?^hs-(t|a4En7G zy{j$s0|vd{psz6KZ#C#E+d{w9p!XSc7&GN{(*`}$7W#}q?=k4~#U$V7_ZalmZK2;{ z&{rGuC4*ix=sj(r)BVC;yVhk4I^7BH@vNt7u|km%wy!PpHyQMm27S?>UuV$!+d`i< z=v@Z=h(X_B(6_XO{yKxc!l2W=*1qQHTj;*#2iiiPGU$OpKWxxnX3z)QLa!V2V^{@v zE$y8*=zRu#s4eu0L0>ZH^kkwZ&wBbWy|4N4w$O_P{is2oGwA0T^h#Uk;|6`vpdU2o z&oby!ZK01C^dkm+)}Wte(5Kr%A2R3*2K|6RKiQz~Zwvi;gMQec&lq%CV*6e<(-u1I zq&<6}UeYwWdM(>nCf6$;GYzuvx zL8s@Kee{Y!zu%zGwS~ULpwAlgaf7~K&=0kRzR92;Fz7=D{qqKWzAf~AgFa)>2MzjP z8}!3%p}*Lm?>FcJ2L0m(eW5M%K7&4O(6<=$gTEy7UV}bm(EAPg9~tx`ZMD6}pjQlf zpFzLXpf9$Cet|(BH|RYE{jCQ5Xj|y34f>ElUv1E*4f;}B=&KC+ph3?V^r}HW))sok zpbr@Il?HwMmxO+{LEmD~yA1j+gB}#x*}GV2(EAPg3WNSKgTA6I^wSJ_pFs}{`dWkD z)fRe}LGLl>$FLpbjk)Vr8T6HHp`T*VR~vM?s^g=t{3W5UFz6YBe$=3^FzA`K+WrKC zzS5vC8uUkTFP~^bb`Ms!g&r96E`xr=pfCNB&>xGhamZDn6$YK|IPmR$Bu1C_Cwvv_ z?)VO+7t<{dUb++4DtnxMG7Ycm$(^%7bj{b5zCTe49S`XdQ2MnVM|mc&lyX9JM;T*b z@3iAAaB*43jz8wQmAj`s#Upn^Me;Oy-cz2bIgIOeP#UmSC`6R&HR!v*gMZ*ziN8=* zD$%vbgRjzSk*@*+oI921TI52vUWu%Js!ZP1HIDxAJ0C z?>sE$QPv-hqn3EfpnA*WLVw7hFB$Yh2K`QhKGYWaqCr1u(B};Ldkp$`Tj<{~=!*vZ zph3UIpjX;LKVs0281z|#K4s9S+Csn2pf4Eo0|vcf(5Kr%Uohx2?sy*FJ7dsy81(&Z zq2FuJ=M6f2fy9$%{Ywn`Ok3!O4f-L2K5fuf8T12fq2F!L=M4IkLGLo?vu&Zz8}x$) zy<*TGJt?w<#JYoRq2FcDXAL?%L*Uz;BDPQjeXcF^Lk9hTK_4>chYk9nw$MLe&}R(# zph5qrL7#66o$f&Pw7PD;K_4*aw;A-qZK2aMJU;rgLEmD~Z#3u&ZJ{4D=u-y0-=J3v z`jNKKZ#U=_gWhM*UuDo2+d`i;=;H>x$Dm(s(2ur-ew#rbGU%%f`U?&EQd{T;4Emr! z&lvPo2K`uD=(ig50fWBMpg+Z+2REemzM>UJi#hF#LEmD~yA1lHn11__c12t0w;1$( zgTBI`KWNaq+CtxN(EAK}V9>u1qsvO_V^Br2m6X00J+4PrkqImrtuopQV5XDq9z-^6 z#Pc{-k@PHwvtWx=WGu6;A`>!8+dtEy?Yi3f6}GGQu-dD|Dw4KMxb4kXkq@hHbl^uS z>F&WlMQzXR8>1V`FT`_(`BL=$+d=FRE$XV@)iDA}@OtW}na2A7ze-QIAy*}#A_*I4 zjL!cj`UJ~Ndlx6;z`EX(pwR{JHQSG(dY*xk_koA1Yxa(pDd=aV(+}~Gbu1Q*iVH3F zf4Zx+YK{PrNZL+%>s>CyTklBuR44Dby_u}DiEY7@KO%6QUqn% zt9c(NGZCdyEtKk`Xz6&eU2g_YKWdF7d=Du4^?9!OV?^;<`gu@v&B#0tg2Las$w0zd zy^1$gm8*P*Hc=@30z5|}c|yG3WH+dM4O)3lp~pv%Foa2|vp|_%L$*@N3ms3=7WCa$ z{el2vT~CzF+EQ4#NN+nNTf|nbgNNP}N+r0|jiBf(g(+_bMdzzb`4dp+zU5eBe+|k3 z&tBgEg}=v1P^`bHP%KS zD3oH)93TojFQybgnO&PK^#-DNGQR_qE;mb2d2Rz`AhH)>d<2vL@hPtPZcxCIpe%yo z>-pb_;`z^0FvLtp@;K{^@Ea3i>#PRPAxOy93GvE+5b<*eSg~(x2hV&@vRyeEykMHR zSC&B;aP8u{@O~RmR)Q_Y`aMwkJsR?fwZ+{C3?9N|)EJ2SA||qyGmew6h&k zR^V~3jE9wx2f(;p_%d~_vJVnQcHfh)4wq|r_pVO%I=t9x558|2@ZI2Qujiv4y~mYh z?gNFs9UObh4p4OWl6i`tWFnr*WW7c$SP`Mq(d(&{r{@oVGVk?*yFeNAwDC`%^k0-j z|1l^75oIDr zmZ#M%;F$*{_SM~>%z8Dy0hB{t&9{Lv=*fHsC^Jw_te;O24;m8pxO+i4;MMb8P*z7g z#acd3qXXX`r8@ixcvg6&PD4jt?V+C!N>}7#s3O=13VoG0mS-0z`@MR`KpBc!njOZA zxlyv>dFFob=v%PZf*%Kkzq6(i-V4egN^(oXaHLoaLlPnpA-@5hnBu&p2p=2M(TdLf z5IobKgik#awcbEHfs2VjunLq}&w}*5j(N{luK-1#cVL;X1qEF>p^Y0rS%}(B==(rH z-%ZH8ACy@y0vrJ4h=+AMCmnK&IRfwBTQ{pXs00SbR3H6xTRT&$)!EuCkcXM(aA z)lG5P%@E(s4Tb&l!G261ZB{pOn}nm&2nE$^>|u+J18{l zvUL#I3Z;=CptnlKGJhC6y7$Gc_!KDojY4hd*Fd>GiV~QU6lh&QJtfx9x51O~VoN7p z^I3_sLG8+bGVf{rLQqym5)#j5Q0Q5+Si)C=LSZ4sngC_itLKfNEO}V(0j1*k>LF12 zJ>U2WC@s`)H52=wt}MEV{|t&H?T=k?WHvCOAF z6D{y~GN9<5l^YpLxrs`^PpzuvUkIK)Pr~h>9PwH)0t&6};<0HTC^UY>lv_aYz2&`B z%JZm$pgat<$D02XC`(>syC0N($P-7}lkkd=A+Me@KsoBwb3XAzz5yNbp^e5JK##Ol<-RMjC*abfkG*shrb1sS&!#-P!4}8)qvB-!o_?;R zdQeH+u3=DSqIO}d9GOIDoAFBB2%Z&QPkB2iD;@RV%4)CX>p_|E`f?SNg-Bxo(#@dw zI|J_~9#5XTKpFCCz6X?}QA^!w3z2OgQ0s)Wu##B{I7(%SY*!Lu0oJk@hOC`UZa?*_%+-`EEVe?465c@HT2qf#zn zXVX#i4)FANTKyYP0#{1wSpcOgl9}ZBCMXMD+rJ0OToNls`w5g*;6MA=&%v`Ls;4HS zIX|teSf`&03B8&x00sC7pWh71pjY!Xpuot&6OK}hU>}2<33?tpOJ2XIfI_};Ld5en zP!>J(_kp5U2Z%2S{v4EJUOj(Hl&D?AvjB>I9g<7^8z@U&%};nv5b(EXwe9DELMwWX zB%@er=1|u_gylRFq<&Cit-b`Mz#=m}jPLlzy?~Gz{pH}HtJ|?Qt^ws>WG^rVWl)ZJ z65a^Pey?5c1f`Bj;(9&|N`Gfkho1zc$1C-DQ1q)1EYAa=1fJLZ1Qh-@E@?x*mO^7n zjMcFU9v*39R3@4|5hbh_Ci3fhgZ+-8ZGRF<9Y7^6EJiGmczsD4Aa3Y00Y zo>zf#*lTGKlyQ$T1&Y4qiQE2WP%@q^-V4gnlaej{Bq$4>bv_5mj3@IEP!>Cr?fNMw zOHrwiKQ|i8dD=MXxoGAKb<1_{?%C@Rs^`~|@|<`ccZJ1ECCB`I^DtcZAM1R1YFW8R$PFnIL39!vND zD07i5D7Mr9wZ)U?r{Ed#eC)K}08`{G_#Lb#ic4ray~Z`@kmESJ96UXdghU?#CF4Ak zG!{;l+}`%Ihh7BFu}EW7>bF7J63I-I-v?#M)5afzGVf{r&q0Ythg^|%24Ni!>u+jJjeFs`Qcg-Mj7!r9IhVVPpVs6W9)~ZsE5X z2l%!@m<#FiDFMGOYgKnOKU%3*yR}@QUaZ$fs^xk(TCV1R>b~C7gl%8xIJjz)<>k1f z=cd8JurQGw%ZJ0+S{~D^hN5IEm9W0Ak`E@bCGd{mIL#PJ#KUB**{R|DSfON2@^m2u zOF~sbnM$P3ZQpvuW!HpTuh_Y3!?tbVrp+(A`m%8QhFx1W@7Te*hqR5fuj3lFK(kdW z#K|js#fKwh{S+v!z18UxyV&8~N$i-|r{I^e934zCNN`zW;|O9bGdpM zUY3#|9D%**asss=r0u2QEUrWuHg=_QaU?&Lt3+?owtP;H+1$iP(W;)6?2zbUj=^vj z9~)7#4R~oo!txd{5xu5R+Md#6k(IU=4%Je{W2MOu4a{TTq+HV1g&P=oDVluXYU73t z@@p&o;*iiH2E_e46*v4Sl8hBDJh0(j^BOdpF*t&R;pH25gxj|6+=bp0hWJc$ScT)) z5FkS3AmT_qMXqG4=z*oliQ#-T-~%))Hy$F&Oy;{msdx9J+m7ibU0rZDEOd(_$}5}W zL-%&(=nw;Tv78-&uZNQr`jxIzujnKgM=)l9aTL2(5WJSF7BJJrd)v#UTD?*&SGw1r z=aq*M_sXTw!q{XLJ)>+Kj+?_Q@H)6|8k#u@qj)Lg@(kHxy%p0QgragaL@OGjK;V(d zT)jC%Enh8Q?{TzN0o$y(Vz&&a9rd13(Lcr8+j6`D5jowfCh!d?7s43Jt$_;Y6m?M zRxqGxovubqaVJZ=l@xUn7K=MVm@noh@{vx^lZFeWP&$b)mPxJ9qoK0c&>8mA##}9~ zTSW($>*$$~%%ia&KT)pk(-xp^7_^?vIepQ%#nlpBR7XE?nVuqTebN~x%)uVjBtg$R z4TOAQiORWADy*0B1H1lXqzoz6m`Fa$5UvhlD&Wfwt{h)T)%ZmYvMrR- zy{>otS|-tQk`6CQRN{Wp{ac}1eug>RFN6OVtqtqhVS#h8&E4b0LYFZcbBDF@@?Lz_ zc678b6~Z4NMIJvTbYfCm*qtx#)7TjwbMTCgNn@{`EL3;b0vUo!ZXK8Ef--@TRUodk zmBX=Oc^K|Eg1}kBzz|bt9$@-#7;fBkWi*b^WB|TgcugLD3@1RJ-s8q?RD_pvPvWZ2 zK6eanFYhkUJT_a;u1cJ2O{Y#$5uXk*UeTw2!?D_Ewosg`=7Y<2h8xQW5L5LX`CPd= zLWIpaEH@wxlo2rS87OL|OlPRsiNl8TGr5|MnO6~Gqm*DRSF;6*N&JyHOyI6YEZmNx z%~h(Ed9Xc=4u_AByD!lN=pQ-kM1>U=Ccr+Tf2{4qve(JRK7}xWex~k+t+^x}j>B-r)mQA=x_xsvuyga(o30FZ zY~FU|MxG*UzG9P|bhj!%a|&+m&dpnB#f~9P9|qMkZt9pA^W`BNqzm#B=z#7` zr1Xm)$qXCMv!p(J41?Mn?#}OH?^Wd_&gW`@p5~wxhT-1zy(}tKK=DpFv(E)bn1@9!f-W<5rAVYzOptkSin&$Kx}Anx+yj} zl$+0UKlNwqAur%u`0if6Zrw%eFr6BntPN9S$kTG#>5(Q?~y#SR86#=|h~l`*U9LNb1< zk}w8V%f+ycm0@iZ5^-}ed7*_w0P}6b#1caih6J+ZJ}mksc44U4P(u^)^h+F`A~d#u z;$0h7Vly128zaFum6{ueq_v_4m=AqiXC{p{pQ2qQ$Lh9qvpHxPQM7=VOeU{kx)GK~ zNsYPPZW@gp3ECk_no}F^HNee?Kq(K0qmw1-Lr$Br4Uw*yJ_TAutan3O_67`SwaMX{ zQ(lO*XpNTs&IRd{VYpRR&C0cILSL)rHzJM}V0{hczL3cUrO47cAZT%a7RE*S(vZ0A zRg?MZKC};0QOH(^WQ!|sE$2-xRl`JW47(cG9*oN&mbx}3x}^I;s(5;U5gbc)>a8{H zvTMQ~cLP^e)r-jhw(nEO=+n3(2)jFRj}U(JBi{9CU{1Hj)WHoMleTHXVrApR$TqiS zDlQOB$YRjeQI2D^*|lQDpv%Z0xNDp)z;C6Ui3YwK_ZmHoF$Dt;^*O0vpjyUCwwA2H z1s`wkVOOz+5||ZCQVbx?Bfi$l#b6i4R>a79UaE=D()D6yb$1AaAs$?bY##Me+VmD% zhZ{q;4jnDz;_eaqWjS7b2B0j`I+`fxI-oGl9B%6_@ku})`z>lT>NZfnO3zYIHM%pdb;F%p=acH;B)bZ^-8{3?(h;xS zfn}Fn-pC0Z%Xp?6DX~U0EP4*KnMH!{n<*d9Ak2*@EZ-bQ237xC>Ru z$%Tsxu?i6IIQn3!9bZ6@_D8EZ5|b|%!#y@;D|IX>WjP6)8ZWOxOxwpwv>oE&plq#U z6my{my{(4*M3#!LpNaO8PE2DyR)Fg0sM_7H6f~VtSQp^N^44J#eHb?6`7~w=8+OS( zDSSe9%J_h94Q^%pP^S&FKgWfj7py3>ukUhu8GHuj;N@wg^iqDWyTO8GujDG+6GR;} zthwE2)a+((>_A%DYn}+qQ`SUxl56{s0Pc2iIg(rZ8;y(D>xRBDP|$Kh1}sRGo_$i3 z-i`@VG0)e_HYDeDHr8;6O|?QUzuC)Z$)PMY3-x+252ulI6SX}wev>bY6mVjFi?7nR-RYq=yuTjr6BE?Q2ysOe_0Dq56gQ3nl-@fw(T#sBzg-t13W+4qRYvT636(m%K@)C0(O}%vn+#O9{%qTc z3o+5wS9{*>O=@B-4R!IO(NIc42@g3U_Nw%HGtg-Eq|;3vIB*oS z4rQrTu(JVm8g%Cgf2)H+J6{>JD-xJG-YIA@2Iz_t22D&hr7;`{B4BnMghqEef8=et z2q|)#oGn%N(f$c7?3nY`&vCzv2) z)4dlyXLaT*E_al9k|yWn5=|*Wq`G%&hh?piS^e9k7)Wnnme$d5h3yYMlDnJv0Nuge z*5P zKjwmKrcU=xyXnTOZ@S`o@1!ekxZ%c#_sYrMo1!;(r{3TVoHx#U{f$>mKBc_8-@q*D z#-Ph})tv{qR!w;RLf30$u8;b^3Nj=@^32$dQ;?-eyUwAmsh>kW#v{O$zSqs9w~7hSIJX*iEDQ`*R3V4Rzbei z?Rs9G^Z$Cej>uM(e^qqj-BjYLE_%-0PFz;vst`th&%aY5lV?WwHggPZ780fHw4?an zL|5a)Q?9xqas@93d-yXk3v)i#qJKWu#P(Be(tz#L_%My{H*p=m7o6{uX&O$ok+!-9 z0QX8yxLV&SGd0|6ihVHP0N^(41MbS{)A{1^-OL~Fz8Tdl^i9_I6we<4?qJ|I?*rdd z4X0$%4xG^E>WsCMNc^4-}IX% z0itz)?;?u>dcslfO_Q&?5kRdI2v~HcYA?9qr=G!k{?&@yL=gmE4@L61Du$n0S1(|$ zZMDF7`F|S!f7BBnaHrQPxZBR*G7)4xt``XM!as%Yj6v$fA(wM`1h|P@@7o95pfeR* zb675YT&{DueA5%oH~iEyYZcr$kyj&dRa}QlV+#LNy@NG<6aCOW4Y=W4FWCoN{b{P; zv{SjX({}~^ugVI@xD$NcUi|+L|7#o=XU4X87rW?q&O@f#Wm+Akwal4v2Df(Qmn*rn zylYw|JbWb&R!PLDYd4c9rORc;mU}N<)+U`+-x^1|{7wD~nl8Ff&{nss30bc-ST9F! zwLSM4C9alsW8Tp~#~in5A9)k_>N1w+R=&KbaM&jw{Ere>y3b+<^qIF!t81%iJbk*^ z(jMJn+QY_D!0r?4Dly`pQRU*J`QzLT(K!mLFTMOH6a1I?CoG$Cig9$D&(yWctv*LT zoNU^q$BA}P_x4U{-?Xy2jA@_zyT4QEA;!_o0&mu@Fyeh6XCFlTvu->wq z)9x+ReJL+8t9W(u=cbi%HjV^OGD!U{uB8LzTGyVWZ$ju@z4qp!akNiMCgsV~gYfU_ zl^U3TMllXmEi5nLk`&Ilob}X{`g~6&qh;jC;|Dwf{8~~tU;YdiXCd#CeS{&YSNW>i zo7Wz%X%9LFsFpRR^``Y!*m~JIIC=&AEEh$Joa6ldbedy1b$s9Hc!s-OertKlyAe<9 zyI#?Oe6Ze;5AXRElzITbx$NJW4Eoe7SocZ5+LY`~Lo!NvmFg^;?~DO$Vnil~06EY2 zopZb@6?rB1)@cE4OFIaoN5#H#N1x6UvU_(XlYX>F|M(hqE<8n1u|&8dR9%=WZnWGC z0r}ErYif0yjwyclBY0CsYFMR1g2n&>8kBf)`WxF~qIHk1aEt0Esn6w#^rMAl>UZ#X ze%J~O9Bf@M@C?%m53F|HKN&f6{n(A3@!ppAHt!YuPX)fov_38FPx34#!;B5v+DLOE zwPvFH*-PE7OyxaKl_)ho)l5|Woj2H$Oy%9#mwf?irvUnxC_hBlfbp1+nspLz3D5mB zEd9Rdo33wu{$CTO#QM}&wycbt8nTD?KdZ4Ma+aAey}`Qn^g%iMU|OAKtiwBa?8lKK z{jqj;u)Z^z4#k#MhwI;pz7&crs|eM99sOlp`=yspScZMew!e0XIQp>FP#sS2-)iV` z)}Vqksupg|FUVihuQ+D^w8FGrP5Q?xEl8Z}b>>_xCSpv5nHW)P+GDFsYusQnF}6Y| z;$Gf$iSf1kUCtjAtY`Ofsb!|u6)6)A3RR{(f)Z_AO4OVEx*v)@E5`v?yeU^T=c@TYJ=J#%6nI`=pBG zh%zZ<-R4VOGL^N+L8fk*=yG99Y#@;IE(Qi<}^&hZ8<*b4S=(7TsL;u3%^v4Bh!Q zU-&tm_c2&4_rKyky{3Rq^pW0C1&@{e%swAl{A}8OZ}Btm)y2=Y|0L1vW}5D5Ql2|6 z4J7f-RfXD*%2QZ^ zYzikl1F0ZvT{Y0FY?~;X@m(f^fAP=VogpGK?)p892u)h9zbE?llAxnzY1mHqU`5F4 zS`qMUaycu9iEo_Q-=FATI(Mg(oZY`o%w?cvle{x0tu|vzOU${u*IpP_Ino&z_)J7$PC$c!*C~_#;Svpox2*ZpJ-we}=xlN$#svYd0zi>$c%0x;H{w(e~XXs{Eo@UuPPxPO zG2tOsV5;9Rt@Sru4^PikP4b*Nk&t}l5=7;4?iEhjBZ1mxCJuVJk$2(5HD%5iv^eV) zCJ}>#E#5sl5fd>=4Af5NJMKqYxBnAM+lv?C1thf9y<`gZY_-!`1pb-^{|xZnfN$*v zj=vRy@1;t7_A|=f6r2~fY2NYTk!DsJi>5dEn)j5=sP)CSM+W#>r`HguX8j}W`xDGW z2&ewU?NY6)Tj~5A)~46Z7xxRm)f!-c0Eiwq_wl(67G%=myvZp?Xy|q?{t)&D<9TQR~0kqF}rPg}OOf(UGyy2Ld%cq)lw98oZ)^k_|{QEX% z;&!gY;-$v3<4fhmhcyHPQh%+EOU@P6-Z4(`e%yo{YwKx2+pmSVx2Md{$45o=ZNQKt z)p0%R+xo4p?*QZ3#!~C8x&O>CcG>Rh<&GXIwO`S#_ALLWbZp))_HnP+Qn&HcJLwIk zt!Vm!j2Zgy+skq^JxX}3X?m$gf6M7xt#~Qx)yQGa$_be75fbSnre&<@WlkBnm6q)) zAX5!D7LB0Gmp`K`IgCoOol0y0AFEVVbxt^p#2KhQ_}> zR&n^(G7f0jt~wn)e$b;CVTQ6Y*v@ch|55Nv7wi)XWGNPpfuv0!Uv^*+cK-d zlQsogK2iG6`h-+qAHPH@3MIk=-C^rrPPwKeWHEZ*#)pQMPevz8H*x2hU0;_e^k37y zY)^%-u@`L21y!TC4_Qa-F=I(G6Va|v{qE>G(>}Ywin{9FHCr-~!*lTq!=n$dRm~s>KNPR?4&%R4F z@Bz1%{@6^m3s7n*e~R@(>=%O!9c||Z3$NOt{xJKg6~U+6PG3^D1pJJAqx)NE;PSyL z){6@>MYKE5Q=Q;vBXT|rcPWfwW ztbO75Hu`3!WsMPklqQD~=hiy64-!R20LzT{VLbC~M1hz(fuHdNE2hQXJtn z=PT~b#F&%n)->SOtm)q5h-%>=gC@B+2M9*`_(ioX?N)N;g`q@bpp0jnsT2$`6lY}3 z*hB_6NwI<*l5tA?LW<~Sz@s5BQi$;n)y6;@YhqDOt zvQAL*V5GK3zuzG$waw`#{SuL$M%(22`!jGVUEhaaAew|$cO7@iU+1hx zY|HqZ)>-S3{Ubr^WiuIEpm=e=)CnV7@8Z$48y+$3LrFYF&VNyO6;4cEm_9_0Z}i6_ z>gYpd0#O^bJ{B4-ARCC!IC4t;thVSoQv&tZFNul+TOc3T(^dI+v=r9v{cY(_c5ngB z8lR6&a^whDdOZ=xNBAfIMFkC$+)8eoD%O>;!Jl!?@b&}ZXdKEL#8J5b>U^=+_9$=I zo>1zqsP$Dq! z8gceku+8xU5F%|ek)dW6MuSX6(oEdc75!04Ml3mgjU>H*jj_HqV@_G9etl%NgzZCa zYmEML`-s71M*KGr5Kc_@VbvPLC_w5$k-?ZY2C3*f)`?roFN5ng&_dHTZrkNHn+JCK z2&swk<_5)t#e^=Vb-U>6Weg@Hnk3#Dfm)<)Kr7>PShaz`@QcDv}mnGgNEZG*$6M z4ChBxAvQIz=SdChM^)$wM^(wy`7Z_P`QqzqgL6{|R-Nf7RI{#6G- zu>269{jonQmb)Wfd3AxV8~L00ZsY&Sgw%UOv~;#m3nS6Bp+tP(R_;Uf@qt}jqf6zD z*b8|h>5u3_X~RKiaQaVE=KJmY2CA}ajF#iYE+_8GmcLJxH(DyPZ#9nl6b_?h7b@yc zY83#f;!7h+n%cq#c>B$0#oGx4Q%ZxS&aGc(GKjD=G6aAzOdO(tLj^zwj2}5~0+2d} z`U>{4XM-iyyhayw7vsK9ihf4jJ>$n*JT#GlPDs_cfItV!YFcmQbpJw1o3`h?zwyEL zO%&fph$bm1^4?wFMEdjM21uDGaUzKB*A)B&L|GIof*F@%2%1C?hqf|FdQzqZxYi1P zxO%y`{B2?(WF%C*q*>iPhH&b`YG@t+aw$NQ7zy zb^iDjhCjF^M^oN@Qs^9AXeouLCa2Jpc5c*#Ql}_mC)Ly3kzUGts>L;rGD=*gZB{rw zz}1){<)(n{pN06BQW;%pFs0z9^_GyAV`(o6!_wUgp+e>MY~M9dD*>ljln*G*Pt}6* z1$LM&^&-~(~4OD^1&$;2{8&$*N!#H(DMeg1gD#p95Z|9RmuX}WjM$2IQszx7F= zWlCA3QanV}xI&n((tFT#mC&_I1l%|cf3_^TF3@*MS$b6)+LuYcmFH(q`i|7}dG`$5p3^AqrHwoQ#?ov1#-nxI{c${w-dKc^DL0tBwcpy= zU~SU8SKUT5q=*1ou5?BvDAQl$;{AQ-$HGxsKfD2J1!VmU*AG3UQgU5&d^ciFhM19> zm`Ae2oZy#;klrGrxE}Hsx#r#?|13F${*$x6(z!P=fd&N*25K*ky!Cl8N2(#B&S+Lr*p<)oBm;`w_~wR|&y6^f z&aNe1427C_al%q4JH9Bx&oO9@93Vz*2p_Ooy^NMC0A||l3NSHd{+#k;g(owMf+md9 zoVXLy6;4dbISp}(KJlEpPmlm@`e5;%2ho16)m(UYTcdbVu~%kddWG}rbS6``MuLmK zkC8!+#DkA#?{+%B<&HrKiNx}?UrOtyV|S+$p)q}B$?Fk5t|tF|&bS7e?fLboLcP(_ zA{E$`Q~pgU@~i3+tB?j+wz`lfQW)>8QZJeF^3((6+zuLa*YgAgZC`~5Za?}>W|a(@ zqSM73UQEa)Pb7>I<(GlQ8ATz* zm6Ib%<$da2?69)8w#Ry0)m)4AD+OKN0jI(DB4a^4zGdI~|j&FtY7<=uMO#Dh(=y zBsJ>G4Uhbn6CN*{j{t&tHJY4)QAEp|bX|{NcCvMu z){*B^BIdbT$~hl6619Spw7*Od$oQ>C{t7g8=P0uo%Avt_5MTx+%y%V&-^j(e4@}Tn z4q90OV+4-eyal$*5>^d4@&oRTxJ2;4q~ya|`9QcO_rl-3l;ID2`5!66&s6C_2R;V8 zWdDq~s8cv`Eo1meUV3pwxPE$7>GPo6Zs{nXk;Mbz;n5=WJ7J#*ew0i7}1N$#MhmuLqK4)L{T#(mz3Gw}@A4&lhR< z@3`rKo_}&Xdl-a$;8TSCi!PE=iV;$6qWpP4oX0}0ePC-A##6Xm7k;9saBnG`^h~0# z{7c=L*AIvj);RHzl&z=P)AL+H!;cd3i#k+DvTQR~Mf`bxsyov6_ov-TmoKViOgfk$ zWw`z;L7@9n1=v$JLJE0?t-_@*S>%_xUGy#=KgoP-tYcDa=TzgaMx`&F8nl>+yjC@l zhY3G}_R73XvoviV&*${`KBC9-=pN5wdpwWp@jSlA^W{CBC-!)r+T;299?vs-Jb&Bc z`PClJkM?-Jt;cgu`cLff{plXhuN6NFzv1D3q48L&`Fr($Z-{}a%7z>9+u^sLDK3_e zTobJOoV4kb`J)po%upO@D-O5N`C!U2c z7F|?IR+zMuxBi_uA4tx2DxdtZZLpU5V;{R4+^bkJ z5HOytm=eTC#o9|k{AaS)okbZrky2MhPMFii^~$K!1lUqo)DG)debd^Q$%01TuIWUA z;O9eWwvK?^xEt8gpw+lL{h0XYuZKL|t?Bt7Xp{=8{2d>c1^d1uw4`o? zId#nYcgyF^-O>rY`IMfOkfF)qYI$e9#po|!B^L1D%sCoH>g>A_U(gpnl_@jk%_#$p z*@A$rpjh>E(+J?KjUj8R^ACw17L9ZdEiqbb1sG)RtX3u|jXURo0s_AX)PHH*eI*Yv z1Hg-krT*sKUgNGqc;z=1y{1zK9UqlCCkq931M@ZQ122P=|6NlD4$COvN)Y~$+Xd4oT;$8F4e2;h+Q9+? z)%f{+r0qzZ?4M}d-Mq_f+_{$WiN=h&@8ljkJ(SkseNJFJmNoK{9&s-DNLt=h;jdX2 za0Q`$^;tXbnDqn=7OcppZXdv=O zdrFO#D=EZ7@1ZEpJ=_QCyNsVN&@V@p4nr~Nfazk9hqmO%r44vvuZJ{qtgU1u!n4Ak#5ex3mwQ63XW4A1zR zyWBVbG`6`E6}Wk-zvj)5`(?lTH7Py&5@`PrE1Z*U%6W#21+r!4e#YMr>O8-eW?p6< zNgF8j*0MeBLnW#*CoDP7gQfFme;Ba7sQI8}dvvhygEfHBE2)vr_c5~YH_vjzp!IS~ zWhFy`j?uD`Cy^ZMfl}9sZ=SSAQo+w3u4E9hMphZ|!&PIuvU6(>@kwF#TQ_@IW%wIo z(FU{QpE3dKwCG}{wUm-{yN^VXlYy!(;b$!Eu50f|Bjfef#;?sM{mp2I5x*3T&`kXn z{)MgR*03FI3s{p0E+J0%ytWX3Bq|>z9EEcTUJ}!{!2lXlH`HUa9Ig3Z8>ru9{Jexw zVe_ssVrAHRHi9U+YX9Vy?`Obu%8IOcDG7;7z+_A!X^psKsE0 z4{wSFAMKJ1RH6JAy3YSlnu%oYq?aA%V1W++ue33cn!&q<&J}p>QL1(jP zZ3(;o>91KKBpHi*rS(bUZq`3#f~*v8{k!l#ek*E|8q1%8NitfdLWO8^&IT2=Dvitb z74f5FnBvE6*iRYWqo@S~iUMv8*ppq(3-2m9l=@pomZtuOnK?1K3KCl05w)b4vJ-x8 zlmThU81bVZ&YYBt1xwxTSuQ#~j^{kvyr&Jqu}gt2)BdG0~k6`P&p#@xh1k{Pm` z9Haw+;1v+0SLTbAFX5SfC8G?16pJO03R4k1&P^aqRR~cU&*&i#bvV>#pKp`r{dg{* z9>ptAI~Y8GibPh7_b|aLY2mEJH{#pjExsvr704j?G6)RFI>kI<&!51k2z1`tkZbCD zD2<+rE~U`{>$-u}!XFSUV988sElBm}zXK@7gD;=*CA~mNBXvEZ$@c{P>Jnb*y9i|h z*4ESvt~q^6{Q;uY`q{zxkka;?_y9`BvhU!ZVI+oeY#^Kn{@Ju$nMNNmL95MM)&TyQ z@Hu*u@$8t9b!+@q=M;a3Qx>+`TUWHc!pra!Yur9RoXdyszDhLm;oKe{0#;}1E4*)1 z`DGb$`ou)@I{$($(9!KVKffUCsn+sq!wPnv@0+q-#C&1EwAg%dVVH#qWyZ53FPLJD zs3@$%+t+%c<;|w;DZ8Jp*Cq-aPDGz)^<+C!>#WmA2A>z6g>7$xtb%yQpSfTl9ct#a zv97Y&H^a2&VWq@P_n;Bd!Ovm7(0FzNi`6$euO6s6JFYHr8(mysSV|<2MPeo{uCqRH{h;3=k2aJ;cq70mve5TUm+1Lb8cj+iXzt+L= z>#{nS?wGGsEWJ2yPkM|$S}BxM7SO(i{uztDl7+_!&pq^VNozB&pnRM3#4JmkZ{N;j zd}rNOqh^MT*dGOr?Rn`wN+f2r3mg55l|_)brmz&p_=N3hf2OGs4$gps#=JWyRm8?PNv-$!_6Z3yVHpukY!`ih|dMy`buGIuy%&5c5rKi)(YX~m;yJYcUrrgc}!Ze z*Z@42frm+txyz-+d4@^^F6C(YfwBoD;rSIRwl_z6(_A%kntnkubWwhO=6mw-U~C-> zMk`qBx5%P;js>x?2-P6hCuUR)S)9MD&19Nyt8qoHhJDTVO2~qVncNN+pNC!PiojXX zmm`<>Sr`@=d|S=UK8(^1S=`|DFD8f-2c@P_G#hSNP5e-s?1M3vIh^jPQyp*NJ!_Nf zw3g9m`d#s7!CI@9`#1IXe1G#n(3iguiM+uU0hXqykW*SF z_{>9PaU=5l27Sh{;cG5qIJO_sgchI7v=h$&{f(2v_EEsGo4%1HsRx5qdBJVY1aaP3 zXg%wwtVCh_-(!D3ZcSuR=KIui787}?8_9#`@>wy`4n^yciq<3N*V5RRRGIco6-=R^ z_@V4l!o;kFgp;$+pnJzzU!;Z>G-;c22~`nFE*$DM7OlGZCuCbLZJzaXZKP6y&=s;c z|20kdX=2}odTzd6Ny=GbC{0FfLssd)$W&$W-$J74 zsI0zBS|<4&JG`RIsiKsOf=KQ-&`h;nq?&STWO39HE1+K@HT~Sf-YgK1+~U8*E`yO% zo9Hn{mkegpObl6mnT14@?!O;D>pa+K=!D0(Hy@LDw`mdP?HZ_B$ztBj~*9*MmVrWIsA z>IdpYLnr-$byAgUw5mDZGJ6QY`wumYmSZJ6mpnzOapw)(*Do{f_Um^CEhem^xd**m z#?`s2JV)yWBVG>(=AaX-x91cXi@DQz2;3xlnkx7+`Jh0}TV!y~O`LIv5hwm*S4Ig` zDXhUwq$DA8RoX-uv^@RWUuMXAD}ce4&m*L~77gH4No$$WGMAUod61u+V}tvPK+Sjl z`sGGqDYz8Ud$DlzVy&I1(g^4EW8{QM#P zuvzJSe_BbNAT;SUj1bI!gGFR<0Q|9kml=0lf^7?s-C*EpZEvu{1G?DfP}b#7G-Ntb zy}mXdO8EmQFTVylKxAZ);GmA`$u(vATrNg=>4dlTbg2g&%%npyX5pmid$>qCJ~ zr#GbFqvtLcz3%2!a{P*Q?TCCRizdBbPoAc*chY)NU#2~}LUc|$?LWLB3xGDH|0YXy zfc>S0{guFCM>WuFfYL2~dw^9&6N5BvH)|BicBkSh{13n}UK`Jb2ke<5ANJ@Jgl^jv zr>fdd1EaKBhFYq6G|=S?1as;T7?WkhH@bR{R4?8N_GZ&yyIxm78=MXX2&r$WScX2; zsU_UuPjZ8aKgiehyrV7WXk=|LSK1=AOXpTdW$g19D4(P5OzKY*$Z_jwrcCLn4^yfe zt8&GiX%tglIi>c}B+BQUqML?UQBBir@%X?{)PQ=5rG`U@fIkiqrOfp%G03M8=b8(2WXwC+=5!A!Fmj6y+xBUJWGnOLqw=G#`yK)ax&H{Vh1JqN>7lxPx4*hq`;O7@f;$H<^=tUB!2h@HI~!8} z+xC^}_8mz3WDSFp>a$n-4)4~!S~b(Tm;4s%eppgOZ)u+1U%j$d`}`Vy4VPT|q<-DL z>jeJ4ZQtdPnr&ZhJ@niylvahbp}oFiwx>1NZgs?V;<#k}b|7&sd99VRXU9^# z%)~`3Ro}2W6;51sUWxLS>8f!3JHgfpcEPd>FxH_ae*)}*JOgiYfYr&&)6Cw@x4K=C z^#J-;xXxiO#-x=iO80YN=!I!nL$Bglb5dve6D5G2AL~{URj-u(W8c#WSuJa#{p`6i z5klnLKdJ6O#x$Xsn7fr5vwp6`*wIgTcJYO0)Y27QTLhbW9y`77{Zhp1=iG&gFujPq zoG(SqNgde$q10z4?z>|?=$$J)S+!jj8Oe5ZU)>t3)(KXNsK=PH?_yb_^J5;d9CNhh zjVG4uww8KFQVdgmqZRG^Cg<;Z#N9`A^ET8U~s8ykUD9Yw>4aBO}`q^?u~UhQ!G6;d*9g zE>YMUHpoO~%hTWq+7sRj5;eB`k%ti5Ld?X-vIfG&kk!5Wk5JTHrI{&uQYFrvaCE z@o}!?nu1qTas# z`jxkrGQ0D7h!z0N%;33D&s3n?TPFWUm!;|`>3@+#R*wD+P$karSg6o!qN| zYTDzOeO-2q0R8oN0TSj=1*&4PU!|!{7AkS@NE?_)G6&n`>bwQ0I?zHy-?UIzC7qCA z>1{N2$y*IqR_yq=V{>nI1@#IpoVvylQ&+Q&aCo7A>Kn3Ex>rLR+lyB|Jj7~fo9#{9 zQ!QhOy!9;lt>d?wsgP&Cn=Skf$R3a_-kQ`eZIF_FyvgjTv)|^GHFi(0ZZ%^ugEo3 z&%OUeQkI$2DclOz6}Q=p5wb^46y8`DPE55^D~Ud9bxHzf)+=OJNEhwWf{^HmijX(( z$=SYh%R)v+*}n54u^w^W)xL1zM$_52OfY`r9CI8-gmLPjT-kN##5N5a>Wv;t=Xu}` zF#f=;pt=^A|qqfW%BZ-7XAN3!5=z&Raji3faFD|0y;xo)WH*jMt?9`{ev^ z-nqC#Xtg&+(q!ijrDQyHy<>eqx5!@DBKW$hovr=!do+vS&C!BecUyF+#(mQVpjHwEl_J1Lip z3E}b&TWGX&VNA@#y`l_e{k`J#u`3&*Cz*+u_WUvB`Hzr}eU|tmTTvuHntEs#rVM~7 z_IagBi#Vz2oH=gS)N{mASuD7m+_qygYSpEz%u+W0yVq+oR#&^6Tcv}k| z&o~-P0XrsKW$U}qav0C>P4hCAjzU&U!u$u(?0R|dG5cuu4gs%N4#WFHc;N8!7+g<@aovKMiYvU;l+ zSFeZCe_OBR$-{S6Dz_-yimM znnM)*M*IyS2n@YI&zj@Nv9zNsD83Qhx#3XZ|11|rmdyZ8y6U*^gl`$6&PU>s9QV5VI)_E_(=tA>#(pAW znPwWGo^5~8^SZCWqN!2Uie;ZF6d<5Z8hd;igCvC#IWf;W2OM z7wp}HY9Nv$RNrz&3pmBTIzojBgSn4w`Y_h%6Nhy&A4xQFzQ*`yZ{PM6?&uBnh+1pJ zH6Wjc>`Js04n_(xk$CMyH8-L|6g08g36rD|SedS1Ma@q3|9w^}2O8{j#xm6w;&xOE7>m_|?eK;JIAmIkp6xMUS(u{p#cD9Ngrrul)K5E!&{iz;7&NLH$ z*A3g|tUQc{Jtt;S)Mh^lwPeI~+O52D#_+YJT}6V?{>j*U-icrs<*v$ABs)G!k5vM^ z9@~&J3dbyl@d8@}DfVh7rc>gVTM*~`?()=8VC2YL<)=`2p-xqwIuB}*Mv-1$*e|E& zTV9R$vSn%DgVe1{bK`RAKqf8Rh!F?q5qWnqorHH_R#Ptn1jP1SlturKqVr60_|Glk z+|R*e|1!t9)jYLHd)dZ*1T5KhjAF@Ibg3Lm29Vh(ohs#)S8#qr92_8Lu@6Qyhw8W4LW4qGJWe8bd4MxcRq_%6H@nrhn|bG^xU1ZXA<=t zV$SUleoja|jO#AM^T5|AcvfR(0d5h1T>WAXyO)2WXZciA+FvMdbt|v=Vdnd%;)iLi zGvdD!`sHNKC*{WW+#`6HX4EMfw&RJz-O4vvmhmXpsUu4zmNO?EZ1!qe*bA3zH7y*b zMx4R6*~cbY^@wx0TMt8L_v6iVue1`KmM|n`>Ukl3{XwZrYY$WK&UGlzu%GcxA4CQ} zC1e-#ALpf_tFO@2!cn7DMvIuR?ns`zM}DFG0#XuDxS>(PebCmfn-cl&Z>hYg1TVf#1O}>j5q6F zG2(yWyIH^56#E=s1^wH7gYSqOZW4k^kj^K@wnlsrU;OeZ%HfeStBE`R$QyfnHE8Xb zCpjy?EQ1Q-f04|N>H8eB9Y|%lF&h(ExiOm>#QWb!@Z1BEwy{o3u;;1Qa)R-bB5&Hx=RaeAb-K zO-lAdH7#{KQq5G(n2^~bIq@Rx8DFW|v-(JuL7hnX zZsWoH{!&vN0L7Zr71{GMBIS0|Rx(LP3_0-j>d2Xl{!Od5YQ5Sls_A9=C8)!Ea`Dq(4>d+iQQ8HtE!A#K}^?_vw zKH8D9clZBIJmW^^i!Ldt_dDp)(R)qXP{N6eFzF8i(occpDvhKZB)M(CV>Obnwb_|M zR7iP<2CEToE28;T4z>@r$YHcISu5p_?RH0T{p6Eakbrg2+mdq|u6(L_z3qbuDdb3( zdr5yl`U5Cjj`Vk*mh8`FLE&YSx~|gk5Z6-0UI@YWZbW>ym?`HRXvqmQzb%FSIAfaf zIC`&>?YTxhmZj`pO1Ux{G(UHiJx8*PCO}bACziO_uM1$B*P9BfH>DO87%vVQ_dCHyN{fU)SZk0 z-iIndwapp9J2nuLV;@69Moi>C_o@vvWdlgFEy_i}RyNn5GY{FsjinMd+0fa^NNn0Z z^CSjCer<4({%CZNv2k5Hqwtvlw5z(?0M`GKcuH9rQ3pjrca6G|PZbKG`4*7_-}mR4 zA#nP6drX=04eMa+G5wt_T+))zOzpE5B=J}~?aQ5IaOhvP z#Drg_eV1x_;sGV(`lXU|j2@Vtne*SKeigZT$h0oTSrwe-CPP0NO`sb49`ePWa;VPj zZ2Cl3WU7X-K6Q#P`YzayTzuMRLdpW` zeEH%lif_Bgn?2luxW7j1=fY62ZYBHEs*yZL0s5*`-&a2RN7ROU`|dx*8jbWy3Z2a6 zHO?ipDa?zIys-TfSwc+gr4`|j^a%Z$k-of^gP`hHMNTn?OmB>S%1&5Q3`Z3hRASm2 zttAJ~D;e6KpT(PgL8>XpDOJyhd^`>?Xnf8UlniX)`@>aW%F@rzECT$nogWkUo9MNf6M)y0%9) zx3u5#87qGnKga^18+5g&QmqnQcKEQ(Nl>5Iyvd)^LqQaImddkhVfGonHQKYLDJ5ss zEkFGbv|e*IZUTomz-7tcZdyb1�e@Y6Gp)`XYZj$nfG?b}LOf$k%#XKWhYM5e9eT z0Pr@RcO_)7MsPkZ+y7)__AnSkX-d!+qRWYF@3tzie6g;_EIiB9X!@^(XBe7E z|0e%TRTd{hMX606CskaX+P`$6n1pj6kicyom+ZV^b}gDHuXD%(`UA;WB6FQN49fk! z{P8upajqS0v?oktb93EFzqK}C1v@!3hZv$^#S|;L+;6?_od2N`L&!=dgYQubV)zg- zu+n>3C}Cn1I8yHZPhg*HS?OSW)n>#y1)$Z-oONg2nkgOWGJmVzZFNmyb3*HipEa$p zw#w}kzcsd`ZcXcoy7r$nEpL5~^^Ad5N8Xn5$KQKqCF$nzp+tyEShQC|C2}&df5oW2 z%-xUb$E5hPV|$|o4c3_r)_JwOD`UQPRR21rMW=M6%35C|Y2Uhvg($K1GCmxHe!R!N z8qtsE5D2$k=MLH@`tbx!lL`5c`2ZzG>qcJq*~G0B9FhSvf(f zWL6>lGnN&IejKfbkY8|lPU4aLoU_u89gm_P=kt2Xd?r6?8zymHp51`?Z!B|O{g~8y zxqMUfYW=C@Sz7kN`wVj>x=S6!pM1Q_dD0vg!YXi<1l39n*cx`dWlxxPs%RtJ@JWBk z+N&aXNvC#)cVx7q;B~&i&rv4Wpz*;Le^un5AWq*e%gzr%^)3kq>)(m=EBIHw_E%r~ z$=7rF8vU4e6}fkdE-~fZ8zEe4gB_}!AV)Zfjm*lY+j{5XGp`epGiO)HI?kOG2h^)K zieQg2@tN%ePNrG^p_!Q09<5BX6=0;P&r9@~^*h+i$2m`wIEE4-Yh%!I!ZN39`a zKaz=-XK-c2lab{Ll|9af9ncXNcVA0j&c0}=5X>=0&_*8zCtT_leWqRj4_2a}FU9eM zR}#(EdX=wQ;-$?pyf{$MD(lK5AMZ?SW|^6Iv7Ot1MTwoxq2RRd@8ku8_jAm|{aY0n z$IRIJRvj}su0qWYSa<5Lk`*S!$tZ9_N*0Ue?4f<9ngwf*K5N?Zx&%=cADQPT&BUGJ zugv;8B_|#IWw#2(kmHuKOpEJruE)Qm??K_u&?DIiTyoB*h=SgK$m#Q5@d0Bk>LPe{ zR{vHEK;(KE(#|wF*+?3H1YT6hL~(r?=j$GiW6TO+S>(_m)2gFiBz=PgN70AqzohV~ z6lNeR0~DDm5>ZV^{pTKN$)E3$dyREy1_d}gp)17A=knFv=hsoUKMxc@J6dbcVy;C~ z@0X#Xa+dv7BXaAhcV{By{vFHZr}>PQ^P!Qs+(`c&EA$J$yvWE4wWGvnVMQZR%q$Wo=6|a(3y+>QG{&&#HVu-r3^-yO5@i^KtdbvuUvk zcZBJ@Pf365Q+Ko)Ivb($Zg6u32i9g*qt&NdE={jtAS*!Lb)z#Ko5xu0mdL40o8!_G zL)DslXli3`SAKYB+6UFj*|1Jbj8Ofa=m%KFHXYAz`XkDA7ZQ5xCt5RjUZ9R!)&_M1AoSe5^piQnD+3kG# z?EJ_Hb!$Y8S7s^`qxew;j?|D7F-^6S-2w z=kO_8MYMmeg!oI^zwdf-^Ml#(q|kf1LiH8Ru3Lj)D$C)?RIUKM(n%fP=RUy6Oyv{u zZSQvE@b?%Wy-4fPj$xlri@Mk z5_|LKKn}c+>O?khR>c>Y%3ajly*%IY{ihp$&4eH8A1X5~!hSy{#-H6DTC87B{4lBbptNvU_ zQ53H!RvoKY#X8@RH&b~poIok%*Zi{5Y!=bd|M$YzO`iK`50gdg*3DGT98tm&m`~Vo zdyA}uiG=LS26A%w?E_gY_hEEEN-B^>nf2dAW(=8L5&bI5cCu{B;K6q0y|W7xWL*OT zhGX#?ESTgT{}f`*rp$SecvQ0Talu!JphStF|37J1cYQ48hl-oDE8MuA;@QY)5vbVs zp`1NK?dcVn%JccfO7(d}l@XuEcOe3u9U=r}X{kz`tt`fvDrGt{mCwKeTEm=)?7xA? zmP-|Ytj5@H?jEsKrp51naE2kNuY5}{$RZv`OV#~h(o*LCjueYj`2bjxE}1oKlRqj| zB0jMXEnxmnea#!>R7wJroImS1zv9z7{noS7Qn{s#*kyjA6EC|7jG4+m(rV%DJSb%^ z=_f2o+GH+yVfd||zJ1?ItXT968BfyMK4RcvS)m*1_{iJPwqc8uNbW% zs%Co_s|;t>1*}ziDez|Qf>Ym>`Pkfwx?p19fw^_TYZxE6{jv98)>l4}+jhV8vJofP z;hyDhZ_AB+c~v-ZGsowB9j#3Dq89W;^pO`v{A(ZrL$0leexA1lI)~a#De>RP{&b}R z>K28#yv*sXW|)kYIf8@(>FL0k%EyJTzkBC%?~PRP0*&Mp!1-w3g^*- zThOC^FM(HeRG%^}x#=MMWv230s_Cxp#Xx>04E=ML%8a4rsbMWZKh*IDVxNlo!^*X} z{ty{j=nE|Bp)&-}5vI1&?kcACi>TBTrd|W5Xk-)|naY15f~2dUk=H0KUaj61v{(kP z`u7FR%yC1hK!TW_`s!^VpYhtvsb=EHx{rw362ne-oNS+1&D7cSHG9y1QZk+YeU8`) z(tXPaYm$TK?vcSro{M`ZS_a8MGMtrGYO;oOPGkOgis%|Xrbdj(tNHaS8@tPsCqu$dgm?5Ir2t5+HJ z8vQf+w-ugqAkv+xRSV(hb-ze{z&$oH+AK z^5>aQELqEn*A3E4uAAhF__hOD5IFqU&r!H?{=-^6l{ufN9MP~+)vOj7FPX91 zsPc&)!mkba78 zsKt1!(Qx0(@a=BVz{kLV2If`^>VYDaFupm9wUv{pr{MqgJ%8CetO+FWreUiQXIjDK z+#xLx6UWH-TV8|{gI;=138L+fRF`y#$BVl*u&idQ@QTAT#a_m}(A~O8A(ka2t0?rdpOo zaQ|Oqe_1fk`G0s@Bo*R!kf&ir4*i2jY1jepD!(8{p0PaJO3F_<`&@hbgOimcB)^lX z{L^3-&L9n=Rj1B)b$C4zDdcly0=SI&a{A=gKN&2Nkap&d*5g_w?d9r~tB6LfVf@QJ z&O9mb7gax|pHlVB`xR9E;Q6TfeL_DBX_suiGXf&Wnzs{>b*7f;5D)*)dCc?ggO^rx zl|G<_eFq!NNvs}gVnIde&0*{MO*B=0F*jr##IE@!j>5UF4||U;=tE4}T9~UfEZ%@egn_>pPq`=SiP{AITA_f22NxZ^G3A|BKeY z<;Q2u!|LxhG7yX=*d=FxP2+%iTw!g zFGPNI>Oh-X}Cc6>(LSY>c-h4ZES#8IMD6V&m~ z-r1ki&h`yltc=E8W(~*J=1OpfDH z-AY9`+3jcqk5|*yT>e#JpWH?@{G+oUa!Z|6=r2VqNeuhoH%eH-Mmy4{mhsyexS$nk zY53^gN}nc?%3dOKB6y%VcY{lYS3P)r2&L2saB|*wH-9s}U@SkKuXT!CuTIa(E|Aub zz>Fp}t%H!nuydhDV%tIGU<_O7^dWoMFAnjfNMOhi_9;tDyN+8q5+BnwkwWP=r1R6^ z>HDhF+ZT9HmZnD-SbFfdO$+3PEKJivxnX=EyEQNHu)HAPspd)d#L9!fMYnz=WR(u& zx*)_9kM#eAaw7(yO>V>jV22S8H=S}*t$zh?e14oFGiU!-GS5O5zO7m95r{B-t zmY*yBvb|NdmBAzVu`K0YW^g{~k>9OV9NzM)EQg;wO#-Q5C!G$@jx5-Nz4#qDGMpbj ztm8Ivsbc&3?D&B_$Ry{*5d^c^8_X)N-m=7dFSN*B<*Y++P~PtBajyP`Ha37oWS6Kk z6{%W&tWrQ&@`GsM3dGm2KyKvCLb*YF4Q+A*{{t0>uL1EfY{iyVo=*dj3K9&;6$u8j z0_3C{B|r9BDe-XshT zz9cT8D0BMf^%gmD?2(`nKg22uuWNw+*M9L6~^eptSWtF!~4+@GqoLMwgjvjWc6A|83lLKh=aeu7|~oM%?0o z6$9s$ZtsB3bK$Mf86VFLq_fpdUQO}G&g)Hw2)1P^$I~nVgpF=ar*ZYAbV}k@Tq^NX zz@C8p3sn(aEC^WdgslFnm@rys9dQp&oJ@{+OdSZmT>R%e2gRvq-k%iLv-MO_^rkjl z$>>C>WSv|g;+{|q>$N=77#zW#l1$~IQxrwLp@>x=o490M%!^c&aSpi?Q(!kNaE@OF zTQIsvQVo}!N?xdxh1t!(7W%8ECsTP9v}iig_meq(+HN3|5_tmZ7|o5bgI;@9n}4y? zM)b9yr9EJT8obs{5}=t%2kIE1lyOMyT@u;oDVBpXl?F%^g-Mr3*eEQo+pZ3+&GAS7 z9vjjg)jL!9p>C#!QBcxVE+qy~qL^hbXovv{LPP^QR`bw}9c3*N`Zl%g&C#P6!)cCQ zbuuov6R~6}r-GB&#Rb_Elp@%OKf|}wWBg&JaiRI(i)et$E@d`w7E9-jNZR{3b3aGS z&yM2<=s6>^x6vwx8Y!L3YdHf}7ITH&9PIFR>QX)z?f0o|9@a}{;Gy&?8T2T&YTrvj+I0+kP-66NQimz+G^GmcX6lMbbN#8KH8%5;;tz4D|Imm0q5 z+)OtAV>Rq{%D!N63D-xqD4MM6;8Lb?I2_X&vUjP1KIP9Nq(!R*7kPOCJBwy;B zt1-4RA)RgI-LLm(C8GtD_ZpTnk`g@%8p$5Q@$yOk1z?hLl$3+Z^K78~5;01XetsfN z5<%sfB>NYFTcu6HU;6A;+LgMN=H&E`{6BT*cI8nf%D-idB%IA*9t37H*)EL8<5u>7 z`Hw>R?f~jLcBJFqN=*;jlRX27z;MbP;L*@3%TdI?9{Z7+hrNHN(vo{=mgXem7JhFh zt@VWs*jY{ve~oUS2rO0_8GH#R!!&@5@-&WHt$0bXNKWx!Y8-CMEQ%5Th43vGoF~e^ zW=K=afzwZb18M`Wm=e*JW(p8=vahD$d1o#3z~6-&kE-@j7Wn&cjj~-1OZn)mr7%O{ zzifv!lSv`jX`0L5$`7d{YbtKySw>#ib*TRW97+##RwZ=-U$s4kzgK9?PjJa*&z#<% z%kg)#z~$?l>h)37$5}?qvUjU+$WHVtUk?gKYm5 z_-^~Py5)ysJ2R099FByXt#G2hA2YKb>czB7X~^B-xA|3`NJGPxmShe&OGCp)hrh37fSlh&_s0O zztlHDFUeK&nYsNRUfZ)OCOd&5H0Bci|BVExE8Umm8`F(nM~;w5wrom%#%6h&sqDk~ zOni%eq9;A&NL1aPZQa__jo&@_FZ28MXm4mzJ4|opKg)ev@1|X0JH(yX`w5}UN4fr@ z<-KqCv5k57kN+p|q49b6?)WDm)6tD#QS(Hp&sY?{qa8AYzEGmHJx|}6K2w%sqU5j@cZ)-^h&G2n+(1NN{l{AGTJM&#AbPkkOCz`C3H68^XXIOq*+jK zvhXvU82A!V*wq5*Ct(1CIoSf3F{&>_Uo(@-s9$0lexo|Nu(?e{?vmAJ)@g_zB@+$TBv+^`X%sM>ccl>O!HJ zW8I7RmLu1cvy=)nTPyfs>O}b;x2yi*;rNx}vzDG=kz49%a4IG0o{pf@lpU(nn;iR5 zTxyP#x(N9e{3F0_4gC8az~>9_cT@q$Z!{HidVriNAnLdN^8N)0LJW&ubh2&;4D|<0vUd~JH(~5yXD0Qv%WL>m0ulMxU?b^TUPCl?es>U z!J&$2nyTsEMdn(YrpB32$lQvUCOskRb2Us_Nnf$(AS_GD`VId~ZIm@wh$y1K-~SKW z^AOp4EKk3Ddzxqb58E^C2ilYO-zM@1vZ60>)6gLM4YX8DyLVnHr)8ybLQX2j1kNgp zT%MJRfyoVEMU-sH*srE#vlNN0$jWAyH~LgoHkG<9NBu`mHvhP}&=#iu^YL%Pq%|Co zNyJk6i*7OsP0Y7R!13_9{+z!-{@cD${CfEKf~7uJY7q~Sb2{4J;-7%uU(+z%a zg0Io=yNb?-_#*lP`28CG;Uf4Ke+d4HEImc=^L_|^u7-c7=$wele+d3}8vfQI_)~re zezAr>p$L9YDvl!Df$n{xxwD|0_?=3m6IR+CRm2v%lkYANjMNLB1u+T2X-i(R-@BfvQkW(kWsI;_>M z)ryeCF7g^?Y(uYb4O{xRk|uL+kgbtw7h2t#OlAMWWt_{rpAp{%O1mE?Rh1^@W-ISJ zPSu^VI;iV$sS4y~Vswd>q?*+}SJI5V1MZJaSz_zBXP#~>y5K;5#jam;pzgmbN_$bi z@&g%u-9AzI>I^w#|DY0JA|E&JDv!L+ph}$|qka}aHbg8lp4~o|#F){X`WSzdsl4kj zW;0jt(~3D~if#B){cau=iQieVS8u$@}@_BS4OC zI$i=nzqO4j9?VstRuio794uJXD1FL&4e>+|h;Jaol{y_-i{?9L=5oyvPl$m0ZSq(D z{>mGGWGc_TRU+AKEET#8YBK9282b!y@KYHJ&6nQXG47v_{&Klj@RTS#Zowl3 z%PAP^B4GPOgcs}_CSM|F4HK{^Kk8oour`{3?ygAr7; zieUpJY$KHgSAUNkE^L0}^F7lDI3$-3XBqx}?t$cgSK?*`0bSO$vw}nv^M!Rf0*6wEhoo?;ajibv^tiBm+T+Cn}?ex1gxOOG~V1B2Y7u2@_2q zRZ*-WC`z?zwK@U3fPtBT91nx2VAZNcYrWfQTOpuA0+Io|Azl%+fVVTo3o3<(!u&pK z?K6{^==XiT@B7D(=OJ^>*=y~~+H0@9_S$Q&y$uSCBV%$~`mL6`7rAuNT?+3ng+s(t z$I73Nhw5D1fWtAykJ?E=6gdvjGgnuIoEr%48;!|oAw1QyieTFntH^&Ls?;%*ze zjwb@_HF6v0VN=Ibm1j&?p;;|tS%u&kaHbeqhdvWpdO(~-?L`ha~)a53s>-eRL+`hGa&Wx3kG2~xh2g{ z1sTojI5|a3BL{ixba3@4CE?oY_~|LEN@;z#Bz$shWn1I7%2C){JdRpILmuhSo*i;n zrp3f}xGLS^1~>{|r{XQ!O#cG~(cv%^02<5>{&M#PLF-Pp5%?0?A53k%cCaXHq6yTo zG`$SY1T3KolDip;rWdwC-_JUgzB^2Tce7cUP2X?aN3e(+`u?aXMD)jyOC5#l&J zHp5Yca8&VMuN97x#rqnk2s_uXw4GrDOKUZ?Id!a}({{F#VW8Jj^Th%~rO)uVXZ$L$ ztvzgN`lYVlsd%bmYsQ`coz64W{wEP;yz#lw{Vz6e!#_)CUoX?X1_NjVnBBgOZbG2R zH`QTh`+s62i4)3&`kc?$VGLb69Dl(9FbK7PuV;bje@VrDdXFix2;i zA*Z0JqOh?ewSAa|kW&?vKQwL<)mMj!=-7GP`L{GpV)2S7MEry%F~uDp{G%{# zzs3AN$Lt7x?(7AXr($@yG8CUsR~KI*_CC13sgf&pBU0P=1a1p@+N(JJ3;49o7sDU* zEtC4t`sZ9i9Ec2 zRyI=zYqLsy%?TGNh;9IG=2es_y#7P?sQQT>h2G<0dx4wcJ=jJ#^vRoK{z%js0`M_Qp% zoAhf5q4=A26*O)RO=>8T!@3_ai*nJxp{`U1xu5?{x>W%}iNgL$1@lTohrz~8v#9c& zn_dw_+@{;y7Qsj;hJl_JC3h*h#J$&~$p=k~-!JqF&1_c?xCf}d?i7U*YZgUw;8kmV zk$xO$Y9PZ03-l|rU;LD0OjNTMow0v(*9StA&}9hqDHjO*d**z}m>IHWqs+9UD@*}- zT7WsH8JfhM3nTX5Dk4CffCSA%`g6{2aQ9vdQ!TC;!mx@svt)>H_xVAnzqY<;lD*Q2 zModz8AIZe)$>czg=cCoR6|7RB8QO_^h-}QD5fICyW(cy%|Aor*;8ayDf zvwC|Cx~;a{!+Xxm7_+oa5eU{_Wa*-hZ6IFCDCe2p2 z4_Tmg&tvZ(&ly`)zDb<$WW6IX1;pst(N9coarOgQv&_r>azK z=EEsjh&$)6M!sRaY;_auqVek;?P{nSUBuQSjvJ$jb(3>;%6}wJrhI&x+(#C7RblE( zQ2-mNo$2pW^p{CpW}uv&Md^fAa;`1a>ycEq(6%qT1V54KYYwxbJ*cxa`*{AcGKq9v zZ$z&b82DvxU-l{Sykh)E*vn+mMzb7@Yqk2#U7U)WzDcbs6S%1@k zw7L*50&y&t*1NS7$dbh!hz5ruBacTt%6eg;NItDR*ykDS7r@R60bi;UzT1l&l9K_S zY~a1d=FwPMdO0}VTbf?Ixi3#jrGCB{#0*zYc?x%3&8RfH>e2*v9@xn$#5F*h07@Rj zGsI%_KTajq1k{b98m@?bElfv809kJ8^?LuVwy2EI#+Z2aLnY(SU;)5CGo?QWc!qEy zLfsMp5?5z{ZZbgA0g_(y0NpPy2IM+rC6UMMXXVO+acOx_=Uh~3zf(JjVJwb{uP6s! zNMF=C;Xx(1<`VtFoiJB7;bXGTpo4P~cRg-XEwA7-oEG{K(Ey6eUG0U7YvTtK?ZMHl z44opb{|i`&hjU@ z?N?o-V}{!Ux83|Wqi&5`K2N%=deD``lqX`KvN)I0A`-^shyblC28tk zO`aSodIgA&KT{UEN+6_vg!7rH?BMfmEl^JIdDPth!aW^-K?}&1-{+)HlxiSAq{JUt zUcQIm4zh0+FZ^?@&A>jcz1E3$k$Ug@kv54~n$!YDH1i+<4n6gvJ=!jmq!(+hOf_)j zDY{w2(?ipz=b8i{Xm67PdpgZ!9Ro}Lo6#mSO?Q2@3Sr1j>w|(!gj7}rrF5V8$lh2I z*?bt6Qbw1;J;QNBdjpWV_`ifNiHgoS5xLDTGAu9r2f4a$Bt$DRWbMz%CvP3C_Zqtg zOq5AtWD)xc63A-46c*{+9v(^?sxp1U;$dVdEn7@Z(+&Aw#agFXqz#`_B`IFr3-4EOkMs{}Y3V5qo2}@-q!{$l zuQ+*AR$uvM<6>+aCH0jX8}Fon|NTVSbA|bA}t~^Ql3<8gvPBeu*~(+&_THR>4Cs;HprhMMaPm?IlP~lPcWyw`SiU zV0zJBS>7raP<#w~>9sI4w|Y2npu$G+GqmJN^m1{y)4d+JQ zbx-Dy1Gc)&#@#FHfFk?V&??pORc1Y67PVdRxV-(9A(Z)>3pKIU=EBSk;r;>aTih%; zh|8hdpyGyl3K}gOsL|2V>l?*q@guc#Z2gh**XFh(Ye`kfWcxIUyK1V2|3H@g968j3 zFn z(O_oKL~zjs7yROa_TWQIV{E15xkXZ+_&8k%hU^cg96+~>&1>3qffa?hc{sv~J}EVb zU*iirU&xauY`$^p1ywxPxMun>0kH`@{CVBr&9(VIhAP>1*b=fvDKB+!m@X8rUleGs zJ~%~S4TSGL&4mXDO>k%`Z2USD*;6=W2;R&W`NWVh0SnEZ!1G6tskF~p-UsK+;TI5A z;YFDnn@18Q=0iCj+)2m$)See;nx21z6_Z1tkcPJc-iGm}YSHBR-OPaV1^xmnc3>Ag zZ+!&5gg-y=$LLzOOEg~mPQ+8KK6o5-dOft@?-_4Yd=XoW>@6-B1N_m>Ov^Yk#1UTbFmP+d7R4{$3| zE9vp#siYGkuD0!yLbqcX!qEPruHeYa`HIzzV;`tD{oQ-+L?PCM21!726hTw)h7Xb@ zX&;i=-pO~*ln3ofIS+y(qAa5XBDql5v5KXTM$bB25sH5p&klj_8qN&lyDKPLr9-+O z%$lU~9j4i$#zWbiIcAGwzKQHYR`3n?ezLSz+MS3U_P2`nBNc^sTrp}=#-PaMPh!z^ zSB^vdc7_&ElHEx}TIa}Sinf0U#7FN5+BqU#V-^n%P^`J0`R%6G!&V)l3wLN4K0fi-Ih=~Q6xX05FfX=Q8!8(Hh!XBU`t#{_b)-%V}=+N__+ zRnFd1_HRwu=To*0D~f#$Uk$qVE_MLjN$7U~>uyuFy(L>;p7}*5J(^aTsl^cTtac9h z9T{L+F3p_gwB@p7Uw=}G(opA2Mor-`N!(Y=7amKk=+|iQp~!NzmsrtbMf|2+gOe=jUTW?%xp2r zY}S;QS0(e9tQm|e(K4P|0~~VJt*628ABPw_9+L5|Q7E_V1%QN`#wd{T2PTLO)ND~% zOU7=;Xe8C1Y?tu1W3t`QqoZ$TehTJ)Nz`QB+gi&oK;nNHczrkIKVq|X{l^>^%jj}f z!ggnzBYiLy0mF7!yP|}LF_F8{s1r!x)Y%+9kI2j02SNG{H6ynXCbv7uO*>N-jrru% zaS(}{|D#1+pPl&eSk=8;;-Hc*zV~O5Cu3>mi_)bTol#C>k;5-c4ku^l@E|#KJWt|n zA8PgkBvI6ODO)Zg_zBVJh&0`iJnFeuD!2*P%;&?a6JgVAFagaTEq z7t_@9rqeF%Dckh$o%WpjDm$IheIH^@N=mddPWBIAo0nXbACJ<3t<+4)Da=q@tCIz> z{d__o{1t6gl0eH!+Cq{?C_RJw98jrbGk+te!pSV&Q!{4CA-oTd5b2(JC z{b3^bCe@b#*Y*O-2=*M&f=mGs;O|;@hmpDKtFL%VUViV_Kdk2Y34#jUcQBR*v_@3Li{VI=5 zudwBlD2ePT4WBJL9FWYF<*DqY{O5lyjo%h&9R7u5$nEXAjih-tKB+oX_7XFI)^Ss^ z8bUFN9rFQ0BMf!rTq^{o9kSvbW(d>|Bc4a#WUUi@QQIL>!`;vzg#MxvA+l08_aeJ` zgzqeGjqHNft?}x--5t$l<85a4eAs>e!SP=-7K))^Os#f&tJe|zh&A^}jOs4gxbk>9;6E_~o0DENu$6Fe~`T4$*8-KiKiiuat&%)It#VX)#|JPT<{ z+#!OO@O{Du`G;Pb-YO7##Mx3qwUtz*{JVF86d%7C)#!Z)BAOxw`aiMsBvL6B$QH>$ z>67x`EwG}Paq%#U7KLIGcSiJ}vo#Jj&D&qpaA)WkAX$@hMWe5fFVjvXQ^cQ_&tOO@ z(&KG5*F1BCEEa|GV9PXTfuEg7{FZ;qpo$;)3d09IVexf9&TL-R)^& zAk^5yJJ{eg8N4*YY(rEBJ@*)Lk+@; z9E7Ancsv(j6I^aZk2eVOauD7%2ruU%Jg5l64Z`>wgoHu(PcFjcig1QOI4%cau|ddZ z2teI5m4+z7Zw5P~@fw;F`%ECee$Ks&tnpd84cfgG0uS!y7^K}qSN z#Q6sD>MTeq@c}$;MNc)AXzfBEHqPk=;TlEwCQa*y6k#-J1c~&W(77PB<6m_ll$Oh~oasbJIp^+8XlH z5bo6!7WZG73v;-_yafztzspVQscB0|^9~&f{vUH;-aAv;({Avu%1v9YX^#v3vB(

^A~$d+_&V!80`0!P{1BqCxAH z_IFLI7VI-J^&7;<%<6+#3L_4M)aAh3w8@%g3x1z8esO?}1m>G<-t3*QV*mOcfX{)N zOnZt4YWfvf=`Tt8x^#NJrk|0O{=TFO7b^ai4U+${S?OO&y7Zu?w`qExtn@vS{`++L z1Df9PbyxkYU8J9$PM@jiFJ+~dO8PPB^oun8iLCT;N#84-9?*0rEB!P{{~UGLv|rP& z$Vxv;($}Ta^ELg9tn~4c{&+fl3x-_UpOyYQNxvnX-lpk&y3(UdB>g`AX!#FlddF9p z_D8Rhbg6`<&(!pny3%8FCHhHXi351>l`u~Tt$>ap7pJ% z^-l0*Q1>^eMWA}d0W|&!_N8Tgz%9!BlsUmxT?V|wGJ^W&nLNGe3M=y_sfBa=7hlkA z@k8D^UDVT|dr+K-EiUmg7Krl6T~vXVgP6$VIvL(d0xi9|-ueex4(@s@O`kba$g)5S z_Y$S?hHzJK*IPxPg_$^=RuyO|?RpCZS`O%XYcRVsUg_fkdee;eHZjn$Zx`fcftG!` z-mVF>_`BYw1zP%N-kc^L11$r(J~Zox{klGg?@2&|f19G5yYz#sU%U^C^uvK&A0E{Y zebXNzH;zMnXoZBePT>xE%rQN7&UO^=0?`b-elu(0qes$5vM`*v>S@xj;1^i2DNGQ$ zGR)nLrZ1-=(BKd3_`KX`UL+!``7kr{0mnRn==z{hm6>oe5S*72h+8us%FKsFnGZwE zhlesBD$Iw!XFgP!5C6=32$>H{G9MbuhnCETapuG7%!i5Q!-mX<%esHK#(a1^12N5f zcr*PW(gfwqx2>6P+O^umk22r1clFyReB-J#>0OVU(rcvHd9PCy|Sv~ZpBYUwZ!BarcQtcB3CJE>o=4o zEGHMBypRDBn-=mheSV9rzG}xeBdE)Jv)wn>+wMEFLCpkVKRen(#B_p>dk=iv2fC~e zTTyX2cAU{~bL8R7FNC&fdwQL7Lj%Q#KQVVBIipIYn0jYoNhof176}ImZR;i_F)mcs z!YERoj+_;XO%Km@YfrSJ3Dq#?+E0HwT>7E!pCuhph1oh9Kn%+bG#!2`)17# z<}kr3G+z((_&nL;5Zib8g4DGIZsT`r8HM!Kv&1Bdbs1Cf=LJs6Ote~Hdc0L zY^$uCgPVEVranCO*iL@e^A6p{zRPcs)qFkGXqs_eo>Oy)%o0|!nDwaF@rGv>Z_7w1 z_m*GF9zQ*Sm2exbqg|D#c1B;K-BahxZlY2lnoBLIu1-dfz5=$OT^}zbj$C@g<;b)JSkU|@2HLUo1OM> zZ9GJhFDBVO>}P@}!O_P3m9Q4`u}Yx>VAm7(64r-etc$eES()&8xQ|-1vhtzi0s#3o>AL(mNSUMBG|6@(D3A~QY_(1-nh zqJTFP)!KvyM$+)Bl7`=mq~W<#?&!jAd%`sGNQ|lwd~5NT^XlTGhjUVAkVq~$$Fk)!5Cx-fnK5OL9Fm6Ef4l^0?BZrw5L&v9~<7Qe7h1xjRq;zx>r=-Qt zpP?8Klb0*RUx3IGKeA=){ux+0Ow>(I#qrNb{Ih!ww-%4;8v92!k<=_95^g|p7}d{x z4Yy8}IVhhZXGHF(G=kb=A&^QR2qdxg$1<{IS8!~Z)x3vV)jH8Zvh9d#3jQQ9$<-Nk z3FkAa<5Tjr8MTvMb&s4%g=8*lgR~V^^hGe6rnfL@d{u8>9kODmvt3zL^_4xb=lE1N zX%sT(Pf}^_VZ(c*zQuiD3g0Cxg0(mwa^3!gl4ieGGDBXr%|(@V=Tu6&f+a+Qt{^1q zkDSzm)QBY{Ny@(#XLBhB(TVuEaf>H@tmyt!4iR+uYUOb0nN2S%-H)cIE-~bmN%oA; zYaSPe#4!~rhF~%)3S1sz-9415rWpv&;3O*xFMgZ3&e0wF$p0JVquJzY=qo!zvyoNK z)Ju|4e#PH*jOS&4Ph(ac#{MXv8>vQlYi;FQ)~tLof+i)QM7|O7T<_qF%?mV7;Di=q zWvn+=#(HCAY=1LW#xh3E6;>$Yw+s<4BQ{6GXLVhjz1HmrQw_TiUpC>Sp&JPLEmrSG(Ele^*JvwPCTNjku968)>o)ldTy{H;|b= zVdx9~NVD^V0Fe~f-uSz5h1MjHK^X-KIk$9@ZSrjZaYXo#A2TKN;;Wewnv;_pztNgTl{n9pR+>eoL?AmYDBVI8 zXUB9M^6QaWuPzrq8N)gCJ+C!~M8935R6gS8>btkpSCl8w@&=*hp_kmJ`|KTedi%fK z&JSxGAN!p|a1mAI-t~vfk5n8^&p8BEto|_GnXki{*PBk^{8swF*Qd<1W!VS5KJ*TJ z72Z!*t6#Y}@TE&2aoCbgKp0Gpd)2T^gG}#n--Ow!6#vb@Zv#!81ydXNn}6NW+sT#J%N)12 zi@vn<1mq1g&3KCDoF_8%EhU;4Crhj2r|sro>xrDYo=b@mhJNa4bbS$HK0eaC^{sdEan{YNu3Q=Rqo{ytPFi=CHk#1-X0=EaUuf4}kAFf994Pgo zTB(kWUHtNYlz%s*J<(ZHa%PWWv zmU}RmP^k<%Ul8r`|87CaC4Oitol014UMWGc%o##?y3A)3yAMKgc9erZTFn(w54P~1 zRT^CXku+a=NGahSSWeeW;sW6GVo!82R)R*!^3<_j!`+Mi0vz5iNa8if-Bx1d_UC;w zvRLNcjOJAjZ^^9!Xkd0d+SYlL9@tShXkugEK+{cw@_VDH@JY$x+}R|Yr4u<7;+Z}5 zZ1xT}j3WKlF9U6l44#OX|5iAXD3v5^1iHQqJA$pTK+cd~wySIXD*U4MS5DYJuF z-<9!O<^+Fi9x36;entfVwnZd>%+Pp@{a70xjb%{mC+_p#3RSJxJYL8`qba5QJKo7C zVT~{p%=PheN-UYt<1Z@Ndu*klN_DzC&;9E!0YC}sSmbeG@>(!u{%eugh?4`AIPx@} z7)ta|{U&i*5m`3AX+ik^YigI~X5?Ikvcfz^>g;tQq)1MVnBo<&AnBU5X5 zE)2BII3bj8kgF6=c$;}awfjyplj5F$a=dMsgt%~uPX-JBjFXIR^%%6mCUz$^UUrE- z*LSAg*1)>BV;m!%F+s@GnexB!7QPoha%=1`Rk%PeP2-1_2=bH>$xL z+)Yk#QmZQDF7_~{f>gsb2#fZ{7p>(Z&kId@NA?5a{myh2+##aBt@E(R=G|C;3f&uT z>XyIE0ZwK1)Y6sbG|4mkq;B4t`BSH%Nk0!hzlov*!-}yeWaJgzY-A9XaTe&QTKC5r zA>YBIdh{WVq0B(H{8M>-2E4vpIQyq(`hIm>w|aZ?d6&O^S(l=lJ`zP0e)c@np37uy z((OFdX69n0Ywlqv(O-(;E7?gmu`6KQ%o(W6*W^DrD2sh2H1iAD%1_s&&RO_0RGA!G z+a7G{*&dv^s699<)gFxWZVyJew~pbi9w6Fcp}IV3daH`mYSP8Geo80~>xk(k~GO4#p=}oN?fu(ZIl%BO5D6u&|iraR5lfCk~A&(X|!f4?>tgCmd z>=9_rZ@f|cun_G+%JHj~itN;#q+~y3j0A^ZLuAPV%imek5^>#U^e*W>=} zxsEb5x?534TS~xe54O_BZ38FUK?0BjTiSy!@@+MJ-+nmX)`SSI7wPOhrEe%v&|4ZV ze+;==A=lxM>vDQKL#~3x->1nX72_r|W^+s)`*jg$KM2IFkV>Fc5U79M;Ef)EUi_a3 z^n|V~g+2w48R}H;_hZMMS=1@m(=o^RbLHC2VjJwY!zZKa$EQEpu@?qGr~XNTJsiof zvDcy5;O|zhj%X5AHZyz6>`^V_X1rLj11(K78bO!xzlTRC6Z__?5{sD zGm3qa1SAnFg|hOGTJTnueoN>b(k3A$HgPgN*`Y>sT^ z-jrZjwY{z0{*-GPotUJHHihF@o}=QFo+{?L#uN!wbj?06?h9fq;OOL;)DIW)9@d=0 zrKWQA#j`?HTq>thmBwSW|6!8ywWm7^b_@9fOM8OLxps&k-mnrEHTp6Mrawwatkv_V zYH|23<=-Db*dq~JM3VgD@lo?cbsD6!__Oo*$*`CcKT*E2PwW5VFO2TdyFePFpB?21 z=BKOZQ}lv)IB}^iCVHT|=t#IPq4ATX3}Y2|LCXvG4LNana__iUniyNev&;eePJPII>!Ngx z7+NxTa!hTkUsLalkp1cK5R{;&)iF0svRTWNWCvmNQv-)N1`2GR`#XH+>9Ul6^zj&) zIDUZfrB;F(V9(?bf)(3=tgN?p!>AGEDkhO&Ly_UIVZjP()|mh#|085`f(^n;4#wT{ z@HJpG3sZG52s1TBajG)q?>x?Q@FYv%o}FKaez$@Cf^)<><-f&%$9ne_mVM|Yaag~>ifw~vPF#>xq2wT-JAWdm zBE^(9t>{(#d3W?BC^!2`rinc8;BJ^XQaPD3131!IXhj#%H^S-q7zBOAU$=9|C^sc%i;V*f(DW2&)kG1l5SbMBZ-nfwOe-2=o30Uccs^lOg@g%GA zI7lWDDz{nDrzjHkG#fI)qYK9KL3lI)ov*Q?a{)kx*U1^jHuu+(>WrNx_K){2@F0=- zoc&`X>^Yg+#n%X93=Mlu7(vXo`v@1ybvl8{AMx*%9GwH0NRNM%95QDD@%3PG;#5oh zHQeiSS+)HU?VeceTsqGEnxY~vG?86_6}?lW!=#wJVa+@a?qL_4!yM*O+!npb{dQ9g-BEf8@0B`njUXU@m zoQmTxWxhe8HA*lig=ugWyLpa<>WVUQZR?>x=$H=9~)!v>tgA*n-=l9zsu z2AheOB-BMzPd}eJNjI=odtAk6{WY%3$B6Ple(lV5VJg$kNGBrs6NExUsUmJii=^`U zCP#5%%Oue>OlXVk1Oe|+*RUS&7`XZhe@3R4Aw=@!v5V_OJ#pe9U)?n^~_q-jH8Cj1z74i3uz6 zuZ)xm#b;blZI2x;!Yg_;O}1ve$vmjSs}C|l+8#ZZ@7{P9TOk%pmhjPQ_cC!S4n^S0 zhIu~YF}ZUmyFDc|V<|X!?%#gv(U~)``y;S~9qpAV|8$~UGOM#>ID?}w{>6()iWi@H zczzy(C1l^bTC_PLM_9CJBENg{JC5ICejE7h%WsI^KKxekyBEI|{PyM-8jLLBx6E2H zQo<~iRyzgmzt58rd>;_85!zi(d9dvYwjgsD=2ceac4I|XmuXLG6!E~)eQA)WXKdb} z!~g3@aZ_whI&4yTI-W?yc+~}-$i#dqgiN#hp>Ua*7|OW=Nyr_$O&Bk7bAP6)R(Ku? zFQN!1-o#&yz&u0G+7n7c_Ne}$No|=ynBR^`D`ZbCvF7e!B8q(9! zWtp68HRL}^S}klor;I^}9N8cFR^=15a1n*bzhsc2v&Kg}Rs!jf_cAA;C5Vto=zP^A zPmoo9jh~??3PW^gtN53hi~Dp28EJnLQy=;Q6Ph3$n8(#F^o4Lm+9(2W5Ma@4k;GOs zCiEanG`wf403=iB4SV#WE{I1{jRtb?G?cH8;II~glp{p%^N46vCp47CQ?1!k7?YV< zuz35ww8vk04f-f&euPj-r~=@UA)XbSOlo_v7o4!_d2t9qk2q$v0_afTNZ9?c6ilUNbna zncG<7zOUBPrK3uvu=ZZ$ISN}^Y!L*=Vi4iKWGQAjN0l9JjI)(aR`g*8bbahgD|#Of zwN8-zm5WG^GaTE-YymS}!`X4m5 zgN0N%8k3wC=- z`rpR0mT1;?TV5NMR1WPC)7nhTTM9#i-y;HPC?0Q>#X|m?_GpjSe@vzFlGh*x;9IyB zmW6Rs{w;(X(8Y}v{T*Y8n!ol}Dv?$!i#I-{Joj5P#qNwe`v9tZLe2m@;_nK59MH<_ zW_jaYAdp2sc3*K0`-j3GEbz)Rvf})OKri@4?9~f(`O>NvTh!s3WRIQpUFeDO)+lGB zd$o_^g4gKd3}u2iheZk@dxp?8D!}-u5?O?pL>5WrEDiFiQvN@of*5I}S^#&*O|zn( zm&i<{EMF(5itFw5b@sw0FcPs={vN^qz*6}ug;emXg~*3xp~AzZUxo3}_H0kfwTE>(_ZiYc_O1W~x}AJm>`30ADH^i)RIdBa$W7pxPiZ&XqmHraQ7?Hnm9 z-W;5sVdN&jlWSjc?LL|+B*%}bLj+S6$_M(|GzV3# zZEJ!1MFa3$$Ed9ORk0ukL&;JGv!km=S#uU6JIr*EmN&1`%uLa~mNi}r3`N%NM{&RW zDm^{Q^ph;*74Dg52IT=DWO0utls&!2wZVt@!idD1!?4yCXdc_&-3ottbAlC<+sV6l zdVMz8jQuO{6!AL8x`^Q!ZufM4w|U zS&Ogp5xKjR^OwAp6V0^`X~M(mEG&_O%zQG$jn;znLQMi%YilT7f} zvdTSHbRWTR7A^uq?9>Exc}XTMZqxQJ7fcp$m5SB4j`j%{l|9T7v$};?~^x16amoue?t`!`6kn@`_gDp z)`<|%fVf}=Bbq?*BSu##qg-!3@#y;LK4|GzU^i7Yak71<47|zqygT`kRcbqx>gt~P zCYynh4MGWmOYfj|*No>EwY%m5er4%VCTyll5b2C2N=e2<^Uyx?HIM`T2_HNo$Pm~}_10ULJ?3J)kzmn*N#?Of0Yrr#%Ts+Fi z#?BX&&ShD1=zm3`O_I1=TyYj&P2bH^K_pItf9@@6dJ_#}QFAme?tki~cVmnAM15zP z=08ZTBHQ>V|Fi|tn}!-??(I^9L9*{(07S?(!Y;j*E;Ng17RkhUfE28e0hue1iP$23 z}-@LRRLCRqUggBKqM^rSaJPT~6Gwa6H+Kv>X(eqn^$7)Y4aDHARDqg~a3z5d!9@pB=qG`c$xctPwOXvRdm{!+~yWF z*9^86FMPOAcWy3j*qI+{aoH`--Q@?0s2t?tmN+w22Qi{!-KUKdh9- zUw}xF32g;Dg8w&7k*G*g16dJa1j`FlthOSr@=%+g`{kzwz7jGm-W^EPl<0GNO~1U! zGhbt`f`J`a%0R#t_A!5(h+`A~Twg!oZ_mI|KR=W07e3`Dqx96<+n5f^B&kje$jeGl ze(cz0fpLPz~y{VvI4vRA?&x$GfEu(k&cmSY~dU!C{V1H`6UEhHuc{ zQ;`wJos*Y$5hj<3SX;(n%YusIi>zBYmLtTH0#p8HaASg$kJ0s$N2IXAe9RLT$KmpLwf0ox-w!AU?8s!)3kNAluYL4SAFS&`ii_Oz0&s@FM&{t(Bf#uzn zT1t(z)=E&iIdq87kp*m^eNb zu(UQQE6g%;DV-r+2@R3~pQKXN!~Q1RLgW@+V2r+yO-YrZq_4Ks8%&1GpZAeP=J&!P z?v4=cc?0b`GGgo5P*PTgW{$xx^f|Fu1g}Y(eiJcQ8q7bV_X^V_lt1JtuvGrGD@g*?EIN-8n7r+q0A_5r_(djka2}1v0Eq55iAuC<=M*H55&J+!5q|Gs zX|T`1DK&R;>rDf*l!i+`$$348SIQNGBMKT6`}_gT=MM4_QJ`YSQ{`6R`l(v9qq8s4 zL}ZJjJk5*DmdRI`-x#{WYB+f=lAlR(g7FMSDANrg_=jGGh@z%5IYi*id$soStA&5C zRQYsHvj4q$uAo8{=FgEn6-reUU+cs~nQ5x>#~LV_LhB;A;B~@dOpf1)P4V^xsR2$cU5b$-Sh}F9>VvulsIFdwy23FlKg>b_++*x4M|i=F#7Y{9#Y1BU}i=_@zn;p zLZL;R2;d5tSll;@fL={Ap}`Qu;;4Pd{b&lOX5hOiNl zp8NxvJkL_mT=z5 zFjf6@6GQc{vBCoR>mw;P4pjxSVpC~SZR7S`oT!$_*z>>Bj-wm2z|C_ znL;j4qEN{@OeMpZ6ucghaoE@s_)VJyKCSAkG%dd(4e0&`7$djn|5Wm+9Oz37^oR`f z5kPmWXE!HQZ4NZJgQbp{>?awq_I?K8TOUhOXQ7IML@-395#M+5SNLDH0FuKf5&4q5 zjcQ6Sd8>$C59%m5TypY+gAp!^$kAlMD8ni6Kj0-|i^x*`b!DF1N=n)v@aO%{|9`uG zL{I!WeedUP-$5E#%UnV-_DNQ9N8sgV9MiMx59*)Z{!g(~hF|UA=7etdk#szX*J~Gi zH-8)B67%GsCJ2%_Pd8#zZ|qERp6)^UUg!Lwlu4i}7(>H1CwuFiMh>S$drOD`F3wJaB2<5Of8_V0Ec zLXjIQ=-W$6>g>(oL!sW5hqS6U;KlB#0q%u8gd#Y46B(VJNRf{<=PtTEl0x@cM1{p2 zBnsJu{2!SND#;*A%&Nbr+mD=*vb{)sG4tapGu&s**(4fM+`khdvFgb<+Ts)5mkUMk z2`?mP_ffVRxWy%?$JzX#m}Bv4d77`eC&fX>_zNb2t+(g*$qU5m2AKsWgmG8=n&wIm zqWFr-9%mXpq`sp~eQow8s+)0;sn*F^i@cQWPt-5gJ*66|a%3nJ50;9OTcMgE4t%;* z$Ykur=fH&#|E9-`ia4bwYFMyTl;Ed%v=$ROddYt)-wq#1vB|$Go%f|!vDeCmlClP( z?W;UdX-fl@FY0EqHH&LPhyqUsST(^C96!Glj}!3(i;62D(sd03-hE^Q&uqyj_>Jtz z51$^}5gwPkAE`GVdOQd{yzoj@!bo)lu(Xy`4=Thm;GEmw-W}0#)E?eXcm2ec-X$*_ zIp-Oim^lYPFkd`+%sBv-ih2%UBEJHKy;#oyT*GfE@6-4#qucZxKyrZOJ0CjWcOP)AVdLJR7xJ9K;X`inkZs>RZ(7&)hR3wUE}BGyQ7Dr z%E&>F%z8>k4Q(sIS5HUH6Ax%_p50|Ma?5c07m%D$Q`Soc3rn``)L2K&Ryd8CJ!LZ3 zj|_e?YChbvhXaPFN}2LO_+qw}xB;_|H%^zM2{rOp(=!ZL58$_$=~DXHp}XaHym`Sc&pIU5a{3O!agF7_yMgGw&?o^o42cyy+8Ah0+n#U9&YW8X$)w{r*a0=bM z7vzIm&N3A@oPIYRdlj443wf zpN8A;z#i@FBew^S(5_W0WP*nQ)LuaE~Y$MXL; z{{Nz&J^0JK!JOIL(jFXw+IvuYu$-y76HnyB-M!z?CCb@@`qjpR2Z@jQVfdKye0Y0s zSg-cra9?|H#LV{KuL~yIV^3`l2KJ&G&K|VCKn@UZ^t@i}Rr$X5svbSss|o;WC~U9l zxmT!iI%p@~XfGo2H@oo;m{?71tsjfO*<$@eR9uKq_Cael>_3qzdC={yxM{Y_y= z&Jv#LsHDtVqHa!Ek3?@zHkjP@GPw=R%Iy;_S~s~JL~hWRuF{)^4&I=c`y0&r?$dgF z#@=0;HJ<Z@asEBtJWj%oOoLS7#$>>M_=trN9AKl8hdziJqPdV zOPa_2l71uUNd6zieEB^fM^^z-U&f!{G5i^S90xO+gG1<){3&}a+n2smKa9xt1bz;d z+H0)H-V_|!g6~5S_H>b z<9)k~_qJUKhovll&3UC|JjwmK>mKyZN`rGDOJKQk>mNS?BlK*Ju7=gC?Z8;zpA%gY2Xlh7c89eH$7lx<$cM-X)KKqcURQc zkmQM9&~4_=6ddM5jq-HWoyeT$Z+%N5uWq|tXl&S|~K&4NudYJh3fSx+)RI8vvC zm1PKoJ&cB7^eff7j8`m_d05UPF*lTA>@Kp`)H`)~EXV75b`nAY|NkwWb%S4x7nau! z-o{w~v8&FSfo$g)ZPi{EX)7Az99&Y_HpV`9pKHHLUM#kq_}Efalahy%J9mB{}R z`%YFbt88`So$ySI71eTCRV8nfzy7;WbJH9Xiz*jPF?mhxmX}*YHbRbbhC;fN z$OJlEYhcB$lvW=PlhW>{#dY=-6=~Hz`5ep=aEk0PMZ`tU`;pfFn7oT`I*TP;c$?f} z_h>72tGTd?S4}GtJIQwifa(dKe22cn2(+FboivjD8A9pxT<(1UYv}W?^9AEK)88q7 z^Iur*#Qj&y5{hjk=CFIziP)fj5^%Uo;MA;SMOQM^mq9!R4nc>9#v!4(i}?wQ;qJTl zRIGzsQS1zT<9{7WPwi8zd_K7QL$sT{>0_@(>7LWGpZzmq!!YCx#9 zzr=xnBaI0(36`(HJQ$A%Sp*1XBY=4@GQ9-#Lj2;1&fo-P52BVn!AWuxKeC@7?0~(f zmDgocB!9*^6%~yZoA+Sa(C(Ychphc=GD-egyJ7%ck?za20#fupjXQQ_kdx5 zZyy7WN-(yzu!|5d%bk9L;hRlXR5$h;s7FNPPj>-^Dr+WjAyE%>BB%HzzNh@R?J@FF z43CD?PVuvn!gbw^HxRh^QC^_%AMew^TnXO-$&P;s-)!&6-7UT>@#43yCM0tCIgF&^ zdr*aZ^$NON88exBJ2`x*J~qhv3AE&uLPU z^rES>QU#=Y!hiQiOA$SXXpS;HvyD=ji^|J^gz)d&+~xE!W?5TZ!(wx4Kij$I}Ggcxv&!q z?De^@w;9;{Tv-3l0?k{%SAc) z=S#U?QQkEu_vWI^?W+v)dbd(0Dar(ca(OPwuT3e5ZYX7n@=s6*nYrl^`5CeOamn5H zf}e?CX8R(fO8VB!)cX3$o#9@!PEBdY$MeOMl=8oNx6v@}k?Dn781TVu$t(HWo37x+ zi-q3E-FF`%btfut@kv*3Y79{adk`&7cIbV_^2z;b8}h}!?JjWwjxEx3O!c3q{D)9L z`C5_mN25ie1u+p3_C*#}JGeJA`hybK_v`=4`Ld*>r|oC7B|1Z z;a_Sc#VC?*(yi$3KAs>)bj&@;6sjY0Ypn%NOgXLU5Ho9-!(c@_72#Isb|*3pIroed8_tG zoxPJjL0w*>7}zL1RV5}s_wv8megP(AY8*lKq6i$1rX0Y1DG*8R)!0JLOudm#%bGKT zn#=4vr;!J}qHiG$&THFJ*!%VBc;IQfc!Q|okJjfgYWWzD*Qd`dvY4OCP|N(qFwGRIEdNBEq`(3|VDJ=tQD+6$CZ9svr*6%BhNchjlWyzU6Q!-F zm?{5<3#F~cNlwXSAn=vb4oWm=RcCPJCyg6dT+~p5f4|~?!N$%CdNEj8S>OJ+$pE9TE{-0ycN6CooCqQgR+8r{k;ql*J!Yz&<9IPv++mcdjOWgtG>(i~E^Ax1q;P>d3I9wC^ zNiA+L_{ICu@Ra|Dd7c)>eGE5!L-P3~Blx#FlKMeb>RpmL!lb^fsVlNlH%RJXCbdOV zAIM5=mehQcI$g_+WTpNnsbc%5+`}~W(yY`cBvo8sNDXM}sI1hZ@JmfTVp5OL)WKP) zZwan#Qhl1*CoA<3!M(zyex`N)GTudv6C}0Xq^{M}*RoPaN$M|6>aKZ0t7o!O&;O3p zeN1Xxaqq}V{k7nJhh|EPuGZAXtkkn4ReY*Q?WsARo0WQ*q%JY3voy6bEA?qfz1yU& zi%YEz%1WIesW*}e_y74C<^C&e<^G|lO1a#BKG*CSrau$!cBIpDdE|VL8&zzE#s-k#w<=Vm@&@KO+4jD8*cE)c&5PQX46X z%oYKhTd8)zc#8Uv<7Le#3BQ%u!WlZ*L6z;#S%A!b+5f@cf%xU6A$#Gw)S}vW0oFPk zFtdZ5{BppmN2o2X0hiMl- z=P@Uy8pcTuH(-zoadO6kr|DxvI1ptE8p-~qr>Bn^Zae@*m2&Uhituvk`*T8QvlKGv zS^Y6Z%C5fDmiyl7;?*Y;__1&#H&08=i3C?zCZ#?HmdTF-tqIy8i90CFET6QHleLhT zw8D8o^0%iQr?F#-XmpNcb3P}x1pxACRPj)OVsXbDCx3(Mbz`6Ff;o1&YxmUUSoizO zp>1@zY^v7gzex24DNzot2;^jEwwQvP@qJSLiKh8*X@%t8RK51zi= zV|w?fEesl_N6s5l3+hL#p(-su=F%ioOpmX=_#arbKW%HNyY7 z9c0Yrm$m}ASx$=Vq;`p5RVk^gur}+VzLbA83@5#`n#CmXEGH5#BRElD0yg~U`$|@< zvgwAubIL#81C{_Pq4@M7v+x(Mm@+V^Q&zN$3k+;bHpi&HR+eZP<&0V416Jf@Ot3gmUSO%5yVb;(T(Z-Xwrmr_%tDY7pc28p zQaN^=gy9mwe)2~2rheKL0O2X(e;SeQ`D4(|X=H`|Udw%$eFHPUPk}HM-kx3xMQ#Uj z**<(hV@df>qAOtQTlq-ZdYx;jv&Y*q>fQ5+Vxqf91IX10Zim`2hpw%S*UQQ9DWJNq z9VGd+xqrcvLP_!>hlRC_Hg^?iLIVk;8!v3CbrvL|lEi|4lnB2+laA}wdDuh<#pD(q zEIqcx{ZT%1xUM(+lYO+C{U+A9DgT?FNw)3Dq*Nu+*=s3AYDhL><7B>DquDS1G*r3v zyN4Sek%rUL(knxNQ4i;)oD+t0o}MtIN1(|GvtiG4NBje>qv}+@zJE$?T#!e$;OI^x zlnzn0+|FOBtt~i>n%BoZwxTsuEjh%DouR*%VIY#K_=d0&dlF+uyRge6cH0NCs|2IG z^C_eryIuAcN>P=#r@-BQdH2D0&n;%~C1(JVk@t+#wE}9&`p}fMlX;|DSy9SLPNjy1 zxlNFqSztR|*mqs0HC_5s>>9!T4NXJ7Xrn$cpz{FLY0n)b5X6H_*Cb4BVX?U8B`hWs zbN9Rt)Qcjh()O*a>Tu~aDO9QRvP?FwT&vj}_0uZ-OR|#fF%S}62=Cg8Ad|KkFzREX zh0hd>QDAs&m}%M|>OxnaTp&PlnK#*9BiZH%z`bde!S?+NG@XESMmQ2QBLH_8HRHse z;J(+K!JR6&QYXbt;uWTnSFdK$Rd?5ZxWwNrZ|%CDQ{FXLt{0!|=ia-+|8L&sd;iV~ zMZRFNe~Im;2gYKd?JJ^MM+b60JVhhlx&P=dO(|{?fDRRy#W(RRv?_JqlMitmy_jP0 zEG9mgkkI{?;$Z#d;`5UhIKzak&v;@wq+ z?Zm%OUXh`Ms1n>R`V+oXa~QgxRKV#8DG2yEIJPNlX-^Tysb71fBfoJ6s^YCu4>CCa z!sI19YCO+P9X;$-@w12+HT-Q_u)gt|j+I&YJH7!QsX*-c9RcU6ut)XeU3jA-DoqHS zJ=S>WR&kxyVN%PM6CV7}@pm7~Q`$Tos$3O5AheT+bcYlRL_}|O9Ur)Wc&H&91DPT| zn2F$bE|JGuc(fDVFUQK)@h(t9?A0m%mjd^zOL+M<)It;Z$9O9LEL8qZ$lenw|0*=F zJyiK&n2y^P+KC1-)H$3IZQla<$tpNAzFS@%U%FxPn-FICue^$Ptm&ff*mQi@YeM#` zknp&zBJJ;&Iyr|N04ZeRjLXFfEJ$ya&oTwKS<$~jB4)$QLWK&RnH}CmRKIJE{|zC@ zH3EQrh%Hh@c$0gZHDlj$N)f=JBX~&o?m+(bF3f99_~JYX@oCZRJi;hX43sxQ)H=SW z%_BixkCJTS#VgPYQ~uxZ!u@kin4u*TCdQQiNWQrtzvLh)ov)s9s1mH^+e&TJ5~Um} z+!fhX5GJa9ct73IP!7!Sw|jmcv^1@fa%P$zeb+6-WLeQ8+%qAbKG=?X;Lo@#KU|do zKL0}P|3e1L(j`9haQPwb;eSGMPPR2nu=8|mwJ)=A+$5Irj-}puy}UI&lFWc2QYN`} z^`E?(6!TZ>R}o_9j}s}vE<6sz#Eik|W6)(r53}_enK%E zMBSSdC^V563xs2G>q&4s`7^(pe3Wpj-Ut~NnsoeapOAr+`*xk3AQZ;D@1!#w-*mpS zNk!02f=z@fU%Iwm9Roke|2pCeSH5J;dRmCcdBI3)|H{uB5n3DFZIE8s4fO_2q|#Sj zMJV}C3UE!RD>!~IdDh}o7f1w2q<%w+(LZNkt9JJ}%-GMmGNt9#m^5>k5ir20GAECE1W8zUDfN_pnVs*Of(l zkC2YzP$x>Ih}g)Ba?2V+J}^FM?@L?1Or9cx*Z<^n<O=VyifrEI>i#l*B6L4P{C)Wu{9?lQhEP~wV4YHi$xFP8kQt0P z@9Z_>cK-I6aa6T)kj7w;1BKPjS%q>Je5^uW&M4w8_{M|a>AnOQk~L`TFcO?I3R!^0 z`pM&2Md}USj{zfKj0P)m5>%>ljtna|UbVhuC9UUZ%)vA9j47BM!

=YDo*~42Mk7eYG(m=YJD#-2#+VgsC zx$#BE+nVAb!Ipx2X-6F06O?P;*NdPCXxn(XwRoR8`|DbJL+#9ULb&LLS}U|6GsPdOu~Zxg;D^5~Pa*c&{SZ&=C*$a7!co1!8T&r9~w zw0Fc#poyvVOm8CC)AQws1)6sYh*L+7fGH{HA<6d+9vg2aPvI$dx|b)`f^e9%l?w3i zvznONkjb+uZv@jsYxvR;?B}&MR)H>baetku5=yC5DSW*qNOh7|(uo=V7{RKyHJlj1 zvadCKXl9;RrSjU;>bZ|g zo2)1X`IP;wj`vzzIWd1y1?(5ouCEp( zjvQ5L&buh9T63acD7#t_I4VzBHhjX=DrMF1U}e+B>NJb~qA%4^7A-X_8XoMirz(N; zPU-oOr<#m}AFQY&c`8qQh?F_`Lv2kM9Z{yD()0E5k0xO9JbsSx=<##-NyE#DG@m>p z^Mn>I)+yOzY00WcTSN{BfcSJzSD=RK8gN>pGV`~ zFiW^MQVYiVMpiNBa{z5qHAvxIbK{Oh1rK}kvC4lr2LPN ztb<=h(kf+{j(bh{%CC;^1z_!$DBAMi()t3~EhR1G-xQWc`{qifu)qMPr1Fi%J{@N` z`&7Oc9*mmFG$-fn2uI4*#ELSctJsYEBz}KM$ZjZcpFki1d4WRq1hRurn{uaS8_T_; z_}cM)W;}^j5S;}ft}R6uZ`|AQ6$2m|#C?415);r1f0GYP60$jubt!M~ZsU8bhu8B= z4a56{obyWDW26GHO$-Sx<%t)+A&Cj!qx{IfgzsVRDdk^t9ksjL(97}N&UXl~zZRSD z-OQ_Wj~Rok=ZbBI6Pl(m&Jeb?yyMLBoWdojmjU{(X9|TxO*^v$FoT;ohkE2EXG~p-Ps1Z}15vPZ;^?e2FLDlO_)4Zh%m{ zuU!|fTT@o;RQ0W`BnnsC)S`kA>h-#7`$#O3y2>?;ACsk)d$-7Ie7>h1 z9CG~InTS~GO`drQ)fpiAlgJUciH})t^F#LQoHx?bpYMexokrVMN@$T#{DL0T?X;dy zZY8mQ#q=18-?XZ%qc`HXEL8bJcyU@C6NTCBN8zyJR#uH!*|T0|zOQq9muhubA+F<~ zO$Ajds)GY%qNbJZBaCYb`l5DH6}ODNUN^X{Hoq00|AwCYsp^L&60gqdAAVWxJ&gCe z9U`qS^Ymk(Rb3@cZY!@Xk{P1%^=l8#&^$@_g~p7|Y;oWQ>O*>~SAN*+JY%seym%rp1- zv#ikml6+9tH$G1Nr_vTW965j(qH;z0DOKVfBK_d{S$T5uV95DHw$xbVsZe^L?|-?K#!IYg zyy}jrsZ0|_fiE6fDaC2V1tRTWg~#c6lKi9TGPBF>|1FFlb#ji9T}zzVMLj4@GV<~Z zOHgLnmeJf%bKbvBym;trjuW|*E8m$XK|biC_O=5^2RJcIRwe?OrvjUFWMPQHZGlZ|tC+;md+3PnV%Q9iZ~`b=1A@XMbhO0bQP2 zT(4zM{M|pIFsSs=XEl(XId?Q+nv|V};S2KdWz3#F_Unc_n#x*TKi0)hwI@IQm1DX; ze1)&+VtHX1D@b!wr#9X2hBVzYT{KlmO1f_TP1F1rn_#(az0>=!Y~^frxn`^<-0=HD zPzTDFn%JY1(Q4I^lTO7Eb1cW<`@Eg!Rnt>ja{2GJlW%MEP)}OROJBc?qhop6{G5=R zmLRRq4WU-^r-ktCW&X5~{;CiP)D16D+*nD``cm)pyxi!4wfNmvv@vwLcCY` znjD%wB<(LD`wC@$813qLHFOM(UJl0u@yJQ-19Dj+gav;OF=6|yT3%3+uZG~+*k_KM zP1bK5x`v{>qxhRQq3@&;o<%rMpMXIpyauIL9RA%ZGuEAHz+2AQRmcO9oyX`HnBR5- zh4pWTXg2k`JF&8LCoJCRh3e_P>|JL@$#^M@hh7H9(kC zoDIw4pK4X@>;49mgM~N0k~u@QzrA(0m9^1b&AQ{CYB^5a{7Ux!wz^(9{;A{9`qkYw zXBMg~n9nlnC-Gm-{AI_3{SRQLmhLAQ1H#cW^U$d%Bs8aZnk0||aQSG$8+%|LeuL!V zvOwra#c8Mygl8~*8<|Ju-!lFQ<5w9!!+0;_2N>VZ_*%vr7+=ZwGRCVIFJOEc;~9+K zj&b~qf5P}x#?LU`%lHAtw==$$@dn0MGQN!QD#i;KpT>9wW3*%2P{xsu<7(c@JF~<8C zzsUGi#yY;KZ9tqnW{~PG3KJfIrd~O=lvh`dBcXj--!~;Ap%zAvOn7@o2nH zL{h0lN`xal**=ktZ;U54$3;tXT~|k4put<$wHjevm5B~S(wX2u@*3l+On)j83^zAi zWAp|?(O5JyXv89$A~EBt-fTRSi6-JkC>V=fV_XD3>0n>v5-c&QU)6u{PX~Ne#nSMi zis}_%h*wd)a?3Raoo7w=tTHOnut{HIh&+owVLfN#o_CIn?SALTO~9K0@kk_WWD-U+ z9zq(^5hNsuG-d`xCXp}(g7HBkl!*66`?9GZB~s8ECw*;v?!Co)DVl1W9O zWg`d;11T{OS~`@9CNnYv)0tFakRvcEpb)cKN8>0O@nFnINBe+c$aZ6MDw>HP3!^cs z`WND(%+_p)WF*cZTO`SrO~uo2(D~dT6KV7Z}n=vx|5uFsML@^@K@kl6xu;8~hm?E?}Vo;G)G1nr) z;-N?^CUeK=O@Jki+^p)2Mf>^@sE)ipn2yiOK#K#(ScC$kC`nF|#1^$mfyfD$eIq;K z5FUThq5eoX3q=|z{N&w?h(tibL;dzpksywX73Pl&BsRgf>8&DZ^rjL6(vu~A3{@Nv zhJslXO;wPzj^RP6S%%oldE65WZKU!H#i4A(46cwume-!aOeD>jhq$AtwwYASl;Kj8 zKIKc5k%fkAC@7bmWe^ssG;*aN4q1@UJVbI0MlhC1M=}}GGx#F$a54dAqhgCd@r?ur zP>ixhBq>W1qf{g-^96lXFdL&>Lvh}c5mZMh?{e)`RW~+OWEbiG6{@CEO+uBSdO`x^ zdOV7g%BXZ=Ai_;cKFBI&X~_#IPjx20nSNwBC%B_a zD&JUau!YH7-`?tL@lu)=Ea+;xysdq0+kyo`jNpi>fqlUD;lEx7^cdn0APMLO_y9G4 zYJdSK2MEC7=iWIo2`EQC2*6?3O#&tWOCzyBIE9WlW%n139NpdFF`!yeyZ_!)Bog3eP)BWdN2{I)6=GnyQxP<++%OgL zA3`&g3iP81cDUvnI6Ml?Y{>)g7T~5k*M}KDB1lIpKbnu-L$P3VAm7#0FU9BRN^<=7 zP30a=1Z3}*!*AMg{IUTi9t;hm@Il(3PCQQ?(p`;}3Nmnb*?20_dlY?>yaT~4foM7r zz&LUvjA;x4&Gc$_ha1Vq;gdTJ5d%C#Bq#Z^xvS14KtluV%IQl7QH&8?0Rh9&bO-~E zR3uD}=>YmI^u(e+lS!^xyjX?4NKO(|n6$n$NBm{M{FIvauDxF2$((tpmLQGMuI#5V zRHhD>$EX-=U@Tb?UW}fk^rNCmZbiU}QeT(LaI|q|ULT)`rkkmks0-!V^vMdlITl+_ofgqN!Qh_KnX1Y!~`EyM+|LJr9 ztv$Dq0aJm4M-9v7pFA%ORAUU0iNw=b6R>+!i4(dG{MbVWnKA4sB6 zcg8_JWPfG#j_6`hf&)E+0a=0_{fVkPIZ-M(bv!~Sv)PKV*-`HtDM|%5%Mb$@bi}f8 zb~xu5Z0S>@Aoi6bmg&#Nk0OTklc^Zlhix7$ZF1_}KmrrNL_8WYFhU4zlr!6S;$l^o z$%9%&FsH)0jWL^-V0thP&vLCnJEHo*T?La&U|FL#oHhm$;b?D^)-+JDY4nD4gTQIuyYuSuYIHdIU-tFIoh2HpzmGbr@PY#xuY^b0osZkmWPm2@r2RkuS+k)QlG&woduN8znifizTA8B8-)Qf+ z(BZK+n!-AfmOL1vK4s9rNGgf}pTJPda+IY|a&;@Lk6Re&076~1m9ZE|Z;>Psh<*L=~pTT8>5 zaSB}6zgjFtBc;=;LNuE(D=;)Ap)5*HL@Uj5k`$*Wo$VQb#&prKnAlye2jsh&`c~@! z1sJf-*pUsOLQdweB$e)Z+3ElLd0i3q>foPCi^2?QLs0>TuiKO0Me4f`S(^hd6Z_K7-(liEnZA%vJ*C0QE`rXUem zuu0UHN+dF3bwmY@A;N|vQW(~;8EMLv$Ura{PbDHrB(>d^sJ=*lB-8I{5|VsYLJJofas>5p+`Fc~EO=|DMR=G+OOwMEIyU z@86AG1e6UqU(?%cRKDR8-BNEhy?>7^F1k#ESC$d1mS8)COSo_U9_*_1)8CJvL}56Q zN@O<$d$50nqL$56?cYn$g!k{kXqUF6_U}O{kL}+>S#4*xN;-Hq>>n`_p-?snp>2g; zcFbheuzybv)F8{AnMw@2Xhf!dC=b|YC3WxLjbTKv2TdsiP)RbyLNvTZ^vj{oX0baZ zH~r>|R>+sY7{HNa8E`v9;wl(N!Qcu3nGB3J$cE~KN*!6Iq5cpyaUdHta@0RYL~WK- zf|`NM5fj@F-Z1gP#FGbak>O8#{@~V$eG`vQJToz7Ogw>q&rf`1Vr=om69@0m24b9e zXyQqjpFB7;@f=*9HW0=b3}X||!t%z0Lozh*-8=F8!5d(4)5HtL#8=_|0=S+$c-z6d zC!RAZC!U*l(l~evLK-`GBOKusA<1x_kU31^QE(9BX`)C513}&h!%gxptPnVPtds(N z6%sr@@f1RSejzvs8xxO1#;=(^Vf!RfwU1&acf>UDMYumn!XrJ9f#kxUv5BX_2s<$` zf;cG7p@TQ5ggkfflLv3)WQvLVrF2h1Z!(@ID3ue>9{ePU@D!qg5)s}$WkLFet`6P` zhkat=VQG94DtsQkl~DU8o)pf^K#oX>zBVxidAA`f(g(@RIY3$TRRr;bQXxeFy-GDx zHaZl8Oy4*0We)H8iDz|(0a=iRl(K_&8ZwHHOW}~a#0-&SVPWAZHBwU~`Bz9&h?7!F z@lr9kfjCssp=VW0AU|AgMkWr)tfF(Vsyyw3j8vv5U5HHT$|{ap)ed~_?P`7VZx~;~ z*vEK?@nej~8Go1YFB$)i@mq{5?@-~^Fus=Yt&Hztyp8cb#)lZ6d#CchgmF9L9>!V5 zH!&Vze1P#AjQ@r4e=t7jE){My<8H?HG2Y8~KjR-U{uSf57_az*3dhIzUdG!Pk1>9Y zvG^qGgYj<0uP{Eu_`G4ocQNC2jK>&HFs{5?@x^1JHziUzt43B98=N1;rxgFWjL&C` zSxpu*aJ9y#C(ZEA<1)v%n5Ut1)MOzq3CO939+u$*LfD!R(Uw6d(HD=>i3s%RnJgxr z3G}p>>IgCO7w;UY1gvD-1iTK=4~XGf?Dc?h#uov%0ImjL|AST}0zKK-#sb4hE8$E@ zW-VaA9Jcdu2pZu!e@_08TC}&ZuwKv^(lLW$OCZNjG>zp25hG{az!tP5)p%U3Ed(%R z!9`3Up3rtU9z-WJnise0tdj##9ZXkT z_W5*zLap@>W2PSiF?D(+D5r~Zy62qYasY{VY!I_abfdk7e{I0;t!7@{Gc!>@!z&?MHE((;(8A?VQdf)k5yvLc^A4*uACe5uAUizuemyzyXui=C)c?6q$#5n~FUb^xwR?t=;bp z*n{bq%C|lKh^py0D$>4|j^A`P*S5&|TF|#8xAxc7*&e8G@z(kS^1R6uQQ{;Z%^^^? z2Z9;QpG|$h1_#w>=4DfHm2Q)$6zkTSvJqACJ%>X%EO)$>f2&H@`kE0Btyd%0=Y?zf zjuGN9!=oL3okPb6>*)Gt`5Ybju>+i1KKqf7|2N^tq9c!v96OYw=|2_8IU@3If;(D% z;)sOVDA5rWG(^m16`qwf<4i0FKO zmZ)i=wY?NtH>?%P-k1i=%#NicGZt=IEgx#nKygnUZYqL>nsi38shD`L;UidcoJ_&S!YU zW<3NoT_~VhY9{4Ur%f2Fl1B0@rOGV716g?_7)?8lR?!fM_I^nJ^;xXM#51)qxg(N^ zz)FpVxTwt4!IY+C)5I#!3?;I($ME(kgax^e04RDl#8qP^>TJRTk(xk6oys z%siB}idGltdV)SJP7*jdXy~GRf|u@KnEXmwA$T4^3gDjIRJW1A61+U(UqB+YODT5@ zaI6cnbmUc3UNA7DFwUhiPL0LJ$Y4(btKu|+8^A0qf>m}kU9y;2FVLTw5?ix7OK7^_ z0WsCh1H>sCE}@SdpCc}6>uPDa1a$;k^C8;Dq`eoTa$W^`j!kKUuwGY_JQ+C_#DKpy zi%}d7!y)hJvIwfBmG9QPkCF&IQGQz9MU=LQ1nLc;UQBSZDJ(iq)xKe(n8fK$gcP5};EZ<87H$}q@0rW(*8E6O_+U9P6nm6GfC#K*7 z$Vb{q>%j&Yx-;26Aw14^D?VAzC>ESTK(j-$Q`zcN>R5c*z5!!wou8I}=|_rb9!Wxu zq98`YJ`xf~sF1(NYl;J_7zhnLh#}AWRHo;v`XUU&uk4!}Rv9>@sAgSL=j$p%-VC7? zE3EoUngecbK+ftpw%KtTP@uk{#P@e>!oZJSF{5rD7qe*2M?cFKP10pqbadL#DD~T- zKN^-d+_ciHtP%NEwFT_fns(q{osEWb&6X!-uzWaj$n@v1wR}6QIgCae=XThuK=Q0P zlstP&l-6K8i}sPKSgJ$TUsIlZCrhY&H!DbADiKDd%?Zt6YX#)6w!-L$q|lwV$@^>F_=NDa%;OzR>ZW@N4`DBn(ttR)X1%!EKy)&v*nX5 ztaLkkpfWmrSQeHKU;khlOO~+)>wuz+4!rqJmZtLEtRQ9TRrNLtgU!wg#AazFx?Q&P zcJD~J-O@_F-IfE8_@+ua4B_jWdEa=^cU~w{%TBufDDI^+h z(8Wz&so_pT^)+caoRE&9)1p;S9Lwi{BSnIr8V=Z{rEV5IBKFnO7FWTgHJ&5Sx2stt!RMoAa4!|_0CoP@qkhY6L*Xz z$q$ycZTuvVFM;cIgLcaVPA)iYo6Yfu=0ibE4K~Pgqs_SZOmkY&I>#zq&4i#9&@?IS zaJB2gj{&sPoK}-GQUM2vK#q}qaO9_lEc4T|mhS1w7^xFgYq=O!_87F##yzn$&oO!I zEHoIQF&~Bt@*upRC2og>PSs*FHpi@3&i?ci(>~OaUAG=`>!Iw_;|q-HC@8hKf!UY$*-q&bi5MvlV{qv*q{eoX3fL#5jxL=qk2@2r8~xI)|8yQDp1Gb z&s{KTZjdozAA=eX1cCvb?S8wVk8NUcn$7_03$wH>l+$=PQsGOaGoA980KIsm(wH~W z6TI?`Nq#S#UZZ(J0?X-i8ZDLxhA)-rS&LC+ zVpY|onqbRPWS5g#9IgU%|G>a4G}8lRW*p0K73-|bR{Moit=INbwrV=4lPf0nMJwii~4$i;t4N5yd!kYd%!LflqKLRsTe}Ko3%+(^z({q*YG%4bMj-rW*}Wk;e30hG+@Hg}x#! z?e*d`X8mz$0fV%*LB%hP{Q$ZLinRtht&qm6Af}8)B^~2K!$u1RxMvXAjFSmy>(zT2 zxB-(1Eh0Ivl!wiKeR5x}IZ+QM_t?#KP#Rv6Dw0_HL%`0kxR_m<9~#!_tP>ybr3)lg zI<%Z}nd_>Gb=P2DRxUZ>S~lMOunKN2AFXv^kc__GQWff{EHLt^4DulF=+d}@R@f2P zl;6ku0TvK-xt^*&Sp_lm zd_%41>in~Z3Mr&iR%+#{8iYXJ=Mv)vz@ z(x+UC%k@5We=}t`ys}4ShXlweFUOSM-V>P#c=z(>dRGZhrEN-)wX8UgLJ!e!uGrOz ztg7s(w`Z1|d*f)Eyf-Rm1&(@jtnyR2W~u6JZAFF)5psO$a?b2}08E$AkX^cveh?ZqpnDm5{i}tQF@Z$m|Ry?;3+MA zbBv}1w8otlPIv6+vEp>PXjcPoD4}aGIb}Kx|9xn-urSk0b zYiXT1&+#;L2I||}8k<+^hh$*U(dln)vs+LeS^@aI^hS=&!q>FEqq)Ae1%11Dro~RP z`10T-l%zJ3rq**mZb@?s$7P6io1iG@3}af=h*HC?YY~+Yo?PqwN5@=SPH}OWLXS#J zM>OSh!5*;?%R<_GRkw|_722CdbAMK@JIJ)C>^g~{BRJ9*d z4L&AG7ZdGMbz;ZW8e7bM8rf4S{c;IG#yFM!5T7iE?>ai-M$I~W)sZ9rfREu+Uw!0A zH(&^mgk34VRdR0kks}}d@R1{1uTf^Q`|pG|0!NN~4sa>rZ|fA7UMiL>p)F1t;ibgV z>Lni(OR5Pk4fvOem5Y{0TC4=BUP)FTl9X73!CH{WWn!I=FutN=wWoYs)!e368EdQG z+_5?tFvOKFcu}2PvAn7WTSBnv@R^ouB6s4|?RY2M+2YkyYP_*7C*Qk-EncFsHf2S9 zZ{I*)YS~h`%T(V=OOOGd9P|l?sn%&+tBv(|(=O~Vn4HqdWbBCc(5Z0E%0`o!%_e(; zy5-*7P%GM7yiWNnH`BXig%Dagnj0E10_7c<4myj9wL+Cdry~MzTCAm`BiUp_6pE;) zrz8<_y0)NYVOui*FIs3N7OlDJ5S+GV5KilYVem9PT__~&Rxmv6xEA%$N}LvrT^sOn zQ#4j9JHdCsrx}kGo|zIXcGIJCI@aDq3%%FF-U~XKX({Mx2HcKwUI-P>e_kFL)B!py z&43)Xq>X%is8>W&gT54I7OBkORO!s)W5!&4g$T=n7T7mH8g1;R8dbi|T)aJ2Bo_c!2l2qJ<6W1&k!qV2#mo}`mooB1H(+{#8{N5?uOFR7XvXE@&{#|!b$AX?+*70a_m)3s{G zX0_Wi4?u4y&rJkzCm350#LW$@W7A%4!=-TF5L3+%t&7sc*9wVy0LR%sYu3xIjsUGm zyDY5uWAUeHOe#+l@;N^(+(Ndd8^{=oU=~j2Cg^r@FojDuDkSQ6Fe$*Wa?0}ucxICx zd!!D0(6)S_{9{B>Sfxn1^AMMH#Ks&>^CCzj%-e;SoAH4i`+*!8k)=KD$w=d|Fj~}e zoZhkckk5%2_CRT;R9}=xi+{&=GTsFI3NWqjy~6?c`y${Tz_ozm0VJRmFL&SOfE%+O zSxj267MK=20)qiL0aM$O)wEWJfsuK3jID9Cb)bj#_^^E$-$=#mI$IoQlj1yEfs<7V z?Q&27RTmzd<94YrU2KK5yM$6;$y`nQLpXSXeH6aEf)r?^qz2-F^) zT!^Iij_9f!bLG41Ek)JP+THVSXi)j*88bg>nES+|iyh^kAfGo#KNwMmH*{Yi|kvqki@1j`Hz2l9u{*Zj0 zv%qs_a-Emj5G=mibfl-hSkA$-GPWjCrh|qeECJ~&n2ZK!MTe}EsYA?o*Xw3on%2qzNL4JlF+ye>qr;*Vu}}T`-a&Q0J(r`rM%h<09(kl&zO^*O*vHsl ze0Y~~A7?zwxSMe`W5IZ0r{W)BoMc?X*u?_~MWg9y0b!`eQ=sECY~5ne`Sc}9o`zqV;? zS=UtG+$1`iVZBUvJN@l#l3LSTD{*Z{Yo{dS$s$lXJLl){6CBay*=*$s=+g{Cm;Bw&AAd+! zKQZUXAOG!~FO4+aUNJQLkv&U(ymi*?|5UbrV)oXP#KrI?dGb@E0!Br&!Dzk zo*u(a)GGDG89s+=@XL`{4u}o}`yy3ob(aM9F4ja-^n{39YvQA4Y6_~~BE}mMdJ`1y zP4dt5hXpvg@TPsrO-^|!PCYek;LA-L=|eq6G9Af=X?ILLrGfPatk&R!B|i3{*S~Q{ zLVqXcX#TLcuCLpf{93L>^bTlHn}oPXWO3?eBLJTf!rx2aL?`cRG1pJavp^Y~4obkq zkf(y8A_m*AI7iIDKOfEtB}5qod=aN*w-Bz_ocQH{sxyvj^s~aC;!|}JKf83%p%8Jnqw9dPXDDj=JFh~kz+pmBd0vW z3!LF?<@eyVj^-Lp_uO~lSJ&6CGAjL%O-mLUby@7M(le&59qT)mQt_qZn)8hhE?TyT zR*mRq@-Ka#|F2p<@3lO<&wup#^1golYxVP9+n@h!`hS=DQLXy>fB(}OC>Np?AViVy z0pEd-nU;bc27cv4A^-lhN#Hdfgw8>C z1HZCDh%z^11O5lV9MF@%cYFvs2R#fteI;ZDT@HL0&;XjSuO2!FP58_Plq=8%@J2ue zbP~AFE5yx21Mh2u%%I1CZ(j{F=waXwG(n%BtAYCflf(}kX+}9A8u(g(@IaryuK`Ly zPXd3d4SE4R0sNVE$O(D`crTy<^ce7FALIl*1bjQ-YS6>LYp=jLY0%xk8vq&5N#IF8 zbPk&E@(v;H1ziJt0PrB_3Ei?_P(rfF1$<(|VM7(Bevj7eLtn zJp_CkU`{dkfj+WH-tQXu|V@LaYQ`4P4%Xw16i37@!mM81S2bFzCa;Z6TCx z&_3X20Yjk2fm^~T+hh;?ali=ZVc?emyFpI?zZpRt2Ynd$ExvRhOfy9#U@Pcq;5xv)pnbrfNFrZA4+GbH1Ze?HcoSe8^bqhf zfCHe%fmfx3_#yEC?@c3*K#u|cB?|zJ3o&95V9qqe1^i)v0lFLbTY!b2CxAb-8EFAM z0=#z%bPak8IDn_gyNMsT^*ZDWXdm#)fUTe>fa|Xp;(oFR9s%qCP55oV7-;dgLNo)O zB_7~CfCHe%fKU4<CVc+Kkr%`R{MuIJJ?Kf` zlW&LqK^wsTd?(yMi@Q)(KZ&{l+6TOM7xG0=qX1ndJn z4E#C3IOq}J-GBq2$ACZdAnG;f8sHYd&p`WtzXW)lcz~xpgn9wG9C$9^FQ5(JN`Pku zWB^_VCawXMW6|Hfe(x#?}!KZzU|06&?CT+9f%ur5_r{4 zA&sC39|k-Mn()9F^bR@+{M_T{D?yI~-|__V6!b9g4PQoCB^vmNuR#7X@Bkm!hr9!g z=eb4t8RQY@A>cEXz5#ZMV!=NXD%U?h{2Ac5P zapVQ@1IJ&4oS>7yf7%Z@L5r8rro93=L5~9$e@h5)9Q*=53YZIe4EWOTK%by%fLHto zIwTtSKYoI83|jmYsd>Imp@;O;}H z3!n)Xy@7lOT@L(dz+1!*e9!Npw^^Wp=l=n99CS7C?Qf#}0X+v0bg*kOKb&Q1ANjcF0li&0X+RYm-q_t15aD&5)(uNAH38h zeh+#Q_zO4g2DpjLpnbsq3a9}s zYF*+~Koe*KxC`I|-3|OCU>)dj;GY4)peKQ!s&k2cvIqWJy-RE%8u(4XR?vrm*EhJt zFz9aJ5a2=3N#G1%1oRN_&43-Chk^eIup6}SxF8;2#052R#Y=u`ZVw0zCx$3gAxS0X}t&OWX_E0Pa`|-Gc50 zK6{-@jFCNX1z;R>%~dXO8Q>+*{}n$M#!2UxD2Dbjo@P%kp6x%*J)?Sh zcWH9kc=3dLQp%>{>XGTQ)5M=Dz^~*VwWrWEcg8Jq-Q_oyRnP36k(@q0ZK8P6eHi*8 z8J{?c%#<(woV+V!r}DGM%+K7k+x7LI@t+%Bu34pTG%tNq=`^>T5Z}@Qy38%7+TZCj zZ#mt4qU%(V8zaiQJ&#Dv+&up00`YKovkQecRoW=*lr8VzxiSH$Uw;#U?Yy~q z&Nb)y)wEY0>bG4lh5C|0ex}lo zU0%gwwL6sVdkWOAsq&w~((S&T*6CLM3a9Z{ecDuIF*jXy-Pmcno~EL6!*nyMYOr^`+k%6Fx=p1g83RbCve?JSfA70&1s;lEe=8}q`+ ztwXtHm1p_&TI=xLV!Ix5{ZO3teka%cy_)Ui!cOO=Z7SW`Wwq0}a@xcGpFnFp*=3#p+a>v?5(s(hR(Ua~LL zE>QkXHAW$w>OM&8xlmdQ=}pPklP5Q~1!or;%Su8s=jZ!XVN`mvW2mgU4kvMB%g zZ3p`~rI4Sax#i}oUAF~fDj0rlUXdPh$Nq)d({c~Z!9@QaOK5nrj1^SIa`!&Zpyex7Z%ebdQ+sI+IF9w~UW;sdakXG;y5k zGGS>A@shme$PQ)-i}MWR`@jE$1}3g~b`5#kv8zbx6U*bYye=w7u%0zqB-ZW3TGQXV zgaN1qlmo^;gSERVtX~1j4XpVA4&PTKwuWGTI@Y;=1m2Hh-{g}*?ydO99`1(#e*wHj zyznyw7=at@<8)Fu3x(Y4r2S*s2ctbr+P9{CY1-qaeKOi-roCg@U!?s;+Eb=|S=zs) zy;Ry$r#(8_x1~K-+OMWPQ`(oMJz?6nrLzUJCrtalv|mp9v2;#=&J!5mF$}~HGws{c zK0fV7(zyfL2c)wIwC7KI{j^U^d%U!7OMAeyk4<}#vsE}FzwUR9;V)Bq`hC-!=*i4+MA_) zRoaWC^98i8O8Zzo=yWoIJPNzS{h;p!7~jWQF~XrU7+bG*$@2xYw?%t(w0B2)d9+tI zc>`n^f*E|Yhc*{}X|J8mYtTO0cq81Q3)-`zebC8nq!Y5xUL);K(!M0^q0;^;oui<0 z6|~<-`;WB0NPCI2he-R5w8u#M`?POIdv3I+MtiYz&f@Snh$jf%`{Dj~C@XsqH`0?t zx%o26><I)qo~I7_bR&58w-cuL8agI1HGxw@54m z)Bpwm4*?zrd=u~{;KVN!i7G%npc`;2;9i|7~7~o@odjY!u-vk^4 z{2zdL5_JtgJyVfz3y&xkC1M)RR87Zu^O>Sd94BUp<3+icElv<8iaFvWak4lCP0gv| zG;uo4Tb(J+5@!oToFhIU&K2j03UR)eCo08!u>cLgLQy3aiN&}DkJod=GMvNupjd&2 zb5@EAaMt}ooW;5rXXq~#HKJD3iF(l>yrNO8#<{F!ahbRrC*WH}n`p<`tSfMSy+d^3 zR{a{BW?v`PXZ4ffBRDmm z#(SMvG}D`Lj%!d{i#zt$qhfzld`t|98^n#`CULX4McgVrF1Cu>#O>k^obkF#d_sIu z42!$PJ>pa1UU8rJwD^p;Uwl?PfDQ8p#Y5P3eprl%ZDLex7dymGzD`rMWKp$zd4^uv zl+RAa4oM-BBqJJrC3y4&a6>t`kByzHDfj z5xpa9`2TybkjkCa!IP@rHflRPjo8{AFrx$tc!M@uvO98xx zA}iVD=XGqQFAz+JqPUi(>M^mr+p@|R@U&Ow<#7(rVJYihj6POY&`*FmnyK8VFR^8Z zGhB8o6n+{_tggjoto)_zF#4@N+~Y@E6VeyvwcN}yC4+p@gPG;i0jX@#`Vg#+$%pQbvGPcS=W?6k@Y;80l$uU655c7@(;SmrEmm%!9f=jQltl?qJjd zBerfv`Jln9d@|kGgTD37y9l%G$bok0c%xx><;*FVr~$2 zCiK$j2+0vjMU(hOfbvT9hAGqh%fEwlr~O#J__}2`2|ME( zSVw}r{v9U1Z(3$;PdLf;*E7DI@dJ!^Gv3Ge+l*gl{Ab3cFRSnk#!DGDGQOH|it&w% z?`Qld%(Veuweg11g?M#&wMSjN^=NW&CNzV~oGe_%+6d82^Rwj8`}vjF&TR zW8A|y&iGcwI~YI8_$kKUW&BIVe_~wps*2|<#>*LB#`tQ+F~+wtevq-w!`*Ctit$T~ zzt8w}#(!Y^XU0X}Qt{7VJcqHtcoE}Oj2jvI7=M^?FXK4lEsTd4Z)JQhJS2AA8_!7oie@!{&_v?ew=lk_R>EVBS zeejBU`kYOy8T&Xviks4%U zHOepDn6E2~@48l-A7%8Z_l(8&^6i?#;s-Wc^$j~%irGc*--0o_S5BYAd1P+ICv;;G zN@^Qs7He_u&9YSzB7K*UUAs9`@$+{r$(97E!IO zsM&luH&>l4?v_Y!Q(gv%c6SRVGA-(ZZ%FC$Zu#7i51(|Qh)`gp7?G5CA4+>axMQl#W`RMA?STp-8Cl?PgURF1#Gu2*Y+QcEyOTbnBudD( zKA5BrCR6F5>CJIu*OEwV%qBH63Qr0Bt0Ew9Cs0|ih?6!wv&BV zTunE^-Yp?~`2~{{QI+8=lTsnlg<(qbt7enKEMWYY#FOq9NsB)Tu;V7NbLC8|@wBOsCR-JUi^+ zgd=8paSGR`w2jP6+{f~)RbNwV#rIgFN&P)V?C8I(UF_dk6z3POrB8Cm3~dvEKp3-S zEEr;*+5uBE(G#F|sc|=31h8Gur)E&tX$tgUttrlLB5uJQa}mH&MI0^8YoN&gWiC0x zf^rAMS6ym86eS1M1?rTL#tm2$h^wai;usj#U&n^^WqMir`L?788jsvH&s1-XwTx< zOCR(Mu+JMj_*7jeiPCl>Q8b$pHxZS_K8pC1Cl#c}$?x-^F_lq0?BNN&*x^ZYLUw!7 zY0P$Urs0boBuJ*`D@4WUMd+^*6(`GaqB7WfKq<*2rra~T;7db z&;RN7?Z$K7xy$E#-{!AE1Cu?n9CS0jlizEr&Ux4EuOhAg>l1;qeb51pnhiNs;lgPa zoWUw!kK>y-TY~%2hjF$EwEivhEC;!UdTRXj%CjcTICp}694ArQa3-Z)vOec|^Bq3L zDgLrx4(wbKU&;Y_aDqn7oY(^Bb~kZ#;Ot3CzQ)*x(9~;>^aa^oI-)0fB~LZZ$5i8F z4B;M-4CBGGamYCZ5pRz zDE=hmQ13>P|9W9?81yD(3Zc`xl?hM=PRS5IamR6@#(+<<&w#H7e&|)oE~Kgs7$5%z z*CyD}85=|TFr-w?+?icbBoNa#!`Pnq5u1e7n}|>fY7AE4gdyuHjwx?;6>)d)L^meY?hYP3)?9r0Eg7 zwZA91XK2sxo{>Fcd&c)n?3vtyv(kIZ_ZoYv_txz7?d{&1+&i>)c<;#GvAxKc3GDR% z%^j&8Svdk?QkjjBN^Jwn_kVxQ8d!+Lsqs~*N+!?y&Yq%GR{Rg))W6~%nWN^37k{9z zmK1*yD;SD@as|&Tajw76Pw{{FIg{V7_`h^!A#S{T1Z$kco`x57B*So0@&99CcIJQZ zc+Efb5yk)Wqo()e1)9Hmlj83yE*yc9r=wQ$Ph6+?pJnyt`cnKAcwvU+zgh7&(H)Bd zKgIv+gyx^*cl!Hx7GQ>z;-7<){3?7OzpMXBVRq(!2q)PUzfr5+>wb0$e#*uo;eAH) z=d!8zuX{nePjYxaMY~++r}*99)%<#$VS6EF*s1vU{ZRAgvZ?UWKho~W29+L~X%zY? z{slkP{KL%u%2CV5w|=MjyPH+`wMXUuHf{ze{f@ON{tda492QQc@8;>6KUZeue$kAn z+*Nv-W@>lCr{cTpsPbKKmgY}(Dt=6-3jS31;%v=7&io|>xpjFw`y9Q^MQ}a!PBSbePOi)I$5Qz6UNqR4$Q1J?H!g>Vf_wSe{>sK`|k>JO%bn~oL-GQxB2 zvru_a=`?Hz^cnIGK5Q55i>r??!ll@9!8*PuDw>w=$8ll9$>u4RjvmFW=xI)t(rFZ@ z{Jd3>N5$u4aFv>7DWj(pPj!jnfOlQJ*VozH-WKqC>)ZVe;(qsMrq4n(FERIb>J#CJ zaNj?D0hKn(x-k~)OAGgBrM<_p_v1sNsjzTAFdf~6D775)&Y$~p({D#me1Plkx4^tJg;@48OBCF}lJi5r2I_?9%` zGp52lRC1jZ*SA!eZ;NSjeP&OG%hdcz=v{?nyn>g!F44W8(_Rm8ds6g3*+t5co7*JVZ1{c zFCpV<81IzE8Zvgkc$YNRm3TSgPso@WN*Yqt!u?4pTN4aRgnL*Td@w8(?z^R79SqBa z`yOfNhGB(pe@YtqVfc`6-zyEt5`S=uaNj2lTT1*P7(OixLnZz&44;vPttI{*819#b z;Szs3i9#R^_rnE-2c%&HE>YqBoHXo405Ci#4Pzz#mBRgyr1zEhFA(m}OM1M-j}NcA zAC`s#Fd#J}(l7x7QnO7OUV{Ot8I^`f7?un7c4;^S!v}?Xhcp~6@kb%dPHA{+dM`>2 zuD7qjmR}-;4;jl--opKS$^GQuW(U3V?tVdf8}ZC&ptH%Q^|-X&?U_M4<8>))`Sy1v zWIQiQmod8weUn_eeOGvh+e83~zxXM-6-rgdLKlUFaaoze( zuPD9)LpV55#Vx)Q4^0YpgEHK;5DrBiPj4&{%m{ajZ%sQs`BeN_s@iC$xD}F3K~Yh$ zYIUe(ad)+}x2+ENI{l(#2{m6Tz!l3y$=9V(1>}C40-8y@!abLs6A&|-YTFuGyu$qn zm+7Y5f93iS0-7m9RyMD@D6E;b#;3ijv$+kPzgBb@b*7AxI19b=anyz!N6p1?<%m#H zVy3Tv$LEXYgWps7Bk&dnT9+(cSu4ujtBbFKZAnXFvv4;RzXUf?(iH9M7w+cbFT+$S zW-3;Bz-^m)emrFa#b4GH`F+HP-W~J51x^>(n z{moUzfZU^ZZ`2#O2;ovIe!hqzUIPa8SX$R~k_&B7MQopm2Y|iVW?~qa{=ZMks11^^4Lp zMkc7^OVTt>CZz8%X__DtBpH*YNiv}kdR&?g&wvT7?Gw_3_6J6^w_ldVa%n_U_!Vh1 zq!F#*lhRl%jnp7MCCxR;43WMn&3OM1fl;%#Pnx@x8Dc#x%}Hg3V9!YNkTOHGuSqjj zy<}mhhEW!F7w-8Mxp&D1aZY0_(}5!}!u^OWpfDqUl+A8wbJB%0Gms%rrz}G_Rm|Fe zLb*?yXNi+b-H*@u8O(Fq=tzqDiCME}z>rKuHbD#0kTV8Z-Q3aXueA?I%H3m<@e~SI zoN@{RC`G-aP!ar-vuY_sb@~W-`_wFIHs+`^DlmUlnu+tktO4R|jAG0|#aXytnMDoD z96lf-+^^1}-W&q8bp|?{>%>a;{#nH{QE<#QyM;dT>3&HGP8Bq?u@0wqg!>yZs8VIs z5*@(l4fi*tU3p1Iwnv|X=@IUirS05PNNl5|HigfSrGlx!E>vS*0xd8V&~HngN_76Q zUg7?Z6rvhwrUcAn;oRSq>6z)%=I_l~09ieyGx2w(uer5$wKve&(h;byZE2~it-oBj zPd=?ha`^FgZXf=rhLsYn8rD-Y!M^(T=CcR;8c}s95u#MuHFx-GJL{XobTWDU{&v5ZAz7$noJka9X|8SS6lG-S zYP-CxeQldKjtmXndMKqu%pybc5>YNWK+IOeQgMPJmWvZ5%StgvS*#Q%Necvfva$hn z3Q@9Col6wd(E+`PQ^`QR=V?TA)HZr+{r=kZ;&d|BEBXwg>4-yvw-KFQgE*5cT6~nw zvlO|O=(CCDVflGPHzThp>+!liO=XLGAp)R3vJrM*tn5`}QQwXLE~(d~Ye z3Q=!4cpC!kb(eYTJ4J)$u&lgfML}tvMzW~KMSY1|IxwPWB65w_-+?Ivd~$TnXOK@A zlq5%vC-WLagA5bpWKfzAhGbmt_cjVqLp0Rr^{=6FHAKc{+;d-zOgnPKW@@eNxEvfR z)Xw!jFIm7S+yUR3#x-L4DbJw|fT5WTbE&&Na}5frEYH&)x`m2o07s$d9!fMA!^9~p zZA>%WHgkc+v;aeqIE%uV{%|e4pB=!Ln}gxL^hY*RmtFKqksKSn3@3xTN!Za4?3@%j zTy_^92y}Yu#JO#m`fMtN^P`;+GzgCvzk)Znr<8o39cZQ|fUdJd!t^=ZU@C&v2hCYu zL^lsb9rR4Na9?peVr#(l8ahcwmwn(M?Yvv+r3bPgPJ;r9V6+NJl?|GSweWo&xjLfE zi|fNGuI&_8XE23>UZUv3DjIb#4<-slRG?80gw&NF*CjL{(o^JCqVaP*Sc-N0^Jy*L zRYN5G<{ht(@L-DnN5oR;^1EjUmzaMVJDdOqSQgPPsi&0MmIZ-&KUIe2PBG&an)UgZ z^+FN^Ki7lbKLPL1Y$o#Z9bjk%^*3>8q}I+r#{A6_(pUrI7ht3nB9WSn=lWa7{$rG; zMQGWIePKVlTb~V%`Y%#Z@47fv7$egjg~%TdfIffPsF^2u>yUc1kYYL0Gbn zdGMf*{G9}zrRqc<-M@3)B^85ptYrt7^Gu|F{+n#5WMyoE=S5c|)+6jN1Pj-F7b3L9 z_rm&egiw78NwsXu7LHi{IZn=p!6{XJ$Svl-#Fi^m=&p7lJ~#%y=Sy9zAzdU8;L={| zJ8@mjwU(?tMOJZ?KhzG_I?C}^V6);oP}*-fK+a@%z%wG^L&F7}Q2rNx0rvB-zOypd z-v!UW1wWY+?{J`#uy9?u7y-(hXn{wW6G;#%CsvSVs!ve4VakwQPhLnnpCV4Fo#h5= zCk{8QkLB00f7`q96049lKpq6HE!`xYD4!Z7c3 zHf(_5z7tgq%#s>V4@nOwfb;&uJhPzUrwj8eJLyD~3lzh=1#BP>zb))x-i6FV5zj)p zsp{uO+-VDEiJiw)&9W`qz${sc_gXek%7PC5B|0tl*jR3Mu;?J?J%=lQ@0Q()gf1&(!`(1kayA<%0P=kI zx)ONy+#SBxL%#3sM?t$Z5J=)wcOWRAKB2Z@5w#828{m(m)&%gpNG6KwmAL3h<(@Fk z5l`RtJIHh%bZN^T;%ddX)_(8)O%*$^f&40$`iZrtn}qkcp*bH)p*O;99s7 z%=Oh6C?jCin#sm%iYDk7?%pqJClHk+bbNT$D zmycC5nmO)jd=Bgc)4$Y+zw$SI%qx#+%Re(;a5ds}GCWuWo?9Eg14Q6DxA6=h0$0Uq zE^I>M88qLtJ#FF{i$|H?*L<~PZR|L*boTebrbc5h-dEikRo?!AkahK=tYUr zF0``d;nn>jZRt7tX;>HWVt?_uWhii-sTcdxnz8DGk}-GfKa0s>v3)zKwfj>0B-qv6vd@~ zB5%3d2PMBETXV(BqZb-I&ZV#7(sQ8aX{96&-eU=2(SLmhY^G;6;Vyhglw5fa!jZZQ4D%*bNVM---S43#Na}KKkiu&Vph(ySq5|8 zhv0tvQKrr1=CqmkXNsa1sny1uho{X%s%bM(G;Nj`(`LdnZI&3*X2LXWCak8-M5$@B zv@@s8Wa4SFWRcTmqReSC8O&)j8O&)j8ED!pIcVCf2uzz5foZd3!L(UfVA?D#Xxgl7 zXxdDanl=+}$}w#w3z{}dtftLG=1-evlTX{Unat+2nGAZ`EE##) zOtfvD zq*pPNXNiS;R0$oV`3!>WY%!)jk!N2Av-C6XI@c-+p4%<0_R(O%!=Z*Obw z>JTm+wUec;tL1W36_(ZM2BA^d2aPBSPcqbNvN~S@3j)3y>`H>b~FXFJJvQdAfr1_ z<2iZSks@vIcGUZueYC_xxy}@VA zSTLOyWxtbL9&L*SU3Pd=IuvUMx>J}4C1RrNkJ6!JPETuai%-5c)`4ZFYEkxQ=`d|h zG`t4Y4ZAL7|0bg>g$=xiv$&F2_7`b2gQQY&h_WNns%%cQH5kwK;#D}@^n~Z4B1+7x zIZ@MZv9vjUPP7A4^M zvO;_Q2*$GMeo?ke+Dw~+m2~X6nh~s!)}?c>xsVEqvQk^QwN7ZA zsP^(to?|1FB&pr1h)aUtqKEL<<=gsGnWbd`sUVH7e*WP>WefC)= z$roSw8Y^Btl@L|A(*@;=nyosZ;n@PVZ6q%>pt*v80R@$$jO#?fK??ycWnT*g2QvzA zPVQoX#X66MI&+svv*K1WD?~Hhjb>JhW(wdEK7^)cacJ1CUv8D;#ByijbdftxI2ZpKl1)fmNE{{5ph-7+a=@X zH_u$XZsCfWC96(G0KD7_#WbL3Xg+8t)VV{bq0Tf*Hs_JKmkKhPzdQ};wz#^PBk3A}U>F7($h}^q4Rm-@Scf+UI`liB;g3R*w&5GhTjoyp-1Gg@fy`gI z@DvX8A4?9|<*S&zNU|QXjcZpsxjQ8r$zQb)uK?#>Cb_KqwT({h75)}*iRGIaZP5}Z z_bP$Joh*)=XzUzHKp(%$K(5xe`IiIGmFWW4|2zvD&>RzD&HsW!LURpEmv6-G-2bQS z3v!k)paG)BAu5vp)j4>%Dwcx~LkxC=$Fbi;0f+|x^D46c?{`prLB0(?2Rhd!VPOiS zl%7k{(fP|X+En8r5J!c$Gz?VoEFrJUU%KKnMisSA1j^(}nfg{3E!aT{F3U$)*@f69 zE^cVV0ejpn!r8?d0!>&a1McLW3h+jP8y6wQA%dhWmdAp5;^S}47mXlBE~8WVU4-*C z1I!GDiW?AA;ts_!Dj94*OZJkIyE1SX9nk#|?po+;x8hj67AlZJ`_ShM3DIC8s`>q0 zx?@k~FSl_`{lTJ-{rLf4i2E!!9FS}%Re~jKIG@Y+K4NZBqYnH$Qj4S)BUxX9A zz_+Ta#BRp!0yDrhQ|F{S*BL@Nfe&{Bm)pQ5RZX0f^0EzV#;iI7txoyX2zP*qFv6je z+dFbG4uk^7nd#6eQ{ghsu7ZcU zDH8$rd+Mwy70wyyh_YET<~paR!}zR~Tb9Alof@hf< z(ovAHwzAe)p9zH%Jgcs5>hzf?vMwDtb><`}_h(yz{ICQeKH?w-qTH2yoaP!CoS*WJq;Pu)hh) z1bWR1mf27!-_Y31&Al@6TeL7AF(Sl=_^DX9)42o>O>(c6OeCKN&QMA2wPJO+1g4&E zpfjupOL53}d*m(f!T}oo9{vyf>BT<)e2IT{y|;y&(%icvZ{rBNbBq>!ucRF;RlFyg zdw+zUx_W01MRYL z_HrW6rRDq+0CVbPxA={zaJok9FCss|X}Im)@?>4Zq$IDQ)FsQRYN~i6BojAj>dd;D zSrZ+%lMZ)VXc9u$>nKh~>M)prp*%B*O`r*O(NHnH3Iot_@rIxFDC1GCz)HSC?f7DfA+}MjJpuO0CnI%K+Om1oR1yc4Bmc1@0E5(j59kV?9 zUx3@TtI`|Le4OQ&DUs((&|pPshHsOqrg8!XJp|njM>86uhZ$Ret5FTha47<}E^CKl zLC!I^yrwYiM`<4cCS1^O2;iI+)7s9{}$Q_!I=eW4t6o}3N?NP~i_*EJBvI~g4Y z5*Ei9F2mHCl1_&~qXEpNrhbA%Zyw3wy(6PsC)Tl?4p9!mwRWr^jbl9BCZ}U1^%}{+ zT{L*U$WLHC3&N32G)5;n8lyXtC)EYRyw2b5{-g(nIR}sbV_9dB!P@R$Ad57dn!s_Q zT5x?^;N61}jytkE1~1IFO!2)0+~XEj@I%(&N!CgRiS>854}z{(ClP*LCGB=n>NX)>$*1fhT%mC*dRSm%e%k|7m=57XN>I{ru-t3)$OL1n= z^D;=v&1}!%5XnHPT~$=gNY>Ti^b58X%OIICtE{$aCa(WZ#Nl$fR8>IlN{7c~!@9;@ztB6oH<(H&W`D59t(=3o8Xv3h zhk5K=ZaMMD&mZkw3PSESnH%pN4qW$qT)5GIv*sC zxdo21E1wTsQ_vszLjc{K-)5|L{}K^v4{WK8Z*ch633jjUEHb_u;@>IQdr%f4tma23 zXpfG6zdr^w?#pk=h;Hsb?Uw=ZB_!o`+8Y4X#yV6qq zfmHkhAh&8b8bjuAjvEVp6=~tf(b9_pzZZR|UN>@4iN^kF(Htfr^tZrTnsz`53yu{- zL#NR22@@V|3D>6+N>(dm<gOT+w8vCim(EL*vaW=s6E{oL3})n4<{w)c4gy0XYEpC_poi01rTO4lgmg5<73pwVot>g5AuXz+ z%}J;B;yT`o2Ow6^xt3-pX;?uorogVR=;lmh`pA?_FAzhfup7bF{ z8E`7jIZC`HIDn47&R+_m0dPeSqS0SRuW5j|QzosXi{Z%n=lSP^NY4`oYhWs#pLe93 zP5RG(s2|)-2LPt~;@%C@G_-zKx&nWmG><_6fd3tEr*JnAg>3&I(Hv$v#^=K|^o!_9 z`uTk!7p^I2egJO|AWfcwdDYe5As*+zjMdeAGs$sJ@;Ln53UC=ha(96MoT2kjt$U$t zMBMX$H9d4;ggrE5@%oi3PjlRhWuG(z-MAw%0QAEyfJ9e-n1!8Oo`5nZ9$+UYi)@BI z&(7U#_`V5%;k!GH?{xv+>r;IH4q_HIe3=uzICLc&({X0uUhU`iOZD7p(;Y!{MQ@Pl zjg_D=y)h`%8-qftTAQY zl`@aA%wM$309)e{+=P5z+VwT?{E5a61A~#&bE1p6$b&Y?kK1wp$x(xWnv16oqedce z2@_>VJdMQBqo*R}){S0(f8Nez$C1K`luS`Z@e^@5(p-c)9v9)-Ig#VdMY!YLx!#6C z?0;n-z~>2nV8XrKTc8Zi4nhW@gAQ)AH#Bpe@GoI7TtxB40Yq{S$1LUOxfpd~)DYh3HaVfxPh_|l5DYK;p z0$%>15)GG@@~+=>G|?@>eKTpA@oLnWa4!|n4{Dhmw%V2}(LZCQF_%hX=0n7yUM?DN zna7jT`;b3ogOB{>V$>r<5myMeo|sQYVBGE!gFYX*WbdweAqzsy25U&}7NG;O)_v(_ z^;_U16G|`@1WkqjcTYj#CY)rwBH8yp4v)-_cW}(9V(#BHJ>5&N~`Z+GQ<@ zWtU9=m|fNch1{-icG*cGxUG-$8x+0{^tKk#UzCEE5A0?Xo6+0DZEuHm6zN|iaSuwv z6I%XUD}Bq)F$hf09~4#Gg_fG0|3rFz&|y%O^!BI1VH@)@yMHG6TaX{mWp}r-<{27) z+<$q^;63V}1=yCy(WX60z_u;|Ms-v2UkYbi73L(TgorOz;!U`Xy(5DdFkEmV_eqiBU@JCv1Z5w*Elw55duN__l1rv2w{OiLLE!lOnj_KSqtn>t;&ig3;c0gMhvmTTMtbP7bo*(%V{KM_T5^t-V{X1*(f=I6Fb^7F>qYr zWxf-0dYC@B4(7@qEPF@WYTgk)_7+rAB-OklzU(*5S8+amSNz$tv8@?vBBBQ%JoKr= zOFc~l{2g4qodqLsY=UXJW)~b{TTZr7@s^0?2ay+MAun3$SER9En33Q znk{cyvtr?CI39EVTlnVq1$vL1v$LM)+d@o|uSswlVYZ;C!0XlER~?ed;R|7*a(9hr07Fqrv1z$?IQ)PEtd ziHSW({ECSdB;G=zWR8|IUPe7$Wq?}|*?9m5jn4R=72xzh37}{Bam#bg0`t;4fgAM@ z{&dC&81*y~$01R2vyyKM&4lB~=UYXviEb?CoirZvEsw28OwK#pv;{A-lnm4KF2gU! zU!zLkLW}jd-iwv0q?QzGjr_PdIaRQTl%&73weZv9lM|s@sxxc3r&TS}&?~D|?Z1IA zCxbP5#ou|bS=anN+QQ}N*{clJI0Wjm<@h6hU^?)4ueks(?Kov8YQ2wvVaY|BVRrf(om7wEUf~eg!{y9b*UPgdBQ( z-#{B?U{1*4Ci7Up%)p$O!;RJ|f(8su4d%l0;FWqGNW86#7PM==J>h_a-lXnT^8}$v~SD?(OPmuTs ziCSW(#QI{RhEvt#v9=8QZxafz+t%Ulw5&5Xj_BX7&MDcW6m<9u7L6IlwP~zk;tK$Nx{{;M0GOki27pA9`@p{%T*78e`z$cG>dMt{t{rCB2R?R$(+@rkqq|LcG=zn~_LyL<#v$7F!hd8$x~=*0des z%_OvjI|4l{A7S;dL%f;m(9)t>wtS~g+_%gpX*N5B!|g{vPs<(mQpxql0fyNaT;_9l z^VCuFv;{?T`~zngn@`>qYS~1f*u}%8i!F(??n&FalIOI*L1W4o$HkfgKvuLCX z4)KgeZV`1-n}r=xm^orQTQ_8mraShCDd?7FTT%*2(^ zs-TC;j3tjEcM<3=Mq4cQDV?K(@iUyGdd z&vY=&@%L%})bUBX+bvS1l_v`|;h*F8)A6dOtC!1`6j?R$!Q8d45ji> zfhpybG%Gyau5IPg^B>rrH(g5cq)U4`S!{o%;zCd7<XBAEbuTQ~C+8^20#9=FM zOTiRR6x`d%qK>RPzkXHtgm*=xKsnzKX!PSzR--FKqc=+X%|$kMl_=q8h%HL^7PLA3 zRyzxfQf6Feih;7Tg9nl!KmVGikBzbqzJ7m1f zw8nPvc`RL^)jftZf83Ubk4FP#y6qyShwbi3DjZ0?o7b7o*_zVi-rCVLL&2(4e_vvGFF^&iM#VTp3 z2PwPzpBx7VjOi((fcz^Ml_Zs708E3X8>>TullAO zdd)TwJ9_zXYyH1bvR8rI2$sc}1XKP3Obak&eHV7b4;9Y?!hd|IZ}gG$eBT1v>LpCHfjm15|!4wWaR_ad9Sg7TL`ruM9pV)yhYG zWwYf|Ps&y%I!IU@K%w2V&}gySX9@&B_7ASUh(6nu1(X?BE`V(7nFA{9p z6Zn5Dj=n}ehXh=6+qBCvnzqW8J{82pnb=umH;cS7_>|oKADU(>lcv>&n)V|tRG!&1 z>oCZt;oV1MS=y(>Ex}yWxzw&@kH}hf5kwwq!eu$`ZzDu^#mF%p?ql+t>}uxq(Y)h6 z9^rHH_W?UrPWzvbXYk91fCf|4lTz)kkdsMh5ZLAT300gN0#EK|>>?QLuS7PDgZBSf z0NvpzCOKURICxG5hPJv6eR`6@?H~cnJWaVm5oyRmHU%%46oTvIj2VSzsIpU`1&FKA-pT5Lbl6JuflNd5 z@^#A^HY~?i=NVkakt5v&%JxBY9e*(WB<(8dM!9Ku4ZS)RclYoX9q-EF-4ptz`8fC* zyT-gp7Xmi{JPC_6Tnj(SHPzp_W6Ox8_-rIfMxvbho(GAU$)l1_K&v>FT(uY>9o?)b zt=`|cYYUg&?C7@;X(8?p}H*>eXtjoHH=1!WsELw1sF<#df&7gyaPJmk^Vk{FA=!jL) z%tNP$h?g?I1|80qg7ns=d#Wh^1f1c>gfj*_aDJc@&N$l4Wm?f*4=q18T3m@);c>uk z;)&32kT{4$EwNLcNA5UiY0A4uJcq>SgGl7~aphO0jH1hB zVDB54niU>b-kVJSWAaHgMwsjlCc3vm#r~aE%$!=J)!kj|c1n5`rfOsB4q4M0Tg2#W zhqiQ$51q}7&VW+oG3pIas*}7;`)oNz#Hm0T&Q9_ng;Sqr8@S&*Itw0GNTELqBep4G zJviMJ;$-V5r)Lz-Y3{xdqxVwqnNKSGUkZbZR`#62IE5x((G2I!-mo!>45E^^6mH!} z`gTt8By9*g`V>PQ?r3Yk(no=Fm)sC){tvZ|Gr{d@h0~m_3c+twIMw(og=1PteyB3B z@lS>5zfm~(yq$v2%~#u?62CL>?B=~&vSQ16ImsGD(zEJ@;ir97vRmPFCKYC;298mg z8giX1j(NKz@X55fT52zTy1$muolqN_>{55ImzI)AnC0bQ`qwg5JO!&U*In+8-UzDc zBh1u%uatikIhh?MqgalA@N_e9>UYET?w*JlS!TC=Q68_s?@L}AvgvH#A$_=WYT0`q=z-}aq3++~|2O`Ul+tQ=TT0ooQj3CUYSvNKv>Mvq%M>G2&Q#dG&I?+Go8Lb^8N-!$x{!p+INy6g@V zf%a?JD}u%pPPUC1D2VHWj>z#@iNVI8 zl8z=g-@Mhjfwr79@Y-+#FcV&3aPV zCwFUt3i*eTJv_#3xwaMZfEK1g+Myn8cyhnOsgS-Y_z8bkc!om4_Ca$`yQYo+N#-Sc zcdIna8DhHfp+GU`)mX)B6~&x_rW?haB_+DU?Hh~BdL~9eil4#W39KmU3b4uX7ucb2 zyw*d-}49Q&c_1{NAcn8A>% zcgk)E6)m|Zl%Y<++bk_?i%cd3xc`Z?olHVk{M|jGoPEk-WuVUbTC2`IqRuHe4m0QG zzmRZOe?ndqMnY_At-?N5PE^i)`sc4c>jA)+y zS_#wNjd0%)5qD^jZGnhiPO(~kM?`!8B93KP3Hw%s`)(HRM%QDHR`eH4_sH)@{!`}f zrnC62aK31aHjNCirk`e(;pEeyracE#MsHX;Y1)h7-bk76Ja<@Tr*J}7Q$$JR=A!lC zr;ll`fVkg^hy}{#yrA*VPPL8yRvJHOtZn3X(#S`dmqvak92&-HBUup3m2G6ba%TVC z4pc@XEuA#-{q#mU^S1w|)@5{RoA0o=z2zR$UggsqH17(W4jZqmw_Kw73gVjy=}0N@ z6C4|eIoUyIjPP3^yx+VRL_ftgC^Q#>lLmDux1|Nasc z<5q_1r49iM5Jp_$Tet&a@!_VS0+#te9{I#$!;3-)eKoK_Uh{K1#0nHS{@fhI8F;@wX$#9-(ugr*Bk5LwoA5dg|eGVxD{p__s!tr z{pNkJl3?9T9--`cR6N$O*JBbK6%Py{=P7bCS}o_uMImIfBDYxNiHf8uE;mRl@qsFS zuIODr-_;5|^Ik>&PT4j=_fIJ7dK7sp1b-#O3SUt+eUehT?RE-sq(!F$IbZvnf{bg8 z-l=H%in9%xN1tUcC|nL#4r+#u;~6QU+^p!|K$a$p zF4Q`WVU#={s`x)unx)pthkQIUmm_$46l|UCK=`UlXSwA!_xW@W{z9HNn&EGrd}tB zA8WjMox%bX8Bw}KFMCngFW*UP#H?H63LKG zjnolZikAGLDHZPS8b#9@V(F>4FePH@VNW`}l>oMg>!o9uO=wdQ>kV+J@tgi!!W3jl4%Nm983w5{`58! z=s>jIs02c4kPrdxJh>CRKnpI1yxXSQxO{c@(3vwqyitX zeTd!0xE=0f#v8%DYuKVwslV1#j1A{jndaG%zUUqJQvCILdW~E0pT8X@G+$)ET`?qZyeFIlz0(SPxiT?8syz1)#M z@pB=Q5SFXl~B<%mZ;}+$hB!6>C=I!}yz96m5J7TH|krs>SIc z?Bn~~#>>Hvza0_Z4*&Sualy&pijyxg=f6d(As&Bo2Spd13$Faljb$(D25SE1=43A_ z0G_|Ozt3tM2|Ry0lr~-o5Pv%)7cIg+{`xPti>?Efzy6DE2+aTDL$rP>7=5H# z%C;Gd-fR73T0azwK61w2QLWE`j_~S{?IqAIzTktu_(pB;Ia(ZgQnVlpeVgB}jl}k_ zSY{ad=oJD@i}xb;NvNZS)T*#Co^bOZ1u_wx9WMkz z_;H5f@k5|g)aFPCYU6-A(Gaj~>I~R=&gmNh)lHf^ zqYB@!bNYpVlV+7UgF<TsQ)RnT+M-Z)&a zPN~l}R)U^e_5siYJ+~}d#|syR4eqkH2FFX_9M!fJ$60*pM7oJIy5idLwEg`-cv0cK6w{L|G#|v+TwDH0%LYSq+ z3%3#C^agKg2swHF8}0yXK01}5zx+2{zV_vGx`7#dxE2{VPveFAAGj|g@8zY%3-|vj zR1pgeLOT0@7ev$|f_Tn2P$u83yv%sv{uhGC&I{s&`~Q+EV}RJ0-~KlOYDcLmG$hb> z0?N%xj~DKH9_#6t7sLzqqXIcBFFjtk9}{pqkD-^#)8mEv?FH8`U?Q!eh5OS5<%^Q7G7uMRwt#I5Q_;fxxq^WC1eK&r>qNmp2LUc+ zT?+*VBMNYizgS?gPEWD*%cNOxqn8z;m+nR{t3@vbShu^Q;ZY6?J8+fFX$t;4c1&+2gYmQnGP87P4mix8L&lN~-=wPvCDm{M2< z-+$gKh3{x=`-QL!FB=&;olRZ7YHH8R)1Hc(3U0! zsPdz5m7i#p(#M~L`q<2Ge$MH&1J*zh6K*x zv8igx=#ZG7_y(=<^v2;XGsg8ou_(0FuY~IyFvMzY2l;R%0u_eBEhEfS7_( z4pYReBB-$vaRzJnZTK<)W3HSvJPfWBX0f0-eEx#Zf#Jn`T+|JX)O^3zKRal`RAHvN znkgC8)m+J7q)yjQmOK7@0r`1YU<_-xgMNc>LzGl1{W37_Ojq|XCn{}=T?0t;A#_Ln zZ#n*N^Y;SKh3Nv<`@Bya1J=YL@V?-Tt~m{M@BNdoNK7t|nqc?dSKoC36@!totC}3| zn=Jsu1Aqyv>HT{U>*sZu!uzRmS3hm=KP6fO7`n&X+pUew_ z-Ft&YAN%ucuzPQaTh$d22`xZ^-Q%mfEcZbG41(Qz!vynD&<7Ii-b)DAgI!ZGTkVZz z*un@wI&N1v5Au$eY}|G7i#ZoQcNPj4SY_GxFWyX{EtFN)ET_Q- zUc6a?8Cx}KQ$&K8O1Z*lp7J<& zUES#5&~aY8RU#4wr-r}xR*OhOgMFXTh1n=S>z|mH+L@VsWDx#7*g;6FdkKG^4l?2I z(_tq3eLBpBzqi{&u7>8bSTtBaC*pNZ2~jq)VNTWbN<`hAfp4Cb+4#(%eRQym2PrAI zm{r!#tenD6ai@0lz#fuCu*U}x_G&Ye_!{~2228?{KusE>pCjJy9a)f{l5mEN(cisQ zjQ$KrdW`;bq>a&^4o!uE-;{|6V)UmYOpN|?mHFC zc{@EG$&69%7iaf@a5%=p-yU34deSy}KFvQop>i@xhE^fJH2Xv;+sLv_L0KsliTxZ4 zc_hXaJexC<1{3#c`JLOC1QYkBFzv+T$)m||JHcf*TOJm0p^;$XIeod-#B4C}oB^ak z!B8;qoPn~=;|wqqOgv}MuRz$IO*#zIthgSolWl{Ew=3s@6GJfZb`_*?j3?3Lw5y~7 zBC)mlT1vYK%x3{YHjx;elt_%LMS5Uvr_S5%_QHc%nYUA~_+#n$vCLrn$^d8S3uOMo z0+JqC+`CZV-Sc=J$%qEtMQ$JTLSdd=#28uJyI6Q(jt?S>dplfutHp3G_;~{CWaw^< z)_M6VnU_lqQk{aU1!f|Phx|W{*5r8JGcM!Sizn;-LD(5L(0f)gu5&n5wgfai`3L$q z0lJB2yn*e+y)NEe)Cl9ucwN0GKVum-gx~f?d$k~p=gA{-Z# z6gtoJ$~vzJWCejoA;Gx4bA{YEhK_fw$M`UbJoDm{cZ+uovZKSi!i(!8-h)7w3Oe;n zDkB)T_loy6s3r-OS?ohS;&`8U?Rz;+UEAnXFmBKFj|E+Qh|a!v;dS+=0<{2MLFPLd z-avmjP|MJu^kCdxi6GX%>B+p??NtkEqp%CM)8Sy;-U7K`?G_xzErn+rW@w z828ZeHu+TOj=b~>r`{I-aS-pyOS_5b{m6e0(A{}$US#wx5wZ5bmf8r$?Oi9>z3S*> zT(a}-6zn}Hi&2#d#_iqje}NkJh zfv^mD=0!yN+MDM_iU2-f!9k%=FmCVg2rK-6mKO@f?Hv`FhN1^`0EL2ad&fjL*uLzl zj<{Btinr|*3jy5WpuP~YM36BZ=Nvyh>E~jcbI{4)KiL9%G6l>^{ENi+sf$Q#hNap@ zD*geGo?|3-8ZtdNZY=mRq=h3#OHU5`o@Zl-_LNA#k=P9u&0!Kkvw4<=(T{`$$BLoh z6lnN_2|uue$D|WVRx4!Xkys}X2uqF~5!F_9yv1ukRk=QJYq4}pUvZ{jRYK!Jb zFlask0_Gx%q1hV@XD}nbGT&oqI0y`ls7cYk2eb#RRhkc;e?>YXpC9Q#tF!a8hqSbd zHYc6hlj~qldMj4Y&X%T{G_0T}Q((vEW0BY>WR5U{+nyIAgok@Nz`c0}={7J4LLM<5 zDRXxad)m8*E`onQ2nrZ`+T?rRh)utD5xc4nqm6ny#F02sJ(tEc>l@asMu5Pgk@zA4 z4-fpqdV>KzH+C(L75aKO%>$s{qS223bE5h!BIykzb^0{$oiP8#cPW${MH~qV^#}TE z6=ppM&a?b?v)FF`Tu>gxjS2wtn2~O3G_Jn?UKWjPz^U99neeG+gDPX;r+GLbJU83t4`*3M83{qtF)@GLsfk(Oq_upyWnV_ z^}75*!%=ek>u8@N_$cgD9QPRca>IbDNtp0OSatx?EHvP%RJt&iG{b!!01j%9!oz)r zqc6OKL?e8j!wte~)WuSCa5s=&0W@WR0gy5hW8wA>0YHrCJ;#Zjhx8C*M8PWJxDVN9 z;J1LBKW@v)0&H+MP>hF|{CpxVH=x3YDQXfgnGHL|aUWr3BQi(FN1019xJfTR4Ja~f z`BJ>`{CE?Rw}a-GIWUA0rR!+O9QTp^Q_sKAelh zcvu{X@j!gIXMtB9a`WtTXT!w2UqaErao7?On=3O{8Gt^mF#nfSB!SA5&v&> z6{LDrNm`)Fq61+$j{PE>i^P^es*y4fasJSh_SsZ-7VZpzqS#t z%n#$^6?gjRkj=Wo=yLr5auA9OHb-;F_MD8juElIEijUdmrkn4k2`HMLRIs;cyF{ewb-R8d5oKKg7mjR-+Gem2~oX>Dm z=DbM?8FMyiTIyzj4#JJ_EhZ&zjBa%~`4moKWoL;SUnn;BLzhM;cFiF46s80lX~+H8 zJ${gcPyD6fvS^81e7aTYS9@m(vG>kSl%kL6Pcwd5G_$@RCNLS9FLV3UTWWiSmGzc! z`3l=1^P>9-3-lJPzRF}DwBmJ1hyZU$5+eOs64Jv^-+^zlI*BnvR-@yBg> zeHiY!N+*6Q_BgZ#c?q%mnb^UCT8wO&T0avG-!d;9Y4R;o?8yJzC9nOMwo11{Hus-m z(_N=wc153kDW#K~UH<_xyqEGrb9KFp!*t|vX7KJ{!GF7hL6LA_ZjAAj_#6b|W+3q) z602q+@dgq{&qCrkBo3dAs9G#o(E%kMM6RM661=Qj(Fcjkk*FMoguip^mWtz$$i`*b z3Dc3dy~I>oS&0lT7^+AU4}#m`q1e-$0QjVn@u%zp{5kx1L%x+`;D9@Q2qbtC@af=} zcmRn)TuV*-3W;90o0+%?iGC*_!FSP5M53GpEB=Vw706Y*jzq(JB;H5jP9_c_@h2v} zMPlDcNOXnO-PM2w^g)7ALMnzL@iHJ4qmVdmAzD&_#E-{lOKOnG@fX;ZI9afL$XPKD z@I9ce+KTm|&Nc*C_pi4Nz$@Z60GzlAe@Ilm6^M$x$o(0)>SaoP+5~KAKwKklT06Bn zlBQCwFbZ>=iThFZ{y`|e6jkOgg6_5>F=woyEx@|s*10!CGR7#kBQHaShy73<@E<)2mHzL>r@TZ zKhfHA`Z&(ofkxUhA@j5xf9RRU4r?S7P7U9RcdB0r(chR(zhQHVeiK;CjW+M`@xFU? z**Md}3!#nIO&K?VD%@hQPRW82IsTi<#Hl`2OHs1iLaWC^OZL-HEu#&6qesKMS0_;P_y zi!|?dp}czHYbPq6UHCn9?z6J9wJ3|y{nTh!D~AK2)mQ4+Ve>yyQMCC}x1=m-GfIf% zouC7m^t}cfMr~N?I!kW{K1H5n=rj7*&IL~ON6MQ5E>Paz)(k5#)6NQ2H$u1@t9EycdM$CMJg&6q`kzOl;-Yx%^` zXY@^4MTwxImqUZR20E3XWMR)FUIpf`;W$s1$eq+jHZ*uUucyWK3j-2XyRAZ+VIL-^UA^4<< zQ~hCRs5w~f!%Z|+VVmgGzHkT=$e=^R2dPACc$wkq#R{G31EKytr_I`S=u#nF{$%Ha`(0tm7id+K-ZyN`h%T*Od^VQ^sAGf7*!fJkyXuc9vp(hw# zZLmk=P5{IM9)t{{1gOc?PF7aB?1X0`OCx4ESFML;^DbOTF&pv{v+3nTdmtSa{*Y(( zZmG0kjaK|m(*(5PV3BP@skGq@h-^0YNssRRm{VXs;@+2g+>+BJogq813Xf&!V;9Tz zq0-|%=BK0=dz&CN`a8ebOlzDdxg$?ig~W$bA^TJzGw)Ejx`HEnXgwz)Gh4aGK@}W2 z)z2vrXRM?W>Wnqd4l{J<29Um?q?{J!2Bgl+FBHBdtsc&C^apH3`IV-p6Ywd2E|k+` z9uyi5@ghH+pz zeywzT4f3Yr*J;OZ)sA1U9e;4M>G%!O@wbp(I=)#u{v+x5jgmWNrFJ~!!Mj-2Promu zt$`z2t;?29)OM2XWOe~mJ@Zp7Ji`<;<63))7Bm;Oqw{Wcw+W_CX*>*HA6QwAA2J@l zd57y%_g7k4&lO6$1@%=Z{Lw?zXS`sU=&KhgF^%X$DKJgUT9#BwwFySFLWyWZE;M7L za%yi@c)Ag#X(Q8!%v>N#2oHwCU7UL6=KfTAW1q5rDwqbA9Ba+wryieY+=2cY!P~2D zi&#f|74Y)8y%vuT9q_ePIoi8gup3ru@2&?MyalekJ8>T-;X;7SgmImBI?~+D89TXN z?WAQ3Cy1XL$-rrP^+eNG!Cb9wC zAnWZ!sR9{^+buBqp9ft?t&fTDJ5-!Y0=3>g(yH|_8GSixtXj>@*`G5n2ZE2wpnC&( zD&tAvx8w&?G^7vbxD7Gr!`lGw z<~^mPd2S*#O|l6l`7cG3z#K0VHYgTxYCBIdozew!k!3BLC}) zJ1S7jQAnDGzvs~*x(!XOu2wQSkB5Q4^uIHEuEO=$fsu;R=fm&4;_QAc3SFa&J`d#B zJet!XUp4>63fhLkM9xi!KUMW>yiE~z^2Lxq~r5Q4DJ1@04dZAGqVuNGn#&we75fl^xc zcV?yAgwX*l_ScB1*=>o8N5wXV?lzxK!`?(~MwavCiPFjIF~-bOq94m6BRV)!i2NyZyL797@JbU`-1{`q7Vt0|B4GSVYTNuyP!7a!@!KiKhXsoFkBfn=2ZT7y_5AawQTu{vJF24zErP zoGXtPg&Hxr2YxRYI`w|@L6^=1hTt?U@)q>J*AzimkD z{xZwm&i5D88cA6GmhUg0c3M;FRR20u{N0S=X1ktN{SK|(seVWcUNagdW(z_=aNa|h zuCN9(FFMsZQ&N)7H}IgPZB$j5-ck+-9&$E^xG-)txF3RxQ~P*`_Rw^q*GaZv=#o>^ zqB*f2)CTBACC#i3ShKoJ3$PCcj1!r{dqO*hNJR(LFrDffv=oi8+?3+z;<>O>{fL?c zC)5)SQj8mCqM;t!C7587q9a4OwjvPm?!M)*K&O+)&y|^{wOyN z?l==pfLs=M!RHG+V>ScdinZgu=(FStz!uB9Hfb;PIPOdSFMuAg#V!>uo25crfro&> zcY5qp^qtDY!5sq%#)eO0R2NK5%@U&x*z_IogTVARX=;Y!uskvC5qw9kN5KPj$$H<+ej6 zNQbP14o!zlln(il`FZfc+({AA?)V|QAY2V1n?xQ3=I_85FRD7E{a1lO7(A=}hg1M+ zzaLN>8WlL;RWRq+83t^%|F^cZpFb_Ncx)GXJ2Y%ft+kJb5f!0gDeb2fNz;A>_0G0M zVtlbqw9f{K_WL@~r;x7C*e|uM{uL3o2e=IoO|BGuIdk7c@dYXp+;jPHTNu4Qk&8do zKZ5ssisBEwTgtr5)v&OsaXGJl_%%;voAu zvwDln{ZWJ$Z!S6)2hhCZwp-=IY$QMK&d9BmP{g~yJqn`4OGtdk#FI$$Jr9ZdZDKDH z69B1wNtyfyhuVkdU>$1g#puJvzQaHDVdqhn50uSBE6Y_8kz*5Ur5x8XK{+VC$nhv4 zl;eFQYLA(2%=1uk0^V5UqwBP5Rgg7~kYffXh9R6## z0)3te_|s?t`Q$nTFSrFf`0M{ZYXJfLZU3O_44(|Koa&BP`Tk#wcC&o-|0c?f_Reib znEq|fgE}&z-1z;T0rLMW%8g$wW&cm2-1uj_k7{j{8-M$743S9eNc{a@N4aSg-v&)= zT7L4XC5sChmn~dt!qqUeO{D+%42FdniYh$iMAUD zK(>aqiRKOf8_7y&n`j5-BaYCU&^B4~7^%q?$U33I7Ld?3S@T&ShIefvF^Zp~p>47+ za#^h1-Qa#X6781(*#SCau&j2ZyakC|LW6)e!Todd0v#KOgEf9j#Jhj0t$1 zZRXs%N_o3&`qY|3p{p1fWct)8Q)kUcg~v(fP&TWk+6m(1q~n6O#8Odn(g|3&0fBWY zleM9D>-0fm=s{Or>`nI6w+gd5jL zB(V=%es9ntAs?TWuUOcGFUS5>s3H~`go}v%T@X==2x3LVJ{3e(JTnqW>L3gobOdL)uqOu+GY8<9w2 z?FH8fw(=yj)`=FB_urV+Vz>FP0MMD~0=yPpl?}7BuZ44HYA$#!oUllC+H2vxfg<<&4PH^YvCj;Oo5crb4fZnp7B~ZiA%#kCC?J_x_Dc! zg|ke3D~uNGAO)AjGhPe76Vv+|0z)t4;kEF;0lbmm%-6y>B)7&hUJGXnwi#d>uZ2^I zI~1GwS~yGY%D}-RmDj@CL({tzm-bpX3+;>RFwys?`s1JtZ_&iVuZ2?|`{SY4!WV(# z0SmCNg|plT0WkbpI58guePCY;C)b1dsTc0-oC8}J;S%Y%UGB=lm^)r_cq`n#&}k%= zcfwcVXe@5u31@qpc&7%+31{7^rR8G2PQ2|`!YM(_2)V*&o#Hrn zBiv}Z-mQQ@~nRr9<|%G@`q-Q>)wXcqUA*tZXQoH39xp8*LG+m81>15q7R& zUgh+u4Ry)#>dKjL`Rv4)dchfss`Y0O&hyI1oscq)JNM%B{8VIjy4G;2xLPuiu0Oz3 z8@pCU1;Qih4nAlzmanC&oY?J==fEfudkKGgyp2CS`3Hax@XtzN3pu5+yCcuxkbrZD zu4hi{UI95+Uio5l?EVPn$yhviX)X3py>QhpCep<3$Yw5BK&WyoA<_L36q6v}4cz1%PzdITUR`2Ebv_AHoN)7V`g1v;o^Q_C5R9k=gWD z;FmbDKG{^8)AbM3%fRe=kckBSZwfSE#Y6Ov#zju7IQw}NjKp5X-yU>sda`s+mg-5B zW|jnKpld7h20;Y*T8tW8_zvaY!kj?55unJCWR$4HGrvcB_U=4>{KuWabB|1gCP(W&kTm}9Dwbpz@x!H_GPZqYb-6jT{(TMY>9** z{c{BSr(LCVPj)H{0`m-mKn9T*o$^SG-nh}Hx6!>Fh>nO~Qq@piGqt?Bp%%NanNz1! zm8XNTb*ka~>cGpA)&+x@5ftWjf`M>sAZmiK7V%>)5ElU+R;!>1Y;AWLvj~{LeP&_Y zGSq+xWRvK6F&c$X2`?g3tTO^aC2&Rn_0& zhH1E+N*huOh?{|#I-|ktmS+f&Sz|a$9)2qAac z(O>jC+sVV-Ei1A zNvO;&AiVe@SVSq%b#0?lH>?mW;uO%;hv-7VBF+YC0rm^_+FO7c=wA)gGULvtK5*wC zSOgJkup4S4SOifUg9=%Io|P^>+$rM81b5W82mK&^vC5PJ{GW(JEGf*SY5+Xxm>1jLgt zr)vT{5Zw3Hk%BC4%yjm6MX3`Ul+NNl^s(CAYb@lL?<=N3)- zH)uMj!2H%?XzT{VdCSPJ%-^syG<`!OYErZdXb;+`G#@+*kVXJSbVm=`nw`x@AuSr9 z%}J;Bq=V42p7klONtR|SX$b7e6xi{cITBleOs{O1ZbAErk05Q%glL6s*g6#hr>cggd}eErR0mgEelY>fe!)uOdGHj)5*9%TGsSgLfkw`~$+E_XIR#C`J7+LKo-XD0mFJ zIj0wXeP_G5RF>GFq6~!eXF~|I0M~^QKUVN@0AFXoe$zf+`5~~xRUzy{2J1C#G{~ZR z6zDfd1kDI;)%6%aXL{c!^029Q+mvb?$>IX106>3 zG;W0GDl1AYuRb5T6BWdwRKZusiwe4c5I0=UR~1BOnhvDEx1xHgASASz&R2=oeqY=DfMnNf}$N;gZ2 z50H->;`_*wJC0G}+>OzaQ5$Kir$|9mZ#KdWOV_SmnJ&ZSMutU!44116ytBPa>w+7$ zQd++jJ3{wLQ!gaAN>a}8YEzkRj(exz>$FeC;}DrYZp*oSt!3RQmesJ`TGm}s`-8}j zF(Nze-NIz_j|p2pxkSj|f!Aq{m*+~49kVQ!3_`8*V`HtC!@nSHsW{ryiPLZwA3{qTu zk@0EEiK!=ad_n``&H>xMs9a7C?g#bwTqNE^!l_&X^i1HAUx0yk zG45@!@TXdMHw&+hPGmtTGzJuCz%!s(u3Fwtn)%T!U^4zgz#Bj^{?ADKh_s1swVlhV za3=vY&>P<4af)iSiYCAnhJ6eNLy2m65{mQ3{U|!Q4|om&?ndye$|Oi03(W6;nVdu- zIR}3}MQ$9I{OQWf!FjuTO|%yo9SeB39pId>SPEAR6a~SJ%Azy1lobvzP+zW1VK1L& zsKYaxHN)03+nFeQbx04_XjSV0zcB>AJ0(KG+6P5=HU%%9r+V8Ac=-~|98?0_zE7-C z7~2%X_|P^bt_dl;AOycD1Rt$%2v&ZS>Yzqpdpb;N_(q2*kc+D3P^6!*6ig_Ff4Xbd{dEJ0otm!QXy=d2Ks@Z>2eZ`I3v%3>vUwsmN|xF^ z+3ZDKtnSX{Du-KkRb09*%XU9T1tZ1bxJ>9wnai_j30weoNoBJ7ehX3-GpjFivif#( zI+00DMoSRdON#DR{mcvu?(_lHLw!ctbRJBKRXr>8qqMhg?|`5?oIvpNmBDa{PG!;L0^18i``b>j60c$ONi#;9O&#yUF*-?C}o* z*7H)XQRMj)a&^ch|AfR{NR%BwBF7)SO}(zQTKvZtmERpDb}3(HEV@Mzc4-;dmE$CQ7NNmlJ{62RM#w(P=8kpn6)1=6kDm+IYnap6x(zGA>k9#YOfa4oH!cS& zb7qe(BGXrUWS7n`k3a@|`BasE98Q&2H^_;fdu(j1u{I2ppT%xI(KNempSHiVX})vI zKs1O)q3#i}C%|mOl|WSPM_2bBjM`T&X=++{GQ7qwEBP~lC0uU9y?9;FKB!u__wsgKP8J$GTo%S%(p zJ=z4>g;Bcy*3y*jaxG0MPCv=?6uJK1z{B%%8q+fay<8P4<-t(?Q{ODGrHcQirDSz3 zY%mpHi;6jV(R8fqYMzvGjNvQ2H%H-=a_#rjx7#|n#mlsmY~prmhCAXL42$;7pE;LB za=*h*PwH_r%;$uZR1c^C?36NvvlCwo3HA$xQ?MRG{<9(uhNrj94!VXne4WHS%Hvk> z7;kt)n!j|iAQA#1V44)FS3)&y`ktCPhkJiBR{!g@_kUpuLfK%R#Y+0cP(if$T_^%0 z$=kfeDet1)^vAY|z4cp!5|WPznL#Ja52havVUh>KLct`b{X$ElhZC=cIGyl)oCbtB zp?T9gt1bChaMqd9@-}H=f+FsLYHu=#9REq%4}1-8Uy!Ny+vUfcqNQ4dJSJIt6 zgOC5*W3qT?>Q0*}jz*EVm65f3w_M{`Z#Afe&wN6)jF*x-TGjNEpr%r-$?z@<^Oi$1 z>z1rtxT*;k0pu;{6-&(dS)I7FyOn!s;Gz8P7`VhDYn||0i#dA)Z%@Fkc&F%ndourLm@o;Heb{lx$v$ir_hDwic}Yv|Wyx!z*RmuxVHbcF7x)#+$>(06 zwD*g%7MMAK76I>Pw`NP3!w;j`j9L2w3FWw01iu69ie6AM&J5rbo>XmXWa%n6N0%kKjpUgQP*Pc zlZl;7ev`>7gHO@L%BPL-Ve68f+-iFg%^am=sEZR&uN@$jp=LIv;6<|({xs;>_f6X{ z$=F#t^`HVC_p4cZm3F*o78LV3IGM);ugWu)NoZiv^C1yhu?#=U0Mie%4l4CY0n?@t zmg$GW^ygrjII=M{!xV$SGENLs1RGpq5aJJwQ23t!Ut$aFcAeQ}Ax^={VV=gwUq#m`yp6uMJTv-U1}tlp0o&c_L_z0V4!hc?yepFR+GvKYCZicRp9!g|H>$KM`8=d5 zg*kH$pwc?6WK__;vnZ*LXIOVZ(&ke$y`eGamJ?mFgo<-O-B5Df&S1+P%hU*3FicLHc)3Fh$9;E$gtE8%Irg z=TjbB;K2aqg&jH6%RyxyGb)0PMxu}FW$D6UnBWBA@ZV5rx>AF zmioqwhS6lDI}zQx3597c+~wEPXc8Z&FkCP%3$O^cql`JEo-**X9fT@Ita)Q#&3&~L z{Yl2bF?BhKh7h;z&@AAG+J8TYgSO# z0WHPz_3Hv|G*@V;=&y>U!&3$BQz7pA?wOWe96f)>&!oO+gOI*@uyKY1klsfCQG>#wT$8GsdP-n5!`8+C_ z%j4~lGKG6P7Zj~+vr2Enn*UT|c=S$|y0^Bfd(t@D-pNvT`@MF!R_AcIRv<63)CRI# z_a9`T5)RS+;F-{35oND(nIEX(Fu3(*)>|y1>_F8rkt`9_e}^n5j+3Q$^&NKNSf+y2 zC7x539AB@aUB*5*zSd!U9Z)Ro>Z=fz0Y#mnFBMB0wsvKAAv`iNj)GoXTCx@%LbP4{ zR5Qwl22HpiXhO6dC+@Q#Wqt5Yf}7QjFEhB)>O(IZ0LZr!-1-@O-^0yr$F~gJxw>2D zT@X{X*-O zxea-lXx$_y+PKaqvj2TpD~n@*xI^2GLQS&&&Ak%|UJRIvgp*jRWdFnzH3c+KpgYM) zT&ZBrT$d;~bi2paBs14bI{x+SL!1H5inl8dPTDsc9`X$Jz5j=|_W-Y}IR1wBoO8>$ zk}S#gl_hs!%W}76EL<^ImSjsJG)1TJ8&g%cY&W0s_z*pR2uoSHboxss9yG|?oOxL9C^>9`qHO*BAu!|GGvK~ai2TD zzNF1iP#bL~P|QDWc#ASxR|r{SkSBV`Z6Rd4LF)Mw)Ywin$izWPecK?VSg7N6ZYbon z2HEGaeZwG=2zjqT_PVO%69Z=xe8Gbw&>HI0jWyX!?XV9G@+72gVhHY{JefMyx|tz( zp@E+O_*?@Yi^%60I2SVqhUn`JybqIt8UvpK`qGslkJ-pFx>jBbpPSKQXfpk3HmuUC zW^<)=SD;v=be!k?4&`bP{sc!`d0?Hla_~tr8u?*ri^{?UWAUI%I0enTCwL z$8q4p8i(YR?l5qvDVKyiCD#}a>n^S8AcWJq2dr)mAs+D%*gY$`Cxm#-LtqA4@`ypO z`hMmiuq9RUOen-)h%Ip-?W^842Hq(ES#0KKI3`>P+huIgGmjcW;B`R$yIIGZvWRWpiy)-dPc#le|Sb+(`qn(?%@6-k};P(EaW<`9lua12c&&IWLqyzl7WnD_o^LI?16v zFNaF6Goje}O7?_2f6*+YDSm0-Y;rNg3f6?L%J0^NNqEV$kY}1Ea(W*_ja?K%l(ZNR zOL2>)`dTT^Fj8`;7rm2`%_cOZ{Z1fAd7pt_YhY+7B`1WUy*Hqpb*6!vGX%2}v>)mQ zb?6V1bAt_S8(aH3#CI?+h7Hby>xexuoD<;R ze$PV5bzo;&nV+ott(KF4;eVo{WetA#Z{G+V+O{?&pR5P0mN@|OKT+NCQWUcj{3n*S zEO4>D$A4nk5qHONsD*#GD0;-1_~pMlA=>gB0`Why>4+|X_;0^&wLASAo!nH-f|D3 z;D5&9E!X0Q|A`eX`vS@Tj8JZvbl0a{mQl4S=$7w1r~wT z`zl+0OO?alhEf%g-+3y^-}1F8#@~vvm6a+^*Af^*Qm(+N8|%wfmRG3+ecH4_hLF_3 zUQ;Grkfpk;cBRUqr>S;%ZQbfxHHe;y%JS+JWi=|Bp6XdDS18~ZtR4HRA=*)@h6>3% zmDGTFDo+4lJ4{31%BO2pU3G;jpbOd2h8XdnBj{)>TZ${R4P|T9NP5e)dlcPG zjg<`*l}oE@k%yxRsHtZ<$7ttjy2sMpP+4BrP=N;#;fC!f;XQ$#CeK$)-_mMWpx~Y7 z#q=$ysavAT=rV?+mS}ffL)o%QXp#B|+Mrl+P-Xc_RpC(tph|+s%A;9IK>1R&Onz$` zk@zY)S5-DNR@WgVUUb!QhD6+2lCN^;UxjGu8nAmzkIo5ID1>VpDwpEWpKfGhWdpCo zt5fK$h8c`yD73G>3i(!)H7*B*=1P-Y1i-6Ym(OP=e#S~^MtWl=CCNHGCh`FQ&Esn%%r44 zQ_Q5KBI{OG!N|wuC#y_!t)1&zd)w9@-L34Sn7htM^!i!N&ArFX0%Q})K|E;fz6bZA zRKE)}J&P;YLBW98+JPP0E6C65iLs?4f7UJwV@bA8!x%a+A;d!vv<7x}lj;~f zTV0F)DjZsN=sZc>4)1W(66({KAA7EvIFbXzJIVj$dBC>L_5Z~j;1p9RuOjdGcRPgk z<^cbHjQWmiqj3HojQyzwAS3-yV5R{`2hY8Mf7k$|;AYJsviLnD@qae>7eu ztvK4Y&4guV`Boh5s6cYEQmr`Ju7Gp1_F~1+&J^5W<>e@hRP^<9bx>!szgxNX2ImIk z=Afnoa^^@!a&pj5vHGx&5sx+K4SM<<$+|&*qi3slB7))iJpRnN?pD_;^{gkkXu~69E4)dGQf7W52-_1owt<6J5KYtP%61hG= zTY`yx@eo25W(DRUqn1U&Ndd@E+7?OYWo_>2>+a~^1Y<_Mm^=&d;xN#V$Ar8-Yk+yk zXqJRoGXP@(4w8VIv%=;fqq)`*5UQKN&>2N^uyrxOTM14v4;dXI9mOeG=GYh`)ln*% zC!EjFK%-jG)2!{1sAz%3Ox$j;<~F&JX_SP#I1NYpMJhVl+8;T6mB9t(A)|#7Xm^%r zf7)V7w8&yF@>rH{9x^&b^5dy2Z{sIA)w%>6U-tlF9x^&j!tL>azIn*#biusmmw}jv zjFt%34+jUPg}lxT#Wq`z${H-Uc%uu&3;U2>1=k|0mT0wAkJ_50^RGq{q_T{C$mj~m zF*l29C(%0VN(hbi6WE809xQFS05S*mA)^ff9G(@j4;gK=zK_6#URL3B2}V*N=SrcS zl(iT8kkKZ=P0rF*5u>ZDKSI)JSvo~)Bt<1zDFz~=Yc0-57JJczdc^3V(yLcw`354R zhe_(zWO?QoqeoazBQy*|((P01b;`FTc20&nS)^akRFhPnn>`lLZpmp-XTZ|Rc? z4K01r5&qIA6`_|tsW5-(lL`)&KB;iM^ht&JLv$sUKB*{g>5~pkS^A_R{iV+UYl5DI zNGa)t$hFV|_R7kiasX5>UUEAR?0-7@4rcv`Iw0<11;sHJ5& zzrzbq)wN6Of=(}hS5z)(f+0J<81?8K7<#lz<0nEm$2}F_JWf-FF&~E=&kwUIJ!EKJ zV=s>1Eny#ESWd@uSP7QT5w2Mb1?5Ipd=6x;m|Kk2(hYNPoHS~Wi|83TUzY2fu86tC z*f`Euay^4Nv0~C7U{{|Q(V+pe*hIo|RU{Nr#U|Sb7iTh>;V9th%ToC|g$_x&i7>xuAz76AsCFjHJdtKYJe^5SjgA+9_WW1l6w zou_;u&K4omxL$0n_~k{Ts@4Q=`(y!9$3JV=5jfEtPuZ;r6#a+Twko=b-idjT<`3{r z7=^B?6J!ae`vSd#RD8SHhPiVDZnN`5b0RcKN+;4%kw-I;mWo=;rWI-yb^wKo)T~^U z&4|-P^cCI17lNkmHgO#%5>w_LoKUkHHTT2I8faa`ws9K0Y=72O#q{>AtV5ZXx0(oQu$9I? zYuCpGUU?tN?q%9T@Uq9V4r7ORHoffhwD)0p+3#70vD^Cs-f8Umv=`+)UB5MTI4cJV zd>Z>g>u}Pdyme(bTvvv9y7Ze_`uqJHZA@xa3j=-+UR@blb!E6wD#JQ@?1xQdhz@6E z*zQ#ZjvV9qbgq8L%5Zc|K1%dcfFDJWl6T?wf{xeVD8$D3tY_hv^(a0i_u^9y&};@Q zbKWjnDD6MaVu0BM z2=VAgNIZw!4=}`6k@&%=aNY>?YyyP%Od*CQNCBie-jKfztkv^8({~)e&w!?+6OK>m zSO-V>qj0Q(ql=D%;P@^b2f%R$9J9%w^xN>g0G~*5xtC5zWq+zA`4>qG0T4;XJVvpR zBY!bfh)v^t$Y7er5W^vX4fF)+6u_|^*Po2b>T2>9gBuCleje^F;?N^Tc07h@kF_R3 zYBl)@L(3+%LetXb)8tnToK37P1TW|hn$n3O_}L-&g(3Le2F@n-h`_yO=GCRtW;Xdb z6M(|Mt{I8Qs`ziADA?j5rf!t1o6;!rRW{p~*C^9^;4fIA)v;Rs8O&V#S-W0BXx#&U z!5+8_8LxZbFWGM%2k%_n%D!Y{`3cd|1%F9)@4>6P;4f3U;IB*SFi z{zY`rA)w{I{YZ4tZv67!ek^)Gsy>ao+d44yaW+NswGnkVs>=VS%8c1j{x43;T1*CS zit5UG$7m$bytejVoR-NGWZiwZz^0t#=#+6@74O}Q&C0_5PV=l8suoVkqUNWgt8-JK zcE?jm+;}gJCiU7n5*NBu0?YON@>JUYeEOB9G$X?5x77|owM;o$6Pz5aMT)T`QxP|6 zj?ALxS&sn_V~{=gkI%Yn-m4LDmsYgRG+h#o33IAv)78OWNBK2q}<_b7Bv6rKvSf=0xtBgmn z)fv0lS&F>Nq`MHWdi@mD6Pvp{wy{4M#$41s|5Y!-BIe{kj&1CJ&cQsy&GL_J?9cDS z-d?T`&<7Is7r#Qt!bEUvV_OypCj}rwXJh``yz+761;vL-bIGp5WVCZB9--&MEKao&J)gO zXkhxWja^_d6So^|%CU_-N0c*o;3R9pRsnq$2bwNh-`gB}oPQyZKvF;rf&$ z6_#>Jl8W+9Nz$PyrzELJ|CGeb-Sv1~V_kbkd*3z{kwX3?au~WHFN@2|>hbJHBNQX+ z%a&BvR8w6v9ap6v&QaD7Qw(09D(K{y+)YKIi0koWRU=eBSC*AmH7~DhsI9DNuHaic z4GQ)^J?TQ5*dkm`lzpTpK(N7F3*E-O!ObT2zySUx_CS>0#2yIuHnF2-K9IhN9V?CJ zqdOVuj>b31PCJivHt$FLa9*L(LWX+z*y4Djgk8(9?S9ylVE(8C&2?(Jo94#ZF~xUzw|yp}JZ7ZZ<0RBT;*J2)El?eV1?V@*kW z?Dzg=(!ZrLZzg$p;zcQ=nTj0~{{V5OBdM$}DaY$zv2)|!h9pDXbMVb)2HXHgo_uI` zDvxsNd>`s^mNwMo6r&(?B4DrhBWSYZM8K}4TV3bErj7-o4V z0`X!QXR^X40`ZB2r9HqDpZqp}F-p1=42E-ZX{iG5M8GZQhzRWr=R3v3yak#N|vbn4x}0RD8dycmbF935wDU*HKXBFPo9HF)NqJ2NB)UA zor|LwDA7=gFr%d?yt;C9Yv20KvZs9!qqTkxiZQa!dl8d92263mhaAT;E^8;_8aoKm zSQnEP`A4A&rAnCBAoh?4PF`TVz&>57ghulculKY>0k&d1niEMgMn6SylF;unhY>ts zeS=gY%@ct%PXy9DNomG)Llck2f=u~ZPctRse0!kJkjwby=A})wUUD zJ+m=}&0c{?g&MAkP6vL1>7%@y+R)b1wh40v8l5w3NLi(pJQ%C(%$Lf{W+Kbj+Ru_g zmW-M!xoYwVnV_JWRe-GkFa3R?^otwYZ;;AcbRGra_-F098iA%<1XSWza9j;X6CF3g zaWx%3h2woVrq+{?zWI+Ed=DKA@gq9O<4riGJ!}@X!HqL)fbjZ0w?h!8v6W_2u%xmm z>&~Z4sGo~ml}bs@YZQhk2P0(%4AS&}n%vkFcB4R(s8 z&#=UQ3;klL^&S>v<`dYC`z7e=x3nC^2v0%ctcR-+GUJ1M^{lbVe0y_$=K$$yS zr87;S34m`4!514iGx}Ns*Y}~d8B1Q@UCTZ0(&dJdoVjCaIPceK;3a_1IX@H)2%^|s z8efmyJ67|n3@!tS;h(kZKfPzS1`hTgv!j1TZp|?z2s22W9+K z0G~6*z**vQE!wb%2`o3Rv#^J0(H?%)%_8 zv@8yC)>~{@ZSc-CW-8y}K=d&29KEbP-d+!8 zIJr20W0dta$0&QpyaS|Xdxs)8J9e|pZV7dT?@a>yw}@b|xgy#Qo%{D0E6%Q3^m%6) zO*}LnXWB9H+Zt+(#Cg(`OjP3b=i&Gg1iywu&A%1s2Z39HyAQ)1i_7D9X zw*1k{Kr?@YHAAGj{^Zh|40}GH)r0UXII$t?V541?zGBd9_!oxIxF63JkK6F29~zRA z!QnE8{Q)&FA;Olu2ny(*n=__Jyag4kr% zhaK2n183DTFb+^CprP($h&$9}XIhameuqXS3`)vcVbvQkw@7P17Vr8Jaa2m@yh28( zYUJBe>3?fwWO@+(CAtIFfQ%QETE;H-e8UT+BY#$-^&pr@zq=7cshTd+5C?$tv(q){Esg?D7Z0V z4U0B)_9M{rjh$W7yN+(}o4&E9_2{Bw>%eyRU> zTiR(B3t4kYv7;S1{%r(x^dkl;a#krjjmZD)wspjHR`Y6L^qfrab1Jmw+-_kW+1Sz5 z3gsi5ET9b2_ODYmtm8FxP`8Q|Sd%~*H+$8w^Q?>Djk@m;*hCUd_NK*La9wQB&bQHj z)pTvCZ^gCZSj_$&NL9ugtV?n6L`avgTT|#V!gQI2F0;9*rmSIEC2u%ZF2f?-jYaIs z5H4#lK7;yIEK8yrbZ~#`1|45Et{EUc$d(c?mLu_nw)Ar&QkomO`q$xdS$1$!(v7~F ziSnpzf+NcDFIq<5cpS22H#e?rTv@q-TQRuV zIO{fY+_DyL9I5!eH0cH33MkfWR`J>N+Bt}7TiwRhZEZ)Xcqu^<0jcx%6k`Y-wzhP1E>1`m>1dzyd>nQ0JOYXtr`fLd6%1giP72e8;wS zphz-4qKtjV;?Bf+EQVO@;>G4K{DbI6I(d6YDsN&6OI*TZw{E@4%{Zhq5-`X(bg9Rn zlMFHrBLf#V^#a{EXGJSR$V%9$rCa4lr>Z?J>KR#P2P@%jTveC0kN5pX|A>LfPGycE z9i+tonmLvwlAEKK^qGaMsRdykeOOIrj{6e>d#mZpVjVubn$Da^SlVhjb22044UP8Z zqmlnx^^UYPe;>qR&A@_q@XM&^*8G3KKLi@`uo2pp6GO3q_P9O6qDa$_XHl$odI;T6=gh)@9?92Ny6n#i{7o4Y0K#(EEK+G9rG6Z@z#<8!m&Jfp((wn8{I> zmkozCSF=awW_R0$%B|>CJMr*@ePD#O!r}9Z`72v{pjk$kcvrP{^!pUxLhIuNq}I73 z7M7eY=OTc;?CFv;4-b`&w!<`*!g@VF7AW#(?fM)+M@YKIGTrB3bRLO4Y9y+Vs&Nxv z#ANX!GhU3QrrBuPE*h;3wS{BBW;ZnCV0UmLBdR|^PkQS8i1x?+wT@^aBRUg|RX9AB z{c;Lm&0zSeO!!0m@U)z&!_Q#&FA;u>SGQ&|*XOdSCu&)$eO@nv zS78zr(@+X+7 zFVh`P9@VPb*PE77#U$Qp0v@TuVZwC<80#cf(OCy3F^m zni#glgk9!`<%N?G(zKe`v{oamsaLC5ueQTqbSx0Zn2;zD`LotGBV^$jK>d>OO(4-$ zLj)l-(IGyp_g4Rtn;9$ z3vA4*CgS-s|6qaXQPgm;(Tm?smbChJ0p~GrH z{;XZc_!1pOi5>yFF&p`es@25+3t#gj?52c0@P_$oL+;AjM%vd6^Pmjw_nB`a^Xq+P zCz9D4Y0PxTcr#g*oT3x^1GxET?JB~oUgzA+WHsh>ucqG2#&{jP6WQ?|WCAW`F5NQe zd4NtXd>r2yZy>{V!*M4ZlZoDkx6BXt16Bne!J+oS&Z@c;-hC2q{E?2Ka18&W$^UN} z&Zm&`<)>nuDfxdh@T!Po$EAi~H~{>!uDFdv#{%^lD@*68YgIkjTH4&h7^@NW{ob@z`BU>Z#WnO00Y2?<~?WV;&(L zv+8X+m~&ZwLidtRKaJTojafF0IW~>CHH|riCCyzX3)pR41HR}9XpU|AR|ft7s^cL^bn417}MhOb;}= z>yakPadm^PYPU(PH36=~e35_Fu66{~RqZxbwOPmo-6{TBw9M!s=6IZ?kHl{}d?%-tkP7sah!{{n24{S#M98@n7D3+lmq`)qG3oy(j zaL}%U3-tGddX&wb=pKIRAn7~z0DQE}GVx$0N1;CeQo;s*FK4^7$2*=4RBveDe!`~O%>Pz$7E7S+jt(neOS=@z5@pf`y@J8;J4GkLjM8|>7MdW)%**w zwPam>4YnGjhMxQ`vQ%p5Ohe$+JL`(4NW>a?4Tz+9{DRcNuG3K0lihWH_1Nw4*`1fp z?gwMB*cW!0?-_P8;LwqmeoIT24*>tHOILW*2Yb|gq@LPtC_ORdz9pN-PSUY?+yjT? z-MDnxf7dh)GV-!%{0wokZeqV-MzeuGEwF=WziaxD2FAMmc0fBl$H>NJ6vIDw1kGrw zK~6G=0nKP;qoGJ?8Z+XiVl?P*Y%rse2BsSj8|tyZM%^xa_hq%4EwejbL6Di|Z`qJe zG3>J>hmps-O53`-a7d$T@#q^Fn5&!pg3S<^)!Hw02L#5r)P1A5$eA?ue|<-T=W+iZ zwllVylvkNbGpGnlNuy=wP~DAsbK@~r`!|~$POnEe-9cvBZrWbQf4sF3ai=i+|Mdn& zXptT<`xSQTYCUb=BBXcMM+w3vEd)1vU+%U{DhD#kIw1?*XvPq9jxn>~jb_aPR=l#{ zjSiweqT;TzgjS?tr!sMRXC-z{l5V}T5<9nSgUf~!|jIw%v{>h-g%UA zj}V{AT%x_r;&l;nyYLPIx-B+A8O;qVYnsa&s#jK*m(?^k!tN5!_OymUiF?@S=g>ql zS8juC0{8IIg$SWC%dyec*VVHG2mdR3TGzK#i=7$w2tnIGw_|GG+R%2^IGqky%Jo(5Q9W;qQhbkZJ(L97!*5mL%q zlJ0u(PTIRP+>cT229ao5W+QcRk!<_|Yu3Tw&1Ic64hubXAd^CkVIz z(zSa@JaKeA(~ja|wkPWUP1(2`M_&%HBJL{)k=Prda!-=di&j<_4T}0K zD$gr2H41OqQ1TonQz&lJT zkz^(W0L?d#KsT4s=f*ZyQU^gLbPg&f#4a(0(K>YKMCeU`HCz!Gf;Y?B%Dc64gc{_SM<+wrg_~z~Cp?N!@ zpm{s(fO$LZfO$J1fq6R(fO$Isz^L6Y4S_44E^Xe9F5kQzJ!0ODj*xjfdOh=Ybf=iN zBfyxq(@t&Pj&9Gq9o^Xc)#mN!3C!Ek=kK~Mrcax?s*(SsAHl16DNU2Sb3+^DS$MEGiJ15sLSZ6G|Pw&q`j&R%g6Vn$shr}7s_UnJ(KC*>@qKZfw%LVygJ zA^O)$>a)+XPRl@xrlMlzk4~i)23^sP$_2xdJc9wBJ&<66cv zDW-SynP*lVN0bs(un3{8_9Q$Gwd#h?5kG|-@eU%`4KGR5$cOQvZ&V|22{oG3W4>;$ znbRyMidDkcV6R!c{$8`p0V8fEXbS1xrx^1>Sg77b9y50l233?e;{0{>&el?M6l;*Buv02{Q-AyZe z&z78~*O04qJc#HWFqp&=vYurLodM>P*BPn{u!i}qjsPl24Qk4 z_Eo08mnxF%mCUfg+&aSf0Yc5(yu7Wav#nz`&J|kzg&|vto$6U6(#1}n6nl;u%`he0 z>=*0eG>>3i_MwSm4sxG=FsqIgEeqsw7RYyzj9I?`w=WFcDO~VhIXoL{#ZLgf6Zn1K zg5xDP)NE4D{I)I!e=qjNWgd0x14BIp4mF!uw!~2TJD%5m4C>N!@P222b`?U+xde`c zbJb3*_)%16!e56_$liogbfLzmqRj^NprG*1?Q{<{{Vs#L9RJrxK$G=B7Qa?v@YnlUd=r-1%;Gng#pfVZlEqbq z?p9{;A5TCulEt?IFIoIsIMgh585w8j7+)vlyQ9Eu-cEq$(?91LxDw78CW99I%FrSc z4QnKAfpVpBcm!jbKI>S%xidq%*U7t5i|BfnDjruqR$)VC-nr{xZvkC`@=MAhrfGzyk!0tocp6;Hdxl($mQb@#NNrdT)*mW+p{)B$5(2zcZ zA%K6@uG*p4?&JUk3XU72|Av&cuIDPV8CQ0&`?*-sa}D5S9I)W$h&B8pG(`?t@N?9n z1{V^)M2NQoS-yqQmP@qGj#Ez7nNcB`q5cl-A&xjlAohf_)l|KOcNy^{f9$h$vZ_!= znJjFs73CS&VF7H~Bm-meY0aOsC!#OC)WBI6Z_sevY;}F~B9;1hy;mO>-ef{CXN$(1 zqeXZ;h_3Qm1{T3aY^?IUu&?MI;~R-&vDZEUUtFukMQg-j@2Hx9`@E0=w|UWT>#Mxe z-!NfPnvCvQQba7d$aGV>n`X{QH=V6UvkaGt&bDW;_EgI{4ZvkGz@I8*qO_8e41+8g zs4kqVQ&;O(h6kV^wn)nDVvFu$P)-L5k4uF|*2mC?S`WtinV^MmTi00M1MR+B;oeLF zb~qlvDJ1x|brA{JF< z$*~eh&vtR6`0jvDw~L$nc2V?@;ZcH+UOj)xz$!wpQQNh&YXaE9?;DtiX0)0~H~NRA(Z67%d_<%?=u=P1M*}Hm?9j14AH-fX-@x7pU<=PQFiKSX zs_~d)sr`fbS4hfNC6>bP>IgXF)LHpsN-16FtI}(n0=bx%uZxt?&pavL2&6pEFgXE1 zy}Z1{z_y2ArRVF&z8An2b{d%ErS3nuWWqay65lBXeLuF9w0tXZ)Q6(R0PuyyCDlSm zvovTU29)rPNt>s)6R4XL3W zo9l(E5z7Ih{T>lNML0+{)b$HHN7{e5Navz-<;;zQv)Odz)9y3b#hGj#8Z}D8?YFYN z!rutaTj!~1Plib5c_b2scAn6As+J(B{5Z0U{Y)&vATXCEezw$!iR0S z%DNzu_)31w| z)LWzqEjC0?>uQQFDLKM)Nt$4*WtmQWn*{g^{L7)8bDa22o_1I$mS1QgWNowXn+Cz| zvgirp`A}12^(yD}>DmnXIJIz(!Lq2Pe;8tjOp6?wbpe(hTJ$a0>4xa%+8Ak6;l(AMz&p*UP3iAioBS9LG!CcO=AV@Jsca0!|5MjW^R+ zVxnTjD!STu?n6dFz_hg7=V4jx{$)IG?TvK$L6_(Rqzpn_p#?F^bmOzsv7EBWSe~Iq zGsQY41=U5#Ha^^P4nY#heWBE@c z#LOt0Hx9QYg0tb1d?Me3Q)Tk$AbHgGIr~);|H5;OL-OrD<9P=%bGic!r=l+m%mtr; zc{%FRpb1Yq)OeU%%QbnpNq90yj!iHEsp&U_LLmYjLg#Txh#-$;_o9XyP_2EP0Ge=KZ_~|ZB=1iw3K7c6 z5IZKys-LbYO+#DJ4s*B|qIl(uhY42WpCNF2>>JfoJf{^=Cyd7i*8i?Xy3s_3rG$0=g*N)@riyI-zBCrK zV=~q!X~(yb@h<}T^*ZYQ@oi)}t@;c&zICAZsST(^4j@5_>N;6FTd3pC1JZRI>Hp*7 z-c(I?Va+K78J$IgU=jD{;2v?;lIeeYC>(KLXRvgWEYT+cjk)?*6$Zg?hu5i>Lsk_X zZlm5r+_wm8Dz7SQP|;DO2Z8pD9xntgz786Ioa;tUrhNL0H+rhL>owxr2MhINQZHGH zUDoK?!p$hxGp~H*ddgvYht*EKCg1*DVX&GEY7A@#VNShK%HMgrQ1IPWP#ECF1UfwD zP|+)?x1Dy{opQV#aYZKoR3tW2iqt=bj+IEk1jo>^SwbLj$*D^0fqYC9&AD{^pMOGx zamg-R?`8q&djRnQtA&`=8dZpEoXqPM1dX`I;TxqhUQ=H#XE^amRv-QKntYjcxezXu z?+@{f(g`#UOAyMsmOgU;9zV|#A-uDt_%5rFXr@UH%;SF)D^H>82k|#8rpk5WA6ert zWGBwW5E%cv#f()6UQLaEEKGRyApWVf)Tj9@O!E&zgH!jE%L8uwZ`N@LlKCa%$m&<| ze@ZNa+ORVd|J-^RP>7cjB>sg&g4m+=?S5=AJ0wwDJR(uTe!-{72-9R5nv4M#A>t8x z5c<%}?FdMbvLqTUQnvk`h?I5*BAz4BWH&Es!V68g?$D#aAO}|&T4yOY$ttXU`zkk& zwL2oX*~%S8Urcw zLp1jg@u1FV@8J&#*>(7aR6tTSKhV5^9un6E9-8Har}(D{W@|1#Sva*7fozq_DmKdV zQ;hil3~jD!GzWJ)yDC!`#GfB^7N`elHU6@AauZXq{}}(hFiYy#FZE(SS;f<$jlVK#9I$EPRIVvgyW;PSIuAO*TA=rZ zxk`vYe-V!n=mYT>fj$(E5$LbtF#`Qf3zWnSksjW5uZJqfiq<2$aF^txQR|Uq7o?)v zJBj+cpe_QcAM@T7t-ZLF^0B}!PHr)loJ3P3{>dnIaF-^xG_=7=(6Lza#Xl9$Woc<< z+Tx#$x(%szR_jNzqSt+ju&6EagjVziaTHLtubw~^hUimoA}jK~K-NZ|V($!cp8%kb zfyF?BZ+6x4%C!>Y>3rL5>hL4Z@yr(t0b)c*ptuk8?ho)M&8|Je$%0oQ+|UJShc zLvZT#pLqzKUA4Nlg2E(*Qwd#!NeuUd0Zt``-zvgTr9B%82=d?!4F0VBJpegdRpJnK zdMam|N*qcT;?N|C!|nvdFgGJViKTpwQP0RI(DG@os8M7L*Rtii8N+6QH1lnQEAZ4a zGDfmBAmJh1iNXwdEFs5N&&Wt}Y*0Qx^UWjB9nR=;bBuaM#_0P1EJ#t$$QZ+DQM#ch zGRFJ>u!u{{P$YXr<1$r}`CTWUbI#3MVD>5Ve1}=4lAbk!%nO`fB9mRzyH?x|gldNK z0~A?qvcvc-~S2D>iV^1mF z6~z!&%KcQ)uaE7&WTf3Qz;{AP6dZsWNkSh97A)Keuc0wDu;P+lx)WM z>M3MBSlJg~NE{8#0i&Kmr&dp)i|Q%z3-uKKQawd}p`OBDs;BT*tEbSV)l&rKtEbRs z)Ki2+)Klp4)l=y4)l=y4)l=x9dWuj`Jw-d9o}wL4PZ1KRr)U7wQv^Wu6b+$z3SC+~ zg)VOjF`OPzPoX2Eov>m%2e zq@F@=pq>))`RXZzh1FByRTY)1L{DVMc1sVzjrAyafw4xFslp-OwP=7L5y!AQS|Boj3lfQMXUu}3OU@pQgJc3R)(Ot5}0 z2wHcDxI_kI6Oi3O7VtBOuDa;7-p@iVb2OV+FYjGAvak2Vc687|Hz1r43s$lE}jm# z(c)|gDz1A?ehRZ8H(76ey?p7UXCYcl)DR$aJ#^^W2Lbl_(xHc(glTrQ_3r*J(m$|yz!#^{V* z4TNfPNKsG3)0Z4>xtgKNb9zvKk)*(biWewg| zp5>R8DWq_X+hJY5my(hvBB?-KQ3eYN0}4{VAX!s}{4Vrj_3~SAt5D~W*^Bpz^heQ_ z0fON*%=Yef>N)Frbgi`zN0kAW^6L6(Tmta=sJ&o?c@6IQBu|BxtMKs*D(d7ld? zgHq}7PUU?ipsZx7f#E#cW@56FzJcMqs6cX(sRoAgTmk1M*VXnPjoS(v+c)+1;8t@N zuEXVJ3U08UgF&C!*1Nu^y&Lx@RAJswyAgN5bROnO2$P2+#DhGn?A#!RPs+^OdU=I{ zu@g(M|ByFXJWg^8-b&^gzOAnj_j^>{G@DtD%#~RQZ?@#k6jJ0~LmT$adpE1R*#e0t z*EQl{md$TsOxT%Z)riMR#IawJS0^4ju`fLh;&Bq|F@WT)5>F(tjGndPi6$L_m}E0(3l3YR-kA5ydBRD0rZFI!F%aZR?IB_1oW zgE?`ol%1WplQC}>OeAp(lX$*(qKV_Mp3A#PJTYAlE)h>WaTxRHO7WobdxfL&u9cYm z{P;mQKW^~zV>+aZjzdZ!?mRlVgoVjL|G^*qtf~F+-8eDJ@$6&E{)P7W_OS_zXk#1A z#y<9w<1v%V!AS_R1eT`k&+7ol^#NLi*8YMU28GEK``9F$6o3q+ZIN_da&zceQ`pBQ z@!~MhkjI3)KDjsh*bK8~0LBCyBmp-kp*{oK8+gQe{W=Bv*e{HOeQW|lmQ(G)))27T zN-zw7rP#;j=JhE_t*UM~=LzRCG;lBWv6+e64VJ1AZ9Tmv;Xp*#i-K7049tN?=U~_ro-K@<#P zb9Aprh7DpfIct(3gV>j16X!5B?q?ixf91S_tQb#siM`2U^Pda~wOx}DY z?IqJxu-NEM1!)`IsW5G$I~C^H==N3;#zr^g%o`J_z^z@M-m}qNWY%7?EhR6Rra{bk zxZZ(2DHZA2=uU-(Y;>n1d>h@V2yLS~73SOMP6czTbSblFYbspZ=uU;nl#fdn+^jn` z73JCJPKRQ~tc_qJNM9<_x6$q8uGeat&9j(#X4()bDh%@3Un+%OGWE*9$C-OY1K^>T zOb6gXFPRR&VSbL6Z~e8lA5Ty){*v3r`S}|2>#v_aeL+VjuRHSS-jbL4lIZ}6QeHCM zJJyqAFLDoj$<&)!1lN_qvx}^}OCovuV0JNz(}v4LaFy82X~Pxbi6jnXuW_|B30K9< zxb7zyBNj|n=G_vR4K6qq!*@ajKE?b1a1eex5xhWZao$fO6EPGfHgnc>x40FCQeM!_ zyD!52(agvmh;Xwek(4`3c@K#%BXJjlJtFdDY5ATM`EqqKo{6v-Cv`G@C!T^NbvQR5stKz66Y`%-iZ7a`$Z**_v!hQ1fQ2o%RZI2Co&x=*dIyc(2~od z-X8$HCGXYy&^0>g+j63u0eGdFevNJ*JgvG10sL!p1H=jh2 z(Z<^BTDp}s)}}q28FMTT8Ed1VwPE8pN69gh8a1q#Gzb`a$aL65nFA z-vnVU6Z0Aza-?giY@G_6L6>u)k^@zv{0h=2Jp=7k`ISt1B*(iNn7@>MUJWFhh`R`r z-H6Ls#zd)#_Eu{nIE`*`kZQaVc+UoLDFz(#dh&4Y;4HZfKmQin? zW#vymjc4Vv&z5l$?PFe zqnd-B+0r@VW9l05Fhgwx4xNOEJ9~B-iRrqzOBzW-neEPs>PFrNFKfUkcZ(=cb{mYw?-@9yni#%@-*zU#ejAS)7J3!>kdyLY<-}orxutbP)N|ev70RK@+H= zZZ#g8s8lEUo~GK0%B9t{5b)&D9zj!WFnB5-x~5(o?0fbtDVePreD5mQU?@{9zJIQ2 z_1*K-y1?B$s~Hci*OcM#L9O?}E6UcW4QiBs9h3!@e~>#7<>g-orAuE2rOUexI{5@t z#r%VZf^-Vo$2d5O`9bApeb3f<_a*s_rvfPLXr;8Hyk{_SNZ-LnP0&&fx8FSbIA|dF$YN<@?~9f$tiffv&4$BeG7KQv^Xy^}a)nIaf%Y3X^DRiqtG0UYOE=Lz zy9Q*1{_2K(kFvilRDf>0&&!BuEX>4|zJL$F+$(YWyvjKa3Ir3h5ery#gdt`)>>|u4m zLn(zSFS zz)D}tg)$l^TZ(iHi#=d5UBE2GPsIHWT3W=N=25khiXQ;E5`}pUcqXv2d*Gwt7LKgq z#cZv`oRJlOm!osUJ;_6}Zimp11MAUT?$NMoygC3!a+zb(l*F?z3BknsM zB`ds$>P40WK;&h8*BI#lBkl|j!zvzNWMT!DRUVp^UZXkP1!j|nVO7@{b~{>r!~7c_ z4J*E;k!&*P?*lr4HB?dso)5zvaoLYgV6F4|@R#8h=~?HbP>VSsD&`2`3HqK#Q$!j@ zP)rxtZHH75Hy0j`1GJz`z2)ZC?smUFy~;V}{23S-aQN=@(53PYMq77!*{!-crlqp4 z)e{=0?_v<;=HQ}E2#32C{R~`?qs_G*`(tR4$3*6?y5X?NzMri;I7YOU*()g_?kTSPR>bd;cm%e z=j5EsST^TPqx+Ozz`OIV#(3v^gYK<)4`NHz`6k_`oIh^amjU_@Kdxr|5{(@sOyv~_NRN`$kE5xL4!9H6)Z z&kmit-ht4g`OX*)|KxPnoXlG(z-mmBF*^>^)i+>i0i7)zHhW;6TAJXA6rcppNCEl5 zGt)$rR{*um5Ox91gKKB`5>jVCpQKmU)?>cz2^qjKizmVpH9+_$&#F+DoE#0xFj(j~ zk1pI7J;br>A|7MDVR1!*Vvlnniz4TWYW;i7Uv#6o6+q&Qr_5f5bHHHP;rM zr&|ehRPH>C7$or2hpAyloc7E2WT^3h<1s!Idisq^%&BbnG~M|vcX)?Qa$flgv^luX zgUa>lIUFZ)(9Nz>&TB-tc~@j1mtJS*EPZFFpL>JqGRZuiaXEj;n9X!xpBgDy&sF5c z{!UCFyI@U)^JeFd6uuCREegVD33_&13_$oouYWfa2r0VysPo)gpum zDwA^l{3+ehX%H>kCpd30drP9z2F`t*JsjbyqAK@1kTAHE%2*_p^?j%xkvU?49#O6{ z%vxA#cCDOzvs=!QPS2&3Qy?%`O-;+H&|FKMVLKzOTfio1^2LuyIit*a-v{}eM@tZQ zA8xYC{yc^gn!R(zSPy^~uA$_9fi%!<(jogDPX_*>o=o0|qo<(t&Lpd0KS;wRNh_W& z;GHXHvNZ|Q1eN%Lg)~L>21=4_wz!A55%;Q`sTQjd&e3!y3_+#|1czvVv~7hIe^xEs z;-*`iaaF0QW;pNY>N={w8|y4*mUSuPmPL}YuSE@6wGW=-foxsf%9(9Z6*gi`m-#}e zB@+hhnQ*Gxk3{Mxi=o z*82z>aX-R$%HwFK@i`cI{(^Xme}cuFG9jybS9fihQwqHRu@ZrR6;?4QF|);Y3fs(L z2IOkDxB@;eU}IZfe|JUuvbH`mP8{1?#(0-mZ4&$_2B$*pnGAjzqAb3dJgB%_EQ;7h z0>h{hr^ywv0->2fa;ma!5l(lI69svKoXAqb7Y{?TPm?Ch#5?36t7_|?!b;6Gtj5Ek zS&@qtk3tncFpw#d=m} zP&gm*kX!M|tc>?iJo#MgxkBv9c@^7aX`{72f=1jW_zI_kJx*Q#WZ4QFlD2MYlRR2w z9W4QR8GyBS2LnuI`;#U>ef?s7yzupS)+EeewRN*FxZPv$yRTu8%B8EfPaE0{^IBv5 zQ+TNbMwl^h=yDM`cv+yBHw081`;WDC6_v_4T-0Idr@c(iA8{EpUhjjCunr)gp%Th@ zwK9iNPO}cG_1=I{PK(t9su^R^BxFz7*=aQ|#PqASOV|7IuFg*BS^-OkSO&5bZ4M7( zpr2^ddPSIxY1(CcL#efc1eo7o;%Hd3(x_)0_Df)vv_~|@45qfLud=hNf79mrt}W>H zqv_x!&|KWoz5yeD%%H0J*VUq-wryD11(DmjJGQB~K~;Cwv~6l#zYQdq7ms5aovW?m znJcDuUeS!o(TuAYkb%|mht`=$Jhl+)|M_fTMT@Kdjqnfy+0ycfib=a&C~Y zshk_z*U7zMpntR%w9bv@>I$itH(Ig%8F?1I68RK3biChTn+O`#P)^)@rMd9jE#dsy zdI-Tpr^)$^CF>ticXOT)kJf2&o)nMPX>y(tkJf2&o)(YRX>y(skJf2&o)wSQX>xum z9<9^lJSQF;*42NlV9xW_o02*vYJ4NciiGom)w0MF^+jQ!^^BaC#H00$oR`Ihht@N4 zelHlUXXLyh9<68Oyeb~8XXHT74>LHeXXLyt9#jCv>bzmS0|~UGDf*w`Yy{PJAsY5z zK0FE%&RfDxC7$5IeUEso^*NVFzJ9w=N}L5%!C)uwSMLtF5EhzOc%co0EaCmH_Z{u3jj3`nX&|uaffC1jeCYDXg4I zo0IHFvRwBa=%E6QMpFz+ZI=JAWMelT+QrmIy!nP#buT*vr^-GXeSU!fdTNDEwWN7? z5-W3D=&#$zv9KOD{ISG4NJJW$G<_mgFpYQ}rXQH)HapF+Y8=zytg!!uG`SJyV0+wR zrDituuA4Qh1cRQw5NnMU5RO~$rj-GW5zuUcRvOS~Rno~lohI!cjh+WLY0>b#g><8e zICb`N#E{jGU7mWO%X|_!h!@0C=$zFe2qZexewh;KOs(!k;@D$%ZYt|*?1x+OtFDJv zU(~s-HO9MnaNMv$^s}2Q*EFx% z*F3l#an{=7%1p8j(aCCs*g9GNDHo?j(mGV~?0*b|N&Pze8APhv<9dlzCB0_5L8m2& zjXmu~13h3#=kO_N8DfCPFJC4FQ9A+Vtxt@MpE_Bp5M&_JvE5w7o=tBD$ zIFepu*w7LQG^83$Xs0xxND>OX?ML??9a7?TF4nz7QrP1F2fJHB%<%xnk5Uz@>v=uN zFK%pf*&iW7Y_KtY*SXxTDrcX??(Yf-trFSvKuHuW*-C;h4u+hoBrY3=VH?`EVl)?T zM6@uRYqT7==dUBh=2TOCbA4I)a!z!vwf}*rJX|n%nv46+bvAVee2Kr7V0C*Z^0c{( zTdd434*l2LyCHqVeFR^bQoaO7@dkcm0FIkLrVLm1w08DlRm-3^+W(TER)q;V84ewk zIZ~Ww<0B*g-yvS{`8b|LBD4%kJNkP!dotWEGWaOkVFmlU>_fm0whlb@T^@U%3uZuN zy{Ja*u&BDhpYJp9z4lHCe7P6+PA{+|tN2?GFwDku$YmW^jdg+>7Le>)$ZEI!2Vu3x zWA(YuiYW|p3A%a)eApgY$pq|!uVgLF2nSiK1>vxjmQ!JloM>u$w7BMtNA1Y>H+HY^ z-RAM#>GNeC>$L}02Vq9c>-w&a_Vu!ud)B^FSls8ac+F?QQV*4y+*bCA2Kgbkt@OgLWq8>bNGT#&g_({VOZgtW z?~O5xx$&k*;7KTSeoZi?2;*hSdB^^t#B_@n(_@Uuujs{`diohAY`p6Ef&E7b`L-7_ zzAPoAD5%3{ONjeO3{%I*ET`%XE|RAqezuW+&DNw#V?Ffc&w&9FE2?$ z9OjKDrleMvF$-*j!}dR>c{zLGrL{PZ(5t+$&d?eRFg_Sor=d>}1}sGnf*~cKz;06e z(SEJK&=Q~;+Hls~8*CO}p%);LVDtzdb2{|=XB19*8|6AS{3!(Hj+&;j>u!()!R)Y*u3 zi&+?Lpg7AMIeJgxJzaXM#EUsv`}&?P?5&E|P1d${!grAPvQ#{UqqAH(f_Qx@w8q(i zXrOL|Z@i{`-E!`ea4Xs@li0P?I(G=oz4%I>{98DRX|pD@Q{e|*g=-;ZuvzK+MFRdE z-w9ta(DC>vo)`3EX4UR(IjUQoHO`beB$o&9dbq<(bgd)9axy4d=Md-n=&4;U%s5B( z=2yx&)Zt7l7xQv6Q^K0Y;S8%FDgB#sxKjaNVG_yPTibJva5!O_MEuv)e5cvryr_gU zp$^MwaX81BNAQ3;;IulN$1El?RP~*84yPei0uBZV<*au&x2VSy+sg>$Y;ZVDSd*02 zHn4d+Z4RdaEgJ84zi5S=lVQ!W(fJ1On>C(7C})$y@w_|fHv?z0!*O~mAiY{r<+M8- zd{0UKn?A!i(m4_|XOJeGyrZ0p0NyU(aPm4Fj-3}LgJ$L&?Qj&lN=K|yr<_h_5rEfY zmW~5xOzm;>T-MMC^Ack30PhWR3h!n(Tb#>SZRC!jvsG-WsHDDg$rJf)j^5`$h2GGQ z-WZ_c1QY|2R8!NGo#O?Jg$&}WXf9ic`}0ehR#rAbW5Zd7C`6ES#IJ#fxPoqKEL(;h z+mkh$#m*_tod-j(CT>PUbHjNCq$)9v`%>Q&kBuV6DRF}wEHByC*XAuiPc<^v$tm(c z{I^U3mg=MAfdr>%8N}#>^KFqM!)$WY;6<)-oW@~fLKCfpf&!|?=|Vrvkcd=E`uqCu z%2jJO&}RsGMi?!7FB*HMU`xVSn(D%)81`}y`YgfkYw$WvVeV%OzBC0NVtlW+v*3BiI?f=~?K5&ZtC_>?HN3&jB{mv!k8l&Tzq=1Ntmr%?n{k{!;@FK|ox?zZM@e+G)3p%mc@JVI^&zDY-6qM4cpy?~Pz)Pp@_sFD1`Fkn zh0+a!Nv**dNt0=9TZQ;1LYx(Xl2${rDeWE3HNLdUxzmWs?uX{NW_ch_RIHud!e1r;EEu?0_!AmOQi+lGVLs9qp}XBD)-J zPddpZ?R`tz+d44tU9JRLf%Q_gk0T^)EvUOC?rSWdF4wYRn(ddAN81(2)zn(HKGgP9QBA^$++ z9fGc%i5ImfY@rA+sY~#Ol2yZ!O&IQaE4Sj5{RU$gOCUH*5pPklrfU;l@RO=_qr-E= zNj{7fOT(rm>o;%f^$Bkh!jb?;N)0Sc_G8;as^C1`vadp!Nz2Aoc6ymQ_eo_iqfw}^ zfp{9>A};HSIT1pOt>7%G43D%!pR5n+LzqO}@BC8;)haWIO2VO+?myw!kQNwBXj6zG zA8<-R8gUokJE4-HPLB=@P~X$m-P(i0Ha0^B+wB}B!H&UKW^Jc2sO%Nc1%{k)g`?#} zX#krCogWLEyF50Jk`05VghhH+w08F6<~{YBdUPeD7!NsrlklH;;Rmnw#NbL-W{~Ne z%y1nr`MEF&%Zm75DG*adJ%9(K52umVvnV)LQJ7yiCnNTVdm6rSgnS8wVPcA3Kp&bS z2WB+jZH7atrU-{eoCk%&qvXKp>C5CGxysdhItSBnGww&z1d}=v!aue*yjPur=_XnI za&M%e=>%zhHGl>Q3ePD>^!NZGnLlHq*)N-lzjkg}!~D7fUrFu5a7b!H36&i7M^v)? zjq_&-_MR6kV=aPlq$|D)ji6XIIHd}WKOCFWxz5~YDswnxF`b$Gz74g&!mGy!a z;Y5lc+4h3)-cRCuQR3V$o1(p#NmW3``LYCAaHQu_b7Mn5P@9m%ybDhA*LNHx3DB_l z(DeeEx?Xd5Fk#gvs7baUc)$GM1Wj))FprlvBxvDw0qSa_7 zWsGx=CEpHRHgga2>PAPXY&wIoApryEvhZujdhXJN*3i~#aY@p4@{{s;?f+2r9dK1w z@Bg0<7ZjYh(o&Pu%F@a*7Y%XYM($1In$-mX1w=(aaiL^Oo7nhfMMbt84I7$mOieRQ z)5>gVwlpoZrD^5={fzUupAU%s{=8nm8PD^a_j%59=I4ysR6boFp~NJTP=3o~QZ##N zi`9j)(bbTlqXJ>v?%wEVx2n%#e}dSaRKE~#qzlB-hiSNJBGz@AxQQknmT-1`+E8@ezb#8?}Drw7s~Z~%V)PUD2w8bACKqj zqGb&W-0N7>9kNX0~I{6MC>PlxI z?O6@z5MWi?mH>N%1hai*uWvyWjsWI z2J&!3Z>$w@H?=dq5+Lq^M-wYQASkgTMMzj9tZmDuXs;m{C7jq;3USIi3EykVk;}^GPt{Mpxo@2Qk?DRX+P_!C*CEc zNNQ_2OLv2S7(^ENSXNytidYlO09MYn*{{?#uYR-w3;o#T2SL}H3-A>#z|W&>Ew~k2 zaDD#KheG<|$-tNseeskNz3giBBWtl9k*8`dVqqli>?}OWdJIu^pnomchV4&mjDOYu z1EoMdHoC_+HjkM)tE@JTtS2B#pxM#XNVl(LTfKSUBOLkgi;eksc-&{Wits?~YX^ZC z6F~=p9Ieex&qEg#&1okqW1N$A+*p%#G^hO*rA-H7z(Gqr(X~z5btLWl8q%(Xw4+a) zt$8sMJQ$Cq24sw~_JbMo5=x+lHmf zcv2#*ew22ZiYMcuAG`byg!X?4e^9h<(?7p80A1|_i~vmA;65#BALP+^g~~yN;vc&_ zI1b-Pc!(nuc3>de-@zCvWZOTGi&*1=)*xgEE#ow_<@}l2Z8?j19lb!o6T5p--v4Co{$FYPEE z%O;ddy+G%znI4vHGA$IyG*2C)>eJK_na-h(JgPn&T(pDM02;fWB*T>rX(*Gd;xQsq z@f#psGAtAe093SE*-*49*_GIhPIljG7@pFtX~^@2L6WrFM%VG-pyiq>)2W z8?77h5!QYLA@)(xcG$!oM`-`+@CT-vP5=CE@$xiZTM@qj(IQ>~tbW8CS54%8g!X@v zWChslb%a@M!j{WoJ1c(&M_1Ewjjn{^n4_y)9)WhLV@y)w^Wc}pEssZ~eS#`dT4294 zYgmh+I;dc%%$#n_eTAewnNg)xLv`+WgGwl#CKOy7Co`&V98?nDye{JDvPzYh48Nc( z6qNH$in6ag3T-efzyj- zoGNQP2N_DG@?GH+W4}D3Frm1-9+Kvoe6SJKtRHnIf#Vfdk4``M%22#L3E4}jf7ti9d{x6M-W}1 z;?>AJh)&krwQNl7Q9?CPb0-)z3B~S zp; z<5|wftK{c=NPLsVC@)?dT;l4zmU8dK_(>q%@H6;VdGO;gL@Jfbxl{}dXJWEuqAwnx zj=(otS;?VMqxSZ)!^|_rX~+YR-I~JQ2+5RPeyqThjZhQ-vy@Fk9)LXF#NSj-$8O!)n=0>(WTnw_w?vWV+$bZdRA3B)$dD%^A$=rDyPZ zX?`;lGZr$MGt~RxVQXz$WAfF97vUr143wnYcpeVZw6aei_LMMbsInDcr$s;qL5e_@#s0%H3H7{L+ej%tOL@%}q_()+ju- z-Ok;cj5j~wl(`c0Lt$iN2{xEjs(GEY6A0E^Yb%O!UtM!!a2Uj;x_3DP6`D|3 zb(5wT)d@wj7DjdNvg(rH7u8j=>XySVs$0#fYjvhk-Fq(8t#PStZCG`4kXVebvs-nq zDWXH9y7wFP1_i5b66Cs6N71ahdlAm6`v4B8uJcnTQ=LiTWU3<&th%%D@D<#y;iY?$ zzl&k#tN4wMt*x4B6ebkso@H9;T|BP5f&4t_-_?kk+DiCEVc)XC2DUT`+v8H$cP@o} zA6D1~Bo^a~bt`PPB8qDYh5gv502HjS2O-y`Fp6e{y@7C6*kL%(O8w(f*ppxm+nY&- zm1aGx!;L=iPm6}p;$dAP$mpkxi{A(#n7-6AR5*Da`Jx-7sVy;K_Z0$_uam zlwy1$)mJEnwK6t%Ach8hx00U+eg|S`;P)>4Tos8C{n3Xy=oq7tWzgYme3gdtmSFOx z2H?gmLweKX;B)If2Ay9G^tsavXrVajfZoTTFKw+Li7>{u)quRWW{`%4L6(IDuB&1Cj=^uO2L6`mM!!Pwl>`1e2H)&#)$ao!jPaEk@W0gz-q0}kxJT5$ zr7I#S48ENeMM<9wytgyj&A_c^q;`a@`RW-4xKJbksAzpR1Ha7xPXb|#FU^6f(^;C@yOQUGsG23tku;4?njQZ!qFR8?~jF zTQg!q!-!+cJw`%O7;y_Lijwvqc6S~-7;jlMyt%UsUZHr(!MlU;eocPvJa)uT=W#}y z;-3LVG$IE7%QfRSG>kv!#ZOWg{~1;kLGj=}$=b>%oQ=wA*|@aCWJ4&11E$U*IUDoH zFSAINu-asU7-M|PO*Zz_oDD<6*{E=`!Gj$S?3(AmA9LD=s-ZvOpcjf`4*HK7eV20# zdWp{?Kd)bj|7rNys2a|u+?1N!G=A1S6!COFhK6%<$jJ>inljBxHHE$da#5&IJmVl;$4GY>q#uD0qo)tFO?w4bG@;_R#r~v5=SfY6FcZ7dN9!W5RE?cx0lC%crB2*5& zhUD!H34apdp<0Wjwnj{`UcQkh>)~WDCic~_aBT+`;reTKk$0Nq`=3(2UBU!990&08 zf&edkj6z5xX6Bvk&Q>UQiIYfkWCSzh|63yODPMnKiYTOEx&tZM3n}e;rKUwiFXhc% zN*U^uLMWHm2`k+c7A!w}!*8f4oAy-D7RaeGJ9+I1j5%**WOP%twV8JxaLz zJ>2t*(gX9Ajf$@!0CSpF(h`?6D!v*eeQYGjUf}Qt2fhJbwyE62dReX_)0~nz?{-sC zLecg@Qx$KjM_=G)lb@^NP4%cMeht5@VBNwc^;kz!QnyM;@prJ>T%|LQOGm2Wd`7_~ z(+vruDsGnMldEFP3);qu8CmvS^@h%`UKOj7aaH^TIJhbvfdfS`L1j@@ya__8*}o=S zr7Aw=Vp}h4?xx?sWiEGBjF@eqMs`5AWclAw8DBELA5m6dpN3Hp|7PS`Nii>mt?iTu ze{_nN$62I2uAz;sC@MjxhSod*>ddN-)dY7N6_?+3hcN)5xTcdafX-|H^U2TCH;La* zex3k{f7nIFATDErcoBZ7x?NlbaXA}=?1bsc2Jr*v*boRnj4w^gBk-n6C08Pf)WYK! z{SImfrQj;G_YHiYY^308gbgEsqpS0N!lARJlTW5{BMPu(&D=>Qp{gyS(3{`dOCBGY?YZjKT zmhGDiX?zp_9(o-r9%l$^+oS?$+ZWB7Bg4BJap0M5dUdwcwT~{-v=2Ka-WT7S$ME5T z_R(~d=qKbSo7C~7l74DP&x=k;M);u1Y%8;BWa4#*368~|Wr)ssNqI-2mCE_X?TLLw zRKqcy+@65jGtT8f`d9R$^1Z-kKLxaMwCDmKb-1z>qN8t78r;0Qq?3<2-fld(zQ}ie zTe$g?_{DqxijIU_!Z$|nE>RLkqGh{*YgcGiwI@dG3!=*u6ej2VW0$WfgW2#mxC{6+ z%N}H2Aw?4;?wBi-t&BS6j?t~}(T@4zE|4>V^uJXpDv6?V^rMiPl8kUaC{igf@jCc| z+4yrif`UbGY=9%Nl!EWXpGKG4R__1ci1D@1sRgHPB*!+Rw0#emv zV^DH)mu(uU@iSa04;C(W%8Oh=OHU&-(Fh&&vP&pnxCBB6Z>SFL1 zV<(0Pez_Zl#XQvgfvd%F_^Ac`F`9US-QgRHTi7ub|0$YInSPBB8Ak7Atz6IpZ7ged zU$nE6gEcSy0>pElOL(zC$6W*FuMk^Kpc-&I`jLCJ_WcANYXnu`ZYzbNlqj0SY<>U~ zdlBBcr){Nt1;=7?Y=xsvJnAEn1^<9A0lr)d`o)KGlVTHi*QmVRByVT*1d`VS;fq0^ z(g}{%SHKYm$9OnWi7eO;z9-;IOok(P9sYa`Uoabv3t)h`)8N2IWlbjVmnK1#>!JIq zRW3uvm8(+g0nMzUiuYRg)51*$-ha~NHOcwwB0_etN6bQ94N`nyoW@f!dumR`3QSVM zC1`<;sW4h6n4#g1LO_fArGX*wGI;#nC4RKTx|@g^a{(fggJUXUrV8i2)Rlv_t0ae% zgO^=N(72WszC39hHZ4YAsIt+hYom%Lh0Jt`^PyZNC)Fj*e?rD@q;u9}g^RH#GkRJ> z4~&V*Y$dI6aaCzQJscej2Ot)?OyeWEi$9*7OFH#>MbLXL72v231U8R1X_XlE{%qIswF&$MvH#z^5zd= z=)t3$S0iY69D+=l&j`mmT&m{L!Cfxji;1$o+hQVa7uB+oHWkGOywzSVp7{Y7(2T-ql!174W^?`6I!5K z=1;7qTdsMUdr0=|n%syLzzmK%W^jo2?B0u_5Hk>tvw9gb5dU=eso;N;Q)&sO;D6^G zzBzAb0#qdaAJy{>(xB{#?r6Ct$W81hS^^l=>P^vbJGS=#tw@6a|AIKP^+PNS>0vfG zd*Z_wBe7*Y%$C(N3rEi%j*z446N|26>8_0Mq_4(38FP4|7pLeS!LWmV?D83pnyH{r^ni|Jj6a7ri>-lQ1}8W2X0e-l zL!(?7=JMXB8~PZX-o#TysZ2LFlFGDd&JYwb9&NF2X+$YK3+lnV3~?*tiRue!`Dg}k zNdgCqp#T(^_@0B0Yg!q2V|*26(-fJ(Sj|f3GmwpY8}%s1xT6Ks65S8Oje2l&f+Lk; zgYDoehA-F|j`zvY2aZPl;TQ@>S8|MmV-y^@X>edrrAY;%-wt=Fkw~LT$7JZZZth;B zEo{&at9O;dXi)YI4jeHNH33vNv(tP^psey?}r0 z@*$6zE@zXR4}f*_=3}kGu@ZjiMn01B0x;VxEGr_>wvy_-BMRIFXwZT*6!KBg?ukOI zRcO^YapEi*Gsy^#|KbxPLVEb>?8VxSgF1ZfmK%zKoP3>$7NakI!V zw>B+u^aP$Ul52Bpb#85Hh!!HE_nnPVf#%kxHz4Z_03l!HFt_%H5SIi0z!vp5{$6M} zVnLkb_+~vJ!Mg%N+4N-*cy6hkca>$W0MlUpsCz35`5gYF90j@G(MFJrq7aFAa_M>W z%ahqhII|Thr-zf-15Rci;mjUKa+0S9PgR^`FXmtTg)H`6vAbwz?6mp`)5Hr!Hd2!&{;ybCReF{DJm35) zmS*!!2Ad}TNNm4zEbArsrO7|a-|bosfyQ`#`*-Z3G>hBoW1RNOh#8VG36H^qpYgJf zv(V5`ZORD^M(10k0pn$x)(SbFn)1J6lR?4Xa=r(Tm6NHl)JX>(QV-eDOwhrIqNiB( zPT=P(D^Tf*y-#9!@0eE73XRkX$s-&;*i5bDW|XjVGa6|{QC0_J7p0HE<8p;K;~vL%bmXrVmE0Tw zH2AU06Q71{^A?dfzOLgzKpc|I`$5_=ORHoJxD5LYIOGlr$;pJa+OdB%`O%)VXWu=3 z_%Ikhmxn~(kgsrtWuM2=+XvLFMj}~EaLrh}*?WSE=2=fY$vVNdF5PlspdmP=TCgx1uxK8nrU^ESQm`Idm2r%mC?$~ zCDasG2Y#&xPxusmY2Y6tDxX`=%Pm_B#=$}K~7 zEqG)^Kjj)`&K(l5$I+5v}4Gt!GwnX>uC zSW#qFyfZ;|N*$BCGS*67-iR{R_tR3-)(OP}un(Cx9&14J#<*+9nCKp!e;UwSZW;X2 zy8hdMKSlHE`F{=QlMA-GWQNk6i~cOzYDgE-qB74Oj_QrAGPu$#lu0k`+IB;_@(i=b z*~2sFMU@;pikX8uQtgO_bgQUu!J*kh}Y@E_#Yx1e(NaJgF|rr|FT=3B6J_7HmJlol-OG~Ck8vOWS2 zkDu!=quS9!KcM@+R=w?fhKkA`nJ~D08&rHb-$etEI5=T2QT0l(@CO&|eDc>`C))ml zxy-(#;))2%-%Fz!JS#PTKlO1Vl%+9bZbKy2ZL$Uun{58mE^|W*<}Xm@v2L-x;)O_Y zzDCXDD8H|GcZ3yq(UsWC%EJqA`qj~s+UJ^@71-or+jly)g$`ST_roafw=U=49&9vSYMvV>oqpc{4bG9`|)BP5Isjk!{F^S?IyZq|sOw%nC zH>R4V`z`(={u=z!biY%Fn(j_P({#VfU&ZCaXC;3vmyh%B@fY$jprb~04X3*hK5h~z zIXqsc^L+pKjZ!WL0RI2nBnF;QE-DQl1aiM;C4Hm8WLl(88djOzV z^-C-`6su$Gz)qFf6M(LGo;4*KLSlSNP37_*RH7S%AUuR1D;`C&#ZdGnQ3b~JGu>ja zTxa>aYve=j7_I@-e_f@q&pWY}|5^=O?FyTxVV`OkBBHthEZXTwOO*z7v&PDryeS(Va(wEVjJkF(PT+CNwm9>GU{bx zsx*2`yUL_MR;NbAhwr*$DgP$L zQVU|KhVzg=#&?B7uvZDr_Yw>>1ZkUV02|lbvJNQNT@3a=0{ej?nk@2M%JqM%QTKY2 zy51z^ulKR&+-?ZceyIU$8o)mEl4y1}gDo8mu*Ve9*@*I5g1_-c zf~A*48O1$elJXB#ENNbXRSrS665Qw|*lGyU>VI-_GpGRA#Fqu^w+uGoI)Lq{h(4?i zwy#DV@Fum_B;~(TvDAlHml^mL8=GCM1Q&Y=+8Bbgi)sM78(@D|uzMKn%>?#3MKn$1 zxy_(RqaN}mb%jaFze%yY;U(}p1bda>OD{pTAxIlm1K2ox+NpR&H2WQct#v)X-ld4n zMN}0tcv_oS8~4nejOboCPaVhGaissU^Tz#dbuKQP!jHvsHG zMKnj`xy_*V7ExSu+$DgT{{Wwn=}$r8tAm0*vTppzj;d%gy+y8-su6{6W68SI?| zHckru2 zUL~6SnZe#qV7Dlu-PIHPNuz9Vxk@?S$n;;Nh*}AOyHr{!maDwH!wqlRrPaY^nMi9w z+*$a(`MQAJ&tT6;2iU(A(OuOOY^1}G7rY71G&22pTFP6z1a~+D^OWF_m!RAbq)j-v z8KkBGEDaJ5FwkWL^g>0`4SA?y0(~?pRiZGA#K=0v_q<8Qf0rgxP@VTVjk?dv`>x?l z+Yp9m1aC8u@)d`#c9PNYc%COFXhFOkX-3B*-ZP_Pp}1&_86A)3`RG{qDZdly(4cr7 z`S5&d&eW_B=2wt!*%Rx~cE2|=WIj5H(>X5_XX^NEHhr|pvh(YV9ZD0aiaA5_Px5M; zWlyg2AP8;&XPCg@E~rBC6_(lTO{o*SfDq$**U*SH z8@*{AFa)8FJEX#+wm+#fh0(AkF8ZK7#0vEcQ>-%-bmUVhx?7<)B zHgB_1e1*GRBz>&V_Ap5wL$cRJ(%TAs8z#vzB!^ri{jJc!Fv&baa@0jK&dE7T}V@{u8#=OXEAh1!Nm4jYm(7fGTO>Jlbt`i^FLp^K!473voz>263W zTqJ{FPhpa44as5`$(7iJrzBK8%Y>%J`tsNFW;pkba=j!RvbY!HyW}}Tutf>Bc?l96 zg565+yO$ub5=!b@<%A;?yO<6eShj;g0CL90rS9?o|NZdZbG|(fwhxWObDf^#*>HOMs>KFAa-|oCZk7gvHD;o-5t{V7i!IC|A4)wCEn|4H zD$HL$tDW6_l{a2kUy8y9Sn^|+H(p~#D?%|20|MFf@hWfnsDNMg^{wPh9y{TeO&zcC zrVd$6U*)>5`E@>w-Fz(g_>ArwobpQeC(?o3XoXOQVW0h4EN|dwFwO=ZXZ>F{Csw(- zXb2x^Ojh=bv8GHvcKLtnOb&$NQV5eA4B^wqufQ)k7{;fMhh$?s#GiJP_z2?>_$5cf z>n%z%2cwc*#~J;u#aKokw2m!@hY zH?}uUG)+^g?4aXjE6BU+nolxCI?8n`#lTdq=M0hIxEGiZ~OOv+(o3 z*yo8ip<<~Gdx9dkO%wmm@JpL^17~M&D>6E9cbRN9nS^5H=-EHB$!^k^au#Cw+aBc? z+p*PdxW(JAO6iP-%1(`K`hm81hrna;y#P1v7Hh%mRH{IBY(7y@tJkDJTfJ`NpjK}* z9GO*FxCOisG28;Kf&=>lb5t&W_uQu*GQE|M4oiqEuCQI^V^CLV5Sx7)Zccs|Mt6JV z;qo+yWbl4vrUtRqMoyI)75XShA1=eK;wwr>n<{z3bDqd{YYKJ!Jf<0l73ni{bkR4u>TFn)!2pcE{DDx}K806{UC|~gb$Q`Fq)WmKy za;?BTS8_glXFiQGhiQsdpiCL5k!>Z6zT!jpM!i%cxU4=@4{0rdse<-p*qisAWRhrd zR;Y)x5!k05D%=M}Y>nBss%F3T_agRXNr{idY4*Em6v^E$a!+M6*(RS!IWET2D95$G zl+M67VhdIJ~9oAP&6$>1H;Fmw(|83fg;l{Y~!)d%~MPxvfVY_ z`Gm(i(ujQOjA7(DhtGKY^9K0n_{k2&L7UIS<(sNCpMc;#Cmrhqy8a+aorEH+vzaY~ z73;^^ixrrrv2*~et;SM+QmWx(9`PDZ)#whFv|v?f{=YRgPh%*BD}D@Dh(!|awg`ih z>-r<6*!+W(Yo$xl2o0kuu-Qnm0&`pmL?Z7fWzTL7PYTPO6dq8v7Rmyw{ueZ?Q#dTJ z-j!-!38&pWzqwMKak^Avm+SN>Q2di{X)aKV7 zDphQSB|mogq%Foug<=@2My%9sOq(xngXK1Em7%iz!nORa%VR;zl?worc3b zcfo;o7xZlAgnV>XbqwVZ5TsH_B9T`iok*|3PS<3J$bKj~oNjXpEVlg4aUK| zBN`zEY&II1T(a^1;GAjgw;ajD?h}39Do8Qgn))$-twz*MfReHqj*kh`S8ycm#h>6G z_|s)3bod_}xD9cOSY7566@?)z|FDpeAY>u4;HX9tmYPUXt4K_`M|s8XC@lpRd9C ziywFh!k^63>?4fZx8R@I(r_QGYes)O6eIYsXdQ}W&`kU*%_Hg(|JaA?KDiC0OV?vP z3%OQc;?Gk2WD1ptB8!rHsk-3aJdGsv|0R*`A}~pD5tzHPtiZdR?F-^CWuPxI&}nqaf(V zE?@R33g>P_ZA9UuJPJprQdGUgaOA##mtVLO#?%N= zyI?HA)^Hr03#+*R4qSP%J0;ZHCbf12N7TioW&Rk7NvTXy&8`v7VrwRu+B zBN|HuFUPtICHWClI!|b90&v?iq6dGD%;X_F9>P;8FgOjqo8SxH49BN%B$mOESdKrz z#rSj7!1$~xjKR@oL7cz{tkc*TXd^E}Fu|Dxcn41oFM}Ee>!28Nve8#T^gjgfEyT6F z6*{X*5Zr*6OvD5~fny~ciM!!QJb*vJqxiEEL9DY#6|J)jtQSPDcfk73(b#VlsH3-} zei}pBkStIma47&Lm1vZ7-DV_WY^CZ*l*TnO!=f8s3KHZ~`0;!V#Pf z$6s(H-UP>l{8m^oBSMP5XdVcOBLj|9ib^DErW|$lAyJ_Bz&;3z~QR^7}eY_@jZVqB`DySq_2uD73 z1_PXj+UeYp`xxnq@_71hl97f^^1mT@xy%*6UVz=C%(eUV3x`=wdJPwaxcnFKvc!!!-ob73d@0nSE-7x4Tzv82t^3=V= z)0)HAOc`I8l`l7pe-kkeOz}mNaP`G5=7@*2N}T%HOn37U2!TNyyp{{KQIeC*(FXSo zgS^ehchI*91YPJZK;J>ST<|JfE_jH}0A7W=1rK9SJG9=O1_&QUlE;4S8@-GW0d%Uq z>wS$mlHKPwf_qaW&0o8ArSMIWq(Hj7P@cEn6iMr;-T3Clk0R;hguF|=g~Q`C)*=wKEg_(T-l#6O!m|3 z*`G$f3Phyo&mtGX#a2L>qD;y|(cK>*E6bAn-oDG^H;V=J%to2YO=?6#S&*z|aaJWe z<0Ly+Zr119HGl_D*$hxJk;9pwK~pX#N4Unb{^Bz-LwMRgRG2-f0Oy=1ME1Oz)FFYm zA7BbyEk7~xQw^2#my;st>H*FY;ii1ZWi#EMtBWipN|yd|vXsbK>c%=8DEegGid*zK zNc4%v(k*+ifXolOIV}=M3CLS#-JhWrV|5gp%ZS}jA7^`Y6qO6#V~I#Mm)%r$??sV` zP{!9XizsGY6qPPZClMr4-V5mdDUB-c5b1jy>36uK-{F#eCrg(S61P;iJ6V7{bt`T{ zaCa1$gdn(w5p?5kQDsccXedd7Ab0xFgq!cyqq`}zcIDwpKFi+CEX%b;o!=H5__51V zBg}re-3)m(8u&4x%$&juu;a+;?x+N;5q((3pD|3}o~T3we!2j&;~k{4@1pJpgro2$ zbK~}XlpK9MG&%WtvfUq|{zE*jpD!59Pr&~eMQ_ZP-pd!)XNIIH`zdNB+AR}%AHs1A zmn0)szp-L7p+?ToB3Z{#5oo4a}^N(&_(dGX&zzY zx$G$bfjk^3){6*^a`>~)fNmtr-u^p^+LUt_o3BR4qU5Vl#pGn1SGR2Ae`+#bt1KuA zO+Bo`#&Lly zFQCi1q!9m&dH|)m5!6GV_y3}2_K4cdTtgw-kO{{nH^gv2TR}xy@*loZEyq^;7|AE z@I3-Y?$h`a<4Z7js0&_nOz_0D2A(-l5B~r>7a;s0Fr}OY$96bUDK^*@zL=LV>gojt zPVG$&4u|6!gak*!@g6zG!_oF-EQa(uE^_I+)#2}DEXF%@>5J7EjogpHQ!}J!25NNe zA&tr~m z5tg)DqjfYVOjw@iq1xG|i4Z)w^I{Z@EaeL{{&k>Z#rWSDCwn82+&#)ivzmq|Vr0<0 zB4$c}r#D}&a6Y^7J>r4h3WnD|PQ(1KGUL;mEn;~6!*E$iuV}E$uWCl|gAs&PXd33M zS3Avb4ZDb~edZz9Mg4Cqs{nckx6R(3KF&lq^MfmgWN?1`T9ACZ$t1YA8$MNU9RS>cS4qWPQ z%$Ft+10p2X`DX*>Pmxdl1ei2&xEb_3mDmDDD#a$!G=irPQLiHjnnI8xk){xdG<`@) zR#`Mjk|8}6_7v)iM%=RtD~vIc)^bW~U{q)?(yBoCRS=U(fr-z-m$(Xlf@|@o5aGF7 z;qWa$1^tR0TPNr4g#)W0x*8sMRHZ%$%e)XGk!Fmq>zis5xG1i86TeVWygSlL+Ni`@ zn(|dccfc8mY*axNK-k~<2HLDA0(TSkHc^l72lfL9UjmFNJK;D=j?Hikcmug1vfxqp z%HYe5)I0>6!4dH$ly(jr!He)G6TV<~ICjF3+Zzr{5+?^o!qN6EMCHM;8IIgpaA4J0 z%Pw$2@lf+nXCLRA+^E8;i{bUlT8Qk(J z-~w?C1svr$@@Huj@Ufq+La_YvG;*j!a695bPWuE$fs~=cL$|ZA&x`$il|vw>8CeQa zcEcDAT7hj!ORZj+(DG%hw=@=@oPPz1{J)^Voc~jb=EBK;-CH<;uU!1+!vImooWk`& zWB$%n`I|Noft3C@;deKxCST0l;*D_PQ6(0=R~oon`RR6^8=dsgJ0xXj%zngBfy}7~ zTLCu2p;x&<+l3`4x7UOZ70=3m9Vn9Q>pyWo3GZ#t{h_fpG$P~L3i28mo*RKGfh_&c-B?HdwJMS zV#J?o4Yva8U2IcN$5!F6^==wg%U!}oYMG$Hq?XMdX(z!RbTu<-KR-1Ki~Zgan-qJ7 z1d~`AT=0Gb?YTYb_)iOvdhU@}EgSf!4$#}6=k8mp)nWA94e3>M7t_FJ6zx2s zv5~edSO%|uLLl6uOoUOdh63hMb{{Kn#0p#RGeSlcBhEFG_)&sk^6s)VI^(iE^s={X z13g?5lz+owjo!&*uKN9CCgTws=N1bS3E0~4k~NMHenNYp29wzPPcL?_+Y(9a2p9k6 z)AOe(EGsa)c36Aghw)6)V8YWL23);nc(UoK8Nict*wqP~hPTpSfkJ4Gl&15^tyF!M z)mlx}hvrD5-$Nat&n-{GkxH@QIntL1;yDsITyvyxDof@_bTAG-8NIOnxb(JZohTZPdE!5(50#D{AFY5(HubfylTE^V2_du(LvlEc>HcFB8=Z zh${nCW>td3*AWwZ4}ab#A=ZfAV=&#-5>1XnIy-80{0kDsBK&8Nq>P3mbuBeLhz(AL zZvlLP`;})ia?=D1)Xs4YtY7@9@BT=+m9$HHE9r6VMVtkR4LlYdaeNmZ9@3Fh86|v9 z?Z=NG;r6>RWk(7rE#T<54vuf?G zI<6wma|{uBHaAOJffUya^f$?Ydw6AJauX1I%hd!(6NC*hv_6vW8X#N({Ln*o35d3`cZG2A%hV^%Ie-5Rum=+7}lfdXN~3TQ$b`+fwSvMsgU|!6{&9B zdqlc)Z#oez!LF`h(y`M>>G1YR?0}{nfpV9W1n9Ji9sD1$99JpSOWvSTFk-}Rqd1?H zbj2x4-IK(ssv5M=X&32A*vldrBR4B>yM|GUTQod6fqK#&mVcLypMK>C=Tvnmb+71| zV*ipRko154v6Gc*nT|cURI^_ZLZG;$$KA_CoOVRd=08;-t z4JNEFo*rv(Mc8(Agg;IDKw1x2ugIufddanJTkD@{#_TE87AvcX9j6^A?KFrJc1^HY zV<^D{Cx%B}+#tTB@sy>K(>#>YZstzyud4&kp6`c^fW9d{xU&NA8*`k|Aa` zK!3Ti?sr(Nz-A32{j~qjTT=jmb|kth|8h+RH_qx})3;E{mCVS4FaISz0WwX5dDJn~ zQ$to&t04oFmukp8!cR4%Sc3`U$5k*&x8uRM*HxR@A>v@>Ki_T{TOK#0(lK^AC%Jnl)<% zKLIoBA+D{b;VLuZtiZE6!l3KXe>P~jJ6fSJ)Tr1t<%3VKee7ar$-%U9ntHbHHD*6V zT_G{DbRzLN$6TC&Wc{c>Xm2-SPN8L&0jZXXToTq)k#Lggx!Wn=n8spTl(AjHNC){i zcY`&KV4V|j+QLiltl*IrlHNJx5XMt0Vx8rqSlWI?AH8{dQ!gtv4WGB^TQ>X8$9=rC zhbiijYq1}1e#o*C&X6p8ia`(k*yUIFFmQbuQF}2sO?e59b2ehk`ZgTF5AbIRe8KH- z`~gSq*KpwE&4kY9SXLZ3`x9p*UORf6S+DsJgI|hc{zT$WB;G{g8`Z42BtH6SZY`Wc zEPenbGw!$vpkI|%Xiu^zn3k#U=&aLeXgiqHxi-Qa9&xz5jnHqysCb4IJ;fl2)ezRWylsZqUAE_fHJwJIg}Pn zyDcN5OU`iTQ1;Mywt1FH4qt!($ziGF(5i;(@F7MwMV^-b^ zBNUIr8syB(j}7U}jJ*jT{P=A9-iG~PBzc>mDSk0zU&BRd*k{DI?ElQ~D9fIs{rtYN zoU1v|koHSOY_YMCLmrR%r6HY}S&9%j@%$^_mjBXLYz*NG84flyXJX{c%pt~&54E!g zU)&gQ#BY6Uwy7L$_#yH^H|W!TpWm3e17i6^4P_25N$9kV4>w<-8c0K4?0pRnN1+1I z&hp;dY|JRqz8Yf zeb0qus>l-!$(X{Up|UWR4m27L{H@IUk&*uiv$>a^bz!#@UC?y%1qDkw3bc}N;`^v7 zAEu8dG@cX`31g}#sV25k&DzpnWL;E^ zlz9C48rB|mT#t~Rdl2G><4YlI4*``4>{VwG5UKrn#1u49H}HUm;>L)A5e#; zz>)kT>d=jFQ1!~a9}e6xV=B`;SE)Q)r&>M?U6snT&Be9jG+fmx(<+y?Thu*ulJ1&P ztAyVZx}kk+^$WoS4-`p%(uAO#j^Jeg2CH1&=dNlo>r-(6Fs zC9ncR)C8$|#2bFx<>RuzrZE!ozqA=WTYkSb8$J@ zlIrP6-&H%%1>SwVWgXI{Iu7GdyK!u6BlJA4Aw1<*{CNo0oU#XwoS)$M433R^;rIZK z)O~O)gJUi^9)~0TXVeH1lY0z4?5Hfr!AVV{Y(Tfm$$ z365oOjLd)|vnqM;HiUkJ=-{JpoOKWaSHi)4?|X3g5fa=CM-e$bhvQ*#dHx)(w z20a@B{3?W>>`%&8MEngTDQn>vatNhDY`I^-N0~rvJXaM@wQ3S%RWUzf1>C58tBcT< zzpHZ17Y_6cs4?6n8cQL0@1929OGaKGP4z=uf1ZY`!r>}Wg%MZB*i&QQ>ToSpE;?2< zgt^RlXk3tr_l!PtNxktjQr~l=ey?0q!p{homM|3~N|;1PY1t9ruTCTS9wR#Gpo{BN z#q)>ZfTe67V_Ca(^bv=Fy?sV(BHD(OS{ayg9)jZ-2=>8|O0kKJ5sYTy6&-R@s}?w@ z9y+g{3tny$tw0MMbWaU-oM0KqTVCoy;HqM#rueQ{}%63^&S)N>*_r&-VN&gN4z`K`>%L^RPTS{ z{ZqXs#2bZN#v_B4E&gWex5eL!;v&S&cUADw8M$wIm5=lk+g{qzBTb+n{MhApT!8a2 ze1K?`k0!+J4%>WWxiC;rT~|=S85P_Z@^5+Z+DV_17Sg-&_xo4 z1xGy7cZQ_E-?g}n!08D8G9~F;Ef%{oZ5(}g>|&9TB?Ko06SLX@!{31Yw_hRwPn?3O zX_zT4#`lNj$MSDf-p@|Kd%Q~SLy?_bIXxF5CM5HzCoH7E40(Z&bDrnSn2X( zd?O8wf0jad%1e;x5Im#=>%0Voh9K>#uBvcP;?{&xpuMF9&~^aYw#Q+dzbl?P2=zks z*E?T?bd)HAbFN9nU;k1e80sas$02B^1QWajj~ars(KX<#1kQ`j1kUcj`4r)7qhMaH zjNZ8QXF57vOwIuED&2xlU2p7#%M z4pA`IiYQmn`!h9arZ<%@Oe+2oRad!};4g>ZVI_FmOAzy(l!KKvy#|~Kz*%w@aHas~ zV!}CF!9*aG%l&|p%7Yr!PNIx9TA5V*S1XKuUV@$u!DuDO@)8U-1ZmsdIGvPXpTK!; zOW@1|&I|tq&X*L-QiHRT5#rydQ6G9!8SN1Kt1u3D3Gy9+vn~_G)kl)9a=+COq^)q{ zbW*k^R08K_!dVEM&k@e=6-+=x#rPa*|Gyel=uM^Eq~d>Dao+DGc-bNNLJ3xQ2|h3c zX$`wcMz|!Ml&uLCRdGUY1*}Q{L9;=SCvqrT9gG(E`O)CDYR9#nk3I1^i zu2q8Ty#!~jG4^@527M*~XY1C$xd1qq6VAa3W|4?;>oY^6)_7CtVN&szD2(sD1ZfVz z!%7f^Bwab3X9&_RszINnz`2faRsiQ^CxEj=!3-8rZk+$qsPW!ZmYP)jZ!3&Dy#(tW zf-jWdc`v~ah9GT74LB=-bHdrc`66(>N;sD*nBS`7{6M3cfWf5=-&!p-|Gx_3axXy( zhv2L(LYm?wxY!V+<R?&T+5qP}z}XFZ9Q@xYn1@A_Tc7`E)SKQ^2AWj-S1F9I zyaf3U!L>^8ua{tldMvayzQ|=WG!P}~?SzdzY9D*;D;88EZ>xLlhgj=6Z${2+L=k;xYvkoS1 zm4tJTg4t6Y=W&hlfx%Vo@0(Qo#R{Xnmtea?aK94t_Y!<-2-0plInLBl;0&GtjD38- z*z7{l`mG`+#^>b7f3ZeA>rLUHNx}cGLfGIXhujkKfbFv*liFjUClldofjcD#N5{wrE0tn%^Wlr}Wt$JKC0Gucr`*-jUo|x#+v&nat(46Rf0#sxK0DN{oArBxG)Id%;UP z<_iUZY?*Pto13OY|8ql>c^NWITlqpIN`jTqSKMN-H^cHT(a4Y8G0wZWFKFx!PAooE zoGY*>FD=ilrWmsvz$#D3G%7E5aRr3SQ&JwbIA=V)McF1ZOSSiQf6(Y#B${%R_qT>2 zyE#pChSv8v=(CM_=)K*y1p*$SePGOZUUl(buF)SWx)QL=)-cLz^m*>Glg~XK)XpQk z{xW52$t=8g=t&JClj|jt!im$OW@jtM%#mY3uj0WMxBl= zc7v%s-L=K0r1OQ1+Ne|wCTY)}PTB@%6(~*F-c%Oa2;Ws(C`w^lIE55f!xe+&zN(Fv zM^%eW3V~HFwgeB`N$Sl}M>`u`AX0@5*-ZM`CGC^|mKsU=Y>vFXH%;E-z+F8>Sp{R$ zGjQEZFTPnfwuk6XSeGt5$|OHum^7#^U6@o< z57PL8q``INf}}&U`DP!wQ7ANVl3t-Rq%M6R=vg1c-!?@4hSq%tmO!89hK!vwWnyM% zY)&53XW7FTb6kT6*)l~M!j49CpI=o;E+|b3zouBd6lG= z`zSm(NTx`pEWSd*S4!DhuXn-_?-kIrY8qip*{HGiYwZ1q&E3Xw->9O|3CADwLKNvkoGQS4FrEM0?7`bGjAntN#NPdx`L(D6By3t3_{=RHB4aQk^uI zlDhTuNqNraBB{LY$}d{%?@DA@IFVdeBKuFDi04=>^%r-#_}im~!@N$V59e5I-uoVO zpS#cv5;3HLe_hh&pI*A>kS)+9jp!wsB^90qnK@+3W(!`F)eh|!zT%Yqye}fqv}agk zo6cUb(y5t7kSk`w2U;gk8}v}Uf0&Bs!R*1>Mb;FnZ9BZ~INc?Cn#gw7c#q)83#$u0 zp!|0;ukM}-gtStVc|C2U;>eo@lWsni;3_3&(zEiOS6VTp=~{{C?ybm6Sp^X#*zAaN zr9Ye2E9XWfdjAPn$ph-40|XZ+2dZ#jg@(7pNVm5ue65Dlr~gqV1<-GDg-;IC`xCWR zJ+EQhphn`#mNwK7<1C0d3dDD|MAd^P5>U{cVPpP0<^4c;xh0p4XMtNaj&OYI!ts@c zlS==Q@TlVD*y4%9PA-$Z@-nY|$dJ&emF*+eWgl4WumUk^vLyN%;isB#iOZ7jJH6Ng zRr-TKnoI1`u-H3XVt=V3_9WI^>OyO-h$weSj>ISc^$dWM*1IHEuX-LG%yWTNsd9{A zcz)lZ*9_{HSTJeAHAMv&GFiUf_U5kCzi((S^R=n@g9=k8VWUHG!6aOlSZMkB*|ob_ zSbfO9hIWqk%NdYW)R*pP?1w8Rdt1H%b^@ZYD_I3Nbp3H$05mxnS%c^jR^LE-J`=7w z6`_tKk?bJ*BPL&7l^p3Cu}a-9t0+Au4_JoS?Ya||#Z`Iw;o`@FNz)DA*hxd_UQORH zdoI&gRHYxDpEVK0fvj;uaBHG3$zIEJ3#-yOSU?Gh1=FFm{H%ha=>Rj_Zr+2ylvQO? z;j9?Vfl0`3&tjf=4i94dQ?d%Ck4(>-lGT4&s^tsVA2Usk8N?8y$->{l~xKXG^ig? zKWBf>@{&z@19LL_QHs5bV8>&o6lK9;-tp~7p+pB(B?9pPTpeop-t{#dNfZfHDUxwX zcX~l#R%XBSqIAnw>FdvQJv?-Y1zA~D2v_^=V8YHGLQ;78#3`5(6-_C~Dlk>;J>PmJ z?ogE&Mw2-uqsY*$@ij^%lyOz*uE{FMNzY4~GGRl~C3E$v5 zj_~28NRqRs7v^N7=b_GJ6y)U7g{!^~d@X~NCCeimLKs6Ji*7Qtd>eg_h9o$(;2922|YL8`)ABDMGjIV=I#GV*xS&Mt<;iL%by40MBDcAG~T6W<= zgkqQNIfAKpeqEZf33sJ(PaBjpviHzI{X(gOk`nt_%}4JCPZXWHnQq{XNzWLM16P(k zKc;a{7WkPY{q~TaQEv!a!}HU{(;2aefx)ydT8MAYet0n4o?~p7(R4p{{ULA zC!z>-XPr&dz(#WV_P2a~p^iH>^}v)qmT!cR#@0+abWk5a>KsZOG!zgmU#f7JiA`+h zi?B}-Ipfn^k=As~;OUO@kdyHvF?Hi9<8j+G<2yk;BO7lr7P>c7jr|XEYv@}S9hIOc zCu4je-N25TU@OU9Ljs%2$PN|dOhCDg%jZN6eWrEi`C_gwF%A1sd3)Ayxb60q6 zaR#v#go?OjwCsrzyHFR@Jh8a!*Rm(kHNN2$w;6h!duU=hAt<6dmodv$+n7O0$i^MP z=~L0OrH{!2$rM`CKzE`kOwTS#9}~ha#eHI5b_JGScNqmcVv^#5oT9AI1hkRU zaAP?(sgV@3C@&;(WAA77t8Cs!RYekq^@%(>oM&SH(b!np5&1My<+7`X#Bi6nTu0A& zg35o7d4N$>WQbmw<#WRVeBsy7yo`UuY>@0IBUK2P#Jo{>27Y5b$#GX|8TgOq-ojfpCGA67xX&00mx z?9vn$-Q&0UxRS{@!$-dn-`FMJHNi7v_>HI+QL+kQ^xN#Bs96(mCG(^VOaHZ~v`Zqu zOux-8jVgHz2kPjz*``{vCuB{?$e(WMzd0CF(AHA@cV_olXjn;-{%i4$O(YpOX{rCt z>^3tFV(IscL9+_;G0H0%YnlIN&9rCU4Se+5Jags%obZjy)%-+7{{I<^iOD`4CMa#44 z6CT-c|srvJviu1@mX%xV(V1!@VLfhJ9Vsio+k z5op@h*dt6UqNA&`ErWmhJA2#PI$N4EFmH(QyD^L~Blr&gjPPVWKS%mhY88$MPhv&T zBIgeun?6-vcml(6VAU$0ueGDA5sfecx=9Le`c)IC8W~bO4D|`$oNK{7eAXa-{l7yO zP0QEZ)lclnjPr3fH0ZNFi!_0VzQ(qqs?v3(b*l<%ON7q{qOv)z)pg)`6kNByqCyxHDqVnP&~uTH^sHHg z7SeN>@YA!XK?LYoTv%5kA}F+~wys84j4Q3JF03nBD}n@-)YMefh)7OSRaGIPD1^3@ z7Otxk(FCktSH7-l<2o^pfZ~#((#paL5ko*}u889l2*j(v0x@0%7KsE-vP>i@#4?e@ z2o#&FFbJhkXhT(Lu}Gy5hNBkaBGL$`MuR6%ptf*zNnuS*VS|`RV37)^Q+R!CNlkId z>e6)>!%2jwsHT2SR>6%Fom>nFOr2p;-h$oR`#u>j ztrCS4LOCUcm130&SJf1*DG^0(L`iX|YE@ZDQJpBZQ@E%SLQzq6n$?6TS}oS_llHA* zEd@7})YO(%p(l2ArIC~qb*q-V8%yv8RD%fjPVJxZHKyA4XZZ@e+tZmB8s_#UJb&Sx*a%s&3}#- zJpPPBw?Gk#Ztd@E(kc3J@;y$ipsm?uQ!aN6d9jb>n}h(WsrQmvmUZk8Xjyd?ohh66U}3nrXnpJnM@-$ z4-HPCfJhC6+VTAxXWG&)LzK^&h~KmpNKpFsAD^HUK&=KQr5yy8{*8%g{dmy7|KSOt z{!Z2t?Wd6}?nA?T;+0E2a6#18)U>0qy%TaMLyzdQdf+#g{Zn#C;^mj-_SRP7`}HK# z%zrV#bP?h6Da^b-FiQBq{RhJ5+xU&Ri14u-;X~;md^UqHBfvSd@S&g*J`^J1!%qkw zdXn(rCxj0@N%+uH2_Fh6;lnsb_z56F!6>;locQd?WNgtK14nDRkR)Q&ov0giOoO3A zbbwb!!*D*GfYSiR9nzWT^D!~>zK7iu2$4{Tc#$v`pVEoaosx@?Jnn}YjVtQVSbF&h zhhETKu?JmXpaL{opCZLmqqif^c##kak-QI8l;ZFsB#h`SKm%FqMUEq6qLxJZ;je?! zG|)cr>-irzpYCkz!*_dnXv46h{GVdX|IhGYIf?=Q9+Pd{{&~!=?;;G??=WCWZwhk} zD8Prcp&2j*6$7RaF<^dz0n?KhFh9Y7=}8Qjo{9leNHJi>ISiN}&44)xGhhli4443i z0TbXbU;>B%a|&X>DgXwo0${+L1PoXqzSF*BG@Fh@{@QsRx>xI&gI8 zq>fgp-?nAOff)2!?9KeZxn^5$sJFkHObFncXSMYB0XPZ$byxh$^HKMl#5r;aKQNJ2 zH}S<#NqtdCbshG;_Da3WyfZifr^5b{T}>_BeR!F@sH++0Eq4WHV`e?*)g6s(y~6w? z<9&e#K)dFrf>)tb%gtNZ+>B#&B>T7E$B{kGuPjZl>EVbPhDyX7;sR3LJY?GK*#XK0 zJ(+h0>mqUVh=UYqO+&LRHba!u*NK;X=Dt8I3iVg#uI<`^ChiaH=O$J!Q1FKtw*1u# z6+FmroWFXJf`=GR^;a)e@BxN1{MAboe30Qe{vzDC*0QTlcli1M4MdK=a#v9=4%%*D zaFM^ZrL73PxiK&ivC9Z72KW&MmlIe5@S_ao5x5%Q#~55m;2MB8F<3xgEx?-@T;(s( z72m=&75j^Oa)kMDZrfS_xxyS~pc(+A(+C6g02T`KRtB~Jz*|SRF|ZB5Qel3Afo^|I z<1Xw{7}({nX##Ku1N;3o%>eFX;6{JVRseS~Fzm1C?Z(72a2H|#e2Rgih-t@MGjKl& z0C0$b<9-~EnRj#eX@AY7!aU63Q~sJ<^yUZyrvachM;Uk-0D5x|1Fr)>Z|-H_EPzGA z{4@i<0I*n?_c8Fczos3H`3wVp4(<$sV2#KPEu?oUYkCW2?76@L6d`p4%`WcK6Xx@r z?WixZxMgd9n}a^Z==*(<6^*@pt8nRF)3&-UuIB}gIqr=iHwcbj3Lan4fG8DHYa zQ==lCykFwz(>@WkssU$+@?%S}sG>H~DVn_LM`(Ifu>x+!J0BN4OO0}*tS|culyQAU z)w(q-;C;C+0#{J@USN<5Ch$cDt64)Z|3VBQnz9Nr)%XhvVn8AO)A%|exMYQS)1b`b zEb~0Rc!~8{(X|r`9;d#)H<*V6o*`cG2jdVTeU$D`Mmmm1+;o5Tru!eAE+$k_ShJ>t zw1|>5F#K8OIb%Jt#eN;d#PtjFFI-#P<^7G#s=B`!4 zjsH$vyD-=KPf!;B+V-|>!YuVu0hWkXNzF3d{oTv8xBddpj?9;je|5?uW+=;W`*+`s*6o z6k-SSJfFX&rMIPLprsiLrc<#&e@RbIS5H-U6Z7jX&KS_h*4Ew@Oh7lY5b$S8S=-XV zD?^x9bJ}R9Osu;eM#cEad7(<@?&aKZjB_*hamqv|GuCN8qmpeFIl%c+6&R{)?A`|&3gZdCd#|gr4Jj~E3g3!N5 z7Ao$_q3}!G0miPpNISdk4e3Ib; z1*1t%FnA!!WN>M~OQ!1sfs}1o>I!igBwu z`f3{oAWT2U1PU1QqcHa~Cbj}}t4esrE+GvTEjR~|R5rgHATb?X?Lnji;S1HQUq|Qr zq1Efx6_LUrqRlgbMG)@(Rdi16XbN9t$`JmN&SnSqHOBe;>pRJffgNhhuQLvdv-*OP z&2I$Opuw6O8cpbuOSwmx}X=&m`{8aD^8iJ;}6*vW$PY3Tto+Nh*WXb8X&ON{3l`f*rr88dWAFn_^<`?q1~&v6yPd*GTtGgfm-f6J2z)WIf0bw-={hvPvD@ zN1=>KIFm;zF}YSFfj}A|ri8F<;Lj7c^|r!;f&7Pzwo^LQU%467kfX2_XMlw^Z7|2W!|63&}>mN7v%YFXQlN(+^r+)U_;c@B8BTk4!tIsJd3oPo84>xwH%g#Q+UL04h* zziIGLxSQtiy|T}OT~tH_s$qVI0$NuAS}v@pSXEe5F8s+8a!I^dOYv(};3xR+s4O@@ zKNP|VxSOrG6z5?$K5l@DJ;$FqAqI|9QQ%cQeOlC2wbnEe&u3D+R-Hws*jzzu1zIFBHZco;uP8O4e_&C+@49FB92#|DdY zmQ#Rob|H{FI(-Tibw6TKsJOETfF*C#g>n;NeeUb%X=zi#fMLR0WjY=?_|G`>J5-yd z#IC+cY=qBG`x2-O7TP4hIb=QxN= zuv8-(7fK*bob|@B89hhEY;j^jyE>=^3t;R)jyX!iz9G(vMSkOXJ03Sdl)l zG4}(XIz^t_S~{Sl_hSCKHS++4@t?2iUw%FU&M$Q zaEyqQ9$p;fm{C9MJKBgyL1jdw5E&8q2_qss$%x2L7!m17MnrllBO-;A5s`6@5s@Hm zMC2rFM5K^oL?pm5A`;*j5eXn8BBvlDq6)x>r~)t|auOI36#_;?MvxIvVaSL`A!S6Q zkYhw7fQ^V0@E8#Zw2g=q4l^PWLK_iPP#F;^Y#R|N>=+RVaE>=;5#(%v3kXt1L<-qP zL>1OXL^r~<7#7h5jnZ|=(MX@SuaTx(c& z>x}N#tHiZJAvj+*g$5c!*vVu2llme$Bf-MA_T#z)m@w@a+{Z0^_SVWqnp2JeZIZ(? z_D*v8yOiiXoveKqI9X%lwR4-SPs4op#&mA;DX(ih*twb9p?#xvT&UFXx<=fE4&J`e zUe|uhWIKZIW4EJXlT8P{n^sU*ZMb|l@23{o8!oe2B_F2!N5HzD5>{y32;l(nqW680 zovtn1VnLEJ%%$7sb?G+UjhR1}M$W7)-Gq&l@ZUBEc}-PZ;4f61&)J3f!gpa-sIsII zTc;3QyGx6}2Ub_rR2K3{Voo3bpq2EZ+Y-| zS*{O9;UX|S{uG)J7o?--u1?x0iNK8bOHoW}5Zg2u&jT|#Nk-7gGm8;3f_1yQ5j~rs zIU@2s8ylDtzXJtE(YRKi(b0VfM2KV@TDb%W%4edRBxZ_*3s)TXS zOw``27TZcP;;tp1_8KuKP?$n1Ik=8as{*T1@=&k{R<`#xiNNXMa~eBdY?XOOafIYk7Gyz77cRjC@J4eb8!3H zh>yF7l#h3$Jf*i_gurbyabUn&%2QBDc?yw~=O?5*JxR**6H=a@B<1O;q&$U`lxLhH zx50gjX>fTTR9AStf`kn$=3DbGnDl&7#Q-K1Pmn9+2~tv?LbjAwVJ+p| z2v?*R+bLXB38BKIJRwNR^HWKA3SKDX$5T#^lqcA66(Ycv@|;jhc?x@^Jb|v1_dt%6 zC!ANxCs@Xcdq8}Njm^!xo6aK^Ari6aZiAuE$S2STGhTlu9lzskMG}xWK*s_NVRN=4 zG?0rA;t~BOL>sIBL`C)P-hqpX!pm99Tz@$l8io)QY_w-{S?bkX^}-!T3Hd@4p1N|WCpVU&v3 zu_%nIq(mxzkHN3rHAul=ddC#U6Nd3Q9B8NNbB~28KhKR0Z)K~30@A1!dQkv}7sfo) zl!mEkrgJ|JjH$BcbBRhcupqRJTDO$zN<(Ow@epdAkk%!PZN_69>}=V|uXOA%cua`p z(M$v^n&p5+WP|e!ZA-yjRdirhYpYC+pd$J+4t3$AJ$*+noXlz|IAx+KCQSx;p~<)Y z6e-M+`YBIoMQb(`!Hn-{U;%(7$T5|ibhqeZm8tYu&Z)3zl#3}p^yd064b&l5Bj>st z_6?-O?L%V9?{w@I#G>u=ot|l=pH0UbcH7A~MP5QYk?N(@$Bk1+GDFSb8A`EMr>5!uU@n*X&StOZ&oQOF}l2VV;H8 z9zmrq8(VZE{s#+^{)|J{$HEzFXQO?l{2kC4G#zU@HzD8Lmr?w@ z+W}Dr7f~-7bb2u#6?YrlgV*dz|7uq{8J7Oc-Z6Wyh$`Yf9MthSRMc}u2WsZx3Xz!y zq=f?1ha0K5N5?D!shDa;RAxUWxT7aq1Ey_ zN@1E`_PQ!vWH#uG6wOh>jzU9-J)F=(eViKdOJf&^a4v-}S%Ao-=^&UD2+(-WE9SsW z`{pO;I@chvGuOPH7weeK9MeD-j%8MiZi2H|!6=Ss^1Yqd;^e+VcWyRZm|Q(_@Js@BJSI?3XYunP#gBpXtf{)2T(TUqD|ch{{EkwOQS#ULU52d^_O_1a~l3XCPo zfv11tvrGPfBT4!5;1j>cjDNs(+@_ws(6+|T=8l#goKI}g zb6W^$M1SWlhd9+I4w82Fe8lhqV*WMX%gtK|rAd1e--Tpx)>z)eR6wemXOuVbDXi!WymRfd zzrG5>s^xkU6P#hW-oymYv9ue6<4sKM z&9NMBVgeUgZ~<1{#AyJR5vaV030zK~@+KxQk3i*3OyEial{Ybg1q3Q@VggrLt~W8& zRBUN)Vrtu30B|!K4iHcc02|m52I>L8!R%HBwg6ynVoJ6R0DBV?&~0gNVghzq+MAew z{g(D7Cg4U(dlM5dY-w*|0`5W#9C$y)^&CYEdlOU4{V0IFi3vDvDQ{v5KW!;*VhW$K zv^OyUrvachN4cz*0iZYcFz`A6^yXd$&H`8@;7v?-$ zdK1qFN#Ugm6`>tE$(xw69rcYH?M+PR`+eia@Fu31}eI}EG5UAm@=Lk z73t*t66b|CvDBx4tFfr0J_Y=5YPx+2n2QL8(dpJiGM%3JcM4U3v)w4LB~n zPG#)UOEZ3ys>Yx`6d>q0K^TsQ89GG}`u7M!FB6289B1e(LG02?`Q9D}h+TRK0w(~- zF1-ZCF~}~x1ZFVEF1-ZiFsNL52`*4Dn)DP`RIOk%>S>0zC>YIphT(1nqhTi)-mhSG z>80}E(#xbwEQ(3j!0W5z(o3u&5~XcC8T=&@ir_G*9!~{nB+xRqLMIzMc7t3n{W8nw zK|r&VB%fK7azEgN(Z~2^aSHV|!F!BvmM{*@8~YgFEKGS8n{|ti@y%5!TT!sE_!!?@ zokG>(S{Y>)aCD$u1nn9?!F#H>nr14H7oXpnu@&k#=j466A9 z0)Z=Nd}MW9RduMMWJ5`XM2X&2H|#D`aeAvw1Qb*z0t%6dfS)iC(34CA{Dg^so@64Rr!o;xNSO#2=a>ix z(k22B47lW2o#1)1Qb#x z0t&6g**4!LL;#xzDBv*>5Ll!R#?vVrW+EVjHW8?xG7(VNHW5(RF%b~png|GTO#}of z69I*66M+hA6M-Ay+5?L16fUZSP+=wlLKMM7z)xi&px}ijf(ew=|zh zc$B483}XsK%XH13s#+cOb*GO3(2>%nMhjP z-iwbdG{Mtf@6&|QNNN9w$P9SLVw{B0L{)!xmMNxQO}U$CXumTX;6?&lDE4L;wx@kg z@AF^6F~p~ER5Km7C#{%{lgJz~;{_e}kd4Q8Nic0^p zMlaIIt94uyMuTcyB&OZqNj_Vnx%6By^ClhlJrp(Vh$msSH(`#LcG45q;f>1`(|+KI zyV0(f+LJ40{mv8Tj6$wwg4rpvMIVs}VxorGHKm#JO)eUY|1 zZ|kg&Qg`uZ9Lh)GQ{3drCiEg$CA<+W1Ph%3+PR>2i*a z`?QT0)ABsYpSMd{{)P4|vUx=SU^=~PKIsm`+* z8>}Cg>~80D5T6Q9g^CfBr*z6o=%Pg2(54^3y!kJI$=3?%oPNH=NM-bG zF$wjaryGG#O@_lI11{8%G&Ts(; zY;^RhNgduI!TtR7YJl%bjy4gEE0^GNuk8?cmvYkA$O$O|ItG0bpaRz+_woh$zAcl2 z=u}(;zgEZkhVV5`+KO5-B3LHFqk%4^fFdG%TRCC|hJY@k@HH_wXYAJS$&jy^TQonS z7MHWPs8g^OMrC1i$LhD3?Qj6*Gu?&DuV)Qu2< z31>CKnWCckYOe7wBlbbWCjM2&Ccy^ZhZML`+$3mOYen)^I?h7k@HQrXWbCF}7R|v09q55i4DJm=)qL@r zFbb#-M|By8oId>C=|chap%)FD(B0EApc=i3rtCX}!-`O-B0}Y4q@x}{?-S=~AiS&88?|Y`i+W%=`Zb^3YtX;~or4%R{TYXHP*B>o;*Jir z8xh8CT9;oy3*nK&R~i|6sB2H>Fh{+`2|f0Kv;*Xv@>&PS1Vj^H$HG6km) z38wq2Rd0xvp@UKSZk;|Z6X_4qC+#LvP^C`_OP}x&opuf7#$PHLJV7mq8)-1Vv;gCa zmBqlgg{DY9taI=foz}ppF-m-AY+97 z9p!9o%%Y|S~<#^yZW2$>|df<6{%NsrQiSNO8;e*#(cEETGy`^?NM5gmn zS@dzV5bw3MsL7SeaT~3rcK`1O-)^r*d?q=(qX$oM51don3+?^dlppau?%NA`vZU<` z|94ykES2q)%`Sh9Es{^nx%2~{!){!a(nJH0p_f(}h>`wg;@c^s?e6Auy2tik)$T5B zMO5y42hCI_J^8UhkexE=$(w#oc%_ueoAHf6S1HvdJvn?BSijXonVgraYbfPK^i+>Y z&zDO>r0U?~J>T=+MD749uKrYmUYZNIW;?uIt%meHjA;?nkY&(VtPBJqa9x}__${ug zwf)%({7)s_4D}=uu4Uv;D*R6;bs;e!nznXy3;#0=n*;+o!H|!jo(`lw$#8&U8+*uw z(*G=@ETAAP6gTpJk#UiPYuu%A&oM3h0el{4X#(9x$$< z^1sMXBF75S%4`MtzAfslap%ban~V_7)}nt{}t|WIz_kaz}G(f|IYC< zG=jc=J!WKOd*=mlM>tOEVPVG`|54RcjVpC;!X>M)@ZZDHmX2QUy?s(8 zxR(<|N4m$kbo&X@@`mGsggq?sEExPv%M|MOKnHA$(Omt`8ZgBEsx=pRyURoC}7XQg)T2wZh8Z*Hy zSWJHFBFVr>lXoCdv=%-1OodvFwOEdp;r~u@JWc`8PaMVZhs*rm<>m^eRGZO!kC~n? zax?>ag;#T`)5fsU{jVmIyRqMT4E5W+a8n5XTU_@zpT8(&2njEEJIo{jAXmAe^m;-g$H&+uZQ_pr;z2{QhaU=mt%8Q`^_)^T1LmY zeA8=D>#tzwse(oOT>Vx43-RNUcL>4YHt* ze+RPBNF4#3&<#niDcYFu6$r${|D?!?3o%>?-JoqdGW`>vSd_dPSF%-?*e82NCQ+7g zDGsq!shL!2QqMr6FfxCPpein#ic9=Dm7GHv5>p^njodgS5Xm>8Nw%(TpV}CQdQoJ` zgNVw(E;sc_1kz69$EZpBE*`Qc^@z$@ptXE#Klsl$M4!y!obAXtfpXqUMNsZk$~&<} zXQ5V$WEznz8dKsF@-7u(;O7Ul$&N$8y$HbY6E-lbcJpK# zMbz8ly7a?N>A!<-|Kx6+gn)ZdMj}s32@T*Bo`lsjY6Upmo5CZvhRSLpkVkJVjov2# zX3zkBS=UiOhYVHEpvb8-c+&{x(R2Gh{m&5ToI5nGzcNVba^;`6@v)P|TryRpAzQ?F318czcQ8Bhs!>e^^|K<$B58*2@8E1W4 z??Xqvh>oZMXr=*}!xYp)6lBzJ2kUhH{pgUf?Nj8%&mAOqbO(3qv^>FLF3s?D8g+`Y zcc=-)8!ec=X@ugbow7tv?J5e;)b2uH?Eb0aUZb1#WpC@Umpff+f@w(griXf?7C|pf z=Ukes-|Gw_3ym32{h;vZex%l@8BqNgO=Bgy$mBUlgPWrhe#~h>VjKpyWgT7=8+;hZ zL+FTV&;e@DJf^RM)F7i?QP=fU&R>yCQP&MbUAegCiW|I0mtQ~){-~y`F&f-3y1^ib z>JkqVI!d*l(y5j>t-TSgRn5DX5^$Yg(y8`So%iX<9;41*jIOh^cU@N}y?8+Th|19J)a)o5#wnuaVic$P{UY^Sv7(oV zRDOz>OH{%1X;!?G(*k0ii5KS8NPL+_LMP~j#@W+Xv!PHJUm+>G1*v$D?$fpBP%qDH zMa^oE2p&C1XTk<)KCR>b(5TDo#(#$g>J1dn1C=>C0T0?ch~_~nSgr@H2?6|N(f6CY zuds}#U2-3=xU+nbFwgbys3{Lu9j_Cnx{Mc}+cI3vmwJ3P> z;2DP^ycUmfpFkR;CZc&~jkb8iuwr<5Lo{sP&{ zqp0Hse6;cZ73v^si9;Pzhz#s|SX}D(dp-mn>fodoqmD}2fcOrOHEi^-jiL+xZKLTT zP)nF_x`=2e9O#1F`SI*kEWtY|Mx3ZeN-O3@^8t=&!a?t-vGT2 zDr9stb(uiilL&Ym!9Kz1_uw0m!t(v)XPjXVor2RR?|0%2ZsGf@UuE1AYVPH+6u!R^ z3O7oG`L0mKz1=7}&c6xHluph5&2*;$gPl~f{|c(v!n-TVN)fn;hEQ860yh)8amaoY z8;oG9LPV-TB}8m2T3c8nA~KA#$p4-WEI!u**b4l|*QjCPmuUxn467+)!!FYfoFz2g zlyV%113&o~VM4VHwRI(x{C(0mEB9(hQ~%C}7F?ojEr1&+L6x}Oc$=^m5@`ByhwJXD z){QMK+l94=P(DTpYcT-<|IW2t{m8t8APbp!@P)OM;7I>YY?-?7jdp7p!O;}o0UI78 zdxdo=VPk~!G|F231K@lizF~b6zGND9Khm*aQWg%M{j1s=dqpsLBa-r020EK@D8YNq zUHae7mYg?;|l=%48S-tuNVnT;xU$y_zGGP+u56&lOv3zCs0CcD>S2I zA{!AG>cq=sM#>XNBS((zjjKcLo3M1euaz39)DhfTzBj&a50vIKqN0)&rWpUOW<7II zbpl^(zE>p9TCY?xMjXYv-jUXM^dr)uwM(6Jdl)&7TDf0mD5dV<&p7lL^$;CgOkbN>3f%|eEEVZsk#EH zE+J1 zSITVdZxzO@1YmvxOk^uu>St47a^%!CLG`^UW6owoe`uvCq6&1yUj*^31BpjtAw`M; zG43NeqEjJ_oM^s5BO2F{M8XCg^_Y(T7BW7e(!eDfiDcxvQ;;es@6x{A(MAKV-iXGf z`Z&|VV~%+(J#xq+Y~1U*m^Z!EP&p_d=lhC!P=G&rJSq24@9N|~K&@~Pq2^NA#^rFM zv0ceyrfyXE{u_y+F44f>0A#8h#%d9@Sfit`YKk>_p@>406pyFiXE7i46f@!+ zBh(a+rzu`}8BH-h6iTz(PXMNxfd>fycT5t9`8|NBUAj8@R^}{}P9rq{$u_9*G~rP< zdlJ!=m1;Oe%$?pu5%p>~A4SmvI#C~uIi^!Y#p+o46zDBZtcaiD!Nc2|JhS}wqub*Z zTXgTejHV_h>`)#7`r$ieBwhmAr~imVnY6R1x2b!#&=3FK1n=Dyz5*kurx6ldsNX<- z0$vG#bxr;H78=PJD2M(d>Jl%*gZ?AVn@Qp44*sPHuAh|ec|#O}CVk@U$`6#I_VzWm zcV!Rsc6RsR#>!Tx+!=agG2r}H@F6gz(HC%LzJR!~F5sk_-7ma=bNhopyBBc&FC}`< zo&Ne31(yZt(khP*%?FK%M?@sKB(?x3K|V~j{{p` zzXi*Mh@}2Stp$D2zb_uB|NqZB0!F+s(@KbvR=hDjA}$3)H$y~4tpoz(nhc6v9 z6mOjPVu7cCKf#bzR21-j17KjBO5`t1ScU`22ug+p%8C4TqTo1zXe^LOPilZsx&~wh zvr95&rlNB0QfEGZu3fW@e#{R6LbOb5@Xg z=PGXfER>`xHZhO0KQd@wa&vh+=X`X~z{|HIt5RWIup@++=QPh#+#Ra8OVCPBar2{$ z^(izanQk>WKc0jNY7kQ&)xdqr_KVyEsy>GTFrh@D4dWvy;{x4N3=Ab$h-L_CpAd^w zizv}zss@)RQMr`SE_bO1fl*(kiWTD0MO@8t)juItM5^J8iU)tm8>@SIwDMJ*x35Z5 zBec>3Lm+wDiXkg-!OPNUehL?34Xv7rpQ2ejEydmxCbE>!4CbYE;!B=1yF#qih!{1h zLaYf(0V2b$O|Qj??rQWdK}l;%T0~erca{3>g&9yyiBKy;tw5r7o*1k^MK@}hMyh2R zzW(ghHjY*sR-cFHxr|tQImCHlcsaz|%K_`r%N!C=D-n@q4xTkhydp_26{h`Uu)i<$z_X z0k;tsE@x82SX9tB(zMYCRVwzkjzqqN_D`^AmTwT=fB^QRiyB?Xe|;Zc(jw zba0%dGE%PfihXVXZD?vzq_;5&71Y}-zrizFlxvd%!wp1*g}A~&Qj!ma3ovI$g}71= z4~YSEDWt^O78iRNk3^$JV8#{8-5SO}F>p;`2(XjpFoud0En$eLPN+1k;V2>6T*P~D zV3*Urhd!j(Za}f!2!{bO8?(aMZcwq^NUz!xWwYIA#dgPem@AhNW3$~@PYjcNoKu3C$ZaNpi&X)v&oDRE`lCm&)0z+XveP^)KuA{yL^8&qaJnH$}qqPZqqzx+%b=H4vjnr4t&)76--C_|Gy=#We#CBjd@6a2Ge}iI(D; zK`+;gw7F)K&DO?XpFAZl`*bQ%%+tf_P)WREMX@hbu$CDvJ^q{M3e z#H2T)h(hd|@qD7k@&bg2hZ8dhZ0yi&w^^-QM$BI_}{4jdY^eoFPZxy3B z3ahs^&&aXYFEM1|ro8usHtQ`QY>|!Tr^ur@@M6v6JZk+CJ%B7hmb$G6|MYS^HQJZD zOmjIg%@y7@*qzY2S)Mz(G!prCR$^)ws=2IvB3XfAh~S!vA+E9+qE>8a5Q=TySYq?W z)gGn@f?cCn;#x1Opp05$6{1Y>(sFk=RR1cxT~=eNd!xB1^H7(l!jcdNO#{uE&6HRY)`7JH}e~_PgG(+Z~ep_b@ zcw(6CMc7+)=BgyKgNpM-+R9y&L$0hms5y_;BgayHTzHDGWfkKlB!Z50$BMu>4+(NZ z<86{2uhy*I&LntvK%$BP!&L#2@5!EGF>@)lG)T3jLE1k$oc1Y-PfHo@D4(t1jMFQ5 zBJ8>>rLPA^kFXj@%wSZwz=;kQIOD?QMU0w-Sck3i@Wkmnn*YapiU3uOA*>u-J<*=d zBwJTcR=PR~CUt(xHF!qMbF!!=9ooGsDJFW=?{v3aI0JPj10u>@M5++HiDdJ7SOnaa zg0oLIseKwUO`|}0VN_)wykH!NjAo!1Ezby?NuVtWX1P={+e1a9<9oDn=MueETvjM&VW#u193Jyq1Fyf76H1f3s-K+P+|Rv8eN zxrl#|gDD-)?_FsDd!FH%eOHa!n(%fRO zB9zX>rUH6XJl4nzGFC5xdJ4&6s`hGI)N)^uq~ z6=NT4vPv}Dr5wB~pw|M&KqFK~`Od*0bU{Vemnb@SwLh#X&x&<*ztP+PRtCGXM7CI4 z_Q(;48_vDpXuE@FG4aT1>x0@7>TNWMm?esjXk7w2pK7#wnrW+5%axk6!jqnuN}kJy z@}1GUaIvrSG#+ct-X;^H1L(0l5LoDGJku%^Kbw-N>qQj8~T+7^ruQrtBVJWc6#x!qS>~IaHMtgO^v;otimp6bH zxTd_(oItN6%^0FmY=Osp0WTn}$HM~@2k^+mSXa8yQj80qK1KdeTx==>KXAtf2W_Jl zT%t>^P-5Izd+jDW<$HD{S#oFaOh!>PbD`+Q@%hZ1=i&G66+BW8LLID*uYl?7L3ZP)NjR!OEbP7uV#tmA`3ltk$NJOc|g?77Y zNw{ZeSagcK7mudqf0%fQ#9T``4~T6kM=eBEwxyg%JN#(F5fDtTQ66E1Y|)zVxyW%| zoh(KXwug8@y0(!!-lL^*RwcqvV1g%xD^!{zRxE3d>QvX(9m8c*DrlK$&OJK7CD=9@ z!hVjqa83&*+R{ATmUxrYq(EbIWsAKgNQ7w-4Xsg;zpXENh+pewwvmpwCMcOD81168 zw&)VdOb_{MMbWj&IbueWKM2$A3ze!>MrTh-S|bQl3kds2L)WQ=nvyCG*@9@@Aya&W zPB9$84I`aPpJ5C;*SltjOt2zS9w5mV6=d< z35+^dqFT!52dg!gMfqx&aoAzE0KP!p`c>^TaNa{>UI}I1)0lF%OT?_mZl~vsDz9`w zWx!fDnuSz_2}CTse~zc9H4{+k^2J4>9&uKV!(||N3Na{KEoK?x*^mBRfoLz~czY?2 zSLe8NVCwM=@*bF?!}fuxW`MBxy9b>qUQR~VerHXj*(_`VR|dW`kphru9>&EiZIZ30 zPxi#{L{72wb=TU@Ii`AeD+-?G-9k)v6mTwL1{Z;epJ{9QP=Ki!v%@w0IjB3#A!x2w zbD!t#11{mQat?6kyM3lTNv7tsm>L4JJf(7TvfY+PMU9J!j-px4aWlEdTs^X!%{DGE z3sozF&Ox2QUgWMDn-eegt{iX@cNu}3D8Oa^(2iY>Pn%6DnaK-UvJ2ou)Xu3Ik*6yG zX<(b_t|e?Su?Crt!A0mW6}&^0GwOt3G~aNTGnj^l=|d&9l^o5vpb9JI2ql9IQSW7+6$tX3N z&P7>2P*T8a`bQlh)meSww?#p85NgZ73x&g0m!fDSn>?bAyVY!~r!DR{gh`jy(Rdo2 zHW#U=ahtbXd~Xs>(<1OHTas>9&2^N44wZ(5&klQM*y$a1A-Y`J)5F(Iqfe^t)w&57 zVbuhD?u6(R*NnnH0B!8EMG+j$UEw^SR|-}bm9o3B?!Qfzm-8B~fr-V`)v z*NhfZ*Nzrs*M+43bK2{s5MrMTsB`T72EHSNf?aV(GxGjiO-ZT{N3fkMJbaz`w`Ftu z_c(+_<3^okD{9b7-*c!<(T40k(VcRK>Z#14}v)3!~pc=yhQa@B?| z=(=VnLJ4tH9r8KyoVM6LM`#3f=pvfng><3$C~Y)tWgMh6(F0=a_2CDx(XitWMSxx} zZBXzHhPFKDqCNgd#3QCE3Z%t5O-<=^rIC|KLN`Gz<(cnIeq+tH9(U%7St)W#(}d0ck4Tblj`%Z7G^r{$7UNoNJ>=z0obDhKI6`U=9ze- zPU*KE{;S4mj8=O4eGzwaupOH_MbP=x-?z*-`+#tFM;bl*5R2&+hgjShW-4Aw3=dJ9 z&6mB$S)9+c$ar^^_6Ah57Uk^dIM*bjw^}^~+Zn9{rs`qkmZa$!W?%yCLngXQ#9PYA7%NuW{TJ!=I##a%ZUiVZ1cVyZ_BPE%w&-K|K?_YAjqW%|@h181!6f=Lx<4O!;~BQ_!R?1rIIa1PdyC< zA6mhu++_rdyzPP;qjx2dwzFjPnq3;kR@td{Sy&nf`b)#o0I}Rf{5`4bT>&m1wwY}} zFX}W<~_=@7j5^x1I2w)?^d8;WRUboZI1^4^%*9~_hjE5mtP_R z`)C)7l0e%fK!fD+>)A6-^RABRp4Bl!MG%?JL{RU~yvBc*l!y}NsPx`rT*?b$gS}Q2 zQ@q3_6}5kvA4Xm1>KJU(W5&|V-AhK{Mr~&pd3bGCM@>4eQ;tn>k&5D6UlL}7_Q{=Q zY~z$F5;K}rc)V|*uMyjdzko%+cBK}6g1ahRmmANBC%Yq_qJrQC*q~fw=DmU&Q|%Sp z04J(a6z3x)O;6$^4^QCUPFANAQ#OOetwH9@4}Sf}TAT z?!IzYA~=ax=)hn(>JSZ^RYgSDu99vHc?lS^gDF=LG}-Rf4I)y-|2@8;WgGJiw>``^ zMpMaDDidnCB9`ecJ!w{<=xhuN5apV!gss<02(6#%twX;JpzTVCg~+sd2Q_FuB_{Hq zmlh#BZ55YXgLF5P9-19Sv14--N}_Uk1gw{~$D+f(%X`8Jz!BUqM!M5Wv*s?053riB zRpl%br7CM#r`g|_)(~5C25r&Fa+svzKX)WV2W;2~yC#cpL#sQdZEJZhcN<3pjANkZ5%L3;Z@$MLF73QK|cN!Exlc6bgUdk5+wTO1-3 zcicQj(OSv(t{9Asr3ORyCFmKANHqshVND}3^)K;v5;r24f-glh{))|)fj=}1|3=aB z?4FkHu57*_Bop8K%EY&UGTYkwvU_`)T&x?S_-y9@{l|g*8o%KinWs?z39umqea?b|1z6 z!ACa5Tdp~W@H-J@6yB93clF(NI}qn0`hd88*Wd;jon_6q@6qdj_EkBluR%Vu@3dTY z`uvLg94mX|!xi&44rn z?aUc#qHM5UE$?5^wxrZry2)BlYWhK}^fdufbQ8IbLB8*s_K0}icj9bNw8+Zt>IE_2 zJBA<`{PDFgm^HKn)7Rg-m1Z4(1NbBaQwt(o(g9#o1E`CyOvIIjDm#_L#D+vR-BD&Q zIZ>2d0K%$9RUy7z*wWbC8zQ>w+NtTSt2ev5tE0n%MANo)^>ugjx2bFn*`YYPk_}k2 z3>WfX4XbwL(UR`VZ12SVJM#WW?dfp_* z*JpziPF&k}eO=|yX3)ca!^${PdfC8;Ps&r*3<7h?H&|W@=%s7Q`T>5?S0>Ly)yrr5 z`gRhX?0fCm9$A0lOz$SE^3uz4kI2Zf+VcMVf$ZyLr`5MEKeItj%Q|0r*%fP7^lx$s zebG0F@N?JXRLWF=5Tt(M;|IVgW>o*OEccV0Ir ze=kmym&^D;{N&;1qj&}f%k$+&jp0}G8_EyJXUtcD`=uN#|9a-iPhBC?kCi{vpDn*` z43=-&AR`aUfvk`IeC{vh?ksDz{10(hj>8)4&6DE>w=J%a{|*FJW#7?zAG&>HMS1?F zww&cFE~DPcE!L~_?7!{gh@A4KjP1MK`UOVt+||~ri2X#&VF3Sqbv?p&#?({FKw036 z&;EWu9@_V+%(q(mH}%VbdO6wRNLgoP$&Ihdd3|!jVfj^ImKf%$as6_pm36RuWBE3D zw8tv5@(W6~FSck#ZoiiJ!GFnPD%`LlAK=RoS@Q6;dGe>Stf5@qeeGbwF8M?GCWdMR z;c^+9htxM;ORN2~@7&>nhRX8x&E?s9t*5Mq+|KFK^d&y zxLNKTwi-4f_<1W)_6*A;tG=wge2V;@u*M%=SW?(fJ+NWuLzP3>vU|{aSk50lyjboo zE3(nshq8YxyWT|1Jge*;kVixQindKMu1sD%XwFN#)ym#9aByg4k9_62bKs%5>&|by zEx)%xKDzI;HC~?Cnkk?WyVqSgx8tue+RQNkotoS6F_~`8H>{M^>v{&d zw*PeC*8GjvkF3aVKO%45H;AGCA2E1yd4K<=w#@7$sQ=?TPhK7d!J9C_{K; z=P<2+-&*wz71^@a>NB$vhK7b@FiUQ;`i4F!b6>UcmdIUY1=oMy%u0Ny0?jl6t$}M! z-f*NG%UE{53i@reb}cK|X5A_y2hX2>L_V@FPkvj}Z*_Wg0P@L!K_I`*2_7F%tMseEbDPeL49T3q z1CJcc{~e8&+(QHH3!K1jz{&_%(-_-HurF|qvGoC~;aT}KX7p&A{Jt>f8S;UBnBBh# zGuyc5yX_~>AAp=$Cp!nN(((p#X=3H3mL=w_B)JQT_F%xRx8x~t?#L?*=g;@bsVBbn z-P|>oo!nf$ac909XvIJ^JPz{PeeA8w>}=WJDrcWlDe^bw=C^HVkdenI`c;meeC+%) z`Muet`Oj`1di3Oq1)Ho*`-!aM>QO+0+;eP5P8mG%ZvOd4tnA)1GWpzVR%U+xBUVC7 zzDzrJW@Fnc`7PN;5qbPmmxdmc@o!RbZO;PniM=-ik&I^Q6q~QU`N{|7gwcq!(TH!0 zb5`HV=er6wy>aJTEAnNqwP7eTd;1Tq$~9KO>OYm-DEE|YK62z}C1&NFZj$~Vjy;F) zyWPYJhGGXBtm6Rxm!pPa`w;$Hci&E84EtmIHl1(C%wB*3bDtflK-AB=NhvwV$^OdW z-^RQtv(BB*`37Rocb`D)$75eb_;=lX`40iQIo7J*G~|<*ODTWT&FoM169f`sV*_u}{ z|Md@bA8(Ms)6b%Um$(Jba|>S3E%+i@AeYt4vObw+wYFJD+N`5PBRL~OBO|iH%CoYq z5xL;ByxgisAc(Y4d9uGuM%A}tRqKX7(ruB%3vc+horcTZr{w|DI$TaX47_-lICA~4 zoYN;a4a-@5@`_v*NF3}3k z^M+xKXW?}+Fc=uB9BIHT8zVH;fmZ&Nx9=M!q?ErB!#_vBlmmkh_v0IO%DW)^&gBDV z+{$TH4wfM+2*G5&@r#>o{qS4zsq4;NZaws;qa!!4E+wxnJM;RQ%BSS)V{&_*4CaBg z?z|kbuV!0CY3XKpRhI0t2IcH5`AL~&9q!+FX7i<$@}v7&@32ljZzX@jT4YTvUs1k& z#j2$%hX%~KX`tLJ862*#c3Ef2SID-!BUZ(b^|kf#()tk@n`O>Q7%7rv*6=oY>)tmj z)()7{63~^;?ISMmeKE}8ypsTaB8Dql)~+0S>l>$T|K<&=u_UiLx?+{JaJpL0%^S{P1dE0eh5C1`lb*%5Pg;szQ2s`X>J#9VAVyrN!u#Rc5Y8kx}Pz0_e|7%A>jz0AyY0HNw@~u0%`DQ9HS`+= z-Kye#tDuqVXsUj1zKL`<*5$hhzmvPpKBd@fbwA$tPH?1_e+bX+i=j#<$T5Ttx z5m|}zbF!^lA;P*au!%RyN$0H3$lZsF( zLq+bqdgs4gb{_O~Lhfw6$2wXrqYhimN93N?HaYR|z1`amt~hzLLPmmIcOM(6IQZH= z8EcijhRPfATTaS^bJoiIHQOID>yTar*RbWM7H6 z9|Vp8e0X>L4R=`O&>5|S6{JJG6rkOFe)4nq73G(RKVYNN~+>O?z={5QX8Wv^(sN;X4_8^TUP##nEbS6osqm*kCP z%T^28K$4kh$Tet&+zzTTGgGX4)^B>_h5U_j&0!EA7SCZbGg00HGQryY{RZe^78U@& zzQfj$jq*0*%|EWbs(KF;+jgrmKU;Pj!ZHYz|M%D}*4jj1$0pC3Q1On#*=kJ*!ztV4wKiZR1XhFkU(30KIR=UZ0Enn^$ zl<6m4U%oQeqP0P4{mAAsBl#`hxyCtbk2SY+Re$-~25bk;U3X00YC=7I`?`90r)iB} zQ7%8Wul~6&TB+b}M+YpL@IMC20DNSith|EM`;UUFe_0G-KeMvo2zcTRAGzUxd}psU z_%SOP={_-F4VEL>Z#dVj17)1)hmph0GV0g?`Ov=8*CW-h`)S|!$;d&3f8MV)0(VB9 zleg_X{93h@{qgdn%`3Cp)}Cyu1b3Z?74#{ZZrSdC#^R7TThaBWdgXHS5KGk$0iIYbCf$|k2n=oU@n{O?zu<}PXHw+zxY-nA1 zq~9uU!Pt*~y;|<7UkRoCiu{%r&X?vNe2ZETz`;pC{;Jm+PlR$ubYCS(|9Nj-1?@rZ zjPCm|68XCEgC#{N|Erfr5DAg)m%Su1J{e8q{|lYx_UOKb{0~D&{o&Hf7QEFqRCO|Y zWA2e`IdBY;jt@Fy=Lu{UA?LDB(v%xl%b3&P)j7N6p1va=8akQZOIW$HUQT=U=<<~) z$KrluEC{`unz7T>-MM)rG%?dXg+^`t3FN7rK-kStO zKmuZ|OQLkOCUI$NYoe%KD5&NA)dg@VZx_I>v<+_EFsQY)t-tS?nKRG5&%FVx{ruj3 z{{QzXxo74%bLPyMGiT16nP={mGB>ajYrA)4Zs(%f4{?7!;evf}{!ngdXc8rVM}H(~ zawNTz#Ha(qK04>X`_mh0KW7iz76{GATau13)mi(vy>vj*ZLr7Ewl(RH*4uuyYyCD2K`|2AGFW2CXX)_^+Q{* zR6_BNJ$Co2(q%>;rO2vkNin?Q(jn1qrx5Y#nojY?&33S7X4cHoybgMbnAWrgwag1j zQA!_r$->;VlxdM&yJ*m!fCh;_t{W8FL~x4u01>Lsh%{sb#n%M|2xt;|KpbATvr{}I zc7lN}@%p+U=)PY(B4{mla9zLn28tY9m)0!?#Llgk*KQHZ6`v?uXLld!6z8Uim)F_J zrQ%7kQ?XPuDE^9C_lUvV^hsjurdwM>ScHx}uqguzPfY6v9-N*r^~j=uKiw)@3TAt} z=(F5hDc<$yS350zNhyL#^_b>MTT?q9qfz?P#+=6>nC(e9Vl4&K4>rIUzkC*=J~w8xl=kA|1KO4j(#`iz*#!9Z4l44OQw{+BjD$as@NE+Q@RS3k zi^NzvO*E&7$$t3aW5szj2nNCaclbNSqw#jy%RkDfZN9Qs2djqSxpV&SO8*}1j5wxrKUe?lbWh}NF}7N@3(K+X#L4D0;y zox3{s%J@J1+?eIL8-G99a+V_9)vc|(EDeu)pKRbg!hN7QyQ@Xd**#t_tb14paBvVI5=gcBc zjB-@i0V|Z^8-`RkWSoajW zbj7tZ+w0-*r-Sl=(LL$nO~iG+IJ$Tvsew=8ubqJ^vS>(NmxjEwQX~gLa%1Bb zOr)hNim%H+)<((FN2C4XTY$V`A%*I%N)xY+PU#~i{~jbJx7ptp<9C9|M%({h>0_lL z(2ofE&QehcHqZ4Fi*;bJ)*gJYQ+(cgpwoU`q-?@p={It(-S8Wdqjvl75FQ05Ak>BB+)=? z#16Y-{x5dC~P)W|H(O(O-G(NBTG_&u}!Y+t;m?kh8wUO%&O zVRI(!W5S`K9{aV2Ci@3A z6XR;Py2>W}=#uN?xMob?R8AD=9&$|?Fe8scpy#*Lb7Ga4U z>#Yl9=oK_&#y;;R`Y!n({T69_U%_^`-vYGpD(xYOM7i+nx zcIuR+=ne0m=nvjK!r$N8Z@ebw87nSj54`#BO=$~lE`4lDTbn&@gFXJ>=F&q`I(FFO zj&zoGPmw!38)e~f->}EO4)ys!?&E*9!{0h1{SeacokGjK+dFcWNss5-68VfHolB=6 z;5x$l4VfPQ#%9`YJ%dJ0!=Oa`k$f=W$V*C(NvXYY_E`w~0220q4whd8FNHG1a_lBZ z;DR*z!YGxgWi;4D$!_ItwGSfYMF?c<>-KE1Hf{FQeO0A_ys8zoluz44UOVZ?*3$YP zOV9a5l_4%4grl>prgp~EkiBb!xDzDKppDAc?I*7SEqT3AnDK2s~6X$S0BNu>L9vv8sdt%D@4c6g`Hv{%{mXCLR-IwJNz;Z&?krPuRAs^ z!=oOV_#;*zPi^Smd(S&m3yxiQtO7aEuvVjt>*$Y7gH7#d(=tU|b^}7+lf58vIL@Y3 z#lvg-fn7-cB93gsLu)oI+bd4BrV%0Q8Ttb!mA+{CXdRs87 z+TD3rp7hwWZk$!uEndEPlfBSBVn2YU+-s%SwRX3iYVQ)izq#v}xZB$KOB`QF6OB8? zI1H}FG%;>SH0Fq;pmoi-?@5PVv=512-#lbpJl_6^cpQ-|G_|45-b!rluxruz-Kps_ zteHu*)-@AEi%nM1Yt1+f`@RbEA*mxgh&ZiZT#jFHg|I7z#3&r( z>Ux>XyEU8si21bAw#4;>fmF|}C0hVdsPT3Mkmuly+bhP9ZIp|7924s8tqs6G8f#CL zYhv-t21xAeq29WzI{S4ycM0N({(HK&i0vEfowec$Rjfa5t8l>G4(tT@|FZ9)rCY5lCStSBzxn#SCIn(-4P^+8od(yw34$0KEZy~mUN~t8 zL)bU$vhdSu-p)y6gXxEAKiT5$Up&zU^Q%ve;b(L!)Vk1R*jy;mg?H>R7!S9)NIF&* z3AVZbYeV%_>gc4(H?S(NeJJ$|Kj};MSS4Dk^^vqNV~;1sY7>^U(hi9TD{h`Eia4_w zYEj2D@g&T=8*dHSECXfgqa8Mw_v09R5C{(`5aDK3xeV@qSk@|3U% zfc*e*$QsH8*2ql@tMc*?#eQ%z4*u*Er}}Xy4LdU8U2hJpqAdG?()5FsH(#o@LtyZyS%))~1zoIUxx zY>ILftqY_(Yg5eFE8~zdJQ=dConU9&l51T)!J0a8K|a2Te^E<8`>DIEY2(DFu=6_g zLu*QcSOW;(L;<$^eA-VG-#OJzKD0>O8uW|zaCqac;NU()3zpD&@bB@63q0|TJy0zw z4*=)$z&Qe(o-mw0I5^`D^okDyIbt&g{6~QvBJ(Jbxnm5Gv1iyv0%BuJSEt?m-yi2+ zuAMun0tLj&s}KAThX${yvwwc+8te}Ht&2|&+;dmmZ~Izdlb39vb6f2=4nXo6VHMDf zJ0cr@L|o5M+zL@|C)3#k1d3_Z=atq>g^n+!^cv|H(m^V5>QHSi9fJB(BBJ+*>)Oe4 z?C}&F%oBkg`z>jlyQhg(yC%2WPRcH|(+^^s@^UW>8;%Ny2T$wyD>ituS0h&G6C2y? z6cWV@62;chLw0Ywoj&7W_KLR==jaj%K??3X-M-15nT3-K=((;23Msxdp8S_DG|)nw zVRCnmj+e_#oDjATl{VO$uV0#HpP^K|+0KF5Z@01ch|uwzpglI-hoE%2Ps*UinmRU4 z{A4|t>9nhfnWwPN)!UBwe8#e@Jo^bvWRQ&d7;u#&zO*5DaM87kWO1r*+pdRxuCSVd zsOj;)*u5Qu_rtj0t6vghh%w8$G@-OJ-9B&nO0lc$fIV&@txD?b*TjTD#3UrfMdM35 zb6*3F=%^8s{Fq*LmXxOdAb1UKnHhk7Z}zTpTUTEjlFj*xvP+ zaw+xbDvAoexp|}b{^}vxxgNYR%`Ua;tP4(m!w%6_b-H~Q#D#;PHU-MQ9H6ko>tjg3 zUk*qCkJ(9)TrXTUge^WFAV=|!7CpcBW;&{JVfJFZM;m1@uwNaG^J3$&w$0A~j+ZuP^M10qZINBP?MGruQkOk0 zzZnM@a7@yVzl0(ls<6A@EQx=dlUBRjKKL#Sw9IcFBu*^*$MP?>84lRJrJ`uiF6|U| zRrJ71s_V6`JpHb_P%RxO`Sm%QL}FL3eGnSbE4EbZq0B#=)734$*Vyw=asKoxr&(8? zkvj`VHuoHOxSr~ObN9J}oqe#_{qKp>hPIRz&suJWM9G1C`~Az?#rtC^o5T{|%`?cJH!Tp5ca8*>|1?7nV`Xvcx>bb+C|7)NW+S%DgS zcT-qayi_(M7xC#&5C@WtZ3NAyKO{8T(Y`lZhW>2nK;pCyvIUJv5g@Dw?O9)`d;T+U zo|FXJXs~$2Xc^)a=cEv#s3(_kq-dvSBkA%KTZmMYR((A*7;|Fs`U^1 zJRC(DMaNc8?|HV(UUZO}E#hRWuqmuuUNAT|ZkwHJ_g+e89eWmDhO;GKh1ZPEu1m3d zVGVHV277ebc^{=`&76smC6Cis_BrCb!6Thp_Tuy;{@sIrBKH7J{?uZXLPr+8_Pf}M z27d=I3G|4&Hqe2TeI5$Ic<+r1#@X)?mkS2$W6LNw-+@hd8&kr225)WwHr1)|9bvS5xsHAM5M}i{&CQ4X(Ht=T|1SZV(F!YgW?c#W&D7 z}dv@h;ya`FykZa7Sl?Z3`>^KfvaxQff{@Ra zfg{Xn}fc#MwKq6|kn@P;{*SF0eIee2)zN56DJon=M9q^XuY?lF53 z1vf1^Cnl16)L>buLVSDizwdMaulhW!s4IDNZAVJ8da^5JWWJd>0fLS|n zgrXM1-T&!QyggA%|Li_72IuF*BV+bJ!gp6}!sPM6IW)iBRzXhDyXWj&*xvcrRPmYi zLAwvx?>CTBdhd9g`c9i^(zi?Jm7ghxwFXvXoan^Kbny>Q8eXSBq$`IU;}^*ny#=p6 z*}V?{WoGL=I8=Fs{dz-gpuz68t{+!8V<0~_+q!(b>g&Z&zO#q+!tunkiAh8>SZOpr zh_2N;?NG+0bMeAPEg4#Pq(z@TB0@otT!VF9s(h)T!A`s9>476Sw)22kMMuYNL`v55 zi096N6NCo*xk4U?+;&bH9n1{`XCdzo71YR{bI5D^Z3TI4+u%`*?y76czGde1*5%TM z!Xw`&-fbJ2Ms1S*^V0-cdzwnYSJn@brq)3(5kGqRX95T1Xc_7K5WY2 zfKX@d66zZHHphrK#O}ykkFd$UjkrRBauhe()5K&s{~%JdPdvM!AM4VTZAw5B#0>~^ zb=Z4Cc$=dehdK7(ovHyWHt}*JP6em5bz>IZv7x7p-0Por*qiL$0(d5&0?@~i?Kmrc zLT+`sHD`Qhr~Rd?>|cKx`QC%rSp33UfGjxb$v6gjVG>TVTsh&0eF0t$sk5>Xg71Mo zt+_O}_exk|vM*jykJFIi(oJGXj`+stJ;$Ne`_A*-WmXN3UTm4j83sGO>p7Y09*Ce$sc?NO2Mtg6by*SUh2>mc~RY;85X=P3vScI5o zol+~j%^*g@BgV2=bqHL)zl22D9&AaAwjL;$JyVedqbZMrzIM`SBmC)Y3ftgc2 z_m!ohpuacw7|w267f&2mGIiSWhecA4D91$l2G)@ei@Kf%#og=e{+AZavY(GRgZ|$8jwLzQ- zrM1snVlNZFUXR7c%&dkm@A{kYuAkfX9r5${;1C7j)}}qZc{9R*=PYK5)Yo^#bF^5rri zJ1DN`7sYAzl7r&1eo@jdE)5<$bg<#Rb}Z+`;q`PF{Q)jU z&6c)|mO?)X^~?>4_F%~F%uZj`D;^(B$AvFWf(b#VHu270mP zs=2!tL$BYOIu7skTIZh;y1Q1qG|E1Jy@^mQ4lf+Qc}Y?07t`>H*^ChU#_C>i>P|Y9 zY^9IeEB?>T)=V#6cDu&gXDGquiY~szT{2Yb@xC&@Z-(v3y?ZqSM8p zo72Rv+A;7x7>%tCA-)}?N#>>a{w6Vb4~{+7OcmerrifF!9uMukKKBp~HLf`_BUCSf zsHR^WTR&)L_gYgi2$HhX>+DB+_jPyn!NlRMs%1T53kGd7y;*RkbsbKi*m%3bx^kR& z+roR9S+hc+>+|hW>~V@cH`Rz8Bd||+Q_b58^1mP+9nmEY-GtbBXX(S@o|`s_cSiW_ z40t_ja?X{HC2uU5D4_#I5W7;*EA|HEf7Doi-2Nq16j% z5Uh1J*@}b=HLwk5L3=K-kHz+It~_uLtd}+=0%{Q0SYBuE_i8 zfc-|GEtLCRgi+-2wb4D+<>;jiuoBjkB=I?{8&OkNJgS09?v&=_1$i!WXCSQ`!rY1| z%0be_zad0$@TNgTEAf)a4K#gKEU!So74 z8N}8{r~qe%aOCV~F!ZHMLgG)};AU}1Sh?1fgdij7d&p~ zwpE415ca;j1LD{^KMuRsh>b!YAyk9VmU{*>NR-k?Ay|BEF@3pMGnm#A{L3l`s^AFtu;7Rvh{ z(TdiNAa8vH31&na{i&`O12@66*%yW|4Ua|LH^MwpnjEK2Cp7%>VQmBdKFsz=V=R9F|v#une@Y^cEy-)m zYdGjk-;^<=t?3b40m)bAcXV{n6 zolCGe&;yBGK<~45;bd#d&^r4(7$$pCx;-vEfBHg^fF9aDU|l#aqj+_9cBtVQu}{!z z*y7ktJ>pMzdl)Yhi}5M;(#L(YPdb0_Me)H+gW|~mh~|l(Cl1+9EV~i&Us~JZJh2zr zo@njEmwDyA#zjuG^UYN-%F>{u(Vm8J|(wa z+^}arzK45k7v2uSocHj}pysjiy}9CHFC>6I?}2LfIOIEU0fzW+-5$JbhKb~_3hA!( zJ-uz>fks%zuVFbb7q0@KveowO;w`)kYbTYa^64 zEyHai4S31y`u4z;_6k^&Ca^uWrW9sy&mpu4@9x8};jM%m@e5B{>45n0P5r(0gRhCk z8tdw$8Df0TKwZfG**6{_7i49PxJ?Xhv-jHP?b}gnC;eEQF=S7k(pj2aE8g*d&OG=z zGt$HyznDpHTKH)b|J`HQW4gv`x7uH!|90#Urz0$#&|`nqnwB8Gz0S(;ihD#4&e2cJ z&aK_I<5=iEJ5#*3c2FD}XSx1{i6Lc{=I~M`;gviziR(Le&dOFex$vJ?C~?W zY~`OMnY%`yNp1Gv<*@Qecq0Sh>C@n~^kyI2f~W_c#miGySY**GaHZ{kd_jJlJ$1mY z&b6-&1rBD@n}bmBcc;SCLs2&`c~HK?K^-OXF|42W^dH0P<8)|sTXBOqY?7>6@1Dy25vzuX9C>kmoTuG(u|JuYizJtBaJsN$HE_-^9?aXDF*r;@q` z#P&u4tL1c*NN?%X63QiRW=@c+07 zJ++mUtIO+~PAmiGAOnOGE)Wtya;6r+IB)*zQ@@dauR70!cCsC>hH9|j|Q*nTs%7cMmc`GR# zWav_)i=|S$FpLQP1(yExapkEElm$X9EzOcuYJ|S!3tWdEVL{S4!V*I(4zpHV>3!%Q z_bx?@NL1~4?1s+Hy2Ytt)E?}oq|BN1SSVyaPsc5L=Ijk&MynG^)~B)f#hnc)H}#5k z9Hrb zF8hk5*t_aqwX1F^opbCs5PGKbvMsa@{yr%XK2|?we`R>~$u3#_~)+X`Dhiu$oo9pw!Dj__G6D% z%&HNYelg2VUW#*_w~^6+ zOze;bamJg@7m#ChZm?Q}4&aT(o%Dk8So=(hJ~!Dp*lNV;x&}8*97w+(;Lav70XNKa zBCwv1jmsJ_2IslXgHK=4lPQn(UD@f^h>SFxm-bH!QJnXQ4Y+~lz^<<@3yI}JKf;+g zKf*PyuO1M_M#*sd4YTmx~ z)IYwHTZ+ZXSiEV9vn~5@UB%`y5gNq3a=6g4en?z%K;-Tb z$p;>PI=AHZ)`4Epd;pzEG46>yc-!B)402ux30t0}|6VzJAhFdLE=ppa23bedzqyWZ zQ$3}zKESn|4QX4RAO3r5`xhrj+@V@s$%~njH4$NE#hk;{qd(cFwFbX&G|JmH<+e+o z5I3friD0mO+Zk=$+3)Y#khOB^tHC*OL z%#jnqTDoHuZ+v<-{ZZuRi0L^Zt7g^`n<$B^{TU*E2rq=bjDegZ4q^UyWJ3xfI@q+b z(-w6R`|CF0PM-YsCH6M>No#YmiczyQ`AqRo1g>wze$n67r-<9U zoA4Gbjvx&o^K-~tlL9aeZvx`7oguLiBsY0;Py~G7MF?W#BmCIkl1`lY{1u8kiXw=z z{R%~1M3Ks&{I*)WO_+nWEhOa6;d(^G)NaJ4)DW%%qyrva913bLU2ECU_>k1bf47%5 zr?9xJre#{HR(V+JmSWvkqu}9?dq|5*%k$`egks|M;A-3(ye6hi3sXSp3UfnF^Ny2m z^wQX}Jm39KX^68{cG>2zb~v{d>yflyH)^74QkR@==KcHpjMeplPjEN%$6sB`dwxB& z)j@hwv$>|KTz74R%Nq6y0>t3loE!Fb=kOwQ&uCO=EuuBXjnVXU1m-Yn&FL^za5`z@ zGWA&AU8xA+l|FXFu6>UzQmr_x$3M#+S9gL&6dDyJ`h|*x3v6PTBE(=PM5JewC8_6 z|9_CcI5hGjd=NG0NFH;F-3JRnpR3guemzFLo0PB9nF)!V*4%{Dn?@%jX8s_-&Wz7i zfPTJBfBST~8FF&)cxERg-f7KFIP(sXnUH+zh|Gjbwv5b7NZlNlnJ~Tcl(`8jts6%t zOb5l(%;yp=$$UN`IrD{tGiSe?kU0C51Uon0`sQ&SXU1C_kMnpQeiqnt;E+B;%hVU)fqQ8!Dls%20K3hJI{fg=M&BZONn5~o*nPGK-1fwr06Zu zX%t&LI>DYF-;iKa*74-K5UZk$kngR;&t~GMbHtoeuOGk4Bnek-|&IK-&KdQ@j$G|0&6T6q>LhMrRL}%j!#qZa{>7boksGXZh?wuncyR5NsaaOe=llj8fQ@mM< zrRQY=Wtp$kGZejB!|4sjS6KvKbBHgJ8}YSU(-|F32W^?B<;ZyZPZIC&N#Y$nNj%S) zs-5_q1Nq^8o~!x00=d+VM2$yj`fxvYin$3HkgC1>2P8uL_?5!X(D=i(o9X&A-o=ut zrVIHLjV1=N{pqX$+A%8@2y#?x>mXimJ}8i(B9!JkpbSo5DBS-2tX%*{00G%~bD=wE?Ia!rkJY2adU5=ClpGN$n zcI?*WzVh+f;fZcXPP~;L)wmq3&PHx4FHn3wE4gsw7JJ;zP3ZDs+$LIG4rSST-3qL< zbUTtSRCK*^jpWe1oBHD}>W@1|&Q3_ZgZg6&^~YvAGa;*U6xV>?>Ts%<{p#!=QZ?Rr z@z!r*WTSR7&Mr~)=7h^Ha^B976x0B$&OcI zk`p{E5s%Z|n%-&`y)e6yYebqKpTk1p@~KxSewMq+8#}ljrIqnRSppPdF}|ohUAp{j z;pK;u?@GxD`#p2GN!kyR@@6?DPf>hr4W~PdoQf6Mm~!I&+pg)gyXb|? ziG|KM@-9+yx>-+Lf%3#(;&esta5z2mlXbi7pxN=(BH2>XAHqMX@mFdGn%i@td1paF zmj(Uo!dv$ds-zV3bThxr)%E!1D860^=L`12_yyKi&^mGq=EajiBxr7Yt^!bo<{9EQ zd9I=}yx(KZW*bUXksYLRExO!aC=(xU=kdph^+?o^z?zvpG`=O>d5WK`@NohAdSdzQ zr}6Exeji?glHMptkLmB8ujucSwK{yCi2mFJWk0N2qv?wUYW^qwyA~+=$MIj4`Bt`; zyf?Lo*FBu3<&c`C=v*7lr|w_5Zew>nj}+ILr&teLbouwf%O7VwvXP|cvF>(SCyCCF zcdd}HJdhM={LB8zR(!hGi)8LN-avR8HD1KJ4()N~qqRm93&Z?t?zh9b{O?Do2C=@K zsNWVO9Ho}Ei2sgZ_fO4^=kc_Ep=!sA;qn@0{*ClZQ~{Pp-=gEogX`O_@jhvN8+|8N zUzf)Fr1h;VIDUOqtQQ)Oeu9xc++VT%`UMFa1$t?tB~rqyA8FwEbK?smb@F_vfy2!! zWVie9kbf9~>=k`v{jl3*I)1Q9>*v*YM)(;;s$CI&U4(vGHyH&52Q*Hp+_6`ex~YI+ECt_K3>+idDU{KDIxjRzhMyn84Vd@y?H@`H<*$Em8DwY*2oV-w$&W zS`e48tlJ_*?#+y+aY*#~{EA+&i{6RGp;=c=jK%NV_@JimS*qx-Q(`iDb7K12X`H8u zD@HiHvphy(#s5@{Yy^O5+)}$XmZ^G&i>EPO*9q`g?tL0B!zHKK`pEI&vu17(d1;w``Qtz=5YX-Phb6^dT(Nzf}$ zt&kKl{ziD{xVz5D=TW0_CaQzAD8>#Jmo>lrQblqWD5> zml(h6B=MQw{ThE#xZXw0V``K??68RN(dw{NW<2Zr(Q3sn&E@oAJ32@68AKkn%TuH9 za7VQKoXE~7e?xe~tby$AxiK7$8x?0NCJL2+yCvftQZMUNy{lBUioXcEtxA(REQnWu z3WBv-dDfvE(b=f!><*V3{H5djvtoQ0|2lq$7||SuVH4D&P-^6oMY6zh&S+5WaId2{ zp3itbjdw|Sd!av-x<43i;|cKQ>UM9}cx2z{Bl|5ve$A3`l38}V3h0H)kLycZrT8bk zr4Q>#iPY-_W!e^P7jHk_I)2HJ-I&940ASHk_T~AAss>dDwG4@dIevv_p zbog2Ro@P~kIK5zdlB)5>hRYwk&zJo)Kc4+|)(@Y?pLsIv|5il%7t%_BOvAA2|8wD= zv?#u}hw~FdVG6heVrw2whQLOTQpThnwGiJ zUn4%Z2UI6!=0Vaa#$Te} z*RI+>+SQMD#Ig?|?kH&=^5d-*Or)*yR|02aY2c1*14tSSm~E zft24GMemO;K2IzMz0No%h8|$t(Rd*GKK&~M?sZTse&t~T9cde`--&MBWb~h=>)!7) zc9AzLbK)1H;bb7?P8gT>tyAsxx#Vcd)3zX$njgPV0Sb}qCDq@j%P$Qt54~F_^(`~r zul1bqJvXcRBK&mV*Gl|(2A}kr==(H&sf#|ZQ~k2sTvLwpgUW5!1vMcE%|H`jzI z#N7DBj;>Hq<~w=4;@j<)E|&Grk6-L+=Sq#gAiVyt@yPgO?UHxmJn8S``-^t7r7(s-wOR&G%3SnsN5xOJDZ(3wg^VY}{1OeVv~>9D5nZa2s6 z-R(}@sQCH1Yup{5pIf5&aplaR$rT@#@8MfiJ-wF7XFGTN`9wSyF{(+t)6v&XUD|zB z^DD`B<7QRQ7*&n&^Qb7T5r!Mj#OL&jFyHI)p9?R4LOPp&Dp&5;5q-~{ivB_u{o{@= z@%1pGQgab;s75!)b)i~zl81Z>;uJkXcpEJIo=>NAIWzIMZi~HOoIfNZLbAEgi zX(fR)UrIgvqADMu=dcH1<+qsf@Tr%W!~%H=N>Q6H_X~*L$}cH;9pUnfnt#<8`J56R znF&OJRRe~zlNaFe%F7YI)_4D(9o}BduY6vP=550B+^6`M;=(JC^LB20p0>+OH&x?L za^bTd!+1W8m+ZnTbjZoZi}BF+h-J$)K)xOfxUWoq|!jW_&yncYEo z+*IvXqg=*Ul)T*Y*8<%xrti~uH@MnwWop5y1#>1ZIJn$)UCur4gz4D=qgojMET6>t z6<@=(oAHuQ5-(Nbx#I!luKrtjl6YMwiMLzh&2Y&r=&IM#quP5Syo?jz@i^G1@gn?u zjF$@8U321VT=nnQ_z~-sF#nbN)7Pu`yeqstk#?goyg$jF%kitrz3G~lPBicFKC?J2 zhCRfDk*4YIe^Bv7Z@SSZ$}h3*09)jk%!@BqfW+hSeGh%I@+}Xm@)7&!k#bRI^dR>$ zv*N4S9o+MuK z*H5m!zLUh;sPWwM46lz^5Bg3(Z!WZ!#?yX{m+Tr(cf|0g#bV>$kq>YQ%&a zq1s7rA<~D}NyGVzDhg(OS≱D`nl98gtUox23xjgKn2$KQ8RtIY$7m>iwN8-2)6 zp?3E5D>{iM$)EBtXsl~5oTy^^saVt7KA`BWbkRG(x^RqC|4O)gPaI#Uh|-HJiU*pN zE!mOjM3U=C-lgif&t;E}KdvHAk4d5kZ&3&`vZhSAPcHTE8C4IxL{A?cXJP(iA(f_S zmY(zYOnz3Ci|}utCnj!T<)K#PA5ggq@Q>>2)8%AiktgeeUlef7%ZD{yDiy|u@%UWL zT;vhG#P2IUY*&BZ5o^4w?O7i1as_VWy<5?tHRdC31?)+E3ue)ZueeQ z54~qkAC}h%^waEMy3D?@Ux_a%x)I|m%Kj+(b(<75DVf*swOyCL+r?K*efSJ_mYl}3 zw~se z`LX?Y9&etXEBfwuvNc-`IOfBr@lrl!d}TqxVTwPk6j?F&h@UOvfHY1w{z~z&$ki_= zZl~HGvdp`b&arwgdWgsG{$DHl|MfBDh?9Y&_Zz+9QQd3mRVg*GoM!Z%>**U*^_=yw z<;3;$#t_tLtQN-K+x>>Br%$Pc8edWRrsm(}+#{_=V^@hw&ER#!Q=U4$7e7mYvkG3}Zo|6fHJwy~!;@;CnL9~57o3D+aYC2YQ` zmctEPp2=^-5Ii^D+H4-=nE5>QPl}#9?s`Xz`6Hmlv3b45Qg1Lj_QHBn8-Hm}q~v&f zb^Te@6S2;R-!R<#qIx#$P!ExW*d3=qX2^Xb8ehpr75$%t%f&hLkM~DlCMP-bzGq0` zpB9b}Id%%1Xr>Wy)N4_|6QwSt&Sv>19#iGM9Ih8Gy=0pZc3>?D{^5LMu9F-;XS=5N znaPSE&m$+Y3uxNu;Ib=Gd^*Osy~W~jz0K=)r{pgZ{j3}5&K7-tg_%6asquoEeb z53bB8rW+xKtB=aHpd4Q@e2pw6%e7EB;)kBE)O1VqbMUj7?u(HAe)DMDQSk$?^IQU6 z&6gNdAC=p!%Srx_Hyj_0c=iGC4{Q7bl8U^)W4L=VT2>EpO$N4CT84RK-VeS)*SCAN z(#sEZeNx{d<`eZ`IKD~0x6eg8^(C`YH66&k5chH9#4l9$aR5c)9o2aC8ZSbQ)nRg+ z6CW;BGv5*)RNqRzMpV-ojz7xx%|l;k{1IXJl+TyAhUdr9%L`EMi@@*FbjmfIaQ-Pa zPIim%JoA)X%k=zmqI+1nyw*QYaFvRzu~^ezIbYHLtIOXw{`$il^f1eh6YZC!p}wy9 zkhi|9^NYGY=wF)>g+gq|Bkcelpp zbF$#W55&3gC6RPJMT%~>Ls#L+(UlpWr}(%rfyGko0YhBpPAoZN&LFG1M1M36^*#3p6<~vtJXJodm5W7SC!SYR#)SBHGT!6 zzOA}U{t`r}g}#H;o~ri3>heHylc#QOV`G-Q_#3#m&^OdtA6%ozRW>)Tst1Yk)q&bF z`r#4}aOcs@sy^b;)7a9AD}YpT^!GlRj_`U*S@c&eJqDjS;v;H~V1UsHUbs$jR+*DRyPWlhb&`kMMmNrOqKzEBkg{tl_QAjb*{s@}@vdb*rHm(dIJTfGe9< zA80Ov5LZ z)kfUS8eTwF6(Ops>Q<<90J>3D-q@&ql%%E{)vMm}RLnI(C|=W2&3vjVwKP=?n(fN+ z%DM>VYeG$x)R`z6FzwXHs#8??*6Q*q4=(9!D+|=Gtq$i}$s66@sB+seCZL$O^%i6T z9_U?bIZ2q5m~_bL)G|`P^2Rb;_SvS&RyJ0bw`#S+U=5U+n?bp0iZvR2L9n!%v#Dpw z(GUz>rK8~;Bt=RXK@16Cg;1wvs1D77T7-2DjTQXl4kQj_$-JkfyfwgdweBl+8=GrA zx;{A)F$6tz%>me!rmFh#CXW==aH<%VPh(S6!ou;i7dHpX8)J=qJscH&MRUM|fB5AM z*^UTRR2b4elFqQGv;^6%MD$O^obUm@xV$k$CMHmcQBYOgL5&6kZItw&d~I`JbSml_ zVRoecp*PW`o{CTn4YpylQ!&71%d}YcNZ43*k7N>)mKw~ev|X&@EzOM><#gdO%ti}| zzX?{D%vZouZ$^I@Z8opk@NiLyLEVa9VrXfs4#HZ?+p%$Le|azz@WA4i1+}s&J1qyT zQby945Nv!|Re7*nD|B;H6{(^$<#LG08d~ZxSQP}uJ(^LO!B!GBw6ad&L|Eg9F4od8 zWnlTsYc*x)NtF~yReL#1m?W+y4H8z3nH*&0{Bst15QQ-xUf3C&Mx>g9P*ZDljkb;Q zI%(<$RVA@e(b`;IRax#>m@sSyONz2ya~ClqC{jw`=z6IbWJ|&gw&o;KyP%Mjp+?N% zMmc14iV|Dq2#cV}1VR<7;Ut)L8h}MEy#TFZumP+ssGc=j))c8r6@}F|hM*0s#&SM0 zq#0<1*0rm_=crSAwj6>q!YVLDdD^vY(EQ-nM4DU6n#xy`7ZWxgMVdQ}EJtZr+w{1p zSgqNUV_6SkU8J(Ssj@n3BGuWE(sqw!jTAO*>LI{mL?gKMSE^)$jC4J+I7W39+DhhG z4R9`AS%DdQOADVlT0xY3aHNZs^g)z{Yf@M~m|z1iGW-P%~*(gFp6GXeipcT0V9 zn3dCcHBC;#b#t^CcM3_aD>0E`fWRU|dyep(;rUjFS^fHmDT01{tg5*k6E%ECawACU zW{OaT5Dpl+M*W zztbSyl8S7ejTTDxHDdPV;Z#O$i>D&95fc~O`|2X?hS9IK!SM}}<5b^V8EnKbt|DiD zcBsCwN)vNG`B9+!-M^d2pcWk1*v7kVOx1)gv#&;b6a57NYmQF!fmQ)R--Slc23b;uHIO9 zRzx)-X%s`W+)_oE36LjGcBfj7-vA^?{#BH7$Dexy#lkafO<5_(XA;(xFO_DuuB5Jtra~Qrc@E@=?Et{zr4fO z+z$V>AXHu@6`O}({_LeN5Bc>?PKSnRq;y{#i&PY7no`Z=+MY>P3(bIAel()fLlvgxjz*ny>Z>ei;tqx!1dg_g> z^aNKUvOxpK;a0O+E~TUlCM@7QvjC5^GNAG5@E5j*l9DImK&xFTp+Gr012uAgM7kx$ zEn>}cO(RkZ9A15`&B5l%=0-F5z^z3H2jZgP<kam<>l{7d3W(J7LO|LhQw<~|?R}Zj{O~1dlgra} z%HRotHn7ght3J;g`D82m$bK}S2||U(fUuvS(vO=UNht= z+$ARi>hF5FIMgWQpc^z^a_YgVyF>R;SXaq8QRz)<^=jB2o@k25=kdt^4a@k%5g}fE zNj;S47=B@n6gP_5giobiZ152or*p^c%JAb!D)I<7Eq3T|UPonh3(X6Kpw(LC%owp^ zis3Or9jYwOD{}Z*P#yHm%U+F1eKwpjPoSu}l7_#htp+0&Kc50FRDctRct+LEX+{(j z`Sr~eWfbd)fil0jHB--mlb zxW1LbIm~}OlL~KepsAh3ldl)ZH73UiF#XR4wEwsEk0pWe8k^6lcs)J_GxZ~{r)ahY zY1fH9$WnmwmtV-+rn9`BLI!_qvX(Q*$4W+cj(H1vIWdQ`92Kg=qlx2{9$&fy(ET=xJbJgn?3Pb;mZdL&|i@7FR1u@!Cz-?d_6(XmYORuMZ zLFPjtM(}||G%J2)g-_FYJu4Ut=guF4J3n)Gj}hDo2AM_T!{5s(=F;o&Gx&X{EQ2gl zRhCoSGBD_F7VnThq#szGRNj0wsL?pnqHw;Wd3n+B;EJh$8(WRd~V+2yjV7ySs zUQY>wr|B%x$--VvjWdXa3|?rmN*KJF*JSZ2Ji}fzUj@w9C{wD4LFPn_cTO=g zFboVbGqAf1GBdzpaIaH?VMqhfeEFHLF{adF2ALBzhB@Vsj~Yc^*4^-`>9T3P4FB15 z(Q*clnJgcJADFD=41Q>crS>wMV3=LbAhU;=i^0n@mgSk&%kcH4q%T8*MNSrji%r&Y z2J20hkHHNlYdM46Cd-ML?5|H+gpWbn^AODQ?0 zEPbF5Q!0a#be84m_8Y<)h^Aiv}n{-pMSE zqRu6`H;H$KL%JX)Z4H?(oLZ6}et-eQV5NR!dDf0$xKZZ;jX@?(X!@!7>eA4FDOSkf zw{%wQp5TJ_n}P)lh8HY|5(5|HYS3f`!wdSO3hvf5{le5($RJNwFuV+&uV**KJ*Q@y zDYl3~{%HePXa=(*%IfOO*Q**j&(JDn@^hRl2AL*Q+)&WKTl)Jw{VhDLiM^cQ8^XaB zgCjI`%hTdv*w%S*oi=es;mg+1eVoq&v5E;DHWEC*DHKMFrSnulkmzaVj zO#T)pi$SItLv`6zPuHb{ClKvuvN!V$L%NVbK8Fs!lEJ?lQtMXsa^jylQ;C986U?+4 z1;7lDrE4>CaZ|Sub8Z8t<{g%iGUt3_%~B3YJ{xRe#`BSOLK-k zMtZIO1|bG#=&Vs5ab|MGDtB8b9Zj%+X@AkwQOqFMrMi?;Tn(%#gMEgXVg{{KRQ;-~ zo0n)l{Ly?YXFeX$tPw4LFQ=FvgfJLnelQO*xY@9_oWawy=cCAR>METJattnrK;+ar z4kCl^M<8;FMGzy#65ak%ZvTU(A4(YH78Apzru`22sG-%aX|MoCd&H%!>Xfr7zDx@y z{2AwMG(sz7@q9`*5$O3XniS_<>^v*tXPn2f46lYIx!oye*yFsX^)s)hltGrO@N~b~ z&Iy(R=$CTcZf#@HvN%rl1Uz=~1sMx3xYYjWEF%%tBG=<$EsQ$-?Rv}t;)c2&b6a=l z_P8Fqo8fxwZV9XKHq${q2APjA{he)O=yPjo4BzF4n&z7hZ3f@gStC3xn>uMUsKVK-$@bUDAf9D+FRVqA(zpXwRy8L^I3*iOFa>?l9gjh={~ zf>5~Kp2;W~UE%}HGm9{`(PpgCMy;Ym*Q_7$D7HLTN3q8^cWPXW+?L@+F5?`Jo*M`B zb__=^QO`=3>2J)Q3{DH1unMD?jxJabt6=mJExMpTR>9~cT6DqESOrU?Sk2H42{>(J z@P3n3{Hg|jY_bX&eBWdhGx!ga1i2#)djtryx(NsY$2NoaxaYZ$n4>Wa%psyyJU?1yHD5U zlrp_8Z^A|`Fu@Em3o$I|!+;0#vhLjgUq5r zgUKpjdDy1L z0%qb0C+j4tdr;G4X?i`&m=MbiSqmbv zD1{8dgOne#{u*4Qzm*I))f$HA5(1MyYRDHb$faV-AW_pyF|>WxX^^Xpu|AooQ7+cs zqdhHRoA;`-XbI;o9{$Y5wZ}~dy2!=n8iooOWQGtZ){AO~-Uqtjrqc&Egyron5-MPCESP@rok;53L3DOCK^i1nI#q*+<68+rG-Ex8Rm+C#&vUJ2+iHM zvt6wr9B$6dhKZB&3|?hQtzeLAR;G?q_d19Sa?J{n zQw|?dHt{-L|1?8uIg{^pvZ4t^MIr9dgdQ*r@-cXcAymY)?{u=5_LEK)gWok-J_enp zM0IV0uK5~M>ISavb50gl=McKV-8TVA;vt!dyW`3f%PS><(=4CkF&@W=TYn?0xnfF-p`rkD5GN)J!N^XfB(WU;Pzlk!#qYapWjNl^tN zgXJcxkilC_R+JC)g08&I)VQ3%2Ay?^r`;E4*PY$V8I8_^Ect*lnw$q2@&RWw>j$={ zea8m*gmbtdc(PqR;T&!ce8A{-MA_WebvxeC-{ed^tZRKtf0H8oLBk`pNMfm7-04cF znHm?uWpszBl4z!)gd0t0c{HJuY2787qwDoI+yn-TO;$03%_gge!5`_Y5uU*I4ZWQD zxq}$ZS5b5Wi`*)Fl_s#r5GrPHiOKRY$koDGh_0?Uy1FPs&xE*DXw804FQ**xMQ-v6 z(OrYeb+_rLW_*I~ec=g3A4u!c>a*R9tU?BVW3q}F{GHBHW0zB*aXfa58En^C3XxMk za}eFkG9TYIl@>5~*klzk$TbuBf?iGq4f!Glxn_mPDTj|DHy>ZtmHkM63(u%`dpYrQ z!-;RYt}D~j>0>ZkXVHk{8v7hH1|K$PZR;5RmV>rmgUl-!`6z0=cvvHe@!SK244!YY ziW$7fWEC=avCdNc6rGUW)OjZelOi*bGryTMnZu04xMwkAk?q>MQhJF!K+7X7v@NR?V zV~{J1WzP3&^bbw3LI$T#Ubn^J`g4w|eY2H!GSg$%x}vy>P(^*4i9#Na<85KZa~ z7Hr`N4NfvyQPzXG-Db!aFnGjd6*I^zV!$xS{3)q&>O-e2gN8q80XgNcRy>>_Z#A_1 z48Cr%N*H8*$jjDGnHgfu-^;1LJ7pPUW)vc)9M+;VBUuY{o)K&zgRLg3n8A?ADrB%t zXQ@8s)MpK1F@twTAi71we9SQg3mCl7WEC;Um816<3@0CL?z%LM?-*Kz4F1Ao6*2g0 zlU2yzVV$L#$*H#uViALXh(L5V^QeA0=}e>A43?U#A_iBQtU?CMb(Z3TQ>zSO5ra2I zAabh1K^%^?iwsHugG)_TF@wwxdVoP@hFB};Td?Ih{1nGAad#y z{aSX6a3r(#l%Z9?;Oi!Q44gM5o{rY)h4Tm!FrQb$Y6ucQXR^v zwFa?>!J8uxIknY6bQ=$5ZMs1zV6ety6*I{EphFpCW>i0M>L#ZwgUpOVAGFgQTzOA#A)HwAwgIL7iKOzu0b;?<6>Z4p1W^IR|RlwluCaai1 z=7)xXe#*=!VQ}h0r!0faj6&p;!&;Qo5;fP;4EKc$R-3FM2J1~$A%hJ%OG%AWYYk!% zgEvPYa%!uC7^Q3a(R71Sz+jEZDrS)RAzjl?nHePvPTk~`WssRsh@5g*i;`NGrtzeq zRmk9ob65>lFnG7lQX=Bi%ySK*yXAj9TjgA3Xcbf4__^N~Faea2^cD|#(V~cL3Ca^(&#}wUe{qRNojpi|U>12=mC}XJL=)Y&^ zEEHt$8z$=p1|QW~v1ujirz!fIMhU}RIuH8=8ZuwG8sgzY#Tafk#iA_8)%uY`nF|@p zOEpxfzvHl_81zi;H3%BmuD@T@-y}T^CYrZtOBkG>vy>1xb+LoU;H43WnxOf5Swjc( zH#M8#*L5DuD}#U5S@K8+Cq8uWG-SR~b>;I7Uj+<~(Ql7Z0}6UMm8f$upBo|?h^FO_ zMav(9mfub5>L|VnnO2Ws)yLptItxR}+slb(96Y{ih_Cm7F=OyYPSJI}oZ!X+k3py1 zQDdEXWp1z-Vep%VdWW}{69)`qeg=Q$;H~TB#G4KtgYP(aExnv@Sc?+lF^$hR4UL6> zws~>nb2{GkkidCSYR=91nyJ2k!6!}iH*V1gLdO4A#4~_~?dzawEI45(DmlNZi%-vp2OmH%HcsX&Vleyi?iL;!{N4%Uk+sW+n za^hSk^NU_i@GU9Cr2oVrAx zMuTBsaKFw{qnT4zJBPg(Wabp&iMjJLcfU5=l`zQs5G{WU?n+{D=kJZ?t|S(B(Z}7R zWmn4Fv5G<8z8Fj2z8Fj29*L!Ihhyp6p;-F1KbF4jiKTD5W9i$DSo*d-mcBg_OW*op z>Dwd2>Kh9Pm;59%%tH`|Y?2v1TT`HeHw-81yb(AW;Em%Hk5vqa?G`6^tRnMG4<~r6 zBJ;3^6FgRtdC0>F9;?XQ@8JZGRb=k*aDvAwGIx78!DH3(v`=T4hbrR#!>4m@GK0X!;N2#xm_e2=WL?KF%NKI3W0)n0DnIb@V0y=#8}~7oqzCu^ zCGK6|wW!KH{&!zMR8kVnyON;d9To4Xlv!$;Gw(%TbZ;Qd75;pY4xOO&koekw6rODm; zRi1psn3x@^QZ|77mP$0l=^|0KIYmEX52d*YHBaY>E1q()p)bo;@zJNd5o1E`)^^ zi$GZFx~>dsxwd0Ui@P~p;W!jzI1&X}k>Z@LiWK9ktJk&D1kP`#z#K#p;uSl0au^k4 zcpw#Id?>Y;WE@I`UU)DSWOxV^WOxve7)xfwCpzEJx*pZ-u>400-r8#Xm<;A|-6MCc zKnnND+v*X?BIx&oIsH)GaTbt?4aBX~GP^VMD0-o*Lv*FOOMgbet(@Oc$$CEEj4(qF zU#H8#OurrbE7hU#j%6)lwmG)?M8QhWC^_AATj{Ba36w9VTIlv#T1Rd24hm25)D(rZ zL$tzP2*s(9MhF#lK_Z4N5UsF&p~B*Y3M&^XEL*5>Bq?wktELyYpHU525?^6mHbNNwWYQE2Im3o0JIdYiAZRm~L&>OZP9Qxuw2$L_!b+DY% zRbd$~Y-bI1zCNehd|?AG*7LuFoYhIkj@55p7G#eKAJeUzobOP`(NpN%t&Q}(ZH2up z^bXT?gafA_!_F0C*nvlMp8Q0&Lu;4TX4JOHI<&6wx`hu1Ew4NDdAs`Z6D~SWheMXT zVK!qf4<(tWbXF)}smcAF2rOQr$9(>%zwiM1W4INLb)E+!cDx_4{?2+ZV$#h1&WbVX z@8o!3>?9W;!&n$2{J@Tz9w1{Z(*nq$RG4xwO|*ll2Y9McE#RF-^#B<~2>|p*VGlvwc$706C%13)&znDe!9Z zJqbu(B&Ss!2)-Ya=*Jm$OxPKVm8dYSnAfX1Dkkx&j*98Is)N3@Y~oE~E`Hrp@x+@H z_Es8DG4WP)R7|{8`l!^81gH8>`7>eM;0E11z`EI>OUxP>yg1irMY}}D^LpLNZ3dHS zp&jAT2aU5Ms|2fWm{oKIceEz^Axk;|vOHFNUNBR&nHU4F+D7UE=h#sy9XfzLOC`=x zPB)wbjtvLSv3__QBB$Yc%9M*7;8dd;XDYnKQ!LV?ErwyvGHxV1#CkayILxTV0SYNg z48xi#F23T_dr5sO%QFG`)SGeYy`(-`8!VG2PQ5qIvl-_ZT^*6<=WMd1KxTq0@Fca7 zWza)X%mL9NDOL-i?ofk&ctcw3``Huc8J$wZ*I=`QJY{j3(?zC?d_jh}79`n{M?r>} z6l6GA3o^`x-vQa(W=;~?Rorc@!<>+4OFO85))r*g$%3p{h?jPRnG~88>*UgCon(HH zXnqL<_OrGXwmnxPXFo$)^qkCdH8A5)aaohAg(ZkuI0QWGyGgHi<>nf=m3`H_0o+EZ zeCerYNV|DO;2r}Mkq+^Sz(WTphS}Y$Sv_dkB?R5cd?mQYSH+z9raJh(If_06eJD~% zA5-c{vx+_-MCDhe5;=ZWcX^d`xl%8gRpc0zznV(q_%+?-Rnq@f>MgU19Ha7fYhdJf zxbC9Y6{o%lsxrlU0bXrX6L_ssZr+5WjIYzoFa`3%2XX=dmVH&cr>{Piny)(W{r27M z7VvnbTwX|5dBrf*IqLQabDsh~U{<|A9OmxR49UBX&MaS2w_WNhKZwDbng0Yh!KfzA z`%0GJD@-i``W&JQs2^(%tE|LiD|N81cLdzus0Q#*qY|J`v_YaXy;js@-Sw!c)PbMX zZ&S;B0Df61H-<>dyy9T)e`M}c;8e3}0&(QVa4=sFny)tS3+Af_NOHNac7{ZRiqrM& z>h>7*mCpz8spdZc^5Yk>&g1;YB}?$ny(Q4+5S<}Ls`mcgir!rADc~%ln!sy~N`OAm zCW-#QYlTf-uDdoH;r7Tm3dr~NWj+9}Q7tzgkiKTN(R~K)N0>?qywa#iKpeXHfaKjr z9{}P0ZRV>Dyi_TAMKpjG^s3G)u&E+)&zPc}(%W4Q8_nJ#<2(vu7q=rC6dGs2> zY}L#^Uj|?8xp80$&p%%V(}bd&a1ckUlL_W*Tn4^SIk_jeMIpW_ZWFLd%qlrkp?8$v z=vJ>4rnFFZy=*FV;D&E!sx^UcQ_9UNq%BOb4m`-HCh(8}wn*>sifd0TB{i(v1RTup zC9A0o+`z&$fK-wDYG+6XdPN{9J4GZ?k)tonV}-`=Hebn>3it68jwX02bd>0>Gfbrp zoMBW0c!5!M;Dt)LaYMSwD~1v0=&pyn3h!8%%uz0Tq^5l_xChv& zuS+{cq(3TKG5X|jtmTmcch@}f6IUm~!A4%NqK5ECO|Q^Ic*Td84B2!HY9><)y#d9uF);dM{0t|8D(Nq$ugfsPdwg=05ad-a5F^Qi&u zvcXG$v`&02=s=)#U9}4q^&vcF%@xggn(P;S(hEAsk8k+rp~1|7A`U~puMT}dBAlUQ zZVmo=SrOrzHgOVQsWS_rXDZKVt}p1e;*>-4K5Wg~FZv)Y)LADt@#k@&o6g$dgNEYZ zD;w$PyEy&iyzxMXTL(R+EdK* zJ#DTwnA4x})J+PR*%C2KUMO<^jW-OtPU;-Ul}EMAB93Y5D)bQOwS3S+k(416knR_z z)I#WFoS@f|g?WetR zKmkh$&aYZM=Xa3cSR391SnBosj*6V;cU0s&zoR1O`O&I)fllqu>Q-_FmU3QHmGhz~ zY{g?!W);rzBM$t!#q0sTp_KgeVPA&8fXV^^UOYe%>EFE~@SXvR;p8Tj?aVL*9%EDkNIrRXX@u`?>idZe$~F( ztm?pPl*;pr|J(?_bMQBB2z*Arw=L%j;B!hjUr2xRiom}QP(-TfSGFrIQOSc}1&|{i zh?ScF;bg*ag%!{S{><`f07=;m8q%v?5lG5T5s6ePCJ%Z1*7BGL{JFVr0*RcvpO_)N z<`scNc8W+ok7y>Gp+0WVZD(zt4EzPN~EK3vc2dXEgbn`_|#fioDTEkTRgSy?c zHuE+2#nuDI%zSmQuedJO;eK7WUGlDcR5MBstCD=VZB;Ep!nES001Q#7y3s<1!&aIC z#H`|YquS%O+RD5`rHTw=mFTn7SS7l!WRh?>B{cw<;Q0X%FJF4eQX8Wl^56M=uVO5# znl?psuF$On1pd~jCh!HNTnM?e@{M0T|ud(?UA)Rhc>l)cM2k9Q~ls4t$((duLx( zjQgsC<68C0cgbW;1rkyoVT@N#2kTZS0un^1)3kxpbt|tV-<%;_X5EcGto^-q_wP1% zO}ye#K34dOI-nY%tV;?OYI^rrn#o>jHQvG}p;a7y65*Gcqe(bA-W)}B4Aowqty{^E zp`w98U9AqNr=kw5R+^*qFABY*G^~U0_o%A;5u&j+SE#5U!!aqyFt36PV{D?neTkDu z)@L>;bR~0RFh?X?p4a4>b787E7rL*S*CcwhCY+xvey^CeR{PpJI;E#-cbabHPB1Jd zR*9w=eIj~S?cA~1-_<3}E6C9K_Bsnul7%r;xlt$8eBE}|E}bx#j-PnZ6go*GF#;8H z6P0sSb(nn9X6WcqLwVJ}M@187Rl_u0z0A|COuAuF{}*aeFX~q62l~Gj-2i@2UzG2z zoiC>?q`IhV;6zm(G(Xjw)?nFN@cK zn;6vqZmN{?=;w+=h=ZeIg9O}|~^F3*rg+uOAb;66sxf%_`uY>{}o zx}uS!cC4kA0%zLyi(0@z> zTh0ma7JJcu67VZZb=5BG%MiY2dJ}<5%6bTon_dF^g;Mzv&sY2o_TP~Lo@`VC>!>6=4H(766K>q6T9{DuB zp?iZBUE2v5-F-v%uu)@%joNAWPmeog#CF3*?YRF=${)YeHaldP{nEal)7n^P(>rZe zwU|QPHec+3+|g5v2&KqbJf1JnX?Zh^JWsdz*nyukZto1tF(IGVuBvfRkaIyIyh{tn zJyOAgC5~#CWrcBg928_Y4h-j;wzx%ee2k|4H7j9U2BrkLBMu7?YF$zlwJ_0&+w0{T z`%k*{<;i<4<%GtWKB7t``vt&1g2ba|F-eL180WwmhRjNEdVG{K3 zn_7=tQULF_5@)RLKw!$q#p#G>JqVj4InbK*HGApT7Lnazo$#;P#IFMv+P4fEK>m8B zTs6xR3#3J==+34{HGA(qx(p)d-z;bf{I&({#nGQV1>}!cy0aV-5v%@A>aR5vIm^)u zB+k(MvC-%xL&jajGfuqSWvTVVR?#!fmTI4`TRAB#3nxVl*NlSP#sK~Is-li!MH`3I zF3E4U5Ql0+xuBMdaikrMoi1#c$?Mv&clvDOo38Kc&X;v7AJPC{Q)G<9@b?U$)jA{UnGO7+dS}8XZ!-^8!d!aW3K4w%C_@q+u zdy!K!gr}5r0g!gFFGw_jUp}uPaho4MuPH|zRo5U3ROcZ}c}9O{_NGchEV(*xQ>8j<=Zy-J2%X7l zh^MX1Q*_TodPkW`9q9igYXkTh)sn+N+Q1(=z0YhLK>pyVQ+!Yr9yi50@JB{PhvfOX z>pD}3vhUSh{6$(>X-MjRvx+V;Q2Bg<_HmU*aQA#?w;<60sL&i=Q_7s))lbDhR@T1;in8!5T^>I_F13za}1NgX7 zZbY9@=~+{(1Ak>y)Kz@_U~rY?x@)zm)PZCCtMNk}-@Cv15*^+Tay3*MEff~}6ygBfz zO65NX8veIX_bv8jz(3>%qj(b#i%Bbu2Xs`fzKP&1d@!iMe?ad&j|T;#}Vc$ zxk2Ggp288|$f$U1HcHDs!rD*=9<(W)=>Z<1lsrI{YnDS*I@>D(&l#Y2u1a6^iogW} z6u+j@y@kR0x85PBK^Bp1b$5^r-(!? z^2i?eBeP9`zN}_g))`vP^;T9As{BfKtvtF&?c0hbncMQ#UwB~jr|F`magM?=G9Hp7~2r#tJ z?}6dne03F0oAruhB}O=TyeI14NDmG5gviwL24RDiXf@C4R+bEWuF#4qR*`WU?kGDV z>p)&<&X0uneGv@bZH6iEbfX%;Gn8^i71F1?BJlbFib$kVvDA|XS|9Mv{wWY*(oCVJepzqk5(UT^OfNK0#Aij{4rVn+^SrX0PFr+8^D%Pb>N9cHGroY zRR@00sKyftN7`%sjcpYk=&AQ8Jl3c>aEeil!K!)63QmDIbQ1t6HD4(Z_fB!J2#;HY zHt_paV-rZNZV-_+wV+KP9dL?B2YE#xi91Cka<2G5_m`UJim;!MiYb&tqE6#qY`uMH+sso2?;YL^{ z*D!_KdTNxyU5%;(cQ-0pcL>K$ON5Qq8jq#2U;m4@@}zcl5yEcJvuH@6I;YqxQ_ z>m*aD1A9Cb#+stLF7YZrzWE?+0*=?W-Q7$>I>g?AkJ^I!E6jZg|cJ#47g{|3#4NG@nJ5R|0(1s3x#m3zX-H7i4i-(NH|AE>@VU6u3$$d5$&$ zT(hpuSlSUi;=>tQ6<1Ib)WL-|5Ov^=`j)Z`B5)^raXEjKhP1P>=P$o3L)yjIOXMj4 z(r(6Hy85yVX%AyBllwa){ye3dGDsg&T}dk((+=IWnW-dOD%{#rK)x>`ADZC%0Ivn~ z;Ucl}1Xz?%av8eoppXKens8L8jc{0xJ1m3Iof+7$Dgkgheh>I6mA{7Ft(I)O)7 zgeH(T`sJhoq)4}HAkFl)KoWO~NLPAAU^(IV)bg|r&oUdP#>)zS@2PO2eNuPvO_=;T z2~5uU<9jga<$7T9s`{7=Uz=(<@)1@1q0b!Mxxi|!1G~0y8OtFFTwf_SmykB|ioneW zD2A1f(!Gb9VI6qX8VwWOJINaYCl4@0I>jr7N$}SwZ}2L>J-4OuCh!2IT;)jr=@mow z&#BunrqYP5qP6aBwL&!?Yp@R%nGt-H0y!3dmmAdt&Qi+Ng7j&x2>i?dMWlsZQIT!l zt>|J?Y2f}-o-%a>SRJc!{>7q?DxOy26xt@VlUp6k&QT>}ImFQ8*V%_zOsnmg|bvRBY7Vt8qT+&Ea zctzk<0~C>N^oqdG4Nye-idO{QHb4>SZm$TuXMiHoBVG~s*Z@VO7rY{HzHc~(yq!@9H5J}>&$IAtbthNzTz`;Y}m%|A}gR5$Ux=3+8Gkx7LnJOfYjy` zkw~TDeWy5&iR5vC<qlJst!EQs0Jzh z&QpYA{Ny?TxT6ha0`y5mhu@y+lW&O0nsJ&^=UBKV8C<1Q@fsor!fl>>Jwsqli{?Kw zgvY$*>I{Luq$-htR40F8t7l6shw{YX&CzYy-?g>7Sb*!7S>FLDZRM5D$`E!`QnCQz zEMHpj!4_ZW$e-2jKX*!T##(D~72g>R-BrxuSS4B~QCZK|0whm48&U$>aoXU9&6_&# zHvOK6yw3}~U8#K5*E1ykjzPtXzqt3`VM>8m<-X$OBQ|VT8ODzjV#A4{q5L_-Z}-sv zw&!UBuD3=c!2hsDOs3?M^vfx7uM0fQs02ufqD2_C^EAwV_;A3#88s3352YmYMSW*z zpmTjdyt4hEX54F;C;UC4FBsKWtne}27Dp?>FFd(AdqIVlbSn!E@O7{ER)(;FPYpOi zsiK5~R5;AYio^QLTJ$%p9}VCOM)guMTdcfFbfm;8(bFtc7!z3-fZp*$VzOO>6(iYE zs~%Kbu>F=+_<&U!<#=DDl0K{yfBH?%);MJQw5mL7juZa8rOz>8!oAG~Ji5C3fjan! zIf@$nWTcW3_77&25^DpC6(x#~&RSoz!s82_HLdWW zt_(5FW*e(SU($?KqBR2*zIR*^h#u}fcrSO>U3-~IG_?JCSl*^vId1^}Qz>@_pgy*- zVOnJvFZZ!wyUH+L?qkD=RfZFz^D|HGU+pSi?FwIQY{TsoCFGz0l1X0U z#0p>0VTyAc4C+f`*#<+ZkPknARe*D|E_H7R+vCagtQFhTdWE%iF^L8F?$#pWx2 z_a5mnWAhI~kd_#mPdTJ_+qFd#c(hS<;4w;7pUKFXUqg{ADc~iRa|?K-Qu4CvFfg~@ zx&JgndXFX20+thr=Q@de*rK+9-!rNQNDK0yZEMJTEocw095g;C=BejzTU~o+Zz!gc zs+UX7R2_OCGZOfK?vh&vlEjlxKnAB`D&M9K$Vp!JUe%Ee)6zD!66?Utm6D&hTCKKz zW`^D*Ag*}UP>};^GIX+10?Q4JM-fBXFHZr0Wy5$RFk~XjBRZh()jH1UL>n^I_X>D{ zQ4QeFm2$@i(u-aZ`1=8hNc`G{3@-4k0g8Ss93s1qT7(q%Bcqx?@^MEO(o0?uNIp&x ziBu|{c+OBCL=qJsVg6-bPg!0KAU{+j=ifM~=p1pKI{2J9O1`LYp{MRrxY$!+mup>) z*-5t&9=Kn(+a)9RZiOp7HJGD)%~1+G+^i-8ap*dSy1}Gx=grnyUal#Wxn5P|b&;#i}p76vB$-9ppAM@CTXEw4p z0moVPlW;@_MLAUmQ*>K(VmeOuouFHBLl>U$R2Y1f?%F_qD@6_#Ab$d0RtMmRRLgy> z7wIF$=GV$dryE;!t-QJJeV=Y6?)w$;yEAf-0{tJRkDl)G2W@vUM-AY) zsiZ(6=f2X4JW}$&y;BTb_bc&vi%_poD?xB=R3~4`8tOMU?R0CMP6pY^<=CiPE z)v)T#qfkeVt*~USv(C5pb>LM>RnLz(y7v)p2>ivrXqZ+R##hZZtJ?)WVpt8kN>@Rl z%5t@S!+Qa4YA3FIy+QI1PwT*`swlraIW0ptYk)P<`O3;P0bVyiG0blZ-Fu7~Hh^`b z>J5b_8Px<%HYx#r#HeWeS85w}Rh4|og9##MH6TIcE!kn<)6IL6swuJR06IX`sY)g# zkPoV)Sz%lF!0KTORtLUpR13&;f}6TX!|dGN0&*cyJ;!fV&qT`00Y7h1n_;f}80L>m zrSUU`FM2Ap8llm)D>Ovsdt=5N*@2PJbHmd&fTXO(l(YyFObMi5y|HfUAWKG zU<8*-9U#Hw19>2k|G&tiP96+~bP-t2qi+3RF#b2=a=rHBuQmt`y11XUy8+~<5#`DN z=zATlJ={}pVJ%kYsn3s_@8pvTmw75YbY|%0o^_eMpB=@nYiH?6b;=rd~4+9BpB z0diq3>mxnc(`x}qPP9nI_asV+47eYuIAyboyR?dTsYHQdmB`Ca)%w@wCAuk&RidLiR4LwF3d&{+34y{GH{|0utFRMM%TUeG5orr-o%1i%L;g;8 z4$XI-G`AahwfQP&>fcn$LmheRfJdes=!dC?9oQx6fcsU#Z0@j9A0+>{3xCv%|Eya% zX9H_?phU|ByPh?b);b?G6vrH{SUh9*P2960$Qc1hm-B<6p2hB?^ThU=wa>nR)sc3r zHGuqdrkr7cKJ{p=4O7oAd&!+dbB=(xs=C_0Nb~%ZbvgNh!Y_L&oE$gmuFrcFpf9-R z^I9nJD^7&N)xrC{BcONGOL2eoTEOAf%wEbp%%}wDGl)((gqv)>qkgmNd{c>rJ64Ij z+@jVGn3qU}T~C`z^bj{ziM)JR>%Z9g5P6AJA}kH+S!_Pu6R2R>m`1NdX3>cF2U<+4Xw zZi)@yi$>LfFDd10kzV(TifqFh3J2)pE-46jv{4P7+SQFpfK!Z$hJLI*bJ$C_RqMvp zYJRFv(yXdwmW~j3!e~J3JP`7f(0r^7!@{71jYY5y3cGhN& z1@qJW!i@qSuUGcMZ2?X_Hv-)7+%RyQsZ>#$ z9VQBH(_Vb1)MM~b=4`(dlDZg%;pV9JD`u4f zpSP>29^gw#<*P`VA#skC^%J;_onTVnDYni>S7LDzZIZxY9v>tqx7xKi?smK44Td({9$39-diKD5_(z?)sytq`;qU$nZ@D{!A&iBp?mf-#L~S41t>( zl>)aiDth5#gt~pmB1TKsD7F58c}an<7}W#(i&8F6q}8UF0zYBDx*W}(kE!O@aj*`>ioDPIrm6X#aaF@52^bmISRq~J^Zd6L6*4K!l1thSW3rPOwXj{NV zYU>n{PSJeDBajlDqR-x;xQ2FEgABL)Nq8M*QkT;(kP$BQ5Ex-0msJh-(rCCvb4e{6 zZy^`gDhB+(iUA*2G2mk>27FY-fNw#k=~hup*sPWw6Q9s+esTogYsX6ixI`)W@sGX? zfkw(X=WE(i#$G7WxYK4vgQ0!54Q+#=ou<@A@-mfsa<^A33MradHQ6ImpELUN7=w1e|_@sg18)?-v-=&bE3q6Fo?#z<| zQ(K{kaJF}NwL&Iu)s6GPI^c)-IRHGvs3wqh$asvU9~{~_2j(yrZVH%nT(~xv<65`` z%wa9uQD6>h;U<7NtmTkg)Q7-vE#$&J1P*K=7xW=8Q27zvhd{R_&RFn?zM(+h(3xYy zIru*98na0z9I({AaTVPgSJAzx72TUs(Y_mYb49Tj#j?`TEy7F9KGVO8@MR5foL z&3m6UF9DXCH!f`6u%LP6L$O|3Mb1z>x5R zIY(6-Yq>vgsVp7}T6GJx3qQ1O)PWxu>9q3Ga6LmhQCYcq0!~$`v-Yv!;L8UXTQ~(z zXf%Fg;CK+ zE!ABsO{EUJaI^AAAziDij1+L5QZnJU0Uu?*mzvMgaHQg>X;suTi=(DQEk}q)Dvr>u ziqNiz&?W-4NL?eq<*4yU{ZqTRku@m+e#oc>zW(m1owQy1>9*pcW4ZeNpjs8@aD-{* zszuAlw9pF&09lu`nv5oJYuzWSA#fX|+>(PWTjtcMW@z6Z{isnX@EoPq?28YDBnco6 z+Zjs=8lG zb?@f(NkV;pg(rGSm288R|B_}3#5xa`W=P&wYEBg3Yhw%724bE2YFGGbhrXy{jQOgE zD${h=MP3E?lv355!jSJH%5VX{T{3KENVpTlFo~sV@LxU&;3)mz#U+8Xv$ArSt=(6O zuPw~ic@JNlA>q@F5R#7&jS%ks?z80!m?H+yi+8)*UIlo8r_cQ()OJJ}zRz zc9mhg>h^1-*%q-5DZf*Gd3vSFNWY}l?cjHkkfH4@scP$Ys5R_J`Se#r8z1D6<;0)L>Cs~zb{ zQ>+754Nwf%<2!WkcXiuYJ9h+_=tFAL^FQW@NCrb{=jJq_mzO+%Ur=sXe)Bdu*AC;8 z-6r~3uADM}TPWo!L^|0k0#6^Hxb_HXRfIGn0^cBzr2|-w5YLymhIUniwneC04Q*gK zLOikJ2otL!Otc6eum}@@r3CPn4!FlQm2}zG>z7PE(B=EulK_MWx*M zBE8}jfo~2_49AxU*O*}n{H;+9AYt;LX@*3EiZ{q{|AhH!1N}?oO&|_)_w5Sz%`p3# ze&W2ly;M*K?qna+&s^Anu(KzZ)ey#da%l}=7f&v!A?)T!`QS)}J#?Et!2$2(xpCmV zJvSD-kLN~#_x0QsVE&GI{@k$x;dxceAG|1Bq1!@lux8D*W~IQNs+}8GB)rL?ymnu0 zd|~AVF*H0>gCAi@BtRUjU%Q|-e$2VG9Y((kit&@Wmedd!KWY3lFvBO@R4}6_+!Qc_ zCtMrM;0c$289d>R0yB8RO#m}^lAt^-)^0L-`DpYZ(A=UFgrBR03?+~@mbwx4@(F#X z;*HY#7NHJb_@u22i~nzJ~QISJQ(_y zJyYOyCBrmBy2~P@z;cB6O!KCuhFf=mfrMKwFp%->w2_E}cG&lgG`T+AcGhN$z~h}I z4vgRR^Q+OJl_vvS^2%$)y(TJjJb!`=_GS~qWcSpB-fM}C%fLq|w}E`xcd`5>=xs)K zWXCC2uhqZy} zw~R0{zMVD_ktM$A#2Z|GL$1CY0hs^Si3M6U=eM~LSG z5jHWyHV~hAgtkREz$*feF=`@^;BveI%X!4ttG8%twpL&HTp@v0i38(RFE7K6!(d;q7La0?USRs*Ba&IWw#SSFSN4hQBn! z6j(NlBd$_|x7llQb>Oy2Ro95&hGv)o%Z72pQEG6g8PG{c3Qt8PfJzi5UjuxuDdT&M<5nqeLI+!`Zd_(L;H zfn~$NBR*<|ZD83jKCG6j!5d~+2fj^ThOC})82-ZyQ()OJP8GwynPD4PHjGmpq515g zTREu#4_#xb8180Vgw&9Dx5SA*}E zVIBCOQq`$qc#j#Tz_MYS>S8r`&J63om1~TM;V;cF1(prth^y3KTYE3L4m{YXCh*ja z+@*jk8)>Sta%2I|G^z<4v2ocpyrg(ogZ;>YCJ(5ON6c3eTCJzMHqvcZ?cBZ$;fOWZ zX%tG8%z=qnHCqbXo|>eP(&ZgL>bu&s65zLtYElecsQ8M;qpJNIvr7J?uuFSa@iqYt z-)ky$VAH53koQ%kVBmaxa$P-@pH?65RjrD@LxO|Frcwt!sBchJ`^NAYGfaWJ&M9v# z1FtFhN;9PEm6hjUK!S>GIA4gkp;@(oya*r%_-M%u8=q zq+1Wub&6rek7{qOvZzfw`#Pg%ue5QLSv5k(e^SR?mixF2yq&vOCXCY#BmG$;@qVC8#L%!}Zf>ioA8sWyfk!Bn&oA&%UhNWvU-r~sDZOsJjlQr& zO*`AmX?5TqjcUE7uv1@RlEVc!&Zy|P!}kiyFa@qO-#tKLxS>Vz?xXLu;J)8{wSm_e zbrSFfrQ89B^i@-A1MfHLB;X51O#+gibB9DziPHcGE*U;be3n>g}T(NVsO zYEL(-hIv$QnC@!oHh&5LZY!4`<j?^W)UihZGPGV8T*ug_Qb6;BOj^$Al+fmpk7 zN4m!=0!Qdea!zru2)r~YLjc658!IH-iXyNaA-*uA^3Pam6M^{5BTUSY9`lO8a)kJT z{%AG0#S9zx!m#4`exGWSj2xU4^mB7m2R^IR+w(J&`?ARRF|wG-XFFj_iTOTzJFyP@ zWN9qo4-R6(w8}8PE}g1wFYyt>q~_?ZC%g*qZ$>pw&=)bkYA<9q?^bxfQT4|aK4(;O zuy7BW?-clkQ7z#6)sg)0?-LhiNF?JXF4Aolv<3XSnO`Pvj3JS@Ge`1eq(I7X(UE*{ zt+2Q)HQvsaN_|&_@Aec4PxaKf3TJt0w!+VN>az;(@)W5)>?!hm)>C1g%XQaZybACu zn>*#aIq^iqaC6m?iwj_%Q7z!*C0}WVlzBzqtwyE5avt%#UQZ1Oo-fE#lsny=HGpR- zC0`ipuslBL^}_xv)LoC6N*#FG7EW32Jbio>i>cF>cN$CwBe=NRwwk%d3Kk>f8aI16|4rMt8uG#ncnhe_V1L<`dmDIPX)t3TEQErlfICM)kl6N0nhR5#PxF4-XPvpo&u6W@tt6Vo4p=+(X5I??gkA`z;cCn%D({`x~lqC=xu>7`H>Ei$CXf_ zC!xa5yjM&3ux|6Do>sif%1eM(X^&+ttf)PuLbo1$=|iCy2K^7s{=2%ByuPpS zr=AL}P6$%%&gcEmXO!KHWC|9EeC5Y2$hJ!}bmrtcNm)^xACw@}+EU3YClNya?^;B$ zrO_k+t*sbMtQbxC<8N}-!jQ}yOFtMr$I=giI5w>Rm33|UGt8F(O(*2P)^vhWM$upb zkoP*zLA?YAGT*^5R7gQ}&=xHZ)G{JIe;sEQ4 z)AD=`yVSzhfo~t>LdbO@a7(4!ltCKj6@iBsRR_LnfNd@Kk362SJW}As=Boi5X;cre z>^{EXi`}1fNY z2_$i+h&06%Qy_`wSDl(DiObUjAT?CX_*7FOYxfBR5{b*rxSUy$NSsd~kjdU@BauDY z$duqBB2k6&fkYur7m2c*uIsk{_bjdKXS$UGmqd@TMz+WXUlkvM;E1Nki4vaipP)lmYkHs7ZGH@Zf1#X2B=uu`MBLB!5uHo_FDVlwcMg8aocH4V zgXX-~`*7$7s_m_ksj7XMStZwNDswHR1n9F&L*M7A1G?E+yF|bK;Wg2@#)8#>J8Llc z&4aN-`F@G>P8=f4Tk5K-cHspXLbnjD15B3#loXOFA1 zit8oNbe3xxyNz}cWXS^_qLf=i!vruKW`-&7K%*MKvak3= z^qMBIyBg++g7-CNNtnU}-PJUeI&ij8CjoC#%9Vq3k5?Sb{b{C>0%sZ32IA1I)kwFQ zVhZ#T+k-`Hn^hY~6*4|RV&oCq8IpHjAIv=tqupISw7;B}A&oP(>hU;xPxbDAyYJ{Cxn?6B zsI0^d`;V^^%vTDWXH*k-b1APhL-OvUTM67>V!qlytlg|fy2BJ(z?Vuv+ZoahR#OW| zxy~b!&#n~~f2ew4H33`SpYyHKVpeG*%a@|9KXt0UT->H>q}#QH{8+=v;$utn!3Ivz!b2ahm3G zr*89pfbX?D6W~6UR0~MHGXH@-iE$N4#FLmLZYU)IzQwrl8Tk8_SkM17W#SN(Q&dsTmGN_?q&x_0B0U0srLsvfzU zgLmpyC?NUBXBM+N5y(jNfG2Ajg&qQlh+f!``*(ND&vYy6DsTfEg&yF>O6BV|5r5;= z3|cRe4uzyrkphiiAd2tDBmC3mO!9`povdLA(D$%G564*#8^B|XO3qh!t*3x=T-JfG z&qZcb@)2JobAUcq{)8VD9ck(J0^hGxm;9J>hVT)uM@^(Cmn4^I*S}gC5wHz|{K+v* za-=2OB!7~wc-8+m+LhO=JClL0E7eu&>&Osp*U8gWyR0KaV6MogpFsLq=rMoDr{Yu6 zu*hLD?dEpp|5NJMwEPWfGy6N|cF&w8|G?c{u@COo75m_5-+J-~1Pg~Wkxa|M!sBVV zHhQzY+#Xq(?pFAqrv|e+#8grs*7*u4t4-u9#qDHPy6Znf(e{^!* zY;Tw4&bpPQ4|s}Ejj0OzJavV_$@@456|ZVc(Ool5r4Bsd5I;`w3yc`{nPCbn8^))T zE7jl@GfaRF7}dIJKNoz7Zsp46{sSHLgl?q`z@Hk`0zPk4;>`TNg!z$$OMrhis`Yb? zyw(2BQZm5jE8aKoHKSUodUT@Po_{IMS#Va66--3<$Hg zg-d{`Q7t0h>@&dU?%p?WU!z*U!;FeDAj~NiE&+brs1}i*^BLgtSnnIyFscQdWK@&^ zVdh%61o$nZT14LV09xL{=ULu2aE4JW;AKWd84%`S3zq<2Fseo5UY`Lzuk*fvbB$^N zZ!s#$fG~fxa0zg;@m4UAZ}u7B^A7JD_${Mazz2+qG9b)O7A^t4&!`rWpYs{u^9k=8 z_*0`=z~_yMG9b)}7A^r!Gpa@8jqR{*;qw*m8~B=0E#R9*MHvw0atoILzhG30$cOt3 z@HzZo#wr1hG^z#M&ZsB@!rX4*65tPwY7zNTp8-C1_r8Jq8r1?GW>k~`VSZ)d65wBr zYE4oHXL(1!8Ai2$ml>73p>QWXt5rM*Ak0uZ=On=GjcQTCvEDbZVN?r9zH+i6GN;Fi z3~fjB3$+PKe@&La(z765w2;TEJV3N`SPdBB?|pf54)}j5dfRt7E-xCqSSuVR&w9u0GVHCbvanFUhk6N>`|(j6!teM}EbxC= zH=Dq(DTFN&~;!5~u@DSE~BR!SF~kOo3&?`0{?N8ldeyCqu%PPsD1$f5)nI zqT7vX)5qP=Arnb|%eE;1J(O$g}*nd4!q_F(*oXL zR2_JWQN2#x|4RldC*UXrK5gNeKr(TQDH6#@fk2Xx;}b|Sq6PGMMQ4X=H6N03GY*M- z+-I#wo2TfJ%q-v;=$wNI_AH%u}|F)_<#G= z;kD*CA^X32>IxlQN|5!)yKsmM@0j4^imAxFJIB(ghh9Pzc?!3CH0wj9p|w8w;p(2X z>Q%h*ySJwDKHcVvFSw~({=M=G^n2xP<$5djg|*Drrv1SVjXH4a_tK;u;Ao}XvWoO) zuQ-_dhs}Ko+|sOCKpeWm3dy@~4d(t&=DrPlr@5aD#9{8fogsPmlSB8tSM9@&)qOPNCOCUh(bJ7Je{MvLoI!INm}tH=BbJEM@wqpA1Wu0 z`u~w35VGo;Yn2)teWWW(PBg%qk9L%s+eo)5D~iB72PlT^Awtt4q`*Z-5wr#To>Fec zBN1FKpMV6H6$?ln6&G0>YH%XERUC=n@`ZJI`5B4eoHdZiz-c3qg!7CYRo)SD=ttsVd;Lj>2tIFyOfl;VhRXE)C zvWXpC!rZ94R+>t5SrMwpjb40N5h}@d)P7ZqE-KLacRQ@cWniB{BOHW9s{Ulj4E(fm zO;8FlMDM09`oda4ul^mDJ27cTGm5&*6R({y}#QLlmcm( zB)7T~fsP5exC4QfAhag&kX|ogz{BfF1wXRea`toX*YzY$#eER(Ot4bsUjf z#Tj^|I(k#L`LY4t+&uNfo_fMUmaFz(%&HFTKh7z;OP0Y5w^1$W9Pmt|TEMeQzS0bd z2o)8Q#G9H|QK8}?>MZ{rEO@wa`($A9$!$~J-`1^MF#>y(Dt?$HPAyu;$oebhst&x* zs1*2JrCb-0o-oBa@V7>#z~2q9MH>1+Hx_ch19woWdZ=cr8?x-KO_wV(BocMkT1X_C zU$5mqUV==v&Ib|+J0D1vu=+6Bvd!}dYan7c;XWT!A?1f9$Q%swukOhIrLX@9x&5rscC zst)|HUi66;@S{f6f!{PLdfY$;hgk+G@F5E~2}maSoJun!l9953BqL9jfFvVYK%dv7 za4!8)J3}&V4M8HG?%HLtRv?iNcaz8@<$NHKm-B%{YEBo4M4fJ!>pwNuw{$D>2>3~D z>yX;{`Ja$OT%@g)tBCm>2;WgMzs&^S>$xf5`#jeM-|x8u{GjKK0@EsqF#*g>lVle4 zAv~prJx8=tH2NS|TD1ElNb7pQ?*UdkfvLyBlf?DN7#b5*oXTC%n_t>Q1dg z?%Kl4gbEX=xVO7U9o?tfO=>e=>EKh2@ng=<|56tF9#$RqAxg0;tcJNlRdO_hDvOnQ z){fdba8JE~b89+MTUj|D0FTz|lj_Bv2*0)nDR3wA)c_L49rQ>im|_b2j8P5XuBANE z42kS29?<=Tl+2e7pzqQ#x{I*VLSV1%%Ku_Jm{cSfkUU&PNNdRIR`q+A&kFdkQH{qG z{@$nr_=-^t;NOf&fL+?HioPVe>k3n;1Ftix0sM?oZupVzFvU9X6{8x!R|nW4)$~&$ znPb4MjA{V)GO7;zH=`QBPa9PS-fC0>_%)@fr*N-kNfX@l3(|E~L;llyNc4egN#r|B zJHPTodd1k>2NM0j2Qp1@c_7gj_Y;6fw8rTo(H*CYM1!0z5v@ z?hIj9PY%ft_VVP=3}L({*UJzN^5n1#;V@6GpCKIK$qh1uqdd7`hH!!>-o#h<9~R8Ik?8kJtG@J6Hbw#2V@vG0^HXPZ?Mh{HVfG(%e8 z6@iZ{Oy)RtfOCMm2#r%Fm-=N=K+V#TOqSDAzPs z4Iuq5e)boEE>#TSQgtzUq6;iT2ppv!(8%+VIU^C?>B%LX2s?OkaVNrPPcG_2*wK>< zI}vvF`sJ<7rP>hio!8;$kf%J%rM)7wwCqIdmA9Q9e<7GG$7@neqsgKn#ij=IKQ zt}$~RaO-4eFQc}g8{zBvK5VYITJe^eNTG;8cDW*Wgrz4Q5y(APB>y+GbA?BQ3;)gK zlPiL^Jgbx=!p%zNir^Q|FDW9tqtqENT`NK({JEqEE*%UDx}9_XFMZv;)Yn6_pP%-9 zo!9+k9odDt&2y%&!}R%j&K+>7bN*i4=G@BD9QRM%7H^^4aIPc&UAIF1HLI%Q`HM7N zJE%obDcihPQ~1z_9F>O!e^fc?RDbu+Rp>dzD}papu27@^=1K1HZ#sdP5;@0I_@&O7 zoV!V<1v4V&9zW9sWbg}4C&2KteKI#qbNCy&&GpU?dX;ld%l{j8pg6R`7RZSqY(SwG zc0lyP`U}0V0Rd^{Ky(F&)g949Nf!a)(eaM{W!U6@#us%G$4 zbd6`UI&1r7V1`LTF6v^SX6YJJkO)KUY|{i1ywF4Nne3N=OH1XVu5eQa~JfY{NEcZ-zF$I=p{<5l>zszPn%c&SM^I1)Wil=!G)10+bv^c5yIo-pY zW_1;^26;2tQn%m z3URuh&RnL^k&2HKnGl@9^F%M#VdW6YIi~2%rL!RTHsxf70y(KmL{>2J%DsU;p zS+8<6@acNlDc*qpsgxW7v%9I2;mvKAp5aF0@4A)bfE(+HRonp&F)9HvK|~A4Vwd{| zGih?QU;)h4w$>B%dvsgm`y~~Ap zo2jJ)mlo57`H-uzSd}m9StNdEi$seNzQYE+6)zI4H4Qq8 zg`^8)pz}Q9;cQh6XFPT-#%`F6U5iEH8@5QafGiSu%)@oT@I$OmqWwVst3%8xkh=#n z#Ki*4ARnUxnky!XPqjf#fQ)Qmi%>PpjBTN~E{i~+xGu|pQ>-|_Fl89^LJ@&uJ+BYU z!CojLlqUh0kuMYxIFfUZV2j6xBCWhGYxGl2?41Xht; z5zJgE6cLy#xgxkUaprd;FoAMKFbhuM5rH#Dt_Wr^DHIWyb-7|N=W0y4^7Sv6>tJy< zryF61(xWTzp32Fj12TOITLk7$o(Py(Q79rXEpkOLgIy>hFxt5yxX*6f6JTjF%;`p8 z0_3(}Mym*dz;NY?U`ER+R@|#IbTq$E47>jsJ^y~z-$4L>Y*dT0OH?ap}I&PCoa^jj2Dn6jTIk+;NT2%lmK~NAXa2D*I$MMSx_r{lcaal`j#el zpHC9#lWY;r`;HoL=S0_%2Xrgd0!trTEa^hvGaDJH{uu~-W+UY4=?HvgBjl>-2z+KE zdhcsfF9J}&7(;PU~g9QdF= zEiLJ)I4ubo{KpExBNX{*)CpBjneMWuOt1295+Q6gwjED z*IEs5-`tL<*5v?bBc42tAQy&ChBbalxsb|Hq7qc zRE525ZAgHngJgDhSfm6F>&vO2v?6X;7YUb=^B=*D@yYdfhndJCUlF0dJB&d2|E(>N zG<<|wIl^F;tJG4yOvHr4uHu(#zNFfB>oy+(@L$YR50JDfE*5SGJW0hk@>We!`Y(G@ z)&#y~R08yg>zkW3`|qO~?sDBqI3P92WfzbPq@Anmfj-^~(i|%|M*SYA+o82-waeu1 ziXfk=yu=04f#Q#s)`I_b)!QW=5lhg!h9G=Zcgj5E(b*yPV5P}(k4N>%R$=;c6_%ID zAZCrAJP#DhIo&+k;li~b3CnYxg1qRX&LK~B3X*HOQs6n=TzK!N*V={Vd=)rl79{6N z?vo0V8zi376eJJYc*<6goItsIa%50%E6VQgrfi;G7Mct~sqFr$ zvgMH0M@FR-1)JR5)frh4tiA@E_GMpJg5c z2YeJlJp(>(2sT7VLO_H5d<$deLHjEz)COC>nUVJ#23PA20Q^i}vv(J}2|<(T zr%+XmvwI?H7rmhH+GSe#4YsBxl=(heQxo8sN)^Krx?&FBXs%koc}jKF&hN+&nCo)l zA*AnYbO((0^VZS(7rfqJiF#K}67^QmQAGlzouB)|ymKy$c9~8M)<-#DFmfxsCyrdfi{uoc^lj#HToF zdCDTR7HBDyRIIu$X)Qkg)>AXxocpP63%!4;&|xcS#fx+MYOqNbG<{s5&!cx`6f!!c z(I1+T9|&~+eb#;XnMcKmZl#aFSB;tsq{iGEgG7up>aWmmiOu*#hba(lJH5oP&_j~&R&P> z0iI}70_06Oxl!X8dY3&f?*VRPR08C+I57mCV_H2Q&<9VbZxRIUlJ}YTjlgl0D~5ICTv$fVQN^G2 z23r<(Ad{eo5f*lyKE~i>x%?Nlz}MO%j^=+TyxmiSdAib6>akUQFe{$4szft~~$PL|o|3$7Nd@d925Bo*1M>MER zkR@Gw5P*|{3@z_c3o?-gVE2F~AyjDfeZ70(rcGSW@8%f{_f!SRyKsH#tRQ(Sjz|T$ zwiq&cVFaN<|3Zb{D~7!y|2ZQ=?~>J=k)i*B3?md|nE!9IM{nvjpCn-VCg&cazRS*Q z(Ya@)zS#5ueN-&x0Ny^}*{)FB)3@whqXti~D5B!z5&D)=`nyB#1sVD;$S^`dhMgeB z^;(B0&FMy1VsCA=fz(;(g}HRp+GOHiy=((1zAz;@Ub!krgkx=Xw}G^&&>O6XQgZXF z8a2P0^h&wR?dpLQtRP`C0e?e6FVLu}va z);m;xlx~OArq}i!lOg(Ux9G(WR8x-PuoF}CvDta{_^b}x?-Hk6{cUCpKWBz1uv-l! z9B^pKSDGR1NG?8g0;E@EVnwI!Y6Bs>97068zfrnevlrC z7W3nT$n@E1BhhEHk!iNmMxxnhBhzuGjYP-MMyBnWw>F=)qm4}Ooi-A^M;n;|aGgS8 z0MJHe6r67)#sqCQ4g9~?=%~@c$mDWAZND$`30((dmC!@x1(p71?*B>bM_PEOvQE z4sEKnjn!@b>305y1wy^B`*QkuGh@muvw6~FNZ#4+JQR8ednqY*aKMwxdI%hHa_(ZJ z$g}XbU66EsXH5Z9bYG!}z;TuCi?x zJ-5(pSMAbS8xE$#TwcF+N%sw%8_4Zx#yq@EODpXf%nOHsJS5&q&p8Z&P&A(-Lnykk z^T(Y_p~B@xC_3V&?Bwlr%08xB(TZpB6e-&y*|vAn&wdokMmSr;YU36 zZH0b~YBD_CcBXBHZ3qt(xpJlrhg%z3K$h2`GA-9%Jthk$U+KD=Hld3Ay0xtZWI0Ba zc5=}HPXoE~fJgqe^|}S*@&i@m2W<>mK*j)727>NOZ9rO#Dt-1>G|{d3);i6$wdqy| za;(ea6IxH7g^F9;8y?xB6}C($y7gDn2PQJDD_q8X>ka4UG1@QRr2nJ&`Ty2rjC&Hzg}A1F@%n{hNiIXewAXw|!;vCd zah}ojOPHs-N(kquW5a3cSY|2-J2uSOvEdYUEVG!*9UCU^*tO4{fARW-wB?#3%vq=~ zVWGlog$h#@YHfKIR|a953o`6-L558($S~i63^OjsFz12{vo6SW$a|JuWR2Iehgi<) ztjK#-XGM%zorA^rmrv8wx^CxWrk9-ZNvm`M4wK?^c!r%J6QEzY?Fp2hMbQ~g&MD+M z#g^$7kZXwi(IuF3qF9ClCsdf|&YB=u$zb$%R?L_F&Wicc-$`x+EzHBP1sMkB%FHj@ zJ>i6w+x~D`2o)wLRG6AjVPZmsX$i$ha!wLzZF%OcCehclc{vBBkrkJQ#VF~;jUV!6 zn7!Ozug=2!bK9_hoC_<+xv&Ic5l9voX0tz4H^TF;XvJsWXl06hxA4ssmdrZfiFyUW zWf4~vTsgoabLAy2fMkqnm^OTzdo=gs+$WPeiOOk^90@E`7*nV?+~lw3`V2PY|TrJZx&jqCzD0s4v9%eZjuom+zcALiZ#zK*JD z8=tfY1r#EJ)EgY2V&zg#+9XW`HKi9?EO4485D+;@lhY=UCdZtl7eonyPyt^eFKE$X zf`C>5i3nO>L8GG9D^XFZc!`1niWn8Oc;o-9+3VRed-j~B305X=_Z*up(BiKmh{d&+8I^d^e%3HgzHMvV#Nzi93i)`ludQ$s ziw7zc^6}&VyVPi6k%0;M7?($F+BLEGVojcqk0*>DYRlkF*t~0Ek?{;g8O|f4oe35h z;gD~t0NV{GhM5(y7g!lOX)n-K`eiTBH#%Z3lyhcc&|Hxx5OuE(x9iHWGSM;kZJkM< zmuMb@Ad}-gagdpCiA@iPU#2;*&E^6?=E85|ARB&;%?5D(Mo$jXYzVDS?KgJyeZK+v zegpLV2I%_@(Dxgl?>9i-Z-7a^uhQtz0n=TR32V?tG*_7j&!@xF4*M^<0E;wTuB*^2 z`v*i>q$mGJU4^dE51YoxDA)`1i018uz3vgT`A-eMOdc$^YVKm6H|c?}C5;P4yBrz> zW0}1(W!sou)Tu=gWBDY-UVy%e_iT6?IhT9B&e0LEl1#%-X&k;1iwDaOS*&W9sR&$uD$msrh3+3ShI#gO>!N(E!NN-@0QmGtz@YI}!LY$)7h zUAXTm!ybY>S$4Gn@xIA9TD(kY$j6g=BR&>as~;gBPj*M(Uxs-y?|m`LJULlGSZ1*| z&UgBCM(8}H5(1Y0dVNe`aDzFyX~48C9^c z$N&o)%ZxMFSY*hBjpd(d#}-=6 zW;(;Vu$sjt3*}gh%z4{gRJ2xmk$9QbxM}UdsGjiOCZ|L;ujPRl#`67&;dSC~YVqBg z@gmCd#}xzHXSDca1hI{-)$SpZX`znN+>}_+S8GKvp8ot!jI%sv01gOdJ~P&Kp$OSP zY}8SLGCXI-$7Pa%qD(Sa#FGId&Y&?;aT~-g(6CU3=S=OmOfqhiNyd(NGJcFxlg1Ca zmv?BKh@G$3Fod%h3#(;M37@^jYJXZ2ByNUSlt+y$G9qzyMq^l`6u(9+%C$xoA4y>+ z7Uf|hi?LYSN|cKogMlws+c2DrLI|?@tWOBCA~Y3(NgLPbd~$B@5Fkz4v=UbO@EYgKkx#!e4N1p?Oi{!C; z)d}+KoxO_r;ap^J8CU0GaujkdCdVV^VzMVW7Za5ZexXCkZo2@bxk@&ElmNYG&~o z3wa*U%-Pmlj>WfGsQFJ?cX|R3KA}246X|C0ehW3TxYI(O2Q+h;HJ4-YRtq%`Y26=; zV!&E$jdZg(Y@ucr=`Y$U*$OoC8EY=b;=>kdX7uR^V(=R^^CxRA$KtaVYG!et4;jNL z9?;B_)?ALo1Kvxi=7T?Aif1Z?2aM}O)?ALoM=aFLBK=MAfM#B4&E;5pgN2$IeR={9 zj@DYui)zPWjfI+7Y_O2m3N&-3HJ4+tXrX4-{n{u7jB912o5jN|)XXCNO^E@`yvv%) zv3QGxnrZpL$OG1Dr8SphakYh-Sv=oDUJPjFUTZGL;*TuUOv?vvwW&d!7eu;Qe4B-u zS-jXno(DAZgf*9AasU6a=4koM$OG!!66t2~S_?I^_(2PK9?;AythpSECtIkQmamOG z*r7Tfh;*~~EekcX_#+E>9?;Ag)?ALoUJEtT@`I5F)cLDOH;YeNsF}rQEaZ7WGnZO( zITk-+q2_~c)bT(mdLwlP(G3WT`&p=&#X~IQc|bGwSaUfRe`uj*)}5ZfgRJU2InvGI zVhc61$Q!1V-bgc#TXQ)UXX$nZ%zZ=aesDC}u~tV|b2%1YZJ}ls>2Hb$H1l$6F2~|Y z7HYmqJ)kFWirM|qsD)X)(?ZQGGH+8npqbOHxg3k!+JQONoy!tHmuN+=wiV8?c%6ls zS>*k7iU+)r|D^7p>=PXDubIOdTUb0&q5XrIyKh(%-otUt%%v!vjGDxa{?ZKZ z(6E=~OPxnQ@3&PrFH&Jj^z2Ey1=Qjz^2}4}dnz>}STM|Tq^U8fN!XGOWOW1RD@t)6 z#^S(-4KrSX`JxsNRe3-Rg;~ z@Au)!rz3D^22bvZz%4U)a&H6<&fv*sBXD;GPd*oclNCJqd;~sG!IS$VaH4`IUx>h6 z6+B@W;rw_7Po5qz)emdLlb75~u(-2=C$CX(-(ch1eUI5$!E;73)KD&#_t;pru*mR1 zZX_+1Thn4Wlorb^X|WufkrK<@X|bG4i{%q(v7AVYt8x8D zjNnG4n0#2g$3jh?y2WrktQ1dgj@EH*t{v}kEH+uFDe2V@)bh`)2RRlQSVVa=Ey}IQ zD2L<4tc(paN8nJwz3Ri~tuHwiW6d$@HODV>FnUHQhVh#<4pBV3k)4e=paGVxST-Oh z7s1$goJs`aT=Gt}C>XtX)Oyj#;$s$iD~pG!gCa?1Z?lcp$l^yW^i~$1j7c7@ZOgV6 zZESBgwqR^shEcF&GbiJLhcnN40SUomL_&}u;g1D};J?&L)H3HEtnM=aNM06MGdz4^ z#h4#}SY#bS15;H(D*AjIl{FCAk7>)@V_PuC;*TwK9-IED2x5^n7iFwx);8*SZ2Eg5 zC|S?FX{-O!YO*fOPSM9QYk)3#&x{YLpY%5b_r_xel|2UA*}=oQ0nb=5KJjZb#N3Eq zW0ElYE%bELyV_K6w8Jmc_&dAf3#C!9je+Ng4v=Wo#LFe-R9 zU~{IKMaIZ5CZl7}WLylIjEF&#u`p;d3I;7#fBJ;6HR%wbq&I+)t^i8<0VwGNpmH8C z=194bw7Dji8vj{YJJ+xZp@L*3LNHm45KLAi1d~+>!DMAZuv~TM4W3x_d~ik(Bpo82 z^oe-VE#gVfh$o#RUe3Q*xTm#%V*L<=9W#=Z3&CW~LNHma5KPu71d|mC!E&{^e#Bgn zfsN%aDux+|MLLZK;7ON7k{(a!C@2^mUS*eAZ)K6=lCUMKAQ)>igpgx0`9+AELdnYi~3w6FmKfG?4uDQiyu?SFzSgV zRM%w%b1dqU%m8Boi!_5eTMb$mRl36}YGm;n3Z;9{tXI#rf;kr7VxiR+Yw>am7CTkZ%%F71Fi$pE?Vc)Dm^(1o=V7r`rCt~e=yyk69K2?jC=DKFuNIZ- zHNwWr>s3j_)*ol%LI=a( zhTt`o^4*xvJ@+R6yI>}i@foY5k;O+U43_c&+u?fYD9e&#vC%^3jA`)!3*}ghbf2S! zJu)Zqh{e|_l%A5*KyJJo$zoj4|1K+Euq92f#asMmRkBej`aX;2D`Z^dSt(*<@j8c* zXZq9;y||G@-S*X?L!~V7U0Idp%Bo@Cl~rl3tQz)R;SDNw5a$EWh z%`DO~vVujLHCe&4$Rg)d8Vs(`63t*VU~#>*xSEPs1#qz#>Gnd(8R9v$fyDufk?!-T z=!@3ec`Sa{LOB*AbKY~3WL0D($GYsaF04w{Mc8aOv~V!i{c;?pG-X-yW4-i?h=oPm zL5GJt6w>1UO0mHiu>4ZRUKEr9es}c6!O_20_^^Gf78YNrP(tEZg-?qlSX`AZ@fL-9 zB8grtzBhtcyk4P%S>s;xceO_1n^8muJRu4ZLFTwaQKz#6AbHc6h8TO6{)VwkKdv-%b4-;AKn>t0Eo z6iZ}@Wlqu(Gl}VeIfBJU)p$6^@q}SYnYVtf{A8UGRC`V*dGJU&=@D6CiI`+z7iKof zXOX7jNeK_t#PU0-g}s(pkyfW9Pl_e7#1cMf={SwvX|~C;!z{Cru)?P!O!AaPKQ*7C z1&kLg@=nam@jT-i4U8<_r?Q5TXFrTIviLWLk!Q2*oYTnS0)>o5p1nR|WO1v*sOmlP z2J6Zy7Fiv!u*%+a>XUm}im=G)7)G9rM;cjVbqpiVSR-g;k<~GbJgc#lTg76$a{h{( zwOnRhX<;#5xfWYFeYpjdYhjVq5m#DLq_?wqvBos&|zbJ8kzPDB~ui$>GEPiOCnM;u zT0F>_%N?r4qa$dp7HcCY8Lu1E8Q$iE9ZZ$KKxz0mn8A66g2Kr1C2>Zc?2Iw8{GB)> zPYzb^L?g?rOlX=X$HW*}W)(w5p0E+Z$|P!>R$*ph#?@3HEJASn-TIP4J7wm+LTR7MSx9Mj*W7Tn!!XoQ! z757FQ``yyh8a91Jile#>FBPHW);z4{(&fv*BsPTsq6 z;6Yt>C^vPdR4=JGt$LL@z`oWFw2f6-th3N67Mm3^HRjoeB1Y@67RYj`WyxKk#Yl=t zY=xI7OS{rE$0zjKZl&lzEdEO&<0a4bn`!i;U0CFzIz8=PssbHW&>PHNrk8kwCJ%2C z$8pM%w_3dFCbgthcTmM|v}zhzyjdYr3!dE?F|xSbLM<%*%aNU>cRPnGH5z%w$3rQV zyhqi1%UWn;kx~Z*Z?{9)+XH_jqwSZd?R|r{W2`EblDe5v~BPO-*Pz?#shiEBAuKnG`ue-KQg$Sl}FT}v=pMu%d`MbSmZ4c zCSw-2D3{3ro^b-&!>oOTRlkbGD=pN-A{C1IRl_`s)N?Xa$sjmVOY^L*oG;~dtr6wE z(@Hh6IANjHEdEjv$$%QXOTrOIKIUeTI3Q1uj8>u%Tl41VV*_m&!alhW3|Ao6bvjZ zen&4=1ZPnZBLs*=Rsn)6M&`WT#~rGZ3S&~(*$59nZ2bcwNaZYP&`aDD!0^E0->uYH zEIy}@X=kfM3%;&Z)b*^@)y!gCmw*4|>uRAc3eE`Lw=(Gh_Z*@d{~U|EtqWc@UaFTK zwk$ao|7M}pEdJX<-pYWAu2L2mkXgRLik-vajS9^SHdhRf>d9wgvMhf!l4bE5aoJ=T zc&@W2QlgQ?7wEP0CiDgQ96yK)`t9Wlwxn6~Z!vwrbJ7I;hfx&#f0e#d9UD~2DfR(9 zAJGOpK-aAbTT)K`YUR+6(g(L#3Aey*Qla|yQ(Dd*_Z6AL8RfsajDP>8Iju)V>0G6} zOvZ@My1=7-m5gh9{lYfgZxwJ%!AGO zeo8BqzDj9Q{+UXHJgaoy7n}1%hZy>Tml&E;+NShUrRHk%_iUB_zS8F_zft9`Q+k8a zo0LYDOleZ_-AezV^rh;5lK)Zld&QyV%AnGpC{6NDyuu)lD}7q&b4ru^xmOzGY^7~V zi%OIHw=4cRrDIATE5pA-*V$iF`W>ZzRGQR(miC*U=*x~+ha`D+%M&C>JHpBKK!=s#HLiPIbP}Ol&(^mSK6U8DSx<*LoZi)gwh`$W;mN(YUqN) z4ZT3=ok~Be^mj^=`oE|1E?>oXQqQ^8|A_YE6`C(+DlI6zP3c`qllu47@n*eJZrxR@ z-uEQ*B;{AA-04bJDJ>{X@>Bnldj0Q8X)nqD67_>`pB|~_<@o6@`_Bzi_}{1cE>ijq zrCXII{dq#iho_W2qx4tWPb#(F9a?6+aH{e(DQ#2wEu~3&N&d^G;J-k}$G0h+qy6z? zI$lgDt<>?ksI;VXQ0bV`eY8IwqI7}M)0HOuoltv^D}7q&{$<9iU#XrM+Q0WzdTg2g z{x{`+PAU11D#L%HuCs1cdb`puDgCq3zbpN>(iyt`dV$hclv$5GsQvs$N`I~Nk4jI| z{@5$UflxB2XsZzR1X=|DB=9jvqG^zAiZZUB? zGEsr2UT%O%rGHZTSEbJ?J+#dFYmw?(skBXLQE8I=T>);I?4#r1!Af7E^tDQp@*mOh z<{_mID}799lK&r2O21HspL}=e_3tQsQ0e!TChh-3@uYp)c|fm!Luom^N%?;$ z|Digb@p;B;^qh}CR+Jg+Q;?YB+wTa1UMk>GnQa?^#M;sPtf^M<`AD!}k?W((6l=o>qpxq&VB%Q+kKeFO=cu=jQsfecq$=eM*!1cWArauaqCi`em8+n z?N^k3P3iZQCiyu}pQ7{gX-eO#^aiD0Rr(#J-&a~r-=Edqzm)D@hX3O_zu&2JROx+6 zzoPU9N|W}^(sjY*O0QIUz0w~meM0F|N`I*PEk9QJ#H*5;&H1BcqAE;cWj6CH|QF+RZs66Ew%E(i$r1F%TPa z8DFzXBhO8Va+R9*v_n0VJFAR5Bk8DNjN~cK9#q8W$evuFba-WTBCH4 zQgb!>d#&QvDcz=YMCq+c?@$^fj>i@Mt(fCEB<4RYoPFgbOgNnaf>2*rKRED4U zul4$$lxCXJ_0MTG_=!sEmA+AFQtGjD4Dz_rr_ML$J#B_gC|$qCoWG#M(3dHF|5|hY zh|+DH=6wGyL$~RT_FZLexWAk?d=D%ArP61V&S*8)pH)hK0`iM(3fs7^kk(Y zN`I~N4@zIM(eU*u{qrVse(q*NuTzRQ^gqe}53TQ=C37X)Z|L8YvOZh1K1umbZI=n9+4BrXpVB1%J&J!;>HjFb^R0%H zd0C_RS*dx+JY`;P)^Fr9tsr0UkjKmj}Cgs19$lGLIwyNAEO8-kK^(OUg)I1r`{{3#H z?DysJn0Au-G8Y?UuF|a18l_48wruJoNsuTYwl-|w9UIY8+_O24EubBVcr z)S#hRr4338mm2&v?=m!Vg`q=AN0joHI{91J{6$Xw;4gn~*GNZyPn)JcgX&kHeof`y zr_@jS$6t_-JTaxDUdpk4l-t|-Rcd@0=bsL$MfLx9^`Ad3PCN9ooE`q&Zqk4LK=Ink z%oYAjD)sRvSd;BiPT#_J8$FXs=^ypdKk7~T6KFjTRhrD3BtL&Xuy~cZlKhRt?rRNx zk<#FO=A1uJ$sd>Cua)r!%920pz+e12_$DLIpKdf~(chg{n=u261B<@v)m{Mn?WJmvB#Pq}fGr=0!K zql5y=U8nMu+7H?k^L+?K=MQ7j%+8yPVXQ^q=2a{?41t zm8X;*`Vn(}kJ2ZVW^OU~r<6`81+2f949DUqV#m7d{LR-Tb9(vFP_*} z{dl3$LzMD^Uwj`VDgS`-eP8L1l=6$flKkID@beqL%JKh2`FAVjH&o2l`n^&q-`h*t zdz)VGS9+z=A*I(VW&D%!Q?*l)|F#N)d|GKv+o@G)l7CG3_~~f!T~LPqHdSzk(z}#? zM(McHT}qRrTJ4>rbdk~(N>?d8M`==?Uoh0B*ZCbhcj`Io^OZ944=MhL(w`}POevqA z@^cAE`-f^=UZM0TrLR?5rLzQsZ1rF=>>#KFqf~un_<%WLWb<8zYndr{?gUQ`|HYP(`z+4n z*cbmzV84#iB=$)5Wa}vrnZni~aB*}BJ@w#eokGu<;K@zFQvgrH6g+PSPj(6(c{V6NQ}Avw`j(^2h^j z@!mc7-seGpXI9*Fco1~E3^+SPllI_{=NglE39gLtyd>m#P@kr|OvfwFi$WgpS%Dba z>lHdQ2EJT*Dnp(x;>>4jQl3LXo`><*Kl0!iv+eG-C%HM_y%@mEidGnMtHyC- z6|U>Jv3cG4uAX%#V*FTBSl88KMv#rLl|_S!TPA>)3xehg^U$wA=)jHOkrjc-Rpz05 zH>e2AtdLFVgg;Sg7+WctnTHa;a3o3N(L9vwGkN$*l-z@PC@pF7a1Kh6ZP78WFLKC? zQAbA?V63X$LayAoBjsgo8*w zl((27%^w9K=@23E+4o8Zk&&;#L4E}!=OFtbT7wQEtJ)CIM2Nxce)yz?AMNnQ*(JZAzKad_4M$zXVl^lT6*hvz*&#vPuU zMGBoTlG*`82J*=Iw}8lJr6Qi60cmwKOUAWgpo@4a&?mselCc^^A{ka z4$my~fa1&JdX54zcHW8+8`NYVBS&VwW9&oZFTtat-#)H!3jza9f~;_&Cexe1PFJ(j~2bTioc zHV1pl%XzQ~h*+6f(Ey$ydtC~g2OCfhGod1f`h-)OT(*a-$7B^|)?+_7ACe}xmcy*a zWb`-dv3H4E-jRVGS%sPP*s*U)TOZ1LOj>!W^_Z-}Ff5>6gPt#9Sk_~*3aboxs?b(W zQwU2S>oHk{VF-dAeyNXKi4IunRGOt2Bhfl z^Z=3BA@b)^;i-x1`7n^I!}BSTs*UrE1F3X)9tASAFwV0-=89}x9C;0pqJyjkGJz(J z{8=kJ^>L~H1~TX%pA;zv*$HIK(ent9?GExZknuOhHNO;DHR$lX7RU(tP!!chAfpa) zDUb$7>Uz=B5SMxY$dH3P4kU1-{tl#dQC#W>bkL$jIQp6FMT{x}%r{>MTc3Y8`bm$J z%t*^{j(!ce9*)@PG0B5>qpw6mn9*;O$Hmd_dKfaJpL|EaDUK?Rej}(`*rpZh#iV!0 z=vTx|jT!x(UKRv3;=Xgp-RME+31;+rL)p>qFQ;sFxR_aP*Tm>(MpP7T5U*e#*LS}Sb9P}Ly&8(4QlK)M4cr@l*-V z1&Wl}i)#i?a9UhXJCNm$o((_-&y4$XJ&+*>xf{rcgM1%ItK;*pflTD$dgL1)G7itn zfn-<3d0r2svN4XV0wVAHM>XvLGV1Vb6dnh;21ssoT+eMl#vMI7fQ&gj4*?lsRHNdF-Rc@>ax2U#FIjvo26_GEKhPXS19RvdW;kc=ZW1f;UX@JRiG;AS9$ilB?& z*a@W7k$MD3!?|(IyMg2!b6tM=3c)kuK$j6bN02z0reh(z;@Kj*n$vMbuAfr~w&MD!T z01qlYiF*(CyI%g&bBa9SGIPo+O_PP~X8v$a*@jTapgXf-6eC)9j3Zi6XRyQ#BUbU( zvUAG$_j69EML++rXHVvoH=}1Ftzj!yc1}593+I$IRgN=yB6G?R${4DkCyT$HsX%r( zWiQ3dDHBpX?~plVBU%Uv3O&og?N1r9qW%dy1siwRGQ8p=L^yn z&+r}~tw&LcxoT_yt@sUOaRVJYrkAS-bK>B-CG&E%UeSQ~oa}IMjWmiXn0!XZPaMqW zm0&RWEIfX?%KGQ}{VH_*GYbyAG@;4d{e1{IZ*o%<=w9UE@*|jsL(t=P4d&rJP_KEoxu@M<-CT}r z8EiB8Q*Lc@19*yam{C%v?LfvTB|z{^AoA&~C|7?b$Qsog^86V{rNgr?T4uC8p1nr^ z8FF~4fCOvfJj;M&Ey4^pwU7+|`948_0XcR&pA64IPI4_R8qDz4W3;9f%Mo7;g|UMf zz7tAJhIhoSnj$m2!)CaQA_!07kPP3359y1AnH9%l$L%`_4wK=(Mar2BFPUK>!6g~~ z@y|2ETcHj>;*boV1U6NMkJ=0$LEZgBGW;HRYBIb6XFi*Z#^<8HN{we$tn?XxOD~w% zi(atH_JXa@gIlK9!CoNmCzxK)+1p?29$1&?2(8GdR?Voib{CZ!z%y>MPLTHi8Ce(4 z%v*p=I@$XfAfugeo*x5g?TRCR2O`lzg~R?61P7o!0;UL)z3w_fR5E+-*hBWRr;ITg6RQJuX>q zycJV`$?){g_)CWG|4nB2Wp0;LjgsLRWWrP#o`WGXh7YA?reyfN7+_3>Ux_oHO)~tW znEgzKXMG0vBpF_b@P=b%#c^J}1(18#Vus_qyib#!;qpxlCd2zX`wDFxrToUOo{rv) zCC&6>QK4~WRH`>YP%Bvnf1>rXe1F`CgPbRUSs&-=7AXgLCy-GGxdBL~Coc6#AgvB^ zzeqXAgTm7rmwFV)go8W-BwLL0%)}FziMPd(!+{hpV4N}R#M%pC3y&)B4E9rsJ5L2E+2G8~UjtpG- z`-|qVzh90p`E1hPe{1{uTRndTklC}i7yZ5NSoZh1u!Y59?BM!vE;^{`?>cMd@%}|@ zjd(ROX5uQ7W99n$jo=BcR-Vwtr-5W0MiTkq#NX|hvi5>@e4-k1vJJNF_kjnSQ^=t={aS-`F#;k*U z4~TrqMb;8fhvOL_Lk=Q)eq#)G&o2e$e@FC1KHlHJw;3fmjD@ec(wtN zy+QHC_;VMK+_iCA^6fD>hv!E?CLEqW0hv56uIB~VjUK-)uICsaIfthf$jE=kd76R9 zr-CDYI)N0gkMq0(NTtIw1f=1HIL}=`Cb63u>G`tgad>_XWZdETBajh?=RoX9j5<6= z02z09P60CL@H7Jn-XHg807$FDvjs@j;gN5@$v8any*I56&kuo2o*S>%6F}tiVNpgs z2V~sgIph_{D2FEtM0TX3_$&r8>F{&{k$vol=j}i;ABfxf0FYLP=MzA34$n7%G&npz z12X9F`~gU%!!zTRXbXquB|s+6iTiUb5czCaRQEa{69|6PPgjW4jfMw9BaTiWofya? zo((|c9kK|y49I9(+}8Vn41OqX>oy=mPQTazWMo^MN4^m#g8<+!9B&0-5d9{dUoF zYnsTOzpNR9E3M6xT9O(iwa$a2O zVjx8axfaOSopGs;i=I!$k*|v$2YCv}go7M_HA3ZGajBz#$a9dWEvkWJM&mrE04aVd zj;sWdwKeVR>d5yN3q1iAIZ-t7;E^Z1Q6BaIndKl?0jWDbZv7@f9G*`Dk>|{jo-rU< z2YDFCB&rbcJPBm3!?RBYncyHt0?9Z?4UnC#IUQUtH0s?xaN<6r@@i>EReuKzArpqi%b0i$WF)SKZ(@0 z;yn8vg?4w4V}Qt>mH1okGa3!x8GkE%24k=q$l!P5n$HKa+iBCciPVE}o~wY2I6OBA z@=%=TZXlzMt*-(ZdpOSXQy{Io;>a^Vg0{Ga`yGw;`f;4+6@u8vOD*OB8F6^d01`MJ zwh7Nq<9ap%8FFl01tk0PIL}9bOti-RxmToq5$BO_M9WOXkv{+leicXdI|e>K8b^)= z(&A)7HISTxECVv?NSzO4%;D(=vco~H1~TOM{9zzD2l*6`5l8AlAfpcQ6p-x>a?l)T zc91F{4UXm|Kz2Gj%|J$ic<){ZWUIsT4j_XLaxIWe4zdkM(Xn+Gkc@+T8OWHE8$Sdx z;UG@{8F7$*00|sD2fZ5g+P5M$9=-}l22Zl05wadg*3q*P$e5FLc_8Bs(g$S1LEa6d z^3b^E>wq-u6CZy*3S^UG>vKT1fF~L=9|6+o@H`Eqa&BDnzQ@96r&qoVNTq|E0A%8I zaj8>)Ogcy&NPsQVC>j@w9*f9$SlHCnpRow|gZF|b>mVNn(qIwp1DN|b8OJ(r!`|}? zM3#rY4{$4@@N!-bDfjdSakel1;|Vx;+=Kf7Td@Ny2C!e}*b#2->E-t0K0rV8ys9Fu ziM#0XQGuDEo`yFC!Dr$uVOjP8e%;G`fY-gTBKZ9alT5PjckwaY2l#`y?j0HM?0P|k zz6X2LK^4L4Js#Ny7=@QF!j(Pk`;EPX`v8+K^^^dReSr797VR49x$;OEzmkXS1Dtvw z_x+AQH2p*N0c4Nb#OFAl0Z8~B?D5K0sT4Z;#|yY!d)_ZbwGt zG^6<2tx1DBz%#ywxv~wPkL&7(RF%o_838lXXqKpc1D6kS6f-j?kRzxtc$~}O2{Ti8 zOlGF==<}V1gPEBUfA?T!K7hzeYR{~|O>d~t<&&&C^pi96>EwH0((Nh29qu-xQD6>w zE=chjBOmk(96Cd@?r*LUJ(H}Pm?G;Wqh_yQMlA-nZ%#6*a40kCgj8FSQR91&QNdzn zR1tb4QqjSkr3-CFt!r;z-^LHPS;ikCTQbZ9-`$`%uYP`2U2S07J(PSLQmvEd4<*OsIoedCR?+6z76?c?MF(^25}RW^ZT+SGw!YY?#WtM? z+g;i;l4pr+I*Dcyx6BHkR}E#G3Qw3VDSCuc+G6Sduq|rQ7Lp(CA#L${bUo7+?{hEe znZ&sP|4p1TKz)M}=k;%9oYQJ%K1uOD+u!{h6LZoQ**&xcBU(vIaYxuGX+mSc*f>)1`(+%fk;;}eOZvLKqk;#BII@; z4eK=PY=4h(L%z@92obdhb3-&6pY0`EU~X9J6`R2A9_;U(w!ddw2Ar|K%Oh?XG1BH8 zu83?cC_g>fafJI<(Tkk@c3+!tF8EN zay6UkkK}4`C3E%oR6Q~`eca~i%RGMtkX&uuL#_&staf(WabpJ%iDq;#pMPQVxxc%F ze0JA5$S-8e*aBUL`_&E=J_w#k<$+loKL=9W<4m-vBj1MgA9!UfpBd!yKrX_{$|5KP ze}SG>JU)}VfM|_m{E^(a1w3w=J)c}1Jb>evTH{$K;l@r1UPoNHqk@`!YF7+Xsg*~q8y zAQeO+gZ~H-;yf3B6ZvE6b#4Q$L_Xsrc4)m8iF8>W*qU?hx#zZm$Jm+`(_o78glEyB zMRHb-N3KbKpZQ((_j@tqVX{vg(%-vZ$Nqj@MdEUJD*gRy_<2s;yrAyqpojQu(%i;h5#jQG*P{{F1(@9nakSlAT% z{6E(T#jwXo-6MIHo=^Xh&lHFAPMV%De-_INfaP<;@GKJBW%DQGS#fS=YMw>X%ggD( zr7(YXJjDF@JiK;eC_Ius|3*hO>y~o_@(#(3F`FA1T=xSYbHVT#%#DJlLjW1)$M(?f zY|}&0HO(EXe2vD&d}pD%Sm@(hU$Bl2XxbE`sP9T>`^DfH^hVk!6Of{bV|tn3jv}Ix zBkhPCX;Vf3{r;Ad?MN%5vEMo}0+fEl7W^!XxwC`VlNLO?iY@q2fxJUna036Q>fQUC z$rk)Rboil_7M$Ee3yNWxsdG!&bC&~gW5iZoWLvpdDhzb=p4eCD?v1_8eH2=7NLw(i z=ZdW?c!C<8%>@XS0lAg^H0bXvD`0tgeIH4bHE@Yk$Xt?9`^{dS3aS&)@8t%WbeOh_Wq5bb@*idIuc*2X6CPkS2_Tj?d4co&Bbk%sd;Onm4ou(oBV!ncIuZ99qUPd;)sXGxI8&nOM@| zCGC#H?N%GIW%La?KKt&5{#^>5L3G#haT>L51($>0fqxo;A&{{hnJ@O%fzh{N-H zAPsM#6m!-1Be^R5@7T}>{&_yRYCWu2PH{__tMVW~X6%_2C)jH&Fju$PT*Wdh@g}_R zN*;b2{SmkO(6a-h-$H?%L-Md1FuDeKMp7d!dAQ{S=HYg?K~j7)iI-J ztK$bxBv*g8nz`DUnya#w7~G3IES}0d%s>ySA3HcgZj0yPdW@2>JY>6P8YB}WJ~0Ja z^xGW@69;#M#+Y>}dPGFp>+=0=djTAQwk$EPV7YtAGR?p7O?J&r(vk|FofUaVJ0;Xh3R$RX$W&w_K4&- z1xTxdtO7FXAZvl-7ICZ-smp*&I>?8BWKW6nd=ki*gM0x^>n{tEQFH6r zE6+E<=S8J5ie?vZ6g@k2=^#CK!e*U}>b@!&MH^1!C|Z6k`s%aTyT!6U0?3U2Z9C&P zCA>AKlD(C^Zi zX#V)_2Femx9=l_25V0;Jm3#cBGpgTals~R;US5LCl&doG~uYReuCC>g%}Z z>ynJR;v{C2bS?joY^j7O%)wTAw#YcYw1t_l8JvD-rIj1@qLo`uV=Mc%*t-YA78HNx zdk+7{+Cslmcg))IOa=cbTcTOwQ`|#*nBgzC8ICW1F7)*GZH_Wr^!y9WXnaoJePRrw zdihJO|5Uv=LT=iNe9rAfJ_koKpN~Ye((`%L=JPrUhj&OmH|#||f5GPSH=rXupGWr4 zUSc>Lwf2{!WcXL(|vi+w)-n%R!os|lic}A@0?jN z2Y=nwmvGA5wD1_V`!PsXnb+Mz=B9VrcAw{WK(Nc2<4P=5%+A{!x8kZUyieJS+&K4K z=En7~<(rf7IVhq|AZhn0Vov(|q|J>{AZ|b87+$iuv9YaGDmeFpd4)2|%CA!LMk;7M zmAS!8FjC^-bEty*ZrFb;6ZF~WU?-z7A(eLyj{Mtfwn!$p2eaiGn=P}!;6_X&BwNmX zEwe@X)jU@b&LmszcmqcXY|Ez{k}bEN%xsZQJ^P1b%lKYo%hPXRwlt<@i>!Mycn8z$ zbj|e*0g;T7&(TknQ6q2WibygF&czO9)JG6Dv+mtc>M8bh_4KcGmIWta+{oaIQ_AhZ z+WZN5B!3X*L@)S{<&VA(Ic9Uit&>!bxpAw_jqEZHjmHQ(RB}V^FW?evW${-4_mGuv1Kz$y)xh&G{`#pXxgnp2Ho4*Z zD;gy?T8q#T>cNsO<&e=Px01Qx`@=TPvQ7Qyq!opR@3%sOBuOPNXJ> z9CMKB2Ds-SwQoc-DWdD=x@lS8#I;_Wmi7BQ>y@5$8ID}* zPkGiiP0RWY&-yISy8Kd>cWY0&4g!t+_QeS zXMOv$tdDrscX`%#de*ml)<>sheVb=}+_OIBS^uzSeaEz{Z}qJ2^sMjjtY7b0ADfo- z>pkmZp7l}B`WDan&S_a6@~rRhtZ(+er)6F4w%nW_^{kJ0);D?9cTLOs7SFnT zcEs_gdaGx>$Fn{$E$f$i)<-<+L!Nc{W`Ffi=l3V3Wqr`IzSXn7#j}3CXMJ*7)-U#~ z4|&!HJ?lBo`tE62-{e`};#uG1SzqQ^5AbuFaz}-`68+h(O6Y;0Ao}Zd{=H1UXMNDK zUi7TL-m^YyTGor6^-Z4jPS5&0&wAywtap3Xi=OpX&$|4AlAH6hr)6Ds0-fGn)9G1n z@vI-}SkXduzaC)Q zi}&x-vfkoZU+!72^Q=GZS#Ow@^(N1HgJ(VKS%1v4zITu)-#^<2R!R7)3UzYvp(0eKHIbY8P9s_w5%`jtYb_2tcAY`=+9qiJjod?jmPZQ&6oEfLhBXb zn{STOx~Eqi`K(AyEIwNIukNAl+)?~rtXK7N?m47=a>~@briFLw<#`rPFgGeNz$Ol_ zUViKBVRi8oHQSxiR{BGvI>%ZNsa+oJ8foNzu!qPq>mohOx|l5;u?PPbvu-XTIaSt0 zJ~QiLK5O0AKuNhC$JY5@tXFjl+pBy=)pW9z%kwOpWNz#s>ukNASJq{znHg0hE8(y$ zh*ZnM*gL)zw=Xusgre!_jS(onzaIH^x*5w!Vlt+*}0ZryiH%lbZ^^&Ot|?Vk0| zc-AMTWj*k$k9yWeJnMIO)}NS`^?ydI6kTg=_pERAtl#QcpPZKU-JbOk&-##O{R+?e z?rB+n#pEWJ(PkGkmyXoBizR9zGhG)HU zTGr)Pa~)eXgP!%GXT939K6_f$AM>nl@~n4y)-#^<%(Sdec-D)a^;XaN0iN}_)3W|k z&w8h4y~VTsPc)W0(q^Y+eV1pw)w7=StUuvdubYop7rIP^kXduZ+q64Ps_S|K1Ewl$NA-+^*Yb`sAoMlE$cfy>kXdutY`iGp7oY#S(o2DcI#f} zS)c1!zrwTLIxXvCp7pF}J>yyL@vL`F%ldtu^|_w)*`D=A&w6oM)^~W;GoJNI&-y8z z^-a^VevfB;wr72oXML_`eQ;XVM?LG6p7p@9KHIatWm?wn@T|}BtncRD4)+sk|BcU+ z!2x;JrgxD;)3UzZvmSWXCq3&=d)Bv3%lfUJb@}xTt(O`7s-N(zKjc{-nU?ht&-$ci zeZsT;WzYKdX<3&~b2~MydBU^4%d>umXMJ>9*0*}rCp_!po^|<^E;s9TOw0Q9p7mXx z^_`yecX`&wre%G|vp()wAM>pDdDeGM%lb8*^_`ye9iH{`JnQ4rvcAQ$KIT~;^{g-R ztnZqZ^~*i$J3Q;#J?ry5>l4$mKImB=^{kJ0)-#^;0bft)BHQp7qB(>%p6+bN^oStPgqC2R-ZG_N>pEmi2DW z`WDanCeQi~&wAywtap0W2R-XW&-!-H`s`_0@9?Z|@~n4y)<5W3&rHjDt7pCFS#R~M zU*%b!J1y(ydDc5U>n)!3i#_YvX<2XathajBbDs5LWL=*I7Sa97Jq@%^LaiSABs8+6 ztJ4P70_*7H;k`eW#`8R$zl;8G)Y`-Icdza>vG{1+-?@jnbJhL7Sg-0?e1=&5DQC@W zK7A|Cv#^@`*cB)w4t|PF?&wXsw{Ko2U#@r}zALBDW52fPwBzxKIoN_r0U8^}SwKuQ zGWfhz2swZLS0i>od!HD$9;QS?u3un%MlCAvct~#Z62~U+JW$DRXOg_~k1N45ieTc_ z33|}=G$wJ*_k*X!_5#u4+mg?k4PiKzh^BqAbzWbouU(ZMC_M7*!R_+x!J-cvk70WR z!7Z>AtTTF~g-`<^V-sx`KKC4X9tAR_**p zuw58^C)jU*Y`50)_%_K4;r-n3*+d2&tShSl z0pYW)8NvF(`t`jV3W51VhG>@KIPl0J`DT!MK`w~vX$g5+W9`)egukpYL)yJtzDIg4 z1fzDp2s|TB46g>V8;InGv9%ot@0$#AFA(ls800%Z2H_s21C@FVNXE&i3Vif;Omo#p z9R_4bpYOoK@W+GKcF5a4k)9L4!#ACb)Ej{e+P1(a^b0*35ND^o&JfK`eAFz4G`XygWwKRv=L(91kh}l7*?oA|P9BRKXma0R+{GwRIi}+F*^BEuJ^B8z`I5GSIka0)z1Q31$s;Sq$ zS>%tCV@CqnX(P72tsDIk{nW{XI`Hr?dd>vGdtqdqeA&?H_;w>$m+OY7U2Hiq>=h{o z83dBi^^cKyFOVVVh_ZJWh#V1eCy?tMBQ%6qNg&RKL=OAA6s{^aWs$} zP7F^3l5u*$A|Ne}<}-jmam>SZk+SW+y1P&)F5MLH3Am~0M)1sbq^?$C$9qZeGEO&Ue197wW3qYQ6GT}!+b~xGc zMqwwtfPhLC3@21F3@^ zxo&v=4rHgJdA}O8yR))73<&onjMT9}!QO~^!JcCwGG5lhEGm=C+9{|sxjz4z+DO%0A6nq}Yq?12C03zd9q~}o} z8EZ?V{w7jRJ|9*KpKVli0TN6sjn^v+o@)*uQtDdQ)7Fh1XR}T;p9G#tCmM}F12Sf~@MP9-+z^f1fHXKG(kFmSu8s5D3nT~4QEq$X2a zEB{QStaZ`+Cy{cpr2^ml%1^SJY&i%B_u>pP2gs-s)g?g2oIG3&Bm?Ueuwta%1%#gy zpAqyGOxGQB>V7SFCI%RJ@o-oW$LG%gks}&KzX7Ddsp;cDp0Iil=l)(S-xy6%YwSt)#Kq{TN={z7qj`a(HxbfKxgge_Nquv8#mz4_F z&lrCiVBPe=yeyt|&IPD--wvq}E46l``2rsE+2oA!d=or@)25FD8FYO9H;~y*d(C=1 zdWsXVBZ0J9J;+1p?m?>)u@k{FYW)#EPXaRH=s69Dd%xTQWVe%tYk;&kdIo^ZvU34K$bi0)dFO$!_y9= z(zX}W2PGhbppmW1fs8wMtTzJL<@DvdflN65d>e?&U(sm%OCVXt`kw@`vv8Qt?Lc5X znp0-uTh=;(V0vQRfy~+v_pk~`&e6OA$Zp5_dBWq=v>V9fcGiRX;4&a{9iHof6dmL? z(PMoUsry9=G^*(jf$(=LObb2*L{>5pPX)dYENk0+?Z!U*{tnh-PL3T2p52br;Xt;+ zR@6FkfXs4u-YA-#@n$-7AWm-d0_k-0T%uA@u6_W>7DwuKhi7qHPkW(zMKAZ~ zjjj8@)9U#1T_8IhJwFFhbXxE!AcOktrbf@RKxRAbelWf_Yr@XUc?>sQ7;k1dnqLQ= zQ3qKJWT&;2H$UqdWE`Hez~kPrb^@t%W}*Qg;#m}*_W_Y3LOu>;ixbt)0$J{4=EFd? zS|nfS>+9(af(FN*KZ_oltN1Ni)Eaenvjx8dTxsJR{va}V>Owsk?K>|6Pu3aL=K|rg zq!|H1h_7wMxaw%G0Z*OvP%JM8(rWee_u{t?3w=RDD8+tyHh2OjV(WoyvU=7Q2l`83 z8Fy^GTcj)x%E665+_v~UkbgRJ!PiA9JTgI-{MV_gRjeiG0~ zy%PwZGtLM$;0vJT%k%0SpRWSXCTqQ~t*cak)-4XtHt-a!^|gHkVF`9RJa>Ud<^tpM zmvA<(qp)URUB0cat!G`K#M7>xwY@C2ty$Ao*ub;yuATzRYy0GrsHy>J#iDFrDXMDm zz1R8ny!-%}{>aXpd3}Yo#s0o|dF`BQ3hVG4v*x!)yo*@!m@TdqXRK(#CUCK@7ZZ4Y ze_MNJp~Dx#FQRsBzz-YAuc8hV%|5rMIl%;G49*@`$L5}J$5LF+%bod}Hf)-EY~fvE z8rqh^D^D(bURjak^ZI4G*v?yRy!ScPacsTF7xm_G(^2Z}38oY@KNZ$iEav++7g1C5 zJ8Fv-v8DFV_ra=qOY0k?J4ymC5rPF1OuftUHSIjo*w+T02FNK zYWEs-Bee8xEajyoC9y)0@Wzb-A=1%RO6Un;?9?k;e$8h5c2=p>)!UQr>Ik~K)_@@| z*HOs#46I*+;WCEGFUO|AZGG~{CB|sn&bM`R;M?L$DOXCx0@7Y3(2wZ1r-MAWr^&Ys z^!I{M`b_@9LSIjzJKxcVZeo2Drm&eP)!9};$`{+#bai+2Z#Hr2?p>GP5XiR)qrh{vTok}>Sr`DM*# zEN)tH<{9}sIJ4O*W2@ALPSsH(n-7NwHtaBI8P4fJ9B#*pTT+xC`J-7{~M4QhLLTi1F_Js4fqw)t5! zf4=nqzpsa}w6G`MI(jP}Se^N{ZX}I-$#%~=&+7#-PbBi4VD^}*ZGMJ75K$)M=T}$L zz8SAD$`;zzd+9zOZLR4Zrc_xr+uY88kZ)_3`O|Z?1v%%V~zLGRWS3ic1`E_+cQV>0_JsMvNo3I2)s9BI* zz=~mE-rJWCzhEOaUSP7eIsf`*evv8@mJ)ln$5_jMKfd;5aE zwvFLw9%HlNPdK-*4xP^RcVS&!jR#?@NpfZ9n^8fhlXh7w#cd~+Afbbt6JwQE@tD&| zL-jVpr4O6r(b~lACB*8pj+m+ap7^V3O?{$)0xi%{*d+7thPLj3WWp}2pKseWCKFX8 z5{!2i-;r1_O5wBXaQ%TAt}kMS!t5WZOg2J&jqTW`Cr%|F_he14OsY0lVs0d^BqLi_ z<@r%-M=lA4EL7&_v$%i6YX{*1CT1t8t=^9MVHNf$8}kvN5>}giTt~#KX6=x{ zXicdiW)Usdj}cYBeo138%<@v0$rGYi;aT8LObKyeI2-aNc4ITtw+ors5 zT{YHl^1GS&@RuUwu07##ea*t;y$Bko3qf%PYN`nrA-=uw{OCU$tW zi|j*?ONGtmL;?)MW`4p{G7e98lFhKdjwmr+<-&R_J+(UW*l}$~Nq>GdN+Z22?bss|x#m}*UUgagJfp{>vfAJ#rKo_- zjyoYYMCjmlnUpF?kDZIDV9Z9UD-zP^PD~QnL_r4x32~TyxRui@p05~~Lzb@Ia1mop z`U>*?Tse`2HC7~C&cq_Djo?|Svjagm+K?^YH=_GpPdZwpql&0=TX(^DV9NOtwgz!? zi%5hDl|$W<&MT{`*frc<;XYo#Qc&95({6{QeEXV&@r4VqE_8WpM#lQ1n*j?K;(o8A zHy_Ha8R)*y8c1rdn{V@1rh&fRJq(d}g059^RVo-R|M~`su@TyYx3|C8jUBf2ZT-0O zMg@J;g`CO6tyq1w$~I)D>W%G^*!?MWi7a*-#WHB>cgdZ37I(IePce;{#LTtz16YN} zGSr-7l10pPYrsGl5~WwfrIP2mD;wH0LbCbR)o#}KJ{;#qD|N)&2u~d^LS#)}Z(B!u z8}6V(Z6T(wJVb!xQS7>mOC2GWSQrc_2a9uq&7?Pd*%xzo5G_Ahka zzHZsw=m^>|vGo`7F(lkdlpZK|i{T;?GhDIDY*iQed<8G7xouxpzpyHh{vHks{+%YS zYdaRZu)k;OX^gMcjv4xf6XQ7c!BEyrKt;@XL$?>|r3U>nBlrxHWCZR^-#r6bv#lKhQ6>~Ed-enVV?x_i;-ov6f)?-0W zn+3buSP~CWzfIVxOzsl!N_%f{vmI&j;kN^KVkPPe7*wVU-Pu~+)v+YMtb3r;xoV(* z8yU%p-V)|$lj_lFINnF6$-Rx}iYT`?q_RH&Al#maSbV>tYvFr^5(XI(W9}H7E22{D zN=oG!X@4)NzNQYDBVj1(r;|YSwYBrHKm~uY#!0qpy=|zpMoh5J#};B#X)zmu@$+q#>u@;UQaGN;E zEL(~(W(|!dMA`6E;jSh{Y)=ubT99gKk1?%U;F@vzcd{m!;o~lqZ-FXo7sNUJ{*hE& zg+VPIq;h@ElfzbQOm2#tuF6)s>^dOE2d9LEY<;rQ-gaz#ZMGhRcg&5HZd#kITWE)7 zvp0qbKR_vb5Z|+IUVY7ingx~xqc?7IFlx(enaA(l%fo<3B`8cJuVD()!wk*hJ=lJ4MDXsI9WB<(qv0_TQ;+Z%3mA^Rw!v#Ff%!?uvJI zy&67l(p3tFd=8GrF^)HQve~sEG3eCP)P;jusKvc!Nk*@FenPf3i}X)&nK3d{hoAAo zGlSSH=knInV8@xBmJLo+>w(x_jFpqCWp^LrD*P?Y zaB7)y#9dfb71)PT;q#-;{r-7{AB3|yl6_G>wvX0e0bMfC>O%h+1M64x z;N6H*2G(M8D6w%+Ut6=V+Dhm83gNbK#}fQ1nxMHnbS`cys#`g%JC+WQqnAj5S~+Hg^Yy}~dgT#_^D zx^C%dALx^(o!A+~P=Ilvx76PhjuK@Cgqk{xE{r4SsRLMe^E}tNxr9x(?j_M4DV+-+ zA-E}4TZNm#PAnmkqXuO(dEJ>OaWAmqjI$Q4T(Km7_KGu>ElIR_?Sci>LHLw49MBV2 zYih7RC+1VlBwWQPXGfJiO>PSo#upb3CnLYdjlcSudgQ6}8*HG%H@jj?IA1#-&L`qD z)mmUdY?yK8g{1DRscbkNX>d3kCRl6g7uMO{?#-GKT&W8Bi#%yZ3hGmqd0nNxwt09! zLJpzP<*@#;A6UW@nb;HkdFXci^Xh}er%Q*+=gf0@JzEk!lFqMKvdB6lwsm9)pVAi5 z&j*T2x*)u`8v`vwN|^l=U5Xb3jFJ`du8o@jH48C;C!lI95Gjm|m;3HWex*Du=GC}r zed<}V7vT-X^x6`<6VTNid1g5p!RMl^Fmrlxj*7g4+%v4YRHHM*{$nraLb?7v>eiN97+Upv3X3u`r=Vo}|fFdtsNn@+QAf8oRh>9Afh1 zV7gxPr^OU=>(B9kEA;8j2?S-N|(nx`F^7@lmHSqN`si@R5 z_O@E`VGTbbn#cQWeT8*Kq5}pyWTQFM7+@jjp3_;ggPYHXn>%@YN}{)Kvl$<=0bZP0 zjkm4fD?(i?bS&G!xTgtq{=hr)KTIENpV4nsH(PbBbI#A|`Z<};dBoW3-lTfMY- z$(i}ar7O=|Y~B%Ddd3pGC-yu9Qkc8eW4(blzVP&2UO6+_w0h}svkR@yEF^;Filjik zVAk5k^-jFC1lQqvP*^{ZFNV82QZhd!oL|>7fTyY2W=Vax5t4}D1&GZiB^f%kC)e9c z0WX_(fAWZSZMAVo7~~lOIq0Yn4C4yO<=1BjNs)Zh%GGuoxL7I-bo8DWw$h0*Y2hcE z^B9liJLn24Bxa`|WY$~nN|0ZM?a$m&ZU4mSDVxub_d^*}%qz;bthaBGzTDkGYWJK8qOd30iu!hzs-DQ|!28s_AcMw6-NT(Nf<^D^R? zZ!4UKZEkrXH88(T9-W5S6rF}+)I3aFcy@PcGgg~RmY%iZjHacH%N8wOiav2l^XgNw z`DH6s0+MDg-*qI{!?7{)6tTyXh}d#lu7`sk6vC*eTz7skFqpk4I4sdu+9Oz84BIw-!(t07(bA%|c-a-x&gpHX z3j@F_@i1d)_!tc*k&BB;*2QS#!e(!2pjRH+;&nGafsj36MlD{7YN0iYrLg~(OydS; zcXUT=9&vIxXUCO`Y)gO);dIu-V?SuYwASPd_=sx6E6<8qY=?Dy4p)f zAYFs@%ETvI%$Q5%P0!x7;sy4QkT&wN0}{B@qn~EO2jat>_tWK3l=#!TCck!|N7~et zmHVJRJU$Ia`nC&XQ9rPz6gF#~3oE&n$9Mb4_ldAoO@)@gN`GN7h84ND! z&ASVd1Txm1En$Jib>{0tBB%E}M3~g+?Z(Sg?Rb94dC%xVzUjznJXj&CBCHFXK`wlG zJmS|o@A6Sq# zmsjF3<4QBDEDEBnCwXD9#5WeDJtPEJu!#qo7MTZO$=7DM+D#c1%2b0xo~Cr5$%x?g zqsIoOQSJNwOueEFsHxk^LfZx}+s&m${Q?SYCsd-TtNlVVKS$A+su7GX{hEWw3)2Cp zhIQc}Y=pv_!R6s=NjCh+9T-#-9UO1UMLnBJ!+|InXQLT)NgYJPI{LE<@}|&Nen`Nl zKjgC;($b5=C$3B74Q#nx?uxHF=~uK87m4tLUT9)$)XBb_-U+BW4jU!2z{Z0-Y}d+t zL^yb)e-gwv5>?Nc#>AreP*!ZVAHaASpX=o-dVonE6Mp?rv^hb9&P1rq(`}4gm?nZf zOxY_IH92D)bjjCU?5XeOgK#{};eBnH-mx)*EzY+M;MPRs)S>YErOX*(ht(vzc#{qt z!e<&IoG+v?!WB$>;MGrLx?}qPSID*PHVp((e^LK|!b6KHB9S52|aXy zs6v!nw#Xtw^1A2eQ|Y1zUC;pi?tnx(FJ+c!`z;^O!&m64!4;pwVg~%Ck&(b z@auBocHylDH}&`*H%b}4og2+S_fX*;5kvtU<=}?cz)Q`l@@h5-KS*n2S2-QDHSr=U zHfn%7JW`wUX&9XsG=oMOyq4j;AUt;nD=)>gYT$#=EAR*4&o~?bRkWU%yUfrXuCc?4 zyHi}SML{}otgmG?ljCi}a$uNbjt%(of!c+t)6;DgR_9E^ z-@`3yiEVe068jxwFLvG$B464!X=SYFonLnNM5aZG*?~hc=c0Muga;t;>A_COHIM-9 zPV4VXpf%wP33_J?^>K{Bq=S)pf4u%Yg1Ev($6J_#4?j`vb|uDBYFBL`WrsOFQEfUL zCdgh*v%a~pfq?V9M11jlBdD%=UF<<3EJRake42b + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/esl_blaster/FW02/.mxproject b/hardware/esl_blaster/FW02/.mxproject new file mode 100644 index 0000000..107bdc7 --- /dev/null +++ b/hardware/esl_blaster/FW02/.mxproject @@ -0,0 +1,14 @@ +[PreviousGenFiles] +HeaderPath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Inc +HeaderFiles=gpio.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f0xx_it.h;stm32_assert.h;stm32f0xx_hal_conf.h;main.h; +SourcePath=C:/Users/furrtek/Documents/Electro/ESLBlaster/FW/ESLBlaster/Src +SourceFiles=gpio.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f0xx_it.c;stm32f0xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Src\main.c;Src\gpio.c;Src\usb_device.c;Src\usbd_conf.c;Src\usbd_desc.c;Src\usbd_cdc_if.c;Src\stm32f0xx_it.c;Src\stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Src/system_stm32f0xx.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;null;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; +HeaderPath=Drivers\STM32F0xx_HAL_Driver\Inc;Drivers\STM32F0xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F0xx\Include;Drivers\CMSIS\Include;Inc; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F070x6; + diff --git a/hardware/esl_blaster/FW02/.project b/hardware/esl_blaster/FW02/.project new file mode 100644 index 0000000..205e5af --- /dev/null +++ b/hardware/esl_blaster/FW02/.project @@ -0,0 +1,30 @@ + + + ESLBlaster02 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/hardware/esl_blaster/FW02/.settings/language.settings.xml b/hardware/esl_blaster/FW02/.settings/language.settings.xml new file mode 100644 index 0000000..5d96a2b --- /dev/null +++ b/hardware/esl_blaster/FW02/.settings/language.settings.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/esl_blaster/FW02/.settings/stm32cubeide.project.prefs b/hardware/esl_blaster/FW02/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..7aba805 --- /dev/null +++ b/hardware/esl_blaster/FW02/.settings/stm32cubeide.project.prefs @@ -0,0 +1,4 @@ +2F62501ED4689FB349E356AB974DBE57=48E8977AAC6E0610396AB14E14747A8F +8DF89ED150041C4CBC7CB9A9CAA90856=48E8977AAC6E0610396AB14E14747A8F +DC22A860405A8BF2F2C095E5B6529F12=8536A59145044C9EC233B979117E068C +eclipse.preferences.version=1 diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h new file mode 100644 index 0000000..630a1e0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h @@ -0,0 +1,5635 @@ +/** + ****************************************************************************** + * @file stm32f070x6.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f070x6 + * @{ + */ + +#ifndef __STM32F070x6_H +#define __STM32F070x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.3 + */ +#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F0_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h new file mode 100644 index 0000000..56c908a --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_common_tables.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000..8742a56 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_const_structs.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000..726d06e --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_math.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_math.h new file mode 100644 index 0000000..d33f8a9 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..74c49c6 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000..cd13240 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_gcc.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..bb89fbb --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..711dad5 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0plus.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b04aa39 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm3.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b4ac4c7 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm4.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..dc840eb --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm7.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..3b7530a --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmFunc.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmInstr.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmSimd.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000..66bf5c2 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc000.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..514dbd8 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc300.h b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..8bd18aa --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..f605e57 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3533 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h new file mode 100644 index 0000000..e9747ee --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h @@ -0,0 +1,562 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_H +#define __STM32F0xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_conf.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Macros + * @{ + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#else +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#endif +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remapping HAL Pin remapping + * @{ + */ +#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). + 0: No remap (pin pair PA9/10 mapped on the pins) + 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ + +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection + * @note Applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ +#endif +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ + +/** + * @} + */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @note applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */ + +#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ +#if defined(STM32F091xC) +#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ +#endif +#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ +#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ +#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ +#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ +#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ +#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ +#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ +#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ +#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ +#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ +#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ +#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ +#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ +#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ +#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ +#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ +#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ +#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ +#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ +#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ +#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ +#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ +#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ +#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ +#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ +#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ +#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ +#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ +#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ +#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ +#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ +#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ +#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ +#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ + +#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup Memory_Mapping_Selection Memory Mapping Selection + * @{ + */ +#if defined(SYSCFG_CFGR1_MEM_MODE) +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#endif /* SYSCFG_CFGR1_MEM_MODE */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ +/** + * @} + */ + + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remap HAL Pin remap + * @brief Pin remapping enable/disable macros + * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping + * @{ + */ +#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 |= (__PIN_REMAP__); \ + }while(0) +#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * That you can find above these macros. + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ + +#if defined(SYSCFG_CFGR2_PVD_LOCK) +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_PVD_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +/** @defgroup SRAM_Parity_Lock SRAM Parity Lock + * @{ + */ +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PEF) +/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM + * @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + * @{ + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PEF */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check + * @brief ISR wrapper check + * @note This feature is applicable on STM32F09x + * @note Allow to determine interrupt source per line. + * @{ + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection + * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register + * @note This feature is applicable on STM32F09x + * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @{ + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ + SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ + SYSCFG->CFGR1 |= (__SOURCE__); \ + }while(0) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); +uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h new file mode 100644 index 0000000..ebea4ea --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h @@ -0,0 +1,149 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CORTEX_H +#define __STM32F0xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ +/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *******************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h new file mode 100644 index 0000000..a65b44e --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DEF +#define __STM32F0xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#if defined(USE_HAL_LEGACY) + #include "Legacy/stm32_hal_legacy.h" +#endif +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ + (__DMA_HANDLE_).Parent = (__HANDLE__); \ + } while(0) + +#define UNUSED(x) ((void)(x)) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h new file mode 100644 index 0000000..6a9fb70 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_H +#define __STM32F0xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ +} DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ +#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ +#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ +#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ +#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ +#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ +#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ +#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ +#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ +#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ +#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ +#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ +#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ +#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ +#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ +#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ +#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ +#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ +#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ +#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ +#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ +#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ +#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ +#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ +#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ +#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ +#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ +#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ + +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ +#if defined (STM32F070xB) +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. + 0: Disabled, need to remap before use + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ + +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif + +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_DMA_RMP */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping + */ +#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +#endif /* SYSCFG_CFGR1_DMA_RMP */ + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* Input and Output operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#if defined(SYSCFG_CFGR1_DMA_RMP) + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ + ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ + ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ + ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) +#elif defined (STM32F070xB) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#else +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#endif + +#endif /* SYSCFG_CFGR1_DMA_RMP */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h new file mode 100644 index 0000000..03217b1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h @@ -0,0 +1,827 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_EX_H +#define __STM32F0xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ +#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#if !defined(STM32F030xC) +#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#endif /* !defined(STM32F030xC) */ + +/****************** DMA1 remap bit field definition********************/ +/* DMA1 - Channel 1 */ +#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ +#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ +#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 2 */ +#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ +#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 3 */ +#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 4 */ +#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 5 */ +#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if !defined(STM32F030xC) +/* DMA1 - Channel 6 */ +#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ +/* DMA1 - Channel 7 */ +#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ + +/****************** DMA2 remap bit field definition********************/ +/* DMA2 - Channel 1 */ +#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ +/* DMA2 - Channel 2 */ +#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ +/* DMA2 - Channel 3 */ +#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ +#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ +#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ +/* DMA2 - Channel 4 */ +#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ +#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ +#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ +/* DMA2 - Channel 5 */ +#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) + +#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) +#endif /* STM32F030xC */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros + * @{ + */ +/* Interrupt & Flag management */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#elif defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif + + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define __HAL_DMA1_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ + DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_DMA2_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ + DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) +#endif /* STM32F091xC || STM32F098xx */ + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h new file mode 100644 index 0000000..f2ee248 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_H +#define __STM32F0xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f0xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h new file mode 100644 index 0000000..0d127e3 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_EX_H +#define __STM32F0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1))/*||\ + ((LEVEL) == OB_RDP_LEVEL_2))*/ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) + +#if defined(FLASH_OBR_BOOT_SEL) +#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) +#endif /* FLASH_OBR_BOOT_SEL */ + + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and + @ref FLASHEx_OB_RAM_Parity_Check_Enable */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size FLASHEx Page Size + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ + || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES (0x00U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_H +#define __STM32F0xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32f0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h new file mode 100644 index 0000000..82169b4 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h @@ -0,0 +1,816 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_EX_H +#define __STM32F0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined (STM32F030x6) +/*------------------------- STM32F030x6---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x6 */ + +/*---------------------------------- STM32F030x8 -------------------------------------------*/ +#if defined (STM32F030x8) +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x8 */ + +#if defined (STM32F031x6) || defined (STM32F038xx) +/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F031x6 || STM32F038xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) +/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F051x8/STM32F058xx */ + +#if defined (STM32F071xB) +/*--------------------------- STM32F071xB ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F071xB */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */ +#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */ +#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */ +#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ +#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */ +#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +/*--------------------------- STM32F030xC ----------------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030xC */ + +#if defined (STM32F072xB) || defined (STM32F078xx) +/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined (STM32F070xB) +/*---------------------------------- STM32F070xB ---------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070xB */ + +#if defined (STM32F042x6) || defined (STM32F048xx) +/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined (STM32F070x6) +/*--------------------------------------- STM32F070x6 ----------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070x6 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index +* @{ + */ +#if defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif + +#if !defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if !defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 5U) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h new file mode 100644 index 0000000..dfdbdec --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h @@ -0,0 +1,708 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_H +#define __STM32F0xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 IP initilisation status\n + * 0 : Reset (IP not initialized)\n + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (IP in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (IP busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ +} I2C_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP I2C_CR2_STOP +#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE I2C_CR2_START +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f0xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h new file mode 100644 index 0000000..69bc8fb --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_EX_H +#define __STM32F0xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#else +#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ +#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ +#endif +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if defined(I2C_CR1_WUPEN) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +#endif +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h new file mode 100644 index 0000000..974827c --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h @@ -0,0 +1,835 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PCD_H +#define __STM32F0xx_HAL_PCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U +} PCD_StateTypeDef; + +/** + * @brief PCD double buffered endpoint direction + */ +typedef enum +{ + PCD_EP_DBUF_OUT, + PCD_EP_DBUF_IN, + PCD_EP_DBUF_ERR, +}PCD_EP_DBUF_DIR; + +/** + * @brief PCD endpoint buffer number + */ +typedef enum +{ + PCD_EP_NOBUF, + PCD_EP_BUF0, + PCD_EP_BUF1 +}PCD_EP_BUF_NUM; + +/** + * @brief PCD Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref PCD_EP0_MPS */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode + This parameter can be set to ENABLE or DISABLE */ + + uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + +}PCD_InitTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref PCD_EP_Type */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +}PCD_EPTypeDef; + +typedef USB_TypeDef PCD_TypeDef; + +/** + * @brief PCD Handle Structure definition + */ +typedef struct +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + void *pData; /*!< Pointer to upper stack Handler */ + +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extension module */ +#include "stm32f0xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Core_Speed PCD Core Speed + * @{ + */ +#define PCD_SPEED_HIGH 0 /* Not Supported */ +#define PCD_SPEED_FULL 2 +/** + * @} + */ + + /** @defgroup PCD_Core_PHY PCD Core PHY + * @{ + */ +#define PCD_PHY_EMBEDDED 2 +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) + +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +/** + * @} + */ + +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define PCD_EP0MPS_64 DEP0CTL_MPS_64 +#define PCD_EP0MPS_32 DEP0CTL_MPS_32 +#define PCD_EP0MPS_16 DEP0CTL_MPS_16 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_EP_Type PCD EP Type + * @{ + */ +#define PCD_EP_TYPE_CTRL 0 +#define PCD_EP_TYPE_ISOC 1 +#define PCD_EP_TYPE_BULK 2 +#define PCD_EP_TYPE_INTR 3 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 ((uint8_t)0U) +#define PCD_ENDP1 ((uint8_t)1U) +#define PCD_ENDP2 ((uint8_t)2U) +#define PCD_ENDP3 ((uint8_t)3U) +#define PCD_ENDP4 ((uint8_t)4U) +#define PCD_ENDP5 ((uint8_t)5U) +#define PCD_ENDP6 ((uint8_t)6U) +#define PCD_ENDP7 ((uint8_t)7U) +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) + + + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + (((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) + + +/** + * @brief free buffer used from the application realizing it to the line + toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir Direction + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ +{\ + if ((bDir) == PCD_EP_DBUF_OUT)\ + { /* OUT double buffered endpoint */\ + PCD_TX_DTOG((USBx), (bEpNum));\ + }\ + else if ((bDir) == PCD_EP_DBUF_IN)\ + { /* IN double buffered endpoint */\ + PCD_RX_DTOG((USBx), (bEpNum));\ + }\ +} + +/** + * @brief gets direction of the double buffered endpoint + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval EP_DBUF_OUT, EP_DBUF_IN, + * EP_DBUF_ERR if the endpoint counter not yet programmed. + */ +#define PCD_GET_DB_DIR(USBx, bEpNum)\ +{\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\ + return(PCD_EP_DBUF_OUT);\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\ + return(PCD_EP_DBUF_IN);\ + else\ + return(PCD_EP_DBUF_ERR);\ +} + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ + \ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wState))!= 0U)\ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\ + } /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ + register uint32_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ + } /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ + == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ + == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK)))) +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))) + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) +#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ + { \ + PCD_RX_DTOG((USBx),(bEpNum));\ + } +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\ + {\ + PCD_TX_DTOG((USBx),(bEpNum));\ + } + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ + USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr)) + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U))))) + +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U))))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param dwReg Register + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 5U;\ + if(((wCount) & 0x1fU) == 0U)\ + { \ + (wNBlocks)--;\ + } \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \ + }/* PCD_CALC_BLK32 */ + + +#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 1U;\ + if(((wCount) & 0x1U) != 0U)\ + { \ + (wNBlocks)++;\ + } \ + *pdwReg = (uint16_t)((wNBlocks) << 10U);\ + }/* PCD_CALC_BLK2 */ + + +#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ + uint16_t wNBlocks;\ + if((wCount) > 62U) \ + { \ + PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \ + } \ + else \ + { \ + PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \ + } \ + }/* PCD_SET_EP_CNT_RX_REG */ + + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\ + } + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) +#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \ + PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ + } + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr))) + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @param wBuf1Addr buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ + } /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \ + else if((bDir) == PCD_EP_DBUF_IN)\ + { \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ + } /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + {/* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \ + } \ + else if((bDir) == PCD_EP_DBUF_IN)\ + {/* IN endpoint */ \ + *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ + } /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + } /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +/** @defgroup PCD_Instance_definition PCD Instance definition + * @{ + */ +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h new file mode 100644 index 0000000..35a70b6 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PCD_EX_H +#define __STM32F0xx_HAL_PCD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Internal macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h new file mode 100644 index 0000000..ce9b7dd --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_H +#define __STM32F0xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * Warning: this Flag is not available on STM32F030x8 products + * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference + * voltage VREFINT is ready. + * Warning: this Flag is not available on STM32F030x8 products + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h new file mode 100644 index 0000000..ef74a81 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h @@ -0,0 +1,475 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_EX_H +#define __STM32F0xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + This parameter can be a value of @ref PWREx_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVD_Mode */ +}PWR_PVDTypeDef; + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) +#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7) || \ + ((PIN) == PWR_WAKEUP_PIN8)) + +#elif defined(STM32F030xC) || defined (STM32F070xB) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#elif defined(STM32F042x6) || defined (STM32F048xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#else +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) + + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) + +#endif + +/** + * @} + */ + +/** @defgroup PWREx_EXTI_Line PWREx EXTI Line + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + +#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ +/** + * @} + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/** + * @} + */ + +/** @defgroup PWREx_PVD_Mode PWREx PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +/** + * @} + */ +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +/** @defgroup PWREx_Flag PWREx Flag + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#else +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWREx Exported Macros + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ + do{ \ + EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + } while(0) + +/** + * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) + +/** + * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. + * @retval EXTI VDDIO2 Monitor Line Status. + */ +#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Clear the VDDIO2 Monitor EXTI flag. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) + + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +/* I/O operation functions ***************************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_Vddio2Monitor_IRQHandler(void); +void HAL_PWREx_Vddio2MonitorCallback(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/* Peripheral Control functions **********************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_EnableVddio2Monitor(void); +void HAL_PWREx_DisableVddio2Monitor(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h new file mode 100644 index 0000000..c9cf5a6 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h @@ -0,0 +1,1702 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_H +#define __STM32F0xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 + +/** + * @} + */ + + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1U) +#define CR2_REG_INDEX ((uint8_t)2U) +#define BDCR_REG_INDEX ((uint8_t)3U) +#define CSR_REG_INDEX ((uint8_t)4U) + +/* Bits position in in the CFGR register */ +#define RCC_CFGR_PLLMUL_BITNUMBER 18U +#define RCC_CFGR_HPRE_BITNUMBER 4U +#define RCC_CFGR_PPRE_BITNUMBER 8U +/* Flags in the CFGR2 register */ +#define RCC_CFGR2_PREDIV_BITNUMBER 0 +/* Flags in the CR register */ +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 +/* Flags in the CR2 register */ +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 +/* Flags in the BDCR register */ +#define RCC_BDCR_LSERDY_BitNumber 1 +/* Flags in the CSR register */ +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 +/* Flags in the HSITRIM register */ +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_HSI14TRIM_BIT_NUMBER 3 +#define RCC_FLAG_MASK ((uint8_t)0x1FU) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ + ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ + ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ + ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ + ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ + ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ + ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ + ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t HSI14State; /*!< The new state of the HSI14. + This parameter can be a value of @ref RCC_HSI14_Config */ + + uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_HSI48_SUPPORT) + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_HSI48_SUPPORT */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) +#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ +#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Config RCC HSI14 Config + * @{ + */ +#define RCC_HSI14_OFF (0x00000000U) +#define RCC_HSI14_ON RCC_CR2_HSI14ON +#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) + +#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00U) +#define RCC_HSI48_ON ((uint8_t)0x01U) + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ +#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 +#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 + +/** + * @} + */ + +/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor + * @{ + */ + +#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +/** + * @} + */ + + +/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK + +/** + * @} + */ +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL +#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_CIR_HSI48RDYF) +#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ +#endif +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: CR2 register + * - 011: BDCR register + * - 0100: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) +/* Flags in the CR2 register */ +#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) +#if defined(RCC_CSR_V18PWRRSTF) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) +#endif +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + + +/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) +/** + * @} + */ +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration + * @{ + */ + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). + * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software + * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be + * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. + * clock cycles. + */ +#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI14 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI14 RC. + * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSI14CALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) +/** + * @} + */ + +/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) + +/** + * @} + */ + +/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ + } while(0U) + + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif +#if defined(RCC_CFGR_MCOPRE) +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#else + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + +#endif + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, + * the RTC cannot be used in STOP and STANDBY modes. + * @note The system must always be configured so as to get a PCLK frequency greater than or + * equal to the RTCCLK frequency for a proper operation of the RTC. + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready + @if STM32F038xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F042x6 + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F048xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F058xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F071xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F072xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F078xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F091xC + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F098xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ + (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h new file mode 100644 index 0000000..e86d950 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h @@ -0,0 +1,2101 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_EX_H +#define __STM32F0xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#else + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV + +/** + * @} + */ + +/** @addtogroup RCC_Interrupt + * @{ + */ +#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source_Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 +/** + * @} + */ + +#else +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ + +#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#else +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 +#endif + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @addtogroup RCC_MCO_Clock_Source + * @{ + */ + +#if defined(RCC_CFGR_PLLNODIV) + +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#endif /* RCC_CFGR_PLLNODIV */ + +#if defined(RCC_CFGR_MCO_HSI48) + +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 + +#endif /* SRCC_CFGR_MCO_HSI48 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Private Constants -------------------------------------------------------------*/ +#if defined(CRS) +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(RCC_CFGR_MCOPRE) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ + ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) +#else + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) + +#endif /* RCC_CFGR_MCOPRE */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) +#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) +#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) +#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ + ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +#endif /* CRS */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F072xB || STM32F078xx */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +}RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3FU */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +}RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USART3 (0x00040000U) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK +#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE +#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI + +/** + * @} + */ + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK +#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE +#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI + +/** + * @} + */ + +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 +#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) + +#define RCC_MCODIV_1 (0x00000000U) +#define RCC_MCODIV_2 (0x10000000U) +#define RCC_MCODIV_4 (0x20000000U) +#define RCC_MCODIV_8 (0x30000000U) +#define RCC_MCODIV_16 (0x40000000U) +#define RCC_MCODIV_32 (0x50000000U) +#define RCC_MCODIV_64 (0x60000000U) +#define RCC_MCODIV_128 (0x70000000U) + +#else + +#define RCC_MCODIV_1 (0x00000000U) + +#endif /* RCC_CFGR_MCOPRE */ + +/** + * @} + */ + +/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration + * @{ + */ + +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE (0x00000000U) +#define RCC_CRS_TIMEOUT (0x00000001U) +#define RCC_CRS_SYNCOK (0x00000002U) +#define RCC_CRS_SYNCWARN (0x00000004U) +#define RCC_CRS_SYNCERR (0x00000008U) +#define RCC_CRS_SYNCMISS (0x00000010U) +#define RCC_CRS_TRIMOVF (0x00000020U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) +#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases peripheral reset. + * @{ + */ + +/** @brief Force or release AHB peripheral reset. + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) + +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @brief Force or release APB1 peripheral reset. + */ +#if defined(STM32F030x8) \ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) + +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) + +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) + +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) + +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) + +#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + + +/** @brief Force or release APB2 peripheral reset. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) + +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) + +#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** @brief AHB Peripheral Clock Enable Disable Status + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) +#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) +#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) +#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable + * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI48 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software + * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be + * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. + * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator + * clock cycles. + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) + +/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSI48_ON HSI48 enabled + * @arg @ref RCC_HSI48_OFF HSI48 disabled + */ +#define __HAL_RCC_GET_HSI48_STATE() \ + (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) + +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F070x6) || defined(STM32F070xB) + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx || */ + /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @brief Macro to configure the CEC clock. + * @param __CECCLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) + +/** @brief Macro to get the HDMI CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined(STM32F098xx) */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ + RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag + * @{ + */ +/* Interrupt & Flag management */ + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0U) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustement of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Disable the automatic hardware adjustement of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h new file mode 100644 index 0000000..410138a --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h @@ -0,0 +1,1830 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_H +#define __STM32F0xx_HAL_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + + +/** + * @brief TIM Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter can be a value of @ref TIM_ClearInput_Prescaler */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct { + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +}TIM_SlaveConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +}HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +typedef struct +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref TIM_DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +}TIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP (0x0000U) +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 (0x0000U) +#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) +#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes + * @{ + */ +#define TIM_OCMODE_TIMING (0x0000U) +#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE (0x0000U) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH (0x0000U) +#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH (0x0000U) +#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) +#define TIM_OCIDLESTATE_RESET (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) +#define TIM_OCNIDLESTATE_RESET (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 (0x0000U) +#define TIM_CHANNEL_2 (0x0004U) +#define TIM_CHANNEL_3 (0x0008U) +#define TIM_CHANNEL_4 (0x000CU) +#define TIM_CHANNEL_ALL (0x0018U) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) +#define TIM_OPMODE_REPETITIVE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE (TIM_DIER_UIE) +#define TIM_IT_CC1 (TIM_DIER_CC1IE) +#define TIM_IT_CC2 (TIM_DIER_CC2IE) +#define TIM_IT_CC3 (TIM_DIER_CC3IE) +#define TIM_IT_CC4 (TIM_DIER_CC4IE) +#define TIM_IT_COM (TIM_DIER_COMIE) +#define TIM_IT_TRIGGER (TIM_DIER_TIE) +#define TIM_IT_BREAK (TIM_DIER_BIE) +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) +#define TIM_COMMUTATION_SOFTWARE (0x0000U) + +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE (TIM_DIER_UDE) +#define TIM_DMA_CC1 (TIM_DIER_CC1DE) +#define TIM_DMA_CC2 (TIM_DIER_CC2DE) +#define TIM_DMA_CC3 (TIM_DIER_CC3DE) +#define TIM_DMA_CC4 (TIM_DIER_CC4DE) +#define TIM_DMA_COM (TIM_DIER_COMDE) +#define TIM_DMA_TRIGGER (TIM_DIER_TDE) +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE (TIM_SR_UIF) +#define TIM_FLAG_CC1 (TIM_SR_CC1IF) +#define TIM_FLAG_CC2 (TIM_SR_CC2IF) +#define TIM_FLAG_CC3 (TIM_SR_CC3IF) +#define TIM_FLAG_CC4 (TIM_SR_CC4IF) +#define TIM_FLAG_COM (TIM_SR_COMIF) +#define TIM_FLAG_TRIGGER (TIM_SR_TIF) +#define TIM_FLAG_BREAK (TIM_SR_BIF) +#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) +#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) +#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) +#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 (0x0000U) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) +#define TIM_OSSR_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) +#define TIM_OSSI_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF (0x0000U) +#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) +#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) +#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable + * @{ + */ +#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) +#define TIM_BREAK_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW (0x0000U) +#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) +/** + * @} + */ +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) +#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET (0x0000U) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave Mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE (0x0000U) +#define TIM_SLAVEMODE_RESET (0x0004U) +#define TIM_SLAVEMODE_GATED (0x0005U) +#define TIM_SLAVEMODE_TRIGGER (0x0006U) +#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) +#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 (0x0000U) +#define TIM_TS_ITR1 (0x0010U) +#define TIM_TS_ITR2 (0x0020U) +#define TIM_TS_ITR3 (0x0030U) +#define TIM_TS_TI1F_ED (0x0040U) +#define TIM_TS_TI1FP1 (0x0050U) +#define TIM_TS_TI2FP2 (0x0060U) +#define TIM_TS_ETRF (0x0070U) +#define TIM_TS_NONE (0xFFFFU) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 (0x0000U) +#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 (0x00000000) +#define TIM_DMABASE_CR2 (0x00000001) +#define TIM_DMABASE_SMCR (0x00000002) +#define TIM_DMABASE_DIER (0x00000003) +#define TIM_DMABASE_SR (0x00000004) +#define TIM_DMABASE_EGR (0x00000005) +#define TIM_DMABASE_CCMR1 (0x00000006) +#define TIM_DMABASE_CCMR2 (0x00000007) +#define TIM_DMABASE_CCER (0x00000008) +#define TIM_DMABASE_CNT (0x00000009) +#define TIM_DMABASE_PSC (0x0000000A) +#define TIM_DMABASE_ARR (0x0000000B) +#define TIM_DMABASE_RCR (0x0000000C) +#define TIM_DMABASE_CCR1 (0x0000000D) +#define TIM_DMABASE_CCR2 (0x0000000E) +#define TIM_DMABASE_CCR3 (0x0000000F) +#define TIM_DMABASE_CCR4 (0x00000010) +#define TIM_DMABASE_BDTR (0x00000011) +#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_OR (0x00000013) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +/** + * @} + */ + +/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE (0x0001U) +#define TIM_CCx_DISABLE (0x0000U) +#define TIM_CCxN_ENABLE (0x0004U) +#define TIM_CCxN_DISABLE (0x0000U) +/** + * @} + */ + +/** + * @} + */ + +/* Private Constants -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ + +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ + ((STATE) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) + +#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_TRIGGER) || \ + ((FLAG) == TIM_FLAG_BREAK) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ + ((STATE) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ + ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ + ((BASE) == TIM_DMABASE_CR2) || \ + ((BASE) == TIM_DMABASE_SMCR) || \ + ((BASE) == TIM_DMABASE_DIER) || \ + ((BASE) == TIM_DMABASE_SR) || \ + ((BASE) == TIM_DMABASE_EGR) || \ + ((BASE) == TIM_DMABASE_CCMR1) || \ + ((BASE) == TIM_DMABASE_CCMR2) || \ + ((BASE) == TIM_DMABASE_CCER) || \ + ((BASE) == TIM_DMABASE_CNT) || \ + ((BASE) == TIM_DMABASE_PSC) || \ + ((BASE) == TIM_DMABASE_ARR) || \ + ((BASE) == TIM_DMABASE_RCR) || \ + ((BASE) == TIM_DMABASE_CCR1) || \ + ((BASE) == TIM_DMABASE_CCR2) || \ + ((BASE) == TIM_DMABASE_CCR3) || \ + ((BASE) == TIM_DMABASE_CCR4) || \ + ((BASE) == TIM_DMABASE_BDTR) || \ + ((BASE) == TIM_DMABASE_DCR) || \ + ((BASE) == TIM_DMABASE_OR)) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __ICPSC__ specifies the prescaler value. + * @retval None + */ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @retval None + */ +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + + +/** @brief Set TIM IC polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __POLARITY__ specifies TIM Channel Polarity + * @retval None + */ +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) + +/** @brief Reset TIM IC polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @retval None + */ +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state + * @param __HANDLE__ TIM handle. + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) +/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/* The Main Output Enable of a timer instance is disabled unconditionally */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled uncondiotionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** + * @brief Enables the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** + * @brief Enables the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disables the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Checks whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Checks whether the specified TIM interrupt has occurred or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Clear the TIM interrupt pending bits + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Sets the TIM active prescaler register value on update event. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the active prescaler register new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Sets the TIM Capture Compare Register value on runtime without + * calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) + +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) + +/** + * @brief Sets the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Sets the TIM Autoreload Register value on runtime without calling + * another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Sets the TIM Clock Division value on runtime without calling + * another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) + + +/** + * @brief Sets the TIM Input Capture prescaler on runtime without calling + * another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * (+) Counter overflow/underflow + * (+) Setting the UG bit + * (+) Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + +/** + * @brief Sets the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ + +/* Include TIM HAL Extension module */ +#include "stm32f0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @{ + */ +/* Timer PWM functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions ***********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions ***************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 + * @{ + */ +/* Timer Encoder functions *****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group9 + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h new file mode 100644 index 0000000..a504794 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_EX_H +#define __STM32F0xx_HAL_TIM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIMEx Exported Types + * @{ + */ + + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct { + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +}TIM_MasterConfigTypeDef; + +/** + * @brief TIM Break and Dead time configuration Structure definition + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIMEx Remap + * @{ + */ + +#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ +#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ +/** + * @} + */ + +/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE (0x00000000U) +#define TIM_CLEARINPUTSOURCE_ETR (0x00000001U) +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ + ((TIM_REMAP) == TIM_TIM14_RTC) ||\ + ((TIM_REMAP) == TIM_TIM14_HSE) ||\ + ((TIM_REMAP) == TIM_TIM14_MCO)) + +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 + * @{ + */ +/* Extension Callback *********************************************************/ +void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 + * @{ + */ +/* Extension Peripheral State functions **************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +* @{ +*/ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +/** +* @} +*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h new file mode 100644 index 0000000..4059159 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h @@ -0,0 +1,861 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_BUS_H +#define __STM32F0xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN +#endif /*GPIOD*/ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN +#endif /*GPIOE*/ +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN +#if defined(TSC) +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN +#endif /*TSC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /*TIM2*/ +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(USART2) +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#endif /* USART2 */ +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN +#endif /* USART4 */ +#if defined(USART5) +#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN +#endif /* USART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /* USB */ +#if defined(CAN) +#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN +#endif /*CAN*/ +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN +#endif /*CRS*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /*DAC*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(USART8) +#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN +#endif /*USART8*/ +#if defined(USART7) +#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN +#endif /*USART7*/ +#if defined(USART6) +#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /*USART6*/ +#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(TIM15) +#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /*TIM15*/ +#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 1). + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 1). + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock (available in register 2). + * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n + * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n + * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n + * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset (available in register 2). + * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n + * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h new file mode 100644 index 0000000..4044db1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h @@ -0,0 +1,336 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CORTEX_H +#define __STM32F0xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC20 for Cortex-M0 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h new file mode 100644 index 0000000..4f154c1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h @@ -0,0 +1,799 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_CRS_H +#define __STM32F0xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. + * A higher TRIM value corresponds to a higher output frequency + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_CRS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h new file mode 100644 index 0000000..9d9eb97 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h @@ -0,0 +1,2224 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_DMA_H +#define __STM32F0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /*DMA1_Channel6*/ +#if defined(DMA1_Channel7) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +#endif /*DMA1_Channel7*/ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/* Define used to get CSELR register offset */ +#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + +/* Defines used for the bit position in the register and perform offsets */ +#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMA_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ +/** + * @} + */ +#endif + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + LL_DMA_CHANNEL_6) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + DMA1_Channel6) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) +/** + * @brief Set DMA request for DMA instance on Channel x. + * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. + * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n + * CSELR C2S LL_DMA_SetPeriphRequest\n + * CSELR C3S LL_DMA_SetPeriphRequest\n + * CSELR C4S LL_DMA_SetPeriphRequest\n + * CSELR C5S LL_DMA_SetPeriphRequest\n + * CSELR C6S LL_DMA_SetPeriphRequest\n + * CSELR C7S LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) +{ + MODIFY_REG(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); +} + +/** + * @brief Get DMA request for DMA instance on Channel x. + * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n + * CSELR C2S LL_DMA_GetPeriphRequest\n + * CSELR C3S LL_DMA_GetPeriphRequest\n + * CSELR C4S LL_DMA_GetPeriphRequest\n + * CSELR C5S LL_DMA_GetPeriphRequest\n + * CSELR C6S LL_DMA_GetPeriphRequest\n + * CSELR C7S LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(DMAx->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} +#endif + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} +#endif + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} +#endif + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h new file mode 100644 index 0000000..647409c --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h @@ -0,0 +1,1032 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_EXTI_H +#define __STM32F0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h new file mode 100644 index 0000000..2782b06 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h @@ -0,0 +1,955 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_GPIO_H +#define __STM32F0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h new file mode 100644 index 0000000..3a6449d --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h @@ -0,0 +1,568 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_PWR_H +#define __STM32F0xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +#if defined(PWR_CSR_EWUP4) +#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ +#endif /* PWR_CSR_EWUP4 */ +#if defined(PWR_CSR_EWUP5) +#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ +#endif /* PWR_CSR_EWUP5 */ +#if defined(PWR_CSR_EWUP6) +#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ +#endif /* PWR_CSR_EWUP6 */ +#if defined(PWR_CSR_EWUP7) +#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ +#endif /* PWR_CSR_EWUP7 */ +#if defined(PWR_CSR_EWUP8) +#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ +#endif /* PWR_CSR_EWUP8 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 (*) + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 (*) + * @arg @ref LL_PWR_WAKEUP_PIN7 (*) + * @arg @ref LL_PWR_WAKEUP_PIN8 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h new file mode 100644 index 0000000..50bba6b --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h @@ -0,0 +1,2257 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_RCC_H +#define __STM32F0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used for the bit position in the register and perform offsets*/ +#define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ +#define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#if defined(RCC_CSR_V18PWRRSTF) +#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ +#endif /* RCC_CSR_V18PWRRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ +#endif /* RCC_CFGR_SW_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#if defined(RCC_CFGR_SWS_HSI48) +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ +#endif /* RCC_CFGR_SWS_HSI48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#if defined(RCC_CFGR_MCOSEL_HSI48) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ +#endif /* RCC_CFGR_MCOSEL_HSI48 */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_PLLNODIV) +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ +#endif /* RCC_CFGR_PLLNODIV */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ +#if defined(RCC_CFGR_MCOPRE) +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ +#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ +#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ +#endif /* RCC_CFGR_MCOPRE */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ +/** + * @} + */ + +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_CFGR3_USBSW_HSI48) +#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ +#endif /*RCC_CFGR3_USBSW_HSI48*/ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ +/** + * @} + */ + +#endif /* USB */ + +/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* USB */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_CFGR_SW_HSI48) +#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ +#endif /* RCC_CFGR_SW_HSI48 */ +#else +#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + * , @ref LL_RCC_PLL_GetPrediv()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param __PLLPREDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disable the Clock Security System. + * @note Cannot be disabled in HSE is ready (only by hardware) + * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); +} + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_HSI14 HSI14 + * @{ + */ + +/** + * @brief Enable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Enable(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Disable HSI14 + * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_Disable(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); +} + +/** + * @brief Check if HSI14 oscillator Ready + * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) +{ + return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); +} + +/** + * @brief ADC interface can turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) +{ + CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief ADC interface can not turn on the HSI14 oscillator + * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) +{ + SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); +} + +/** + * @brief Set HSI14 Calibration trimming + * @note user-programmable trimming value that is added to the HSI14CAL + * @note Default value is 16, which, when added to the HSI14CAL value, + * should trim the HSI14 to 14 MHz +/- 1 % + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration value + * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of + * HSI14TRIM and the factory trim value + * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); +} + +/** + * @brief Get HSI14 Calibration trimming + * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO\n + * CFGR PLLNODIV LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_HSI14 + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * + * (*) value not defined in all devices + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 (*) + * @arg @ref LL_RCC_MCO1_DIV_4 (*) + * @arg @ref LL_RCC_MCO1_DIV_8 (*) + * @arg @ref LL_RCC_MCO1_DIV_16 (*) + * @arg @ref LL_RCC_MCO1_DIV_32 (*) + * @arg @ref LL_RCC_MCO1_DIV_64 (*) + * @arg @ref LL_RCC_MCO1_DIV_128 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ +#if defined(RCC_CFGR_MCOPRE) +#if defined(RCC_CFGR_PLLNODIV) + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +#endif /* RCC_CFGR_PLLNODIV */ +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +#endif /* RCC_CFGR_MCOPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); +} + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); +} +#endif /* USB */ + +/** + * @brief Get USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); +} + +#if defined(CEC) +/** + * @brief Get CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); +} +#endif /* USB */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); +} + +#else + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); +} +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get PREDIV division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear HSI14 ready interrupt flag + * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if HSI14 ready interrupt occurred or not + * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_V18PWRRSTF) +/** + * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. + * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); +} +#endif /* RCC_CSR_V18PWRRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Enable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable HSI14 ready interrupt + * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @brief Checks if HSI14 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h new file mode 100644 index 0000000..65af161 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h @@ -0,0 +1,1868 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_SYSTEM_H +#define __STM32F0xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation + * @{ + */ +#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */ +#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap + * @{ + */ +#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) +#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */ +#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */ +#endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) +#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */ +#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */ +#endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART2_DMA_RMP) +#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */ +#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_USART3_DMA_RMP) +#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap + * @{ + */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */ +#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ + +#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap + * @{ + */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */ +#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */ +/** + * @} + */ + +#endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap + * @{ + */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */ +#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap + * @{ + */ +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */ +#else +#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ +#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ +#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) +#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */ +#else +#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ +#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ +#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ +#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) +#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */ +#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) +#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */ +#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ +#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) +#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */ +#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */ +#endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */ +#endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#if defined(GPIOE_BASE) +#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ +#endif /*GPIOE_BASE*/ +#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CFGR2_PVD_LOCK) +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection + with TIM1/15/16U/17 Break Input and also + the PVDE and PLS bits of the Power Control Interface */ +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal + with Break Input of TIM1/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of + CortexM0 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ +#endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ +#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +#if defined(SYSCFG_CFGR1_IR_MOD) +/** + * @brief Set IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); +} + +/** + * @brief Get IR Modulation Envelope signal source. + * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IR_MOD_TIM16 + * @arg @ref LL_SYSCFG_IR_MOD_USART1 + * @arg @ref LL_SYSCFG_IR_MOD_USART4 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); +} +#endif /* SYSCFG_CFGR1_IR_MOD */ + +#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for USART + * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n + * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) + * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) + * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) + * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) + * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) +/** + * @brief Set DMA request remapping bits for SPI + * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 + * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) +/** + * @brief Set DMA request remapping bits for I2C + * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 + * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) +/** + * @brief Set DMA request remapping bits for ADC + * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 + * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); +} +#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) +/** + * @brief Set DMA request remapping bits for TIM + * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) + * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) + * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); +} +#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** + * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} + +/** + * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either + * PA9/10 or PA11/12 pin pair on small pin-count packages) + * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); +} +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16)); +} + +#if defined(SYSCFG_ITLINE0_SR_EWDG) +/** + * @brief Check if Window watchdog interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); +} +#endif /* SYSCFG_ITLINE0_SR_EWDG */ + +#if defined(SYSCFG_ITLINE1_SR_PVDOUT) +/** + * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). + * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); +} +#endif /* SYSCFG_ITLINE1_SR_PVDOUT */ + +#if defined(SYSCFG_ITLINE1_SR_VDDIO2) +/** + * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). + * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); +} +#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) +/** + * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) +/** + * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ + +#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) +/** + * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). + * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA)); +} +#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ + +#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) +/** + * @brief Check if Flash interface interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)); +} +#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ + +#if defined(SYSCFG_ITLINE4_SR_CRS) +/** + * @brief Check if Clock recovery system interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); +} +#endif /* SYSCFG_ITLINE4_SR_CRS */ + +#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) +/** + * @brief Check if Reset and clock control interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)); +} +#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI0) +/** + * @brief Check if EXTI line 0 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ + +#if defined(SYSCFG_ITLINE5_SR_EXTI1) +/** + * @brief Check if EXTI line 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); +} +#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI2) +/** + * @brief Check if EXTI line 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ + +#if defined(SYSCFG_ITLINE6_SR_EXTI3) +/** + * @brief Check if EXTI line 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); +} +#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI4) +/** + * @brief Check if EXTI line 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI5) +/** + * @brief Check if EXTI line 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI6) +/** + * @brief Check if EXTI line 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI7) +/** + * @brief Check if EXTI line 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI8) +/** + * @brief Check if EXTI line 8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI9) +/** + * @brief Check if EXTI line 9 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI10) +/** + * @brief Check if EXTI line 10 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI11) +/** + * @brief Check if EXTI line 11 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI12) +/** + * @brief Check if EXTI line 12 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI13) +/** + * @brief Check if EXTI line 13 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI14) +/** + * @brief Check if EXTI line 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ + +#if defined(SYSCFG_ITLINE7_SR_EXTI15) +/** + * @brief Check if EXTI line 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); +} +#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_EOA) +/** + * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ + +#if defined(SYSCFG_ITLINE8_SR_TSC_MCE) +/** + * @brief Check if Touch sensing controller max counterror interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE)); +} +#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ + +#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) +/** + * @brief Check if DMA1 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)); +} +#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) +/** + * @brief Check if DMA1 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) +/** + * @brief Check if DMA1 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) +/** + * @brief Check if DMA2 channel 1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ + +#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) +/** + * @brief Check if DMA2 channel 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2)); +} +#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) +/** + * @brief Check if DMA1 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) +/** + * @brief Check if DMA1 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) +/** + * @brief Check if DMA1 channel 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) +/** + * @brief Check if DMA1 channel 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) +/** + * @brief Check if DMA2 channel 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) +/** + * @brief Check if DMA2 channel 4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ + +#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) +/** + * @brief Check if DMA2 channel 5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)); +} +#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ + +#if defined(SYSCFG_ITLINE12_SR_ADC) +/** + * @brief Check if ADC interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); +} +#endif /* SYSCFG_ITLINE12_SR_ADC */ + +#if defined(SYSCFG_ITLINE12_SR_COMP1) +/** + * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). + * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP1 */ + +#if defined(SYSCFG_ITLINE12_SR_COMP2) +/** + * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). + * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)); +} +#endif /* SYSCFG_ITLINE12_SR_COMP2 */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) +/** + * @brief Check if Timer 1 break interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) +/** + * @brief Check if Timer 1 update interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) +/** + * @brief Check if Timer 1 trigger interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ + +#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) +/** + * @brief Check if Timer 1 commutation interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)); +} +#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ + +#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) +/** + * @brief Check if Timer 1 capture compare interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)); +} +#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ + +#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) +/** + * @brief Check if Timer 2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)); +} +#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ + +#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) +/** + * @brief Check if Timer 3 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)); +} +#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ + +#if defined(SYSCFG_ITLINE17_SR_DAC) +/** + * @brief Check if DAC underrun interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); +} +#endif /* SYSCFG_ITLINE17_SR_DAC */ + +#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) +/** + * @brief Check if Timer 6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)); +} +#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ + +#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) +/** + * @brief Check if Timer 7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)); +} +#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ + +#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) +/** + * @brief Check if Timer 14 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)); +} +#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ + +#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) +/** + * @brief Check if Timer 15 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)); +} +#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ + +#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) +/** + * @brief Check if Timer 16 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)); +} +#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ + +#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) +/** + * @brief Check if Timer 17 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)); +} +#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ + +#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) +/** + * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. + * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)); +} +#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ + +#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) +/** + * @brief Check if I2C2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)); +} +#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ + +#if defined(SYSCFG_ITLINE25_SR_SPI1) +/** + * @brief Check if SPI1 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); +} +#endif /* SYSCFG_ITLINE25_SR_SPI1 */ + +#if defined(SYSCFG_ITLINE26_SR_SPI2) +/** + * @brief Check if SPI2 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); +} +#endif /* SYSCFG_ITLINE26_SR_SPI2 */ + +#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) +/** + * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. + * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)); +} +#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ + +#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) +/** + * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. + * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)); +} +#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) +/** + * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. + * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) +/** + * @brief Check if USART4 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART5_GLB) +/** + * @brief Check if USART5 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART6_GLB) +/** + * @brief Check if USART6 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART7_GLB) +/** + * @brief Check if USART7 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ + +#if defined(SYSCFG_ITLINE29_SR_USART8_GLB) +/** + * @brief Check if USART8 interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB)); +} +#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ + +#if defined(SYSCFG_ITLINE30_SR_CAN) +/** + * @brief Check if CAN interrupt occurred or not. + * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); +} +#endif /* SYSCFG_ITLINE30_SR_CAN */ + +#if defined(SYSCFG_ITLINE30_SR_CEC) +/** + * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. + * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) +{ + return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); +} +#endif /* SYSCFG_ITLINE30_SR_CEC */ + +/** + * @brief Set connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); +#else + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Get connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(SYSCFG_CFGR2_PVD_LOCK) + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, + SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)); +#endif /*SYSCFG_CFGR2_PVD_LOCK*/ +} + +/** + * @brief Check if SRAM parity error detected + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); +} + +/** + * @brief Clear SRAM parity error flag + * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F03x devices, the device ID is 0x444 + * @note For STM32F04x devices, the device ID is 0x445. + * @note For STM32F05x devices, the device ID is 0x440 + * @note For STM32F07x devices, the device ID is 0x448 + * @note For STM32F09x devices, the device ID is 0x442 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as 0x1000 for Revision 1.0. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h new file mode 100644 index 0000000..ca5ed3e --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h @@ -0,0 +1,287 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_LL_UTILS_H +#define __STM32F0xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#else + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#if defined(RCC_CFGR_SW_HSI48) +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#endif /*RCC_CFGR_SW_HSI48*/ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c new file mode 100644 index 0000000..56e21e8 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c @@ -0,0 +1,467 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) HAL Initialization and de-initialization functions + (+) HAL Control functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F0xx HAL Driver version number V1.7.1 + */ +#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F0xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK (0x00000FFFU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +__IO uint32_t uwTick; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on HSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick++; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(__IO uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait++; + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c new file mode 100644 index 0000000..fba72d3 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32f0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0 based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK) functionalities. + + +@endverbatim + * @{ + */ + + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c new file mode 100644 index 0000000..9bd69a0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c @@ -0,0 +1,905 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialize DmaBaseAddress and ChannelIndex parameters used + by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +/* Get DMA Base Address */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete, & transfer error interrupts */ + /* Half transfer interrupt is optional: enable it only if associated callback is available */ + if(NULL != hdma->XferHalfCpltCallback ) + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + } + else + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Abort the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + { + if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + + /* DMA peripheral state is not updated in Half Transfer */ + /* State is updated only in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete & transfer error interrupts */ + /* if the DMA mode is not CIRCULAR */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management ***************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Then, disable all DMA interrupts */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameters. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief set the DMA base address and channel index depending on DMA instance + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c new file mode 100644 index 0000000..514fafe --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c @@ -0,0 +1,710 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F0xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programmation (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0U; + uint8_t nbiterations = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + /* In case of error, stop programation procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + flags |= FLASH_FLAG_PGERR; + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c new file mode 100644 index 0000000..bb6143d --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c @@ -0,0 +1,1000 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F0xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT 8U +#define FLASH_POSITION_OB_USERDATA0_BIT 16U +#define FLASH_POSITION_OB_USERDATA1_BIT 24U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(void); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0U; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); +#if defined(FLASH_OBR_BOOT_SEL) + assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); + assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); +#endif /* FLASH_OBR_BOOT_SEL */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_OBR_BOOT_SEL) + OB->USER = UserConfig; +#else + OB->USER = (UserConfig | 0x88U); +#endif + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t tmp_reg; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); + + if (tmp_reg == 0U) + { + return OB_RDP_LEVEL_0; + } + else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2) + { + return OB_RDP_LEVEL_2; + } + else + { + return OB_RDP_LEVEL_1; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c new file mode 100644 index 0000000..2890fcc --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c @@ -0,0 +1,543 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also + recommended to use it to unconfigure pin which was used as an external interrupt + or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG + registers. + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) + +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != RESET) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + + if(iocurrent) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U)); + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + SET_BIT(temp, GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(temp, iocurrent); + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(temp, iocurrent); + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->FTSR = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != RESET) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1U << position); + + if (iocurrent) + { + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + + /* Configure the default value for IO Speed */ + CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U)); + + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= ((0x0FU) << (4U * (position & 0x03U))); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + tmp = (0x0FU) << (4U * (position & 0x03U)); + CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; + } + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bits to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c new file mode 100644 index 0000000..c64e0f0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c @@ -0,0 +1,4868 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) + +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ + ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ + ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private functions to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private functions to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; + } + + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + __IO uint32_t I2C_Trials = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials++ == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If size > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Call the Error Callback in case of Error detected */ + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, hi2c->ErrorCode); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + { + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + } + + /* Check if STOPF is set */ + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress = 0U; + uint32_t xfermode = 0U; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection = 0U; + uint16_t slaveaddrcode = 0U; + uint16_t ownadd1code = 0U; + uint16_t ownadd2code = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if ((ITFlags & I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + { + hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Store Last receive data if any */ + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Rx Complete callback */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Tx Complete callback */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Get the CR2 register value */ + tmpreg = hi2c->Instance->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + + /* update CR2 register */ + hi2c->Instance->CR2 = tmpreg; +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c new file mode 100644 index 0000000..6c24c54 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c @@ -0,0 +1,347 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F0xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#if defined(I2C_CR1_WUPEN) + +/** + * @brief Enable I2C wakeup from stop mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from stop mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c new file mode 100644 index 0000000..a802483 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c @@ -0,0 +1,1404 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE); + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable HCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PCD_Private_Define PCD Private Define + * @{ + */ +#define BTABLE_ADDRESS (0x000) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and create the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + uint32_t i = 0U; + + uint32_t wInterrupt_Mask = 0U; + + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + /* Control until ep is actvated */ + hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + /*CNTR_FRES = 1*/ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /*CNTR_FRES = 0*/ + hpcd->Instance->CNTR = 0; + + /*Clear pending interrupts*/ + hpcd->Instance->ISTR = 0; + + /*Set Btable Adress*/ + hpcd->Instance->BTABLE = BTABLE_ADDRESS; + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + hpcd->USB_Address = 0U; + hpcd->State= HAL_PCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + HAL_PCD_Stop(hpcd); + + /* DeInit the low level hardware */ + HAL_PCD_MspDeInit(hpcd); + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* disable all interrupts and force USB reset */ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /* clear interrupt status register */ + hpcd->Instance->ISTR = 0; + + /* switch-off device */ + hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wInterrupt_Mask = 0U; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + HAL_PCD_ResetCallback(hpcd); + HAL_PCD_SetAddress(hpcd, 0U); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + { + + hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE)); + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + HAL_PCD_ResumeCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) + { + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + { + HAL_PCD_SuspendCallback(hpcd); + } + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + HAL_PCD_SOFCallback(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} + +/** + * @brief Data out stage callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callbacks + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callbacks + * @param hpcd PCD handle + * @retval None + */ + __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Disable DP Pull-Down bit*/ + hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + + if(address == 0U) + { + /* set device address and enable function */ + hpcd->Instance->DADDR = USB_DADDR_EF; + } + else /* USB Address will be applied later */ + { + hpcd->USB_Address = address; + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packert size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + } + ep->num = ep_addr & 0x7FU; + + ep->is_in = (0x80U & ep_addr) != 0U; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + __HAL_LOCK(hpcd); + + /* initialize Endpoint */ + switch (ep->type) + { + case PCD_EP_TYPE_CTRL: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); + break; + case PCD_EP_TYPE_BULK: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); + break; + case PCD_EP_TYPE_INTR: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); + break; + case PCD_EP_TYPE_ISOC: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); + break; + default: + break; + } + + PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + /* Configure NAK status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket) + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + } + } + /*Double Buffer*/ + else + { + /*Set the endpoint as double buffered*/ + PCD_SET_EP_DBUF(hpcd->Instance, ep->num); + /*Set buffer address for double buffered mode*/ + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1) + + if (ep->is_in==0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + + __HAL_UNLOCK(hpcd); + return ret; +} + + +/** + * @brief Deactivate an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + } + ep->num = ep_addr & 0x7FU; + + ep->is_in = (0x80U & ep_addr) != 0U; + + __HAL_LOCK(hpcd); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + /*Double Buffer*/ + else + { + if (ep->is_in==0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + } + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0x7FU; + + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0U; + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0) + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len) + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len) + } + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + uint16_t pmabuffer = 0U; + + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0x7FU; + + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0U; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); + PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Write the data to the USB endpoint*/ + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) + { + /*Set the Double buffer counter for pmabuffer1*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) + pmabuffer = ep->pmaaddr1; + } + else + { + /*Set the Double buffer counter for pmabuffer0*/ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len) + pmabuffer = ep->pmaaddr0; + } + + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) + } + + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + __HAL_LOCK(hpcd); + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 1; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); + + if (ep->num == 0U) + { + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) + } + else + { + if (ep->is_in) + { + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL) + } + else + { + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL) + } + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 0U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); + + __HAL_LOCK(hpcd); + + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return HAL_OK; +} + +/** + * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling +* @param hpcd PCD handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + if (hpcd->Init.lpm_enable ==1) + { + /* Apply L1 Resume */ + hpcd->Instance->CNTR |= USB_CNTR_L1RESUME; + } + else + { + /* Apply L2 Resume */ + hpcd->Instance->CNTR |= USB_CNTR_RESUME; + } + + return (HAL_OK); +} + +/** +* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling +* @param hpcd PCD handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + if (hpcd->Init.lpm_enable ==1) + { + /* Release L1 Resume */ + hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_L1RESUME)); + } + else + { + /* Release L2 Resume */ + hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_RESUME)) ; + } + + return (HAL_OK); +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD state + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PCD_Private_Functions + * @{ + */ +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; + uint32_t i; + uint16_t temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ; + *pdwVal++ = temp2; + pbUsrBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf = pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1U; + uint32_t i; + uint16_t *pdwVal; + uint32_t temp; + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + + for (i = n; i != 0U; i--) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + *pbUsrBuf++ = ((temp >> 8) & 0xFF); + } + + if (wNBytes % 2) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + } +} + +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count=0U; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0U; + + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0U); + + + if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0U); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket) + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID) + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0U) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT) + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0U) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0U) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0U) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c new file mode 100644 index 0000000..b00d2f8 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief Extended PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Configuration of the PMA for EP + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update PMA configuration + +@endverbatim + * @{ + */ + +/** + * @brief Configure PMA for EP + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * @arg USB_SNG_BUF: Single Buffer used + * @arg USB_DBL_BUF: Double Buffer used + * @param pmaadress EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval : status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) + +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /*Single Buffer*/ + ep->doublebuffer = 0U; + /*Configure the PMA*/ + ep->pmaadress = (uint16_t)pmaadress; + } + else /*USB_DBL_BUF*/ + { + /*Double Buffer Endpoint*/ + ep->doublebuffer = 1U; + /*Configure the PMA*/ + ep->pmaaddr0 = pmaadress & 0xFFFFU; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; + } + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c new file mode 100644 index 0000000..4eef3d0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c @@ -0,0 +1,470 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization function + * + Peripheral Control function + * + @verbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + PWR->CR |= (uint32_t)PWR_CR_DBP; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. + (++)WakeUp Pin 1 on PA.00. + (++)WakeUp Pin 2 on PC.13. + (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) + (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) + (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) + (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + when programmed in wakeup mode (the peripheral must be + programmed in wakeup mode and the corresponding interrupt vector + must be enabled in the NVIC) + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. + The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers and Standby circuitry. + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. +@endverbatim + * @{ + */ + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be value of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be values of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator Specifies the regulator state in SLEEP mode. + * On STM32F0 devices, this parameter is a dummy value and it is ignored + * as regulator can't be modified in this mode. Parameter is kept for platform + * compatibility. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC alternate function pins if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pins if enabled. + * STM32F0x8 devices, the Stop mode is available, but it is + * aningless to distinguish between voltage regulator in Low power + * mode and voltage regulator in Run mode because the regulator + * not used and the core is supplied directly from an external source. + * Consequently, the Standby mode is not available on those devices. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= (uint32_t)PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c new file mode 100644 index 0000000..d83817d --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWREx HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @brief Extended Peripheral Control functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. + (+) The PVD is stopped in Standby mode. + -@- PVD is not available on STM32F030x4/x6/x8 + + *** VDDIO2 Monitor Configuration *** + ==================================== + [..] + (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it + to VREFInt Voltage + (+) This monitor is internally connected to the EXTI line31 + and can generate an interrupt if enabled. This is done through + HAL_PWREx_EnableVddio2Monitor() function. + -@- VDDIO2 is available on STM32F07x/09x/04x + +@endverbatim + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F091xC) || \ + defined (STM32F042x6) || defined (STM32F072xB) +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + PWR->CR |= (uint32_t)PWR_CR_PVDE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_PVDE); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F091xC) || */ + /* defined (STM32F042x6) || defined (STM32F072xB) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. + * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, + an interrupt is generated Irq line 1. + NVIS has to be enable by user. + * @retval None + */ +void HAL_PWREx_EnableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); +} + +/** + * @brief Disable the Vddio2 Monitor. + * @retval None + */ +void HAL_PWREx_DisableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); + +} + +/** + * @brief This function handles the PWR Vddio2 monitor interrupt request. + * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWREx_Vddio2Monitor_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) + { + /* PWR Vddio2 monitor interrupt user callback */ + HAL_PWREx_Vddio2MonitorCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR Vddio2 Monitor interrupt callback + * @retval None + */ +__weak void HAL_PWREx_Vddio2MonitorCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c new file mode 100644 index 0000000..619a481 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c @@ -0,0 +1,1332 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, + AHB and APB1). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + The HSI clock can be used also to clock the USART and I2C peripherals. + + (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock + the ADC peripheral. + + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 48 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the TIM, I2C and USART + peripherals (up to 48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. + + (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + + /* Reset CFGR3 register */ + CLEAR_REG(RCC->CFGR3); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(RCC_HSI48_SUPPORT) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Check the HSI48 State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } +#endif /* RCC_HSI48_SUPPORT */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(RCC_CFGR_SWS_HSI48) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* RCC_CFGR_SWS_HSI48 */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(RCC_CFGR_SWS_HSI48) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* RCC_CFGR_SWS_HSI48 */ + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @retval None + */ +#else +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +#endif +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based + * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the + * PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE / prediv) * pllmul; + } +#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (HSI48_VALUE / prediv) * pllmul; + } +#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ + else + { +#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (HSI_VALUE / prediv) * pllmul; +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul); +#endif + } + sysclockfreq = pllclk; + break; + } +#if defined(RCC_CFGR_SWS_HSI48) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + { + sysclockfreq = HSI48_VALUE; + break; + } +#endif /* RCC_CFGR_SWS_HSI48 */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif /* RCC_HSI48_SUPPORT */ + + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI14 configuration -----------------------------------------------*/ + if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) + { + RCC_OscInitStruct->HSI14State = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration if any-----------------------------------------*/ + RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c new file mode 100644 index 0000000..a5699bf --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c @@ -0,0 +1,980 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(CRS) +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/* Bit position in register */ +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t temp_reg = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART3 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* STM32F091xC || STM32F098xx */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + /* Common part first */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + /* Get the RTC configuration --------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USART1 clock configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + /* Get the USB clock source ---------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + @if STM32F042x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F048xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F051x8 + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F058xx + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F070x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F070xB + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F071xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F072xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F078xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F091xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F098xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* frequency == 0 : means that no available frequency for the peripheral */ + uint32_t frequency = 0U; + + uint32_t srcclk = 0U; +#if defined(USB) + uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; +#endif /* USB */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 32U; + } + break; + } + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + /* Check if USART1 clock selection is PCLK1 */ + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART1 clock selection is HSI */ + else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART1 clock selection is SYSCLK */ + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART1 clock selection is LSE */ + else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#if defined(RCC_CFGR3_USART2SW) + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + /* Check if USART2 clock selection is PCLK1 */ + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART2 clock selection is HSI */ + else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART2 clock selection is SYSCLK */ + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART2 clock selection is LSE */ + else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + case RCC_PERIPHCLK_USART3: + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + /* Check if USART3 clock selection is PCLK1 */ + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART3 clock selection is HSI */ + else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART3 clock selection is SYSCLK */ + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART3 clock selection is LSE */ + else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART3SW */ + case RCC_PERIPHCLK_I2C1: + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Check if HSI is ready and if I2C1 clock selection is HSI */ + if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C1 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#if defined(USB) + case RCC_PERIPHCLK_USB: + { + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + /* Check if PLL is ready and if USB clock selection is PLL */ + if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ + frequency = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(RCC_CR2_HSI48ON) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ + frequency = (HSI48_VALUE / predivfactor) * pllmull; + } +#endif /* RCC_CR2_HSI48ON */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) + /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ + frequency = (HSI_VALUE / predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ + frequency = (HSI_VALUE >> 1U) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ + } + } +#if defined(RCC_CR2_HSI48ON) + /* Check if HSI48 is ready and if USB clock selection is HSI48 */ + else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) + { + frequency = HSI48_VALUE; + } +#endif /* RCC_CR2_HSI48ON */ + break; + } +#endif /* USB */ +#if defined(CEC) + case RCC_PERIPHCLK_CEC: + { + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + /* Check if HSI is ready and if CEC clock selection is HSI */ + if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if LSE is ready and if CEC clock selection is LSE */ + else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* CEC */ + default: + { + break; + } + } + return(frequency); +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function @ref HAL_RCCEx_CRSConfig which + (+++) Reset CRS registers to their default values. + (+++) Configure CRS registers with synchronization configuration + (+++) Enable automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + @ref HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (RCC_IRQn/RCC_IRQHandler) + (++) Call function @ref HAL_RCCEx_CRSConfig() + (++) Enable RCC_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() + (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() + (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the timeout +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart = 0U; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while(RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + { + if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + { + crserror |= RCC_CRS_SYNCERR; + } + if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + { + crserror |= RCC_CRS_SYNCMISS; + } + if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c new file mode 100644 index 0000000..459f362 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c @@ -0,0 +1,5495 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + Time Base Initialization + * + Time Base Start + * + Time Base Start Interruption + * + Time Base Start DMA + * + Time Output Compare/PWM Initialization + * + Time Output Compare/PWM Channel Configuration + * + Time Output Compare/PWM Start + * + Time Output Compare/PWM Start Interruption + * + Time Output Compare/PWM Start DMA + * + Time Input Capture Initialization + * + Time Input Capture Channel Configuration + * + Time Input Capture Start + * + Time Input Capture Start Interruption + * + Time Input Capture Start DMA + * + Time One Pulse Initialization + * + Time One Pulse Channel Configuration + * + Time One Pulse Start + * + Time Encoder Interface Initialization + * + Time Encoder Interface Start + * + Time Encoder Interface Start Interruption + * + Time Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + Time OCRef clear configuration + * + Time External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions + * +@verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions + * +@verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM OPWM. + (+) De-initialize the TIM PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions + * +@verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions + * +@verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions + * +@verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +{ + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Reset the SMS bits */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_ALL: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + HAL_TIM_PeriodElapsedCallback(htim); + } + } + /* TIM Break input event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + HAL_TIMEx_BreakCallback(htim); + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + HAL_TIM_TriggerCallback(htim); + } + } + /* TIM commutation event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + HAL_TIMEx_CommutationCallback(htim); + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + __HAL_LOCK(htim); + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if(OutputChannel != InputChannel) + { + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; + } + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0U ) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); + } + break; + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0U ) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); + } + break; + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + uint32_t tmpsmcr = 0U; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Reset the SMS and TS Bits */ + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + } + break; + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + } + break; + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + } + break; + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + } + break; + case TIM_CLOCKSOURCE_ITR0: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); + } + break; + case TIM_CLOCKSOURCE_ITR1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); + } + break; + case TIM_CLOCKSOURCE_ITR2: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); + } + break; + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) + { + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1 : TIM Channel 1 selected + * @arg TIM_CHANNEL_2 : TIM Channel 2 selected + * @arg TIM_CHANNEL_3 : TIM Channel 3 selected + * @arg TIM_CHANNEL_4 : TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) Timer Period elapsed callback + (+) Timer Output Compare callback + (+) Timer Input capture callback + (+) Timer Trigger callback + (+) Timer Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ + +} +/** + * @brief Output Compare callback in non blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} +/** + * @brief Input Capture callback in non blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base state + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC state + * @param htim TIM Ouput Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM state + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture state + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode state + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode state + * @param htim TIM Encoder handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_ErrorCallback(htim); +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_PWM_PulseFinishedCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_IC_CaptureCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_PeriodElapsedCallback(htim); +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_TriggerCallback(htim); +} + +/** + * @brief Time Base configuration + * @param TIMx TIM periheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1 = 0U; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = (uint32_t)Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0 : Internal Trigger 0 + * @arg TIM_TS_ITR1 : Internal Trigger 1 + * @arg TIM_TS_ITR2 : Internal Trigger 2 + * @arg TIM_TS_ITR3 : Internal Trigger 3 + * @arg TIM_TS_TI1F_ED : TI1 Edge Detector + * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 + * @arg TIM_TS_ETRF : External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +{ + uint32_t tmpsmcr = 0U; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0U; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1 : TIM Channel 1 + * @arg TIM_CHANNEL_2 : TIM Channel 2 + * @arg TIM_CHANNEL_3 : TIM Channel 3 + * @arg TIM_CHANNEL_4 : TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << Channel); +} + + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c new file mode 100644 index 0000000..9bf2c75 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c @@ -0,0 +1,2012 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal bread and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Complementary Output Compare : HAL_TIM_OC_MspInit() + (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() + (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: +{ + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0U ) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complemetary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) + { + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; + } + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ +/** + * @brief Configure the TIM commutation event sequence. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation Interrupt Request */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the MMS Bits */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + htim->Instance->SMCR &= ~TIM_SMCR_MSM; + /* Set or Reset the MSM Bit */ + htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM14 Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock + * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @retval None + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + uint32_t tmpsmcr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions + * @brief Extension Callbacks functions + * +@verbatim + ============================================================================== + ##### Extension Callbacks functions ##### + ============================================================================== + [..] + This section provides Extension TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_CommutationCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIMEx_CommutationCallback(htim); +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions + * @brief Extension Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extension Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface state + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIMEx_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp = 0U; + + tmp = TIM_CCER_CC1NE << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << Channel); +} + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c new file mode 100644 index 0000000..d9e4253 --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c @@ -0,0 +1,238 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ +#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) + LL_EXTI_WriteReg(IMR, 0x0FF40000U); +#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) + LL_EXTI_WriteReg(IMR, 0x7FF40000U); +#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + LL_EXTI_WriteReg(IMR, 0x0F940000U); +#else + LL_EXTI_WriteReg(IMR, 0x7F840000U); +#endif + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register clear */ + LL_EXTI_WriteReg(PR, 0x007BFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c new file mode 100644 index 0000000..3fae50c --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_gpio.h" +#include "stm32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + } +#endif /* GPIOF */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos = 0x00000000U; + uint32_t currentpin = 0x00000000U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + /* pinpos = 0; useless as already done in default initialization */ + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + + if (currentpin) + { + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + } + pinpos++; + } + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c new file mode 100644 index 0000000..6a244fd --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) +#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) + +#if defined(USB) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB */ + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + uint32_t vl_mask = 0U; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x10U); + + /* Reset SW, HPRE, PPRE and MCOSEL bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); + LL_RCC_WriteReg(CFGR, vl_mask); + + /* Reset HSEON, CSSON, PLLON bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); + LL_RCC_WriteReg(CR, vl_mask); + + /* Reset HSEBYP bit */ + LL_RCC_HSE_DisableBypass(); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + +#if defined(RCC_HSI48_SUPPORT) + /* Reset CR2 register */ + LL_RCC_WriteReg(CR2, 0x00000000U); + + /* Disable HSI48 */ + LL_RCC_HSI48_Disable(); + +#endif /*RCC_HSI48_SUPPORT*/ + /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ + LL_RCC_HSI14_SetCalibTrimming(0x10U); + LL_RCC_HSI14_Disable(); + LL_RCC_HSI14_EnableADCControl(); + + /* Reset CFGR2 register */ + LL_RCC_WriteReg(CFGR2, 0x00000000U); + + /* Reset CFGR3 register */ + LL_RCC_WriteReg(CFGR3, 0x00000000U); + + /* Clear pending flags */ +#if defined(RCC_HSI48_SUPPORT) + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); +#else + vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); +#endif /* RCC_HSI48_SUPPORT */ + SET_BIT(RCC->CIR, vl_mask); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIR, 0x00000000U); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a defined constant but the real value may vary + * depending on the variations in voltage and temperature. + * @note (***) HSE_VALUE is a defined constant, user has to ensure that + * HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval USART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); +#if defined(RCC_CFGR3_USART1SW) + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART1SW */ + +#if defined(RCC_CFGR3_USART2SW) + if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) + if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady()) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady()) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + +#endif /* RCC_CFGR3_USART3SW */ + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + /* I2C1 CLK clock frequency */ + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady()) + { + i2c_frequency = HSI_VALUE; + } + break; + } + } + + return i2c_frequency; +} + +#if defined(USB) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + +#if defined(RCC_CFGR3_USBSW_HSI48) + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + default: + if (LL_RCC_HSI48_IsReady()) + { + usb_frequency = HSI48_VALUE; + } + break; +#else + case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ + default: + usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; +#endif /* RCC_CFGR3_USBSW_HSI48 */ + } + + return usb_frequency; +} +#endif /* USB */ + +#if defined(CEC) +/** + * @brief Return CECx clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ + if (LL_RCC_HSI_IsReady()) + { + cec_frequency = HSI_VALUE / 244U; + } + break; + + case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ + default: + if (LL_RCC_LSE_IsReady()) + { + cec_frequency = LSE_VALUE; + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + frequency = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; +#else + case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ + pllinputfreq = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllinputfreq = HSI_VALUE; +#else + pllinputfreq = HSI_VALUE / 2U; +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + break; + } +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); +#else + return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c new file mode 100644 index 0000000..836204a --- /dev/null +++ b/hardware/esl_blaster/FW02/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c @@ -0,0 +1,620 @@ +/** + ****************************************************************************** + * @file stm32f0xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_system.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F0xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ + +/* Defines used for PLL range */ +#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to SYSCLK Frequency */ +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_16)) + +#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)) + + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. + @endverbatim + @internal + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + (++) +-----------------------------------------------+ + (++) | Latency | SYSCLK clock frequency (MHz) | + (++) |---------------|-------------------------------| + (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + (++) |---------------|-------------------------------| + (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + (++) +-----------------------------------------------+ + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + * - PREDIV: Set to 2 for few devices + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + /* Force PREDIV value to 2 */ + UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#if defined(RCC_CFGR_SW_HSI48) +/** + * @brief This function configures system clock with HSI48 as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI48 if not enabled */ + if (LL_RCC_HSI48_IsReady() != 1U) + { + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1U) + { + /* Wait for HSI48 ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +#endif /*RCC_CFGR_SW_HSI48*/ +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * be in the range 16-48MHz + * @note FLASH latency can be modified through this function. + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check PREDIV value */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency SYSCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + { + status = ERROR; + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} +#endif /* FLASH_ACR_LATENCY */ + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + + /* Check different PLL parameters according to RM */ + /* The application software must set correctly the PLL multiplication factor to + be in the range 16-48MHz */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t sysclk_frequency_current = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + + /* Calculate current SYSCLK frequency */ + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (sysclk_frequency_current < SYSCLK_Frequency) + { + /* Set FLASH latency to highest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (sysclk_frequency_current > SYSCLK_Frequency) + { + /* Set FLASH latency to lowest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/gpio.h b/hardware/esl_blaster/FW02/Inc/gpio.h new file mode 100644 index 0000000..a5a8577 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/gpio.h @@ -0,0 +1,57 @@ +/** + ****************************************************************************** + * File Name : gpio.h + * Description : This file contains all the functions prototypes for + * the gpio + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __gpio_H +#define __gpio_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ pinoutConfig_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/main.h b/hardware/esl_blaster/FW02/Inc/main.h new file mode 100644 index 0000000..f30c871 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/main.h @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#ifndef __MAIN_H +#define __MAIN_H + +#include "stm32f0xx_hal.h" +#include "stm32f0xx_ll_crs.h" +#include "stm32f0xx_ll_rcc.h" +#include "stm32f0xx_ll_bus.h" +#include "stm32f0xx_ll_system.h" +#include "stm32f0xx_ll_exti.h" +#include "stm32f0xx_ll_cortex.h" +#include "stm32f0xx_ll_utils.h" +#include "stm32f0xx_ll_pwr.h" +#include "stm32f0xx_ll_dma.h" +#include "stm32f0xx_ll_gpio.h" + +#define FIFO_SIZE 256 // Must be 2^N + +#define FIFO_INCR(x) (((x)+1)&((FIFO_SIZE)-1)) + +typedef struct FIFO { + uint32_t head; + uint32_t tail; + uint8_t data[FIFO_SIZE]; +} FIFO; + +extern volatile FIFO RX_FIFO; + +void Error_Handler(void); + +#endif diff --git a/hardware/esl_blaster/FW02/Inc/stm32_assert.h b/hardware/esl_blaster/FW02/Inc/stm32_assert.h new file mode 100644 index 0000000..47016da --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/stm32f0xx_hal_conf.h b/hardware/esl_blaster/FW02/Inc/stm32f0xx_hal_conf.h new file mode 100644 index 0000000..e53753b --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/stm32f0xx_hal_conf.h @@ -0,0 +1,323 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CONF_H +#define __STM32F0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)4000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator for ADC (HSI14) value. + */ +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSI) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f0xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/stm32f0xx_it.h b/hardware/esl_blaster/FW02/Inc/stm32f0xx_it.h new file mode 100644 index 0000000..38076f1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/stm32f0xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_IT_H +#define __STM32F0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USB_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/usb_device.h b/hardware/esl_blaster/FW02/Inc/usb_device.h new file mode 100644 index 0000000..f255f88 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/usb_device.h @@ -0,0 +1,105 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.h + * @version : v2.0_Cube + * @brief : Header for usb_device.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEVICE__H__ +#define __USB_DEVICE__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_DEVICE USBD_DEVICE + * @brief Device file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables + * @brief Public variables. + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ +/** + * @} + */ + +/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/** USB Device initialization function. */ +void MX_USB_DEVICE_Init(void); + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEVICE__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/usbd_cdc_if.h b/hardware/esl_blaster/FW02/Inc/usbd_cdc_if.h new file mode 100644 index 0000000..0a9b7c1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/usbd_cdc_if.h @@ -0,0 +1,130 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_cdc_if.h + * @version : v2.0_Cube + * @brief : Header for usbd_cdc_if.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_H__ +#define __USBD_CDC_IF_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief For Usb device. + * @{ + */ + +/** @defgroup USBD_CDC_IF USBD_CDC_IF + * @brief Usb VCP device module + * @{ + */ + +/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines + * @brief Defines. + * @{ + */ +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** CDC Interface callback. */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CDC_IF_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/usbd_conf.h b/hardware/esl_blaster/FW02/Inc/usbd_conf.h new file mode 100644 index 0000000..0e2b921 --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/usbd_conf.h @@ -0,0 +1,175 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.h + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "main.h" +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_CONF USBD_CONF + * @brief Configuration file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines + * @brief Defines for configuration of the Usb device. + * @{ + */ + +/*---------- -----------*/ +#define USBD_MAX_NUM_INTERFACES 1 +/*---------- -----------*/ +#define USBD_MAX_NUM_CONFIGURATION 1 +/*---------- -----------*/ +#define USBD_MAX_STR_DESC_SIZ 512 +/*---------- -----------*/ +#define USBD_SUPPORT_USER_STRING 0 +/*---------- -----------*/ +#define USBD_DEBUG_LEVEL 0 +/*---------- -----------*/ +#define USBD_SELF_POWERED 1 +/*---------- -----------*/ +#define MAX_STATIC_ALLOC_SIZE 512 + +/****************************************/ +/* #define for FS and HS identification */ +#define DEVICE_FS 0 + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* Memory management macros */ + +/** Alias for memory allocation. */ +#define USBD_malloc (uint32_t *)USBD_static_malloc + +/** Alias for memory release. */ +#define USBD_free USBD_static_free + +/** Alias for memory set. */ +#define USBD_memset /* Not used */ + +/** Alias for memory copy. */ +#define USBD_memcpy /* Not used */ + +/** Alias for delay. */ +#define USBD_Delay HAL_Delay + +/* DEBUG macros */ + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types + * @brief Types. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ +void *USBD_static_malloc(uint32_t size); +void USBD_static_free(void *p); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CONF__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Inc/usbd_desc.h b/hardware/esl_blaster/FW02/Inc/usbd_desc.h new file mode 100644 index 0000000..c1ca14e --- /dev/null +++ b/hardware/esl_blaster/FW02/Inc/usbd_desc.h @@ -0,0 +1,51 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC__C__ +#define __USBD_DESC__C__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants + * @brief Constants. + * @{ + */ +#define DEVICE_ID1 (UID_BASE) +#define DEVICE_ID2 (UID_BASE + 0x4) +#define DEVICE_ID3 (UID_BASE + 0x8) + +#define USB_SIZ_STRING_SERIAL 0x1A // 10 Unicode chars + +/** Descriptor for the Usb device. */ +extern USBD_DescriptorsTypeDef FS_Desc; + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DESC__C__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h new file mode 100644 index 0000000..d937b2e --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file usbd_cdc.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief header file for the usbd_cdc.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for usbd_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#define CDC_IN_EP 0x81 /* EP1 for data IN */ +#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ +#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ + +#define USB_CDC_CONFIG_DESC_SIZ 67 +#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE +#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE + +#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE +#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ +typedef struct +{ + uint32_t bitrate; + uint8_t format; + uint8_t paritytype; + uint8_t datatype; +}USBD_CDC_LineCodingTypeDef; + +typedef struct _USBD_CDC_Itf +{ + int8_t (* Init) (void); + int8_t (* DeInit) (void); + int8_t (* Control) (uint8_t, uint8_t * , uint16_t); + int8_t (* Receive) (uint8_t *, uint32_t *); + +}USBD_CDC_ItfTypeDef; + + +typedef struct +{ + uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; +} +USBD_CDC_HandleTypeDef; + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); + +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length); + +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff); + +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c new file mode 100644 index 0000000..b2ca5f1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -0,0 +1,925 @@ +/** + ****************************************************************************** + * @file usbd_cdc.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" +#include "usbd_desc.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ + + +/* CDC interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_GetHSCfgDesc, + USBD_CDC_GetFSCfgDesc, + USBD_CDC_GetOtherSpeedCfgDesc, + USBD_CDC_GetDeviceQualifierDescriptor, +}; + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_Init + * Initialize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + USBD_CDC_HandleTypeDef *hcdc; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); + + } + else + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + /* Open Command IN EP */ + USBD_LL_OpenEP(pdev, + CDC_CMD_EP, + USBD_EP_TYPE_INTR, + CDC_CMD_PACKET_SIZE); + + + pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); + + if(pdev->pClassData == NULL) + { + ret = 1; + } + else + { + hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init Xfer states */ + hcdc->TxState =0; + hcdc->RxState =0; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + + + } + return ret; +} + +/** + * @brief USBD_CDC_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + + /* Open EP IN */ + USBD_LL_CloseEP(pdev, + CDC_IN_EP); + + /* Open EP OUT */ + USBD_LL_CloseEP(pdev, + CDC_OUT_EP); + + /* Open Command IN EP */ + USBD_LL_CloseEP(pdev, + CDC_CMD_EP); + + + /* DeInit physical Interface components */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return ret; +} + +/** + * @brief USBD_CDC_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + static uint8_t ifalt = 0; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength) + { + if (req->bmRequest & 0x80) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + USBD_CtlSendData (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = req->wLength; + + USBD_CtlPrepareRx (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t*)req, + 0); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_INTERFACE : + USBD_CtlSendData (pdev, + &ifalt, + 1); + break; + + case USB_REQ_SET_INTERFACE : + break; + } + + default: + break; + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if(pdev->pClassData != NULL) + { + + hcdc->TxState = 0; + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + + + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + (uint8_t *)hcdc->data, + hcdc->CmdLength); + hcdc->CmdOpCode = 0xFF; + + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; +} + +/** + * @brief USBD_CDC_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; +} + +/** + * @brief USBD_CDC_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; +} + +/** +* @brief DeviceQualifierDescriptor +* return Device Qualifier descriptor +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) +{ + *length = sizeof (USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; +} + +/** +* @brief USBD_CDC_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + uint8_t ret = USBD_FAIL; + + if(fops != NULL) + { + pdev->pUserData= fops; + ret = USBD_OK; + } + + return ret; +} + +/** + * @brief USBD_CDC_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return USBD_OK; +} + + +/** + * @brief USBD_CDC_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return USBD_OK; +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if(pdev->pClassData != NULL) + { + if(hcdc->TxState == 0) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1; + + /* Transmit next packet */ + USBD_LL_Transmit(pdev, + CDC_IN_EP, + hcdc->TxBuffer, + hcdc->TxLength); + + return USBD_OK; + } + else + { + return USBD_BUSY; + } + } + else + { + return USBD_FAIL; + } +} + + +/** + * @brief USBD_CDC_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + /* Suspend or Resume USB Out process */ + if(pdev->pClassData != NULL) + { + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h new file mode 100644 index 0000000..013a5c1 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for usbd_core.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "usbd_def.h" +#include "usbd_ioreq.h" +#include "usbd_ctlreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +#define USBD_SOF USBD_LL_SOF +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); + +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); + +/* USBD Low Level Driver */ +USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); +USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +void USBD_LL_Delay (uint32_t Delay); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h new file mode 100644 index 0000000..bf88252 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -0,0 +1,113 @@ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_REQUEST_H +#define __USB_REQUEST_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_req.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + + +void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + +void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); + +void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_REQUEST_H */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h new file mode 100644 index 0000000..8fbe81e --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -0,0 +1,330 @@ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief General defines for the usb device library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0 +#endif + + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_OTG_DESC 0x03 +#define USB_LEN_LANGID_STR_DESC 0x04 +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 +#define USB_DESC_TYPE_BOS 0x0F + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + +#define USB_DEVICE_CAPABITY_TYPE 0x10 + +#define USB_HS_MAX_PACKET_SIZE 512 +#define USB_FS_MAX_PACKET_SIZE 64 +#define USB_MAX_EP0_SIZE 64 + +/* Device Status */ +#define USBD_STATE_DEFAULT 1 +#define USBD_STATE_ADDRESSED 2 +#define USBD_STATE_CONFIGURED 3 +#define USBD_STATE_SUSPENDED 4 + + +/* EP0 State */ +#define USBD_EP0_IDLE 0 +#define USBD_EP0_SETUP 1 +#define USBD_EP0_DATA_IN 2 +#define USBD_EP0_DATA_OUT 3 +#define USBD_EP0_STATUS_IN 4 +#define USBD_EP0_STATUS_OUT 5 +#define USBD_EP0_STALL 6 + +#define USBD_EP_TYPE_CTRL 0 +#define USBD_EP_TYPE_ISOC 1 +#define USBD_EP_TYPE_BULK 2 +#define USBD_EP_TYPE_INTR 3 + + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ + +typedef struct usb_setup_req +{ + + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +}USBD_SetupReqTypedef; + +struct _USBD_HandleTypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); + uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); + uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); + uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + + uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); +#if (USBD_SUPPORT_USER_STRING == 1) + uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); +#endif + +} USBD_ClassTypeDef; + +/* Following USB Device Speed */ +typedef enum +{ + USBD_SPEED_HIGH = 0, + USBD_SPEED_FULL = 1, + USBD_SPEED_LOW = 2, +}USBD_SpeedTypeDef; + +/* Following USB Device status */ +typedef enum { + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_StatusTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); +#if (USBD_LPM_ENABLED == 1) + uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); +#endif +} USBD_DescriptorsTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; +} USBD_EndpointTypeDef; + +/* USB Device handle structure */ +typedef struct _USBD_HandleTypeDef +{ + uint8_t id; + uint32_t dev_config; + uint32_t dev_default_config; + uint32_t dev_config_status; + USBD_SpeedTypeDef dev_speed; + USBD_EndpointTypeDef ep_in[15]; + USBD_EndpointTypeDef ep_out[15]; + uint32_t ep0_state; + uint32_t ep0_data_len; + uint8_t dev_state; + uint8_t dev_old_state; + uint8_t dev_address; + uint8_t dev_connection_status; + uint8_t dev_test_mode; + uint32_t dev_remote_wakeup; + + USBD_SetupReqTypedef request; + USBD_DescriptorsTypeDef *pDesc; + USBD_ClassTypeDef *pClass; + void *pClassData; + void *pUserData; + void *pData; +} USBD_HandleTypeDef; + +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) +#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN +#else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ +#endif /* __GNUC__ */ + + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h new file mode 100644 index 0000000..b476307 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief Header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_IOREQ_H +#define __USBD_IOREQ_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *buf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); + +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , + uint8_t epnum); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_IOREQ_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c new file mode 100644 index 0000000..9a8aef6 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -0,0 +1,565 @@ +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initializes the device stack and load the class driver +* @param pdev: device instance +* @param pdesc: Descriptor structure address +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + /* Check whether the USB Host handle is valid */ + if(pdev == NULL) + { + USBD_ErrLog("Invalid Device handle"); + return USBD_FAIL; + } + + /* Unlink previous class*/ + if(pdev->pClass != NULL) + { + pdev->pClass = NULL; + } + + /* Assign USBD Descriptors */ + if(pdesc != NULL) + { + pdev->pDesc = pdesc; + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->id = id; + /* Initialize low level driver */ + USBD_LL_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_DeInit +* Re-Initialize th device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) +{ + /* Set Default State */ + pdev->dev_state = USBD_STATE_DEFAULT; + + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + /* Initialize low level driver */ + USBD_LL_DeInit(pdev); + + return USBD_OK; +} + + +/** + * @brief USBD_RegisterClass + * Link class driver to Device Core. + * @param pDevice : Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + USBD_StatusTypeDef status = USBD_OK; + if(pclass != 0) + { + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + status = USBD_OK; + } + else + { + USBD_ErrLog("Invalid Class handle"); + status = USBD_FAIL; + } + + return status; +} + +/** + * @brief USBD_Start + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) +{ + + /* Start the low level driver */ + USBD_LL_Start(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_Stop + * Stop the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + + +/** +* @brief USBD_SetClassConfig +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_FAIL; + + if(pdev->pClass != NULL) + { + /* Set configuration and Start the Class*/ + if(pdev->pClass->Init(pdev, cfgidx) == 0) + { + ret = USBD_OK; + } + } + return ret; +} + +/** +* @brief USBD_ClrClassConfig +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Clear configuration and De-initialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + return USBD_OK; +} + + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + + USBD_ParseSetupRequest(&pdev->request, psetup); + + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data OUT stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_out[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_OUT) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueRx (pdev, + pdata, + MIN(pep->rem_length ,pep->maxpacket)); + } + else + { + if((pdev->pClass->EP0_RxReady != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + } + else if((pdev->pClass->DataOut != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataOut(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_in[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_IN) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueSendData (pdev, + pdata, + pep->rem_length); + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + NULL, + 0); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((pep->total_length % pep->maxpacket == 0) && + (pep->total_length >= pep->maxpacket) && + (pep->total_length < pdev->ep0_data_len )) + { + + USBD_CtlContinueSendData(pdev , NULL, 0); + pdev->ep0_data_len = 0; + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + NULL, + 0); + } + else + { + if((pdev->pClass->EP0_TxSent != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_TxSent(pdev); + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev_test_mode == 1) + { + USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0; + } + } + else if((pdev->pClass->DataIn != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataIn(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, + 0x00, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, + 0x80, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + + if (pdev->pClassData) + pdev->pClass->DeInit(pdev, pdev->dev_config); + + + return USBD_OK; +} + + + + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + return USBD_OK; +} + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + pdev->dev_state = pdev->dev_old_state; + return USBD_OK; +} + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + if(pdev->dev_state == USBD_STATE_CONFIGURED) + { + if(pdev->pClass->SOF != NULL) + { + pdev->pClass->SOF(pdev); + } + } + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->pClass->DeInit(pdev, pdev->dev_config); + + return USBD_OK; +} +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c new file mode 100644 index 0000000..3498604 --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -0,0 +1,596 @@ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ctlreq.h" +#include "usbd_ioreq.h" + +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetAddress(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetStatus(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor (pdev, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (pdev, req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (pdev, req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (pdev, req); + break; + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (pdev, req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (pdev, req); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; + + switch (pdev->dev_state) { + case USBD_STATE_CONFIGURED: + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) { + pdev->pClass->Setup (pdev, req); + + if((req->wLength == 0)&& (ret == USBD_OK)) + USBD_CtlSendStatus(pdev); + } else { + USBD_CtlError(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + + break; + } + return USBD_OK; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) +{ + + uint8_t ep_addr; + USBD_StatusTypeDef ret = USBD_OK; + USBD_EndpointTypeDef *pep; + ep_addr = LOBYTE(req->wIndex); + + /* Check if it is a class request */ + if ((req->bmRequest & 0x60) == 0x20) + { + pdev->pClass->Setup (pdev, req); + + return USBD_OK; + } + + switch (req->bRequest) + { + + case USB_REQ_SET_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + + } + } + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_ClearStallEP(pdev , ep_addr); + pdev->pClass->Setup (pdev, req); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ + &pdev->ep_out[ep_addr & 0x7F]; + if(USBD_LL_IsStallEP(pdev, ep_addr)) + { + pep->status = 0x0001; + } + else + { + pep->status = 0x0000; + } + + USBD_CtlSendData (pdev, + (uint8_t *)&pep->status, + 2); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + default: + break; + } + return ret; +} +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) { + uint16_t len; + uint8_t *pbuf; + + switch (req->wValue >> 8) + { +#if (USBD_LPM_ENABLED == 1) + case USB_DESC_TYPE_BOS: + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + break; + + default: +#if (USBD_SUPPORT_USER_STRING == 1) + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); + break; +#else + USBD_CtlError(pdev , req); + return; +#endif + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + default: + USBD_CtlError(pdev , req); + return; + } + + if((len != 0)&& (req->wLength != 0)) + { + + len = MIN(len , req->wLength); + + USBD_CtlSendData (pdev, + pbuf, + len); + } + +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (pdev->dev_state == USBD_STATE_CONFIGURED) { + USBD_CtlError(pdev , req); + } else { + pdev->dev_address = dev_addr; + USBD_LL_SetUSBAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0) + pdev->dev_state = USBD_STATE_ADDRESSED; + else + pdev->dev_state = USBD_STATE_DEFAULT; + } + } else { + USBD_CtlError(pdev , req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if (cfgidx) + { + pdev->dev_config = cfgidx; + pdev->dev_state = USBD_STATE_CONFIGURED; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + USBD_ClrClassConfig(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + USBD_ClrClassConfig(pdev , pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + if (req->wLength != 1) { + USBD_CtlError(pdev , req); + } else { + switch (pdev->dev_state ) { + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0; + USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_default_config, 1); + break; + + case USBD_STATE_CONFIGURED: + USBD_CtlSendData (pdev, (uint8_t *)&pdev->dev_config, 1); + break; + + default: + USBD_CtlError(pdev , req); + + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + switch (pdev->dev_state) { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + #if ( USBD_SELF_POWERED == 1) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + #else + pdev->dev_config_status = 0; + #endif + + if (pdev->dev_remote_wakeup) + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + + USBD_CtlSendData (pdev, (uint8_t *)& pdev->dev_config_status, 2); + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev_remote_wakeup = 1; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + switch (pdev->dev_state) { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev_remote_wakeup = 0; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { + req->bmRequest = *(uint8_t *) (pdata); + req->bRequest = *(uint8_t *) (pdata + 1); + req->wValue = SWAPBYTE (pdata + 2); + req->wIndex = SWAPBYTE (pdata + 4); + req->wLength = SWAPBYTE (pdata + 6); +} + +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_LL_StallEP(pdev , 0x80); + USBD_LL_StallEP(pdev , 0); +} diff --git a/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c new file mode 100644 index 0000000..093afad --- /dev/null +++ b/hardware/esl_blaster/FW02/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @version V2.4.2 + * @date 11-December-2015 + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + pdev->ep_in[0].total_length = len; + pdev->ep_in[0].rem_length = len; + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Start the next transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + pdev->ep_out[0].total_length = len; + pdev->ep_out[0].rem_length = len; + /* Start the transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + return USBD_OK; +} +/** +* @brief USBD_CtlSendStatus +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) +{ + + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, NULL, 0); + + return USBD_OK; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + + /* Start the transfer */ + USBD_LL_PrepareReceive ( pdev, + 0, + NULL, + 0); + + return USBD_OK; +} + + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval Rx Data blength +*/ +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) +{ + return USBD_LL_GetRxDataSize(pdev, ep_addr); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Release/ESLBlaster02.bin b/hardware/esl_blaster/FW02/Release/ESLBlaster02.bin new file mode 100644 index 0000000000000000000000000000000000000000..d2b99552e203ed78f7e5008f5ec46352228bc428 GIT binary patch literal 13460 zcmbt*4SZD9weLD-W|GV#kVz)U%p`&N2$*D0NdhP!dYFj^GD9?kw1!D~I|)!v2(O)5 z+Z(OD41sDO?JWeXBtc67Ulp-(@upU5o&juoMSJfIkqV^VI|215YE7+n@_pWapP31P zXWx6j_rh<@S!eCN*T>#_t-bf!2W2+d_AI2d9v7v(2%!JX-%HcVe*?T1kW~_I!=7IT zjNO;fr?*Rr{EH*bYpwGtuVnk=Gue*4{}%F%Jt=FPE#yj#=zQej!`jsprB^wpGidC6 zfFm2LR}bB^K4TBLG+|9eyoRy2Ph@2+sKd(1;Yn+EKhUqyx4XaIuQ9Z{%lkFy?e4;U zO-8$WM!(|F^Vu&mobS)h*7KXftklv^QN7_bFs}a%O`o-T<#rWsS8b`|%ixKG8I=4hefr(p}~lUiTJ z+f|&|$o2bFe5IAna$@yLqZnMJ$XpNlYA9uxXZ=zX3x7`zt_rT|6OBDu;)ZsQj@oyU z65FECQ2j7xBZr*?Hw{^b$!6@u7Am~J4dw4NX$owtt|Nzb2v4D|L1-0qPR&lm*8Ma5`yoP%IQ@mHa zTf9q*_B?vrAW<76&#!%FThJc>jd|!CMaDuF9i~c8gyluXt2=8``XbPQMnt z(mmob;i#}mT;|~eUg=)(We>NEE6zOMD%~f}7S2dVg=L=BfLl7`$swrWxeQdzY?~2_cbl@>}%*~Diw4cx~?wtN#2?xVq^I}>4;bpzh>P@P z3d+gh|B_O{$vKLoGu5R2mfH&@cXdVy`!#su^t|O)YB&dzeWeC7uJ=R6&2g%RANpYI zWtp>mf%!+TDhemnI@AHEB=EOS;9fD!E>cLFM5?{Avm6sHLmPPvffWo?{T$W zS~N-91KM7d=4g40ILTMH=k7AWnQGF3+X_d3zZ*O^>s?FWz zkmD?|2ym#4v+wd)LyRLYMa=zve~RW@nXnBU(nF4x4$?}8{r^;vF4*io;h~Cj&*AC) z(wo%eThQb?swOYVkTh>yT~bm|jWkI)yc92~GdEZK2(!1_d`Y^a*l}U4e&>m^DO`kG zy7R!LW0|g#R(sCxH3_1P(M!;12{gKW zN~2`&Y0oVLy=02c#@Gev3smX$mYo>&X8$c-tI+4{=GF=GP_wx@X;VREk-%(OqiTLt zRxWtjr+8kKH4F3`rszzT5wdQ$Mph>3WLzU9Gasb|^~d5kRY=WM<+$ zq$quWSAU`?S}joufbbsbQp<+kaih0IKKQiy~uT9aOySu_506dOR zt~%0}{65&^Q^)wKPcH1eDz6aIelJhsg3-AhT<*Mv%L;H=rg9mOncULIwJjE+MVZ=S z8Xfu+gARZ`jINWO@y}b6AaiUJ~x}?r?DvO0I&tUaa*XeZw zYFehaUA5W>I$)ZV3`ohmMv5MF0Mn$TC8XSsk^HXA#w|H!Z2XdA73|qsU>Dw`jn*Ti zwag>SVr6l0z(M(?N~tN3wwN5nf!QmHgAUSzk`Up-Xa7mLZ`-)8Eyh zW=e;fR2|-#(!pC<3>~iL^zDdFs&X9lC;N%T^@5gnDciCFEA6K8YD>NTNZgX!kDNHd zFZJblazdRl)A5~YI$qEBuD{Fo#w6b~@MRnpF}^vWZ^`hL@D^Do-BWsOs&{W7{Ssx# zl9s>GbC!*kJk>g9DA^C$OiJmOX+JX|1-wJxB`*Bb;Ptv-+%p)#nGWRp=U@cQV;5#+)|iQSl;2 zkiXp?EGn}Gsc0~~6YIhT|4hU?qhppsVai{0YE(N9iw6E~3^4Z8=WR?2IS1%~7$^^!X+e5; zBV}09NwBVO(eu_8=5u`60e387>?IoR(GeS`LDJ_kPu;cQjSb{5Y&1|&DQ7bVxn(&) zZ!_6hjOav+xJ22x9q|0fhEg>)6o!kWB(1R2*wRYX{^}HZ>-*6pwMebEI8s%*%il*v zb3JBWL%CqS!{t!@^}>|Deie4}AxHFQC*G$exxb=cT2B0UIsHp>p`^t2D#a4p*%U4* zN$hRbsO$FJP;r!b=7lNGxw+l+k-4yp z^>(3j%6}_Xk6YEaG)NiP^)0XzE@JzmLTS6dG%=DTf@Egs5a@%Yt8djtI|WK z<)qxW-T6~?V{f0Z+i;!TX4P)Pm)fD5vg7QJyX33#G7|DWl{wclUt)(2cBH9xbjeBo zW`6x;YsXN}??mc3Al9XY3f`rIqEOyyhO4+{gfnOk-D_P@H!paTVN;O1gI`29$0BtU zHotD(AhKAdX-f}=UimdULC{doAH{n_QS9q!Jq}S)x%0F?7qQ`<0jE^%=<-+V=-k0e z2^?#8x!vzSxtbUJ)p1%!g4R2Yc2-O0_9oh7>vGPOJ39TpTFnWa)iz0Rp7f{9EApHK ze$ua9!7!)P?H|z6TkVN99gw**fuGgIW&T3t&mWJz^0N3Z;?vN*StQ5B5YxB&1b5UF zVp<=$IGZw^`^9GQ$^739YTCLHZ!{r0X5kzDLdT){v$P94?4PQ$Ft@E+*FD3z@lZ3{ zZ6Dr1b{nz){SyVw%Qz`f=+r&2qXHiF6QIit0Dz2uZO-u(@ zL-*kI`{Z8^K1-eAN%JXxX{fA?*?7wUp77SnL5JiM`~8jJS|P5h{)p<}7njYY@C&B* zM^T$pRd(8cg{tBGhs;@2SfYm?t~A$~zlt6HhVpn1m^M;`AIzeTAMb2dVlPdMN2?Hz z4WT4I6LyS@V?l)RJLON(*-kRIWdPB>-|U&PzH3H@NUmGM$y!#L!FB^}7Sy&#>qI4X zXtEHRCClSnx+vRUt=)XC%F*hNbG+#~j<-dwZP873>5Tuz)kfh)FYh^1T_t`<6^Mon zW&_zF(Il-aHwDs($+b$=<<>wx+s{bkN((1z&H_a*wYhy~r}MV7un{^r?vs;LD`j41 zgE09b)+Yt)k@8=F7+@0nZmdzvUzzXz1pB?D-(Iz9-*r~)o7PWR*U6YU`9nFWDcg(b zp_dYqN0s-l_8yCYYTsc#9F1O;^Zh9~-7}Kok8#GV*b_}!6_1~+7lY`UF>3vOG8JpMe_^-SlpWlNQHEnmRevA2b zotKqQvn%Ok%&OY=~;%1&2 z!`SS4VT|cJ8EaS8z9%3$YHiy*oz=5^cB#FZmH*qA9nrVlpS@Zmv{$cxkI{~eed|5O zW#$x@onu?xV{O9m>tnY#Wk^IGIRZ^A8}$&SW7Nl_=k=T!d|V4&ayZGyFqy+VT%-&1IKs2c-S0*vW=zhP)YNPRu4G72OoM)JDZ~!XxM%v9=DeIOAfVh3WrMZMRecO)s^TP$3r8Uysj@HnuRmKdZUa zmf>T+C7_=gPmf-0!7|MISMkUK8C+bLN#-1U1r2qM56jHX-RNhg`!+i_v|xnEd++Cq@BW=uznf3%7UZwhPCH@U2DoNWA_ts zXl*yeIoZY*Qm|KW#%26|lwt9blcR6S+raNi?QfC8i_`RDH2-~>oBys%MOxK{lT-5| zK4V&;i=}D@=9ynDVboK#Im;vJ8_U|qDO5ZwtXAfyL3=8^AjWerF#KyK2ynbtDbIvp}s^&^BRb~4w`EOW$ zsmfS3Sbqgpr3;)ZGt9fP!^{V_Iy*hAFEU0o(IT>;>SHhoIXWRkt}~ zZ_CxWry7_>H1yFZImr=UNnRc~Ba?&aA01_!$Z@F(rFPbH$3|X}ZSdT8WTp#BYFgy&_W*uZv3e)#Cml-Zwwlpp%CdL{d=eSTe{7jkoUoCKK;RN^Y+jgVC}$8hk~ovsE6PO!^3f_KObgu zZeh>%<18}zTJ$cu&_0Nn?Cr1pndob?8d8htLT9vtdMkF-J}%P3%nv?7M-g%Mhi8fK%-<3{K8s1lo}{4N@w zOIK=6Cb;G*uSDBhkfRTBF8%qqZ}P>dVdeu$EJJw??exmgDB-q+b9w^fkgCDm3TIbh zznb6+HDM;}2P2&cet(_Z7p0-^j_g5;tnf;SE3$=OKcU2)pIGU$v@`{nC0%G|RNFO- z{2Ul&H4R$(l zeP&I5DEm@mb!0M>%kldGdd#oPGmN znh0z4jo}`dJugpQ%W>#Sd7YVf61)zmyiQK;mo+I_Z?XJV0jEP&64@MZ`u(J5&i<9Q z0FONrdruwSA;;_FpvEUy9ZkemC%#}u)%J$d4F)1R4gEX%kFBdFiogGE>Ydfqpzg=Z zwqrlDy((V*>Qs6B{l&yPTUoUj`}q1mLx-l(b<^lSQ|ZB;w&VG}^-UpLpN8|SZ}2zq z0^h-R`I|!aoxH*0Z>Vd+n!K0mHaazXX+Q+#0x}UPUVa+q_TyWd4fRdEQ?pUtf zoBGo@?dD-bW5-U8mCqcpspa`7kC)CJPCFiC-y+~HSnJ~))_~S)YSOZd18#!*#DhH9 z@K2ajkSF$aHKikG+0|f`)H}w2-bW5=aJO?nXKgZKhWXv=R_5|r@45}FEtPY^r)YP8 z@z9cB?Ah#7a}1H!qmnOIV!N)s=zS_y5&4F9Zxj1YVsFDnpH&L@tbq+`?YZGb)EG!L zyw!kbLxn-A%1aA$n~_5}@pVL}fACpbGVKQ8YZZo|wIy3`4SqH8O+}Sz&)#S?+I6QI zB5UzndrkX$(Ee_;*Pwl++P)*r8Wa=l|5IKGomQhS_BO0wmIm%rHM%G4#Dxw9oIy4OhfR;vx()hO%29gHfDdq_b9_@ z7(0yPdEjBd2Y?|!6!0z}0$^jjpp?>{#yRn0yqm}IL_GT(ZQsKC5%78#JkdX3Y-6v)L{kSoabmXY8Hndl!42i;XjUgV^<010Tvs-I;Dl`nTMU#yNk>pLllmp8hS*e;l8P{d_`+J&r8Z3llW-_~;*e7n*oSmghpl zg(l>i_oQ{6Z^E}dI7*)f#V(}oN$uR<#3Az9Jo_6uK}p$@0!pah2%n_r_UKf~yHgbH z9&Kl56IWpObT)K1IR(vLO*eMOoF4Hl<1s_WjD5Rp`e*ud6R|TB&-tEcoQF|2E%R^a zYLd{$h(wzm9&4k2OUSNg5pv^G-p3kuHwp6>dUiJ$H`_eM#;PrxXYIy_WcNfcFHk$+ zZ*m}(9`Hhr#uWH1&Ti{!J6CIjbyc0djrPvQ{j1M6KGBfhcmZuL1T6Tq1lBj%5s^dA zT(o!%If1?F+4oT)`|CQ)gtb5Roo@^}x*GBtF@BhdNjW*5`i4h+?*vjE{sv2FSECZU zFuB9G-@WMkc3*DWesQ}Rp+dfHaogRU;wdpB>JgXG%%_#uw!KOsx;apd~Q zz7CQ7lDtl&uJt0*a?WI5G{attI5IZ!n`m|Ay?49X_@nDWyq$k`e;y4DjZoomM7y}h z{TTwq(I~foB2Ptm{Jt60;P($vt@^9O@7vLo1r**NyETQQ{krx{*12 zA$p6?=D3Im%IO3R+JU78-Uo>Ck zgReN6ID5Ot)R2c>Xc;jiViETk6_iHf>nh<6gT)iVcXkTF->{zImso6JF{2%u26{Li z8(FMW*Gs&AjySXrdqTDbpGVB35WvRc1FHM(dUofhe_(Nx_Hv7E@~xM+62-wHLt;!L zv*aR-rN41LVh7gBhXzg%diM@_jqCPs4bD<|@}2m#$@jXJgsW9-o$F#miOm>)TZT;m zZc)G7C31_xvX!5-zs?ziwPKcMmpGvB76~^c+@jO6AiDErK9gRvTcqwT_irLp@RH2g zXP_TGA9ess2lnZ31u#9ZE5j1LQ+ry*w}E?83XUL0z-(iE!E9!>d;nng&aKBYe258% zHJykf27x-L>mv3*6*>dHV;o5Afe_OY-&OL*(F*a5h!b$uRlm+O_Dsaqj;#WsZ*bI>Mk{2$Cg1hTRN+!A^n<1kZ~)h)!tUX za%q@n#$N3j1F>w)WNfjjSNY`UvT6g)h5T)7PtGl5V@=2lWcYZ*A)L65Q?J1r!TuLt zCwd|c{Y@Hmx65)Xb8Qo`Z;!IygQHh4cc>n|gT6-=OuZ{(xy-)WNu1Ewn7@(uo*;gU zlPr7jnzF9uB>e-Go_zbhVpOxA+a(@n%14p?)Cs&eKIx+-yt(=?wUL=Gv8o+YV2uKdvYRHHOB5AS#Rc$ zmEu$0ocH<5640-=! zh%;=?WjoW=djJ9RT${jafZv$FhpnpPj&e1Ux^19|3OcsUbqPGM)4mDoBam zT51i}2Z`g$+VO2JpQ$hY;`~C;K9|{yvZ7@=ZbH(r|L(&T83*4F_Ue84QtFzY=cPH6 z*xQPovP-ncHz=`)@~M0*rp*0UKrM7Tj;Cq$4@J{zPSVdbdH1+=k?hr`3NBzu{N_~T zc*)5}->PM^=QZ<>+#~&2-mEoTvD`~Ghi7)J@rRYNXrHk0G0q&1AH*J6H?GV1CRz_%XtA{4!{Ah0dfHNyppm3M!*e#Jb)Qs1>6UC5(DrbcrL+Hhv#fS zIv@*hgT_PUW3?H^q!Z28+(qkX4eGdQ3wV4d!Ouq3sQEp*SuG*@5N4hPOqlWiTmXv!to;+S zDQz2oOT050`+Enp2;f7&7XUr)A)ceYQaxrL#{<jv5 zj4pgWR*%UE^ABf$Gr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp z0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n z8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+R zz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hC zGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mE zI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwt zfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X z1~>zp0nPwtfHS}u;0*k~Wgt9_>30{ggnLPo$ zs#ms?`}~_RVrxatm@T=z{4KX5{2TPI9f+^V>0t#E0&!MWpz>>$vLO4lkdx!pp704w zPkL+Mo5rdgU}SW+QQjn zv3wfVp|2A4#qut(Y!=H_u}mI7Uo8Lr%xQRq7J}G9EbkJ_X0dD)%j7v)h~?853-p<& zFP3+SWg4S!)+(0Eb?l5_sV~=Byi39%VE|kW#t*BAmsvyp2SVN@-X$k3+5rs{1|PnD z-LR8|huXqyaLurwXGQ}vRj@(bFw<*KU=FI&-C9GkIo-kZ;i0#~s=;rKkOa2$Dw7IQ zp)}n=_FmO6y?21+O}V@y;Ru^zJ!EOEJUR1c><6pVMy=^23+L$AHq#^KokFr{yQ#qZ z_zLfd$vJ9M!lM3!ewJ9h&(c!)hDV*NCtc$dw!`!T=q8!Anexq-obQI%70mxfEOZe}@q9TVUs{97XE zM?x5TFk)+P;7^wOEz2y6Ey01WKb_=e`7H3eAj=VEYI7g6OuXm&mfqafxW_HcHJVIU zMO%4mg?gVkcqw5I+m@l)Gj;t_mI*Van|{nD-}zJ1&n@dL6_)Rqk6R{termdxHCv{d zRR^aw-xXxJPnlen+2(zY71e2O;m}*=TK7k4cK*Sj(NtTT?^y4yb^jQ6D{xiqddE@V zk5pehXEZIYJ?eO$q^eCo(^z@+YYw3_$vuU=ZtC)vu|uf4(1tM_@z%=?^s zJSC>MJ#hyQf|Kl;BbMgMeeNTcT8qdE#=Xw+L-_D;?ptw(D_CGtXiClDigJ&$ zhn_XZm3c!#ZhJ_T+ZGZY%{MZ$Zw*_DRlbzv3;wN6?~<*}BO&iV-0fBV_jAIfr`NE8d&QF4_ zQk!?xQ*3^cvznb=BNU|jsU)Bco0SxJbWwQGmJ$JdQY~2`-Q1j0jsFO#^w%)f+GA|a ztjk+wPBMMMj$|ESiDlt3P3D%F#U_LIqscDsRmYoN*)|K*UXiW8*`q380aq~n0xOvA z&*|xBaqjnRhpSRehpUs!@7HGs$86@o;`xxeAT1#4eH(h;5%m&+a@}s!?G@{cJ&!QK zZC$;4S*a=A{BU);+1l{K>GtX_sFt;;!UGxWT~>NEN?dW~loWq`-}1j9pS zT`yTwxdRzzZMJyz`BKwXSV-61ot-d3G%a)@40pBncS+rLz&nob(`2rEpD==o~>vCxVHSeYQ47mCSBX73vz*}q2k zM_TXK!@HS#qu$9pTWRa7;#^29!K3-`=$@!YGJBfyMW`>1 z*3%ppp!eBg?}nb8nDq^|xz#$;$((+n!88M!8|vjT<<`zJ(O7Ck&&T@8f=xrz=2%}- zQGZ*sp8C?FuiM7;H5oc7<9eAa^^%E*&c^zfoXA-3j&Qj5L0sFy;mMPMd&A+AxPJYu za9E>ZEFKpF?mZa}e+%nr@+82m;c(GF3adWG^6$F5#b7YK!dB~WcflGwok2L$duFoD z`-!ohZCfKC+dmnkvS8TSc<{?Ce^J2J!}5)O9pX%Ieo#a+ zMy-vFT8nyIie6IC%j9vrBti$5qL&1zmrl%NcZlXqo->+1d9J(zTXGGiS6Qp>2-9TF zV43s6^YR@=HoYWVlI}>D$Bg-oY4_%PjVuv0sotr`Xht{7-CH4CJfur!FSB|b-GisH z>1a9Ikq)giFnD)B$ILT>}bXpYoEe?WJ>0J1=BCu689XtOly1Lo@0Ad z8>~8v@fEg8x097;Bo>E@lQGN8eaf~rx}IAxOD|B4K4D8hTUya2)YjO0H6-_yB>CX^ zr#>`BeV8Nq@J7^!>e_tx5Nqj+fjD=a@u*GaiSl}G&s!`l^IqI(U6u8jYZ8w{Msm-Q zV@FgAtl8!%y$3?%;~NSeW9=^fr*`j@?Iyr3StujBQ+hi>SS$XvP@H>t$x~5wZ)1t` z!}I6&{Db{Cvo$kY99>SY%tIRWQgSQrCrQ2BSMc2nFNu~v7t+A;XXoum#_UWLvR-Rt zPVXG#1$oWWdZ&0&AqOP0Erv|2bDBR>hM_22#QMBT7%Li(?|Jpn`>FL9E0}Tl6=oBo zX9`OOqr!|C-YvN)CW@6Q-bfTAAqrSdvX{-y3kdF{KAlx((phb|=q@yF&F4_xlw(e3 zWV8G-qgQp0!8@x|=Vi05_;=#I&|;f}e5W-wn39q6TI&BCI)dDiv^o(sv1=7lJ6+j(O9)oPMZhc$MP979Pn-_j?HP6emSF2PRWhQW!YG`5(3(?~9;z4$XiqRUJP^ldp02ROELy1#wY<{8j7hCY zY*vY&*LsD8Q@qt1n1OP{0py6QEG=sfR(_zRM9d9&{#kChF0Vw}vyIi;>f_nDuLR}V zS)$&&KwZg0wv$You?CUntTbiZS6~#^>&57L{XE94>NN(xckCTDKkH}gCz;2-xrqJy zhCFw8Xm2>*O*@;s`Nh)SrbfJP-_e^Nq?LIwx-wP0LQu#r_RIaJ{ab(3Uc}bM@T~cz zxYIiWZ?dece)d5|UMaDi=YGL<7w#T+iFxS?OTn&hc4l4~?T_-@+ifM%oEBqFwzmf~t?nIz1HZMffkT$n3B9>*vBMTq<+cngm4b=>6m~ni zUw7~78QwWbF0XK(s*Dv51y(bE#!DG37RqJnzGQFj@t@NZ1REUqqh-0pVmUdm?P+x7 zuFN@Y%R+8gemTcoX*_7Fk7MT#UzN(ZcUKy0wo^-0CR=@^ZjV%VLQ!`{!_M!O+N8xz zIbUf!VEfrp!E~Tr?>6O}vL(!zWj=-SDVyeAD&@HQZI?Cd+%Boj9`w0WDxZmq^!Y>4 zzUt}V@n2Z}-SPx{-(X?JOTFZ8|1sfcdM|l>g$i|pP1A7*aq5dKiq;H^-GTiQ+1v)3+Y~k<_v*dQJ$(lD5%OnvC@*Yu zr}trxZc4{vjxgAFv;E3cwx@5FCp@GJ7kG|($cF-F|CQK%@=vZj$qrafWxQZ3=`HP} zG0we=Z>-kZD@M1~a@N)it5ueU`VZJ@tcy1@O0X`-?+=1{cU|de+xx5@tN*c#RF+qq zh;>+=u{z`P*x|QSMi@wMWdYTdRJP}vJ2!-fp1(N~tV2Fd>Xq%KW5-Aqa|2}W1)E$? zJISn`%gFX;GtAM^ADpNV@n z*BQ6jA{OVwSiCzhzC}MXxL>y2xm0Vqvsz_-xxUWw9;-q&bY>(m1A0t%H&muOk{R`@ zbJthu9Mfq(<7Nd3epz!WY7*Uj71lFK+nGHyL#IZpA-Pt^CdZ7yH2NIwPhs4T!hgm! zgliQ0Zrr12z0%tK7WRAcx*Z$UzL-(%Q}C1;)5oOIuZ3h!X)l%tzrsVI>*06C*rOaM za))?08XW8AE75-XC(84Wc}7(14$7m7bv!!M&@V@AN z2=SQ$aYxUB^1d*9BOGQY5TAd=byM6w#iyK)Jaag)Ps}SeWw89Dz_!lqy>y!SDx+G8 zH&e#PA;Gw<^K@@kihAo{h%v#M;r1@UnIX=TwF7ioIy!WIM7UdRZE`Tce+o*8<$e4EE>ymV`|3OH1G-WJ2ye6EN;E$_* zY)!x0!1gccg+|zT6{kJg6M~8{bB?-~E%h$Bn=!py-mECUigJ>qa}s4Q&UYWg`RmtK z34^cQ*bZy&);+$86(sqo{9Z=FqIa7zO5bd{?B2hGo@~f7oSU%}mfYhorm{?vu41-d zKWk3lY9GtL-G2@2SejNN7pGiu^pO7_H1)fS;px@BVwQ)S>d!}}1)F=w?~fa=_N7?q zZ!zj$7)cI}wV)H`{Yz9h1xhLq{M55xR8_IT10%yB8t22{nS9@B5C&)85D+oKVBU>w z;&<*1V)ae1n(QYJ-fUV8?;o7;W9Gmpy*F4+%L=kc?bVxEL1~~DvI3?ulC^8ssT8sJ z_v;BcYGcIeN7uiu??o>)H{uxC57x1~Ierbe$s%rYX#Sq8)08|}H*+&9oEqpYowD#~ zQ$LGX(%&dz-V>&rNFTquPNj(C)b&?GTVe10rr+QUFH)CygUx&=B+Ps(#Aa#4F`SCV zMI>Uj!I#Xs9f&iVD52UHnx-rYh=@+@BQ-34s$a9{Y?Gj;T%bMiHRuV3KppCA+t9kc zsc%7e0kQYn>rDR_?8QF}X$R!C)BKvvY<5!M06g0&YEx@r@cHX{raeJkpOL&427h{; z<^CNfw0}c;mUo+)q|F%3?Kar@O$NnW`nBugS?SffH0xE{ zZHunfX-luHc^{)nHVFlj{i=dAKdr$nIS0(dMap$`a2C^}5R?F4_v3yq9!%Ym&t>Q>EV*y?lbP)6_YMRe9Q8%0*!x^wAQHewSKbh zxbbdir!Edpqgx#hRj`XmY|pVwv0v+r%c1>CJ`6?L_M`3DXxl#o_AhxAt1!~@a;axk ze!QPn)tfjQHo*t)i5EO^>yK7sUwF_nixnXsrQcw);sXN}nhPUf9vDdO{LH}yl~6nyx*g!E3W88wDWwl-d07+x4T0UyN)`wMG?MG>SOAg$AD z)M8GFtcKG~m*LrvfB%wCL&-gAueHbQeYq!1wX3H;!`xfFDNU8UsXt?T@5?CdLg{p` zcL~jUFV?~EaAee<3{%V%4Qzj!GNZL8v4CCNbp?@JeYWX)7Hgj_X+l1`cp$ikov3=K z={pv-nbyGv$Q(^TzMtfC`+55W0^JPWdnb4(Uarp}_>}7{VPvm}AOZ~nOl56^3 z{xRAmhK~jr-nIxiX2%G6RpZ@?UE4Fi9`)ZKJp`y1nu+Cuh;7zjFc+D$We0g*OEY@6e z2Vd!fkAX=1stVvEo@c{DzZhK&ADh*)+d9by6v?ORnUvmSbhxbd!m8WqJ-@k-(CS1!= z*qd~LGxONLnADPiFj559Y=_2fjD3eWO^2$sN zBySQ5lBKLk{eFNMPY6)H`Hx`@Y??*|{Jj_L=^joiuCFg~ld;E0h6PAB5e)Y11s*7%S(Gb!OWLoMi46R^gs#2R&& zR@|5k;$rKt|CW{pZ@vgiFNp0zqrVa@{Subc0cy2&cpyaIZ;p<)ICx82FW>wwY#kD9 zof_RAQpcyBqw}p?Ar7aKIL(2j-;J7Y-(RkGsIX@uJYjf8D55h38Xw{An9k_#q{`h< zx7~T#nZ%fZ4gLZA(S0?YMeuK}R&uMdZJZ$|LwW3DccbgSn5~AK2hy ziuyQ3{rALr??B(v)2*vKz50`C!Mw_8^QcU!J*tB?Pp@I8D#>hfuJ+)byjSSg=BW3w z8S#&39ua27eVg75tA9k#1$PgdAc=qEzD1h76TTg(D;!2PHtrNiKIxiXluw5|BE4fc z;b|}Z76I>qHCDl>b7-p5JsLW3z?bwukm?LTy>4VEQZC9U>bVX3`F6|JFGfKi>Q5vzZn{rCnTM7;@er3csKv4c4Pw|AeH#3Vg2^*M2$LFGG7Z+SiKh_ax}N z7ODN8LgnyjDY)3{yq8Am_?+m`a(@NB`&mWx!KV4}a{-X;_Pyn+D?W$k&+FLh(y7e7 z_@%*T(nkJU@=;PH;cxZa~ z4$*2tKrl>S$_DQkQ3vD5L)gc+ht9Ioo!S#LXRqV;D8mVuJIvz+l>NBg#Wjd4i0ds} z0bDf4vrAaQ6L?Pi5IAE5-^gd5pzS%}Be1m@@;1^z`5a^vPuhX(8oh(*v+y^o#^}hZ z)+(-aM;4w1h1@J_w)f>@cz@u>wJ- zWU^$pu42R=U%l6@p*VG9C=<+T41a+V&ai)mYb#OY0}&o&BZeOn0xbUPEm&Nm~=qo&xPb$ZZarJ00tf zzSY3O0&1JdQjAu2x+$UHMqpwMo%PfXvB-_}%fS>CHW&l5662$B8v>MQb#>H3trOgj|F9 zfV1C|V^Z%`_hWY~BqG11Jd(6$;=YIVi9b3ScXR0Fn?JTb+B^fZp1#o5a?s-j$H+wM zjb>f5t*zIPNEx#A2i1=>KkPBhEHXdr)UMZ?was;Hf_X)2z-=%G5EsyP*gQt$(nHng zN1g8Y4W8W^nhq>gn;Pm4SX&JTn)ffg(EO-#dh#_ru7c413vt=Qh^h9{*i=+Qqo!-L=MgqdTm5ck!r<-v8 zmU)@2uDoOC!M=wrm-S#l+%Ak63e>NK&yvFi|1DbgQ z6(1u}91RMyS>Ojj75=^&RO9dOgBtN~9R9u*jGxW?`-8%P+U)Y`hQOghw8Q zm%D#>Gt(V>X zI5~VKIM=E-UP1;Y{f9`$L+eQA%(d$9-0~8m6G|<+l$ps?rHOs1z1u5>1IB32cSv^j z1*eO4@GB0FVAy3&cV>fyo@+@`E)pJLxh28KeU;%I2IUim-`Ry3)*J4p_{%7_P|nze zO#|B;$&HjN#rq}jC&)wluqUK@@CD>d){9H8!Vjp{Eq-$6Uw=<|lwL?}BQGFd9JC;ce7@nH+= zKUne00Ly(oBp4=whfju$C?%ux*WoIZ5>a}8*p1(*JrTlh1NX+~9>Ey_jg7dVG1FMy z#YOL(w>_O=MNUAjIe%JrHu5^t(#c(`bc!#+YEjv#$8- zOzptUp%pi152so>I`qVK%6s~WSR2voY;&hB#rr5Qrp31o-;>2}n_E07rJStahMcV1 zkWBS0x(&U0+*Mj^8<2_d-t?eD+~c6%l%Iza!r_15Bp-*S;gjJulyJ^tOsz^o-|=CV zmm1JkO-4Bzh3c^58g(rrS7V3xQg?>BCjPX@uvvD*|{9Y~Y zQX@M06sFfFlb)I-);x$4x7;Sp-MMs@hB(un(9|R`I;|NUnkV{IIr>RR90Q&URd>^# zTqvTsW;ho}v8s@V@Wk~rJCRf!!2TD%PBaIcXFY0hw@YU$cj#{peepW|J$(Ir#1317 zwFB;P3MRfQqqEGDO`~{1qd9*?`aMD9EsiXEZk+7k2D$!Sv0g@B32VjE&+Tp%o+-bM z(@(+RST#Ci3)A1Suov_6)ab{d$oZDsYFYSk@eB*U=k>(Xofdm2`mHUUhHQrl#d6LFof|Qnr;=9oNNNJ>S%Z< zXLv2ns(XY!AFK;oXnqFor@ZMl`Mlzm4GkUyBly&*2`4mrRaz9%1{AY2l z`f`sjw(924w_){<<7&FFXZd}kMjFS%K!`J(`#*&|Lot_@lPtamFd@!0Qn?Z3JEig< z_NlX^@{1@>lgi&fdAd|Sg0gm?kujWBCbPs$mKz_ut3>Br<7I-XbQgY`tD2mc|LKJy z)O`}7h|-~DGTwwFWB+{;ugCvZ>on(t>P7{f!ag$*pNScCJ1@K7N9*U(c# z;X9ti)db(3#&`PCuUXQU3hu;7>D9X{;sR+))2jqWy7YHS)s$+MqY9pDqUd=s;~N#% z&ZbtU)*#;o(;b?U$0}}|4G(R>UT*p@PHt|DhUninXh6*!xH7Po1bkBt6~7qM`_Qkx zlqJx&X)@D~BIfb?^qDEO6Kh(tj%fc^MPh)>WP_Q*NwrB*O|Y|x|4T?N zeH_Yw9r?;ed3fNYW%zi)@$cdn_R8{Gcd&#qJ^I9ToAmwE?JS{ndZg|svmj5TzXtnaN*~bEDe_y*KN46ab@7r;aZ35yO@Cg#P@uB$KiV#u4G)P zxNcLMStT>WmYH?1cD9yz#5UQ{`YP1=n2U8n=434>(I-!BVcn?f6lELG-UYpNXx)wy zX;X=MXKbc=F>7Eo(5YZ;u+b&i)3bVLKEMh^31jbJn5QB`72EMYoB_@NXMi)n8Q=_X z1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@N zXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5S za0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ z0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?( z3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk z&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u z;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp z0nWhxoPnDeEa3#MdAP{hqtjTzR$PLF#g6xIV>|s4_E^z)qGVY8Vq#D8}V7 ztq_+hFhP^6QpM%QGhss9Hgy8iCTawxN`j>cae~T3Ut8&m{a@Q)D$xeMSW-OwWhQ~_ zO(35%{~e#g|I8rq_a$8~WoOL!aCOQv&%J$u@v+d#s_Y1o|H0?Wk^0wDP{>vQ7)gP-J$uK z`a#vd2?||7)TOqwaU}{YA&CgT^+${&HH#>mWRbX1i_?S#n`Im!$cKK(jG7^i@X08Z zaa;_JkHHgSuxN&5N82Zga{SR#LCq)t8S@D;P8P9gvW#hTV;?n}I0jHsvq>>{vNXa- zwTAsIY(Vj0#6+Y<#d1-2N`dDAA6MW7z&}%93-BKlxElCn1^ztnpA@(mSS#_zz%TW$ z#9rW_Lca@G{*b@_3b00Mk9ZKuelN!Uh(Zn->w*19j7IFs@j+^zLM~&3q}abazvR!9h-1*gnv~`z zffU7$iroRZ64UtZi3ss`GP~;*?Xy*5?ajB4>lJbXtW+v6*>@-~$y*he4tH;K({uce^D&(YpK{KXL_68Mr%PrcEDCE@sP~71kV5_!$Z3C4CdtYE zs|q>k`xRJ?odNAxD6`A?>w-c~`mZZ+CiH2aqtt&(At(KJ6?iW6X+NaYA5_Rm{}Tl! ze@7IUFF6x~?+U9kVKbbk<}`vYN^#V3-_QP2~@PEO3hX}@r6%h{U46OM`G|3F<5?npdC5c z`%vNkN0=|dCe#a3{LU_s{nM~(kP}wQ+Z1vQ9!Usm740`GFrn6mrrh zIlk~oX0P00zAwb+2Njs?y`{h+e+o?UK?NrHumY2OM1e`JQ9RF+JVAj;u2o=?Pf=i! zXDcwt^$PqN#%BPYje0p=YZP*7-y4H*-ls=3K9T*KDF!#j;HDV-4Ml!^3;h$G25WNu zKBADTkq8LWnVBqqQ6aw_a>6*~ipmES@_QgBOvi83ekCOq=_9XSItPnXMe<*b01YJg)-&{X~{<4oYd5@r}SYkUw%IydC)alUPEbgdYa}BKAMM z5`GkTBA#a!O8DP_M-rGm7wd`a{|fjTp3jd65&QoM{3Gm_Z#1{uTm1hx-@l6E*>3TE&kR=RI}6Cm<&RNbUfp{H+B} zMZA6q_-{C$pyxM|?*yI-|4b4-4Ez!Lqx?E8e@M|{ciJBf~PH?xF~ zF}_sn_oe}V4f^uoC5`D{B4hx#4Bso0;JB>4ltIRA>a-wLec=Uc#k#d!6Sem^iiditYk50n0(K$ZOwcF){{SpZ1fLSV3cM10;~80$e+WDe`}N}z4g_Lc&pZ@pR4Zvmc)^|@4%cLNt=zGyv>zkR?#MgRMO-^2Nx zR*KIjfTyRjghAv*(*Gr}l8-;c;6DNDlffV2gYwBoz%#&4k<{N!;4et|lkBN+q+g8q zl;bfSSZO~u2A2ZM=l>Mn3xIdy{#FP3lz)~0(|LqEej9Ki_?F|hh1!Ep>W}z*0GOU% z{~rD$tVMo)2mBh&SMHPWpMh6FUtS-d z0#AUxj5R69KR91_QPR%<{vy`f4hhcyz6iO>6i@zGPf z(fAy|zeD`V^X&uvKKzsU{uZ#3&wgMf|4+u?U&r7-0QV9(_)va*BS!uY;O8;_*^rZe z>3Bs$?>i_TQNGFnelKM#e=Y#lr;NqVQed+pKE43_HwFLgz|SCF=S%jt0xSJL1WfM% z;fB~h&W4!*{N_s74@}Ru^8CIDOz%o%{Y2bIl=iZLe}jB2^H~5)?;2(OO5o{;9~z$# z`KTT^7x6~pr}?k}zpGepZr~>r@#h2n8{%~b0+RUJ1WfNNW&8U{uIO(7_(O%gUjb7- zM0bqx;j6&UEAD3(fN}mGjrXg-Taf?cd^!kx0`~DG_8&i)G1?Ep9nt^WfXflDUzX$r zz~^D#E#djV9>w~;2l)G#A35Htfeqk?_^0)HKkz5;hoJ+?7ariRqkma{3$P3N#5d{h z0!~!$@k8J{6#CBr3y2SSe*C~!Fg|%ae+E|0=U;(8!Tu*QzGQX{_<+J*5)9qMe&dKV zzG=Xl5u$Q_$p=>2TMYaI#Jjv+9l+sf7#}{gKHR`lF&;5rV170M(>rQ;e*1x)I4^oa z>hCb{*!?Pr{ScVmWmih_)4*V#QPQ_p*GVyte z_@4}{j9=vbarO&iun8FNbE5oNV&pF1Cl!2d27U?oN1l(}!21wic&8`M{{i4f@&2bq z%5P5rKLdSve{~A@BJ!CWZ|8u!74gj)e9lf^w|8z=+we!6_g&i!{ z$I89lHcyMw=jmt{wOLI^hu7TU-BjuHIjh<|KC!~$X=}5&Iy;)Xx+1uv)AfL>lU22^ z^+3mEr&cVtm9=#Gx_sSh*A})gyM6IeyQRLocCo!;@sg@#b~~zCJM8P)I+~qr_Euj< zXP4dC-NRZsHhSA!K38ku-3yB6-CD^`{n(wIoz6{mSG%us6Icq9o0p4pR3Eq?5z)MY_ndGcil(Stddu47KDVp0 z!RvChex?m|x4hdoX1c+J7#o9?E-`GP?up2=*4c&$Dw{t~srZ1W#kHc_+2&d6adnEG zMaGBdijLLS*6I2pP|MnNp4J{Rad(6T541?I(dlW&m)Bc7-|p({L{vq}T|SqWie+Q9 zWmo}JIer#5c6rf$tj^;jxCyEop{1dnne$X%NS4w={^z+<_?V zXp>>RtHtGcz$HWCgv!!z+sTGV7$(Gyf*oto*WJZ7x;7TxJ#XG!5ye)_9TcnDeT^L} z+dVBEtuBep<;yHpOIFsGH&!iQW^ZV$uUfXmURmB)9uZe9Yg}A!DK{_vtf;np*-A(n zSJp4C|E#pGetG3ebK^JxttdFrx)50f|0AKabT_*^tuA|UVNqexxT?9{w(fPF_O7{D z;)Pv4{4c2&LcefhOLw8G$LH#7M{Lj!gbLTSch3<^bMRB4IihyqXMQU5B~N>42|AmH z?!=!B72`KT3rfo7iY@0hd)ns~7S3(+G|yev(lXcCxp7W=N4skd{ak6T_`9OHK6m%V z=D82dpR;jpd&gSuTqG?I*82ZvLu$v6?Bf$)D=NI5E}Ft&%t*#dUUbTPI?*ZLF@|)#dV;QPb>f*}zEa{!ZK>>T1hbZIgXTUDa|s zMZaugagQA$td_N&bV>__(~1Nu8mY&KC_|fTtQO=tR_AJOZTNh&`(?FN(Qihy0I>3uOT<3q8+#P9(;At=0R-Nh2-XG!F}2#O=`Vsod;caiZeUL-?*O0 zKe``@VhSq+TKC4W>64vZTt~i&$n0xtAj%@Sw7bjIDN-wIR{7S-!;*rzvD4Y!wGqK7 zs?<3B{p*t5Ec5jB}z3QA&y8E~VA_#&KE0?xH9ab69k3iEPmw9$O(xgSbs`wzk+i z5dabUmIiwyYl$-KOQkJnrx-5SGqgD)sYjeCb9ZMa$RJXpWYs~{*-2c9onaPefoz1& z9g5wWJUl6VMEvr#Nl66}L0bl~786L!Dwd@p<3&}*))!XFV%j>1{LEMKgPaYE_R7Ub zrHdn(JJN5ZS@OOuvTUWGlZ9BGku@F7kJ4(ug2YQVUA!g&H zE~ht=j4Nx)k@DTn_I6j>xHTlN6B;r0sh~xXD>(=|UVSeJrz&8=Pnpfm7pbUsqMx;1jpMogOcqilXa5 z%GS|)10^#|Yp3|M_SyY?BnHRrrzL~LZjpT)OXy$eyzI_c97|2@cJYVa_BMJxVq&D@ z0U~nSmDh8pYhwqV0XNcqly>8hz<_Ra?#GW$?hN~h*6tR}kaF;19G17x^JApvZV$R< z4WBnh7o>$A{b+ilkt{CQC=zFq@7mGxIQDeMtp3Num4F*2vf0iHFH?vs_i**o2({kr>sE+=|BQt!yZ-Z!A%c5|0uak$b!F zpoEE7$JW`sYui7M$A5b86RDJL`yyp-Ja&r-jP3|hKv6s)lxxZxmMRU4U5#5K6?7+$ z>@6$mt@f35_Qv`pcJuPu@y#M!%PBnapeK0(k`WW~U5eE=*)3I;<>)xX@5ZEg%yfButG)PiYF8YmLA2(5Q?mD+(QB@^h6&RSmD?~3@eN@raNY#owiqYH>KxDP>432K3}J&xf{nS ztdJ%S_dT?7HFvLz+#<#Exc}ClENIcWG@T{mgEKt*;~lXW`9m`L+=+|I@wiSx?d`y-?0=$1 z|E7X`lc>-W<2ZATe&q4)K#j~FoypR8@!Rs~N7mb^(4%)NrpYSStN2}kY`PzM=+i43 zAbWW-z_+aTq*Rut^bqtKV)RJ&Sw$NX4??eo3erdRk93tYbq~&=gLuJ@qg1vCLeiso jNW>*^f)ak$U{JBEq$GW0|ENl-H(H{ie}fYJ$a?=9e1N{a literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW02/Release/ESLBlaster02.list b/hardware/esl_blaster/FW02/Release/ESLBlaster02.list new file mode 100644 index 0000000..aa5b490 --- /dev/null +++ b/hardware/esl_blaster/FW02/Release/ESLBlaster02.list @@ -0,0 +1,6098 @@ + +ESLBlaster02.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000030b4 080000c0 080000c0 000100c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .flash_data_array 000003f2 08007c00 08007c00 00027c00 2**2 + ALLOC + 3 .rodata 000001a4 08003174 08003174 00013174 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ARM.extab 00000000 08003318 08003318 00020174 2**0 + CONTENTS + 5 .ARM 00000000 08003318 08003318 00020174 2**0 + CONTENTS + 6 .preinit_array 00000000 08003318 08003318 00020174 2**0 + CONTENTS, ALLOC, LOAD, DATA + 7 .init_array 00000004 08003318 08003318 00013318 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .fini_array 00000004 0800331c 0800331c 0001331c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .data 00000174 20000000 08003320 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 10 .bss 00000dcc 20000174 08003494 00020174 2**2 + ALLOC + 11 ._user_heap_stack 00000580 20000f40 08003494 00020f40 2**0 + ALLOC + 12 .ARM.attributes 00000028 00000000 00000000 00020174 2**0 + CONTENTS, READONLY + 13 .comment 00000053 00000000 00000000 0002019c 2**0 + CONTENTS, READONLY + 14 .debug_frame 0000004c 00000000 00000000 000201f0 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000c0 <__do_global_dtors_aux>: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 20000174 .word 0x20000174 + 80000e0: 00000000 .word 0x00000000 + 80000e4: 0800315c .word 0x0800315c + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop ; (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 20000178 .word 0x20000178 + 8000104: 0800315c .word 0x0800315c + +08000108 <__udivsi3>: + 8000108: 2200 movs r2, #0 + 800010a: 0843 lsrs r3, r0, #1 + 800010c: 428b cmp r3, r1 + 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> + 8000110: 0903 lsrs r3, r0, #4 + 8000112: 428b cmp r3, r1 + 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> + 8000116: 0a03 lsrs r3, r0, #8 + 8000118: 428b cmp r3, r1 + 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> + 800011c: 0b03 lsrs r3, r0, #12 + 800011e: 428b cmp r3, r1 + 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> + 8000122: 0c03 lsrs r3, r0, #16 + 8000124: 428b cmp r3, r1 + 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> + 8000128: 22ff movs r2, #255 ; 0xff + 800012a: 0209 lsls r1, r1, #8 + 800012c: ba12 rev r2, r2 + 800012e: 0c03 lsrs r3, r0, #16 + 8000130: 428b cmp r3, r1 + 8000132: d302 bcc.n 800013a <__udivsi3+0x32> + 8000134: 1212 asrs r2, r2, #8 + 8000136: 0209 lsls r1, r1, #8 + 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> + 800013a: 0b03 lsrs r3, r0, #12 + 800013c: 428b cmp r3, r1 + 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> + 8000140: e000 b.n 8000144 <__udivsi3+0x3c> + 8000142: 0a09 lsrs r1, r1, #8 + 8000144: 0bc3 lsrs r3, r0, #15 + 8000146: 428b cmp r3, r1 + 8000148: d301 bcc.n 800014e <__udivsi3+0x46> + 800014a: 03cb lsls r3, r1, #15 + 800014c: 1ac0 subs r0, r0, r3 + 800014e: 4152 adcs r2, r2 + 8000150: 0b83 lsrs r3, r0, #14 + 8000152: 428b cmp r3, r1 + 8000154: d301 bcc.n 800015a <__udivsi3+0x52> + 8000156: 038b lsls r3, r1, #14 + 8000158: 1ac0 subs r0, r0, r3 + 800015a: 4152 adcs r2, r2 + 800015c: 0b43 lsrs r3, r0, #13 + 800015e: 428b cmp r3, r1 + 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> + 8000162: 034b lsls r3, r1, #13 + 8000164: 1ac0 subs r0, r0, r3 + 8000166: 4152 adcs r2, r2 + 8000168: 0b03 lsrs r3, r0, #12 + 800016a: 428b cmp r3, r1 + 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> + 800016e: 030b lsls r3, r1, #12 + 8000170: 1ac0 subs r0, r0, r3 + 8000172: 4152 adcs r2, r2 + 8000174: 0ac3 lsrs r3, r0, #11 + 8000176: 428b cmp r3, r1 + 8000178: d301 bcc.n 800017e <__udivsi3+0x76> + 800017a: 02cb lsls r3, r1, #11 + 800017c: 1ac0 subs r0, r0, r3 + 800017e: 4152 adcs r2, r2 + 8000180: 0a83 lsrs r3, r0, #10 + 8000182: 428b cmp r3, r1 + 8000184: d301 bcc.n 800018a <__udivsi3+0x82> + 8000186: 028b lsls r3, r1, #10 + 8000188: 1ac0 subs r0, r0, r3 + 800018a: 4152 adcs r2, r2 + 800018c: 0a43 lsrs r3, r0, #9 + 800018e: 428b cmp r3, r1 + 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> + 8000192: 024b lsls r3, r1, #9 + 8000194: 1ac0 subs r0, r0, r3 + 8000196: 4152 adcs r2, r2 + 8000198: 0a03 lsrs r3, r0, #8 + 800019a: 428b cmp r3, r1 + 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> + 800019e: 020b lsls r3, r1, #8 + 80001a0: 1ac0 subs r0, r0, r3 + 80001a2: 4152 adcs r2, r2 + 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> + 80001a6: 09c3 lsrs r3, r0, #7 + 80001a8: 428b cmp r3, r1 + 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> + 80001ac: 01cb lsls r3, r1, #7 + 80001ae: 1ac0 subs r0, r0, r3 + 80001b0: 4152 adcs r2, r2 + 80001b2: 0983 lsrs r3, r0, #6 + 80001b4: 428b cmp r3, r1 + 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> + 80001b8: 018b lsls r3, r1, #6 + 80001ba: 1ac0 subs r0, r0, r3 + 80001bc: 4152 adcs r2, r2 + 80001be: 0943 lsrs r3, r0, #5 + 80001c0: 428b cmp r3, r1 + 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> + 80001c4: 014b lsls r3, r1, #5 + 80001c6: 1ac0 subs r0, r0, r3 + 80001c8: 4152 adcs r2, r2 + 80001ca: 0903 lsrs r3, r0, #4 + 80001cc: 428b cmp r3, r1 + 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> + 80001d0: 010b lsls r3, r1, #4 + 80001d2: 1ac0 subs r0, r0, r3 + 80001d4: 4152 adcs r2, r2 + 80001d6: 08c3 lsrs r3, r0, #3 + 80001d8: 428b cmp r3, r1 + 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> + 80001dc: 00cb lsls r3, r1, #3 + 80001de: 1ac0 subs r0, r0, r3 + 80001e0: 4152 adcs r2, r2 + 80001e2: 0883 lsrs r3, r0, #2 + 80001e4: 428b cmp r3, r1 + 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> + 80001e8: 008b lsls r3, r1, #2 + 80001ea: 1ac0 subs r0, r0, r3 + 80001ec: 4152 adcs r2, r2 + 80001ee: 0843 lsrs r3, r0, #1 + 80001f0: 428b cmp r3, r1 + 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> + 80001f4: 004b lsls r3, r1, #1 + 80001f6: 1ac0 subs r0, r0, r3 + 80001f8: 4152 adcs r2, r2 + 80001fa: 1a41 subs r1, r0, r1 + 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> + 80001fe: 4601 mov r1, r0 + 8000200: 4152 adcs r2, r2 + 8000202: 4610 mov r0, r2 + 8000204: 4770 bx lr + 8000206: e7ff b.n 8000208 <__udivsi3+0x100> + 8000208: b501 push {r0, lr} + 800020a: 2000 movs r0, #0 + 800020c: f000 f806 bl 800021c <__aeabi_idiv0> + 8000210: bd02 pop {r1, pc} + 8000212: 46c0 nop ; (mov r8, r8) + +08000214 <__aeabi_uidivmod>: + 8000214: 2900 cmp r1, #0 + 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> + 8000218: e776 b.n 8000108 <__udivsi3> + 800021a: 4770 bx lr + +0800021c <__aeabi_idiv0>: + 800021c: 4770 bx lr + 800021e: 46c0 nop ; (mov r8, r8) + +08000220 : + 8000220: b510 push {r4, lr} + 8000222: 0004 movs r4, r0 + 8000224: f001 fa90 bl 8001748 + 8000228: 21fa movs r1, #250 ; 0xfa + 800022a: 0089 lsls r1, r1, #2 + 800022c: f7ff ff6c bl 8000108 <__udivsi3> + 8000230: f000 f85c bl 80002ec + 8000234: 2001 movs r0, #1 + 8000236: 2200 movs r2, #0 + 8000238: 0021 movs r1, r4 + 800023a: 4240 negs r0, r0 + 800023c: f000 f81a bl 8000274 + 8000240: 2000 movs r0, #0 + 8000242: bd10 pop {r4, pc} + +08000244 : + 8000244: b510 push {r4, lr} + 8000246: 4a06 ldr r2, [pc, #24] ; (8000260 ) + 8000248: 6813 ldr r3, [r2, #0] + 800024a: 2110 movs r1, #16 + 800024c: 430b orrs r3, r1 + 800024e: 6013 str r3, [r2, #0] + 8000250: 2000 movs r0, #0 + 8000252: f7ff ffe5 bl 8000220 + 8000256: f002 fc8f bl 8002b78 + 800025a: 2000 movs r0, #0 + 800025c: bd10 pop {r4, pc} + 800025e: 46c0 nop ; (mov r8, r8) + 8000260: 40022000 .word 0x40022000 + +08000264 : + 8000264: 4a02 ldr r2, [pc, #8] ; (8000270 ) + 8000266: 6813 ldr r3, [r2, #0] + 8000268: 3301 adds r3, #1 + 800026a: 6013 str r3, [r2, #0] + 800026c: 4770 bx lr + 800026e: 46c0 nop ; (mov r8, r8) + 8000270: 200004cc .word 0x200004cc + +08000274 : + 8000274: b570 push {r4, r5, r6, lr} + 8000276: 2800 cmp r0, #0 + 8000278: db14 blt.n 80002a4 + 800027a: 0884 lsrs r4, r0, #2 + 800027c: 00a4 lsls r4, r4, #2 + 800027e: 4b14 ldr r3, [pc, #80] ; (80002d0 ) + 8000280: 469c mov ip, r3 + 8000282: 4464 add r4, ip + 8000284: 26c0 movs r6, #192 ; 0xc0 + 8000286: 00b6 lsls r6, r6, #2 + 8000288: 59a5 ldr r5, [r4, r6] + 800028a: 2203 movs r2, #3 + 800028c: 4010 ands r0, r2 + 800028e: 00c0 lsls r0, r0, #3 + 8000290: 23ff movs r3, #255 ; 0xff + 8000292: 001a movs r2, r3 + 8000294: 4082 lsls r2, r0 + 8000296: 4395 bics r5, r2 + 8000298: 0189 lsls r1, r1, #6 + 800029a: 400b ands r3, r1 + 800029c: 4083 lsls r3, r0 + 800029e: 432b orrs r3, r5 + 80002a0: 51a3 str r3, [r4, r6] + 80002a2: bd70 pop {r4, r5, r6, pc} + 80002a4: 230f movs r3, #15 + 80002a6: 4003 ands r3, r0 + 80002a8: 3b08 subs r3, #8 + 80002aa: 089b lsrs r3, r3, #2 + 80002ac: 009b lsls r3, r3, #2 + 80002ae: 4a09 ldr r2, [pc, #36] ; (80002d4 ) + 80002b0: 4694 mov ip, r2 + 80002b2: 4463 add r3, ip + 80002b4: 69dd ldr r5, [r3, #28] + 80002b6: 2403 movs r4, #3 + 80002b8: 4020 ands r0, r4 + 80002ba: 00c0 lsls r0, r0, #3 + 80002bc: 22ff movs r2, #255 ; 0xff + 80002be: 0014 movs r4, r2 + 80002c0: 4084 lsls r4, r0 + 80002c2: 43a5 bics r5, r4 + 80002c4: 0189 lsls r1, r1, #6 + 80002c6: 400a ands r2, r1 + 80002c8: 4082 lsls r2, r0 + 80002ca: 432a orrs r2, r5 + 80002cc: 61da str r2, [r3, #28] + 80002ce: e7e8 b.n 80002a2 + 80002d0: e000e100 .word 0xe000e100 + 80002d4: e000ed00 .word 0xe000ed00 + +080002d8 : + 80002d8: 231f movs r3, #31 + 80002da: 4018 ands r0, r3 + 80002dc: 3b1e subs r3, #30 + 80002de: 4083 lsls r3, r0 + 80002e0: 4a01 ldr r2, [pc, #4] ; (80002e8 ) + 80002e2: 6013 str r3, [r2, #0] + 80002e4: 4770 bx lr + 80002e6: 46c0 nop ; (mov r8, r8) + 80002e8: e000e100 .word 0xe000e100 + +080002ec : + 80002ec: 3801 subs r0, #1 + 80002ee: 2380 movs r3, #128 ; 0x80 + 80002f0: 045b lsls r3, r3, #17 + 80002f2: 4298 cmp r0, r3 + 80002f4: d20f bcs.n 8000316 + 80002f6: 4a09 ldr r2, [pc, #36] ; (800031c ) + 80002f8: 6050 str r0, [r2, #4] + 80002fa: 4809 ldr r0, [pc, #36] ; (8000320 ) + 80002fc: 6a03 ldr r3, [r0, #32] + 80002fe: 021b lsls r3, r3, #8 + 8000300: 0a1b lsrs r3, r3, #8 + 8000302: 21c0 movs r1, #192 ; 0xc0 + 8000304: 0609 lsls r1, r1, #24 + 8000306: 430b orrs r3, r1 + 8000308: 6203 str r3, [r0, #32] + 800030a: 2300 movs r3, #0 + 800030c: 6093 str r3, [r2, #8] + 800030e: 3307 adds r3, #7 + 8000310: 6013 str r3, [r2, #0] + 8000312: 2000 movs r0, #0 + 8000314: 4770 bx lr + 8000316: 2001 movs r0, #1 + 8000318: e7fc b.n 8000314 + 800031a: 46c0 nop ; (mov r8, r8) + 800031c: e000e010 .word 0xe000e010 + 8000320: e000ed00 .word 0xe000ed00 + +08000324 : + 8000324: b5f0 push {r4, r5, r6, r7, lr} + 8000326: 46de mov lr, fp + 8000328: 4657 mov r7, sl + 800032a: 464e mov r6, r9 + 800032c: 4645 mov r5, r8 + 800032e: b5e0 push {r5, r6, r7, lr} + 8000330: b087 sub sp, #28 + 8000332: 680a ldr r2, [r1, #0] + 8000334: 2a00 cmp r2, #0 + 8000336: d100 bne.n 800033a + 8000338: e0c7 b.n 80004ca + 800033a: 2300 movs r3, #0 + 800033c: 2601 movs r6, #1 + 800033e: 2410 movs r4, #16 + 8000340: 46a2 mov sl, r4 + 8000342: 3c0d subs r4, #13 + 8000344: 46a1 mov r9, r4 + 8000346: 2480 movs r4, #128 ; 0x80 + 8000348: 0564 lsls r4, r4, #21 + 800034a: 46a3 mov fp, r4 + 800034c: 4c62 ldr r4, [pc, #392] ; (80004d8 ) + 800034e: 1904 adds r4, r0, r4 + 8000350: 4265 negs r5, r4 + 8000352: 416c adcs r4, r5 + 8000354: 4264 negs r4, r4 + 8000356: 9403 str r4, [sp, #12] + 8000358: e043 b.n 80003e2 + 800035a: 08da lsrs r2, r3, #3 + 800035c: 0092 lsls r2, r2, #2 + 800035e: 1882 adds r2, r0, r2 + 8000360: 9202 str r2, [sp, #8] + 8000362: 6a15 ldr r5, [r2, #32] + 8000364: 46ac mov ip, r5 + 8000366: 2507 movs r5, #7 + 8000368: 401d ands r5, r3 + 800036a: 00ad lsls r5, r5, #2 + 800036c: 270f movs r7, #15 + 800036e: 40af lsls r7, r5 + 8000370: 46b8 mov r8, r7 + 8000372: 4667 mov r7, ip + 8000374: 4642 mov r2, r8 + 8000376: 4397 bics r7, r2 + 8000378: 46bc mov ip, r7 + 800037a: 690f ldr r7, [r1, #16] + 800037c: 40af lsls r7, r5 + 800037e: 003d movs r5, r7 + 8000380: 4662 mov r2, ip + 8000382: 4315 orrs r5, r2 + 8000384: 9a02 ldr r2, [sp, #8] + 8000386: 6215 str r5, [r2, #32] + 8000388: e037 b.n 80003fa + 800038a: 2400 movs r4, #0 + 800038c: 40ac lsls r4, r5 + 800038e: 4665 mov r5, ip + 8000390: 432c orrs r4, r5 + 8000392: 6094 str r4, [r2, #8] + 8000394: 4a51 ldr r2, [pc, #324] ; (80004dc ) + 8000396: 6812 ldr r2, [r2, #0] + 8000398: 9c01 ldr r4, [sp, #4] + 800039a: 43e4 mvns r4, r4 + 800039c: 684d ldr r5, [r1, #4] + 800039e: 03ed lsls r5, r5, #15 + 80003a0: d500 bpl.n 80003a4 + 80003a2: e086 b.n 80004b2 + 80003a4: 4022 ands r2, r4 + 80003a6: 4d4d ldr r5, [pc, #308] ; (80004dc ) + 80003a8: 602a str r2, [r5, #0] + 80003aa: 686a ldr r2, [r5, #4] + 80003ac: 684d ldr r5, [r1, #4] + 80003ae: 03ad lsls r5, r5, #14 + 80003b0: d500 bpl.n 80003b4 + 80003b2: e081 b.n 80004b8 + 80003b4: 4022 ands r2, r4 + 80003b6: 4d49 ldr r5, [pc, #292] ; (80004dc ) + 80003b8: 606a str r2, [r5, #4] + 80003ba: 68aa ldr r2, [r5, #8] + 80003bc: 684d ldr r5, [r1, #4] + 80003be: 02ed lsls r5, r5, #11 + 80003c0: d47d bmi.n 80004be + 80003c2: 4022 ands r2, r4 + 80003c4: 4d45 ldr r5, [pc, #276] ; (80004dc ) + 80003c6: 60aa str r2, [r5, #8] + 80003c8: 68ea ldr r2, [r5, #12] + 80003ca: 684d ldr r5, [r1, #4] + 80003cc: 02ad lsls r5, r5, #10 + 80003ce: d479 bmi.n 80004c4 + 80003d0: 4022 ands r2, r4 + 80003d2: 0017 movs r7, r2 + 80003d4: 4a41 ldr r2, [pc, #260] ; (80004dc ) + 80003d6: 60d7 str r7, [r2, #12] + 80003d8: 3301 adds r3, #1 + 80003da: 680a ldr r2, [r1, #0] + 80003dc: 0014 movs r4, r2 + 80003de: 40dc lsrs r4, r3 + 80003e0: d073 beq.n 80004ca + 80003e2: 0034 movs r4, r6 + 80003e4: 409c lsls r4, r3 + 80003e6: 0017 movs r7, r2 + 80003e8: 4027 ands r7, r4 + 80003ea: 9701 str r7, [sp, #4] + 80003ec: 4222 tst r2, r4 + 80003ee: d0f3 beq.n 80003d8 + 80003f0: 684a ldr r2, [r1, #4] + 80003f2: 4655 mov r5, sl + 80003f4: 43aa bics r2, r5 + 80003f6: 2a02 cmp r2, #2 + 80003f8: d0af beq.n 800035a + 80003fa: 6802 ldr r2, [r0, #0] + 80003fc: 4690 mov r8, r2 + 80003fe: 005d lsls r5, r3, #1 + 8000400: 464a mov r2, r9 + 8000402: 40aa lsls r2, r5 + 8000404: 43d7 mvns r7, r2 + 8000406: 46bc mov ip, r7 + 8000408: 4647 mov r7, r8 + 800040a: 4397 bics r7, r2 + 800040c: 46b8 mov r8, r7 + 800040e: 684a ldr r2, [r1, #4] + 8000410: 464f mov r7, r9 + 8000412: 403a ands r2, r7 + 8000414: 40aa lsls r2, r5 + 8000416: 4647 mov r7, r8 + 8000418: 433a orrs r2, r7 + 800041a: 6002 str r2, [r0, #0] + 800041c: 684a ldr r2, [r1, #4] + 800041e: 4657 mov r7, sl + 8000420: 43ba bics r2, r7 + 8000422: 3a01 subs r2, #1 + 8000424: 2a01 cmp r2, #1 + 8000426: d80f bhi.n 8000448 + 8000428: 6882 ldr r2, [r0, #8] + 800042a: 4667 mov r7, ip + 800042c: 4017 ands r7, r2 + 800042e: 68ca ldr r2, [r1, #12] + 8000430: 40aa lsls r2, r5 + 8000432: 433a orrs r2, r7 + 8000434: 6082 str r2, [r0, #8] + 8000436: 6842 ldr r2, [r0, #4] + 8000438: 43a2 bics r2, r4 + 800043a: 0014 movs r4, r2 + 800043c: 684a ldr r2, [r1, #4] + 800043e: 0912 lsrs r2, r2, #4 + 8000440: 4032 ands r2, r6 + 8000442: 409a lsls r2, r3 + 8000444: 4322 orrs r2, r4 + 8000446: 6042 str r2, [r0, #4] + 8000448: 68c4 ldr r4, [r0, #12] + 800044a: 4662 mov r2, ip + 800044c: 4014 ands r4, r2 + 800044e: 688a ldr r2, [r1, #8] + 8000450: 40aa lsls r2, r5 + 8000452: 4322 orrs r2, r4 + 8000454: 60c2 str r2, [r0, #12] + 8000456: 684a ldr r2, [r1, #4] + 8000458: 465c mov r4, fp + 800045a: 4222 tst r2, r4 + 800045c: d0bc beq.n 80003d8 + 800045e: 4a20 ldr r2, [pc, #128] ; (80004e0 ) + 8000460: 6994 ldr r4, [r2, #24] + 8000462: 4334 orrs r4, r6 + 8000464: 6194 str r4, [r2, #24] + 8000466: 6992 ldr r2, [r2, #24] + 8000468: 4032 ands r2, r6 + 800046a: 9205 str r2, [sp, #20] + 800046c: 9a05 ldr r2, [sp, #20] + 800046e: 089a lsrs r2, r3, #2 + 8000470: 0092 lsls r2, r2, #2 + 8000472: 4c1c ldr r4, [pc, #112] ; (80004e4 ) + 8000474: 46a4 mov ip, r4 + 8000476: 4462 add r2, ip + 8000478: 6894 ldr r4, [r2, #8] + 800047a: 46a4 mov ip, r4 + 800047c: 464d mov r5, r9 + 800047e: 401d ands r5, r3 + 8000480: 00ad lsls r5, r5, #2 + 8000482: 240f movs r4, #15 + 8000484: 40ac lsls r4, r5 + 8000486: 4667 mov r7, ip + 8000488: 43a7 bics r7, r4 + 800048a: 46bc mov ip, r7 + 800048c: 2490 movs r4, #144 ; 0x90 + 800048e: 05e4 lsls r4, r4, #23 + 8000490: 42a0 cmp r0, r4 + 8000492: d100 bne.n 8000496 + 8000494: e779 b.n 800038a + 8000496: 4c14 ldr r4, [pc, #80] ; (80004e8 ) + 8000498: 42a0 cmp r0, r4 + 800049a: d006 beq.n 80004aa + 800049c: 4c13 ldr r4, [pc, #76] ; (80004ec ) + 800049e: 42a0 cmp r0, r4 + 80004a0: d005 beq.n 80004ae + 80004a2: 9c03 ldr r4, [sp, #12] + 80004a4: 43b4 bics r4, r6 + 80004a6: 3405 adds r4, #5 + 80004a8: e770 b.n 800038c + 80004aa: 2401 movs r4, #1 + 80004ac: e76e b.n 800038c + 80004ae: 2402 movs r4, #2 + 80004b0: e76c b.n 800038c + 80004b2: 9d01 ldr r5, [sp, #4] + 80004b4: 432a orrs r2, r5 + 80004b6: e776 b.n 80003a6 + 80004b8: 9d01 ldr r5, [sp, #4] + 80004ba: 432a orrs r2, r5 + 80004bc: e77b b.n 80003b6 + 80004be: 9d01 ldr r5, [sp, #4] + 80004c0: 432a orrs r2, r5 + 80004c2: e77f b.n 80003c4 + 80004c4: 9f01 ldr r7, [sp, #4] + 80004c6: 4317 orrs r7, r2 + 80004c8: e784 b.n 80003d4 + 80004ca: b007 add sp, #28 + 80004cc: bcf0 pop {r4, r5, r6, r7} + 80004ce: 46bb mov fp, r7 + 80004d0: 46b2 mov sl, r6 + 80004d2: 46a9 mov r9, r5 + 80004d4: 46a0 mov r8, r4 + 80004d6: bdf0 pop {r4, r5, r6, r7, pc} + 80004d8: b7fff400 .word 0xb7fff400 + 80004dc: 40010400 .word 0x40010400 + 80004e0: 40021000 .word 0x40021000 + 80004e4: 40010000 .word 0x40010000 + 80004e8: 48000400 .word 0x48000400 + 80004ec: 48000800 .word 0x48000800 + +080004f0 : + 80004f0: 2a00 cmp r2, #0 + 80004f2: d001 beq.n 80004f8 + 80004f4: 6181 str r1, [r0, #24] + 80004f6: 4770 bx lr + 80004f8: 6281 str r1, [r0, #40] ; 0x28 + 80004fa: e7fc b.n 80004f6 + +080004fc : + 80004fc: b570 push {r4, r5, r6, lr} + 80004fe: 1e05 subs r5, r0, #0 + 8000500: d049 beq.n 8000596 + 8000502: 23ea movs r3, #234 ; 0xea + 8000504: 33ff adds r3, #255 ; 0xff + 8000506: 5cc3 ldrb r3, [r0, r3] + 8000508: 2b00 cmp r3, #0 + 800050a: d03d beq.n 8000588 + 800050c: 23ea movs r3, #234 ; 0xea + 800050e: 33ff adds r3, #255 ; 0xff + 8000510: 2203 movs r2, #3 + 8000512: 54ea strb r2, [r5, r3] + 8000514: 686c ldr r4, [r5, #4] + 8000516: 2c00 cmp r4, #0 + 8000518: d01d beq.n 8000556 + 800051a: 002b movs r3, r5 + 800051c: 3328 adds r3, #40 ; 0x28 + 800051e: 2100 movs r1, #0 + 8000520: 2001 movs r0, #1 + 8000522: 2200 movs r2, #0 + 8000524: 7058 strb r0, [r3, #1] + 8000526: 7019 strb r1, [r3, #0] + 8000528: 70da strb r2, [r3, #3] + 800052a: 60da str r2, [r3, #12] + 800052c: 611a str r2, [r3, #16] + 800052e: 615a str r2, [r3, #20] + 8000530: 3101 adds r1, #1 + 8000532: 331c adds r3, #28 + 8000534: 42a1 cmp r1, r4 + 8000536: d1f5 bne.n 8000524 + 8000538: 002b movs r3, r5 + 800053a: 3309 adds r3, #9 + 800053c: 33ff adds r3, #255 ; 0xff + 800053e: 2100 movs r1, #0 + 8000540: 2200 movs r2, #0 + 8000542: 705a strb r2, [r3, #1] + 8000544: 7019 strb r1, [r3, #0] + 8000546: 70da strb r2, [r3, #3] + 8000548: 60da str r2, [r3, #12] + 800054a: 611a str r2, [r3, #16] + 800054c: 615a str r2, [r3, #20] + 800054e: 3101 adds r1, #1 + 8000550: 331c adds r3, #28 + 8000552: 42a1 cmp r1, r4 + 8000554: d1f5 bne.n 8000542 + 8000556: 2340 movs r3, #64 ; 0x40 + 8000558: 2201 movs r2, #1 + 800055a: 6829 ldr r1, [r5, #0] + 800055c: 52ca strh r2, [r1, r3] + 800055e: 2200 movs r2, #0 + 8000560: 6829 ldr r1, [r5, #0] + 8000562: 52ca strh r2, [r1, r3] + 8000564: 2144 movs r1, #68 ; 0x44 + 8000566: 6828 ldr r0, [r5, #0] + 8000568: 5242 strh r2, [r0, r1] + 800056a: 310c adds r1, #12 + 800056c: 6828 ldr r0, [r5, #0] + 800056e: 5242 strh r2, [r0, r1] + 8000570: 4a0a ldr r2, [pc, #40] ; (800059c ) + 8000572: 6829 ldr r1, [r5, #0] + 8000574: 52ca strh r2, [r1, r3] + 8000576: 2200 movs r2, #0 + 8000578: 3b1c subs r3, #28 + 800057a: 54ea strb r2, [r5, r3] + 800057c: 2201 movs r2, #1 + 800057e: 23ea movs r3, #234 ; 0xea + 8000580: 33ff adds r3, #255 ; 0xff + 8000582: 54ea strb r2, [r5, r3] + 8000584: 2000 movs r0, #0 + 8000586: bd70 pop {r4, r5, r6, pc} + 8000588: 33e9 adds r3, #233 ; 0xe9 + 800058a: 33ff adds r3, #255 ; 0xff + 800058c: 2200 movs r2, #0 + 800058e: 54c2 strb r2, [r0, r3] + 8000590: f002 fbe8 bl 8002d64 + 8000594: e7ba b.n 800050c + 8000596: 2001 movs r0, #1 + 8000598: e7f5 b.n 8000586 + 800059a: 46c0 nop ; (mov r8, r8) + 800059c: ffffbf00 .word 0xffffbf00 + +080005a0 : + 80005a0: 6801 ldr r1, [r0, #0] + 80005a2: 2258 movs r2, #88 ; 0x58 + 80005a4: 5a8b ldrh r3, [r1, r2] + 80005a6: 2080 movs r0, #128 ; 0x80 + 80005a8: 0200 lsls r0, r0, #8 + 80005aa: 4303 orrs r3, r0 + 80005ac: 528b strh r3, [r1, r2] + 80005ae: 2000 movs r0, #0 + 80005b0: 4770 bx lr + +080005b2 : + 80005b2: 23f4 movs r3, #244 ; 0xf4 + 80005b4: 005b lsls r3, r3, #1 + 80005b6: 5cc3 ldrb r3, [r0, r3] + 80005b8: 2b01 cmp r3, #1 + 80005ba: d013 beq.n 80005e4 + 80005bc: 23f4 movs r3, #244 ; 0xf4 + 80005be: 005b lsls r3, r3, #1 + 80005c0: 2201 movs r2, #1 + 80005c2: 54c2 strb r2, [r0, r3] + 80005c4: 2900 cmp r1, #0 + 80005c6: d10a bne.n 80005de + 80005c8: 3b9d subs r3, #157 ; 0x9d + 80005ca: 3bff subs r3, #255 ; 0xff + 80005cc: 327f adds r2, #127 ; 0x7f + 80005ce: 6801 ldr r1, [r0, #0] + 80005d0: 52ca strh r2, [r1, r3] + 80005d2: 23f4 movs r3, #244 ; 0xf4 + 80005d4: 005b lsls r3, r3, #1 + 80005d6: 2200 movs r2, #0 + 80005d8: 54c2 strb r2, [r0, r3] + 80005da: 2000 movs r0, #0 + 80005dc: 4770 bx lr + 80005de: 2324 movs r3, #36 ; 0x24 + 80005e0: 54c1 strb r1, [r0, r3] + 80005e2: e7f6 b.n 80005d2 + 80005e4: 2002 movs r0, #2 + 80005e6: e7f9 b.n 80005dc + +080005e8 : + 80005e8: b570 push {r4, r5, r6, lr} + 80005ea: b24d sxtb r5, r1 + 80005ec: 2d00 cmp r5, #0 + 80005ee: db29 blt.n 8000644 + 80005f0: 267f movs r6, #127 ; 0x7f + 80005f2: 400e ands r6, r1 + 80005f4: 00f4 lsls r4, r6, #3 + 80005f6: 1ba4 subs r4, r4, r6 + 80005f8: 00a4 lsls r4, r4, #2 + 80005fa: 3409 adds r4, #9 + 80005fc: 34ff adds r4, #255 ; 0xff + 80005fe: 1904 adds r4, r0, r4 + 8000600: 267f movs r6, #127 ; 0x7f + 8000602: 4031 ands r1, r6 + 8000604: 7021 strb r1, [r4, #0] + 8000606: 0fed lsrs r5, r5, #31 + 8000608: 7065 strb r5, [r4, #1] + 800060a: 60e2 str r2, [r4, #12] + 800060c: 70e3 strb r3, [r4, #3] + 800060e: 23f4 movs r3, #244 ; 0xf4 + 8000610: 005b lsls r3, r3, #1 + 8000612: 5cc3 ldrb r3, [r0, r3] + 8000614: 2b01 cmp r3, #1 + 8000616: d100 bne.n 800061a + 8000618: e14d b.n 80008b6 + 800061a: 23f4 movs r3, #244 ; 0xf4 + 800061c: 005b lsls r3, r3, #1 + 800061e: 2201 movs r2, #1 + 8000620: 54c2 strb r2, [r0, r3] + 8000622: 78e3 ldrb r3, [r4, #3] + 8000624: 2b02 cmp r3, #2 + 8000626: d100 bne.n 800062a + 8000628: e065 b.n 80006f6 + 800062a: d813 bhi.n 8000654 + 800062c: 2b00 cmp r3, #0 + 800062e: d01d beq.n 800066c + 8000630: 7823 ldrb r3, [r4, #0] + 8000632: 009b lsls r3, r3, #2 + 8000634: 6805 ldr r5, [r0, #0] + 8000636: 5aea ldrh r2, [r5, r3] + 8000638: 49a0 ldr r1, [pc, #640] ; (80008bc ) + 800063a: 4011 ands r1, r2 + 800063c: 4aa0 ldr r2, [pc, #640] ; (80008c0 ) + 800063e: 430a orrs r2, r1 + 8000640: 52ea strh r2, [r5, r3] + 8000642: e01c b.n 800067e + 8000644: 267f movs r6, #127 ; 0x7f + 8000646: 400e ands r6, r1 + 8000648: 00f4 lsls r4, r6, #3 + 800064a: 1ba4 subs r4, r4, r6 + 800064c: 00a4 lsls r4, r4, #2 + 800064e: 3428 adds r4, #40 ; 0x28 + 8000650: 1904 adds r4, r0, r4 + 8000652: e7d5 b.n 8000600 + 8000654: 2b03 cmp r3, #3 + 8000656: d112 bne.n 800067e + 8000658: 7823 ldrb r3, [r4, #0] + 800065a: 009b lsls r3, r3, #2 + 800065c: 6805 ldr r5, [r0, #0] + 800065e: 5aea ldrh r2, [r5, r3] + 8000660: 4996 ldr r1, [pc, #600] ; (80008bc ) + 8000662: 4011 ands r1, r2 + 8000664: 4a97 ldr r2, [pc, #604] ; (80008c4 ) + 8000666: 430a orrs r2, r1 + 8000668: 52ea strh r2, [r5, r3] + 800066a: e008 b.n 800067e + 800066c: 7823 ldrb r3, [r4, #0] + 800066e: 009b lsls r3, r3, #2 + 8000670: 6805 ldr r5, [r0, #0] + 8000672: 5aea ldrh r2, [r5, r3] + 8000674: 4991 ldr r1, [pc, #580] ; (80008bc ) + 8000676: 4011 ands r1, r2 + 8000678: 4a93 ldr r2, [pc, #588] ; (80008c8 ) + 800067a: 430a orrs r2, r1 + 800067c: 52ea strh r2, [r5, r3] + 800067e: 7822 ldrb r2, [r4, #0] + 8000680: 0095 lsls r5, r2, #2 + 8000682: 6801 ldr r1, [r0, #0] + 8000684: 5b4b ldrh r3, [r1, r5] + 8000686: 4e91 ldr r6, [pc, #580] ; (80008cc ) + 8000688: 4033 ands r3, r6 + 800068a: 4313 orrs r3, r2 + 800068c: 4a90 ldr r2, [pc, #576] ; (80008d0 ) + 800068e: 4313 orrs r3, r2 + 8000690: 534b strh r3, [r1, r5] + 8000692: 7aa3 ldrb r3, [r4, #10] + 8000694: 2b00 cmp r3, #0 + 8000696: d000 beq.n 800069a + 8000698: e07d b.n 8000796 + 800069a: 7863 ldrb r3, [r4, #1] + 800069c: 2b00 cmp r3, #0 + 800069e: d034 beq.n 800070a + 80006a0: 6802 ldr r2, [r0, #0] + 80006a2: 2350 movs r3, #80 ; 0x50 + 80006a4: 5ad3 ldrh r3, [r2, r3] + 80006a6: 7821 ldrb r1, [r4, #0] + 80006a8: 00c9 lsls r1, r1, #3 + 80006aa: 1852 adds r2, r2, r1 + 80006ac: 189b adds r3, r3, r2 + 80006ae: 2280 movs r2, #128 ; 0x80 + 80006b0: 00d2 lsls r2, r2, #3 + 80006b2: 4694 mov ip, r2 + 80006b4: 4463 add r3, ip + 80006b6: 88a2 ldrh r2, [r4, #4] + 80006b8: 2101 movs r1, #1 + 80006ba: 438a bics r2, r1 + 80006bc: 801a strh r2, [r3, #0] + 80006be: 7823 ldrb r3, [r4, #0] + 80006c0: 009b lsls r3, r3, #2 + 80006c2: 6802 ldr r2, [r0, #0] + 80006c4: 18d1 adds r1, r2, r3 + 80006c6: 5ad3 ldrh r3, [r2, r3] + 80006c8: 065a lsls r2, r3, #25 + 80006ca: d503 bpl.n 80006d4 + 80006cc: 4033 ands r3, r6 + 80006ce: 4a81 ldr r2, [pc, #516] ; (80008d4 ) + 80006d0: 4313 orrs r3, r2 + 80006d2: 800b strh r3, [r1, #0] + 80006d4: 7822 ldrb r2, [r4, #0] + 80006d6: 0092 lsls r2, r2, #2 + 80006d8: 6804 ldr r4, [r0, #0] + 80006da: 5aa3 ldrh r3, [r4, r2] + 80006dc: 497e ldr r1, [pc, #504] ; (80008d8 ) + 80006de: 400b ands r3, r1 + 80006e0: 2120 movs r1, #32 + 80006e2: 404b eors r3, r1 + 80006e4: 497a ldr r1, [pc, #488] ; (80008d0 ) + 80006e6: 430b orrs r3, r1 + 80006e8: 52a3 strh r3, [r4, r2] + 80006ea: 23f4 movs r3, #244 ; 0xf4 + 80006ec: 005b lsls r3, r3, #1 + 80006ee: 2200 movs r2, #0 + 80006f0: 54c2 strb r2, [r0, r3] + 80006f2: 2000 movs r0, #0 + 80006f4: bd70 pop {r4, r5, r6, pc} + 80006f6: 7823 ldrb r3, [r4, #0] + 80006f8: 009b lsls r3, r3, #2 + 80006fa: 6805 ldr r5, [r0, #0] + 80006fc: 5aea ldrh r2, [r5, r3] + 80006fe: 496f ldr r1, [pc, #444] ; (80008bc ) + 8000700: 4011 ands r1, r2 + 8000702: 4a73 ldr r2, [pc, #460] ; (80008d0 ) + 8000704: 430a orrs r2, r1 + 8000706: 52ea strh r2, [r5, r3] + 8000708: e7b9 b.n 800067e + 800070a: 6802 ldr r2, [r0, #0] + 800070c: 2550 movs r5, #80 ; 0x50 + 800070e: 5b53 ldrh r3, [r2, r5] + 8000710: 7821 ldrb r1, [r4, #0] + 8000712: 00c9 lsls r1, r1, #3 + 8000714: 1852 adds r2, r2, r1 + 8000716: 189b adds r3, r3, r2 + 8000718: 4a70 ldr r2, [pc, #448] ; (80008dc ) + 800071a: 4694 mov ip, r2 + 800071c: 4463 add r3, ip + 800071e: 88a2 ldrh r2, [r4, #4] + 8000720: 2101 movs r1, #1 + 8000722: 438a bics r2, r1 + 8000724: 801a strh r2, [r3, #0] + 8000726: 6802 ldr r2, [r0, #0] + 8000728: 5b53 ldrh r3, [r2, r5] + 800072a: 7821 ldrb r1, [r4, #0] + 800072c: 00c9 lsls r1, r1, #3 + 800072e: 185b adds r3, r3, r1 + 8000730: 496b ldr r1, [pc, #428] ; (80008e0 ) + 8000732: 468c mov ip, r1 + 8000734: 4462 add r2, ip + 8000736: 189b adds r3, r3, r2 + 8000738: 68e2 ldr r2, [r4, #12] + 800073a: 2a3e cmp r2, #62 ; 0x3e + 800073c: d922 bls.n 8000784 + 800073e: 0951 lsrs r1, r2, #5 + 8000740: b289 uxth r1, r1 + 8000742: 06d2 lsls r2, r2, #27 + 8000744: d101 bne.n 800074a + 8000746: 3901 subs r1, #1 + 8000748: b289 uxth r1, r1 + 800074a: 0289 lsls r1, r1, #10 + 800074c: 4a65 ldr r2, [pc, #404] ; (80008e4 ) + 800074e: 4311 orrs r1, r2 + 8000750: 8019 strh r1, [r3, #0] + 8000752: 7823 ldrb r3, [r4, #0] + 8000754: 009b lsls r3, r3, #2 + 8000756: 6802 ldr r2, [r0, #0] + 8000758: 18d1 adds r1, r2, r3 + 800075a: 5ad3 ldrh r3, [r2, r3] + 800075c: 045a lsls r2, r3, #17 + 800075e: d504 bpl.n 800076a + 8000760: 4a5a ldr r2, [pc, #360] ; (80008cc ) + 8000762: 4013 ands r3, r2 + 8000764: 4a60 ldr r2, [pc, #384] ; (80008e8 ) + 8000766: 4313 orrs r3, r2 + 8000768: 800b strh r3, [r1, #0] + 800076a: 7823 ldrb r3, [r4, #0] + 800076c: 009b lsls r3, r3, #2 + 800076e: 6804 ldr r4, [r0, #0] + 8000770: 5ae1 ldrh r1, [r4, r3] + 8000772: 4a5e ldr r2, [pc, #376] ; (80008ec ) + 8000774: 4011 ands r1, r2 + 8000776: 22c0 movs r2, #192 ; 0xc0 + 8000778: 0192 lsls r2, r2, #6 + 800077a: 4051 eors r1, r2 + 800077c: 4a54 ldr r2, [pc, #336] ; (80008d0 ) + 800077e: 430a orrs r2, r1 + 8000780: 52e2 strh r2, [r4, r3] + 8000782: e7b2 b.n 80006ea + 8000784: 0851 lsrs r1, r2, #1 + 8000786: b289 uxth r1, r1 + 8000788: 07d2 lsls r2, r2, #31 + 800078a: d501 bpl.n 8000790 + 800078c: 3101 adds r1, #1 + 800078e: b289 uxth r1, r1 + 8000790: 0289 lsls r1, r1, #10 + 8000792: 8019 strh r1, [r3, #0] + 8000794: e7dd b.n 8000752 + 8000796: 7823 ldrb r3, [r4, #0] + 8000798: 009b lsls r3, r3, #2 + 800079a: 6805 ldr r5, [r0, #0] + 800079c: 5aea ldrh r2, [r5, r3] + 800079e: 4954 ldr r1, [pc, #336] ; (80008f0 ) + 80007a0: 4011 ands r1, r2 + 80007a2: 4a54 ldr r2, [pc, #336] ; (80008f4 ) + 80007a4: 430a orrs r2, r1 + 80007a6: 52ea strh r2, [r5, r3] + 80007a8: 6802 ldr r2, [r0, #0] + 80007aa: 2650 movs r6, #80 ; 0x50 + 80007ac: 5b93 ldrh r3, [r2, r6] + 80007ae: 7821 ldrb r1, [r4, #0] + 80007b0: 00c9 lsls r1, r1, #3 + 80007b2: 1852 adds r2, r2, r1 + 80007b4: 189b adds r3, r3, r2 + 80007b6: 2280 movs r2, #128 ; 0x80 + 80007b8: 00d2 lsls r2, r2, #3 + 80007ba: 4694 mov ip, r2 + 80007bc: 4463 add r3, ip + 80007be: 88e2 ldrh r2, [r4, #6] + 80007c0: 2501 movs r5, #1 + 80007c2: 43aa bics r2, r5 + 80007c4: 801a strh r2, [r3, #0] + 80007c6: 6802 ldr r2, [r0, #0] + 80007c8: 5b93 ldrh r3, [r2, r6] + 80007ca: 7821 ldrb r1, [r4, #0] + 80007cc: 00c9 lsls r1, r1, #3 + 80007ce: 1852 adds r2, r2, r1 + 80007d0: 189b adds r3, r3, r2 + 80007d2: 4a42 ldr r2, [pc, #264] ; (80008dc ) + 80007d4: 4694 mov ip, r2 + 80007d6: 4463 add r3, ip + 80007d8: 8922 ldrh r2, [r4, #8] + 80007da: 43aa bics r2, r5 + 80007dc: 801a strh r2, [r3, #0] + 80007de: 7863 ldrb r3, [r4, #1] + 80007e0: 2b00 cmp r3, #0 + 80007e2: d135 bne.n 8000850 + 80007e4: 7823 ldrb r3, [r4, #0] + 80007e6: 009b lsls r3, r3, #2 + 80007e8: 6802 ldr r2, [r0, #0] + 80007ea: 18d1 adds r1, r2, r3 + 80007ec: 5ad3 ldrh r3, [r2, r3] + 80007ee: 045a lsls r2, r3, #17 + 80007f0: d504 bpl.n 80007fc + 80007f2: 4a36 ldr r2, [pc, #216] ; (80008cc ) + 80007f4: 4013 ands r3, r2 + 80007f6: 4a3c ldr r2, [pc, #240] ; (80008e8 ) + 80007f8: 4313 orrs r3, r2 + 80007fa: 800b strh r3, [r1, #0] + 80007fc: 7823 ldrb r3, [r4, #0] + 80007fe: 009b lsls r3, r3, #2 + 8000800: 6802 ldr r2, [r0, #0] + 8000802: 18d1 adds r1, r2, r3 + 8000804: 5ad3 ldrh r3, [r2, r3] + 8000806: 065a lsls r2, r3, #25 + 8000808: d504 bpl.n 8000814 + 800080a: 4a30 ldr r2, [pc, #192] ; (80008cc ) + 800080c: 4013 ands r3, r2 + 800080e: 4a31 ldr r2, [pc, #196] ; (80008d4 ) + 8000810: 4313 orrs r3, r2 + 8000812: 800b strh r3, [r1, #0] + 8000814: 7823 ldrb r3, [r4, #0] + 8000816: 009b lsls r3, r3, #2 + 8000818: 6805 ldr r5, [r0, #0] + 800081a: 5aea ldrh r2, [r5, r3] + 800081c: 492b ldr r1, [pc, #172] ; (80008cc ) + 800081e: 4011 ands r1, r2 + 8000820: 4a2c ldr r2, [pc, #176] ; (80008d4 ) + 8000822: 430a orrs r2, r1 + 8000824: 52ea strh r2, [r5, r3] + 8000826: 7821 ldrb r1, [r4, #0] + 8000828: 0089 lsls r1, r1, #2 + 800082a: 6805 ldr r5, [r0, #0] + 800082c: 5a6b ldrh r3, [r5, r1] + 800082e: 4a2f ldr r2, [pc, #188] ; (80008ec ) + 8000830: 401a ands r2, r3 + 8000832: 23c0 movs r3, #192 ; 0xc0 + 8000834: 019b lsls r3, r3, #6 + 8000836: 4053 eors r3, r2 + 8000838: 4a25 ldr r2, [pc, #148] ; (80008d0 ) + 800083a: 4313 orrs r3, r2 + 800083c: 526b strh r3, [r5, r1] + 800083e: 7823 ldrb r3, [r4, #0] + 8000840: 009b lsls r3, r3, #2 + 8000842: 6804 ldr r4, [r0, #0] + 8000844: 5ae1 ldrh r1, [r4, r3] + 8000846: 4d24 ldr r5, [pc, #144] ; (80008d8 ) + 8000848: 4029 ands r1, r5 + 800084a: 430a orrs r2, r1 + 800084c: 52e2 strh r2, [r4, r3] + 800084e: e74c b.n 80006ea + 8000850: 7823 ldrb r3, [r4, #0] + 8000852: 009b lsls r3, r3, #2 + 8000854: 6802 ldr r2, [r0, #0] + 8000856: 18d1 adds r1, r2, r3 + 8000858: 5ad3 ldrh r3, [r2, r3] + 800085a: 045a lsls r2, r3, #17 + 800085c: d504 bpl.n 8000868 + 800085e: 4a1b ldr r2, [pc, #108] ; (80008cc ) + 8000860: 4013 ands r3, r2 + 8000862: 4a21 ldr r2, [pc, #132] ; (80008e8 ) + 8000864: 4313 orrs r3, r2 + 8000866: 800b strh r3, [r1, #0] + 8000868: 7823 ldrb r3, [r4, #0] + 800086a: 009b lsls r3, r3, #2 + 800086c: 6802 ldr r2, [r0, #0] + 800086e: 18d1 adds r1, r2, r3 + 8000870: 5ad3 ldrh r3, [r2, r3] + 8000872: 065a lsls r2, r3, #25 + 8000874: d504 bpl.n 8000880 + 8000876: 4a15 ldr r2, [pc, #84] ; (80008cc ) + 8000878: 4013 ands r3, r2 + 800087a: 4a16 ldr r2, [pc, #88] ; (80008d4 ) + 800087c: 4313 orrs r3, r2 + 800087e: 800b strh r3, [r1, #0] + 8000880: 7823 ldrb r3, [r4, #0] + 8000882: 009b lsls r3, r3, #2 + 8000884: 6805 ldr r5, [r0, #0] + 8000886: 5aea ldrh r2, [r5, r3] + 8000888: 4910 ldr r1, [pc, #64] ; (80008cc ) + 800088a: 4011 ands r1, r2 + 800088c: 4a16 ldr r2, [pc, #88] ; (80008e8 ) + 800088e: 430a orrs r2, r1 + 8000890: 52ea strh r2, [r5, r3] + 8000892: 7821 ldrb r1, [r4, #0] + 8000894: 0089 lsls r1, r1, #2 + 8000896: 6805 ldr r5, [r0, #0] + 8000898: 5a6b ldrh r3, [r5, r1] + 800089a: 4a0f ldr r2, [pc, #60] ; (80008d8 ) + 800089c: 4013 ands r3, r2 + 800089e: 4a0c ldr r2, [pc, #48] ; (80008d0 ) + 80008a0: 4313 orrs r3, r2 + 80008a2: 526b strh r3, [r5, r1] + 80008a4: 7823 ldrb r3, [r4, #0] + 80008a6: 009b lsls r3, r3, #2 + 80008a8: 6804 ldr r4, [r0, #0] + 80008aa: 5ae1 ldrh r1, [r4, r3] + 80008ac: 4d0f ldr r5, [pc, #60] ; (80008ec ) + 80008ae: 4029 ands r1, r5 + 80008b0: 430a orrs r2, r1 + 80008b2: 52e2 strh r2, [r4, r3] + 80008b4: e719 b.n 80006ea + 80008b6: 2002 movs r0, #2 + 80008b8: e71c b.n 80006f4 + 80008ba: 46c0 nop ; (mov r8, r8) + 80008bc: 0000090f .word 0x0000090f + 80008c0: ffff8480 .word 0xffff8480 + 80008c4: ffff8680 .word 0xffff8680 + 80008c8: ffff8280 .word 0xffff8280 + 80008cc: 00000f0f .word 0x00000f0f + 80008d0: ffff8080 .word 0xffff8080 + 80008d4: ffff80c0 .word 0xffff80c0 + 80008d8: ffff8fbf .word 0xffff8fbf + 80008dc: 00000404 .word 0x00000404 + 80008e0: 00000406 .word 0x00000406 + 80008e4: ffff8000 .word 0xffff8000 + 80008e8: ffffc080 .word 0xffffc080 + 80008ec: ffffbf8f .word 0xffffbf8f + 80008f0: 00000e0f .word 0x00000e0f + 80008f4: ffff8180 .word 0xffff8180 + +080008f8 : + 80008f8: b530 push {r4, r5, lr} + 80008fa: 000c movs r4, r1 + 80008fc: b24a sxtb r2, r1 + 80008fe: 2a00 cmp r2, #0 + 8000900: db37 blt.n 8000972 + 8000902: 217f movs r1, #127 ; 0x7f + 8000904: 4021 ands r1, r4 + 8000906: 00cb lsls r3, r1, #3 + 8000908: 1a5b subs r3, r3, r1 + 800090a: 009b lsls r3, r3, #2 + 800090c: 3309 adds r3, #9 + 800090e: 33ff adds r3, #255 ; 0xff + 8000910: 18c3 adds r3, r0, r3 + 8000912: 217f movs r1, #127 ; 0x7f + 8000914: 4021 ands r1, r4 + 8000916: 7019 strb r1, [r3, #0] + 8000918: 0fd2 lsrs r2, r2, #31 + 800091a: 705a strb r2, [r3, #1] + 800091c: 22f4 movs r2, #244 ; 0xf4 + 800091e: 0052 lsls r2, r2, #1 + 8000920: 5c82 ldrb r2, [r0, r2] + 8000922: 2a01 cmp r2, #1 + 8000924: d100 bne.n 8000928 + 8000926: e0ab b.n 8000a80 + 8000928: 22f4 movs r2, #244 ; 0xf4 + 800092a: 0052 lsls r2, r2, #1 + 800092c: 2101 movs r1, #1 + 800092e: 5481 strb r1, [r0, r2] + 8000930: 7a9a ldrb r2, [r3, #10] + 8000932: 2a00 cmp r2, #0 + 8000934: d13b bne.n 80009ae + 8000936: 785a ldrb r2, [r3, #1] + 8000938: 2a00 cmp r2, #0 + 800093a: d022 beq.n 8000982 + 800093c: 781a ldrb r2, [r3, #0] + 800093e: 0092 lsls r2, r2, #2 + 8000940: 6801 ldr r1, [r0, #0] + 8000942: 188c adds r4, r1, r2 + 8000944: 5a8a ldrh r2, [r1, r2] + 8000946: 0651 lsls r1, r2, #25 + 8000948: d504 bpl.n 8000954 + 800094a: 494e ldr r1, [pc, #312] ; (8000a84 ) + 800094c: 400a ands r2, r1 + 800094e: 494e ldr r1, [pc, #312] ; (8000a88 ) + 8000950: 430a orrs r2, r1 + 8000952: 8022 strh r2, [r4, #0] + 8000954: 781b ldrb r3, [r3, #0] + 8000956: 009b lsls r3, r3, #2 + 8000958: 6804 ldr r4, [r0, #0] + 800095a: 5ae2 ldrh r2, [r4, r3] + 800095c: 494b ldr r1, [pc, #300] ; (8000a8c ) + 800095e: 4011 ands r1, r2 + 8000960: 4a4b ldr r2, [pc, #300] ; (8000a90 ) + 8000962: 430a orrs r2, r1 + 8000964: 52e2 strh r2, [r4, r3] + 8000966: 23f4 movs r3, #244 ; 0xf4 + 8000968: 005b lsls r3, r3, #1 + 800096a: 2200 movs r2, #0 + 800096c: 54c2 strb r2, [r0, r3] + 800096e: 2000 movs r0, #0 + 8000970: bd30 pop {r4, r5, pc} + 8000972: 217f movs r1, #127 ; 0x7f + 8000974: 4021 ands r1, r4 + 8000976: 00cb lsls r3, r1, #3 + 8000978: 1a5b subs r3, r3, r1 + 800097a: 009b lsls r3, r3, #2 + 800097c: 3328 adds r3, #40 ; 0x28 + 800097e: 18c3 adds r3, r0, r3 + 8000980: e7c7 b.n 8000912 + 8000982: 781a ldrb r2, [r3, #0] + 8000984: 0092 lsls r2, r2, #2 + 8000986: 6801 ldr r1, [r0, #0] + 8000988: 188c adds r4, r1, r2 + 800098a: 5a8a ldrh r2, [r1, r2] + 800098c: 0451 lsls r1, r2, #17 + 800098e: d504 bpl.n 800099a + 8000990: 493c ldr r1, [pc, #240] ; (8000a84 ) + 8000992: 400a ands r2, r1 + 8000994: 493f ldr r1, [pc, #252] ; (8000a94 ) + 8000996: 430a orrs r2, r1 + 8000998: 8022 strh r2, [r4, #0] + 800099a: 781b ldrb r3, [r3, #0] + 800099c: 009b lsls r3, r3, #2 + 800099e: 6804 ldr r4, [r0, #0] + 80009a0: 5ae2 ldrh r2, [r4, r3] + 80009a2: 493d ldr r1, [pc, #244] ; (8000a98 ) + 80009a4: 4011 ands r1, r2 + 80009a6: 4a3a ldr r2, [pc, #232] ; (8000a90 ) + 80009a8: 430a orrs r2, r1 + 80009aa: 52e2 strh r2, [r4, r3] + 80009ac: e7db b.n 8000966 + 80009ae: 785a ldrb r2, [r3, #1] + 80009b0: 2a00 cmp r2, #0 + 80009b2: d132 bne.n 8000a1a + 80009b4: 781a ldrb r2, [r3, #0] + 80009b6: 0092 lsls r2, r2, #2 + 80009b8: 6801 ldr r1, [r0, #0] + 80009ba: 188c adds r4, r1, r2 + 80009bc: 5a8a ldrh r2, [r1, r2] + 80009be: 0451 lsls r1, r2, #17 + 80009c0: d504 bpl.n 80009cc + 80009c2: 4930 ldr r1, [pc, #192] ; (8000a84 ) + 80009c4: 400a ands r2, r1 + 80009c6: 4933 ldr r1, [pc, #204] ; (8000a94 ) + 80009c8: 430a orrs r2, r1 + 80009ca: 8022 strh r2, [r4, #0] + 80009cc: 781a ldrb r2, [r3, #0] + 80009ce: 0092 lsls r2, r2, #2 + 80009d0: 6801 ldr r1, [r0, #0] + 80009d2: 188c adds r4, r1, r2 + 80009d4: 5a8a ldrh r2, [r1, r2] + 80009d6: 0651 lsls r1, r2, #25 + 80009d8: d504 bpl.n 80009e4 + 80009da: 492a ldr r1, [pc, #168] ; (8000a84 ) + 80009dc: 400a ands r2, r1 + 80009de: 492a ldr r1, [pc, #168] ; (8000a88 ) + 80009e0: 430a orrs r2, r1 + 80009e2: 8022 strh r2, [r4, #0] + 80009e4: 781a ldrb r2, [r3, #0] + 80009e6: 0092 lsls r2, r2, #2 + 80009e8: 6805 ldr r5, [r0, #0] + 80009ea: 5aa9 ldrh r1, [r5, r2] + 80009ec: 4c25 ldr r4, [pc, #148] ; (8000a84 ) + 80009ee: 400c ands r4, r1 + 80009f0: 4925 ldr r1, [pc, #148] ; (8000a88 ) + 80009f2: 4321 orrs r1, r4 + 80009f4: 52a9 strh r1, [r5, r2] + 80009f6: 781c ldrb r4, [r3, #0] + 80009f8: 00a4 lsls r4, r4, #2 + 80009fa: 6805 ldr r5, [r0, #0] + 80009fc: 5b2a ldrh r2, [r5, r4] + 80009fe: 4926 ldr r1, [pc, #152] ; (8000a98 ) + 8000a00: 400a ands r2, r1 + 8000a02: 4923 ldr r1, [pc, #140] ; (8000a90 ) + 8000a04: 430a orrs r2, r1 + 8000a06: 532a strh r2, [r5, r4] + 8000a08: 781b ldrb r3, [r3, #0] + 8000a0a: 009b lsls r3, r3, #2 + 8000a0c: 6804 ldr r4, [r0, #0] + 8000a0e: 5ae2 ldrh r2, [r4, r3] + 8000a10: 4d1e ldr r5, [pc, #120] ; (8000a8c ) + 8000a12: 402a ands r2, r5 + 8000a14: 4311 orrs r1, r2 + 8000a16: 52e1 strh r1, [r4, r3] + 8000a18: e7a5 b.n 8000966 + 8000a1a: 781a ldrb r2, [r3, #0] + 8000a1c: 0092 lsls r2, r2, #2 + 8000a1e: 6801 ldr r1, [r0, #0] + 8000a20: 188c adds r4, r1, r2 + 8000a22: 5a8a ldrh r2, [r1, r2] + 8000a24: 0451 lsls r1, r2, #17 + 8000a26: d504 bpl.n 8000a32 + 8000a28: 4916 ldr r1, [pc, #88] ; (8000a84 ) + 8000a2a: 400a ands r2, r1 + 8000a2c: 4919 ldr r1, [pc, #100] ; (8000a94 ) + 8000a2e: 430a orrs r2, r1 + 8000a30: 8022 strh r2, [r4, #0] + 8000a32: 781a ldrb r2, [r3, #0] + 8000a34: 0092 lsls r2, r2, #2 + 8000a36: 6801 ldr r1, [r0, #0] + 8000a38: 188c adds r4, r1, r2 + 8000a3a: 5a8a ldrh r2, [r1, r2] + 8000a3c: 0651 lsls r1, r2, #25 + 8000a3e: d504 bpl.n 8000a4a + 8000a40: 4910 ldr r1, [pc, #64] ; (8000a84 ) + 8000a42: 400a ands r2, r1 + 8000a44: 4910 ldr r1, [pc, #64] ; (8000a88 ) + 8000a46: 430a orrs r2, r1 + 8000a48: 8022 strh r2, [r4, #0] + 8000a4a: 781a ldrb r2, [r3, #0] + 8000a4c: 0092 lsls r2, r2, #2 + 8000a4e: 6805 ldr r5, [r0, #0] + 8000a50: 5aa9 ldrh r1, [r5, r2] + 8000a52: 4c0c ldr r4, [pc, #48] ; (8000a84 ) + 8000a54: 400c ands r4, r1 + 8000a56: 490f ldr r1, [pc, #60] ; (8000a94 ) + 8000a58: 4321 orrs r1, r4 + 8000a5a: 52a9 strh r1, [r5, r2] + 8000a5c: 781c ldrb r4, [r3, #0] + 8000a5e: 00a4 lsls r4, r4, #2 + 8000a60: 6805 ldr r5, [r0, #0] + 8000a62: 5b2a ldrh r2, [r5, r4] + 8000a64: 4909 ldr r1, [pc, #36] ; (8000a8c ) + 8000a66: 400a ands r2, r1 + 8000a68: 4909 ldr r1, [pc, #36] ; (8000a90 ) + 8000a6a: 430a orrs r2, r1 + 8000a6c: 532a strh r2, [r5, r4] + 8000a6e: 781b ldrb r3, [r3, #0] + 8000a70: 009b lsls r3, r3, #2 + 8000a72: 6804 ldr r4, [r0, #0] + 8000a74: 5ae2 ldrh r2, [r4, r3] + 8000a76: 4d08 ldr r5, [pc, #32] ; (8000a98 ) + 8000a78: 402a ands r2, r5 + 8000a7a: 4311 orrs r1, r2 + 8000a7c: 52e1 strh r1, [r4, r3] + 8000a7e: e772 b.n 8000966 + 8000a80: 2002 movs r0, #2 + 8000a82: e775 b.n 8000970 + 8000a84: 00000f0f .word 0x00000f0f + 8000a88: ffff80c0 .word 0xffff80c0 + 8000a8c: ffff8fbf .word 0xffff8fbf + 8000a90: ffff8080 .word 0xffff8080 + 8000a94: ffffc080 .word 0xffffc080 + 8000a98: ffffbf8f .word 0xffffbf8f + +08000a9c : + 8000a9c: b570 push {r4, r5, r6, lr} + 8000a9e: 247f movs r4, #127 ; 0x7f + 8000aa0: 4021 ands r1, r4 + 8000aa2: 00cc lsls r4, r1, #3 + 8000aa4: 1a64 subs r4, r4, r1 + 8000aa6: 00a4 lsls r4, r4, #2 + 8000aa8: 1904 adds r4, r0, r4 + 8000aaa: 0025 movs r5, r4 + 8000aac: 3519 adds r5, #25 + 8000aae: 35ff adds r5, #255 ; 0xff + 8000ab0: 602a str r2, [r5, #0] + 8000ab2: 0022 movs r2, r4 + 8000ab4: 321d adds r2, #29 + 8000ab6: 32ff adds r2, #255 ; 0xff + 8000ab8: 6013 str r3, [r2, #0] + 8000aba: 3508 adds r5, #8 + 8000abc: 2200 movs r2, #0 + 8000abe: 602a str r2, [r5, #0] + 8000ac0: 3d17 subs r5, #23 + 8000ac2: 702a strb r2, [r5, #0] + 8000ac4: 0022 movs r2, r4 + 8000ac6: 3209 adds r2, #9 + 8000ac8: 32ff adds r2, #255 ; 0xff + 8000aca: 7011 strb r1, [r2, #0] + 8000acc: 3415 adds r4, #21 + 8000ace: 34ff adds r4, #255 ; 0xff + 8000ad0: 6822 ldr r2, [r4, #0] + 8000ad2: 2400 movs r4, #0 + 8000ad4: 4293 cmp r3, r2 + 8000ad6: d901 bls.n 8000adc + 8000ad8: 1a9c subs r4, r3, r2 + 8000ada: 0013 movs r3, r2 + 8000adc: 00ca lsls r2, r1, #3 + 8000ade: 1a52 subs r2, r2, r1 + 8000ae0: 0092 lsls r2, r2, #2 + 8000ae2: 1882 adds r2, r0, r2 + 8000ae4: 0015 movs r5, r2 + 8000ae6: 351d adds r5, #29 + 8000ae8: 35ff adds r5, #255 ; 0xff + 8000aea: 602c str r4, [r5, #0] + 8000aec: 3213 adds r2, #19 + 8000aee: 32ff adds r2, #255 ; 0xff + 8000af0: 7812 ldrb r2, [r2, #0] + 8000af2: 2a00 cmp r2, #0 + 8000af4: d138 bne.n 8000b68 + 8000af6: 6804 ldr r4, [r0, #0] + 8000af8: 3250 adds r2, #80 ; 0x50 + 8000afa: 5aa5 ldrh r5, [r4, r2] + 8000afc: 00ca lsls r2, r1, #3 + 8000afe: 1a52 subs r2, r2, r1 + 8000b00: 0092 lsls r2, r2, #2 + 8000b02: 1882 adds r2, r0, r2 + 8000b04: 3209 adds r2, #9 + 8000b06: 32ff adds r2, #255 ; 0xff + 8000b08: 7812 ldrb r2, [r2, #0] + 8000b0a: 00d2 lsls r2, r2, #3 + 8000b0c: 18aa adds r2, r5, r2 + 8000b0e: 4d71 ldr r5, [pc, #452] ; (8000cd4 ) + 8000b10: 46ac mov ip, r5 + 8000b12: 4464 add r4, ip + 8000b14: 1914 adds r4, r2, r4 + 8000b16: 2b3e cmp r3, #62 ; 0x3e + 8000b18: d91d bls.n 8000b56 + 8000b1a: 095a lsrs r2, r3, #5 + 8000b1c: b292 uxth r2, r2 + 8000b1e: 06db lsls r3, r3, #27 + 8000b20: d101 bne.n 8000b26 + 8000b22: 3a01 subs r2, #1 + 8000b24: b292 uxth r2, r2 + 8000b26: 0292 lsls r2, r2, #10 + 8000b28: 4b6b ldr r3, [pc, #428] ; (8000cd8 ) + 8000b2a: 431a orrs r2, r3 + 8000b2c: 8022 strh r2, [r4, #0] + 8000b2e: 00cb lsls r3, r1, #3 + 8000b30: 1a59 subs r1, r3, r1 + 8000b32: 0089 lsls r1, r1, #2 + 8000b34: 1841 adds r1, r0, r1 + 8000b36: 3109 adds r1, #9 + 8000b38: 31ff adds r1, #255 ; 0xff + 8000b3a: 780b ldrb r3, [r1, #0] + 8000b3c: 009b lsls r3, r3, #2 + 8000b3e: 6800 ldr r0, [r0, #0] + 8000b40: 5ac1 ldrh r1, [r0, r3] + 8000b42: 4a66 ldr r2, [pc, #408] ; (8000cdc ) + 8000b44: 4011 ands r1, r2 + 8000b46: 22c0 movs r2, #192 ; 0xc0 + 8000b48: 0192 lsls r2, r2, #6 + 8000b4a: 4051 eors r1, r2 + 8000b4c: 4a64 ldr r2, [pc, #400] ; (8000ce0 ) + 8000b4e: 430a orrs r2, r1 + 8000b50: 52c2 strh r2, [r0, r3] + 8000b52: 2000 movs r0, #0 + 8000b54: bd70 pop {r4, r5, r6, pc} + 8000b56: 085a lsrs r2, r3, #1 + 8000b58: b292 uxth r2, r2 + 8000b5a: 07db lsls r3, r3, #31 + 8000b5c: d501 bpl.n 8000b62 + 8000b5e: 3201 adds r2, #1 + 8000b60: b292 uxth r2, r2 + 8000b62: 0292 lsls r2, r2, #10 + 8000b64: 8022 strh r2, [r4, #0] + 8000b66: e7e2 b.n 8000b2e + 8000b68: 00ca lsls r2, r1, #3 + 8000b6a: 1a52 subs r2, r2, r1 + 8000b6c: 0092 lsls r2, r2, #2 + 8000b6e: 1882 adds r2, r0, r2 + 8000b70: 320a adds r2, #10 + 8000b72: 32ff adds r2, #255 ; 0xff + 8000b74: 7812 ldrb r2, [r2, #0] + 8000b76: 2a00 cmp r2, #0 + 8000b78: d169 bne.n 8000c4e + 8000b7a: 6804 ldr r4, [r0, #0] + 8000b7c: 3250 adds r2, #80 ; 0x50 + 8000b7e: 5aa5 ldrh r5, [r4, r2] + 8000b80: 00ca lsls r2, r1, #3 + 8000b82: 1a52 subs r2, r2, r1 + 8000b84: 0092 lsls r2, r2, #2 + 8000b86: 1882 adds r2, r0, r2 + 8000b88: 3209 adds r2, #9 + 8000b8a: 32ff adds r2, #255 ; 0xff + 8000b8c: 7812 ldrb r2, [r2, #0] + 8000b8e: 00d2 lsls r2, r2, #3 + 8000b90: 18aa adds r2, r5, r2 + 8000b92: 4d54 ldr r5, [pc, #336] ; (8000ce4 ) + 8000b94: 46ac mov ip, r5 + 8000b96: 4464 add r4, ip + 8000b98: 1914 adds r4, r2, r4 + 8000b9a: 2b3e cmp r3, #62 ; 0x3e + 8000b9c: d92d bls.n 8000bfa + 8000b9e: 095a lsrs r2, r3, #5 + 8000ba0: b292 uxth r2, r2 + 8000ba2: 06dd lsls r5, r3, #27 + 8000ba4: d101 bne.n 8000baa + 8000ba6: 3a01 subs r2, #1 + 8000ba8: b292 uxth r2, r2 + 8000baa: 0292 lsls r2, r2, #10 + 8000bac: 4d4a ldr r5, [pc, #296] ; (8000cd8 ) + 8000bae: 432a orrs r2, r5 + 8000bb0: 8022 strh r2, [r4, #0] + 8000bb2: 00ca lsls r2, r1, #3 + 8000bb4: 1a52 subs r2, r2, r1 + 8000bb6: 0092 lsls r2, r2, #2 + 8000bb8: 1882 adds r2, r0, r2 + 8000bba: 320a adds r2, #10 + 8000bbc: 32ff adds r2, #255 ; 0xff + 8000bbe: 7812 ldrb r2, [r2, #0] + 8000bc0: 2a00 cmp r2, #0 + 8000bc2: d171 bne.n 8000ca8 + 8000bc4: 6805 ldr r5, [r0, #0] + 8000bc6: 2250 movs r2, #80 ; 0x50 + 8000bc8: 5aaa ldrh r2, [r5, r2] + 8000bca: 00cc lsls r4, r1, #3 + 8000bcc: 1a64 subs r4, r4, r1 + 8000bce: 00a4 lsls r4, r4, #2 + 8000bd0: 1904 adds r4, r0, r4 + 8000bd2: 3409 adds r4, #9 + 8000bd4: 34ff adds r4, #255 ; 0xff + 8000bd6: 7824 ldrb r4, [r4, #0] + 8000bd8: 00e4 lsls r4, r4, #3 + 8000bda: 1912 adds r2, r2, r4 + 8000bdc: 4c3d ldr r4, [pc, #244] ; (8000cd4 ) + 8000bde: 46a4 mov ip, r4 + 8000be0: 4465 add r5, ip + 8000be2: 1952 adds r2, r2, r5 + 8000be4: 095c lsrs r4, r3, #5 + 8000be6: b2a4 uxth r4, r4 + 8000be8: 06db lsls r3, r3, #27 + 8000bea: d101 bne.n 8000bf0 + 8000bec: 3c01 subs r4, #1 + 8000bee: b2a4 uxth r4, r4 + 8000bf0: 02a4 lsls r4, r4, #10 + 8000bf2: 4b39 ldr r3, [pc, #228] ; (8000cd8 ) + 8000bf4: 431c orrs r4, r3 + 8000bf6: 8014 strh r4, [r2, #0] + 8000bf8: e799 b.n 8000b2e + 8000bfa: 085a lsrs r2, r3, #1 + 8000bfc: b292 uxth r2, r2 + 8000bfe: 07dd lsls r5, r3, #31 + 8000c00: d501 bpl.n 8000c06 + 8000c02: 3201 adds r2, #1 + 8000c04: b292 uxth r2, r2 + 8000c06: 0292 lsls r2, r2, #10 + 8000c08: 8022 strh r2, [r4, #0] + 8000c0a: 00ca lsls r2, r1, #3 + 8000c0c: 1a52 subs r2, r2, r1 + 8000c0e: 0092 lsls r2, r2, #2 + 8000c10: 1882 adds r2, r0, r2 + 8000c12: 320a adds r2, #10 + 8000c14: 32ff adds r2, #255 ; 0xff + 8000c16: 7812 ldrb r2, [r2, #0] + 8000c18: 2a00 cmp r2, #0 + 8000c1a: d145 bne.n 8000ca8 + 8000c1c: 6805 ldr r5, [r0, #0] + 8000c1e: 2250 movs r2, #80 ; 0x50 + 8000c20: 5aaa ldrh r2, [r5, r2] + 8000c22: 00cc lsls r4, r1, #3 + 8000c24: 1a64 subs r4, r4, r1 + 8000c26: 00a4 lsls r4, r4, #2 + 8000c28: 1904 adds r4, r0, r4 + 8000c2a: 3409 adds r4, #9 + 8000c2c: 34ff adds r4, #255 ; 0xff + 8000c2e: 7824 ldrb r4, [r4, #0] + 8000c30: 00e4 lsls r4, r4, #3 + 8000c32: 1912 adds r2, r2, r4 + 8000c34: 4c27 ldr r4, [pc, #156] ; (8000cd4 ) + 8000c36: 46a4 mov ip, r4 + 8000c38: 4465 add r5, ip + 8000c3a: 1952 adds r2, r2, r5 + 8000c3c: 085c lsrs r4, r3, #1 + 8000c3e: b2a4 uxth r4, r4 + 8000c40: 07db lsls r3, r3, #31 + 8000c42: d501 bpl.n 8000c48 + 8000c44: 3401 adds r4, #1 + 8000c46: b2a4 uxth r4, r4 + 8000c48: 02a4 lsls r4, r4, #10 + 8000c4a: 8014 strh r4, [r2, #0] + 8000c4c: e76f b.n 8000b2e + 8000c4e: 2a01 cmp r2, #1 + 8000c50: d000 beq.n 8000c54 + 8000c52: e76c b.n 8000b2e + 8000c54: 6805 ldr r5, [r0, #0] + 8000c56: 324f adds r2, #79 ; 0x4f + 8000c58: 5aac ldrh r4, [r5, r2] + 8000c5a: 00ca lsls r2, r1, #3 + 8000c5c: 1a52 subs r2, r2, r1 + 8000c5e: 0092 lsls r2, r2, #2 + 8000c60: 1882 adds r2, r0, r2 + 8000c62: 0016 movs r6, r2 + 8000c64: 3609 adds r6, #9 + 8000c66: 36ff adds r6, #255 ; 0xff + 8000c68: 7836 ldrb r6, [r6, #0] + 8000c6a: 00f6 lsls r6, r6, #3 + 8000c6c: 19ad adds r5, r5, r6 + 8000c6e: 1964 adds r4, r4, r5 + 8000c70: 4d1c ldr r5, [pc, #112] ; (8000ce4 ) + 8000c72: 46ac mov ip, r5 + 8000c74: 4464 add r4, ip + 8000c76: 8023 strh r3, [r4, #0] + 8000c78: 320a adds r2, #10 + 8000c7a: 32ff adds r2, #255 ; 0xff + 8000c7c: 7812 ldrb r2, [r2, #0] + 8000c7e: 2a00 cmp r2, #0 + 8000c80: d112 bne.n 8000ca8 + 8000c82: 6805 ldr r5, [r0, #0] + 8000c84: 3250 adds r2, #80 ; 0x50 + 8000c86: 5aaa ldrh r2, [r5, r2] + 8000c88: 00cc lsls r4, r1, #3 + 8000c8a: 1a64 subs r4, r4, r1 + 8000c8c: 00a4 lsls r4, r4, #2 + 8000c8e: 1904 adds r4, r0, r4 + 8000c90: 3409 adds r4, #9 + 8000c92: 34ff adds r4, #255 ; 0xff + 8000c94: 7824 ldrb r4, [r4, #0] + 8000c96: 00e4 lsls r4, r4, #3 + 8000c98: 1912 adds r2, r2, r4 + 8000c9a: 4c0e ldr r4, [pc, #56] ; (8000cd4 ) + 8000c9c: 46a4 mov ip, r4 + 8000c9e: 4465 add r5, ip + 8000ca0: 1952 adds r2, r2, r5 + 8000ca2: 2b3e cmp r3, #62 ; 0x3e + 8000ca4: d89e bhi.n 8000be4 + 8000ca6: e7c9 b.n 8000c3c + 8000ca8: 2a01 cmp r2, #1 + 8000caa: d000 beq.n 8000cae + 8000cac: e73f b.n 8000b2e + 8000cae: 6804 ldr r4, [r0, #0] + 8000cb0: 324f adds r2, #79 ; 0x4f + 8000cb2: 5aa5 ldrh r5, [r4, r2] + 8000cb4: 00ca lsls r2, r1, #3 + 8000cb6: 1a52 subs r2, r2, r1 + 8000cb8: 0092 lsls r2, r2, #2 + 8000cba: 1882 adds r2, r0, r2 + 8000cbc: 3209 adds r2, #9 + 8000cbe: 32ff adds r2, #255 ; 0xff + 8000cc0: 7812 ldrb r2, [r2, #0] + 8000cc2: 00d2 lsls r2, r2, #3 + 8000cc4: 18a4 adds r4, r4, r2 + 8000cc6: 192c adds r4, r5, r4 + 8000cc8: 4a02 ldr r2, [pc, #8] ; (8000cd4 ) + 8000cca: 4694 mov ip, r2 + 8000ccc: 4464 add r4, ip + 8000cce: 8023 strh r3, [r4, #0] + 8000cd0: e72d b.n 8000b2e + 8000cd2: 46c0 nop ; (mov r8, r8) + 8000cd4: 00000406 .word 0x00000406 + 8000cd8: ffff8000 .word 0xffff8000 + 8000cdc: ffffbf8f .word 0xffffbf8f + 8000ce0: ffff8080 .word 0xffff8080 + 8000ce4: 00000402 .word 0x00000402 + +08000ce8 : + 8000ce8: 000b movs r3, r1 + 8000cea: 217f movs r1, #127 ; 0x7f + 8000cec: 4019 ands r1, r3 + 8000cee: 00cb lsls r3, r1, #3 + 8000cf0: 1a59 subs r1, r3, r1 + 8000cf2: 0089 lsls r1, r1, #2 + 8000cf4: 1840 adds r0, r0, r1 + 8000cf6: 3021 adds r0, #33 ; 0x21 + 8000cf8: 30ff adds r0, #255 ; 0xff + 8000cfa: 8800 ldrh r0, [r0, #0] + 8000cfc: 4770 bx lr + ... + +08000d00 : + 8000d00: b530 push {r4, r5, lr} + 8000d02: 23f4 movs r3, #244 ; 0xf4 + 8000d04: 005b lsls r3, r3, #1 + 8000d06: 5cc3 ldrb r3, [r0, r3] + 8000d08: 2b01 cmp r3, #1 + 8000d0a: d052 beq.n 8000db2 + 8000d0c: 23f4 movs r3, #244 ; 0xf4 + 8000d0e: 005b lsls r3, r3, #1 + 8000d10: 2201 movs r2, #1 + 8000d12: 54c2 strb r2, [r0, r3] + 8000d14: b24b sxtb r3, r1 + 8000d16: 2b00 cmp r3, #0 + 8000d18: db25 blt.n 8000d66 + 8000d1a: 00cb lsls r3, r1, #3 + 8000d1c: 1a5a subs r2, r3, r1 + 8000d1e: 0092 lsls r2, r2, #2 + 8000d20: 1882 adds r2, r0, r2 + 8000d22: 0014 movs r4, r2 + 8000d24: 340b adds r4, #11 + 8000d26: 34ff adds r4, #255 ; 0xff + 8000d28: 2501 movs r5, #1 + 8000d2a: 7025 strb r5, [r4, #0] + 8000d2c: 247f movs r4, #127 ; 0x7f + 8000d2e: 400c ands r4, r1 + 8000d30: 3209 adds r2, #9 + 8000d32: 32ff adds r2, #255 ; 0xff + 8000d34: 7014 strb r4, [r2, #0] + 8000d36: 1a59 subs r1, r3, r1 + 8000d38: 0089 lsls r1, r1, #2 + 8000d3a: 1841 adds r1, r0, r1 + 8000d3c: 310a adds r1, #10 + 8000d3e: 31ff adds r1, #255 ; 0xff + 8000d40: 2300 movs r3, #0 + 8000d42: 700b strb r3, [r1, #0] + 8000d44: 2c00 cmp r4, #0 + 8000d46: d128 bne.n 8000d9a + 8000d48: 6801 ldr r1, [r0, #0] + 8000d4a: 880a ldrh r2, [r1, #0] + 8000d4c: 4b1a ldr r3, [pc, #104] ; (8000db8 ) + 8000d4e: 401a ands r2, r3 + 8000d50: 4b1a ldr r3, [pc, #104] ; (8000dbc ) + 8000d52: 405a eors r2, r3 + 8000d54: 4b1a ldr r3, [pc, #104] ; (8000dc0 ) + 8000d56: 4313 orrs r3, r2 + 8000d58: 800b strh r3, [r1, #0] + 8000d5a: 23f4 movs r3, #244 ; 0xf4 + 8000d5c: 005b lsls r3, r3, #1 + 8000d5e: 2200 movs r2, #0 + 8000d60: 54c2 strb r2, [r0, r3] + 8000d62: 2000 movs r0, #0 + 8000d64: bd30 pop {r4, r5, pc} + 8000d66: 237f movs r3, #127 ; 0x7f + 8000d68: 4019 ands r1, r3 + 8000d6a: 00cb lsls r3, r1, #3 + 8000d6c: 1a5b subs r3, r3, r1 + 8000d6e: 009b lsls r3, r3, #2 + 8000d70: 18c3 adds r3, r0, r3 + 8000d72: 001c movs r4, r3 + 8000d74: 342a adds r4, #42 ; 0x2a + 8000d76: 7022 strb r2, [r4, #0] + 8000d78: 3c02 subs r4, #2 + 8000d7a: 7021 strb r1, [r4, #0] + 8000d7c: 3329 adds r3, #41 ; 0x29 + 8000d7e: 701a strb r2, [r3, #0] + 8000d80: 2900 cmp r1, #0 + 8000d82: d0e1 beq.n 8000d48 + 8000d84: 0089 lsls r1, r1, #2 + 8000d86: 6804 ldr r4, [r0, #0] + 8000d88: 5a63 ldrh r3, [r4, r1] + 8000d8a: 4a0e ldr r2, [pc, #56] ; (8000dc4 ) + 8000d8c: 4013 ands r3, r2 + 8000d8e: 2210 movs r2, #16 + 8000d90: 4053 eors r3, r2 + 8000d92: 4a0b ldr r2, [pc, #44] ; (8000dc0 ) + 8000d94: 4313 orrs r3, r2 + 8000d96: 5263 strh r3, [r4, r1] + 8000d98: e7df b.n 8000d5a + 8000d9a: 00a4 lsls r4, r4, #2 + 8000d9c: 6801 ldr r1, [r0, #0] + 8000d9e: 5b0a ldrh r2, [r1, r4] + 8000da0: 4b09 ldr r3, [pc, #36] ; (8000dc8 ) + 8000da2: 401a ands r2, r3 + 8000da4: 2380 movs r3, #128 ; 0x80 + 8000da6: 015b lsls r3, r3, #5 + 8000da8: 405a eors r2, r3 + 8000daa: 4b05 ldr r3, [pc, #20] ; (8000dc0 ) + 8000dac: 4313 orrs r3, r2 + 8000dae: 530b strh r3, [r1, r4] + 8000db0: e7d3 b.n 8000d5a + 8000db2: 2002 movs r0, #2 + 8000db4: e7d6 b.n 8000d64 + 8000db6: 46c0 nop ; (mov r8, r8) + 8000db8: ffffbfbf .word 0xffffbfbf + 8000dbc: 00001010 .word 0x00001010 + 8000dc0: ffff8080 .word 0xffff8080 + 8000dc4: ffff8fbf .word 0xffff8fbf + 8000dc8: ffffbf8f .word 0xffffbf8f + +08000dcc : + 8000dcc: b510 push {r4, lr} + 8000dce: 000c movs r4, r1 + 8000dd0: b24a sxtb r2, r1 + 8000dd2: 2a00 cmp r2, #0 + 8000dd4: db35 blt.n 8000e42 + 8000dd6: 00cb lsls r3, r1, #3 + 8000dd8: 1a5b subs r3, r3, r1 + 8000dda: 009b lsls r3, r3, #2 + 8000ddc: 3309 adds r3, #9 + 8000dde: 33ff adds r3, #255 ; 0xff + 8000de0: 18c3 adds r3, r0, r3 + 8000de2: 2100 movs r1, #0 + 8000de4: 7099 strb r1, [r3, #2] + 8000de6: 317f adds r1, #127 ; 0x7f + 8000de8: 4021 ands r1, r4 + 8000dea: 7019 strb r1, [r3, #0] + 8000dec: 0fd2 lsrs r2, r2, #31 + 8000dee: 705a strb r2, [r3, #1] + 8000df0: 22f4 movs r2, #244 ; 0xf4 + 8000df2: 0052 lsls r2, r2, #1 + 8000df4: 5c82 ldrb r2, [r0, r2] + 8000df6: 2a01 cmp r2, #1 + 8000df8: d044 beq.n 8000e84 + 8000dfa: 22f4 movs r2, #244 ; 0xf4 + 8000dfc: 0052 lsls r2, r2, #1 + 8000dfe: 2101 movs r1, #1 + 8000e00: 5481 strb r1, [r0, r2] + 8000e02: 785a ldrb r2, [r3, #1] + 8000e04: 2a00 cmp r2, #0 + 8000e06: d024 beq.n 8000e52 + 8000e08: 781a ldrb r2, [r3, #0] + 8000e0a: 0092 lsls r2, r2, #2 + 8000e0c: 6801 ldr r1, [r0, #0] + 8000e0e: 188c adds r4, r1, r2 + 8000e10: 5a8a ldrh r2, [r1, r2] + 8000e12: 0651 lsls r1, r2, #25 + 8000e14: d504 bpl.n 8000e20 + 8000e16: 491c ldr r1, [pc, #112] ; (8000e88 ) + 8000e18: 400a ands r2, r1 + 8000e1a: 491c ldr r1, [pc, #112] ; (8000e8c ) + 8000e1c: 430a orrs r2, r1 + 8000e1e: 8022 strh r2, [r4, #0] + 8000e20: 781a ldrb r2, [r3, #0] + 8000e22: 0092 lsls r2, r2, #2 + 8000e24: 6804 ldr r4, [r0, #0] + 8000e26: 5aa3 ldrh r3, [r4, r2] + 8000e28: 4919 ldr r1, [pc, #100] ; (8000e90 ) + 8000e2a: 400b ands r3, r1 + 8000e2c: 2130 movs r1, #48 ; 0x30 + 8000e2e: 404b eors r3, r1 + 8000e30: 4918 ldr r1, [pc, #96] ; (8000e94 ) + 8000e32: 430b orrs r3, r1 + 8000e34: 52a3 strh r3, [r4, r2] + 8000e36: 23f4 movs r3, #244 ; 0xf4 + 8000e38: 005b lsls r3, r3, #1 + 8000e3a: 2200 movs r2, #0 + 8000e3c: 54c2 strb r2, [r0, r3] + 8000e3e: 2000 movs r0, #0 + 8000e40: bd10 pop {r4, pc} + 8000e42: 217f movs r1, #127 ; 0x7f + 8000e44: 4021 ands r1, r4 + 8000e46: 00cb lsls r3, r1, #3 + 8000e48: 1a5b subs r3, r3, r1 + 8000e4a: 009b lsls r3, r3, #2 + 8000e4c: 3328 adds r3, #40 ; 0x28 + 8000e4e: 18c3 adds r3, r0, r3 + 8000e50: e7c7 b.n 8000de2 + 8000e52: 781a ldrb r2, [r3, #0] + 8000e54: 0092 lsls r2, r2, #2 + 8000e56: 6801 ldr r1, [r0, #0] + 8000e58: 188c adds r4, r1, r2 + 8000e5a: 5a8a ldrh r2, [r1, r2] + 8000e5c: 0451 lsls r1, r2, #17 + 8000e5e: d504 bpl.n 8000e6a + 8000e60: 4909 ldr r1, [pc, #36] ; (8000e88 ) + 8000e62: 400a ands r2, r1 + 8000e64: 490c ldr r1, [pc, #48] ; (8000e98 ) + 8000e66: 430a orrs r2, r1 + 8000e68: 8022 strh r2, [r4, #0] + 8000e6a: 781b ldrb r3, [r3, #0] + 8000e6c: 009b lsls r3, r3, #2 + 8000e6e: 6804 ldr r4, [r0, #0] + 8000e70: 5ae1 ldrh r1, [r4, r3] + 8000e72: 4a0a ldr r2, [pc, #40] ; (8000e9c ) + 8000e74: 4011 ands r1, r2 + 8000e76: 22c0 movs r2, #192 ; 0xc0 + 8000e78: 0192 lsls r2, r2, #6 + 8000e7a: 4051 eors r1, r2 + 8000e7c: 4a05 ldr r2, [pc, #20] ; (8000e94 ) + 8000e7e: 430a orrs r2, r1 + 8000e80: 52e2 strh r2, [r4, r3] + 8000e82: e7d8 b.n 8000e36 + 8000e84: 2002 movs r0, #2 + 8000e86: e7db b.n 8000e40 + 8000e88: 00000f0f .word 0x00000f0f + 8000e8c: ffff80c0 .word 0xffff80c0 + 8000e90: ffff8fbf .word 0xffff8fbf + 8000e94: ffff8080 .word 0xffff8080 + 8000e98: ffffc080 .word 0xffffc080 + 8000e9c: ffffbf8f .word 0xffffbf8f + +08000ea0 : + 8000ea0: b510 push {r4, lr} + 8000ea2: 1c5c adds r4, r3, #1 + 8000ea4: 0864 lsrs r4, r4, #1 + 8000ea6: 2380 movs r3, #128 ; 0x80 + 8000ea8: 00db lsls r3, r3, #3 + 8000eaa: 469c mov ip, r3 + 8000eac: 4460 add r0, ip + 8000eae: 1880 adds r0, r0, r2 + 8000eb0: 2c00 cmp r4, #0 + 8000eb2: d00b beq.n 8000ecc + 8000eb4: 0064 lsls r4, r4, #1 + 8000eb6: 190c adds r4, r1, r4 + 8000eb8: 000b movs r3, r1 + 8000eba: 1a40 subs r0, r0, r1 + 8000ebc: 7859 ldrb r1, [r3, #1] + 8000ebe: 0209 lsls r1, r1, #8 + 8000ec0: 781a ldrb r2, [r3, #0] + 8000ec2: 430a orrs r2, r1 + 8000ec4: 52c2 strh r2, [r0, r3] + 8000ec6: 3302 adds r3, #2 + 8000ec8: 429c cmp r4, r3 + 8000eca: d1f7 bne.n 8000ebc + 8000ecc: bd10 pop {r4, pc} + ... + +08000ed0 : + 8000ed0: b5f8 push {r3, r4, r5, r6, r7, lr} + 8000ed2: 0005 movs r5, r0 + 8000ed4: 247f movs r4, #127 ; 0x7f + 8000ed6: 400c ands r4, r1 + 8000ed8: 00e1 lsls r1, r4, #3 + 8000eda: 1b09 subs r1, r1, r4 + 8000edc: 0089 lsls r1, r1, #2 + 8000ede: 1841 adds r1, r0, r1 + 8000ee0: 638a str r2, [r1, #56] ; 0x38 + 8000ee2: 63cb str r3, [r1, #60] ; 0x3c + 8000ee4: 2200 movs r2, #0 + 8000ee6: 640a str r2, [r1, #64] ; 0x40 + 8000ee8: 000a movs r2, r1 + 8000eea: 3229 adds r2, #41 ; 0x29 + 8000eec: 2001 movs r0, #1 + 8000eee: 7010 strb r0, [r2, #0] + 8000ef0: 3a01 subs r2, #1 + 8000ef2: 7014 strb r4, [r2, #0] + 8000ef4: 6b4a ldr r2, [r1, #52] ; 0x34 + 8000ef6: 2100 movs r1, #0 + 8000ef8: 4293 cmp r3, r2 + 8000efa: d901 bls.n 8000f00 + 8000efc: 1a99 subs r1, r3, r2 + 8000efe: 0013 movs r3, r2 + 8000f00: 00e2 lsls r2, r4, #3 + 8000f02: 1b12 subs r2, r2, r4 + 8000f04: 0092 lsls r2, r2, #2 + 8000f06: 18aa adds r2, r5, r2 + 8000f08: 63d1 str r1, [r2, #60] ; 0x3c + 8000f0a: 3232 adds r2, #50 ; 0x32 + 8000f0c: 7812 ldrb r2, [r2, #0] + 8000f0e: 2a00 cmp r2, #0 + 8000f10: d028 beq.n 8000f64 + 8000f12: 6829 ldr r1, [r5, #0] + 8000f14: 00e2 lsls r2, r4, #3 + 8000f16: 1b12 subs r2, r2, r4 + 8000f18: 0092 lsls r2, r2, #2 + 8000f1a: 18aa adds r2, r5, r2 + 8000f1c: 3228 adds r2, #40 ; 0x28 + 8000f1e: 7810 ldrb r0, [r2, #0] + 8000f20: 0082 lsls r2, r0, #2 + 8000f22: 5a52 ldrh r2, [r2, r1] + 8000f24: 0652 lsls r2, r2, #25 + 8000f26: d400 bmi.n 8000f2a + 8000f28: e07b b.n 8001022 + 8000f2a: 00e2 lsls r2, r4, #3 + 8000f2c: 1b12 subs r2, r2, r4 + 8000f2e: 0092 lsls r2, r2, #2 + 8000f30: 18aa adds r2, r5, r2 + 8000f32: 3229 adds r2, #41 ; 0x29 + 8000f34: 7812 ldrb r2, [r2, #0] + 8000f36: 2a00 cmp r2, #0 + 8000f38: d135 bne.n 8000fa6 + 8000f3a: 3250 adds r2, #80 ; 0x50 + 8000f3c: 5a8a ldrh r2, [r1, r2] + 8000f3e: 00c0 lsls r0, r0, #3 + 8000f40: 1810 adds r0, r2, r0 + 8000f42: 4a5c ldr r2, [pc, #368] ; (80010b4 ) + 8000f44: 4694 mov ip, r2 + 8000f46: 4461 add r1, ip + 8000f48: 1840 adds r0, r0, r1 + 8000f4a: 2b3e cmp r3, #62 ; 0x3e + 8000f4c: d922 bls.n 8000f94 + 8000f4e: 095a lsrs r2, r3, #5 + 8000f50: b292 uxth r2, r2 + 8000f52: 06d9 lsls r1, r3, #27 + 8000f54: d101 bne.n 8000f5a + 8000f56: 3a01 subs r2, #1 + 8000f58: b292 uxth r2, r2 + 8000f5a: 0292 lsls r2, r2, #10 + 8000f5c: 4956 ldr r1, [pc, #344] ; (80010b8 ) + 8000f5e: 430a orrs r2, r1 + 8000f60: 8002 strh r2, [r0, #0] + 8000f62: e022 b.n 8000faa + 8000f64: b29f uxth r7, r3 + 8000f66: 00e6 lsls r6, r4, #3 + 8000f68: 1b36 subs r6, r6, r4 + 8000f6a: 00b6 lsls r6, r6, #2 + 8000f6c: 19ae adds r6, r5, r6 + 8000f6e: 8db2 ldrh r2, [r6, #44] ; 0x2c + 8000f70: 003b movs r3, r7 + 8000f72: 6bb1 ldr r1, [r6, #56] ; 0x38 + 8000f74: 6828 ldr r0, [r5, #0] + 8000f76: f7ff ff93 bl 8000ea0 + 8000f7a: 682a ldr r2, [r5, #0] + 8000f7c: 2350 movs r3, #80 ; 0x50 + 8000f7e: 5ad3 ldrh r3, [r2, r3] + 8000f80: 3628 adds r6, #40 ; 0x28 + 8000f82: 7831 ldrb r1, [r6, #0] + 8000f84: 00c9 lsls r1, r1, #3 + 8000f86: 1852 adds r2, r2, r1 + 8000f88: 189b adds r3, r3, r2 + 8000f8a: 4a4c ldr r2, [pc, #304] ; (80010bc ) + 8000f8c: 4694 mov ip, r2 + 8000f8e: 4463 add r3, ip + 8000f90: 801f strh r7, [r3, #0] + 8000f92: e02a b.n 8000fea + 8000f94: 085a lsrs r2, r3, #1 + 8000f96: b292 uxth r2, r2 + 8000f98: 07d9 lsls r1, r3, #31 + 8000f9a: d501 bpl.n 8000fa0 + 8000f9c: 3201 adds r2, #1 + 8000f9e: b292 uxth r2, r2 + 8000fa0: 0292 lsls r2, r2, #10 + 8000fa2: 8002 strh r2, [r0, #0] + 8000fa4: e001 b.n 8000faa + 8000fa6: 2a01 cmp r2, #1 + 8000fa8: d031 beq.n 800100e + 8000faa: 00e2 lsls r2, r4, #3 + 8000fac: 1b12 subs r2, r2, r4 + 8000fae: 0092 lsls r2, r2, #2 + 8000fb0: 18aa adds r2, r5, r2 + 8000fb2: 8e12 ldrh r2, [r2, #48] ; 0x30 + 8000fb4: b29b uxth r3, r3 + 8000fb6: 00e6 lsls r6, r4, #3 + 8000fb8: 1b36 subs r6, r6, r4 + 8000fba: 00b6 lsls r6, r6, #2 + 8000fbc: 19ae adds r6, r5, r6 + 8000fbe: 6bb1 ldr r1, [r6, #56] ; 0x38 + 8000fc0: 6828 ldr r0, [r5, #0] + 8000fc2: f7ff ff6d bl 8000ea0 + 8000fc6: 3629 adds r6, #41 ; 0x29 + 8000fc8: 7833 ldrb r3, [r6, #0] + 8000fca: 2b00 cmp r3, #0 + 8000fcc: d161 bne.n 8001092 + 8000fce: 00e3 lsls r3, r4, #3 + 8000fd0: 1b1b subs r3, r3, r4 + 8000fd2: 009b lsls r3, r3, #2 + 8000fd4: 18eb adds r3, r5, r3 + 8000fd6: 3328 adds r3, #40 ; 0x28 + 8000fd8: 781b ldrb r3, [r3, #0] + 8000fda: 009b lsls r3, r3, #2 + 8000fdc: 6828 ldr r0, [r5, #0] + 8000fde: 5ac2 ldrh r2, [r0, r3] + 8000fe0: 4937 ldr r1, [pc, #220] ; (80010c0 ) + 8000fe2: 4011 ands r1, r2 + 8000fe4: 4a37 ldr r2, [pc, #220] ; (80010c4 ) + 8000fe6: 430a orrs r2, r1 + 8000fe8: 52c2 strh r2, [r0, r3] + 8000fea: 00e1 lsls r1, r4, #3 + 8000fec: 1b0c subs r4, r1, r4 + 8000fee: 00a4 lsls r4, r4, #2 + 8000ff0: 192c adds r4, r5, r4 + 8000ff2: 3428 adds r4, #40 ; 0x28 + 8000ff4: 7822 ldrb r2, [r4, #0] + 8000ff6: 0092 lsls r2, r2, #2 + 8000ff8: 6828 ldr r0, [r5, #0] + 8000ffa: 5a83 ldrh r3, [r0, r2] + 8000ffc: 4932 ldr r1, [pc, #200] ; (80010c8 ) + 8000ffe: 400b ands r3, r1 + 8001000: 2130 movs r1, #48 ; 0x30 + 8001002: 404b eors r3, r1 + 8001004: 4931 ldr r1, [pc, #196] ; (80010cc ) + 8001006: 430b orrs r3, r1 + 8001008: 5283 strh r3, [r0, r2] + 800100a: 2000 movs r0, #0 + 800100c: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800100e: 324f adds r2, #79 ; 0x4f + 8001010: 5a8a ldrh r2, [r1, r2] + 8001012: 00c0 lsls r0, r0, #3 + 8001014: 1809 adds r1, r1, r0 + 8001016: 1851 adds r1, r2, r1 + 8001018: 4a26 ldr r2, [pc, #152] ; (80010b4 ) + 800101a: 4694 mov ip, r2 + 800101c: 4461 add r1, ip + 800101e: 800b strh r3, [r1, #0] + 8001020: e7c3 b.n 8000faa + 8001022: 00e2 lsls r2, r4, #3 + 8001024: 1b12 subs r2, r2, r4 + 8001026: 0092 lsls r2, r2, #2 + 8001028: 18aa adds r2, r5, r2 + 800102a: 3229 adds r2, #41 ; 0x29 + 800102c: 7812 ldrb r2, [r2, #0] + 800102e: 2a00 cmp r2, #0 + 8001030: d11d bne.n 800106e + 8001032: 3250 adds r2, #80 ; 0x50 + 8001034: 5a8a ldrh r2, [r1, r2] + 8001036: 00c0 lsls r0, r0, #3 + 8001038: 1810 adds r0, r2, r0 + 800103a: 4a20 ldr r2, [pc, #128] ; (80010bc ) + 800103c: 4694 mov ip, r2 + 800103e: 4461 add r1, ip + 8001040: 1840 adds r0, r0, r1 + 8001042: 2b3e cmp r3, #62 ; 0x3e + 8001044: d90a bls.n 800105c + 8001046: 095a lsrs r2, r3, #5 + 8001048: b292 uxth r2, r2 + 800104a: 06d9 lsls r1, r3, #27 + 800104c: d101 bne.n 8001052 + 800104e: 3a01 subs r2, #1 + 8001050: b292 uxth r2, r2 + 8001052: 0292 lsls r2, r2, #10 + 8001054: 4918 ldr r1, [pc, #96] ; (80010b8 ) + 8001056: 430a orrs r2, r1 + 8001058: 8002 strh r2, [r0, #0] + 800105a: e00a b.n 8001072 + 800105c: 085a lsrs r2, r3, #1 + 800105e: b292 uxth r2, r2 + 8001060: 07d9 lsls r1, r3, #31 + 8001062: d501 bpl.n 8001068 + 8001064: 3201 adds r2, #1 + 8001066: b292 uxth r2, r2 + 8001068: 0292 lsls r2, r2, #10 + 800106a: 8002 strh r2, [r0, #0] + 800106c: e001 b.n 8001072 + 800106e: 2a01 cmp r2, #1 + 8001070: d005 beq.n 800107e + 8001072: 00e2 lsls r2, r4, #3 + 8001074: 1b12 subs r2, r2, r4 + 8001076: 0092 lsls r2, r2, #2 + 8001078: 18aa adds r2, r5, r2 + 800107a: 8dd2 ldrh r2, [r2, #46] ; 0x2e + 800107c: e79a b.n 8000fb4 + 800107e: 324f adds r2, #79 ; 0x4f + 8001080: 5a8a ldrh r2, [r1, r2] + 8001082: 00c0 lsls r0, r0, #3 + 8001084: 1809 adds r1, r1, r0 + 8001086: 1851 adds r1, r2, r1 + 8001088: 4a0c ldr r2, [pc, #48] ; (80010bc ) + 800108a: 4694 mov ip, r2 + 800108c: 4461 add r1, ip + 800108e: 800b strh r3, [r1, #0] + 8001090: e7ef b.n 8001072 + 8001092: 2b01 cmp r3, #1 + 8001094: d1a9 bne.n 8000fea + 8001096: 00e3 lsls r3, r4, #3 + 8001098: 1b1b subs r3, r3, r4 + 800109a: 009b lsls r3, r3, #2 + 800109c: 18eb adds r3, r5, r3 + 800109e: 3328 adds r3, #40 ; 0x28 + 80010a0: 781b ldrb r3, [r3, #0] + 80010a2: 009b lsls r3, r3, #2 + 80010a4: 6828 ldr r0, [r5, #0] + 80010a6: 5ac2 ldrh r2, [r0, r3] + 80010a8: 4905 ldr r1, [pc, #20] ; (80010c0 ) + 80010aa: 4011 ands r1, r2 + 80010ac: 4a08 ldr r2, [pc, #32] ; (80010d0 ) + 80010ae: 430a orrs r2, r1 + 80010b0: 52c2 strh r2, [r0, r3] + 80010b2: e79a b.n 8000fea + 80010b4: 00000406 .word 0x00000406 + 80010b8: ffff8000 .word 0xffff8000 + 80010bc: 00000402 .word 0x00000402 + 80010c0: 00000f0f .word 0x00000f0f + 80010c4: ffff80c0 .word 0xffff80c0 + 80010c8: ffff8fbf .word 0xffff8fbf + 80010cc: ffff8080 .word 0xffff8080 + 80010d0: ffffc080 .word 0xffffc080 + +080010d4 : + 80010d4: b5f0 push {r4, r5, r6, r7, lr} + 80010d6: 46c6 mov lr, r8 + 80010d8: b500 push {lr} + 80010da: 469c mov ip, r3 + 80010dc: 085b lsrs r3, r3, #1 + 80010de: 2480 movs r4, #128 ; 0x80 + 80010e0: 00e4 lsls r4, r4, #3 + 80010e2: 46a0 mov r8, r4 + 80010e4: 4440 add r0, r8 + 80010e6: 1882 adds r2, r0, r2 + 80010e8: 0010 movs r0, r2 + 80010ea: 2b00 cmp r3, #0 + 80010ec: d00d beq.n 800110a + 80010ee: 000c movs r4, r1 + 80010f0: 001e movs r6, r3 + 80010f2: 1a57 subs r7, r2, r1 + 80010f4: 5b3d ldrh r5, [r7, r4] + 80010f6: 7025 strb r5, [r4, #0] + 80010f8: 0a2d lsrs r5, r5, #8 + 80010fa: 7065 strb r5, [r4, #1] + 80010fc: 3e01 subs r6, #1 + 80010fe: 3402 adds r4, #2 + 8001100: 2e00 cmp r6, #0 + 8001102: d1f7 bne.n 80010f4 + 8001104: 005b lsls r3, r3, #1 + 8001106: 18d0 adds r0, r2, r3 + 8001108: 18c9 adds r1, r1, r3 + 800110a: 4663 mov r3, ip + 800110c: 07db lsls r3, r3, #31 + 800110e: d501 bpl.n 8001114 + 8001110: 8803 ldrh r3, [r0, #0] + 8001112: 700b strb r3, [r1, #0] + 8001114: bc80 pop {r7} + 8001116: 46b8 mov r8, r7 + 8001118: bdf0 pop {r4, r5, r6, r7, pc} + ... + +0800111c : + 800111c: b5f0 push {r4, r5, r6, r7, lr} + 800111e: 46d6 mov lr, sl + 8001120: 464f mov r7, r9 + 8001122: 4646 mov r6, r8 + 8001124: b5c0 push {r6, r7, lr} + 8001126: b082 sub sp, #8 + 8001128: 0004 movs r4, r0 + 800112a: 6800 ldr r0, [r0, #0] + 800112c: 2344 movs r3, #68 ; 0x44 + 800112e: 5ac3 ldrh r3, [r0, r3] + 8001130: b21b sxth r3, r3 + 8001132: 2b00 cmp r3, #0 + 8001134: db4f blt.n 80011d6 + 8001136: 6823 ldr r3, [r4, #0] + 8001138: 2244 movs r2, #68 ; 0x44 + 800113a: 5a9a ldrh r2, [r3, r2] + 800113c: 0552 lsls r2, r2, #21 + 800113e: d500 bpl.n 8001142 + 8001140: e2a0 b.n 8001684 + 8001142: 6823 ldr r3, [r4, #0] + 8001144: 2244 movs r2, #68 ; 0x44 + 8001146: 5a9a ldrh r2, [r3, r2] + 8001148: 0452 lsls r2, r2, #17 + 800114a: d504 bpl.n 8001156 + 800114c: 2144 movs r1, #68 ; 0x44 + 800114e: 5a5a ldrh r2, [r3, r1] + 8001150: 48c1 ldr r0, [pc, #772] ; (8001458 ) + 8001152: 4002 ands r2, r0 + 8001154: 525a strh r2, [r3, r1] + 8001156: 6823 ldr r3, [r4, #0] + 8001158: 2244 movs r2, #68 ; 0x44 + 800115a: 5a9a ldrh r2, [r3, r2] + 800115c: 0492 lsls r2, r2, #18 + 800115e: d504 bpl.n 800116a + 8001160: 2144 movs r1, #68 ; 0x44 + 8001162: 5a5a ldrh r2, [r3, r1] + 8001164: 48bd ldr r0, [pc, #756] ; (800145c ) + 8001166: 4002 ands r2, r0 + 8001168: 525a strh r2, [r3, r1] + 800116a: 6823 ldr r3, [r4, #0] + 800116c: 2244 movs r2, #68 ; 0x44 + 800116e: 5a9a ldrh r2, [r3, r2] + 8001170: 04d2 lsls r2, r2, #19 + 8001172: d500 bpl.n 8001176 + 8001174: e293 b.n 800169e + 8001176: 6823 ldr r3, [r4, #0] + 8001178: 2244 movs r2, #68 ; 0x44 + 800117a: 5a9a ldrh r2, [r3, r2] + 800117c: 0512 lsls r2, r2, #20 + 800117e: d514 bpl.n 80011aa + 8001180: 2244 movs r2, #68 ; 0x44 + 8001182: 5a99 ldrh r1, [r3, r2] + 8001184: 48b6 ldr r0, [pc, #728] ; (8001460 ) + 8001186: 4001 ands r1, r0 + 8001188: 5299 strh r1, [r3, r2] + 800118a: 6820 ldr r0, [r4, #0] + 800118c: 2340 movs r3, #64 ; 0x40 + 800118e: 5ac1 ldrh r1, [r0, r3] + 8001190: 2508 movs r5, #8 + 8001192: 4329 orrs r1, r5 + 8001194: 52c1 strh r1, [r0, r3] + 8001196: 6820 ldr r0, [r4, #0] + 8001198: 5ac1 ldrh r1, [r0, r3] + 800119a: 3d04 subs r5, #4 + 800119c: 4329 orrs r1, r5 + 800119e: 52c1 strh r1, [r0, r3] + 80011a0: 6823 ldr r3, [r4, #0] + 80011a2: 5a9b ldrh r3, [r3, r2] + 80011a4: 04db lsls r3, r3, #19 + 80011a6: d400 bmi.n 80011aa + 80011a8: e28b b.n 80016c2 + 80011aa: 6823 ldr r3, [r4, #0] + 80011ac: 2244 movs r2, #68 ; 0x44 + 80011ae: 5a9a ldrh r2, [r3, r2] + 80011b0: 0592 lsls r2, r2, #22 + 80011b2: d500 bpl.n 80011b6 + 80011b4: e289 b.n 80016ca + 80011b6: 6823 ldr r3, [r4, #0] + 80011b8: 2244 movs r2, #68 ; 0x44 + 80011ba: 5a9a ldrh r2, [r3, r2] + 80011bc: 05d2 lsls r2, r2, #23 + 80011be: d504 bpl.n 80011ca + 80011c0: 2144 movs r1, #68 ; 0x44 + 80011c2: 5a5a ldrh r2, [r3, r1] + 80011c4: 48a7 ldr r0, [pc, #668] ; (8001464 ) + 80011c6: 4002 ands r2, r0 + 80011c8: 525a strh r2, [r3, r1] + 80011ca: b002 add sp, #8 + 80011cc: bce0 pop {r5, r6, r7} + 80011ce: 46ba mov sl, r7 + 80011d0: 46b1 mov r9, r6 + 80011d2: 46a8 mov r8, r5 + 80011d4: bdf0 pop {r4, r5, r6, r7, pc} + 80011d6: 466b mov r3, sp + 80011d8: 2200 movs r2, #0 + 80011da: 80da strh r2, [r3, #6] + 80011dc: 2344 movs r3, #68 ; 0x44 + 80011de: 5ac3 ldrh r3, [r0, r3] + 80011e0: b29b uxth r3, r3 + 80011e2: aa01 add r2, sp, #4 + 80011e4: 8013 strh r3, [r2, #0] + 80011e6: b21b sxth r3, r3 + 80011e8: 2b00 cmp r3, #0 + 80011ea: daa4 bge.n 8001136 + 80011ec: 0017 movs r7, r2 + 80011ee: 230f movs r3, #15 + 80011f0: 4698 mov r8, r3 + 80011f2: 466b mov r3, sp + 80011f4: 1d9e adds r6, r3, #6 + 80011f6: e1c6 b.n 8001586 + 80011f8: 8803 ldrh r3, [r0, #0] + 80011fa: 4a9b ldr r2, [pc, #620] ; (8001468 ) + 80011fc: 4013 ands r3, r2 + 80011fe: 8003 strh r3, [r0, #0] + 8001200: 6821 ldr r1, [r4, #0] + 8001202: 2350 movs r3, #80 ; 0x50 + 8001204: 5acb ldrh r3, [r1, r3] + 8001206: 2228 movs r2, #40 ; 0x28 + 8001208: 5ca2 ldrb r2, [r4, r2] + 800120a: 00d2 lsls r2, r2, #3 + 800120c: 188a adds r2, r1, r2 + 800120e: 189b adds r3, r3, r2 + 8001210: 4a96 ldr r2, [pc, #600] ; (800146c ) + 8001212: 4694 mov ip, r2 + 8001214: 4463 add r3, ip + 8001216: 881b ldrh r3, [r3, #0] + 8001218: 059b lsls r3, r3, #22 + 800121a: 0d9b lsrs r3, r3, #22 + 800121c: 6423 str r3, [r4, #64] ; 0x40 + 800121e: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8001220: 4694 mov ip, r2 + 8001222: 4463 add r3, ip + 8001224: 63a3 str r3, [r4, #56] ; 0x38 + 8001226: 2100 movs r1, #0 + 8001228: 0020 movs r0, r4 + 800122a: f001 fdd3 bl 8002dd4 + 800122e: 2324 movs r3, #36 ; 0x24 + 8001230: 5ce3 ldrb r3, [r4, r3] + 8001232: 2b00 cmp r3, #0 + 8001234: d100 bne.n 8001238 + 8001236: e19d b.n 8001574 + 8001238: 6be3 ldr r3, [r4, #60] ; 0x3c + 800123a: 2b00 cmp r3, #0 + 800123c: d000 beq.n 8001240 + 800123e: e199 b.n 8001574 + 8001240: 2224 movs r2, #36 ; 0x24 + 8001242: 5ca3 ldrb r3, [r4, r2] + 8001244: 2180 movs r1, #128 ; 0x80 + 8001246: 430b orrs r3, r1 + 8001248: 3934 subs r1, #52 ; 0x34 + 800124a: 6820 ldr r0, [r4, #0] + 800124c: 5243 strh r3, [r0, r1] + 800124e: 2300 movs r3, #0 + 8001250: 54a3 strb r3, [r4, r2] + 8001252: e18f b.n 8001574 + 8001254: 2350 movs r3, #80 ; 0x50 + 8001256: 5ac3 ldrh r3, [r0, r3] + 8001258: 2284 movs r2, #132 ; 0x84 + 800125a: 0052 lsls r2, r2, #1 + 800125c: 5ca2 ldrb r2, [r4, r2] + 800125e: 00d2 lsls r2, r2, #3 + 8001260: 1882 adds r2, r0, r2 + 8001262: 189b adds r3, r3, r2 + 8001264: 4a82 ldr r2, [pc, #520] ; (8001470 ) + 8001266: 4694 mov ip, r2 + 8001268: 4463 add r3, ip + 800126a: 881b ldrh r3, [r3, #0] + 800126c: 059b lsls r3, r3, #22 + 800126e: 0d9b lsrs r3, r3, #22 + 8001270: 0022 movs r2, r4 + 8001272: 3209 adds r2, #9 + 8001274: 32ff adds r2, #255 ; 0xff + 8001276: 6193 str r3, [r2, #24] + 8001278: 8892 ldrh r2, [r2, #4] + 800127a: 0021 movs r1, r4 + 800127c: 31ed adds r1, #237 ; 0xed + 800127e: 31ff adds r1, #255 ; 0xff + 8001280: f7ff ff28 bl 80010d4 + 8001284: 6822 ldr r2, [r4, #0] + 8001286: 8813 ldrh r3, [r2, #0] + 8001288: 497a ldr r1, [pc, #488] ; (8001474 ) + 800128a: 400b ands r3, r1 + 800128c: 8013 strh r3, [r2, #0] + 800128e: 0020 movs r0, r4 + 8001290: f001 fd88 bl 8002da4 + 8001294: e16e b.n 8001574 + 8001296: 0015 movs r5, r2 + 8001298: 8892 ldrh r2, [r2, #4] + 800129a: 6929 ldr r1, [r5, #16] + 800129c: f7ff ff1a bl 80010d4 + 80012a0: 692b ldr r3, [r5, #16] + 80012a2: 69aa ldr r2, [r5, #24] + 80012a4: 4694 mov ip, r2 + 80012a6: 4463 add r3, ip + 80012a8: 612b str r3, [r5, #16] + 80012aa: e19b b.n 80015e4 + 80012ac: 0851 lsrs r1, r2, #1 + 80012ae: b289 uxth r1, r1 + 80012b0: 07d2 lsls r2, r2, #31 + 80012b2: d501 bpl.n 80012b8 + 80012b4: 3101 adds r1, #1 + 80012b6: b289 uxth r1, r1 + 80012b8: 0289 lsls r1, r1, #10 + 80012ba: 8019 strh r1, [r3, #0] + 80012bc: e1ae b.n 800161c + 80012be: 00ab lsls r3, r5, #2 + 80012c0: 4699 mov r9, r3 + 80012c2: 18c1 adds r1, r0, r3 + 80012c4: 5ac2 ldrh r2, [r0, r3] + 80012c6: 8032 strh r2, [r6, #0] + 80012c8: 8833 ldrh r3, [r6, #0] + 80012ca: b21b sxth r3, r3 + 80012cc: 2b00 cmp r3, #0 + 80012ce: db2f blt.n 8001330 + 80012d0: 8833 ldrh r3, [r6, #0] + 80012d2: 061b lsls r3, r3, #24 + 80012d4: d400 bmi.n 80012d8 + 80012d6: e14d b.n 8001574 + 80012d8: 6822 ldr r2, [r4, #0] + 80012da: 464b mov r3, r9 + 80012dc: 5ad3 ldrh r3, [r2, r3] + 80012de: 4962 ldr r1, [pc, #392] ; (8001468 ) + 80012e0: 400b ands r3, r1 + 80012e2: 4649 mov r1, r9 + 80012e4: 5253 strh r3, [r2, r1] + 80012e6: 00eb lsls r3, r5, #3 + 80012e8: 1b5b subs r3, r3, r5 + 80012ea: 009b lsls r3, r3, #2 + 80012ec: 18e3 adds r3, r4, r3 + 80012ee: 3332 adds r3, #50 ; 0x32 + 80012f0: 781b ldrb r3, [r3, #0] + 80012f2: 2b00 cmp r3, #0 + 80012f4: d000 beq.n 80012f8 + 80012f6: e0eb b.n 80014d0 + 80012f8: 6820 ldr r0, [r4, #0] + 80012fa: 3350 adds r3, #80 ; 0x50 + 80012fc: 5ac3 ldrh r3, [r0, r3] + 80012fe: 00ea lsls r2, r5, #3 + 8001300: 1b52 subs r2, r2, r5 + 8001302: 0092 lsls r2, r2, #2 + 8001304: 18a2 adds r2, r4, r2 + 8001306: 0011 movs r1, r2 + 8001308: 3128 adds r1, #40 ; 0x28 + 800130a: 7809 ldrb r1, [r1, #0] + 800130c: 00c9 lsls r1, r1, #3 + 800130e: 1841 adds r1, r0, r1 + 8001310: 185b adds r3, r3, r1 + 8001312: 4956 ldr r1, [pc, #344] ; (800146c ) + 8001314: 468c mov ip, r1 + 8001316: 4463 add r3, ip + 8001318: 881b ldrh r3, [r3, #0] + 800131a: 059b lsls r3, r3, #22 + 800131c: 0d9b lsrs r3, r3, #22 + 800131e: 6413 str r3, [r2, #64] ; 0x40 + 8001320: d100 bne.n 8001324 + 8001322: e102 b.n 800152a + 8001324: 0011 movs r1, r2 + 8001326: 8d92 ldrh r2, [r2, #44] ; 0x2c + 8001328: 6b89 ldr r1, [r1, #56] ; 0x38 + 800132a: f7ff fdb9 bl 8000ea0 + 800132e: e0fc b.n 800152a + 8001330: 4b50 ldr r3, [pc, #320] ; (8001474 ) + 8001332: 401a ands r2, r3 + 8001334: 800a strh r2, [r1, #0] + 8001336: 00eb lsls r3, r5, #3 + 8001338: 1b5b subs r3, r3, r5 + 800133a: 009b lsls r3, r3, #2 + 800133c: 18e3 adds r3, r4, r3 + 800133e: 3313 adds r3, #19 + 8001340: 33ff adds r3, #255 ; 0xff + 8001342: 781b ldrb r3, [r3, #0] + 8001344: 2b00 cmp r3, #0 + 8001346: d124 bne.n 8001392 + 8001348: 6820 ldr r0, [r4, #0] + 800134a: 3350 adds r3, #80 ; 0x50 + 800134c: 5ac2 ldrh r2, [r0, r3] + 800134e: 00eb lsls r3, r5, #3 + 8001350: 1b5b subs r3, r3, r5 + 8001352: 009b lsls r3, r3, #2 + 8001354: 18e3 adds r3, r4, r3 + 8001356: 3309 adds r3, #9 + 8001358: 33ff adds r3, #255 ; 0xff + 800135a: 781b ldrb r3, [r3, #0] + 800135c: 00db lsls r3, r3, #3 + 800135e: 18c3 adds r3, r0, r3 + 8001360: 18d3 adds r3, r2, r3 + 8001362: 4a43 ldr r2, [pc, #268] ; (8001470 ) + 8001364: 4694 mov ip, r2 + 8001366: 4463 add r3, ip + 8001368: 881b ldrh r3, [r3, #0] + 800136a: 059b lsls r3, r3, #22 + 800136c: 0d9a lsrs r2, r3, #22 + 800136e: 4692 mov sl, r2 + 8001370: 2b00 cmp r3, #0 + 8001372: d037 beq.n 80013e4 + 8001374: 00eb lsls r3, r5, #3 + 8001376: 1b5b subs r3, r3, r5 + 8001378: 009b lsls r3, r3, #2 + 800137a: 18e3 adds r3, r4, r3 + 800137c: 001a movs r2, r3 + 800137e: 320d adds r2, #13 + 8001380: 32ff adds r2, #255 ; 0xff + 8001382: 8812 ldrh r2, [r2, #0] + 8001384: 3319 adds r3, #25 + 8001386: 33ff adds r3, #255 ; 0xff + 8001388: 6819 ldr r1, [r3, #0] + 800138a: 4653 mov r3, sl + 800138c: f7ff fea2 bl 80010d4 + 8001390: e028 b.n 80013e4 + 8001392: 6820 ldr r0, [r4, #0] + 8001394: 00eb lsls r3, r5, #3 + 8001396: 1b5b subs r3, r3, r5 + 8001398: 009b lsls r3, r3, #2 + 800139a: 18e3 adds r3, r4, r3 + 800139c: 3309 adds r3, #9 + 800139e: 33ff adds r3, #255 ; 0xff + 80013a0: 781b ldrb r3, [r3, #0] + 80013a2: 009a lsls r2, r3, #2 + 80013a4: 5a12 ldrh r2, [r2, r0] + 80013a6: 0452 lsls r2, r2, #17 + 80013a8: d56a bpl.n 8001480 + 80013aa: 2250 movs r2, #80 ; 0x50 + 80013ac: 5a82 ldrh r2, [r0, r2] + 80013ae: 00db lsls r3, r3, #3 + 80013b0: 18c3 adds r3, r0, r3 + 80013b2: 18d3 adds r3, r2, r3 + 80013b4: 4a2d ldr r2, [pc, #180] ; (800146c ) + 80013b6: 4694 mov ip, r2 + 80013b8: 4463 add r3, ip + 80013ba: 881b ldrh r3, [r3, #0] + 80013bc: 059b lsls r3, r3, #22 + 80013be: 0d9a lsrs r2, r3, #22 + 80013c0: 4692 mov sl, r2 + 80013c2: 2b00 cmp r3, #0 + 80013c4: d138 bne.n 8001438 + 80013c6: 00eb lsls r3, r5, #3 + 80013c8: 1b5b subs r3, r3, r5 + 80013ca: 009b lsls r3, r3, #2 + 80013cc: 18e3 adds r3, r4, r3 + 80013ce: 3309 adds r3, #9 + 80013d0: 33ff adds r3, #255 ; 0xff + 80013d2: 781b ldrb r3, [r3, #0] + 80013d4: 009b lsls r3, r3, #2 + 80013d6: 6821 ldr r1, [r4, #0] + 80013d8: 5aca ldrh r2, [r1, r3] + 80013da: 4827 ldr r0, [pc, #156] ; (8001478 ) + 80013dc: 4010 ands r0, r2 + 80013de: 4a27 ldr r2, [pc, #156] ; (800147c ) + 80013e0: 4302 orrs r2, r0 + 80013e2: 52ca strh r2, [r1, r3] + 80013e4: 4650 mov r0, sl + 80013e6: 00e9 lsls r1, r5, #3 + 80013e8: 1b49 subs r1, r1, r5 + 80013ea: 0089 lsls r1, r1, #2 + 80013ec: 1861 adds r1, r4, r1 + 80013ee: 000a movs r2, r1 + 80013f0: 3221 adds r2, #33 ; 0x21 + 80013f2: 32ff adds r2, #255 ; 0xff + 80013f4: 6813 ldr r3, [r2, #0] + 80013f6: 4453 add r3, sl + 80013f8: 6013 str r3, [r2, #0] + 80013fa: 000b movs r3, r1 + 80013fc: 3319 adds r3, #25 + 80013fe: 33ff adds r3, #255 ; 0xff + 8001400: 681a ldr r2, [r3, #0] + 8001402: 4452 add r2, sl + 8001404: 601a str r2, [r3, #0] + 8001406: 311d adds r1, #29 + 8001408: 31ff adds r1, #255 ; 0xff + 800140a: 680b ldr r3, [r1, #0] + 800140c: 2b00 cmp r3, #0 + 800140e: d008 beq.n 8001422 + 8001410: 00e9 lsls r1, r5, #3 + 8001412: 1b49 subs r1, r1, r5 + 8001414: 0089 lsls r1, r1, #2 + 8001416: 1861 adds r1, r4, r1 + 8001418: 3115 adds r1, #21 + 800141a: 31ff adds r1, #255 ; 0xff + 800141c: 6809 ldr r1, [r1, #0] + 800141e: 4288 cmp r0, r1 + 8001420: d24b bcs.n 80014ba + 8001422: 00eb lsls r3, r5, #3 + 8001424: 1b5b subs r3, r3, r5 + 8001426: 009b lsls r3, r3, #2 + 8001428: 18e3 adds r3, r4, r3 + 800142a: 3309 adds r3, #9 + 800142c: 33ff adds r3, #255 ; 0xff + 800142e: 7819 ldrb r1, [r3, #0] + 8001430: 0020 movs r0, r4 + 8001432: f001 fcc1 bl 8002db8 + 8001436: e74b b.n 80012d0 + 8001438: 00eb lsls r3, r5, #3 + 800143a: 1b5b subs r3, r3, r5 + 800143c: 009b lsls r3, r3, #2 + 800143e: 18e3 adds r3, r4, r3 + 8001440: 001a movs r2, r3 + 8001442: 320f adds r2, #15 + 8001444: 32ff adds r2, #255 ; 0xff + 8001446: 8812 ldrh r2, [r2, #0] + 8001448: 3319 adds r3, #25 + 800144a: 33ff adds r3, #255 ; 0xff + 800144c: 6819 ldr r1, [r3, #0] + 800144e: 4653 mov r3, sl + 8001450: f7ff fe40 bl 80010d4 + 8001454: e7b7 b.n 80013c6 + 8001456: 46c0 nop ; (mov r8, r8) + 8001458: ffffbfff .word 0xffffbfff + 800145c: ffffdfff .word 0xffffdfff + 8001460: fffff7ff .word 0xfffff7ff + 8001464: fffffeff .word 0xfffffeff + 8001468: ffff8f0f .word 0xffff8f0f + 800146c: 00000402 .word 0x00000402 + 8001470: 00000406 .word 0x00000406 + 8001474: 00000f8f .word 0x00000f8f + 8001478: 00000f0f .word 0x00000f0f + 800147c: ffff80c0 .word 0xffff80c0 + 8001480: 2250 movs r2, #80 ; 0x50 + 8001482: 5a82 ldrh r2, [r0, r2] + 8001484: 00db lsls r3, r3, #3 + 8001486: 18c3 adds r3, r0, r3 + 8001488: 18d3 adds r3, r2, r3 + 800148a: 4a94 ldr r2, [pc, #592] ; (80016dc ) + 800148c: 4694 mov ip, r2 + 800148e: 4463 add r3, ip + 8001490: 881b ldrh r3, [r3, #0] + 8001492: 059b lsls r3, r3, #22 + 8001494: 0d9a lsrs r2, r3, #22 + 8001496: 4692 mov sl, r2 + 8001498: 2b00 cmp r3, #0 + 800149a: d094 beq.n 80013c6 + 800149c: 00eb lsls r3, r5, #3 + 800149e: 1b5b subs r3, r3, r5 + 80014a0: 009b lsls r3, r3, #2 + 80014a2: 18e3 adds r3, r4, r3 + 80014a4: 001a movs r2, r3 + 80014a6: 3211 adds r2, #17 + 80014a8: 32ff adds r2, #255 ; 0xff + 80014aa: 8812 ldrh r2, [r2, #0] + 80014ac: 3319 adds r3, #25 + 80014ae: 33ff adds r3, #255 ; 0xff + 80014b0: 6819 ldr r1, [r3, #0] + 80014b2: 4653 mov r3, sl + 80014b4: f7ff fe0e bl 80010d4 + 80014b8: e785 b.n 80013c6 + 80014ba: 00e9 lsls r1, r5, #3 + 80014bc: 1b49 subs r1, r1, r5 + 80014be: 0089 lsls r1, r1, #2 + 80014c0: 1861 adds r1, r4, r1 + 80014c2: 3109 adds r1, #9 + 80014c4: 31ff adds r1, #255 ; 0xff + 80014c6: 7809 ldrb r1, [r1, #0] + 80014c8: 0020 movs r0, r4 + 80014ca: f7ff fae7 bl 8000a9c + 80014ce: e6ff b.n 80012d0 + 80014d0: 6820 ldr r0, [r4, #0] + 80014d2: 00eb lsls r3, r5, #3 + 80014d4: 1b5b subs r3, r3, r5 + 80014d6: 009b lsls r3, r3, #2 + 80014d8: 18e3 adds r3, r4, r3 + 80014da: 3328 adds r3, #40 ; 0x28 + 80014dc: 781b ldrb r3, [r3, #0] + 80014de: 009a lsls r2, r3, #2 + 80014e0: 5a12 ldrh r2, [r2, r0] + 80014e2: 0652 lsls r2, r2, #25 + 80014e4: d400 bmi.n 80014e8 + 80014e6: e0aa b.n 800163e + 80014e8: 2250 movs r2, #80 ; 0x50 + 80014ea: 5a82 ldrh r2, [r0, r2] + 80014ec: 00db lsls r3, r3, #3 + 80014ee: 18c3 adds r3, r0, r3 + 80014f0: 18d3 adds r3, r2, r3 + 80014f2: 4a7b ldr r2, [pc, #492] ; (80016e0 ) + 80014f4: 4694 mov ip, r2 + 80014f6: 4463 add r3, ip + 80014f8: 881b ldrh r3, [r3, #0] + 80014fa: 059b lsls r3, r3, #22 + 80014fc: 0d9b lsrs r3, r3, #22 + 80014fe: 00ea lsls r2, r5, #3 + 8001500: 1b52 subs r2, r2, r5 + 8001502: 0092 lsls r2, r2, #2 + 8001504: 18a2 adds r2, r4, r2 + 8001506: 6413 str r3, [r2, #64] ; 0x40 + 8001508: 2b00 cmp r3, #0 + 800150a: d000 beq.n 800150e + 800150c: e091 b.n 8001632 + 800150e: 00eb lsls r3, r5, #3 + 8001510: 1b5b subs r3, r3, r5 + 8001512: 009b lsls r3, r3, #2 + 8001514: 18e3 adds r3, r4, r3 + 8001516: 3328 adds r3, #40 ; 0x28 + 8001518: 781b ldrb r3, [r3, #0] + 800151a: 009b lsls r3, r3, #2 + 800151c: 6821 ldr r1, [r4, #0] + 800151e: 5aca ldrh r2, [r1, r3] + 8001520: 4870 ldr r0, [pc, #448] ; (80016e4 ) + 8001522: 4010 ands r0, r2 + 8001524: 4a70 ldr r2, [pc, #448] ; (80016e8 ) + 8001526: 4302 orrs r2, r0 + 8001528: 52ca strh r2, [r1, r3] + 800152a: 6821 ldr r1, [r4, #0] + 800152c: 2350 movs r3, #80 ; 0x50 + 800152e: 5aca ldrh r2, [r1, r3] + 8001530: 00eb lsls r3, r5, #3 + 8001532: 1b5b subs r3, r3, r5 + 8001534: 009b lsls r3, r3, #2 + 8001536: 18e3 adds r3, r4, r3 + 8001538: 0018 movs r0, r3 + 800153a: 3028 adds r0, #40 ; 0x28 + 800153c: 7800 ldrb r0, [r0, #0] + 800153e: 00c0 lsls r0, r0, #3 + 8001540: 1809 adds r1, r1, r0 + 8001542: 1852 adds r2, r2, r1 + 8001544: 4966 ldr r1, [pc, #408] ; (80016e0 ) + 8001546: 468c mov ip, r1 + 8001548: 4462 add r2, ip + 800154a: 8812 ldrh r2, [r2, #0] + 800154c: 0592 lsls r2, r2, #22 + 800154e: 0d92 lsrs r2, r2, #22 + 8001550: 641a str r2, [r3, #64] ; 0x40 + 8001552: 6b99 ldr r1, [r3, #56] ; 0x38 + 8001554: 468c mov ip, r1 + 8001556: 4462 add r2, ip + 8001558: 639a str r2, [r3, #56] ; 0x38 + 800155a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800155c: 2b00 cmp r3, #0 + 800155e: d000 beq.n 8001562 + 8001560: e086 b.n 8001670 + 8001562: 00eb lsls r3, r5, #3 + 8001564: 1b5d subs r5, r3, r5 + 8001566: 00ad lsls r5, r5, #2 + 8001568: 1965 adds r5, r4, r5 + 800156a: 3528 adds r5, #40 ; 0x28 + 800156c: 7829 ldrb r1, [r5, #0] + 800156e: 0020 movs r0, r4 + 8001570: f001 fc30 bl 8002dd4 + 8001574: 6820 ldr r0, [r4, #0] + 8001576: 2344 movs r3, #68 ; 0x44 + 8001578: 5ac3 ldrh r3, [r0, r3] + 800157a: b29b uxth r3, r3 + 800157c: 803b strh r3, [r7, #0] + 800157e: b21b sxth r3, r3 + 8001580: 2b00 cmp r3, #0 + 8001582: db00 blt.n 8001586 + 8001584: e5d7 b.n 8001136 + 8001586: 883b ldrh r3, [r7, #0] + 8001588: 4645 mov r5, r8 + 800158a: 401d ands r5, r3 + 800158c: 4642 mov r2, r8 + 800158e: 4213 tst r3, r2 + 8001590: d000 beq.n 8001594 + 8001592: e694 b.n 80012be + 8001594: 883b ldrh r3, [r7, #0] + 8001596: 06db lsls r3, r3, #27 + 8001598: d400 bmi.n 800159c + 800159a: e62d b.n 80011f8 + 800159c: 8803 ldrh r3, [r0, #0] + 800159e: 8033 strh r3, [r6, #0] + 80015a0: 8833 ldrh r3, [r6, #0] + 80015a2: 051b lsls r3, r3, #20 + 80015a4: d500 bpl.n 80015a8 + 80015a6: e655 b.n 8001254 + 80015a8: 8833 ldrh r3, [r6, #0] + 80015aa: b21b sxth r3, r3 + 80015ac: 2b00 cmp r3, #0 + 80015ae: dae1 bge.n 8001574 + 80015b0: 8803 ldrh r3, [r0, #0] + 80015b2: 4a4e ldr r2, [pc, #312] ; (80016ec ) + 80015b4: 4013 ands r3, r2 + 80015b6: 8003 strh r3, [r0, #0] + 80015b8: 6820 ldr r0, [r4, #0] + 80015ba: 2350 movs r3, #80 ; 0x50 + 80015bc: 5ac3 ldrh r3, [r0, r3] + 80015be: 2284 movs r2, #132 ; 0x84 + 80015c0: 0052 lsls r2, r2, #1 + 80015c2: 5ca2 ldrb r2, [r4, r2] + 80015c4: 00d2 lsls r2, r2, #3 + 80015c6: 1882 adds r2, r0, r2 + 80015c8: 189b adds r3, r3, r2 + 80015ca: 4a44 ldr r2, [pc, #272] ; (80016dc ) + 80015cc: 4694 mov ip, r2 + 80015ce: 4463 add r3, ip + 80015d0: 881b ldrh r3, [r3, #0] + 80015d2: 059b lsls r3, r3, #22 + 80015d4: 0d9b lsrs r3, r3, #22 + 80015d6: 0022 movs r2, r4 + 80015d8: 3209 adds r2, #9 + 80015da: 32ff adds r2, #255 ; 0xff + 80015dc: 6193 str r3, [r2, #24] + 80015de: 2b00 cmp r3, #0 + 80015e0: d000 beq.n 80015e4 + 80015e2: e658 b.n 8001296 + 80015e4: 2100 movs r1, #0 + 80015e6: 0020 movs r0, r4 + 80015e8: f001 fbe6 bl 8002db8 + 80015ec: 6823 ldr r3, [r4, #0] + 80015ee: 2250 movs r2, #80 ; 0x50 + 80015f0: 5a9a ldrh r2, [r3, r2] + 80015f2: 493a ldr r1, [pc, #232] ; (80016dc ) + 80015f4: 468c mov ip, r1 + 80015f6: 4463 add r3, ip + 80015f8: 189b adds r3, r3, r2 + 80015fa: 0022 movs r2, r4 + 80015fc: 3209 adds r2, #9 + 80015fe: 32ff adds r2, #255 ; 0xff + 8001600: 68d2 ldr r2, [r2, #12] + 8001602: 2a3e cmp r2, #62 ; 0x3e + 8001604: d800 bhi.n 8001608 + 8001606: e651 b.n 80012ac + 8001608: 0951 lsrs r1, r2, #5 + 800160a: b289 uxth r1, r1 + 800160c: 06d2 lsls r2, r2, #27 + 800160e: d101 bne.n 8001614 + 8001610: 3901 subs r1, #1 + 8001612: b289 uxth r1, r1 + 8001614: 0289 lsls r1, r1, #10 + 8001616: 4a36 ldr r2, [pc, #216] ; (80016f0 ) + 8001618: 4311 orrs r1, r2 + 800161a: 8019 strh r1, [r3, #0] + 800161c: 6821 ldr r1, [r4, #0] + 800161e: 880a ldrh r2, [r1, #0] + 8001620: 4b34 ldr r3, [pc, #208] ; (80016f4 ) + 8001622: 401a ands r2, r3 + 8001624: 23c0 movs r3, #192 ; 0xc0 + 8001626: 019b lsls r3, r3, #6 + 8001628: 405a eors r2, r3 + 800162a: 4b33 ldr r3, [pc, #204] ; (80016f8 ) + 800162c: 4313 orrs r3, r2 + 800162e: 800b strh r3, [r1, #0] + 8001630: e7a0 b.n 8001574 + 8001632: 0011 movs r1, r2 + 8001634: 8dd2 ldrh r2, [r2, #46] ; 0x2e + 8001636: 6b89 ldr r1, [r1, #56] ; 0x38 + 8001638: f7ff fc32 bl 8000ea0 + 800163c: e767 b.n 800150e + 800163e: 2250 movs r2, #80 ; 0x50 + 8001640: 5a82 ldrh r2, [r0, r2] + 8001642: 00db lsls r3, r3, #3 + 8001644: 18c3 adds r3, r0, r3 + 8001646: 18d3 adds r3, r2, r3 + 8001648: 4a24 ldr r2, [pc, #144] ; (80016dc ) + 800164a: 4694 mov ip, r2 + 800164c: 4463 add r3, ip + 800164e: 881b ldrh r3, [r3, #0] + 8001650: 059b lsls r3, r3, #22 + 8001652: 0d9b lsrs r3, r3, #22 + 8001654: 00ea lsls r2, r5, #3 + 8001656: 1b52 subs r2, r2, r5 + 8001658: 0092 lsls r2, r2, #2 + 800165a: 18a2 adds r2, r4, r2 + 800165c: 6413 str r3, [r2, #64] ; 0x40 + 800165e: 2b00 cmp r3, #0 + 8001660: d100 bne.n 8001664 + 8001662: e754 b.n 800150e + 8001664: 0011 movs r1, r2 + 8001666: 8e12 ldrh r2, [r2, #48] ; 0x30 + 8001668: 6b89 ldr r1, [r1, #56] ; 0x38 + 800166a: f7ff fc19 bl 8000ea0 + 800166e: e74e b.n 800150e + 8001670: 00e9 lsls r1, r5, #3 + 8001672: 1b4d subs r5, r1, r5 + 8001674: 00ad lsls r5, r5, #2 + 8001676: 1965 adds r5, r4, r5 + 8001678: 3528 adds r5, #40 ; 0x28 + 800167a: 7829 ldrb r1, [r5, #0] + 800167c: 0020 movs r0, r4 + 800167e: f7ff fc27 bl 8000ed0 + 8001682: e777 b.n 8001574 + 8001684: 2144 movs r1, #68 ; 0x44 + 8001686: 5a5a ldrh r2, [r3, r1] + 8001688: 481c ldr r0, [pc, #112] ; (80016fc ) + 800168a: 4002 ands r2, r0 + 800168c: 525a strh r2, [r3, r1] + 800168e: 0020 movs r0, r4 + 8001690: f001 fbb3 bl 8002dfa + 8001694: 2100 movs r1, #0 + 8001696: 0020 movs r0, r4 + 8001698: f7fe ff8b bl 80005b2 + 800169c: e551 b.n 8001142 + 800169e: 2240 movs r2, #64 ; 0x40 + 80016a0: 5a99 ldrh r1, [r3, r2] + 80016a2: 2004 movs r0, #4 + 80016a4: 4381 bics r1, r0 + 80016a6: 5299 strh r1, [r3, r2] + 80016a8: 4b15 ldr r3, [pc, #84] ; (8001700 ) + 80016aa: 6821 ldr r1, [r4, #0] + 80016ac: 528b strh r3, [r1, r2] + 80016ae: 0020 movs r0, r4 + 80016b0: f001 fbc8 bl 8002e44 + 80016b4: 6821 ldr r1, [r4, #0] + 80016b6: 2244 movs r2, #68 ; 0x44 + 80016b8: 5a8b ldrh r3, [r1, r2] + 80016ba: 4812 ldr r0, [pc, #72] ; (8001704 ) + 80016bc: 4003 ands r3, r0 + 80016be: 528b strh r3, [r1, r2] + 80016c0: e559 b.n 8001176 + 80016c2: 0020 movs r0, r4 + 80016c4: f001 fbac bl 8002e20 + 80016c8: e56f b.n 80011aa + 80016ca: 2144 movs r1, #68 ; 0x44 + 80016cc: 5a5a ldrh r2, [r3, r1] + 80016ce: 480e ldr r0, [pc, #56] ; (8001708 ) + 80016d0: 4002 ands r2, r0 + 80016d2: 525a strh r2, [r3, r1] + 80016d4: 0020 movs r0, r4 + 80016d6: f001 fb89 bl 8002dec + 80016da: e56c b.n 80011b6 + 80016dc: 00000406 .word 0x00000406 + 80016e0: 00000402 .word 0x00000402 + 80016e4: 00000f0f .word 0x00000f0f + 80016e8: ffffc080 .word 0xffffc080 + 80016ec: 00000f8f .word 0x00000f8f + 80016f0: ffff8000 .word 0xffff8000 + 80016f4: ffffbf8f .word 0xffffbf8f + 80016f8: ffff8080 .word 0xffff8080 + 80016fc: fffffbff .word 0xfffffbff + 8001700: ffffbd00 .word 0xffffbd00 + 8001704: ffffefff .word 0xffffefff + 8001708: fffffdff .word 0xfffffdff + +0800170c : + 800170c: b510 push {r4, lr} + 800170e: 060c lsls r4, r1, #24 + 8001710: d50c bpl.n 800172c + 8001712: 247f movs r4, #127 ; 0x7f + 8001714: 4021 ands r1, r4 + 8001716: 00cc lsls r4, r1, #3 + 8001718: 1a61 subs r1, r4, r1 + 800171a: 0089 lsls r1, r1, #2 + 800171c: 3128 adds r1, #40 ; 0x28 + 800171e: 1840 adds r0, r0, r1 + 8001720: 2a00 cmp r2, #0 + 8001722: d10a bne.n 800173a + 8001724: 7282 strb r2, [r0, #10] + 8001726: 8083 strh r3, [r0, #4] + 8001728: 2000 movs r0, #0 + 800172a: bd10 pop {r4, pc} + 800172c: 00cc lsls r4, r1, #3 + 800172e: 1a61 subs r1, r4, r1 + 8001730: 0089 lsls r1, r1, #2 + 8001732: 3109 adds r1, #9 + 8001734: 31ff adds r1, #255 ; 0xff + 8001736: 1840 adds r0, r0, r1 + 8001738: e7f2 b.n 8001720 + 800173a: 2201 movs r2, #1 + 800173c: 7282 strb r2, [r0, #10] + 800173e: 80c3 strh r3, [r0, #6] + 8001740: 0c1b lsrs r3, r3, #16 + 8001742: 8103 strh r3, [r0, #8] + 8001744: e7f0 b.n 8001728 + ... + +08001748 : + 8001748: 4b01 ldr r3, [pc, #4] ; (8001750 ) + 800174a: 6818 ldr r0, [r3, #0] + 800174c: 4770 bx lr + 800174e: 46c0 nop ; (mov r8, r8) + 8001750: 20000110 .word 0x20000110 + +08001754 : + 8001754: b510 push {r4, lr} + 8001756: 21fa movs r1, #250 ; 0xfa + 8001758: 0089 lsls r1, r1, #2 + 800175a: f7fe fcd5 bl 8000108 <__udivsi3> + 800175e: 3801 subs r0, #1 + 8001760: 4b03 ldr r3, [pc, #12] ; (8001770 ) + 8001762: 6058 str r0, [r3, #4] + 8001764: 2200 movs r2, #0 + 8001766: 609a str r2, [r3, #8] + 8001768: 3205 adds r2, #5 + 800176a: 601a str r2, [r3, #0] + 800176c: bd10 pop {r4, pc} + 800176e: 46c0 nop ; (mov r8, r8) + 8001770: e000e010 .word 0xe000e010 + +08001774 : + 8001774: 4b01 ldr r3, [pc, #4] ; (800177c ) + 8001776: 6018 str r0, [r3, #0] + 8001778: 4770 bx lr + 800177a: 46c0 nop ; (mov r8, r8) + 800177c: 20000110 .word 0x20000110 + +08001780 : + 8001780: 2386 movs r3, #134 ; 0x86 + 8001782: 009b lsls r3, r3, #2 + 8001784: 58c3 ldr r3, [r0, r3] + 8001786: 2b00 cmp r3, #0 + 8001788: d005 beq.n 8001796 + 800178a: 2285 movs r2, #133 ; 0x85 + 800178c: 0092 lsls r2, r2, #2 + 800178e: 2100 movs r1, #0 + 8001790: 5099 str r1, [r3, r2] + 8001792: 2000 movs r0, #0 + 8001794: 4770 bx lr + 8001796: 2002 movs r0, #2 + 8001798: e7fc b.n 8001794 + ... + +0800179c : + 800179c: b510 push {r4, lr} + 800179e: 2387 movs r3, #135 ; 0x87 + 80017a0: 009b lsls r3, r3, #2 + 80017a2: 58c3 ldr r3, [r0, r3] + 80017a4: 2b00 cmp r3, #0 + 80017a6: d00f beq.n 80017c8 + 80017a8: 2286 movs r2, #134 ; 0x86 + 80017aa: 0092 lsls r2, r2, #2 + 80017ac: 5884 ldr r4, [r0, r2] + 80017ae: 3a18 subs r2, #24 + 80017b0: 5ca0 ldrb r0, [r4, r2] + 80017b2: 28ff cmp r0, #255 ; 0xff + 80017b4: d008 beq.n 80017c8 + 80017b6: 4a05 ldr r2, [pc, #20] ; (80017cc ) + 80017b8: 5ca2 ldrb r2, [r4, r2] + 80017ba: 689b ldr r3, [r3, #8] + 80017bc: 0021 movs r1, r4 + 80017be: 4798 blx r3 + 80017c0: 2380 movs r3, #128 ; 0x80 + 80017c2: 009b lsls r3, r3, #2 + 80017c4: 22ff movs r2, #255 ; 0xff + 80017c6: 54e2 strb r2, [r4, r3] + 80017c8: 2000 movs r0, #0 + 80017ca: bd10 pop {r4, pc} + 80017cc: 00000201 .word 0x00000201 + +080017d0 : + 80017d0: 2343 movs r3, #67 ; 0x43 + 80017d2: 8003 strh r3, [r0, #0] + 80017d4: 4800 ldr r0, [pc, #0] ; (80017d8 ) + 80017d6: 4770 bx lr + 80017d8: 20000038 .word 0x20000038 + +080017dc : + 80017dc: 2343 movs r3, #67 ; 0x43 + 80017de: 8003 strh r3, [r0, #0] + 80017e0: 4800 ldr r0, [pc, #0] ; (80017e4 ) + 80017e2: 4770 bx lr + 80017e4: 2000007c .word 0x2000007c + +080017e8 : + 80017e8: 2343 movs r3, #67 ; 0x43 + 80017ea: 8003 strh r3, [r0, #0] + 80017ec: 4800 ldr r0, [pc, #0] ; (80017f0 ) + 80017ee: 4770 bx lr + 80017f0: 200000cc .word 0x200000cc + +080017f4 : + 80017f4: 230a movs r3, #10 + 80017f6: 8003 strh r3, [r0, #0] + 80017f8: 4800 ldr r0, [pc, #0] ; (80017fc ) + 80017fa: 4770 bx lr + 80017fc: 200000c0 .word 0x200000c0 + +08001800 : + 8001800: b570 push {r4, r5, r6, lr} + 8001802: 0004 movs r4, r0 + 8001804: 2686 movs r6, #134 ; 0x86 + 8001806: 00b6 lsls r6, r6, #2 + 8001808: 5985 ldr r5, [r0, r6] + 800180a: f001 fbd7 bl 8002fbc + 800180e: 2383 movs r3, #131 ; 0x83 + 8001810: 009b lsls r3, r3, #2 + 8001812: 50e8 str r0, [r5, r3] + 8001814: 59a3 ldr r3, [r4, r6] + 8001816: 2b00 cmp r3, #0 + 8001818: d00a beq.n 8001830 + 800181a: 2383 movs r3, #131 ; 0x83 + 800181c: 009b lsls r3, r3, #2 + 800181e: 18e9 adds r1, r5, r3 + 8001820: 3b08 subs r3, #8 + 8001822: 58e8 ldr r0, [r5, r3] + 8001824: 3318 adds r3, #24 + 8001826: 58e3 ldr r3, [r4, r3] + 8001828: 68db ldr r3, [r3, #12] + 800182a: 4798 blx r3 + 800182c: 2000 movs r0, #0 + 800182e: bd70 pop {r4, r5, r6, pc} + 8001830: 2002 movs r0, #2 + 8001832: e7fc b.n 800182e + +08001834 : + 8001834: b570 push {r4, r5, r6, lr} + 8001836: 0005 movs r5, r0 + 8001838: 000c movs r4, r1 + 800183a: 780b ldrb r3, [r1, #0] + 800183c: 2260 movs r2, #96 ; 0x60 + 800183e: 0011 movs r1, r2 + 8001840: 4019 ands r1, r3 + 8001842: 421a tst r2, r3 + 8001844: d02c beq.n 80018a0 + 8001846: 2920 cmp r1, #32 + 8001848: d12d bne.n 80018a6 + 800184a: 88e2 ldrh r2, [r4, #6] + 800184c: 2a00 cmp r2, #0 + 800184e: d01e beq.n 800188e + 8001850: 31f9 adds r1, #249 ; 0xf9 + 8001852: 31ff adds r1, #255 ; 0xff + 8001854: 5846 ldr r6, [r0, r1] + 8001856: b25b sxtb r3, r3 + 8001858: 2b00 cmp r3, #0 + 800185a: da0c bge.n 8001876 + 800185c: 7860 ldrb r0, [r4, #1] + 800185e: 2387 movs r3, #135 ; 0x87 + 8001860: 009b lsls r3, r3, #2 + 8001862: 58eb ldr r3, [r5, r3] + 8001864: 689b ldr r3, [r3, #8] + 8001866: 0031 movs r1, r6 + 8001868: 4798 blx r3 + 800186a: 88e2 ldrh r2, [r4, #6] + 800186c: 0031 movs r1, r6 + 800186e: 0028 movs r0, r5 + 8001870: f000 fcb8 bl 80021e4 + 8001874: e017 b.n 80018a6 + 8001876: 7862 ldrb r2, [r4, #1] + 8001878: 2380 movs r3, #128 ; 0x80 + 800187a: 009b lsls r3, r3, #2 + 800187c: 54f2 strb r2, [r6, r3] + 800187e: 88e2 ldrh r2, [r4, #6] + 8001880: 4b0c ldr r3, [pc, #48] ; (80018b4 ) + 8001882: 54f2 strb r2, [r6, r3] + 8001884: 88e2 ldrh r2, [r4, #6] + 8001886: 0031 movs r1, r6 + 8001888: f000 fcc2 bl 8002210 + 800188c: e00b b.n 80018a6 + 800188e: 7860 ldrb r0, [r4, #1] + 8001890: 2387 movs r3, #135 ; 0x87 + 8001892: 009b lsls r3, r3, #2 + 8001894: 58eb ldr r3, [r5, r3] + 8001896: 689b ldr r3, [r3, #8] + 8001898: 2200 movs r2, #0 + 800189a: 0021 movs r1, r4 + 800189c: 4798 blx r3 + 800189e: e002 b.n 80018a6 + 80018a0: 7863 ldrb r3, [r4, #1] + 80018a2: 2b0a cmp r3, #10 + 80018a4: d001 beq.n 80018aa + 80018a6: 2000 movs r0, #0 + 80018a8: bd70 pop {r4, r5, r6, pc} + 80018aa: 2201 movs r2, #1 + 80018ac: 4902 ldr r1, [pc, #8] ; (80018b8 ) + 80018ae: f000 fc99 bl 80021e4 + 80018b2: e7f8 b.n 80018a6 + 80018b4: 00000201 .word 0x00000201 + 80018b8: 20000190 .word 0x20000190 + +080018bc : + 80018bc: b570 push {r4, r5, r6, lr} + 80018be: 0004 movs r4, r0 + 80018c0: 2181 movs r1, #129 ; 0x81 + 80018c2: f001 fb2c bl 8002f1e + 80018c6: 2101 movs r1, #1 + 80018c8: 0020 movs r0, r4 + 80018ca: f001 fb28 bl 8002f1e + 80018ce: 2182 movs r1, #130 ; 0x82 + 80018d0: 0020 movs r0, r4 + 80018d2: f001 fb24 bl 8002f1e + 80018d6: 2386 movs r3, #134 ; 0x86 + 80018d8: 009b lsls r3, r3, #2 + 80018da: 58e3 ldr r3, [r4, r3] + 80018dc: 2b00 cmp r3, #0 + 80018de: d00b beq.n 80018f8 + 80018e0: 2387 movs r3, #135 ; 0x87 + 80018e2: 009b lsls r3, r3, #2 + 80018e4: 58e3 ldr r3, [r4, r3] + 80018e6: 685b ldr r3, [r3, #4] + 80018e8: 4798 blx r3 + 80018ea: 2586 movs r5, #134 ; 0x86 + 80018ec: 00ad lsls r5, r5, #2 + 80018ee: 5960 ldr r0, [r4, r5] + 80018f0: f001 fb70 bl 8002fd4 + 80018f4: 2300 movs r3, #0 + 80018f6: 5163 str r3, [r4, r5] + 80018f8: 2000 movs r0, #0 + 80018fa: bd70 pop {r4, r5, r6, pc} + +080018fc : + 80018fc: b570 push {r4, r5, r6, lr} + 80018fe: 0004 movs r4, r0 + 8001900: 7c03 ldrb r3, [r0, #16] + 8001902: 2b00 cmp r3, #0 + 8001904: d133 bne.n 800196e + 8001906: 2580 movs r5, #128 ; 0x80 + 8001908: 00ad lsls r5, r5, #2 + 800190a: 002b movs r3, r5 + 800190c: 2202 movs r2, #2 + 800190e: 2181 movs r1, #129 ; 0x81 + 8001910: f001 faf9 bl 8002f06 + 8001914: 002b movs r3, r5 + 8001916: 2202 movs r2, #2 + 8001918: 2101 movs r1, #1 + 800191a: 0020 movs r0, r4 + 800191c: f001 faf3 bl 8002f06 + 8001920: 2308 movs r3, #8 + 8001922: 2203 movs r2, #3 + 8001924: 2182 movs r1, #130 ; 0x82 + 8001926: 0020 movs r0, r4 + 8001928: f001 faed bl 8002f06 + 800192c: 2087 movs r0, #135 ; 0x87 + 800192e: 0080 lsls r0, r0, #2 + 8001930: f001 fb4c bl 8002fcc + 8001934: 0005 movs r5, r0 + 8001936: 2386 movs r3, #134 ; 0x86 + 8001938: 009b lsls r3, r3, #2 + 800193a: 50e0 str r0, [r4, r3] + 800193c: 2800 cmp r0, #0 + 800193e: d02d beq.n 800199c + 8001940: 3304 adds r3, #4 + 8001942: 58e3 ldr r3, [r4, r3] + 8001944: 681b ldr r3, [r3, #0] + 8001946: 4798 blx r3 + 8001948: 2300 movs r3, #0 + 800194a: 2285 movs r2, #133 ; 0x85 + 800194c: 0092 lsls r2, r2, #2 + 800194e: 50ab str r3, [r5, r2] + 8001950: 3204 adds r2, #4 + 8001952: 50ab str r3, [r5, r2] + 8001954: 7c26 ldrb r6, [r4, #16] + 8001956: 2e00 cmp r6, #0 + 8001958: d115 bne.n 8001986 + 800195a: 3380 adds r3, #128 ; 0x80 + 800195c: 3a14 subs r2, #20 + 800195e: 58aa ldr r2, [r5, r2] + 8001960: 009b lsls r3, r3, #2 + 8001962: 2101 movs r1, #1 + 8001964: 0020 movs r0, r4 + 8001966: f001 fb20 bl 8002faa + 800196a: 0030 movs r0, r6 + 800196c: bd70 pop {r4, r5, r6, pc} + 800196e: 2340 movs r3, #64 ; 0x40 + 8001970: 2202 movs r2, #2 + 8001972: 2181 movs r1, #129 ; 0x81 + 8001974: f001 fac7 bl 8002f06 + 8001978: 2340 movs r3, #64 ; 0x40 + 800197a: 2202 movs r2, #2 + 800197c: 2101 movs r1, #1 + 800197e: 0020 movs r0, r4 + 8001980: f001 fac1 bl 8002f06 + 8001984: e7cc b.n 8001920 + 8001986: 2381 movs r3, #129 ; 0x81 + 8001988: 009b lsls r3, r3, #2 + 800198a: 58ea ldr r2, [r5, r3] + 800198c: 3bc5 subs r3, #197 ; 0xc5 + 800198e: 3bff subs r3, #255 ; 0xff + 8001990: 2101 movs r1, #1 + 8001992: 0020 movs r0, r4 + 8001994: f001 fb09 bl 8002faa + 8001998: 2600 movs r6, #0 + 800199a: e7e6 b.n 800196a + 800199c: 2601 movs r6, #1 + 800199e: e7e4 b.n 800196a + +080019a0 : + 80019a0: 2900 cmp r1, #0 + 80019a2: d004 beq.n 80019ae + 80019a4: 2387 movs r3, #135 ; 0x87 + 80019a6: 009b lsls r3, r3, #2 + 80019a8: 50c1 str r1, [r0, r3] + 80019aa: 2000 movs r0, #0 + 80019ac: 4770 bx lr + 80019ae: 2002 movs r0, #2 + 80019b0: e7fc b.n 80019ac + +080019b2 : + 80019b2: 2386 movs r3, #134 ; 0x86 + 80019b4: 009b lsls r3, r3, #2 + 80019b6: 58c3 ldr r3, [r0, r3] + 80019b8: 2082 movs r0, #130 ; 0x82 + 80019ba: 0080 lsls r0, r0, #2 + 80019bc: 5019 str r1, [r3, r0] + 80019be: 2184 movs r1, #132 ; 0x84 + 80019c0: 0089 lsls r1, r1, #2 + 80019c2: 505a str r2, [r3, r1] + 80019c4: 2000 movs r0, #0 + 80019c6: 4770 bx lr + +080019c8 : + 80019c8: 2386 movs r3, #134 ; 0x86 + 80019ca: 009b lsls r3, r3, #2 + 80019cc: 58c2 ldr r2, [r0, r3] + 80019ce: 3b14 subs r3, #20 + 80019d0: 50d1 str r1, [r2, r3] + 80019d2: 2000 movs r0, #0 + 80019d4: 4770 bx lr + +080019d6 : + 80019d6: b510 push {r4, lr} + 80019d8: 0004 movs r4, r0 + 80019da: 2386 movs r3, #134 ; 0x86 + 80019dc: 009b lsls r3, r3, #2 + 80019de: 58c2 ldr r2, [r0, r3] + 80019e0: 2a00 cmp r2, #0 + 80019e2: d015 beq.n 8001a10 + 80019e4: 3b04 subs r3, #4 + 80019e6: 58d3 ldr r3, [r2, r3] + 80019e8: 2001 movs r0, #1 + 80019ea: 2b00 cmp r3, #0 + 80019ec: d000 beq.n 80019f0 + 80019ee: bd10 pop {r4, pc} + 80019f0: 2385 movs r3, #133 ; 0x85 + 80019f2: 009b lsls r3, r3, #2 + 80019f4: 2101 movs r1, #1 + 80019f6: 50d1 str r1, [r2, r3] + 80019f8: 3b04 subs r3, #4 + 80019fa: 5ad3 ldrh r3, [r2, r3] + 80019fc: 2182 movs r1, #130 ; 0x82 + 80019fe: 0089 lsls r1, r1, #2 + 8001a00: 5852 ldr r2, [r2, r1] + 8001a02: 3988 subs r1, #136 ; 0x88 + 8001a04: 39ff subs r1, #255 ; 0xff + 8001a06: 0020 movs r0, r4 + 8001a08: f001 fac6 bl 8002f98 + 8001a0c: 2000 movs r0, #0 + 8001a0e: e7ee b.n 80019ee + 8001a10: 2002 movs r0, #2 + 8001a12: e7ec b.n 80019ee + +08001a14 : + 8001a14: b510 push {r4, lr} + 8001a16: 2386 movs r3, #134 ; 0x86 + 8001a18: 009b lsls r3, r3, #2 + 8001a1a: 58c2 ldr r2, [r0, r3] + 8001a1c: 2a00 cmp r2, #0 + 8001a1e: d017 beq.n 8001a50 + 8001a20: 7c04 ldrb r4, [r0, #16] + 8001a22: 2c00 cmp r4, #0 + 8001a24: d10a bne.n 8001a3c + 8001a26: 3b99 subs r3, #153 ; 0x99 + 8001a28: 3bff subs r3, #255 ; 0xff + 8001a2a: 2181 movs r1, #129 ; 0x81 + 8001a2c: 0089 lsls r1, r1, #2 + 8001a2e: 5852 ldr r2, [r2, r1] + 8001a30: 009b lsls r3, r3, #2 + 8001a32: 2101 movs r1, #1 + 8001a34: f001 fab9 bl 8002faa + 8001a38: 0020 movs r0, r4 + 8001a3a: bd10 pop {r4, pc} + 8001a3c: 2381 movs r3, #129 ; 0x81 + 8001a3e: 009b lsls r3, r3, #2 + 8001a40: 58d2 ldr r2, [r2, r3] + 8001a42: 3bc5 subs r3, #197 ; 0xc5 + 8001a44: 3bff subs r3, #255 ; 0xff + 8001a46: 2101 movs r1, #1 + 8001a48: f001 faaf bl 8002faa + 8001a4c: 2400 movs r4, #0 + 8001a4e: e7f3 b.n 8001a38 + 8001a50: 2402 movs r4, #2 + 8001a52: e7f1 b.n 8001a38 + +08001a54 : + 8001a54: b510 push {r4, lr} + 8001a56: 2800 cmp r0, #0 + 8001a58: d016 beq.n 8001a88 + 8001a5a: 2385 movs r3, #133 ; 0x85 + 8001a5c: 009b lsls r3, r3, #2 + 8001a5e: 58c3 ldr r3, [r0, r3] + 8001a60: 2b00 cmp r3, #0 + 8001a62: d003 beq.n 8001a6c + 8001a64: 2385 movs r3, #133 ; 0x85 + 8001a66: 009b lsls r3, r3, #2 + 8001a68: 2400 movs r4, #0 + 8001a6a: 50c4 str r4, [r0, r3] + 8001a6c: 2900 cmp r1, #0 + 8001a6e: d002 beq.n 8001a76 + 8001a70: 2384 movs r3, #132 ; 0x84 + 8001a72: 009b lsls r3, r3, #2 + 8001a74: 50c1 str r1, [r0, r3] + 8001a76: 23fe movs r3, #254 ; 0xfe + 8001a78: 005b lsls r3, r3, #1 + 8001a7a: 2101 movs r1, #1 + 8001a7c: 54c1 strb r1, [r0, r3] + 8001a7e: 7002 strb r2, [r0, #0] + 8001a80: f001 f9f6 bl 8002e70 + 8001a84: 2000 movs r0, #0 + 8001a86: bd10 pop {r4, pc} + 8001a88: 2002 movs r0, #2 + 8001a8a: e7fc b.n 8001a86 + +08001a8c : + 8001a8c: 2900 cmp r1, #0 + 8001a8e: d004 beq.n 8001a9a + 8001a90: 2385 movs r3, #133 ; 0x85 + 8001a92: 009b lsls r3, r3, #2 + 8001a94: 50c1 str r1, [r0, r3] + 8001a96: 2000 movs r0, #0 + 8001a98: 4770 bx lr + 8001a9a: 2002 movs r0, #2 + 8001a9c: e7fc b.n 8001a98 + +08001a9e : + 8001a9e: b510 push {r4, lr} + 8001aa0: f001 fa28 bl 8002ef4 + 8001aa4: 2000 movs r0, #0 + 8001aa6: bd10 pop {r4, pc} + +08001aa8 : + 8001aa8: b510 push {r4, lr} + 8001aaa: 2385 movs r3, #133 ; 0x85 + 8001aac: 009b lsls r3, r3, #2 + 8001aae: 58c3 ldr r3, [r0, r3] + 8001ab0: 2b00 cmp r3, #0 + 8001ab2: d004 beq.n 8001abe + 8001ab4: 681b ldr r3, [r3, #0] + 8001ab6: 4798 blx r3 + 8001ab8: 2800 cmp r0, #0 + 8001aba: d102 bne.n 8001ac2 + 8001abc: bd10 pop {r4, pc} + 8001abe: 2002 movs r0, #2 + 8001ac0: e7fc b.n 8001abc + 8001ac2: 2002 movs r0, #2 + 8001ac4: e7fa b.n 8001abc + +08001ac6 : + 8001ac6: b510 push {r4, lr} + 8001ac8: 2385 movs r3, #133 ; 0x85 + 8001aca: 009b lsls r3, r3, #2 + 8001acc: 58c3 ldr r3, [r0, r3] + 8001ace: 685b ldr r3, [r3, #4] + 8001ad0: 4798 blx r3 + 8001ad2: 2000 movs r0, #0 + 8001ad4: bd10 pop {r4, pc} + ... + +08001ad8 : + 8001ad8: b570 push {r4, r5, r6, lr} + 8001ada: 0004 movs r4, r0 + 8001adc: 2382 movs r3, #130 ; 0x82 + 8001ade: 009b lsls r3, r3, #2 + 8001ae0: 18c5 adds r5, r0, r3 + 8001ae2: 0028 movs r0, r5 + 8001ae4: f000 f913 bl 8001d0e + 8001ae8: 23fa movs r3, #250 ; 0xfa + 8001aea: 005b lsls r3, r3, #1 + 8001aec: 2201 movs r2, #1 + 8001aee: 50e2 str r2, [r4, r3] + 8001af0: 4b12 ldr r3, [pc, #72] ; (8001b3c ) + 8001af2: 5ae2 ldrh r2, [r4, r3] + 8001af4: 3b16 subs r3, #22 + 8001af6: 50e2 str r2, [r4, r3] + 8001af8: 3310 adds r3, #16 + 8001afa: 5ce1 ldrb r1, [r4, r3] + 8001afc: 3bea subs r3, #234 ; 0xea + 8001afe: 3bff subs r3, #255 ; 0xff + 8001b00: 400b ands r3, r1 + 8001b02: 2b01 cmp r3, #1 + 8001b04: d00f beq.n 8001b26 + 8001b06: 2b02 cmp r3, #2 + 8001b08: d012 beq.n 8001b30 + 8001b0a: 2b00 cmp r3, #0 + 8001b0c: d005 beq.n 8001b1a + 8001b0e: 237f movs r3, #127 ; 0x7f + 8001b10: 4399 bics r1, r3 + 8001b12: 0020 movs r0, r4 + 8001b14: f001 fa0c bl 8002f30 + 8001b18: e003 b.n 8001b22 + 8001b1a: 0029 movs r1, r5 + 8001b1c: 0020 movs r0, r4 + 8001b1e: f000 f915 bl 8001d4c + 8001b22: 2000 movs r0, #0 + 8001b24: bd70 pop {r4, r5, r6, pc} + 8001b26: 0029 movs r1, r5 + 8001b28: 0020 movs r0, r4 + 8001b2a: f000 faab bl 8002084 + 8001b2e: e7f8 b.n 8001b22 + 8001b30: 0029 movs r1, r5 + 8001b32: 0020 movs r0, r4 + 8001b34: f000 fac4 bl 80020c0 + 8001b38: e7f3 b.n 8001b22 + 8001b3a: 46c0 nop ; (mov r8, r8) + 8001b3c: 0000020e .word 0x0000020e + +08001b40 : + 8001b40: b510 push {r4, lr} + 8001b42: 0004 movs r4, r0 + 8001b44: 0013 movs r3, r2 + 8001b46: 2900 cmp r1, #0 + 8001b48: d12a bne.n 8001ba0 + 8001b4a: 22fa movs r2, #250 ; 0xfa + 8001b4c: 0052 lsls r2, r2, #1 + 8001b4e: 5882 ldr r2, [r0, r2] + 8001b50: 2a03 cmp r2, #3 + 8001b52: d001 beq.n 8001b58 + 8001b54: 2000 movs r0, #0 + 8001b56: bd10 pop {r4, pc} + 8001b58: 1d42 adds r2, r0, #5 + 8001b5a: 32ff adds r2, #255 ; 0xff + 8001b5c: 6891 ldr r1, [r2, #8] + 8001b5e: 68d2 ldr r2, [r2, #12] + 8001b60: 4291 cmp r1, r2 + 8001b62: d80e bhi.n 8001b82 + 8001b64: 2385 movs r3, #133 ; 0x85 + 8001b66: 009b lsls r3, r3, #2 + 8001b68: 58c3 ldr r3, [r0, r3] + 8001b6a: 691b ldr r3, [r3, #16] + 8001b6c: 2b00 cmp r3, #0 + 8001b6e: d004 beq.n 8001b7a + 8001b70: 22fe movs r2, #254 ; 0xfe + 8001b72: 0052 lsls r2, r2, #1 + 8001b74: 5c82 ldrb r2, [r0, r2] + 8001b76: 2a03 cmp r2, #3 + 8001b78: d010 beq.n 8001b9c + 8001b7a: 0020 movs r0, r4 + 8001b7c: f000 fb60 bl 8002240 + 8001b80: e7e8 b.n 8001b54 + 8001b82: 1a89 subs r1, r1, r2 + 8001b84: 3005 adds r0, #5 + 8001b86: 30ff adds r0, #255 ; 0xff + 8001b88: 6081 str r1, [r0, #8] + 8001b8a: 428a cmp r2, r1 + 8001b8c: d900 bls.n 8001b90 + 8001b8e: 000a movs r2, r1 + 8001b90: b292 uxth r2, r2 + 8001b92: 0019 movs r1, r3 + 8001b94: 0020 movs r0, r4 + 8001b96: f000 fb4b bl 8002230 + 8001b9a: e7db b.n 8001b54 + 8001b9c: 4798 blx r3 + 8001b9e: e7ec b.n 8001b7a + 8001ba0: 2385 movs r3, #133 ; 0x85 + 8001ba2: 009b lsls r3, r3, #2 + 8001ba4: 58c3 ldr r3, [r0, r3] + 8001ba6: 699b ldr r3, [r3, #24] + 8001ba8: 2b00 cmp r3, #0 + 8001baa: d0d3 beq.n 8001b54 + 8001bac: 22fe movs r2, #254 ; 0xfe + 8001bae: 0052 lsls r2, r2, #1 + 8001bb0: 5c82 ldrb r2, [r0, r2] + 8001bb2: 2a03 cmp r2, #3 + 8001bb4: d1ce bne.n 8001b54 + 8001bb6: 4798 blx r3 + 8001bb8: e7cc b.n 8001b54 + +08001bba : + 8001bba: b570 push {r4, r5, r6, lr} + 8001bbc: 0004 movs r4, r0 + 8001bbe: 0013 movs r3, r2 + 8001bc0: 2900 cmp r1, #0 + 8001bc2: d14f bne.n 8001c64 + 8001bc4: 22fa movs r2, #250 ; 0xfa + 8001bc6: 0052 lsls r2, r2, #1 + 8001bc8: 5882 ldr r2, [r0, r2] + 8001bca: 2a02 cmp r2, #2 + 8001bcc: d006 beq.n 8001bdc + 8001bce: 2380 movs r3, #128 ; 0x80 + 8001bd0: 009b lsls r3, r3, #2 + 8001bd2: 5ce3 ldrb r3, [r4, r3] + 8001bd4: 2b01 cmp r3, #1 + 8001bd6: d040 beq.n 8001c5a + 8001bd8: 2000 movs r0, #0 + 8001bda: bd70 pop {r4, r5, r6, pc} + 8001bdc: 69c2 ldr r2, [r0, #28] + 8001bde: 6a05 ldr r5, [r0, #32] + 8001be0: 42aa cmp r2, r5 + 8001be2: d81c bhi.n 8001c1e + 8001be4: 6986 ldr r6, [r0, #24] + 8001be6: 0029 movs r1, r5 + 8001be8: 0030 movs r0, r6 + 8001bea: f7fe fb13 bl 8000214 <__aeabi_uidivmod> + 8001bee: 2900 cmp r1, #0 + 8001bf0: d106 bne.n 8001c00 + 8001bf2: 42b5 cmp r5, r6 + 8001bf4: d804 bhi.n 8001c00 + 8001bf6: 23fc movs r3, #252 ; 0xfc + 8001bf8: 005b lsls r3, r3, #1 + 8001bfa: 58e3 ldr r3, [r4, r3] + 8001bfc: 429e cmp r6, r3 + 8001bfe: d31b bcc.n 8001c38 + 8001c00: 2385 movs r3, #133 ; 0x85 + 8001c02: 009b lsls r3, r3, #2 + 8001c04: 58e3 ldr r3, [r4, r3] + 8001c06: 68db ldr r3, [r3, #12] + 8001c08: 2b00 cmp r3, #0 + 8001c0a: d004 beq.n 8001c16 + 8001c0c: 22fe movs r2, #254 ; 0xfe + 8001c0e: 0052 lsls r2, r2, #1 + 8001c10: 5ca2 ldrb r2, [r4, r2] + 8001c12: 2a03 cmp r2, #3 + 8001c14: d01e beq.n 8001c54 + 8001c16: 0020 movs r0, r4 + 8001c18: f000 fb1e bl 8002258 + 8001c1c: e7d7 b.n 8001bce + 8001c1e: 1b52 subs r2, r2, r5 + 8001c20: 61c2 str r2, [r0, #28] + 8001c22: b292 uxth r2, r2 + 8001c24: 0019 movs r1, r3 + 8001c26: f000 faeb bl 8002200 + 8001c2a: 2300 movs r3, #0 + 8001c2c: 2200 movs r2, #0 + 8001c2e: 2100 movs r1, #0 + 8001c30: 0020 movs r0, r4 + 8001c32: f001 f9ba bl 8002faa + 8001c36: e7ca b.n 8001bce + 8001c38: 2200 movs r2, #0 + 8001c3a: 0020 movs r0, r4 + 8001c3c: f000 fae0 bl 8002200 + 8001c40: 23fc movs r3, #252 ; 0xfc + 8001c42: 005b lsls r3, r3, #1 + 8001c44: 2200 movs r2, #0 + 8001c46: 50e2 str r2, [r4, r3] + 8001c48: 2300 movs r3, #0 + 8001c4a: 2100 movs r1, #0 + 8001c4c: 0020 movs r0, r4 + 8001c4e: f001 f9ac bl 8002faa + 8001c52: e7bc b.n 8001bce + 8001c54: 0020 movs r0, r4 + 8001c56: 4798 blx r3 + 8001c58: e7dd b.n 8001c16 + 8001c5a: 2380 movs r3, #128 ; 0x80 + 8001c5c: 009b lsls r3, r3, #2 + 8001c5e: 2200 movs r2, #0 + 8001c60: 54e2 strb r2, [r4, r3] + 8001c62: e7b9 b.n 8001bd8 + 8001c64: 2385 movs r3, #133 ; 0x85 + 8001c66: 009b lsls r3, r3, #2 + 8001c68: 58c3 ldr r3, [r0, r3] + 8001c6a: 695b ldr r3, [r3, #20] + 8001c6c: 2b00 cmp r3, #0 + 8001c6e: d0b3 beq.n 8001bd8 + 8001c70: 22fe movs r2, #254 ; 0xfe + 8001c72: 0052 lsls r2, r2, #1 + 8001c74: 5c82 ldrb r2, [r0, r2] + 8001c76: 2a03 cmp r2, #3 + 8001c78: d1ae bne.n 8001bd8 + 8001c7a: 4798 blx r3 + 8001c7c: e7ac b.n 8001bd8 + +08001c7e : + 8001c7e: b570 push {r4, r5, r6, lr} + 8001c80: 0004 movs r4, r0 + 8001c82: 2340 movs r3, #64 ; 0x40 + 8001c84: 2200 movs r2, #0 + 8001c86: 2100 movs r1, #0 + 8001c88: f001 f93d bl 8002f06 + 8001c8c: 2540 movs r5, #64 ; 0x40 + 8001c8e: 2388 movs r3, #136 ; 0x88 + 8001c90: 005b lsls r3, r3, #1 + 8001c92: 50e5 str r5, [r4, r3] + 8001c94: 3bd0 subs r3, #208 ; 0xd0 + 8001c96: 2200 movs r2, #0 + 8001c98: 2180 movs r1, #128 ; 0x80 + 8001c9a: 0020 movs r0, r4 + 8001c9c: f001 f933 bl 8002f06 + 8001ca0: 6225 str r5, [r4, #32] + 8001ca2: 23fe movs r3, #254 ; 0xfe + 8001ca4: 005b lsls r3, r3, #1 + 8001ca6: 2201 movs r2, #1 + 8001ca8: 54e2 strb r2, [r4, r3] + 8001caa: 331c adds r3, #28 + 8001cac: 58e3 ldr r3, [r4, r3] + 8001cae: 2b00 cmp r3, #0 + 8001cb0: d006 beq.n 8001cc0 + 8001cb2: 7921 ldrb r1, [r4, #4] + 8001cb4: 2385 movs r3, #133 ; 0x85 + 8001cb6: 009b lsls r3, r3, #2 + 8001cb8: 58e3 ldr r3, [r4, r3] + 8001cba: 685b ldr r3, [r3, #4] + 8001cbc: 0020 movs r0, r4 + 8001cbe: 4798 blx r3 + 8001cc0: 2000 movs r0, #0 + 8001cc2: bd70 pop {r4, r5, r6, pc} + +08001cc4 : + 8001cc4: 7401 strb r1, [r0, #16] + 8001cc6: 2000 movs r0, #0 + 8001cc8: 4770 bx lr + +08001cca : + 8001cca: 23fe movs r3, #254 ; 0xfe + 8001ccc: 005b lsls r3, r3, #1 + 8001cce: 5cc1 ldrb r1, [r0, r3] + 8001cd0: 22fe movs r2, #254 ; 0xfe + 8001cd2: 32ff adds r2, #255 ; 0xff + 8001cd4: 5481 strb r1, [r0, r2] + 8001cd6: 3afa subs r2, #250 ; 0xfa + 8001cd8: 3aff subs r2, #255 ; 0xff + 8001cda: 54c2 strb r2, [r0, r3] + 8001cdc: 2000 movs r0, #0 + 8001cde: 4770 bx lr + +08001ce0 : + 8001ce0: 23fe movs r3, #254 ; 0xfe + 8001ce2: 33ff adds r3, #255 ; 0xff + 8001ce4: 5cc2 ldrb r2, [r0, r3] + 8001ce6: 3b01 subs r3, #1 + 8001ce8: 54c2 strb r2, [r0, r3] + 8001cea: 2000 movs r0, #0 + 8001cec: 4770 bx lr + +08001cee : + 8001cee: b510 push {r4, lr} + 8001cf0: 23fe movs r3, #254 ; 0xfe + 8001cf2: 005b lsls r3, r3, #1 + 8001cf4: 5cc3 ldrb r3, [r0, r3] + 8001cf6: 2b03 cmp r3, #3 + 8001cf8: d001 beq.n 8001cfe + 8001cfa: 2000 movs r0, #0 + 8001cfc: bd10 pop {r4, pc} + 8001cfe: 2385 movs r3, #133 ; 0x85 + 8001d00: 009b lsls r3, r3, #2 + 8001d02: 58c3 ldr r3, [r0, r3] + 8001d04: 69db ldr r3, [r3, #28] + 8001d06: 2b00 cmp r3, #0 + 8001d08: d0f7 beq.n 8001cfa + 8001d0a: 4798 blx r3 + 8001d0c: e7f5 b.n 8001cfa + +08001d0e : + 8001d0e: 780b ldrb r3, [r1, #0] + 8001d10: 7003 strb r3, [r0, #0] + 8001d12: 784b ldrb r3, [r1, #1] + 8001d14: 7043 strb r3, [r0, #1] + 8001d16: 78ca ldrb r2, [r1, #3] + 8001d18: 0212 lsls r2, r2, #8 + 8001d1a: 788b ldrb r3, [r1, #2] + 8001d1c: 189b adds r3, r3, r2 + 8001d1e: 8043 strh r3, [r0, #2] + 8001d20: 794a ldrb r2, [r1, #5] + 8001d22: 0212 lsls r2, r2, #8 + 8001d24: 790b ldrb r3, [r1, #4] + 8001d26: 189b adds r3, r3, r2 + 8001d28: 8083 strh r3, [r0, #4] + 8001d2a: 79ca ldrb r2, [r1, #7] + 8001d2c: 0212 lsls r2, r2, #8 + 8001d2e: 798b ldrb r3, [r1, #6] + 8001d30: 189b adds r3, r3, r2 + 8001d32: 80c3 strh r3, [r0, #6] + 8001d34: 4770 bx lr + +08001d36 : + 8001d36: b510 push {r4, lr} + 8001d38: 0004 movs r4, r0 + 8001d3a: 2180 movs r1, #128 ; 0x80 + 8001d3c: f001 f8f8 bl 8002f30 + 8001d40: 2100 movs r1, #0 + 8001d42: 0020 movs r0, r4 + 8001d44: f001 f8f4 bl 8002f30 + 8001d48: bd10 pop {r4, pc} + ... + +08001d4c : + 8001d4c: b530 push {r4, r5, lr} + 8001d4e: b083 sub sp, #12 + 8001d50: 0005 movs r5, r0 + 8001d52: 000c movs r4, r1 + 8001d54: 784b ldrb r3, [r1, #1] + 8001d56: 2b09 cmp r3, #9 + 8001d58: d900 bls.n 8001d5c + 8001d5a: e18b b.n 8002074 + 8001d5c: 009b lsls r3, r3, #2 + 8001d5e: 4ac1 ldr r2, [pc, #772] ; (8002064 ) + 8001d60: 58d3 ldr r3, [r2, r3] + 8001d62: 469f mov pc, r3 + 8001d64: 884b ldrh r3, [r1, #2] + 8001d66: 0a1a lsrs r2, r3, #8 + 8001d68: 2a07 cmp r2, #7 + 8001d6a: d900 bls.n 8001d6e + 8001d6c: e099 b.n 8001ea2 + 8001d6e: 0092 lsls r2, r2, #2 + 8001d70: 49bd ldr r1, [pc, #756] ; (8002068 ) + 8001d72: 588a ldr r2, [r1, r2] + 8001d74: 4697 mov pc, r2 + 8001d76: 7c00 ldrb r0, [r0, #16] + 8001d78: 2384 movs r3, #132 ; 0x84 + 8001d7a: 009b lsls r3, r3, #2 + 8001d7c: 58eb ldr r3, [r5, r3] + 8001d7e: 681b ldr r3, [r3, #0] + 8001d80: 466a mov r2, sp + 8001d82: 1d91 adds r1, r2, #6 + 8001d84: 4798 blx r3 + 8001d86: 466b mov r3, sp + 8001d88: 3306 adds r3, #6 + 8001d8a: 881b ldrh r3, [r3, #0] + 8001d8c: 2b00 cmp r3, #0 + 8001d8e: d100 bne.n 8001d92 + 8001d90: e174 b.n 800207c + 8001d92: 88e2 ldrh r2, [r4, #6] + 8001d94: 2a00 cmp r2, #0 + 8001d96: d100 bne.n 8001d9a + 8001d98: e170 b.n 800207c + 8001d9a: 1c19 adds r1, r3, #0 + 8001d9c: 4293 cmp r3, r2 + 8001d9e: d900 bls.n 8001da2 + 8001da0: 1c11 adds r1, r2, #0 + 8001da2: b28a uxth r2, r1 + 8001da4: 466b mov r3, sp + 8001da6: 80d9 strh r1, [r3, #6] + 8001da8: 0001 movs r1, r0 + 8001daa: 0028 movs r0, r5 + 8001dac: f000 fa1a bl 80021e4 + 8001db0: e164 b.n 800207c + 8001db2: 7c03 ldrb r3, [r0, #16] + 8001db4: 2b00 cmp r3, #0 + 8001db6: d109 bne.n 8001dcc + 8001db8: 2385 movs r3, #133 ; 0x85 + 8001dba: 009b lsls r3, r3, #2 + 8001dbc: 58c3 ldr r3, [r0, r3] + 8001dbe: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001dc0: 466a mov r2, sp + 8001dc2: 1d90 adds r0, r2, #6 + 8001dc4: 4798 blx r3 + 8001dc6: 2302 movs r3, #2 + 8001dc8: 7043 strb r3, [r0, #1] + 8001dca: e7dc b.n 8001d86 + 8001dcc: 2385 movs r3, #133 ; 0x85 + 8001dce: 009b lsls r3, r3, #2 + 8001dd0: 58c3 ldr r3, [r0, r3] + 8001dd2: 6adb ldr r3, [r3, #44] ; 0x2c + 8001dd4: 466a mov r2, sp + 8001dd6: 1d90 adds r0, r2, #6 + 8001dd8: 4798 blx r3 + 8001dda: 2302 movs r3, #2 + 8001ddc: 7043 strb r3, [r0, #1] + 8001dde: e7d2 b.n 8001d86 + 8001de0: b2da uxtb r2, r3 + 8001de2: 2a05 cmp r2, #5 + 8001de4: d839 bhi.n 8001e5a + 8001de6: 0093 lsls r3, r2, #2 + 8001de8: 4aa0 ldr r2, [pc, #640] ; (800206c ) + 8001dea: 58d3 ldr r3, [r2, r3] + 8001dec: 469f mov pc, r3 + 8001dee: 7c00 ldrb r0, [r0, #16] + 8001df0: 2384 movs r3, #132 ; 0x84 + 8001df2: 009b lsls r3, r3, #2 + 8001df4: 58eb ldr r3, [r5, r3] + 8001df6: 685b ldr r3, [r3, #4] + 8001df8: 466a mov r2, sp + 8001dfa: 1d91 adds r1, r2, #6 + 8001dfc: 4798 blx r3 + 8001dfe: e7c2 b.n 8001d86 + 8001e00: 7c00 ldrb r0, [r0, #16] + 8001e02: 2384 movs r3, #132 ; 0x84 + 8001e04: 009b lsls r3, r3, #2 + 8001e06: 58eb ldr r3, [r5, r3] + 8001e08: 689b ldr r3, [r3, #8] + 8001e0a: 466a mov r2, sp + 8001e0c: 1d91 adds r1, r2, #6 + 8001e0e: 4798 blx r3 + 8001e10: e7b9 b.n 8001d86 + 8001e12: 7c00 ldrb r0, [r0, #16] + 8001e14: 2384 movs r3, #132 ; 0x84 + 8001e16: 009b lsls r3, r3, #2 + 8001e18: 58eb ldr r3, [r5, r3] + 8001e1a: 68db ldr r3, [r3, #12] + 8001e1c: 466a mov r2, sp + 8001e1e: 1d91 adds r1, r2, #6 + 8001e20: 4798 blx r3 + 8001e22: e7b0 b.n 8001d86 + 8001e24: 7c00 ldrb r0, [r0, #16] + 8001e26: 2384 movs r3, #132 ; 0x84 + 8001e28: 009b lsls r3, r3, #2 + 8001e2a: 58eb ldr r3, [r5, r3] + 8001e2c: 691b ldr r3, [r3, #16] + 8001e2e: 466a mov r2, sp + 8001e30: 1d91 adds r1, r2, #6 + 8001e32: 4798 blx r3 + 8001e34: e7a7 b.n 8001d86 + 8001e36: 7c00 ldrb r0, [r0, #16] + 8001e38: 2384 movs r3, #132 ; 0x84 + 8001e3a: 009b lsls r3, r3, #2 + 8001e3c: 58eb ldr r3, [r5, r3] + 8001e3e: 695b ldr r3, [r3, #20] + 8001e40: 466a mov r2, sp + 8001e42: 1d91 adds r1, r2, #6 + 8001e44: 4798 blx r3 + 8001e46: e79e b.n 8001d86 + 8001e48: 7c00 ldrb r0, [r0, #16] + 8001e4a: 2384 movs r3, #132 ; 0x84 + 8001e4c: 009b lsls r3, r3, #2 + 8001e4e: 58eb ldr r3, [r5, r3] + 8001e50: 699b ldr r3, [r3, #24] + 8001e52: 466a mov r2, sp + 8001e54: 1d91 adds r1, r2, #6 + 8001e56: 4798 blx r3 + 8001e58: e795 b.n 8001d86 + 8001e5a: 0021 movs r1, r4 + 8001e5c: f7ff ff6b bl 8001d36 + 8001e60: e10c b.n 800207c + 8001e62: 7c03 ldrb r3, [r0, #16] + 8001e64: 2b00 cmp r3, #0 + 8001e66: d107 bne.n 8001e78 + 8001e68: 2385 movs r3, #133 ; 0x85 + 8001e6a: 009b lsls r3, r3, #2 + 8001e6c: 58c3 ldr r3, [r0, r3] + 8001e6e: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001e70: 466a mov r2, sp + 8001e72: 1d90 adds r0, r2, #6 + 8001e74: 4798 blx r3 + 8001e76: e786 b.n 8001d86 + 8001e78: 0021 movs r1, r4 + 8001e7a: f7ff ff5c bl 8001d36 + 8001e7e: e0fd b.n 800207c + 8001e80: 7c03 ldrb r3, [r0, #16] + 8001e82: 2b00 cmp r3, #0 + 8001e84: d109 bne.n 8001e9a + 8001e86: 2385 movs r3, #133 ; 0x85 + 8001e88: 009b lsls r3, r3, #2 + 8001e8a: 58c3 ldr r3, [r0, r3] + 8001e8c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001e8e: 466a mov r2, sp + 8001e90: 1d90 adds r0, r2, #6 + 8001e92: 4798 blx r3 + 8001e94: 2307 movs r3, #7 + 8001e96: 7043 strb r3, [r0, #1] + 8001e98: e775 b.n 8001d86 + 8001e9a: 0021 movs r1, r4 + 8001e9c: f7ff ff4b bl 8001d36 + 8001ea0: e0ec b.n 800207c + 8001ea2: 0021 movs r1, r4 + 8001ea4: 0028 movs r0, r5 + 8001ea6: f7ff ff46 bl 8001d36 + 8001eaa: e0e7 b.n 800207c + 8001eac: 888b ldrh r3, [r1, #4] + 8001eae: 2b00 cmp r3, #0 + 8001eb0: d122 bne.n 8001ef8 + 8001eb2: 88cb ldrh r3, [r1, #6] + 8001eb4: 2b00 cmp r3, #0 + 8001eb6: d11f bne.n 8001ef8 + 8001eb8: 33fd adds r3, #253 ; 0xfd + 8001eba: 33ff adds r3, #255 ; 0xff + 8001ebc: 5cc3 ldrb r3, [r0, r3] + 8001ebe: 2b03 cmp r3, #3 + 8001ec0: d012 beq.n 8001ee8 + 8001ec2: 884b ldrh r3, [r1, #2] + 8001ec4: 247f movs r4, #127 ; 0x7f + 8001ec6: 401c ands r4, r3 + 8001ec8: 23ff movs r3, #255 ; 0xff + 8001eca: 005b lsls r3, r3, #1 + 8001ecc: 54c4 strb r4, [r0, r3] + 8001ece: 0021 movs r1, r4 + 8001ed0: f001 f859 bl 8002f86 + 8001ed4: 0028 movs r0, r5 + 8001ed6: f000 f9b3 bl 8002240 + 8001eda: 2c00 cmp r4, #0 + 8001edc: d007 beq.n 8001eee + 8001ede: 23fe movs r3, #254 ; 0xfe + 8001ee0: 005b lsls r3, r3, #1 + 8001ee2: 2202 movs r2, #2 + 8001ee4: 54ea strb r2, [r5, r3] + 8001ee6: e0c9 b.n 800207c + 8001ee8: f7ff ff25 bl 8001d36 + 8001eec: e0c6 b.n 800207c + 8001eee: 23fe movs r3, #254 ; 0xfe + 8001ef0: 005b lsls r3, r3, #1 + 8001ef2: 2201 movs r2, #1 + 8001ef4: 54ea strb r2, [r5, r3] + 8001ef6: e0c1 b.n 800207c + 8001ef8: 0021 movs r1, r4 + 8001efa: 0028 movs r0, r5 + 8001efc: f7ff ff1b bl 8001d36 + 8001f00: e0bc b.n 800207c + 8001f02: 788b ldrb r3, [r1, #2] + 8001f04: 4a5a ldr r2, [pc, #360] ; (8002070 ) + 8001f06: 7013 strb r3, [r2, #0] + 8001f08: 2b01 cmp r3, #1 + 8001f0a: d809 bhi.n 8001f20 + 8001f0c: 22fe movs r2, #254 ; 0xfe + 8001f0e: 0052 lsls r2, r2, #1 + 8001f10: 5c82 ldrb r2, [r0, r2] + 8001f12: 2a02 cmp r2, #2 + 8001f14: d007 beq.n 8001f26 + 8001f16: 2a03 cmp r2, #3 + 8001f18: d01e beq.n 8001f58 + 8001f1a: f7ff ff0c bl 8001d36 + 8001f1e: e0ad b.n 800207c + 8001f20: f7ff ff09 bl 8001d36 + 8001f24: e0aa b.n 800207c + 8001f26: 2b00 cmp r3, #0 + 8001f28: d013 beq.n 8001f52 + 8001f2a: 2301 movs r3, #1 + 8001f2c: 6043 str r3, [r0, #4] + 8001f2e: 33fc adds r3, #252 ; 0xfc + 8001f30: 33ff adds r3, #255 ; 0xff + 8001f32: 2203 movs r2, #3 + 8001f34: 54c2 strb r2, [r0, r3] + 8001f36: 2101 movs r1, #1 + 8001f38: f7ff fdb6 bl 8001aa8 + 8001f3c: 2802 cmp r0, #2 + 8001f3e: d003 beq.n 8001f48 + 8001f40: 0028 movs r0, r5 + 8001f42: f000 f97d bl 8002240 + 8001f46: e099 b.n 800207c + 8001f48: 0021 movs r1, r4 + 8001f4a: 0028 movs r0, r5 + 8001f4c: f7ff fef3 bl 8001d36 + 8001f50: e094 b.n 800207c + 8001f52: f000 f975 bl 8002240 + 8001f56: e091 b.n 800207c + 8001f58: 2b00 cmp r3, #0 + 8001f5a: d011 beq.n 8001f80 + 8001f5c: 6841 ldr r1, [r0, #4] + 8001f5e: 2901 cmp r1, #1 + 8001f60: d020 beq.n 8001fa4 + 8001f62: b2c9 uxtb r1, r1 + 8001f64: f7ff fdaf bl 8001ac6 + 8001f68: 4b41 ldr r3, [pc, #260] ; (8002070 ) + 8001f6a: 7819 ldrb r1, [r3, #0] + 8001f6c: 6069 str r1, [r5, #4] + 8001f6e: 0028 movs r0, r5 + 8001f70: f7ff fd9a bl 8001aa8 + 8001f74: 2802 cmp r0, #2 + 8001f76: d010 beq.n 8001f9a + 8001f78: 0028 movs r0, r5 + 8001f7a: f000 f961 bl 8002240 + 8001f7e: e07d b.n 800207c + 8001f80: 33fd adds r3, #253 ; 0xfd + 8001f82: 33ff adds r3, #255 ; 0xff + 8001f84: 2202 movs r2, #2 + 8001f86: 54c2 strb r2, [r0, r3] + 8001f88: 2300 movs r3, #0 + 8001f8a: 6043 str r3, [r0, #4] + 8001f8c: 2100 movs r1, #0 + 8001f8e: f7ff fd9a bl 8001ac6 + 8001f92: 0028 movs r0, r5 + 8001f94: f000 f954 bl 8002240 + 8001f98: e070 b.n 800207c + 8001f9a: 0021 movs r1, r4 + 8001f9c: 0028 movs r0, r5 + 8001f9e: f7ff feca bl 8001d36 + 8001fa2: e06b b.n 800207c + 8001fa4: f000 f94c bl 8002240 + 8001fa8: e068 b.n 800207c + 8001faa: 88cb ldrh r3, [r1, #6] + 8001fac: 2b01 cmp r3, #1 + 8001fae: d109 bne.n 8001fc4 + 8001fb0: 23fe movs r3, #254 ; 0xfe + 8001fb2: 005b lsls r3, r3, #1 + 8001fb4: 5cc3 ldrb r3, [r0, r3] + 8001fb6: 2b02 cmp r3, #2 + 8001fb8: d007 beq.n 8001fca + 8001fba: 2b03 cmp r3, #3 + 8001fbc: d00d beq.n 8001fda + 8001fbe: f7ff feba bl 8001d36 + 8001fc2: e05b b.n 800207c + 8001fc4: f7ff feb7 bl 8001d36 + 8001fc8: e058 b.n 800207c + 8001fca: 2300 movs r3, #0 + 8001fcc: 6083 str r3, [r0, #8] + 8001fce: 0001 movs r1, r0 + 8001fd0: 3108 adds r1, #8 + 8001fd2: 2201 movs r2, #1 + 8001fd4: f000 f906 bl 80021e4 + 8001fd8: e050 b.n 800207c + 8001fda: 1d01 adds r1, r0, #4 + 8001fdc: 2201 movs r2, #1 + 8001fde: f000 f901 bl 80021e4 + 8001fe2: e04b b.n 800207c + 8001fe4: 23fe movs r3, #254 ; 0xfe + 8001fe6: 005b lsls r3, r3, #1 + 8001fe8: 5cc3 ldrb r3, [r0, r3] + 8001fea: 3b02 subs r3, #2 + 8001fec: 2b01 cmp r3, #1 + 8001fee: d80f bhi.n 8002010 + 8001ff0: 2301 movs r3, #1 + 8001ff2: 60c3 str r3, [r0, #12] + 8001ff4: 2381 movs r3, #129 ; 0x81 + 8001ff6: 009b lsls r3, r3, #2 + 8001ff8: 58c3 ldr r3, [r0, r3] + 8001ffa: 2b00 cmp r3, #0 + 8001ffc: d001 beq.n 8002002 + 8001ffe: 2303 movs r3, #3 + 8002000: 60c3 str r3, [r0, #12] + 8002002: 0029 movs r1, r5 + 8002004: 310c adds r1, #12 + 8002006: 2202 movs r2, #2 + 8002008: 0028 movs r0, r5 + 800200a: f000 f8eb bl 80021e4 + 800200e: e035 b.n 800207c + 8002010: f7ff fe91 bl 8001d36 + 8002014: e032 b.n 800207c + 8002016: 884b ldrh r3, [r1, #2] + 8002018: 2b01 cmp r3, #1 + 800201a: d12f bne.n 800207c + 800201c: 2381 movs r3, #129 ; 0x81 + 800201e: 009b lsls r3, r3, #2 + 8002020: 2201 movs r2, #1 + 8002022: 50c2 str r2, [r0, r3] + 8002024: 3310 adds r3, #16 + 8002026: 58c3 ldr r3, [r0, r3] + 8002028: 689b ldr r3, [r3, #8] + 800202a: 4798 blx r3 + 800202c: 0028 movs r0, r5 + 800202e: f000 f907 bl 8002240 + 8002032: e023 b.n 800207c + 8002034: 23fe movs r3, #254 ; 0xfe + 8002036: 005b lsls r3, r3, #1 + 8002038: 5cc3 ldrb r3, [r0, r3] + 800203a: 3b02 subs r3, #2 + 800203c: 2b01 cmp r3, #1 + 800203e: d80e bhi.n 800205e + 8002040: 884b ldrh r3, [r1, #2] + 8002042: 2b01 cmp r3, #1 + 8002044: d11a bne.n 800207c + 8002046: 2381 movs r3, #129 ; 0x81 + 8002048: 009b lsls r3, r3, #2 + 800204a: 2200 movs r2, #0 + 800204c: 50c2 str r2, [r0, r3] + 800204e: 3310 adds r3, #16 + 8002050: 58c3 ldr r3, [r0, r3] + 8002052: 689b ldr r3, [r3, #8] + 8002054: 4798 blx r3 + 8002056: 0028 movs r0, r5 + 8002058: f000 f8f2 bl 8002240 + 800205c: e00e b.n 800207c + 800205e: f7ff fe6a bl 8001d36 + 8002062: e00b b.n 800207c + 8002064: 08003174 .word 0x08003174 + 8002068: 0800319c .word 0x0800319c + 800206c: 080031bc .word 0x080031bc + 8002070: 20000191 .word 0x20000191 + 8002074: 0021 movs r1, r4 + 8002076: 0028 movs r0, r5 + 8002078: f7ff fe5d bl 8001d36 + 800207c: 2000 movs r0, #0 + 800207e: b003 add sp, #12 + 8002080: bd30 pop {r4, r5, pc} + 8002082: 46c0 nop ; (mov r8, r8) + +08002084 : + 8002084: b570 push {r4, r5, r6, lr} + 8002086: 0004 movs r4, r0 + 8002088: 000d movs r5, r1 + 800208a: 23fe movs r3, #254 ; 0xfe + 800208c: 005b lsls r3, r3, #1 + 800208e: 5cc3 ldrb r3, [r0, r3] + 8002090: 2b03 cmp r3, #3 + 8002092: d111 bne.n 80020b8 + 8002094: 790b ldrb r3, [r1, #4] + 8002096: 2b01 cmp r3, #1 + 8002098: d80b bhi.n 80020b2 + 800209a: 2385 movs r3, #133 ; 0x85 + 800209c: 009b lsls r3, r3, #2 + 800209e: 58c3 ldr r3, [r0, r3] + 80020a0: 689b ldr r3, [r3, #8] + 80020a2: 4798 blx r3 + 80020a4: 88eb ldrh r3, [r5, #6] + 80020a6: 2b00 cmp r3, #0 + 80020a8: d108 bne.n 80020bc + 80020aa: 0020 movs r0, r4 + 80020ac: f000 f8c8 bl 8002240 + 80020b0: e004 b.n 80020bc + 80020b2: f7ff fe40 bl 8001d36 + 80020b6: e001 b.n 80020bc + 80020b8: f7ff fe3d bl 8001d36 + 80020bc: 2000 movs r0, #0 + 80020be: bd70 pop {r4, r5, r6, pc} + +080020c0 : + 80020c0: b570 push {r4, r5, r6, lr} + 80020c2: 0005 movs r5, r0 + 80020c4: 000c movs r4, r1 + 80020c6: 8888 ldrh r0, [r1, #4] + 80020c8: 7909 ldrb r1, [r1, #4] + 80020ca: 7822 ldrb r2, [r4, #0] + 80020cc: 2360 movs r3, #96 ; 0x60 + 80020ce: 4013 ands r3, r2 + 80020d0: 2b20 cmp r3, #32 + 80020d2: d008 beq.n 80020e6 + 80020d4: 7863 ldrb r3, [r4, #1] + 80020d6: 2b01 cmp r3, #1 + 80020d8: d032 beq.n 8002140 + 80020da: 2b03 cmp r3, #3 + 80020dc: d00b beq.n 80020f6 + 80020de: 2b00 cmp r3, #0 + 80020e0: d054 beq.n 800218c + 80020e2: 2000 movs r0, #0 + 80020e4: bd70 pop {r4, r5, r6, pc} + 80020e6: 33f5 adds r3, #245 ; 0xf5 + 80020e8: 33ff adds r3, #255 ; 0xff + 80020ea: 58eb ldr r3, [r5, r3] + 80020ec: 689b ldr r3, [r3, #8] + 80020ee: 0021 movs r1, r4 + 80020f0: 0028 movs r0, r5 + 80020f2: 4798 blx r3 + 80020f4: e7f5 b.n 80020e2 + 80020f6: 23fe movs r3, #254 ; 0xfe + 80020f8: 005b lsls r3, r3, #1 + 80020fa: 5ceb ldrb r3, [r5, r3] + 80020fc: 2b02 cmp r3, #2 + 80020fe: d006 beq.n 800210e + 8002100: 2b03 cmp r3, #3 + 8002102: d00a beq.n 800211a + 8002104: 0021 movs r1, r4 + 8002106: 0028 movs r0, r5 + 8002108: f7ff fe15 bl 8001d36 + 800210c: e7e9 b.n 80020e2 + 800210e: 064b lsls r3, r1, #25 + 8002110: d0e7 beq.n 80020e2 + 8002112: 0028 movs r0, r5 + 8002114: f000 ff0c bl 8002f30 + 8002118: e7e3 b.n 80020e2 + 800211a: 8863 ldrh r3, [r4, #2] + 800211c: 2b00 cmp r3, #0 + 800211e: d104 bne.n 800212a + 8002120: 064b lsls r3, r1, #25 + 8002122: d002 beq.n 800212a + 8002124: 0028 movs r0, r5 + 8002126: f000 ff03 bl 8002f30 + 800212a: 2385 movs r3, #133 ; 0x85 + 800212c: 009b lsls r3, r3, #2 + 800212e: 58eb ldr r3, [r5, r3] + 8002130: 689b ldr r3, [r3, #8] + 8002132: 0021 movs r1, r4 + 8002134: 0028 movs r0, r5 + 8002136: 4798 blx r3 + 8002138: 0028 movs r0, r5 + 800213a: f000 f881 bl 8002240 + 800213e: e7d0 b.n 80020e2 + 8002140: 23fe movs r3, #254 ; 0xfe + 8002142: 005b lsls r3, r3, #1 + 8002144: 5ceb ldrb r3, [r5, r3] + 8002146: 2b02 cmp r3, #2 + 8002148: d006 beq.n 8002158 + 800214a: 2b03 cmp r3, #3 + 800214c: d00a beq.n 8002164 + 800214e: 0021 movs r1, r4 + 8002150: 0028 movs r0, r5 + 8002152: f7ff fdf0 bl 8001d36 + 8002156: e7c4 b.n 80020e2 + 8002158: 064b lsls r3, r1, #25 + 800215a: d0c2 beq.n 80020e2 + 800215c: 0028 movs r0, r5 + 800215e: f000 fee7 bl 8002f30 + 8002162: e7be b.n 80020e2 + 8002164: 8863 ldrh r3, [r4, #2] + 8002166: 2b00 cmp r3, #0 + 8002168: d1bb bne.n 80020e2 + 800216a: 064b lsls r3, r1, #25 + 800216c: d103 bne.n 8002176 + 800216e: 0028 movs r0, r5 + 8002170: f000 f866 bl 8002240 + 8002174: e7b5 b.n 80020e2 + 8002176: 0028 movs r0, r5 + 8002178: f000 fee3 bl 8002f42 + 800217c: 2385 movs r3, #133 ; 0x85 + 800217e: 009b lsls r3, r3, #2 + 8002180: 58eb ldr r3, [r5, r3] + 8002182: 689b ldr r3, [r3, #8] + 8002184: 0021 movs r1, r4 + 8002186: 0028 movs r0, r5 + 8002188: 4798 blx r3 + 800218a: e7f0 b.n 800216e + 800218c: 23fe movs r3, #254 ; 0xfe + 800218e: 005b lsls r3, r3, #1 + 8002190: 5ceb ldrb r3, [r5, r3] + 8002192: 2b02 cmp r3, #2 + 8002194: d006 beq.n 80021a4 + 8002196: 2b03 cmp r3, #3 + 8002198: d00a beq.n 80021b0 + 800219a: 0021 movs r1, r4 + 800219c: 0028 movs r0, r5 + 800219e: f7ff fdca bl 8001d36 + 80021a2: e79e b.n 80020e2 + 80021a4: 064b lsls r3, r1, #25 + 80021a6: d09c beq.n 80020e2 + 80021a8: 0028 movs r0, r5 + 80021aa: f000 fec1 bl 8002f30 + 80021ae: e798 b.n 80020e2 + 80021b0: 0603 lsls r3, r0, #24 + 80021b2: d411 bmi.n 80021d8 + 80021b4: 247f movs r4, #127 ; 0x7f + 80021b6: 400c ands r4, r1 + 80021b8: 0124 lsls r4, r4, #4 + 80021ba: 3405 adds r4, #5 + 80021bc: 34ff adds r4, #255 ; 0xff + 80021be: 192c adds r4, r5, r4 + 80021c0: 0028 movs r0, r5 + 80021c2: f000 fec7 bl 8002f54 + 80021c6: 1e43 subs r3, r0, #1 + 80021c8: 4198 sbcs r0, r3 + 80021ca: 6020 str r0, [r4, #0] + 80021cc: 2202 movs r2, #2 + 80021ce: 0021 movs r1, r4 + 80021d0: 0028 movs r0, r5 + 80021d2: f000 f807 bl 80021e4 + 80021d6: e784 b.n 80020e2 + 80021d8: 247f movs r4, #127 ; 0x7f + 80021da: 400c ands r4, r1 + 80021dc: 0124 lsls r4, r4, #4 + 80021de: 3414 adds r4, #20 + 80021e0: 192c adds r4, r5, r4 + 80021e2: e7ed b.n 80021c0 + +080021e4 : + 80021e4: b510 push {r4, lr} + 80021e6: 0013 movs r3, r2 + 80021e8: 22fa movs r2, #250 ; 0xfa + 80021ea: 0052 lsls r2, r2, #1 + 80021ec: 2402 movs r4, #2 + 80021ee: 5084 str r4, [r0, r2] + 80021f0: 6183 str r3, [r0, #24] + 80021f2: 61c3 str r3, [r0, #28] + 80021f4: 000a movs r2, r1 + 80021f6: 2100 movs r1, #0 + 80021f8: f000 fece bl 8002f98 + 80021fc: 2000 movs r0, #0 + 80021fe: bd10 pop {r4, pc} + +08002200 : + 8002200: b510 push {r4, lr} + 8002202: 0013 movs r3, r2 + 8002204: 000a movs r2, r1 + 8002206: 2100 movs r1, #0 + 8002208: f000 fec6 bl 8002f98 + 800220c: 2000 movs r0, #0 + 800220e: bd10 pop {r4, pc} + +08002210 : + 8002210: b510 push {r4, lr} + 8002212: 0013 movs r3, r2 + 8002214: 22fa movs r2, #250 ; 0xfa + 8002216: 0052 lsls r2, r2, #1 + 8002218: 2403 movs r4, #3 + 800221a: 5084 str r4, [r0, r2] + 800221c: 3aec subs r2, #236 ; 0xec + 800221e: 5083 str r3, [r0, r2] + 8002220: 3204 adds r2, #4 + 8002222: 5083 str r3, [r0, r2] + 8002224: 000a movs r2, r1 + 8002226: 2100 movs r1, #0 + 8002228: f000 febf bl 8002faa + 800222c: 2000 movs r0, #0 + 800222e: bd10 pop {r4, pc} + +08002230 : + 8002230: b510 push {r4, lr} + 8002232: 0013 movs r3, r2 + 8002234: 000a movs r2, r1 + 8002236: 2100 movs r1, #0 + 8002238: f000 feb7 bl 8002faa + 800223c: 2000 movs r0, #0 + 800223e: bd10 pop {r4, pc} + +08002240 : + 8002240: b510 push {r4, lr} + 8002242: 23fa movs r3, #250 ; 0xfa + 8002244: 005b lsls r3, r3, #1 + 8002246: 2204 movs r2, #4 + 8002248: 50c2 str r2, [r0, r3] + 800224a: 2300 movs r3, #0 + 800224c: 2200 movs r2, #0 + 800224e: 2100 movs r1, #0 + 8002250: f000 fea2 bl 8002f98 + 8002254: 2000 movs r0, #0 + 8002256: bd10 pop {r4, pc} + +08002258 : + 8002258: b510 push {r4, lr} + 800225a: 23fa movs r3, #250 ; 0xfa + 800225c: 005b lsls r3, r3, #1 + 800225e: 2205 movs r2, #5 + 8002260: 50c2 str r2, [r0, r3] + 8002262: 2300 movs r3, #0 + 8002264: 2200 movs r2, #0 + 8002266: 2100 movs r1, #0 + 8002268: f000 fe9f bl 8002faa + 800226c: 2000 movs r0, #0 + 800226e: bd10 pop {r4, pc} + +08002270 : + 8002270: b570 push {r4, r5, r6, lr} + 8002272: b088 sub sp, #32 + 8002274: 4b1d ldr r3, [pc, #116] ; (80022ec ) + 8002276: 6959 ldr r1, [r3, #20] + 8002278: 2080 movs r0, #128 ; 0x80 + 800227a: 03c0 lsls r0, r0, #15 + 800227c: 4301 orrs r1, r0 + 800227e: 6159 str r1, [r3, #20] + 8002280: 695a ldr r2, [r3, #20] + 8002282: 4002 ands r2, r0 + 8002284: 9202 str r2, [sp, #8] + 8002286: 9a02 ldr r2, [sp, #8] + 8002288: 695a ldr r2, [r3, #20] + 800228a: 2180 movs r1, #128 ; 0x80 + 800228c: 0289 lsls r1, r1, #10 + 800228e: 430a orrs r2, r1 + 8002290: 615a str r2, [r3, #20] + 8002292: 695b ldr r3, [r3, #20] + 8002294: 400b ands r3, r1 + 8002296: 9301 str r3, [sp, #4] + 8002298: 9b01 ldr r3, [sp, #4] + 800229a: 2310 movs r3, #16 + 800229c: 9303 str r3, [sp, #12] + 800229e: 2500 movs r5, #0 + 80022a0: 9506 str r5, [sp, #24] + 80022a2: 9504 str r5, [sp, #16] + 80022a4: 2601 movs r6, #1 + 80022a6: 9605 str r6, [sp, #20] + 80022a8: 2490 movs r4, #144 ; 0x90 + 80022aa: 05e4 lsls r4, r4, #23 + 80022ac: a903 add r1, sp, #12 + 80022ae: 0020 movs r0, r4 + 80022b0: f7fe f838 bl 8000324 + 80022b4: 2340 movs r3, #64 ; 0x40 + 80022b6: 9303 str r3, [sp, #12] + 80022b8: 9506 str r5, [sp, #24] + 80022ba: 3b3e subs r3, #62 ; 0x3e + 80022bc: 9304 str r3, [sp, #16] + 80022be: 9607 str r6, [sp, #28] + 80022c0: a903 add r1, sp, #12 + 80022c2: 0020 movs r0, r4 + 80022c4: f7fe f82e bl 8000324 + 80022c8: 2180 movs r1, #128 ; 0x80 + 80022ca: 2201 movs r2, #1 + 80022cc: 0189 lsls r1, r1, #6 + 80022ce: 0020 movs r0, r4 + 80022d0: f7fe f90e bl 80004f0 + 80022d4: 2320 movs r3, #32 + 80022d6: 9303 str r3, [sp, #12] + 80022d8: 9506 str r5, [sp, #24] + 80022da: 3b1d subs r3, #29 + 80022dc: 9304 str r3, [sp, #16] + 80022de: a903 add r1, sp, #12 + 80022e0: 0020 movs r0, r4 + 80022e2: f7fe f81f bl 8000324 + 80022e6: b008 add sp, #32 + 80022e8: bd70 pop {r4, r5, r6, pc} + 80022ea: 46c0 nop ; (mov r8, r8) + 80022ec: 40021000 .word 0x40021000 + +080022f0 : + 80022f0: 4b04 ldr r3, [pc, #16] ; (8002304 ) + 80022f2: 2201 movs r2, #1 + 80022f4: 601a str r2, [r3, #0] + 80022f6: 4a04 ldr r2, [pc, #16] ; (8002308 ) + 80022f8: 6913 ldr r3, [r2, #16] + 80022fa: 4904 ldr r1, [pc, #16] ; (800230c ) + 80022fc: 400b ands r3, r1 + 80022fe: 6113 str r3, [r2, #16] + 8002300: 4770 bx lr + 8002302: 46c0 nop ; (mov r8, r8) + 8002304: 200002a0 .word 0x200002a0 + 8002308: 40002000 .word 0x40002000 + 800230c: 0000fffe .word 0x0000fffe + +08002310 : + 8002310: 4b0b ldr r3, [pc, #44] ; (8002340 ) + 8002312: 699a ldr r2, [r3, #24] + 8002314: 490b ldr r1, [pc, #44] ; (8002344 ) + 8002316: 400a ands r2, r1 + 8002318: 619a str r2, [r3, #24] + 800231a: 681a ldr r2, [r3, #0] + 800231c: 2101 movs r1, #1 + 800231e: 438a bics r2, r1 + 8002320: 601a str r2, [r3, #0] + 8002322: 4b09 ldr r3, [pc, #36] ; (8002348 ) + 8002324: 2200 movs r2, #0 + 8002326: 701a strb r2, [r3, #0] + 8002328: 2390 movs r3, #144 ; 0x90 + 800232a: 05db lsls r3, r3, #23 + 800232c: 691a ldr r2, [r3, #16] + 800232e: 2310 movs r3, #16 + 8002330: 4013 ands r3, r2 + 8002332: 425a negs r2, r3 + 8002334: 4153 adcs r3, r2 + 8002336: 021b lsls r3, r3, #8 + 8002338: 4a04 ldr r2, [pc, #16] ; (800234c ) + 800233a: 6353 str r3, [r2, #52] ; 0x34 + 800233c: 4770 bx lr + 800233e: 46c0 nop ; (mov r8, r8) + 8002340: 40014400 .word 0x40014400 + 8002344: 0000ffef .word 0x0000ffef + 8002348: 2000029c .word 0x2000029c + 800234c: 40000400 .word 0x40000400 + +08002350 : + 8002350: b510 push {r4, lr} + 8002352: 4b6a ldr r3, [pc, #424] ; (80024fc ) + 8002354: 781b ldrb r3, [r3, #0] + 8002356: 2b00 cmp r3, #0 + 8002358: d100 bne.n 800235c + 800235a: e0c9 b.n 80024f0 + 800235c: 4b68 ldr r3, [pc, #416] ; (8002500 ) + 800235e: 681b ldr r3, [r3, #0] + 8002360: 2b00 cmp r3, #0 + 8002362: d000 beq.n 8002366 + 8002364: e0c0 b.n 80024e8 + 8002366: 4b67 ldr r3, [pc, #412] ; (8002504 ) + 8002368: 681b ldr r3, [r3, #0] + 800236a: 2b00 cmp r3, #0 + 800236c: d149 bne.n 8002402 + 800236e: 4a66 ldr r2, [pc, #408] ; (8002508 ) + 8002370: 6993 ldr r3, [r2, #24] + 8002372: 2110 movs r1, #16 + 8002374: 430b orrs r3, r1 + 8002376: 6193 str r3, [r2, #24] + 8002378: 4b64 ldr r3, [pc, #400] ; (800250c ) + 800237a: 681a ldr r2, [r3, #0] + 800237c: 4b60 ldr r3, [pc, #384] ; (8002500 ) + 800237e: 601a str r2, [r3, #0] + 8002380: 4b63 ldr r3, [pc, #396] ; (8002510 ) + 8002382: 781b ldrb r3, [r3, #0] + 8002384: 2b00 cmp r3, #0 + 8002386: d01f beq.n 80023c8 + 8002388: 4b62 ldr r3, [pc, #392] ; (8002514 ) + 800238a: 681b ldr r3, [r3, #0] + 800238c: 07db lsls r3, r3, #31 + 800238e: d40a bmi.n 80023a6 + 8002390: 4b61 ldr r3, [pc, #388] ; (8002518 ) + 8002392: 681b ldr r3, [r3, #0] + 8002394: 4961 ldr r1, [pc, #388] ; (800251c ) + 8002396: 680a ldr r2, [r1, #0] + 8002398: 1c50 adds r0, r2, #1 + 800239a: 6008 str r0, [r1, #0] + 800239c: 189b adds r3, r3, r2 + 800239e: 781b ldrb r3, [r3, #0] + 80023a0: b2db uxtb r3, r3 + 80023a2: 4a5f ldr r2, [pc, #380] ; (8002520 ) + 80023a4: 7013 strb r3, [r2, #0] + 80023a6: 4b5e ldr r3, [pc, #376] ; (8002520 ) + 80023a8: 781a ldrb r2, [r3, #0] + 80023aa: 210f movs r1, #15 + 80023ac: 400a ands r2, r1 + 80023ae: 495d ldr r1, [pc, #372] ; (8002524 ) + 80023b0: 700a strb r2, [r1, #0] + 80023b2: 781a ldrb r2, [r3, #0] + 80023b4: 0912 lsrs r2, r2, #4 + 80023b6: 701a strb r2, [r3, #0] + 80023b8: 4a56 ldr r2, [pc, #344] ; (8002514 ) + 80023ba: 6813 ldr r3, [r2, #0] + 80023bc: 3301 adds r3, #1 + 80023be: 6013 str r3, [r2, #0] + 80023c0: 4b50 ldr r3, [pc, #320] ; (8002504 ) + 80023c2: 2201 movs r2, #1 + 80023c4: 601a str r2, [r3, #0] + 80023c6: e093 b.n 80024f0 + 80023c8: 4b52 ldr r3, [pc, #328] ; (8002514 ) + 80023ca: 681b ldr r3, [r3, #0] + 80023cc: 079b lsls r3, r3, #30 + 80023ce: d10a bne.n 80023e6 + 80023d0: 4b51 ldr r3, [pc, #324] ; (8002518 ) + 80023d2: 681b ldr r3, [r3, #0] + 80023d4: 4951 ldr r1, [pc, #324] ; (800251c ) + 80023d6: 680a ldr r2, [r1, #0] + 80023d8: 1c50 adds r0, r2, #1 + 80023da: 6008 str r0, [r1, #0] + 80023dc: 189b adds r3, r3, r2 + 80023de: 781b ldrb r3, [r3, #0] + 80023e0: b2db uxtb r3, r3 + 80023e2: 4a4f ldr r2, [pc, #316] ; (8002520 ) + 80023e4: 7013 strb r3, [r2, #0] + 80023e6: 4b4e ldr r3, [pc, #312] ; (8002520 ) + 80023e8: 781a ldrb r2, [r3, #0] + 80023ea: 2103 movs r1, #3 + 80023ec: 400a ands r2, r1 + 80023ee: 494d ldr r1, [pc, #308] ; (8002524 ) + 80023f0: 700a strb r2, [r1, #0] + 80023f2: 781a ldrb r2, [r3, #0] + 80023f4: 0892 lsrs r2, r2, #2 + 80023f6: 701a strb r2, [r3, #0] + 80023f8: 4a46 ldr r2, [pc, #280] ; (8002514 ) + 80023fa: 6813 ldr r3, [r2, #0] + 80023fc: 3301 adds r3, #1 + 80023fe: 6013 str r3, [r2, #0] + 8002400: e7de b.n 80023c0 + 8002402: 4a41 ldr r2, [pc, #260] ; (8002508 ) + 8002404: 6993 ldr r3, [r2, #24] + 8002406: 4948 ldr r1, [pc, #288] ; (8002528 ) + 8002408: 400b ands r3, r1 + 800240a: 6193 str r3, [r2, #24] + 800240c: 4b3d ldr r3, [pc, #244] ; (8002504 ) + 800240e: 2200 movs r2, #0 + 8002410: 601a str r2, [r3, #0] + 8002412: 4b3f ldr r3, [pc, #252] ; (8002510 ) + 8002414: 781b ldrb r3, [r3, #0] + 8002416: 2b00 cmp r3, #0 + 8002418: d04f beq.n 80024ba + 800241a: 4b42 ldr r3, [pc, #264] ; (8002524 ) + 800241c: 781b ldrb r3, [r3, #0] + 800241e: 009b lsls r3, r3, #2 + 8002420: 4a42 ldr r2, [pc, #264] ; (800252c ) + 8002422: 589a ldr r2, [r3, r2] + 8002424: 4b36 ldr r3, [pc, #216] ; (8002500 ) + 8002426: 601a str r2, [r3, #0] + 8002428: 4b39 ldr r3, [pc, #228] ; (8002510 ) + 800242a: 781b ldrb r3, [r3, #0] + 800242c: 1e5a subs r2, r3, #1 + 800242e: 4193 sbcs r3, r2 + 8002430: 425b negs r3, r3 + 8002432: 4a3f ldr r2, [pc, #252] ; (8002530 ) + 8002434: 4013 ands r3, r2 + 8002436: 22fa movs r2, #250 ; 0xfa + 8002438: 0092 lsls r2, r2, #2 + 800243a: 4694 mov ip, r2 + 800243c: 4463 add r3, ip + 800243e: 4a3d ldr r2, [pc, #244] ; (8002534 ) + 8002440: 6812 ldr r2, [r2, #0] + 8002442: 429a cmp r2, r3 + 8002444: d309 bcc.n 800245a + 8002446: 4a2e ldr r2, [pc, #184] ; (8002500 ) + 8002448: 6813 ldr r3, [r2, #0] + 800244a: 3301 adds r3, #1 + 800244c: 6013 str r3, [r2, #0] + 800244e: 4a39 ldr r2, [pc, #228] ; (8002534 ) + 8002450: 6813 ldr r3, [r2, #0] + 8002452: 4939 ldr r1, [pc, #228] ; (8002538 ) + 8002454: 468c mov ip, r1 + 8002456: 4463 add r3, ip + 8002458: 6013 str r3, [r2, #0] + 800245a: 4b2d ldr r3, [pc, #180] ; (8002510 ) + 800245c: 781b ldrb r3, [r3, #0] + 800245e: 2b00 cmp r3, #0 + 8002460: d031 beq.n 80024c6 + 8002462: 4b30 ldr r3, [pc, #192] ; (8002524 ) + 8002464: 781b ldrb r3, [r3, #0] + 8002466: 009b lsls r3, r3, #2 + 8002468: 4a34 ldr r2, [pc, #208] ; (800253c ) + 800246a: 5899 ldr r1, [r3, r2] + 800246c: 4a31 ldr r2, [pc, #196] ; (8002534 ) + 800246e: 6813 ldr r3, [r2, #0] + 8002470: 185b adds r3, r3, r1 + 8002472: 6013 str r3, [r2, #0] + 8002474: 4b29 ldr r3, [pc, #164] ; (800251c ) + 8002476: 681a ldr r2, [r3, #0] + 8002478: 4b31 ldr r3, [pc, #196] ; (8002540 ) + 800247a: 681b ldr r3, [r3, #0] + 800247c: 429a cmp r2, r3 + 800247e: d937 bls.n 80024f0 + 8002480: 4b30 ldr r3, [pc, #192] ; (8002544 ) + 8002482: 681b ldr r3, [r3, #0] + 8002484: 2b00 cmp r3, #0 + 8002486: d024 beq.n 80024d2 + 8002488: 4a2e ldr r2, [pc, #184] ; (8002544 ) + 800248a: 6813 ldr r3, [r2, #0] + 800248c: 3b01 subs r3, #1 + 800248e: 6013 str r3, [r2, #0] + 8002490: 2300 movs r3, #0 + 8002492: 4a22 ldr r2, [pc, #136] ; (800251c ) + 8002494: 6013 str r3, [r2, #0] + 8002496: 4a1f ldr r2, [pc, #124] ; (8002514 ) + 8002498: 6013 str r3, [r2, #0] + 800249a: 4a26 ldr r2, [pc, #152] ; (8002534 ) + 800249c: 6013 str r3, [r2, #0] + 800249e: 4b1c ldr r3, [pc, #112] ; (8002510 ) + 80024a0: 781b ldrb r3, [r3, #0] + 80024a2: 1e5a subs r2, r3, #1 + 80024a4: 4193 sbcs r3, r2 + 80024a6: 425a negs r2, r3 + 80024a8: 234b movs r3, #75 ; 0x4b + 80024aa: 4013 ands r3, r2 + 80024ac: 3332 adds r3, #50 ; 0x32 + 80024ae: 4a26 ldr r2, [pc, #152] ; (8002548 ) + 80024b0: 6812 ldr r2, [r2, #0] + 80024b2: 4353 muls r3, r2 + 80024b4: 4a12 ldr r2, [pc, #72] ; (8002500 ) + 80024b6: 6013 str r3, [r2, #0] + 80024b8: e01a b.n 80024f0 + 80024ba: 4b1a ldr r3, [pc, #104] ; (8002524 ) + 80024bc: 781b ldrb r3, [r3, #0] + 80024be: 009b lsls r3, r3, #2 + 80024c0: 4a22 ldr r2, [pc, #136] ; (800254c ) + 80024c2: 589a ldr r2, [r3, r2] + 80024c4: e7ae b.n 8002424 + 80024c6: 4b17 ldr r3, [pc, #92] ; (8002524 ) + 80024c8: 781b ldrb r3, [r3, #0] + 80024ca: 009b lsls r3, r3, #2 + 80024cc: 4a20 ldr r2, [pc, #128] ; (8002550 ) + 80024ce: 5899 ldr r1, [r3, r2] + 80024d0: e7cc b.n 800246c + 80024d2: f7ff ff1d bl 8002310 + 80024d6: 4b1f ldr r3, [pc, #124] ; (8002554 ) + 80024d8: 681b ldr r3, [r3, #0] + 80024da: 2b00 cmp r3, #0 + 80024dc: d108 bne.n 80024f0 + 80024de: 2101 movs r1, #1 + 80024e0: 481d ldr r0, [pc, #116] ; (8002558 ) + 80024e2: f000 fc1f bl 8002d24 + 80024e6: e003 b.n 80024f0 + 80024e8: 4a05 ldr r2, [pc, #20] ; (8002500 ) + 80024ea: 6813 ldr r3, [r2, #0] + 80024ec: 3b01 subs r3, #1 + 80024ee: 6013 str r3, [r2, #0] + 80024f0: 4a05 ldr r2, [pc, #20] ; (8002508 ) + 80024f2: 6913 ldr r3, [r2, #16] + 80024f4: 4919 ldr r1, [pc, #100] ; (800255c ) + 80024f6: 400b ands r3, r1 + 80024f8: 6113 str r3, [r2, #16] + 80024fa: bd10 pop {r4, pc} + 80024fc: 2000029c .word 0x2000029c + 8002500: 200004dc .word 0x200004dc + 8002504: 200008f8 .word 0x200008f8 + 8002508: 40014400 .word 0x40014400 + 800250c: 200004d8 .word 0x200004d8 + 8002510: 200004d0 .word 0x200004d0 + 8002514: 200004e8 .word 0x200004e8 + 8002518: 200004f0 .word 0x200004f0 + 800251c: 200004e0 .word 0x200004e0 + 8002520: 200004e4 .word 0x200004e4 + 8002524: 200004d1 .word 0x200004d1 + 8002528: 0000ffef .word 0x0000ffef + 800252c: 0800322c .word 0x0800322c + 8002530: fffffda8 .word 0xfffffda8 + 8002534: 200004ec .word 0x200004ec + 8002538: fffffc18 .word 0xfffffc18 + 800253c: 080031ec .word 0x080031ec + 8002540: 200008f4 .word 0x200008f4 + 8002544: 200004d4 .word 0x200004d4 + 8002548: 200002a4 .word 0x200002a4 + 800254c: 0800327c .word 0x0800327c + 8002550: 0800326c .word 0x0800326c + 8002554: 200002a8 .word 0x200002a8 + 8002558: 080031d4 .word 0x080031d4 + 800255c: 0000fffe .word 0x0000fffe + +08002560 : + 8002560: b510 push {r4, lr} + 8002562: 4c1c ldr r4, [pc, #112] ; (80025d4 ) + 8002564: 6020 str r0, [r4, #0] + 8002566: 2000 movs r0, #0 + 8002568: 4c1b ldr r4, [pc, #108] ; (80025d8 ) + 800256a: 6020 str r0, [r4, #0] + 800256c: 4c1b ldr r4, [pc, #108] ; (80025dc ) + 800256e: 6022 str r2, [r4, #0] + 8002570: 4a1b ldr r2, [pc, #108] ; (80025e0 ) + 8002572: 6010 str r0, [r2, #0] + 8002574: 4a1b ldr r2, [pc, #108] ; (80025e4 ) + 8002576: 6010 str r0, [r2, #0] + 8002578: 4a1b ldr r2, [pc, #108] ; (80025e8 ) + 800257a: 6010 str r0, [r2, #0] + 800257c: 4a1b ldr r2, [pc, #108] ; (80025ec ) + 800257e: 6013 str r3, [r2, #0] + 8002580: 4b1b ldr r3, [pc, #108] ; (80025f0 ) + 8002582: 6018 str r0, [r3, #0] + 8002584: 2401 movs r4, #1 + 8002586: 4b1b ldr r3, [pc, #108] ; (80025f4 ) + 8002588: 701c strb r4, [r3, #0] + 800258a: b2ca uxtb r2, r1 + 800258c: 4b1a ldr r3, [pc, #104] ; (80025f8 ) + 800258e: 701a strb r2, [r3, #0] + 8002590: 4b1a ldr r3, [pc, #104] ; (80025fc ) + 8002592: 681a ldr r2, [r3, #0] + 8002594: 43a2 bics r2, r4 + 8002596: 601a str r2, [r3, #0] + 8002598: 6258 str r0, [r3, #36] ; 0x24 + 800259a: 2900 cmp r1, #0 + 800259c: d011 beq.n 80025c2 + 800259e: 22bf movs r2, #191 ; 0xbf + 80025a0: 62da str r2, [r3, #44] ; 0x2c + 80025a2: 4b17 ldr r3, [pc, #92] ; (8002600 ) + 80025a4: 3abd subs r2, #189 ; 0xbd + 80025a6: 601a str r2, [r3, #0] + 80025a8: 4b16 ldr r3, [pc, #88] ; (8002604 ) + 80025aa: 2280 movs r2, #128 ; 0x80 + 80025ac: 01d2 lsls r2, r2, #7 + 80025ae: 635a str r2, [r3, #52] ; 0x34 + 80025b0: 4b12 ldr r3, [pc, #72] ; (80025fc ) + 80025b2: 68d9 ldr r1, [r3, #12] + 80025b4: 2001 movs r0, #1 + 80025b6: 4301 orrs r1, r0 + 80025b8: 60d9 str r1, [r3, #12] + 80025ba: 681a ldr r2, [r3, #0] + 80025bc: 4302 orrs r2, r0 + 80025be: 601a str r2, [r3, #0] + 80025c0: bd10 pop {r4, pc} + 80025c2: 4b0e ldr r3, [pc, #56] ; (80025fc ) + 80025c4: 22e4 movs r2, #228 ; 0xe4 + 80025c6: 32ff adds r2, #255 ; 0xff + 80025c8: 62da str r2, [r3, #44] ; 0x2c + 80025ca: 4b0d ldr r3, [pc, #52] ; (8002600 ) + 80025cc: 3ae1 subs r2, #225 ; 0xe1 + 80025ce: 3aff subs r2, #255 ; 0xff + 80025d0: 601a str r2, [r3, #0] + 80025d2: e7e9 b.n 80025a8 + 80025d4: 200004f0 .word 0x200004f0 + 80025d8: 200004e0 .word 0x200004e0 + 80025dc: 200008f4 .word 0x200008f4 + 80025e0: 200004dc .word 0x200004dc + 80025e4: 200008f8 .word 0x200008f8 + 80025e8: 200004e8 .word 0x200004e8 + 80025ec: 200004d4 .word 0x200004d4 + 80025f0: 200004ec .word 0x200004ec + 80025f4: 2000029c .word 0x2000029c + 80025f8: 200004d0 .word 0x200004d0 + 80025fc: 40014400 .word 0x40014400 + 8002600: 200004d8 .word 0x200004d8 + 8002604: 40000400 .word 0x40000400 + +08002608 : + 8002608: 4b09 ldr r3, [pc, #36] ; (8002630 ) + 800260a: 2201 movs r2, #1 + 800260c: 609a str r2, [r3, #8] + 800260e: 0019 movs r1, r3 + 8002610: 680b ldr r3, [r1, #0] + 8002612: 421a tst r2, r3 + 8002614: d0fc beq.n 8002610 + 8002616: 4a06 ldr r2, [pc, #24] ; (8002630 ) + 8002618: 6893 ldr r3, [r2, #8] + 800261a: 2104 movs r1, #4 + 800261c: 430b orrs r3, r1 + 800261e: 6093 str r3, [r2, #8] + 8002620: 0011 movs r1, r2 + 8002622: 2204 movs r2, #4 + 8002624: 680b ldr r3, [r1, #0] + 8002626: 421a tst r2, r3 + 8002628: d0fc beq.n 8002624 + 800262a: 4b01 ldr r3, [pc, #4] ; (8002630 ) + 800262c: 6c18 ldr r0, [r3, #64] ; 0x40 + 800262e: 4770 bx lr + 8002630: 40012400 .word 0x40012400 + +08002634 : + 8002634: b510 push {r4, lr} + 8002636: 4b28 ldr r3, [pc, #160] ; (80026d8 ) + 8002638: 681a ldr r2, [r3, #0] + 800263a: 2101 movs r1, #1 + 800263c: 430a orrs r2, r1 + 800263e: 601a str r2, [r3, #0] + 8002640: 681b ldr r3, [r3, #0] + 8002642: 4a26 ldr r2, [pc, #152] ; (80026dc ) + 8002644: 6811 ldr r1, [r2, #0] + 8002646: 2380 movs r3, #128 ; 0x80 + 8002648: 025b lsls r3, r3, #9 + 800264a: 430b orrs r3, r1 + 800264c: 6013 str r3, [r2, #0] + 800264e: 0011 movs r1, r2 + 8002650: 2280 movs r2, #128 ; 0x80 + 8002652: 0292 lsls r2, r2, #10 + 8002654: 680b ldr r3, [r1, #0] + 8002656: 4213 tst r3, r2 + 8002658: d0fc beq.n 8002654 + 800265a: 4b20 ldr r3, [pc, #128] ; (80026dc ) + 800265c: 685a ldr r2, [r3, #4] + 800265e: 4920 ldr r1, [pc, #128] ; (80026e0 ) + 8002660: 4011 ands r1, r2 + 8002662: 2288 movs r2, #136 ; 0x88 + 8002664: 0352 lsls r2, r2, #13 + 8002666: 430a orrs r2, r1 + 8002668: 605a str r2, [r3, #4] + 800266a: 6ada ldr r2, [r3, #44] ; 0x2c + 800266c: 210f movs r1, #15 + 800266e: 438a bics r2, r1 + 8002670: 62da str r2, [r3, #44] ; 0x2c + 8002672: 6819 ldr r1, [r3, #0] + 8002674: 2280 movs r2, #128 ; 0x80 + 8002676: 0452 lsls r2, r2, #17 + 8002678: 430a orrs r2, r1 + 800267a: 601a str r2, [r3, #0] + 800267c: 0019 movs r1, r3 + 800267e: 2280 movs r2, #128 ; 0x80 + 8002680: 0492 lsls r2, r2, #18 + 8002682: 680b ldr r3, [r1, #0] + 8002684: 4213 tst r3, r2 + 8002686: d0fc beq.n 8002682 + 8002688: 4b14 ldr r3, [pc, #80] ; (80026dc ) + 800268a: 685a ldr r2, [r3, #4] + 800268c: 21f0 movs r1, #240 ; 0xf0 + 800268e: 438a bics r2, r1 + 8002690: 605a str r2, [r3, #4] + 8002692: 685a ldr r2, [r3, #4] + 8002694: 4913 ldr r1, [pc, #76] ; (80026e4 ) + 8002696: 400a ands r2, r1 + 8002698: 605a str r2, [r3, #4] + 800269a: 685a ldr r2, [r3, #4] + 800269c: 2103 movs r1, #3 + 800269e: 438a bics r2, r1 + 80026a0: 3901 subs r1, #1 + 80026a2: 430a orrs r2, r1 + 80026a4: 605a str r2, [r3, #4] + 80026a6: 0019 movs r1, r3 + 80026a8: 220c movs r2, #12 + 80026aa: 684b ldr r3, [r1, #4] + 80026ac: 4013 ands r3, r2 + 80026ae: 2b08 cmp r3, #8 + 80026b0: d1fb bne.n 80026aa + 80026b2: 4c0d ldr r4, [pc, #52] ; (80026e8 ) + 80026b4: 0020 movs r0, r4 + 80026b6: f7ff f84d bl 8001754 + 80026ba: 4a0c ldr r2, [pc, #48] ; (80026ec ) + 80026bc: 6813 ldr r3, [r2, #0] + 80026be: 2104 movs r1, #4 + 80026c0: 430b orrs r3, r1 + 80026c2: 6013 str r3, [r2, #0] + 80026c4: 0020 movs r0, r4 + 80026c6: f7ff f855 bl 8001774 + 80026ca: 4a04 ldr r2, [pc, #16] ; (80026dc ) + 80026cc: 6b13 ldr r3, [r2, #48] ; 0x30 + 80026ce: 2180 movs r1, #128 ; 0x80 + 80026d0: 430b orrs r3, r1 + 80026d2: 6313 str r3, [r2, #48] ; 0x30 + 80026d4: bd10 pop {r4, pc} + 80026d6: 46c0 nop ; (mov r8, r8) + 80026d8: 40022000 .word 0x40022000 + 80026dc: 40021000 .word 0x40021000 + 80026e0: ffc27fff .word 0xffc27fff + 80026e4: fffff8ff .word 0xfffff8ff + 80026e8: 02dc6c00 .word 0x02dc6c00 + 80026ec: e000e010 .word 0xe000e010 + +080026f0
: + 80026f0: b5f0 push {r4, r5, r6, r7, lr} + 80026f2: 46de mov lr, fp + 80026f4: 4657 mov r7, sl + 80026f6: 464e mov r6, r9 + 80026f8: 4645 mov r5, r8 + 80026fa: b5e0 push {r5, r6, r7, lr} + 80026fc: b0cf sub sp, #316 ; 0x13c + 80026fe: f7fd fda1 bl 8000244 + 8002702: f7ff ff97 bl 8002634 + 8002706: f7ff fdb3 bl 8002270 + 800270a: f000 fa97 bl 8002c3c + 800270e: 4bcd ldr r3, [pc, #820] ; (8002a44 ) + 8002710: 69d9 ldr r1, [r3, #28] + 8002712: 2202 movs r2, #2 + 8002714: 4311 orrs r1, r2 + 8002716: 61d9 str r1, [r3, #28] + 8002718: 69d9 ldr r1, [r3, #28] + 800271a: 4011 ands r1, r2 + 800271c: 9108 str r1, [sp, #32] + 800271e: 9908 ldr r1, [sp, #32] + 8002720: 69d8 ldr r0, [r3, #28] + 8002722: 2480 movs r4, #128 ; 0x80 + 8002724: 0064 lsls r4, r4, #1 + 8002726: 4320 orrs r0, r4 + 8002728: 61d8 str r0, [r3, #28] + 800272a: 69d9 ldr r1, [r3, #28] + 800272c: 4021 ands r1, r4 + 800272e: 9107 str r1, [sp, #28] + 8002730: 9907 ldr r1, [sp, #28] + 8002732: 6998 ldr r0, [r3, #24] + 8002734: 3401 adds r4, #1 + 8002736: 34ff adds r4, #255 ; 0xff + 8002738: 4320 orrs r0, r4 + 800273a: 6198 str r0, [r3, #24] + 800273c: 6999 ldr r1, [r3, #24] + 800273e: 4021 ands r1, r4 + 8002740: 9106 str r1, [sp, #24] + 8002742: 9906 ldr r1, [sp, #24] + 8002744: 6998 ldr r0, [r3, #24] + 8002746: 2480 movs r4, #128 ; 0x80 + 8002748: 02a4 lsls r4, r4, #10 + 800274a: 4320 orrs r0, r4 + 800274c: 6198 str r0, [r3, #24] + 800274e: 6999 ldr r1, [r3, #24] + 8002750: 4021 ands r1, r4 + 8002752: 9105 str r1, [sp, #20] + 8002754: 9905 ldr r1, [sp, #20] + 8002756: 6998 ldr r0, [r3, #24] + 8002758: 2480 movs r4, #128 ; 0x80 + 800275a: 02e4 lsls r4, r4, #11 + 800275c: 4320 orrs r0, r4 + 800275e: 6198 str r0, [r3, #24] + 8002760: 6999 ldr r1, [r3, #24] + 8002762: 4021 ands r1, r4 + 8002764: 9104 str r1, [sp, #16] + 8002766: 9904 ldr r1, [sp, #16] + 8002768: 6999 ldr r1, [r3, #24] + 800276a: 2401 movs r4, #1 + 800276c: 4321 orrs r1, r4 + 800276e: 6199 str r1, [r3, #24] + 8002770: 699b ldr r3, [r3, #24] + 8002772: 4023 ands r3, r4 + 8002774: 9303 str r3, [sp, #12] + 8002776: 9b03 ldr r3, [sp, #12] + 8002778: 2380 movs r3, #128 ; 0x80 + 800277a: 019b lsls r3, r3, #6 + 800277c: 9309 str r3, [sp, #36] ; 0x24 + 800277e: 2500 movs r5, #0 + 8002780: 950c str r5, [sp, #48] ; 0x30 + 8002782: 920a str r2, [sp, #40] ; 0x28 + 8002784: 940d str r4, [sp, #52] ; 0x34 + 8002786: 2090 movs r0, #144 ; 0x90 + 8002788: a909 add r1, sp, #36 ; 0x24 + 800278a: 05c0 lsls r0, r0, #23 + 800278c: f7fd fdca bl 8000324 + 8002790: 4bad ldr r3, [pc, #692] ; (8002a48 ) + 8002792: 629d str r5, [r3, #40] ; 0x28 + 8002794: 2225 movs r2, #37 ; 0x25 + 8002796: 62da str r2, [r3, #44] ; 0x2c + 8002798: 3a13 subs r2, #19 + 800279a: 635a str r2, [r3, #52] ; 0x34 + 800279c: 699a ldr r2, [r3, #24] + 800279e: 2168 movs r1, #104 ; 0x68 + 80027a0: 430a orrs r2, r1 + 80027a2: 619a str r2, [r3, #24] + 80027a4: 6a1a ldr r2, [r3, #32] + 80027a6: 4322 orrs r2, r4 + 80027a8: 621a str r2, [r3, #32] + 80027aa: 6c5a ldr r2, [r3, #68] ; 0x44 + 80027ac: 2180 movs r1, #128 ; 0x80 + 80027ae: 0209 lsls r1, r1, #8 + 80027b0: 430a orrs r2, r1 + 80027b2: 645a str r2, [r3, #68] ; 0x44 + 80027b4: 4aa5 ldr r2, [pc, #660] ; (8002a4c ) + 80027b6: 6295 str r5, [r2, #40] ; 0x28 + 80027b8: 6990 ldr r0, [r2, #24] + 80027ba: 2640 movs r6, #64 ; 0x40 + 80027bc: 4330 orrs r0, r6 + 80027be: 6190 str r0, [r2, #24] + 80027c0: 6a10 ldr r0, [r2, #32] + 80027c2: 4320 orrs r0, r4 + 80027c4: 6210 str r0, [r2, #32] + 80027c6: 6c50 ldr r0, [r2, #68] ; 0x44 + 80027c8: 4301 orrs r1, r0 + 80027ca: 6451 str r1, [r2, #68] ; 0x44 + 80027cc: 68d1 ldr r1, [r2, #12] + 80027ce: 4321 orrs r1, r4 + 80027d0: 60d1 str r1, [r2, #12] + 80027d2: 681a ldr r2, [r3, #0] + 80027d4: 4322 orrs r2, r4 + 80027d6: 601a str r2, [r3, #0] + 80027d8: 695a ldr r2, [r3, #20] + 80027da: 4322 orrs r2, r4 + 80027dc: 615a str r2, [r3, #20] + 80027de: 4a9c ldr r2, [pc, #624] ; (8002a50 ) + 80027e0: 2380 movs r3, #128 ; 0x80 + 80027e2: 039b lsls r3, r3, #14 + 80027e4: 6013 str r3, [r2, #0] + 80027e6: 21c5 movs r1, #197 ; 0xc5 + 80027e8: 0089 lsls r1, r1, #2 + 80027ea: 5853 ldr r3, [r2, r1] + 80027ec: 4899 ldr r0, [pc, #612] ; (8002a54 ) + 80027ee: 4003 ands r3, r0 + 80027f0: 5053 str r3, [r2, r1] + 80027f2: 4b99 ldr r3, [pc, #612] ; (8002a58 ) + 80027f4: 2164 movs r1, #100 ; 0x64 + 80027f6: 6299 str r1, [r3, #40] ; 0x28 + 80027f8: 4898 ldr r0, [pc, #608] ; (8002a5c ) + 80027fa: 62d8 str r0, [r3, #44] ; 0x2c + 80027fc: 619d str r5, [r3, #24] + 80027fe: 621d str r5, [r3, #32] + 8002800: 68d9 ldr r1, [r3, #12] + 8002802: 4321 orrs r1, r4 + 8002804: 60d9 str r1, [r3, #12] + 8002806: 6819 ldr r1, [r3, #0] + 8002808: 4321 orrs r1, r4 + 800280a: 6019 str r1, [r3, #0] + 800280c: 6959 ldr r1, [r3, #20] + 800280e: 4321 orrs r1, r4 + 8002810: 6159 str r1, [r3, #20] + 8002812: 2380 movs r3, #128 ; 0x80 + 8002814: 031b lsls r3, r3, #12 + 8002816: 6013 str r3, [r2, #0] + 8002818: 26c4 movs r6, #196 ; 0xc4 + 800281a: 00b6 lsls r6, r6, #2 + 800281c: 5993 ldr r3, [r2, r6] + 800281e: 021b lsls r3, r3, #8 + 8002820: 0a1b lsrs r3, r3, #8 + 8002822: 2180 movs r1, #128 ; 0x80 + 8002824: 05c9 lsls r1, r1, #23 + 8002826: 430b orrs r3, r1 + 8002828: 5193 str r3, [r2, r6] + 800282a: 4b8d ldr r3, [pc, #564] ; (8002a60 ) + 800282c: 62d8 str r0, [r3, #44] ; 0x2c + 800282e: 2270 movs r2, #112 ; 0x70 + 8002830: 619a str r2, [r3, #24] + 8002832: 621c str r4, [r3, #32] + 8002834: 2280 movs r2, #128 ; 0x80 + 8002836: 0152 lsls r2, r2, #5 + 8002838: 635a str r2, [r3, #52] ; 0x34 + 800283a: 681a ldr r2, [r3, #0] + 800283c: 4322 orrs r2, r4 + 800283e: 601a str r2, [r3, #0] + 8002840: 695a ldr r2, [r3, #20] + 8002842: 4314 orrs r4, r2 + 8002844: 615c str r4, [r3, #20] + 8002846: 4b87 ldr r3, [pc, #540] ; (8002a64 ) + 8002848: 60dd str r5, [r3, #12] + 800284a: 2207 movs r2, #7 + 800284c: 615a str r2, [r3, #20] + 800284e: 3219 adds r2, #25 + 8002850: 629a str r2, [r3, #40] ; 0x28 + 8002852: f7ff fed9 bl 8002608 + 8002856: 4b84 ldr r3, [pc, #528] ; (8002a68 ) + 8002858: 4298 cmp r0, r3 + 800285a: d834 bhi.n 80028c6 + 800285c: 4b83 ldr r3, [pc, #524] ; (8002a6c ) + 800285e: 881b ldrh r3, [r3, #0] + 8002860: 4698 mov r8, r3 + 8002862: 4b83 ldr r3, [pc, #524] ; (8002a70 ) + 8002864: 2201 movs r2, #1 + 8002866: 601a str r2, [r3, #0] + 8002868: 4b80 ldr r3, [pc, #512] ; (8002a6c ) + 800286a: 469b mov fp, r3 + 800286c: 4e81 ldr r6, [pc, #516] ; (8002a74 ) + 800286e: 4699 mov r9, r3 + 8002870: 46c2 mov sl, r8 + 8002872: e00c b.n 800288e + 8002874: 4643 mov r3, r8 + 8002876: 003a movs r2, r7 + 8002878: a80e add r0, sp, #56 ; 0x38 + 800287a: f7ff fe71 bl 8002560 + 800287e: 4a7e ldr r2, [pc, #504] ; (8002a78 ) + 8002880: 7813 ldrb r3, [r2, #0] + 8002882: 2b00 cmp r3, #0 + 8002884: d1fc bne.n 8002880 + 8002886: 3501 adds r5, #1 + 8002888: 4555 cmp r5, sl + 800288a: 419b sbcs r3, r3 + 800288c: 401d ands r5, r3 + 800288e: 00eb lsls r3, r5, #3 + 8002890: 195b adds r3, r3, r5 + 8002892: 00db lsls r3, r3, #3 + 8002894: 445b add r3, fp + 8002896: 891f ldrh r7, [r3, #8] + 8002898: 889a ldrh r2, [r3, #4] + 800289a: 4690 mov r8, r2 + 800289c: 88da ldrh r2, [r3, #6] + 800289e: 6032 str r2, [r6, #0] + 80028a0: 8859 ldrh r1, [r3, #2] + 80028a2: 2301 movs r3, #1 + 80028a4: 4019 ands r1, r3 + 80028a6: 2f00 cmp r7, #0 + 80028a8: d0e4 beq.n 8002874 + 80028aa: ac0e add r4, sp, #56 ; 0x38 + 80028ac: 00ea lsls r2, r5, #3 + 80028ae: 1952 adds r2, r2, r5 + 80028b0: 00d2 lsls r2, r2, #3 + 80028b2: 320a adds r2, #10 + 80028b4: 444a add r2, r9 + 80028b6: 2000 movs r0, #0 + 80028b8: 5c13 ldrb r3, [r2, r0] + 80028ba: 7023 strb r3, [r4, #0] + 80028bc: 3001 adds r0, #1 + 80028be: 3401 adds r4, #1 + 80028c0: 4287 cmp r7, r0 + 80028c2: d8f9 bhi.n 80028b8 + 80028c4: e7d6 b.n 8002874 + 80028c6: 2400 movs r4, #0 + 80028c8: 9401 str r4, [sp, #4] + 80028ca: 46a0 mov r8, r4 + 80028cc: 46a2 mov sl, r4 + 80028ce: 9400 str r4, [sp, #0] + 80028d0: 46a3 mov fp, r4 + 80028d2: 4b6a ldr r3, [pc, #424] ; (8002a7c ) + 80028d4: 4699 mov r9, r3 + 80028d6: 4a6a ldr r2, [pc, #424] ; (8002a80 ) + 80028d8: 1a9f subs r7, r3, r2 + 80028da: e006 b.n 80028ea + 80028dc: 2400 movs r4, #0 + 80028de: 4b69 ldr r3, [pc, #420] ; (8002a84 ) + 80028e0: 681a ldr r2, [r3, #0] + 80028e2: 685b ldr r3, [r3, #4] + 80028e4: 429a cmp r2, r3 + 80028e6: d000 beq.n 80028ea + 80028e8: e0e9 b.n 8002abe + 80028ea: 4b67 ldr r3, [pc, #412] ; (8002a88 ) + 80028ec: 681b ldr r3, [r3, #0] + 80028ee: 2b00 cmp r3, #0 + 80028f0: d0f5 beq.n 80028de + 80028f2: 4b65 ldr r3, [pc, #404] ; (8002a88 ) + 80028f4: 2200 movs r2, #0 + 80028f6: 601a str r2, [r3, #0] + 80028f8: 4b5f ldr r3, [pc, #380] ; (8002a78 ) + 80028fa: 781b ldrb r3, [r3, #0] + 80028fc: b2dc uxtb r4, r3 + 80028fe: 2b00 cmp r3, #0 + 8002900: d1ec bne.n 80028dc + 8002902: 2390 movs r3, #144 ; 0x90 + 8002904: 05db lsls r3, r3, #23 + 8002906: 691a ldr r2, [r3, #16] + 8002908: 2310 movs r3, #16 + 800290a: 4013 ands r3, r2 + 800290c: 425a negs r2, r3 + 800290e: 4153 adcs r3, r2 + 8002910: 021b lsls r3, r3, #8 + 8002912: 4a53 ldr r2, [pc, #332] ; (8002a60 ) + 8002914: 6353 str r3, [r2, #52] ; 0x34 + 8002916: e7e2 b.n 80028de + 8002918: 4653 mov r3, sl + 800291a: 9a00 ldr r2, [sp, #0] + 800291c: 4659 mov r1, fp + 800291e: a80e add r0, sp, #56 ; 0x38 + 8002920: f7ff fe1e bl 8002560 + 8002924: e0c0 b.n 8002aa8 + 8002926: 210c movs r1, #12 + 8002928: 4858 ldr r0, [pc, #352] ; (8002a8c ) + 800292a: f000 f9fb bl 8002d24 + 800292e: e0bb b.n 8002aa8 + 8002930: 4d52 ldr r5, [pc, #328] ; (8002a7c ) + 8002932: 4e57 ldr r6, [pc, #348] ; (8002a90 ) + 8002934: 882b ldrh r3, [r5, #0] + 8002936: aa02 add r2, sp, #8 + 8002938: 8053 strh r3, [r2, #2] + 800293a: 2102 movs r1, #2 + 800293c: ab02 add r3, sp, #8 + 800293e: 1c98 adds r0, r3, #2 + 8002940: f000 f9f0 bl 8002d24 + 8002944: 2800 cmp r0, #0 + 8002946: d1f8 bne.n 800293a + 8002948: 3504 adds r5, #4 + 800294a: 42b5 cmp r5, r6 + 800294c: d1f2 bne.n 8002934 + 800294e: 0004 movs r4, r0 + 8002950: e0aa b.n 8002aa8 + 8002952: 2c01 cmp r4, #1 + 8002954: d100 bne.n 8002958 + 8002956: e0a5 b.n 8002aa4 + 8002958: 2c02 cmp r4, #2 + 800295a: d100 bne.n 800295e + 800295c: e0cc b.n 8002af8 + 800295e: 2c03 cmp r4, #3 + 8002960: d100 bne.n 8002964 + 8002962: e0cd b.n 8002b00 + 8002964: 2c04 cmp r4, #4 + 8002966: d100 bne.n 800296a + 8002968: e0cd b.n 8002b06 + 800296a: 2c05 cmp r4, #5 + 800296c: d100 bne.n 8002970 + 800296e: e0d7 b.n 8002b20 + 8002970: 2c06 cmp r4, #6 + 8002972: d000 beq.n 8002976 + 8002974: e098 b.n 8002aa8 + 8002976: 9901 ldr r1, [sp, #4] + 8002978: 1c4d adds r5, r1, #1 + 800297a: 4a41 ldr r2, [pc, #260] ; (8002a80 ) + 800297c: 5453 strb r3, [r2, r1] + 800297e: 066b lsls r3, r5, #25 + 8002980: d100 bne.n 8002984 + 8002982: e0d7 b.n 8002b34 + 8002984: 2380 movs r3, #128 ; 0x80 + 8002986: 00db lsls r3, r3, #3 + 8002988: 9501 str r5, [sp, #4] + 800298a: 429d cmp r5, r3 + 800298c: d000 beq.n 8002990 + 800298e: e08b b.n 8002aa8 + 8002990: 4a40 ldr r2, [pc, #256] ; (8002a94 ) + 8002992: 2301 movs r3, #1 + 8002994: 68d1 ldr r1, [r2, #12] + 8002996: 420b tst r3, r1 + 8002998: d1fc bne.n 8002994 + 800299a: 4b3e ldr r3, [pc, #248] ; (8002a94 ) + 800299c: 691b ldr r3, [r3, #16] + 800299e: 061b lsls r3, r3, #24 + 80029a0: d504 bpl.n 80029ac + 80029a2: 4b3c ldr r3, [pc, #240] ; (8002a94 ) + 80029a4: 4a3c ldr r2, [pc, #240] ; (8002a98 ) + 80029a6: 605a str r2, [r3, #4] + 80029a8: 4a3c ldr r2, [pc, #240] ; (8002a9c ) + 80029aa: 605a str r2, [r3, #4] + 80029ac: 4b39 ldr r3, [pc, #228] ; (8002a94 ) + 80029ae: 691a ldr r2, [r3, #16] + 80029b0: 2102 movs r1, #2 + 80029b2: 430a orrs r2, r1 + 80029b4: 611a str r2, [r3, #16] + 80029b6: 464a mov r2, r9 + 80029b8: 615a str r2, [r3, #20] + 80029ba: 691a ldr r2, [r3, #16] + 80029bc: 313e adds r1, #62 ; 0x3e + 80029be: 430a orrs r2, r1 + 80029c0: 611a str r2, [r3, #16] + 80029c2: 001a movs r2, r3 + 80029c4: 2301 movs r3, #1 + 80029c6: 68d1 ldr r1, [r2, #12] + 80029c8: 420b tst r3, r1 + 80029ca: d1fc bne.n 80029c6 + 80029cc: 4b31 ldr r3, [pc, #196] ; (8002a94 ) + 80029ce: 68db ldr r3, [r3, #12] + 80029d0: 069b lsls r3, r3, #26 + 80029d2: d400 bmi.n 80029d6 + 80029d4: e0b3 b.n 8002b3e + 80029d6: 4b2f ldr r3, [pc, #188] ; (8002a94 ) + 80029d8: 2220 movs r2, #32 + 80029da: 60da str r2, [r3, #12] + 80029dc: 4b2d ldr r3, [pc, #180] ; (8002a94 ) + 80029de: 691a ldr r2, [r3, #16] + 80029e0: 2102 movs r1, #2 + 80029e2: 438a bics r2, r1 + 80029e4: 611a str r2, [r3, #16] + 80029e6: 691a ldr r2, [r3, #16] + 80029e8: 3901 subs r1, #1 + 80029ea: 430a orrs r2, r1 + 80029ec: 611a str r2, [r3, #16] + 80029ee: 4b24 ldr r3, [pc, #144] ; (8002a80 ) + 80029f0: 001a movs r2, r3 + 80029f2: 2180 movs r1, #128 ; 0x80 + 80029f4: 00c9 lsls r1, r1, #3 + 80029f6: 468c mov ip, r1 + 80029f8: 4462 add r2, ip + 80029fa: 0010 movs r0, r2 + 80029fc: 19da adds r2, r3, r7 + 80029fe: 0019 movs r1, r3 + 8002a00: 3302 adds r3, #2 + 8002a02: 8809 ldrh r1, [r1, #0] + 8002a04: 8011 strh r1, [r2, #0] + 8002a06: 4283 cmp r3, r0 + 8002a08: d1f8 bne.n 80029fc + 8002a0a: 4a22 ldr r2, [pc, #136] ; (8002a94 ) + 8002a0c: 2301 movs r3, #1 + 8002a0e: 68d1 ldr r1, [r2, #12] + 8002a10: 420b tst r3, r1 + 8002a12: d1fc bne.n 8002a0e + 8002a14: 4b1f ldr r3, [pc, #124] ; (8002a94 ) + 8002a16: 68db ldr r3, [r3, #12] + 8002a18: 069b lsls r3, r3, #26 + 8002a1a: d400 bmi.n 8002a1e + 8002a1c: e094 b.n 8002b48 + 8002a1e: 4b1d ldr r3, [pc, #116] ; (8002a94 ) + 8002a20: 2220 movs r2, #32 + 8002a22: 60da str r2, [r3, #12] + 8002a24: 4a1b ldr r2, [pc, #108] ; (8002a94 ) + 8002a26: 6913 ldr r3, [r2, #16] + 8002a28: 2101 movs r1, #1 + 8002a2a: 438b bics r3, r1 + 8002a2c: 6113 str r3, [r2, #16] + 8002a2e: 481c ldr r0, [pc, #112] ; (8002aa0 ) + 8002a30: f000 f978 bl 8002d24 + 8002a34: 4b0a ldr r3, [pc, #40] ; (8002a60 ) + 8002a36: 2280 movs r2, #128 ; 0x80 + 8002a38: 01d2 lsls r2, r2, #7 + 8002a3a: 635a str r2, [r3, #52] ; 0x34 + 8002a3c: 9501 str r5, [sp, #4] + 8002a3e: 2400 movs r4, #0 + 8002a40: e032 b.n 8002aa8 + 8002a42: 46c0 nop ; (mov r8, r8) + 8002a44: 40021000 .word 0x40021000 + 8002a48: 40014800 .word 0x40014800 + 8002a4c: 40014400 .word 0x40014400 + 8002a50: e000e100 .word 0xe000e100 + 8002a54: ffff00ff .word 0xffff00ff + 8002a58: 40002000 .word 0x40002000 + 8002a5c: 0000ffff .word 0x0000ffff + 8002a60: 40000400 .word 0x40000400 + 8002a64: 40012400 .word 0x40012400 + 8002a68: 00000a8b .word 0x00000a8b + 8002a6c: 08007c00 .word 0x08007c00 + 8002a70: 200002a8 .word 0x200002a8 + 8002a74: 200002a4 .word 0x200002a4 + 8002a78: 2000029c .word 0x2000029c + 8002a7c: 08007c00 .word 0x08007c00 + 8002a80: 200004f4 .word 0x200004f4 + 8002a84: 20000194 .word 0x20000194 + 8002a88: 200002a0 .word 0x200002a0 + 8002a8c: 080031d8 .word 0x080031d8 + 8002a90: 08008000 .word 0x08008000 + 8002a94: 40022000 .word 0x40022000 + 8002a98: 45670123 .word 0x45670123 + 8002a9c: cdef89ab .word 0xcdef89ab + 8002aa0: 080031d4 .word 0x080031d4 + 8002aa4: 9300 str r3, [sp, #0] + 8002aa6: 3401 adds r4, #1 + 8002aa8: 4b2d ldr r3, [pc, #180] ; (8002b60 ) + 8002aaa: 6859 ldr r1, [r3, #4] + 8002aac: 3101 adds r1, #1 + 8002aae: 22ff movs r2, #255 ; 0xff + 8002ab0: 400a ands r2, r1 + 8002ab2: 605a str r2, [r3, #4] + 8002ab4: 681a ldr r2, [r3, #0] + 8002ab6: 685b ldr r3, [r3, #4] + 8002ab8: 429a cmp r2, r3 + 8002aba: d100 bne.n 8002abe + 8002abc: e715 b.n 80028ea + 8002abe: 4b29 ldr r3, [pc, #164] ; (8002b64 ) + 8002ac0: 2200 movs r2, #0 + 8002ac2: 625a str r2, [r3, #36] ; 0x24 + 8002ac4: 4b26 ldr r3, [pc, #152] ; (8002b60 ) + 8002ac6: 685a ldr r2, [r3, #4] + 8002ac8: 189b adds r3, r3, r2 + 8002aca: 7a1b ldrb r3, [r3, #8] + 8002acc: b2db uxtb r3, r3 + 8002ace: 2c00 cmp r4, #0 + 8002ad0: d000 beq.n 8002ad4 + 8002ad2: e73e b.n 8002952 + 8002ad4: 2b4c cmp r3, #76 ; 0x4c + 8002ad6: d03c beq.n 8002b52 + 8002ad8: 2b54 cmp r3, #84 ; 0x54 + 8002ada: d100 bne.n 8002ade + 8002adc: e71c b.n 8002918 + 8002ade: 2b3f cmp r3, #63 ; 0x3f + 8002ae0: d100 bne.n 8002ae4 + 8002ae2: e720 b.n 8002926 + 8002ae4: 2b57 cmp r3, #87 ; 0x57 + 8002ae6: d036 beq.n 8002b56 + 8002ae8: 2b52 cmp r3, #82 ; 0x52 + 8002aea: d100 bne.n 8002aee + 8002aec: e720 b.n 8002930 + 8002aee: 2b53 cmp r3, #83 ; 0x53 + 8002af0: d1da bne.n 8002aa8 + 8002af2: f7ff fc0d bl 8002310 + 8002af6: e7d7 b.n 8002aa8 + 8002af8: 4a1b ldr r2, [pc, #108] ; (8002b68 ) + 8002afa: 6013 str r3, [r2, #0] + 8002afc: 3401 adds r4, #1 + 8002afe: e7d3 b.n 8002aa8 + 8002b00: 469a mov sl, r3 + 8002b02: 3401 adds r4, #1 + 8002b04: e7d0 b.n 8002aa8 + 8002b06: 021a lsls r2, r3, #8 + 8002b08: 21fe movs r1, #254 ; 0xfe + 8002b0a: 01c9 lsls r1, r1, #7 + 8002b0c: 400a ands r2, r1 + 8002b0e: 4651 mov r1, sl + 8002b10: 4311 orrs r1, r2 + 8002b12: 468a mov sl, r1 + 8002b14: 09db lsrs r3, r3, #7 + 8002b16: 469b mov fp, r3 + 8002b18: 2300 movs r3, #0 + 8002b1a: 4698 mov r8, r3 + 8002b1c: 3401 adds r4, #1 + 8002b1e: e7c3 b.n 8002aa8 + 8002b20: 4640 mov r0, r8 + 8002b22: 1c42 adds r2, r0, #1 + 8002b24: a90e add r1, sp, #56 ; 0x38 + 8002b26: 540b strb r3, [r1, r0] + 8002b28: 4690 mov r8, r2 + 8002b2a: 9b00 ldr r3, [sp, #0] + 8002b2c: 429a cmp r2, r3 + 8002b2e: d1bb bne.n 8002aa8 + 8002b30: 2400 movs r4, #0 + 8002b32: e7b9 b.n 8002aa8 + 8002b34: 2101 movs r1, #1 + 8002b36: 480d ldr r0, [pc, #52] ; (8002b6c ) + 8002b38: f000 f8f4 bl 8002d24 + 8002b3c: e722 b.n 8002984 + 8002b3e: 2101 movs r1, #1 + 8002b40: 480b ldr r0, [pc, #44] ; (8002b70 ) + 8002b42: f000 f8ef bl 8002d24 + 8002b46: e749 b.n 80029dc + 8002b48: 2101 movs r1, #1 + 8002b4a: 4809 ldr r0, [pc, #36] ; (8002b70 ) + 8002b4c: f000 f8ea bl 8002d24 + 8002b50: e768 b.n 8002a24 + 8002b52: 2401 movs r4, #1 + 8002b54: e7a8 b.n 8002aa8 + 8002b56: 2300 movs r3, #0 + 8002b58: 9301 str r3, [sp, #4] + 8002b5a: 2406 movs r4, #6 + 8002b5c: e7a4 b.n 8002aa8 + 8002b5e: 46c0 nop ; (mov r8, r8) + 8002b60: 20000194 .word 0x20000194 + 8002b64: 40002000 .word 0x40002000 + 8002b68: 200002a4 .word 0x200002a4 + 8002b6c: 080031d4 .word 0x080031d4 + 8002b70: 080031e8 .word 0x080031e8 + +08002b74 : + 8002b74: 4770 bx lr + ... + +08002b78 : + 8002b78: b082 sub sp, #8 + 8002b7a: 4b0c ldr r3, [pc, #48] ; (8002bac ) + 8002b7c: 6999 ldr r1, [r3, #24] + 8002b7e: 2201 movs r2, #1 + 8002b80: 4311 orrs r1, r2 + 8002b82: 6199 str r1, [r3, #24] + 8002b84: 6999 ldr r1, [r3, #24] + 8002b86: 400a ands r2, r1 + 8002b88: 9200 str r2, [sp, #0] + 8002b8a: 9a00 ldr r2, [sp, #0] + 8002b8c: 69da ldr r2, [r3, #28] + 8002b8e: 2180 movs r1, #128 ; 0x80 + 8002b90: 0549 lsls r1, r1, #21 + 8002b92: 430a orrs r2, r1 + 8002b94: 61da str r2, [r3, #28] + 8002b96: 69db ldr r3, [r3, #28] + 8002b98: 400b ands r3, r1 + 8002b9a: 9301 str r3, [sp, #4] + 8002b9c: 9b01 ldr r3, [sp, #4] + 8002b9e: 4a04 ldr r2, [pc, #16] ; (8002bb0 ) + 8002ba0: 6813 ldr r3, [r2, #0] + 8002ba2: 2110 movs r1, #16 + 8002ba4: 430b orrs r3, r1 + 8002ba6: 6013 str r3, [r2, #0] + 8002ba8: b002 add sp, #8 + 8002baa: 4770 bx lr + 8002bac: 40021000 .word 0x40021000 + 8002bb0: 40010000 .word 0x40010000 + +08002bb4 : + 8002bb4: 4770 bx lr + +08002bb6 : + 8002bb6: e7fe b.n 8002bb6 + +08002bb8 : + 8002bb8: 4770 bx lr + +08002bba : + 8002bba: 4770 bx lr + +08002bbc : + 8002bbc: b510 push {r4, lr} + 8002bbe: f7fd fb51 bl 8000264 + 8002bc2: bd10 pop {r4, pc} + +08002bc4 : + 8002bc4: b510 push {r4, lr} + 8002bc6: 4802 ldr r0, [pc, #8] ; (8002bd0 ) + 8002bc8: f7fe faa8 bl 800111c + 8002bcc: bd10 pop {r4, pc} + 8002bce: 46c0 nop ; (mov r8, r8) + 8002bd0: 20000d20 .word 0x20000d20 + +08002bd4 : + 8002bd4: 4b13 ldr r3, [pc, #76] ; (8002c24 ) + 8002bd6: 681a ldr r2, [r3, #0] + 8002bd8: 2101 movs r1, #1 + 8002bda: 430a orrs r2, r1 + 8002bdc: 601a str r2, [r3, #0] + 8002bde: 685a ldr r2, [r3, #4] + 8002be0: 4811 ldr r0, [pc, #68] ; (8002c28 ) + 8002be2: 4002 ands r2, r0 + 8002be4: 605a str r2, [r3, #4] + 8002be6: 681a ldr r2, [r3, #0] + 8002be8: 4810 ldr r0, [pc, #64] ; (8002c2c ) + 8002bea: 4002 ands r2, r0 + 8002bec: 601a str r2, [r3, #0] + 8002bee: 681a ldr r2, [r3, #0] + 8002bf0: 480f ldr r0, [pc, #60] ; (8002c30 ) + 8002bf2: 4002 ands r2, r0 + 8002bf4: 601a str r2, [r3, #0] + 8002bf6: 685a ldr r2, [r3, #4] + 8002bf8: 480e ldr r0, [pc, #56] ; (8002c34 ) + 8002bfa: 4002 ands r2, r0 + 8002bfc: 605a str r2, [r3, #4] + 8002bfe: 6ada ldr r2, [r3, #44] ; 0x2c + 8002c00: 200f movs r0, #15 + 8002c02: 4382 bics r2, r0 + 8002c04: 62da str r2, [r3, #44] ; 0x2c + 8002c06: 6b1a ldr r2, [r3, #48] ; 0x30 + 8002c08: 480b ldr r0, [pc, #44] ; (8002c38 ) + 8002c0a: 4002 ands r2, r0 + 8002c0c: 631a str r2, [r3, #48] ; 0x30 + 8002c0e: 6b1a ldr r2, [r3, #48] ; 0x30 + 8002c10: 2080 movs r0, #128 ; 0x80 + 8002c12: 4302 orrs r2, r0 + 8002c14: 631a str r2, [r3, #48] ; 0x30 + 8002c16: 6b5a ldr r2, [r3, #52] ; 0x34 + 8002c18: 438a bics r2, r1 + 8002c1a: 635a str r2, [r3, #52] ; 0x34 + 8002c1c: 2200 movs r2, #0 + 8002c1e: 609a str r2, [r3, #8] + 8002c20: 4770 bx lr + 8002c22: 46c0 nop ; (mov r8, r8) + 8002c24: 40021000 .word 0x40021000 + 8002c28: 08ffb80c .word 0x08ffb80c + 8002c2c: fef6ffff .word 0xfef6ffff + 8002c30: fffbffff .word 0xfffbffff + 8002c34: ffc0ffff .word 0xffc0ffff + 8002c38: fffffe6c .word 0xfffffe6c + +08002c3c : + 8002c3c: b510 push {r4, lr} + 8002c3e: 2200 movs r2, #0 + 8002c40: 4911 ldr r1, [pc, #68] ; (8002c88 ) + 8002c42: 4812 ldr r0, [pc, #72] ; (8002c8c ) + 8002c44: f7fe ff06 bl 8001a54 + 8002c48: 2800 cmp r0, #0 + 8002c4a: d111 bne.n 8002c70 + 8002c4c: 4910 ldr r1, [pc, #64] ; (8002c90 ) + 8002c4e: 480f ldr r0, [pc, #60] ; (8002c8c ) + 8002c50: f7fe ff1c bl 8001a8c + 8002c54: 2800 cmp r0, #0 + 8002c56: d10e bne.n 8002c76 + 8002c58: 490e ldr r1, [pc, #56] ; (8002c94 ) + 8002c5a: 480c ldr r0, [pc, #48] ; (8002c8c ) + 8002c5c: f7fe fea0 bl 80019a0 + 8002c60: 2800 cmp r0, #0 + 8002c62: d10b bne.n 8002c7c + 8002c64: 4809 ldr r0, [pc, #36] ; (8002c8c ) + 8002c66: f7fe ff1a bl 8001a9e + 8002c6a: 2800 cmp r0, #0 + 8002c6c: d109 bne.n 8002c82 + 8002c6e: bd10 pop {r4, pc} + 8002c70: f7ff ff80 bl 8002b74 + 8002c74: e7ea b.n 8002c4c + 8002c76: f7ff ff7d bl 8002b74 + 8002c7a: e7ed b.n 8002c58 + 8002c7c: f7ff ff7a bl 8002b74 + 8002c80: e7f0 b.n 8002c64 + 8002c82: f7ff ff77 bl 8002b74 + 8002c86: e7f2 b.n 8002c6e + 8002c88: 20000124 .word 0x20000124 + 8002c8c: 200008fc .word 0x200008fc + 8002c90: 20000000 .word 0x20000000 + 8002c94: 20000114 .word 0x20000114 + +08002c98 : + 8002c98: 2000 movs r0, #0 + 8002c9a: 4770 bx lr + +08002c9c : + 8002c9c: 2000 movs r0, #0 + 8002c9e: 4770 bx lr + +08002ca0 : + 8002ca0: b570 push {r4, r5, r6, lr} + 8002ca2: 0005 movs r5, r0 + 8002ca4: 680e ldr r6, [r1, #0] + 8002ca6: 4c13 ldr r4, [pc, #76] ; (8002cf4 ) + 8002ca8: 0001 movs r1, r0 + 8002caa: 0020 movs r0, r4 + 8002cac: f7fe fe8c bl 80019c8 + 8002cb0: 0020 movs r0, r4 + 8002cb2: f7fe feaf bl 8001a14 + 8002cb6: 2e00 cmp r6, #0 + 8002cb8: d017 beq.n 8002cea + 8002cba: 002c movs r4, r5 + 8002cbc: 19a8 adds r0, r5, r6 + 8002cbe: 4d0e ldr r5, [pc, #56] ; (8002cf8 ) + 8002cc0: 26ff movs r6, #255 ; 0xff + 8002cc2: 002a movs r2, r5 + 8002cc4: 682b ldr r3, [r5, #0] + 8002cc6: 6869 ldr r1, [r5, #4] + 8002cc8: 3301 adds r3, #1 + 8002cca: 4033 ands r3, r6 + 8002ccc: 428b cmp r3, r1 + 8002cce: d00e beq.n 8002cee + 8002cd0: 6813 ldr r3, [r2, #0] + 8002cd2: 7821 ldrb r1, [r4, #0] + 8002cd4: 18d3 adds r3, r2, r3 + 8002cd6: 7219 strb r1, [r3, #8] + 8002cd8: 6813 ldr r3, [r2, #0] + 8002cda: 3301 adds r3, #1 + 8002cdc: 4033 ands r3, r6 + 8002cde: 6013 str r3, [r2, #0] + 8002ce0: 3401 adds r4, #1 + 8002ce2: 4284 cmp r4, r0 + 8002ce4: d1ee bne.n 8002cc4 + 8002ce6: 2000 movs r0, #0 + 8002ce8: e002 b.n 8002cf0 + 8002cea: 2000 movs r0, #0 + 8002cec: e000 b.n 8002cf0 + 8002cee: 2002 movs r0, #2 + 8002cf0: bd70 pop {r4, r5, r6, pc} + 8002cf2: 46c0 nop ; (mov r8, r8) + 8002cf4: 200008fc .word 0x200008fc + 8002cf8: 20000194 .word 0x20000194 + +08002cfc : + 8002cfc: b510 push {r4, lr} + 8002cfe: 4c06 ldr r4, [pc, #24] ; (8002d18 ) + 8002d00: 2200 movs r2, #0 + 8002d02: 4906 ldr r1, [pc, #24] ; (8002d1c ) + 8002d04: 0020 movs r0, r4 + 8002d06: f7fe fe54 bl 80019b2 + 8002d0a: 4905 ldr r1, [pc, #20] ; (8002d20 ) + 8002d0c: 0020 movs r0, r4 + 8002d0e: f7fe fe5b bl 80019c8 + 8002d12: 2000 movs r0, #0 + 8002d14: bd10 pop {r4, pc} + 8002d16: 46c0 nop ; (mov r8, r8) + 8002d18: 200008fc .word 0x200008fc + 8002d1c: 20000c20 .word 0x20000c20 + 8002d20: 20000b20 .word 0x20000b20 + +08002d24 : + 8002d24: b510 push {r4, lr} + 8002d26: 0003 movs r3, r0 + 8002d28: 4c09 ldr r4, [pc, #36] ; (8002d50 ) + 8002d2a: 2086 movs r0, #134 ; 0x86 + 8002d2c: 0080 lsls r0, r0, #2 + 8002d2e: 5824 ldr r4, [r4, r0] + 8002d30: 3804 subs r0, #4 + 8002d32: 5824 ldr r4, [r4, r0] + 8002d34: 2001 movs r0, #1 + 8002d36: 2c00 cmp r4, #0 + 8002d38: d000 beq.n 8002d3c + 8002d3a: bd10 pop {r4, pc} + 8002d3c: 4c04 ldr r4, [pc, #16] ; (8002d50 ) + 8002d3e: 000a movs r2, r1 + 8002d40: 0019 movs r1, r3 + 8002d42: 0020 movs r0, r4 + 8002d44: f7fe fe35 bl 80019b2 + 8002d48: 0020 movs r0, r4 + 8002d4a: f7fe fe44 bl 80019d6 + 8002d4e: e7f4 b.n 8002d3a + 8002d50: 200008fc .word 0x200008fc + +08002d54 : + 8002d54: 2800 cmp r0, #0 + 8002d56: d003 beq.n 8002d60 + 8002d58: 3802 subs r0, #2 + 8002d5a: 1e43 subs r3, r0, #1 + 8002d5c: 4198 sbcs r0, r3 + 8002d5e: 3001 adds r0, #1 + 8002d60: 4770 bx lr + ... + +08002d64 : + 8002d64: b500 push {lr} + 8002d66: b083 sub sp, #12 + 8002d68: 4b0c ldr r3, [pc, #48] ; (8002d9c ) + 8002d6a: 6802 ldr r2, [r0, #0] + 8002d6c: 429a cmp r2, r3 + 8002d6e: d001 beq.n 8002d74 + 8002d70: b003 add sp, #12 + 8002d72: bd00 pop {pc} + 8002d74: 4a0a ldr r2, [pc, #40] ; (8002da0 ) + 8002d76: 69d1 ldr r1, [r2, #28] + 8002d78: 2080 movs r0, #128 ; 0x80 + 8002d7a: 0400 lsls r0, r0, #16 + 8002d7c: 4301 orrs r1, r0 + 8002d7e: 61d1 str r1, [r2, #28] + 8002d80: 69d3 ldr r3, [r2, #28] + 8002d82: 4003 ands r3, r0 + 8002d84: 9301 str r3, [sp, #4] + 8002d86: 9b01 ldr r3, [sp, #4] + 8002d88: 2200 movs r2, #0 + 8002d8a: 2100 movs r1, #0 + 8002d8c: 201f movs r0, #31 + 8002d8e: f7fd fa71 bl 8000274 + 8002d92: 201f movs r0, #31 + 8002d94: f7fd faa0 bl 80002d8 + 8002d98: e7ea b.n 8002d70 + 8002d9a: 46c0 nop ; (mov r8, r8) + 8002d9c: 40005c00 .word 0x40005c00 + 8002da0: 40021000 .word 0x40021000 + +08002da4 : + 8002da4: b510 push {r4, lr} + 8002da6: 0001 movs r1, r0 + 8002da8: 31ed adds r1, #237 ; 0xed + 8002daa: 31ff adds r1, #255 ; 0xff + 8002dac: 2387 movs r3, #135 ; 0x87 + 8002dae: 009b lsls r3, r3, #2 + 8002db0: 58c0 ldr r0, [r0, r3] + 8002db2: f7fe fe91 bl 8001ad8 + 8002db6: bd10 pop {r4, pc} + +08002db8 : + 8002db8: b510 push {r4, lr} + 8002dba: 00cb lsls r3, r1, #3 + 8002dbc: 1a5b subs r3, r3, r1 + 8002dbe: 009b lsls r3, r3, #2 + 8002dc0: 18c3 adds r3, r0, r3 + 8002dc2: 3319 adds r3, #25 + 8002dc4: 33ff adds r3, #255 ; 0xff + 8002dc6: 681a ldr r2, [r3, #0] + 8002dc8: 2387 movs r3, #135 ; 0x87 + 8002dca: 009b lsls r3, r3, #2 + 8002dcc: 58c0 ldr r0, [r0, r3] + 8002dce: f7fe feb7 bl 8001b40 + 8002dd2: bd10 pop {r4, pc} + +08002dd4 : + 8002dd4: b510 push {r4, lr} + 8002dd6: 00cb lsls r3, r1, #3 + 8002dd8: 1a5b subs r3, r3, r1 + 8002dda: 009b lsls r3, r3, #2 + 8002ddc: 18c3 adds r3, r0, r3 + 8002dde: 6b9a ldr r2, [r3, #56] ; 0x38 + 8002de0: 2387 movs r3, #135 ; 0x87 + 8002de2: 009b lsls r3, r3, #2 + 8002de4: 58c0 ldr r0, [r0, r3] + 8002de6: f7fe fee8 bl 8001bba + 8002dea: bd10 pop {r4, pc} + +08002dec : + 8002dec: b510 push {r4, lr} + 8002dee: 2387 movs r3, #135 ; 0x87 + 8002df0: 009b lsls r3, r3, #2 + 8002df2: 58c0 ldr r0, [r0, r3] + 8002df4: f7fe ff7b bl 8001cee + 8002df8: bd10 pop {r4, pc} + +08002dfa : + 8002dfa: b570 push {r4, r5, r6, lr} + 8002dfc: 0004 movs r4, r0 + 8002dfe: 6883 ldr r3, [r0, #8] + 8002e00: 2b02 cmp r3, #2 + 8002e02: d109 bne.n 8002e18 + 8002e04: 2587 movs r5, #135 ; 0x87 + 8002e06: 00ad lsls r5, r5, #2 + 8002e08: 2101 movs r1, #1 + 8002e0a: 5960 ldr r0, [r4, r5] + 8002e0c: f7fe ff5a bl 8001cc4 + 8002e10: 5960 ldr r0, [r4, r5] + 8002e12: f7fe ff34 bl 8001c7e + 8002e16: bd70 pop {r4, r5, r6, pc} + 8002e18: f7ff feac bl 8002b74 + 8002e1c: e7f2 b.n 8002e04 + ... + +08002e20 : + 8002e20: b510 push {r4, lr} + 8002e22: 0004 movs r4, r0 + 8002e24: 2387 movs r3, #135 ; 0x87 + 8002e26: 009b lsls r3, r3, #2 + 8002e28: 58c0 ldr r0, [r0, r3] + 8002e2a: f7fe ff4e bl 8001cca + 8002e2e: 69a3 ldr r3, [r4, #24] + 8002e30: 2b00 cmp r3, #0 + 8002e32: d004 beq.n 8002e3e + 8002e34: 4a02 ldr r2, [pc, #8] ; (8002e40 ) + 8002e36: 6913 ldr r3, [r2, #16] + 8002e38: 2106 movs r1, #6 + 8002e3a: 430b orrs r3, r1 + 8002e3c: 6113 str r3, [r2, #16] + 8002e3e: bd10 pop {r4, pc} + 8002e40: e000ed00 .word 0xe000ed00 + +08002e44 : + 8002e44: b510 push {r4, lr} + 8002e46: 0004 movs r4, r0 + 8002e48: 6983 ldr r3, [r0, #24] + 8002e4a: 2b00 cmp r3, #0 + 8002e4c: d105 bne.n 8002e5a + 8002e4e: 2387 movs r3, #135 ; 0x87 + 8002e50: 009b lsls r3, r3, #2 + 8002e52: 58e0 ldr r0, [r4, r3] + 8002e54: f7fe ff44 bl 8001ce0 + 8002e58: bd10 pop {r4, pc} + 8002e5a: 4a04 ldr r2, [pc, #16] ; (8002e6c ) + 8002e5c: 6913 ldr r3, [r2, #16] + 8002e5e: 2106 movs r1, #6 + 8002e60: 438b bics r3, r1 + 8002e62: 6113 str r3, [r2, #16] + 8002e64: f7ff fbe6 bl 8002634 + 8002e68: e7f1 b.n 8002e4e + 8002e6a: 46c0 nop ; (mov r8, r8) + 8002e6c: e000ed00 .word 0xe000ed00 + +08002e70 : + 8002e70: b570 push {r4, r5, r6, lr} + 8002e72: 0004 movs r4, r0 + 8002e74: 481d ldr r0, [pc, #116] ; (8002eec ) + 8002e76: 2387 movs r3, #135 ; 0x87 + 8002e78: 009b lsls r3, r3, #2 + 8002e7a: 50c4 str r4, [r0, r3] + 8002e7c: 3304 adds r3, #4 + 8002e7e: 50e0 str r0, [r4, r3] + 8002e80: 4b1b ldr r3, [pc, #108] ; (8002ef0 ) + 8002e82: 6003 str r3, [r0, #0] + 8002e84: 2308 movs r3, #8 + 8002e86: 6043 str r3, [r0, #4] + 8002e88: 3b06 subs r3, #6 + 8002e8a: 6083 str r3, [r0, #8] + 8002e8c: 6103 str r3, [r0, #16] + 8002e8e: 2300 movs r3, #0 + 8002e90: 6183 str r3, [r0, #24] + 8002e92: 61c3 str r3, [r0, #28] + 8002e94: 6203 str r3, [r0, #32] + 8002e96: f7fd fb31 bl 80004fc + 8002e9a: 2800 cmp r0, #0 + 8002e9c: d123 bne.n 8002ee6 + 8002e9e: 2588 movs r5, #136 ; 0x88 + 8002ea0: 00ad lsls r5, r5, #2 + 8002ea2: 2318 movs r3, #24 + 8002ea4: 2200 movs r2, #0 + 8002ea6: 2100 movs r1, #0 + 8002ea8: 5960 ldr r0, [r4, r5] + 8002eaa: f7fe fc2f bl 800170c + 8002eae: 2358 movs r3, #88 ; 0x58 + 8002eb0: 2200 movs r2, #0 + 8002eb2: 2180 movs r1, #128 ; 0x80 + 8002eb4: 5960 ldr r0, [r4, r5] + 8002eb6: f7fe fc29 bl 800170c + 8002eba: 23c0 movs r3, #192 ; 0xc0 + 8002ebc: 2200 movs r2, #0 + 8002ebe: 2181 movs r1, #129 ; 0x81 + 8002ec0: 5960 ldr r0, [r4, r5] + 8002ec2: f7fe fc23 bl 800170c + 8002ec6: 2388 movs r3, #136 ; 0x88 + 8002ec8: 005b lsls r3, r3, #1 + 8002eca: 2200 movs r2, #0 + 8002ecc: 2101 movs r1, #1 + 8002ece: 5960 ldr r0, [r4, r5] + 8002ed0: f7fe fc1c bl 800170c + 8002ed4: 2380 movs r3, #128 ; 0x80 + 8002ed6: 5960 ldr r0, [r4, r5] + 8002ed8: 005b lsls r3, r3, #1 + 8002eda: 2200 movs r2, #0 + 8002edc: 2182 movs r1, #130 ; 0x82 + 8002ede: f7fe fc15 bl 800170c + 8002ee2: 2000 movs r0, #0 + 8002ee4: bd70 pop {r4, r5, r6, pc} + 8002ee6: f7ff fe45 bl 8002b74 + 8002eea: e7d8 b.n 8002e9e + 8002eec: 20000d20 .word 0x20000d20 + 8002ef0: 40005c00 .word 0x40005c00 + +08002ef4 : + 8002ef4: b510 push {r4, lr} + 8002ef6: 2388 movs r3, #136 ; 0x88 + 8002ef8: 009b lsls r3, r3, #2 + 8002efa: 58c0 ldr r0, [r0, r3] + 8002efc: f7fd fb50 bl 80005a0 + 8002f00: f7ff ff28 bl 8002d54 + 8002f04: bd10 pop {r4, pc} + +08002f06 : + 8002f06: b510 push {r4, lr} + 8002f08: 0014 movs r4, r2 + 8002f0a: 001a movs r2, r3 + 8002f0c: 2388 movs r3, #136 ; 0x88 + 8002f0e: 009b lsls r3, r3, #2 + 8002f10: 58c0 ldr r0, [r0, r3] + 8002f12: 0023 movs r3, r4 + 8002f14: f7fd fb68 bl 80005e8 + 8002f18: f7ff ff1c bl 8002d54 + 8002f1c: bd10 pop {r4, pc} + +08002f1e : + 8002f1e: b510 push {r4, lr} + 8002f20: 2388 movs r3, #136 ; 0x88 + 8002f22: 009b lsls r3, r3, #2 + 8002f24: 58c0 ldr r0, [r0, r3] + 8002f26: f7fd fce7 bl 80008f8 + 8002f2a: f7ff ff13 bl 8002d54 + 8002f2e: bd10 pop {r4, pc} + +08002f30 : + 8002f30: b510 push {r4, lr} + 8002f32: 2388 movs r3, #136 ; 0x88 + 8002f34: 009b lsls r3, r3, #2 + 8002f36: 58c0 ldr r0, [r0, r3] + 8002f38: f7fd fee2 bl 8000d00 + 8002f3c: f7ff ff0a bl 8002d54 + 8002f40: bd10 pop {r4, pc} + +08002f42 : + 8002f42: b510 push {r4, lr} + 8002f44: 2388 movs r3, #136 ; 0x88 + 8002f46: 009b lsls r3, r3, #2 + 8002f48: 58c0 ldr r0, [r0, r3] + 8002f4a: f7fd ff3f bl 8000dcc + 8002f4e: f7ff ff01 bl 8002d54 + 8002f52: bd10 pop {r4, pc} + +08002f54 : + 8002f54: 2388 movs r3, #136 ; 0x88 + 8002f56: 009b lsls r3, r3, #2 + 8002f58: 58c3 ldr r3, [r0, r3] + 8002f5a: b24a sxtb r2, r1 + 8002f5c: 2a00 cmp r2, #0 + 8002f5e: db09 blt.n 8002f74 + 8002f60: 227f movs r2, #127 ; 0x7f + 8002f62: 4011 ands r1, r2 + 8002f64: 00ca lsls r2, r1, #3 + 8002f66: 1a51 subs r1, r2, r1 + 8002f68: 0089 lsls r1, r1, #2 + 8002f6a: 185b adds r3, r3, r1 + 8002f6c: 330b adds r3, #11 + 8002f6e: 33ff adds r3, #255 ; 0xff + 8002f70: 7818 ldrb r0, [r3, #0] + 8002f72: 4770 bx lr + 8002f74: 227f movs r2, #127 ; 0x7f + 8002f76: 4011 ands r1, r2 + 8002f78: 00ca lsls r2, r1, #3 + 8002f7a: 1a51 subs r1, r2, r1 + 8002f7c: 0089 lsls r1, r1, #2 + 8002f7e: 185b adds r3, r3, r1 + 8002f80: 332a adds r3, #42 ; 0x2a + 8002f82: 7818 ldrb r0, [r3, #0] + 8002f84: e7f5 b.n 8002f72 + +08002f86 : + 8002f86: b510 push {r4, lr} + 8002f88: 2388 movs r3, #136 ; 0x88 + 8002f8a: 009b lsls r3, r3, #2 + 8002f8c: 58c0 ldr r0, [r0, r3] + 8002f8e: f7fd fb10 bl 80005b2 + 8002f92: f7ff fedf bl 8002d54 + 8002f96: bd10 pop {r4, pc} + +08002f98 : + 8002f98: b510 push {r4, lr} + 8002f9a: 2488 movs r4, #136 ; 0x88 + 8002f9c: 00a4 lsls r4, r4, #2 + 8002f9e: 5900 ldr r0, [r0, r4] + 8002fa0: f7fd ff96 bl 8000ed0 + 8002fa4: f7ff fed6 bl 8002d54 + 8002fa8: bd10 pop {r4, pc} + +08002faa : + 8002faa: b510 push {r4, lr} + 8002fac: 2488 movs r4, #136 ; 0x88 + 8002fae: 00a4 lsls r4, r4, #2 + 8002fb0: 5900 ldr r0, [r0, r4] + 8002fb2: f7fd fd73 bl 8000a9c + 8002fb6: f7ff fecd bl 8002d54 + 8002fba: bd10 pop {r4, pc} + +08002fbc : + 8002fbc: b510 push {r4, lr} + 8002fbe: 2388 movs r3, #136 ; 0x88 + 8002fc0: 009b lsls r3, r3, #2 + 8002fc2: 58c0 ldr r0, [r0, r3] + 8002fc4: f7fd fe90 bl 8000ce8 + 8002fc8: bd10 pop {r4, pc} + ... + +08002fcc : + 8002fcc: 4800 ldr r0, [pc, #0] ; (8002fd0 ) + 8002fce: 4770 bx lr + 8002fd0: 200002ac .word 0x200002ac + +08002fd4 : + 8002fd4: 4770 bx lr + ... + +08002fd8 : + 8002fd8: 2312 movs r3, #18 + 8002fda: 800b strh r3, [r1, #0] + 8002fdc: 4800 ldr r0, [pc, #0] ; (8002fe0 ) + 8002fde: 4770 bx lr + 8002fe0: 20000140 .word 0x20000140 + +08002fe4 : + 8002fe4: 2304 movs r3, #4 + 8002fe6: 800b strh r3, [r1, #0] + 8002fe8: 4800 ldr r0, [pc, #0] ; (8002fec ) + 8002fea: 4770 bx lr + 8002fec: 20000154 .word 0x20000154 + +08002ff0 : + 8002ff0: 2327 movs r3, #39 ; 0x27 + 8002ff2: 800b strh r3, [r1, #0] + 8002ff4: 4800 ldr r0, [pc, #0] ; (8002ff8 ) + 8002ff6: 4770 bx lr + 8002ff8: 080032f0 .word 0x080032f0 + +08002ffc : + 8002ffc: 2329 movs r3, #41 ; 0x29 + 8002ffe: 800b strh r3, [r1, #0] + 8003000: 4800 ldr r0, [pc, #0] ; (8003004 ) + 8003002: 4770 bx lr + 8003004: 080032c4 .word 0x080032c4 + +08003008 : + 8003008: 2317 movs r3, #23 + 800300a: 800b strh r3, [r1, #0] + 800300c: 4800 ldr r0, [pc, #0] ; (8003010 ) + 800300e: 4770 bx lr + 8003010: 0800328c .word 0x0800328c + +08003014 : + 8003014: 231d movs r3, #29 + 8003016: 800b strh r3, [r1, #0] + 8003018: 4800 ldr r0, [pc, #0] ; (800301c ) + 800301a: 4770 bx lr + 800301c: 080032a4 .word 0x080032a4 + +08003020 : + 8003020: b510 push {r4, lr} + 8003022: 0054 lsls r4, r2, #1 + 8003024: 2a00 cmp r2, #0 + 8003026: d010 beq.n 800304a + 8003028: 000b movs r3, r1 + 800302a: 1909 adds r1, r1, r4 + 800302c: 2400 movs r4, #0 + 800302e: e006 b.n 800303e + 8003030: 3237 adds r2, #55 ; 0x37 + 8003032: 701a strb r2, [r3, #0] + 8003034: 705c strb r4, [r3, #1] + 8003036: 0100 lsls r0, r0, #4 + 8003038: 3302 adds r3, #2 + 800303a: 428b cmp r3, r1 + 800303c: d005 beq.n 800304a + 800303e: 0f02 lsrs r2, r0, #28 + 8003040: 2a09 cmp r2, #9 + 8003042: d8f5 bhi.n 8003030 + 8003044: 3230 adds r2, #48 ; 0x30 + 8003046: 701a strb r2, [r3, #0] + 8003048: e7f4 b.n 8003034 + 800304a: bd10 pop {r4, pc} + +0800304c : + 800304c: b570 push {r4, r5, r6, lr} + 800304e: 231a movs r3, #26 + 8003050: 800b strh r3, [r1, #0] + 8003052: 4b0b ldr r3, [pc, #44] ; (8003080 ) + 8003054: 6818 ldr r0, [r3, #0] + 8003056: 4b0b ldr r3, [pc, #44] ; (8003084 ) + 8003058: 681b ldr r3, [r3, #0] + 800305a: 18c0 adds r0, r0, r3 + 800305c: 2800 cmp r0, #0 + 800305e: d101 bne.n 8003064 + 8003060: 4809 ldr r0, [pc, #36] ; (8003088 ) + 8003062: bd70 pop {r4, r5, r6, pc} + 8003064: 4b09 ldr r3, [pc, #36] ; (800308c ) + 8003066: 681d ldr r5, [r3, #0] + 8003068: 4c07 ldr r4, [pc, #28] ; (8003088 ) + 800306a: 1ca1 adds r1, r4, #2 + 800306c: 2208 movs r2, #8 + 800306e: f7ff ffd7 bl 8003020 + 8003072: 0021 movs r1, r4 + 8003074: 3112 adds r1, #18 + 8003076: 2204 movs r2, #4 + 8003078: 0028 movs r0, r5 + 800307a: f7ff ffd1 bl 8003020 + 800307e: e7ef b.n 8003060 + 8003080: 1ffff7ac .word 0x1ffff7ac + 8003084: 1ffff7b4 .word 0x1ffff7b4 + 8003088: 20000158 .word 0x20000158 + 800308c: 1ffff7b0 .word 0x1ffff7b0 + +08003090 : + 8003090: 4813 ldr r0, [pc, #76] ; (80030e0 ) + 8003092: 4685 mov sp, r0 + 8003094: 4813 ldr r0, [pc, #76] ; (80030e4 ) + 8003096: 6801 ldr r1, [r0, #0] + 8003098: 0e09 lsrs r1, r1, #24 + 800309a: 4a13 ldr r2, [pc, #76] ; (80030e8 ) + 800309c: 4291 cmp r1, r2 + 800309e: d105 bne.n 80030ac + 80030a0: 4812 ldr r0, [pc, #72] ; (80030ec ) + 80030a2: 4913 ldr r1, [pc, #76] ; (80030f0 ) + 80030a4: 6001 str r1, [r0, #0] + 80030a6: 4813 ldr r0, [pc, #76] ; (80030f4 ) + 80030a8: 4913 ldr r1, [pc, #76] ; (80030f8 ) + 80030aa: 6001 str r1, [r0, #0] + +080030ac : + 80030ac: 4813 ldr r0, [pc, #76] ; (80030fc ) + 80030ae: 4914 ldr r1, [pc, #80] ; (8003100 ) + 80030b0: 4a14 ldr r2, [pc, #80] ; (8003104 ) + 80030b2: 2300 movs r3, #0 + 80030b4: e002 b.n 80030bc + +080030b6 : + 80030b6: 58d4 ldr r4, [r2, r3] + 80030b8: 50c4 str r4, [r0, r3] + 80030ba: 3304 adds r3, #4 + +080030bc : + 80030bc: 18c4 adds r4, r0, r3 + 80030be: 428c cmp r4, r1 + 80030c0: d3f9 bcc.n 80030b6 + 80030c2: 4a11 ldr r2, [pc, #68] ; (8003108 ) + 80030c4: 4c11 ldr r4, [pc, #68] ; (800310c ) + 80030c6: 2300 movs r3, #0 + 80030c8: e001 b.n 80030ce + +080030ca : + 80030ca: 6013 str r3, [r2, #0] + 80030cc: 3204 adds r2, #4 + +080030ce : + 80030ce: 42a2 cmp r2, r4 + 80030d0: d3fb bcc.n 80030ca + 80030d2: f7ff fd7f bl 8002bd4 + 80030d6: f000 f81d bl 8003114 <__libc_init_array> + 80030da: f7ff fb09 bl 80026f0
+ +080030de : + 80030de: e7fe b.n 80030de + 80030e0: 200017ff .word 0x200017ff + 80030e4: 00000004 .word 0x00000004 + 80030e8: 0000001f .word 0x0000001f + 80030ec: 40021018 .word 0x40021018 + 80030f0: 00000001 .word 0x00000001 + 80030f4: 40010000 .word 0x40010000 + 80030f8: 00000000 .word 0x00000000 + 80030fc: 20000000 .word 0x20000000 + 8003100: 20000174 .word 0x20000174 + 8003104: 08003320 .word 0x08003320 + 8003108: 20000174 .word 0x20000174 + 800310c: 20000f40 .word 0x20000f40 + +08003110 : + 8003110: e7fe b.n 8003110 + ... + +08003114 <__libc_init_array>: + 8003114: b570 push {r4, r5, r6, lr} + 8003116: 2600 movs r6, #0 + 8003118: 4d0c ldr r5, [pc, #48] ; (800314c <__libc_init_array+0x38>) + 800311a: 4c0d ldr r4, [pc, #52] ; (8003150 <__libc_init_array+0x3c>) + 800311c: 1b64 subs r4, r4, r5 + 800311e: 10a4 asrs r4, r4, #2 + 8003120: 42a6 cmp r6, r4 + 8003122: d109 bne.n 8003138 <__libc_init_array+0x24> + 8003124: 2600 movs r6, #0 + 8003126: f000 f819 bl 800315c <_init> + 800312a: 4d0a ldr r5, [pc, #40] ; (8003154 <__libc_init_array+0x40>) + 800312c: 4c0a ldr r4, [pc, #40] ; (8003158 <__libc_init_array+0x44>) + 800312e: 1b64 subs r4, r4, r5 + 8003130: 10a4 asrs r4, r4, #2 + 8003132: 42a6 cmp r6, r4 + 8003134: d105 bne.n 8003142 <__libc_init_array+0x2e> + 8003136: bd70 pop {r4, r5, r6, pc} + 8003138: 00b3 lsls r3, r6, #2 + 800313a: 58eb ldr r3, [r5, r3] + 800313c: 4798 blx r3 + 800313e: 3601 adds r6, #1 + 8003140: e7ee b.n 8003120 <__libc_init_array+0xc> + 8003142: 00b3 lsls r3, r6, #2 + 8003144: 58eb ldr r3, [r5, r3] + 8003146: 4798 blx r3 + 8003148: 3601 adds r6, #1 + 800314a: e7f2 b.n 8003132 <__libc_init_array+0x1e> + 800314c: 08003318 .word 0x08003318 + 8003150: 08003318 .word 0x08003318 + 8003154: 08003318 .word 0x08003318 + 8003158: 0800331c .word 0x0800331c + +0800315c <_init>: + 800315c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800315e: 46c0 nop ; (mov r8, r8) + 8003160: bcf8 pop {r3, r4, r5, r6, r7} + 8003162: bc08 pop {r3} + 8003164: 469e mov lr, r3 + 8003166: 4770 bx lr + +08003168 <_fini>: + 8003168: b5f8 push {r3, r4, r5, r6, r7, lr} + 800316a: 46c0 nop ; (mov r8, r8) + 800316c: bcf8 pop {r3, r4, r5, r6, r7} + 800316e: bc08 pop {r3} + 8003170: 469e mov lr, r3 + 8003172: 4770 bx lr diff --git a/hardware/esl_blaster/FW02/Release/ESLBlaster02.map b/hardware/esl_blaster/FW02/Release/ESLBlaster02.map new file mode 100644 index 0000000..e984d4d --- /dev/null +++ b/hardware/esl_blaster/FW02/Release/ESLBlaster02.map @@ -0,0 +1,1489 @@ +Archive member included to satisfy reference by file (symbol) + +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o (__aeabi_uidiv) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) (__aeabi_idiv0) +d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) (_exit) + +Allocating common symbols +Common symbol size file + +Protocol 0x1 Src/main.o +hUsbDeviceFS 0x224 Src/usb_device.o +Symbol 0x1 Src/main.o +Repeats 0x4 Src/main.o +burst_time 0x4 Src/main.o +TickCounter 0x4 Src/main.o +uwTick 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o +pFlash 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o +ByteSentCounter 0x4 Src/main.o +UserRxBufferFS 0x100 Src/usbd_cdc_if.o +CurrentByte 0x1 Src/main.o +UserTxBufferFS 0x100 Src/usbd_cdc_if.o +SymbolCounter 0x4 Src/main.o +ErrorAcc 0x4 Src/main.o +FrameData 0x4 Src/main.o +flash_data_buffer 0x400 Src/main.o +ByteCount 0x4 Src/main.o +hpcd_USB_FS 0x220 Src/usbd_conf.o +Burst 0x4 Src/main.o + +Discarded input sections + + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000000000000 0x80 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.extab 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.exidx 0x0000000000000000 0x10 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.attributes + 0x0000000000000000 0x1b d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DeInit + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetTick + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_Delay + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_SuspendTick + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_ResumeTick + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetHalVersion + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetREVID + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetDEVID + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x0000000000000000 0x1c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x0000000000000000 0x44 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Init + 0x0000000000000000 0x74 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start + 0x0000000000000000 0x6c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x0000000000000000 0x92 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort + 0x0000000000000000 0x2e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x0000000000000000 0x4a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x0000000000000000 0xca Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x0000000000000000 0xaa Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x0000000000000000 0x4a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .rodata.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetState + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetError + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x0000000000000000 0x40 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x0000000000000000 0x74 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x0000000000000000 0x160 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0x5c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Program + 0x0000000000000000 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + COMMON 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_MassErase + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBErase + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x0000000000000000 0x184 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetUserData + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_PageErase + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x0000000000000000 0xc4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x0000000000000000 0x5c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x0000000000000000 0x11c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_ReadPin + 0x0000000000000000 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_TogglePin + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x0000000000000000 0x2a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x0000000000000000 0x1c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x0000000000000000 0x1e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_TransferConfig + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x0000000000000000 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x0000000000000000 0x78 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x0000000000000000 0x52 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x0000000000000000 0x8e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x0000000000000000 0x8a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x0000000000000000 0x50 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x0000000000000000 0x88 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Init + 0x0000000000000000 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x0000000000000000 0x32 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x0000000000000000 0x1ac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x0000000000000000 0x1ac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x0000000000000000 0x1b4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x0000000000000000 0x1a4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x0000000000000000 0x90 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x0000000000000000 0x90 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x0000000000000000 0x110 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x0000000000000000 0x10c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x0000000000000000 0xac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x0000000000000000 0xb0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x0000000000000000 0x1dc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x0000000000000000 0x1d4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x0000000000000000 0xec Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x0000000000000000 0xf0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x0000000000000000 0x134 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x0000000000000000 0x138 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x0000000000000000 0x174 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Sequential_Transmit_IT + 0x0000000000000000 0x88 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Sequential_Receive_IT + 0x0000000000000000 0x8c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Sequential_Transmit_IT + 0x0000000000000000 0xa0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Sequential_Receive_IT + 0x0000000000000000 0xa0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x0000000000000000 0x36 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x0000000000000000 0x60 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x0000000000000000 0x12 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterSequentialCplt + 0x0000000000000000 0x52 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveSequentialCplt + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x0000000000000000 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITError + 0x0000000000000000 0xf8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x0000000000000000 0x118 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x0000000000000000 0x1ec Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x0000000000000000 0x86 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x0000000000000000 0xd4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x0000000000000000 0x170 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x0000000000000000 0xda Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAError + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x0000000000000000 0x74 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAAbort + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x0000000000000000 0x8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x0000000000000000 0x58 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableFastModePlus + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableFastModePlus + 0x0000000000000000 0x28 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_MspInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_Stop + 0x0000000000000000 0x32 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DeInit + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DataOutStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DataInStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SetupStageCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SOFCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ResetCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_SuspendCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ResumeCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ISOINIncompleteCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ConnectCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DisconnectCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DevConnect + 0x0000000000000000 0x2e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DevDisconnect + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_EP_Flush + 0x0000000000000000 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_ActivateRemoteWakeup + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_DeActivateRemoteWakeup + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text.HAL_PCD_GetState + 0x0000000000000000 0xa Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x0000000000000000 0x3c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0x4c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_OscConfig + 0x0000000000000000 0x4a8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DisableCSS + 0x0000000000000000 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .rodata.HAL_RCC_GetSysClockFreq.str1.4 + 0x0000000000000000 0x25 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetSysClockFreq + 0x0000000000000000 0x80 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_ClockConfig + 0x0000000000000000 0x16c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetPCLK1Freq + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x0000000000000000 0x9c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x0000000000000000 0x38 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x0000000000000000 0x2 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x0000000000000000 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_PeriphCLKConfig + 0x0000000000000000 0x144 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x0000000000000000 0x3c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x0000000000000000 0x160 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .ARM.attributes + 0x0000000000000000 0x31 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_DeInit + 0x0000000000000000 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_Init + 0x0000000000000000 0xc8 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text.LL_EXTI_StructInit + 0x0000000000000000 0xe Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_DeInit + 0x0000000000000000 0xc4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_Init + 0x0000000000000000 0xc4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text.LL_GPIO_StructInit + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_DeInit + 0x0000000000000000 0x68 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetHCLKClockFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetPCLK1ClockFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_PLL_GetFreqDomain_SYS + 0x0000000000000000 0x48 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetUSBClockFreq + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.RCC_GetSystemClockFreq + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetSystemClocksFreq + 0x0000000000000000 0x18 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetUSARTClockFreq + 0x0000000000000000 0x60 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text.LL_RCC_GetI2CClockFreq + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .comment 0x0000000000000000 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .data 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .bss 0x0000000000000000 0x0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.UTILS_SetFlashLatency + 0x0000000000000000 0x34 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.UTILS_EnablePLLAndSwitchSystem + 0x0000000000000000 0xac Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_mDelay + 0x0000000000000000 0x30 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSI + 0x0000000000000000 0x7c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSE + 0x0000000000000000 0xa4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_DeInit + 0x0000000000000000 0x26 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_Stop + 0x0000000000000000 0x1a Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_RunTestMode + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_IsoINIncomplete + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_IsoOUTIncomplete + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_DevConnected + 0x0000000000000000 0x4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_LL_DevDisconnected + 0x0000000000000000 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .text 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .data 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .bss 0x0000000000000000 0x0 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .text.USBD_GetRxCount + 0x0000000000000000 0xa Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .text 0x0000000000000000 0x0 Src/gpio.o + .data 0x0000000000000000 0x0 Src/gpio.o + .bss 0x0000000000000000 0x0 Src/gpio.o + .text 0x0000000000000000 0x0 Src/main.o + .data 0x0000000000000000 0x0 Src/main.o + .bss 0x0000000000000000 0x0 Src/main.o + .text 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .data 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .bss 0x0000000000000000 0x0 Src/stm32f0xx_hal_msp.o + .text 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .data 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .bss 0x0000000000000000 0x0 Src/stm32f0xx_it.o + .text 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .data 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .bss 0x0000000000000000 0x0 Src/system_stm32f0xx.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0x94 Src/system_stm32f0xx.o + .rodata.AHBPrescTable + 0x0000000000000000 0x10 Src/system_stm32f0xx.o + .rodata.APBPrescTable + 0x0000000000000000 0x8 Src/system_stm32f0xx.o + .text 0x0000000000000000 0x0 Src/usb_device.o + .data 0x0000000000000000 0x0 Src/usb_device.o + .bss 0x0000000000000000 0x0 Src/usb_device.o + .text 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .data 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .bss 0x0000000000000000 0x0 Src/usbd_cdc_if.o + .text 0x0000000000000000 0x0 Src/usbd_conf.o + .data 0x0000000000000000 0x0 Src/usbd_conf.o + .bss 0x0000000000000000 0x0 Src/usbd_conf.o + .text.HAL_PCD_MspDeInit + 0x0000000000000000 0x2c Src/usbd_conf.o + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_ISOINIncompleteCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_ConnectCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.HAL_PCD_DisconnectCallback + 0x0000000000000000 0xe Src/usbd_conf.o + .text.USBD_LL_DeInit + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_Stop + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_FlushEP + 0x0000000000000000 0x12 Src/usbd_conf.o + .text.USBD_LL_Delay + 0x0000000000000000 0x8 Src/usbd_conf.o + .text 0x0000000000000000 0x0 Src/usbd_desc.o + .data 0x0000000000000000 0x0 Src/usbd_desc.o + .bss 0x0000000000000000 0x0 Src/usbd_desc.o + .text 0x0000000000000000 0x14 Startup/startup_stm32f070f6px.o + .data 0x0000000000000000 0x0 Startup/startup_stm32f070f6px.o + .bss 0x0000000000000000 0x0 Startup/startup_stm32f070f6px.o + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .data.impure_data + 0x0000000000000000 0x60 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .rodata._global_impure_ptr + 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .text.memset 0x0000000000000000 0x10 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000000000 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .text._exit 0x0000000000000000 0x2 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .debug_frame 0x0000000000000000 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a(_exit.o) + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .eh_frame 0x0000000000000000 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .ARM.attributes + 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .text 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .data 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .bss 0x0000000000000000 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +FLASH 0x0000000008000000 0x0000000000008000 xr +FLASH_USER 0x0000000008007c00 0x0000000000000400 rw +RAM 0x0000000020000000 0x0000000000001800 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.o +LOAD Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o +LOAD Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o +LOAD Src/gpio.o +LOAD Src/main.o +LOAD Src/stm32f0xx_hal_msp.o +LOAD Src/stm32f0xx_it.o +LOAD Src/system_stm32f0xx.o +LOAD Src/usb_device.o +LOAD Src/usbd_cdc_if.o +LOAD Src/usbd_conf.o +LOAD Src/usbd_desc.o +LOAD Startup/startup_stm32f070f6px.o +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +START GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x00000000200017ff _estack = 0x200017ff + 0x0000000000000180 _Min_Heap_Size = 0x180 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xc0 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xc0 Startup/startup_stm32f070f6px.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000c0 . = ALIGN (0x4) + +.text 0x00000000080000c0 0x30b4 + 0x00000000080000c0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080000c0 0x48 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000008000108 0x114 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x0000000008000108 __aeabi_uidiv + 0x0000000008000108 __udivsi3 + 0x0000000008000214 __aeabi_uidivmod + .text 0x000000000800021c 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x000000000800021c __aeabi_idiv0 + 0x000000000800021c __aeabi_ldiv0 + *(.text*) + .text.HAL_InitTick + 0x0000000008000220 0x24 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000220 HAL_InitTick + .text.HAL_Init + 0x0000000008000244 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000244 HAL_Init + .text.HAL_IncTick + 0x0000000008000264 0x10 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x0000000008000264 HAL_IncTick + .text.HAL_NVIC_SetPriority + 0x0000000008000274 0x64 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x0000000008000274 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x00000000080002d8 0x14 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x00000000080002d8 HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x00000000080002ec 0x38 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x00000000080002ec HAL_SYSTICK_Config + .text.HAL_GPIO_Init + 0x0000000008000324 0x1cc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x0000000008000324 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x00000000080004f0 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x00000000080004f0 HAL_GPIO_WritePin + .text.HAL_PCD_Init + 0x00000000080004fc 0xa4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080004fc HAL_PCD_Init + .text.HAL_PCD_Start + 0x00000000080005a0 0x12 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080005a0 HAL_PCD_Start + .text.HAL_PCD_SetAddress + 0x00000000080005b2 0x36 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080005b2 HAL_PCD_SetAddress + .text.HAL_PCD_EP_Open + 0x00000000080005e8 0x310 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080005e8 HAL_PCD_EP_Open + .text.HAL_PCD_EP_Close + 0x00000000080008f8 0x1a4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080008f8 HAL_PCD_EP_Close + .text.HAL_PCD_EP_Receive + 0x0000000008000a9c 0x24c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000a9c HAL_PCD_EP_Receive + .text.HAL_PCD_EP_GetRxCount + 0x0000000008000ce8 0x16 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000ce8 HAL_PCD_EP_GetRxCount + *fill* 0x0000000008000cfe 0x2 + .text.HAL_PCD_EP_SetStall + 0x0000000008000d00 0xcc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000d00 HAL_PCD_EP_SetStall + .text.HAL_PCD_EP_ClrStall + 0x0000000008000dcc 0xd4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000dcc HAL_PCD_EP_ClrStall + .text.PCD_WritePMA + 0x0000000008000ea0 0x2e Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000ea0 PCD_WritePMA + *fill* 0x0000000008000ece 0x2 + .text.HAL_PCD_EP_Transmit + 0x0000000008000ed0 0x204 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x0000000008000ed0 HAL_PCD_EP_Transmit + .text.PCD_ReadPMA + 0x00000000080010d4 0x46 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x00000000080010d4 PCD_ReadPMA + *fill* 0x000000000800111a 0x2 + .text.HAL_PCD_IRQHandler + 0x000000000800111c 0x5f0 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + 0x000000000800111c HAL_PCD_IRQHandler + .text.HAL_PCDEx_PMAConfig + 0x000000000800170c 0x3a Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + 0x000000000800170c HAL_PCDEx_PMAConfig + *fill* 0x0000000008001746 0x2 + .text.HAL_RCC_GetHCLKFreq + 0x0000000008001748 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x0000000008001748 HAL_RCC_GetHCLKFreq + .text.LL_Init1msTick + 0x0000000008001754 0x20 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + 0x0000000008001754 LL_Init1msTick + .text.LL_SetSystemCoreClock + 0x0000000008001774 0xc Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + 0x0000000008001774 LL_SetSystemCoreClock + .text.USBD_CDC_DataIn + 0x0000000008001780 0x1a Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x000000000800179a 0x2 + .text.USBD_CDC_EP0_RxReady + 0x000000000800179c 0x34 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetFSCfgDesc + 0x00000000080017d0 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetHSCfgDesc + 0x00000000080017dc 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetOtherSpeedCfgDesc + 0x00000000080017e8 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_GetDeviceQualifierDescriptor + 0x00000000080017f4 0xc Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000080017f4 USBD_CDC_GetDeviceQualifierDescriptor + .text.USBD_CDC_DataOut + 0x0000000008001800 0x34 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_Setup + 0x0000000008001834 0x88 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_DeInit + 0x00000000080018bc 0x40 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_Init + 0x00000000080018fc 0xa4 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text.USBD_CDC_RegisterInterface + 0x00000000080019a0 0x12 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000080019a0 USBD_CDC_RegisterInterface + .text.USBD_CDC_SetTxBuffer + 0x00000000080019b2 0x16 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000080019b2 USBD_CDC_SetTxBuffer + .text.USBD_CDC_SetRxBuffer + 0x00000000080019c8 0xe Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000080019c8 USBD_CDC_SetRxBuffer + .text.USBD_CDC_TransmitPacket + 0x00000000080019d6 0x3e Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000080019d6 USBD_CDC_TransmitPacket + .text.USBD_CDC_ReceivePacket + 0x0000000008001a14 0x40 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000008001a14 USBD_CDC_ReceivePacket + .text.USBD_Init + 0x0000000008001a54 0x38 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001a54 USBD_Init + .text.USBD_RegisterClass + 0x0000000008001a8c 0x12 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001a8c USBD_RegisterClass + .text.USBD_Start + 0x0000000008001a9e 0xa Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001a9e USBD_Start + .text.USBD_SetClassConfig + 0x0000000008001aa8 0x1e Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001aa8 USBD_SetClassConfig + .text.USBD_ClrClassConfig + 0x0000000008001ac6 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001ac6 USBD_ClrClassConfig + *fill* 0x0000000008001ad6 0x2 + .text.USBD_LL_SetupStage + 0x0000000008001ad8 0x68 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001ad8 USBD_LL_SetupStage + .text.USBD_LL_DataOutStage + 0x0000000008001b40 0x7a Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001b40 USBD_LL_DataOutStage + .text.USBD_LL_DataInStage + 0x0000000008001bba 0xc4 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001bba USBD_LL_DataInStage + .text.USBD_LL_Reset + 0x0000000008001c7e 0x46 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001c7e USBD_LL_Reset + .text.USBD_LL_SetSpeed + 0x0000000008001cc4 0x6 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001cc4 USBD_LL_SetSpeed + .text.USBD_LL_Suspend + 0x0000000008001cca 0x16 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001cca USBD_LL_Suspend + .text.USBD_LL_Resume + 0x0000000008001ce0 0xe Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001ce0 USBD_LL_Resume + .text.USBD_LL_SOF + 0x0000000008001cee 0x20 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x0000000008001cee USBD_LL_SOF + .text.USBD_ParseSetupRequest + 0x0000000008001d0e 0x28 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001d0e USBD_ParseSetupRequest + .text.USBD_CtlError + 0x0000000008001d36 0x14 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001d36 USBD_CtlError + *fill* 0x0000000008001d4a 0x2 + .text.USBD_StdDevReq + 0x0000000008001d4c 0x338 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008001d4c USBD_StdDevReq + .text.USBD_StdItfReq + 0x0000000008002084 0x3c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000008002084 USBD_StdItfReq + .text.USBD_StdEPReq + 0x00000000080020c0 0x124 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x00000000080020c0 USBD_StdEPReq + .text.USBD_CtlSendData + 0x00000000080021e4 0x1c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x00000000080021e4 USBD_CtlSendData + .text.USBD_CtlContinueSendData + 0x0000000008002200 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002200 USBD_CtlContinueSendData + .text.USBD_CtlPrepareRx + 0x0000000008002210 0x20 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002210 USBD_CtlPrepareRx + .text.USBD_CtlContinueRx + 0x0000000008002230 0x10 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002230 USBD_CtlContinueRx + .text.USBD_CtlSendStatus + 0x0000000008002240 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002240 USBD_CtlSendStatus + .text.USBD_CtlReceiveStatus + 0x0000000008002258 0x18 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0000000008002258 USBD_CtlReceiveStatus + .text.MX_GPIO_Init + 0x0000000008002270 0x80 Src/gpio.o + 0x0000000008002270 MX_GPIO_Init + .text.TIM14_IRQHandler + 0x00000000080022f0 0x20 Src/main.o + 0x00000000080022f0 TIM14_IRQHandler + .text.IRStop 0x0000000008002310 0x40 Src/main.o + 0x0000000008002310 IRStop + .text.TIM16_IRQHandler + 0x0000000008002350 0x210 Src/main.o + 0x0000000008002350 TIM16_IRQHandler + .text.IRTX 0x0000000008002560 0xa8 Src/main.o + 0x0000000008002560 IRTX + .text.adc_read + 0x0000000008002608 0x2c Src/main.o + 0x0000000008002608 adc_read + .text.SystemClock_Config + 0x0000000008002634 0xbc Src/main.o + 0x0000000008002634 SystemClock_Config + .text.main 0x00000000080026f0 0x484 Src/main.o + 0x00000000080026f0 main + .text.Error_Handler + 0x0000000008002b74 0x2 Src/main.o + 0x0000000008002b74 Error_Handler + *fill* 0x0000000008002b76 0x2 + .text.HAL_MspInit + 0x0000000008002b78 0x3c Src/stm32f0xx_hal_msp.o + 0x0000000008002b78 HAL_MspInit + .text.NMI_Handler + 0x0000000008002bb4 0x2 Src/stm32f0xx_it.o + 0x0000000008002bb4 NMI_Handler + .text.HardFault_Handler + 0x0000000008002bb6 0x2 Src/stm32f0xx_it.o + 0x0000000008002bb6 HardFault_Handler + .text.SVC_Handler + 0x0000000008002bb8 0x2 Src/stm32f0xx_it.o + 0x0000000008002bb8 SVC_Handler + .text.PendSV_Handler + 0x0000000008002bba 0x2 Src/stm32f0xx_it.o + 0x0000000008002bba PendSV_Handler + .text.SysTick_Handler + 0x0000000008002bbc 0x8 Src/stm32f0xx_it.o + 0x0000000008002bbc SysTick_Handler + .text.USB_IRQHandler + 0x0000000008002bc4 0x10 Src/stm32f0xx_it.o + 0x0000000008002bc4 USB_IRQHandler + .text.SystemInit + 0x0000000008002bd4 0x68 Src/system_stm32f0xx.o + 0x0000000008002bd4 SystemInit + .text.MX_USB_DEVICE_Init + 0x0000000008002c3c 0x5c Src/usb_device.o + 0x0000000008002c3c MX_USB_DEVICE_Init + .text.CDC_DeInit_FS + 0x0000000008002c98 0x4 Src/usbd_cdc_if.o + .text.CDC_Control_FS + 0x0000000008002c9c 0x4 Src/usbd_cdc_if.o + .text.CDC_Receive_FS + 0x0000000008002ca0 0x5c Src/usbd_cdc_if.o + .text.CDC_Init_FS + 0x0000000008002cfc 0x28 Src/usbd_cdc_if.o + .text.CDC_Transmit_FS + 0x0000000008002d24 0x30 Src/usbd_cdc_if.o + 0x0000000008002d24 CDC_Transmit_FS + .text.USBD_Get_USB_Status + 0x0000000008002d54 0xe Src/usbd_conf.o + *fill* 0x0000000008002d62 0x2 + .text.HAL_PCD_MspInit + 0x0000000008002d64 0x40 Src/usbd_conf.o + 0x0000000008002d64 HAL_PCD_MspInit + .text.HAL_PCD_SetupStageCallback + 0x0000000008002da4 0x14 Src/usbd_conf.o + 0x0000000008002da4 HAL_PCD_SetupStageCallback + .text.HAL_PCD_DataOutStageCallback + 0x0000000008002db8 0x1c Src/usbd_conf.o + 0x0000000008002db8 HAL_PCD_DataOutStageCallback + .text.HAL_PCD_DataInStageCallback + 0x0000000008002dd4 0x18 Src/usbd_conf.o + 0x0000000008002dd4 HAL_PCD_DataInStageCallback + .text.HAL_PCD_SOFCallback + 0x0000000008002dec 0xe Src/usbd_conf.o + 0x0000000008002dec HAL_PCD_SOFCallback + .text.HAL_PCD_ResetCallback + 0x0000000008002dfa 0x24 Src/usbd_conf.o + 0x0000000008002dfa HAL_PCD_ResetCallback + *fill* 0x0000000008002e1e 0x2 + .text.HAL_PCD_SuspendCallback + 0x0000000008002e20 0x24 Src/usbd_conf.o + 0x0000000008002e20 HAL_PCD_SuspendCallback + .text.HAL_PCD_ResumeCallback + 0x0000000008002e44 0x2c Src/usbd_conf.o + 0x0000000008002e44 HAL_PCD_ResumeCallback + .text.USBD_LL_Init + 0x0000000008002e70 0x84 Src/usbd_conf.o + 0x0000000008002e70 USBD_LL_Init + .text.USBD_LL_Start + 0x0000000008002ef4 0x12 Src/usbd_conf.o + 0x0000000008002ef4 USBD_LL_Start + .text.USBD_LL_OpenEP + 0x0000000008002f06 0x18 Src/usbd_conf.o + 0x0000000008002f06 USBD_LL_OpenEP + .text.USBD_LL_CloseEP + 0x0000000008002f1e 0x12 Src/usbd_conf.o + 0x0000000008002f1e USBD_LL_CloseEP + .text.USBD_LL_StallEP + 0x0000000008002f30 0x12 Src/usbd_conf.o + 0x0000000008002f30 USBD_LL_StallEP + .text.USBD_LL_ClearStallEP + 0x0000000008002f42 0x12 Src/usbd_conf.o + 0x0000000008002f42 USBD_LL_ClearStallEP + .text.USBD_LL_IsStallEP + 0x0000000008002f54 0x32 Src/usbd_conf.o + 0x0000000008002f54 USBD_LL_IsStallEP + .text.USBD_LL_SetUSBAddress + 0x0000000008002f86 0x12 Src/usbd_conf.o + 0x0000000008002f86 USBD_LL_SetUSBAddress + .text.USBD_LL_Transmit + 0x0000000008002f98 0x12 Src/usbd_conf.o + 0x0000000008002f98 USBD_LL_Transmit + .text.USBD_LL_PrepareReceive + 0x0000000008002faa 0x12 Src/usbd_conf.o + 0x0000000008002faa USBD_LL_PrepareReceive + .text.USBD_LL_GetRxDataSize + 0x0000000008002fbc 0xe Src/usbd_conf.o + 0x0000000008002fbc USBD_LL_GetRxDataSize + *fill* 0x0000000008002fca 0x2 + .text.USBD_static_malloc + 0x0000000008002fcc 0x8 Src/usbd_conf.o + 0x0000000008002fcc USBD_static_malloc + .text.USBD_static_free + 0x0000000008002fd4 0x2 Src/usbd_conf.o + 0x0000000008002fd4 USBD_static_free + *fill* 0x0000000008002fd6 0x2 + .text.USBD_FS_DeviceDescriptor + 0x0000000008002fd8 0xc Src/usbd_desc.o + 0x0000000008002fd8 USBD_FS_DeviceDescriptor + .text.USBD_FS_LangIDStrDescriptor + 0x0000000008002fe4 0xc Src/usbd_desc.o + 0x0000000008002fe4 USBD_FS_LangIDStrDescriptor + .text.USBD_FS_ProductStrDescriptor + 0x0000000008002ff0 0xc Src/usbd_desc.o + 0x0000000008002ff0 USBD_FS_ProductStrDescriptor + .text.USBD_FS_ManufacturerStrDescriptor + 0x0000000008002ffc 0xc Src/usbd_desc.o + 0x0000000008002ffc USBD_FS_ManufacturerStrDescriptor + .text.USBD_FS_ConfigStrDescriptor + 0x0000000008003008 0xc Src/usbd_desc.o + 0x0000000008003008 USBD_FS_ConfigStrDescriptor + .text.USBD_FS_InterfaceStrDescriptor + 0x0000000008003014 0xc Src/usbd_desc.o + 0x0000000008003014 USBD_FS_InterfaceStrDescriptor + .text.IntToUnicode + 0x0000000008003020 0x2c Src/usbd_desc.o + .text.USBD_FS_SerialStrDescriptor + 0x000000000800304c 0x44 Src/usbd_desc.o + 0x000000000800304c USBD_FS_SerialStrDescriptor + .text.Reset_Handler + 0x0000000008003090 0x80 Startup/startup_stm32f070f6px.o + 0x0000000008003090 Reset_Handler + .text.Default_Handler + 0x0000000008003110 0x2 Startup/startup_stm32f070f6px.o + 0x0000000008003110 TIM1_CC_IRQHandler + 0x0000000008003110 I2C1_IRQHandler + 0x0000000008003110 SPI1_IRQHandler + 0x0000000008003110 EXTI2_3_IRQHandler + 0x0000000008003110 ADC1_IRQHandler + 0x0000000008003110 TIM17_IRQHandler + 0x0000000008003110 RTC_IRQHandler + 0x0000000008003110 TIM3_IRQHandler + 0x0000000008003110 EXTI4_15_IRQHandler + 0x0000000008003110 RCC_IRQHandler + 0x0000000008003110 DMA1_Channel1_IRQHandler + 0x0000000008003110 Default_Handler + 0x0000000008003110 DMA1_Channel4_5_IRQHandler + 0x0000000008003110 EXTI0_1_IRQHandler + 0x0000000008003110 WWDG_IRQHandler + 0x0000000008003110 DMA1_Channel2_3_IRQHandler + 0x0000000008003110 USART2_IRQHandler + 0x0000000008003110 FLASH_IRQHandler + 0x0000000008003110 USART1_IRQHandler + 0x0000000008003110 TIM1_BRK_UP_TRG_COM_IRQHandler + *fill* 0x0000000008003112 0x2 + .text.__libc_init_array + 0x0000000008003114 0x48 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + 0x0000000008003114 __libc_init_array + *(.glue_7) + .glue_7 0x000000000800315c 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x000000000800315c 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x000000000800315c 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.init) + .init 0x000000000800315c 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x000000000800315c _init + .init 0x0000000008003160 0x8 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + *(.fini) + .fini 0x0000000008003168 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x0000000008003168 _fini + .fini 0x000000000800316c 0x8 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000008003174 . = ALIGN (0x4) + 0x0000000008003174 _etext = . + +.vfp11_veneer 0x0000000008003174 0x0 + .vfp11_veneer 0x0000000008003174 0x0 linker stubs + +.v4_bx 0x0000000008003174 0x0 + .v4_bx 0x0000000008003174 0x0 linker stubs + +.iplt 0x0000000008003174 0x0 + .iplt 0x0000000008003174 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.flash_data_array + 0x0000000008007c00 0x3f2 + 0x0000000008007c00 . = ALIGN (0x4) + .flash_data_array + 0x0000000008007c00 0x3f2 Src/main.o + 0x0000000008007c00 userdata + +.rodata 0x0000000008003174 0x1a4 + 0x0000000008003174 . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.USBD_StdDevReq + 0x0000000008003174 0x60 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .rodata.TIM16_IRQHandler.str1.4 + 0x00000000080031d4 0x2 Src/main.o + *fill* 0x00000000080031d6 0x2 + .rodata.main.str1.4 + 0x00000000080031d8 0x12 Src/main.o + *fill* 0x00000000080031ea 0x2 + .rodata.pp16_errors + 0x00000000080031ec 0x40 Src/main.o + .rodata.pp16_steps + 0x000000000800322c 0x40 Src/main.o + .rodata.pp4_errors + 0x000000000800326c 0x10 Src/main.o + .rodata.pp4_steps + 0x000000000800327c 0x10 Src/main.o + .rodata.USBD_CONFIGURATION_STRING_DATA + 0x000000000800328c 0x17 Src/usbd_desc.o + *fill* 0x00000000080032a3 0x1 + .rodata.USBD_INTERFACE_STRING_DATA + 0x00000000080032a4 0x1d Src/usbd_desc.o + *fill* 0x00000000080032c1 0x3 + .rodata.USBD_MANUFACTURER_STRING_DATA + 0x00000000080032c4 0x29 Src/usbd_desc.o + *fill* 0x00000000080032ed 0x3 + .rodata.USBD_PRODUCT_STRING_DATA + 0x00000000080032f0 0x27 Src/usbd_desc.o + 0x0000000008003318 . = ALIGN (0x4) + *fill* 0x0000000008003317 0x1 + +.rel.dyn 0x0000000008003318 0x0 + .rel.iplt 0x0000000008003318 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.ARM.extab 0x0000000008003318 0x0 + 0x0000000008003318 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000008003318 . = ALIGN (0x4) + +.ARM 0x0000000008003318 0x0 + 0x0000000008003318 . = ALIGN (0x4) + 0x0000000008003318 __exidx_start = . + *(.ARM.exidx*) + 0x0000000008003318 __exidx_end = . + 0x0000000008003318 . = ALIGN (0x4) + +.preinit_array 0x0000000008003318 0x0 + 0x0000000008003318 . = ALIGN (0x4) + 0x0000000008003318 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0000000008003318 PROVIDE (__preinit_array_end = .) + 0x0000000008003318 . = ALIGN (0x4) + +.init_array 0x0000000008003318 0x4 + 0x0000000008003318 . = ALIGN (0x4) + 0x0000000008003318 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0000000008003318 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x000000000800331c PROVIDE (__init_array_end = .) + 0x000000000800331c . = ALIGN (0x4) + +.fini_array 0x000000000800331c 0x4 + 0x000000000800331c . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x000000000800331c 0x4 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0000000008003320 . = ALIGN (0x4) + 0x0000000008003320 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0x174 load address 0x0000000008003320 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.USBD_CDC + 0x0000000020000000 0x38 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000020000000 USBD_CDC + .data.USBD_CDC_CfgFSDesc + 0x0000000020000038 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000020000038 USBD_CDC_CfgFSDesc + *fill* 0x000000002000007b 0x1 + .data.USBD_CDC_CfgHSDesc + 0x000000002000007c 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x000000002000007c USBD_CDC_CfgHSDesc + *fill* 0x00000000200000bf 0x1 + .data.USBD_CDC_DeviceQualifierDesc + 0x00000000200000c0 0xa Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x00000000200000ca 0x2 + .data.USBD_CDC_OtherSpeedCfgDesc + 0x00000000200000cc 0x43 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x00000000200000cc USBD_CDC_OtherSpeedCfgDesc + *fill* 0x000000002000010f 0x1 + .data.SystemCoreClock + 0x0000000020000110 0x4 Src/system_stm32f0xx.o + 0x0000000020000110 SystemCoreClock + .data.USBD_Interface_fops_FS + 0x0000000020000114 0x10 Src/usbd_cdc_if.o + 0x0000000020000114 USBD_Interface_fops_FS + .data.FS_Desc 0x0000000020000124 0x1c Src/usbd_desc.o + 0x0000000020000124 FS_Desc + .data.USBD_FS_DeviceDesc + 0x0000000020000140 0x12 Src/usbd_desc.o + 0x0000000020000140 USBD_FS_DeviceDesc + *fill* 0x0000000020000152 0x2 + .data.USBD_LangIDDesc + 0x0000000020000154 0x4 Src/usbd_desc.o + 0x0000000020000154 USBD_LangIDDesc + .data.USBD_StringSerial + 0x0000000020000158 0x1a Src/usbd_desc.o + 0x0000000020000158 USBD_StringSerial + 0x0000000020000174 . = ALIGN (0x4) + *fill* 0x0000000020000172 0x2 + 0x0000000020000174 _edata = . + +.igot.plt 0x0000000020000174 0x0 load address 0x0000000008003494 + .igot.plt 0x0000000020000174 0x0 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x0000000020000174 . = ALIGN (0x4) + +.bss 0x0000000020000174 0xdcc load address 0x0000000008003494 + 0x0000000020000174 _sbss = . + 0x0000000020000174 __bss_start__ = _sbss + *(.bss) + .bss 0x0000000020000174 0x1c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.bss*) + .bss.ifalt.8465 + 0x0000000020000190 0x1 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .bss.cfgidx.8468 + 0x0000000020000191 0x1 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x0000000020000192 0x2 + .bss.RX_FIFO 0x0000000020000194 0x108 Src/main.o + 0x0000000020000194 RX_FIFO + .bss.SendOperationReady + 0x000000002000029c 0x1 Src/main.o + 0x000000002000029c SendOperationReady + *fill* 0x000000002000029d 0x3 + .bss.comm_reset_flag + 0x00000000200002a0 0x4 Src/main.o + 0x00000000200002a0 comm_reset_flag + .bss.ram_frame_repeat_delay + 0x00000000200002a4 0x4 Src/main.o + 0x00000000200002a4 ram_frame_repeat_delay + .bss.remote_mode + 0x00000000200002a8 0x4 Src/main.o + 0x00000000200002a8 remote_mode + .bss.mem.8557 0x00000000200002ac 0x220 Src/usbd_conf.o + *(COMMON) + COMMON 0x00000000200004cc 0x4 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x00000000200004cc uwTick + COMMON 0x00000000200004d0 0x42c Src/main.o + 0x00000000200004d0 Protocol + 0x00000000200004d1 Symbol + 0x00000000200004d4 Repeats + 0x00000000200004d8 burst_time + 0x00000000200004dc TickCounter + 0x00000000200004e0 ByteSentCounter + 0x00000000200004e4 CurrentByte + 0x00000000200004e8 SymbolCounter + 0x00000000200004ec ErrorAcc + 0x00000000200004f0 FrameData + 0x00000000200004f4 flash_data_buffer + 0x00000000200008f4 ByteCount + 0x00000000200008f8 Burst + COMMON 0x00000000200008fc 0x224 Src/usb_device.o + 0x00000000200008fc hUsbDeviceFS + COMMON 0x0000000020000b20 0x200 Src/usbd_cdc_if.o + 0x0000000020000b20 UserRxBufferFS + 0x0000000020000c20 UserTxBufferFS + COMMON 0x0000000020000d20 0x220 Src/usbd_conf.o + 0x0000000020000d20 hpcd_USB_FS + 0x0000000020000f40 . = ALIGN (0x4) + 0x0000000020000f40 _ebss = . + 0x0000000020000f40 __bss_end__ = _ebss + +._user_heap_stack + 0x0000000020000f40 0x580 load address 0x0000000008003494 + 0x0000000020000f40 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + [!provide] PROVIDE (_end = .) + 0x00000000200010c0 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000f40 0x180 + 0x00000000200014c0 . = (. + _Min_Stack_Size) + *fill* 0x00000000200010c0 0x400 + 0x00000000200014c0 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .ARM.attributes + 0x000000000000001e 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .ARM.attributes + 0x000000000000004a 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .ARM.attributes + 0x0000000000000076 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .ARM.attributes + 0x00000000000000a2 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .ARM.attributes + 0x00000000000000ce 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .ARM.attributes + 0x00000000000000fa 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .ARM.attributes + 0x0000000000000126 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .ARM.attributes + 0x0000000000000152 0x2c Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .ARM.attributes + 0x000000000000017e 0x2c Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .ARM.attributes + 0x00000000000001aa 0x2c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .ARM.attributes + 0x00000000000001d6 0x2c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .ARM.attributes + 0x0000000000000202 0x2c Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .ARM.attributes + 0x000000000000022e 0x2c Src/gpio.o + .ARM.attributes + 0x000000000000025a 0x2c Src/main.o + .ARM.attributes + 0x0000000000000286 0x2c Src/stm32f0xx_hal_msp.o + .ARM.attributes + 0x00000000000002b2 0x2c Src/stm32f0xx_it.o + .ARM.attributes + 0x00000000000002de 0x2c Src/system_stm32f0xx.o + .ARM.attributes + 0x000000000000030a 0x2c Src/usb_device.o + .ARM.attributes + 0x0000000000000336 0x2c Src/usbd_cdc_if.o + .ARM.attributes + 0x0000000000000362 0x2c Src/usbd_conf.o + .ARM.attributes + 0x000000000000038e 0x2c Src/usbd_desc.o + .ARM.attributes + 0x00000000000003ba 0x21 Startup/startup_stm32f070f6px.o + .ARM.attributes + 0x00000000000003db 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x0000000000000407 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .ARM.attributes + 0x0000000000000425 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000443 0x1e d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(ESLBlaster02.elf elf32-littlearm) +LOAD linker stubs +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a + +.comment 0x0000000000000000 0x53 + .comment 0x0000000000000000 0x53 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x54 (size before relaxing) + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.o + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.o + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .comment 0x0000000000000053 0x54 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.o + .comment 0x0000000000000053 0x54 Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .comment 0x0000000000000053 0x54 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .comment 0x0000000000000053 0x54 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .comment 0x0000000000000053 0x54 Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .comment 0x0000000000000053 0x54 Src/gpio.o + .comment 0x0000000000000053 0x54 Src/main.o + .comment 0x0000000000000053 0x54 Src/stm32f0xx_hal_msp.o + .comment 0x0000000000000053 0x54 Src/stm32f0xx_it.o + .comment 0x0000000000000053 0x54 Src/system_stm32f0xx.o + .comment 0x0000000000000053 0x54 Src/usb_device.o + .comment 0x0000000000000053 0x54 Src/usbd_cdc_if.o + .comment 0x0000000000000053 0x54 Src/usbd_conf.o + .comment 0x0000000000000053 0x54 Src/usbd_desc.o + +.debug_frame 0x0000000000000000 0x4c + .debug_frame 0x0000000000000000 0x2c d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(lib_a-init.o) + .debug_frame 0x000000000000002c 0x20 d:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) diff --git a/hardware/esl_blaster/FW02/Release/makefile b/hardware/esl_blaster/FW02/Release/makefile new file mode 100644 index 0000000..5c0cd6b --- /dev/null +++ b/hardware/esl_blaster/FW02/Release/makefile @@ -0,0 +1,103 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Startup/subdir.mk +-include Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk +-include Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := ESLBlaster02 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +ESLBlaster02.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +ESLBlaster02.list \ + +OBJCOPY_BIN += \ +ESLBlaster02.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: ESLBlaster02.elf secondary-outputs + +# Tool invocations +ESLBlaster02.elf: $(OBJS) $(USER_OBJS) C:\Users\furrtek\Documents\Electro\ESLBlaster\FW02\STM32F070F6PX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "ESLBlaster02.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0 -T"C:\Users\furrtek\Documents\Electro\ESLBlaster\FW02\STM32F070F6PX_FLASH.ld" --specs=nosys.specs -Wl,-Map="ESLBlaster02.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +ESLBlaster02.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "ESLBlaster02.list" + @echo 'Finished building: $@' + @echo ' ' + +ESLBlaster02.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "ESLBlaster02.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/hardware/esl_blaster/FW02/Release/program.bat b/hardware/esl_blaster/FW02/Release/program.bat new file mode 100644 index 0000000..ea5daf3 --- /dev/null +++ b/hardware/esl_blaster/FW02/Release/program.bat @@ -0,0 +1 @@ +..\dfu-util-0.9-win64\dfu-util --device 0483:df11 -a 0 -s 0x08000000:leave --download ESLBlaster02.bin \ No newline at end of file diff --git a/hardware/esl_blaster/FW02/STM32F070F6PX_FLASH.ld b/hardware/esl_blaster/FW02/STM32F070F6PX_FLASH.ld new file mode 100644 index 0000000..261dccb --- /dev/null +++ b/hardware/esl_blaster/FW02/STM32F070F6PX_FLASH.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32F070F6Px Device from STM32F0 series +** 32Kbytes FLASH +** 6Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x200017ff; /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x180; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K + FLASH_USER (rw) : ORIGIN = 0x8007C00, LENGTH = 1K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 6K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + .flash_data_array (NOLOAD) : + { + . = ALIGN(4); + } >FLASH_USER + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hardware/esl_blaster/FW02/Src/gpio.c b/hardware/esl_blaster/FW02/Src/gpio.c new file mode 100644 index 0000000..5c5214d --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/gpio.c @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * File Name : gpio.c + * Description : This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#include "gpio.h" + +void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct; + + // GPIO Ports Clock Enable, GPIOB isn't used + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); + + // Configure PA4 as input + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // Red LED off + //HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); + + // Configure PA6 as push-pull output + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Alternate = GPIO_AF1_IR; // TIM3_CH1 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // IR LEDs off + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_SET); + + // Configure PA7 as analog input + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +} diff --git a/hardware/esl_blaster/FW02/Src/main.c b/hardware/esl_blaster/FW02/Src/main.c new file mode 100644 index 0000000..2158bc0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/main.c @@ -0,0 +1,523 @@ +// ESL Blaster firmware v2.00 +// For board rev. B +// 2022 furrtek +// DO NOT COMPILE WITH -O3 ! Only -O1, or USB won't work anymore + +// Bloated stuff: +// HAL_GPIO_Init 0x1b4 +// HAL_PCD_Init 0x240 +// HAL_PCD_EP_Open 0x35c +// HAL_PCD_IRQHandler 0x5cc +// USBD_StdDevReq 0x338 + +// States: +// STATE_IDLE +// STATE_GET_FRAME_SIZE +// STATE_GET_FRAME_REPEAT_DELAY +// STATE_GET_FRAME_REPEATS_LOW +// STATE_GET_FRAME_REPEATS_HIGH +// STATE_GET_FRAME_DATA (n) +// STATE_IDLE + +// Ack after T command when frame is transmitted + +// STATE_IDLE +// STATE_FLASH_LOAD (1024 bytes, ack every 128 bytes) +// Ack or Nack depending on flash programming success +// STATE_IDLE + +#include "main.h" +#include "usb_device.h" +#include "gpio.h" + +void SystemClock_Config(void); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +volatile FIFO RX_FIFO = {.head=0, .tail=0}; + +volatile uint32_t ByteSentCounter, ByteCount; +volatile uint32_t SymbolCounter; +volatile uint32_t TickCounter, Burst, Repeats, ErrorAcc, burst_time; +volatile uint8_t SendOperationReady = 0, CurrentByte, Symbol, Protocol; +volatile const uint8_t * FrameData; +volatile uint32_t comm_reset_flag = 0, ram_frame_repeat_delay = 0; +volatile uint32_t remote_mode = 0; + +typedef struct { + uint16_t flags; // protocol + uint16_t repeats; + uint16_t delay; + uint16_t frame_size; + uint8_t frame_data[64]; +} entry_t; + +typedef struct { + uint16_t entry_count; // 0~13 + entry_t entries[14]; +} userdata_t; + +#define RED_LED_OFF TIM3->CCR1 = 0x0000; +#define RED_LED_NORMAL TIM3->CCR1 = (GPIOA->IDR & GPIO_IDR_4) ? 0x0000 : 0x0100; // Off/Charge +#define RED_LED_MAX TIM3->CCR1 = 0x4000; // IR transmit + +#define CDC_NOK CDC_Transmit_FS((uint8_t*)"N", 1); +#define CDC_OK CDC_Transmit_FS((uint8_t*)"K", 1); + +/* +static const uint8_t frame_button1[11] = { + 0x84, 0x00, 0x00, 0x00, 0x00, 0xAB, 0x09, 0x00, 0x00, 0xF2, 0xA7 +}; + +static const uint8_t frame_dmchange1[11] = { + 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x09, 0x00, 0x00, 0xBD, 0xC3 +}; + +static const uint8_t frame_dmchange2[11] = { + 0x85, 0x00, 0x00, 0x00, 0x00, 0x06, 0x11, 0x00, 0x00, 0xEA, 0x80 +};*/ + +// PP4 symbol times in TIM16@10us steps +// t=1/32768: 30.52us +// 00: 61us (2t=61.03) (TIM16 6 *10=60 Err=-1.03) +// 01: 244us (8t=244.14) (TIM16 24 *10=240 Err=-4.14) +// 10: 122us (4t=122.07) (TIM16 12 *10=120 Err=-2.07) +// 11: 183us (6t=183.10) (TIM16 18 *10=180 Err=-3.10) +// Burst: 40us (TIM16 4 *10=40 Err=0) +static const uint32_t pp4_steps[4] = { + 6-1, 24-1, 12-1, 18-1 +}; +static const uint32_t pp4_errors[4] = { + 103, 414, 207, 310 // All *100 +}; + +// PP16 symbol times in TIM16@4us steps +// 0000: 27us (TIM16 7 *4=28 Err=1) +// 0001: 51us (TIM16 13*4=52 Err=1) +// 0010: 35us (TIM16 9 *4=36 Err=1) +// 0011: 43us (TIM16 11*4=44 Err=1) +// 0100: 147us (TIM16 37*4=148 Err=1) +// 0101: 123us (TIM16 31*4=124 Err=1) +// 0110: 139us (TIM16 35*4=140 Err=1) +// 0111: 131us (TIM16 33*4=132 Err=1) +// 0100: 83us (TIM16 21*4=84 Err=1) +// 0101: 59us (TIM16 15*4=60 Err=1) +// 0110: 75us (TIM16 19*4=76 Err=1) +// 0111: 67us (TIM16 17*4=68 Err=1) +// 0100: 91us (TIM16 23*4=92 Err=1) +// 0101: 115us (TIM16 29*4=116 Err=1) +// 0110: 99us (TIM16 25*4=100 Err=1) +// 0111: 107us (TIM16 27*4=108 Err=1) +// Burst: 21us (TIM16 5 *4=20 Err=-1) +static const uint32_t pp16_steps[16] = { + 7-1, 13-1, 9-1, 11-1, 37-1, 31-1, 35-1, 33-1, 21-1, 15-1, 19-1, 17-1, 23-1, 29-1, 25-1, 27-1 +}; +static const uint32_t pp16_errors[16] = { + 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 // All *100 +}; + +#define PP4_ARR 484 - 1 // 10.08us +#define PP4_BURST 4 - 1 +#define PP16_ARR 192 - 1 // 4us +#define PP16_BURST 3 - 1 + +void TIM16_IRQHandler(void) { + if (SendOperationReady) { + if (!TickCounter) { + if (Burst == 0) { + // Start burst ASAP + TIM16->CCMR1 |= TIM_CCMR1_OC1M_0; // Force active level + TickCounter = burst_time; + + if (Protocol) { + // PP16 + if (!(SymbolCounter & 1)) + CurrentByte = FrameData[ByteSentCounter++]; // Load byte + + // Load symbol + Symbol = CurrentByte & 15; + CurrentByte >>= 4; + SymbolCounter++; + } else { + // PP4 + if (!(SymbolCounter & 3)) + CurrentByte = FrameData[ByteSentCounter++]; // Load byte + + // Load symbol + Symbol = CurrentByte & 3; + CurrentByte >>= 2; + SymbolCounter++; + } + + Burst = 1; + } else { + // Stop burst ASAP + TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // Force inactive level + + Burst = 0; + + TickCounter = Protocol ? pp16_steps[Symbol] : pp4_steps[Symbol]; + // Auto-adjust symbol time depending on timing error accumulation + if (ErrorAcc >= (Protocol ? 400 : 1000)) { + TickCounter++; + ErrorAcc -= 1000; + } + ErrorAcc += Protocol ? pp16_errors[Symbol] : pp4_errors[Symbol]; + + if (ByteSentCounter > ByteCount) { + if (Repeats) { + Repeats--; + ByteSentCounter = 0; + SymbolCounter = 0; + ErrorAcc = 0; + TickCounter = ram_frame_repeat_delay * (Protocol ? 125 : 50); //2000; + } else { + IRStop(); + if (!remote_mode) CDC_OK + } + } + } + } else + TickCounter--; + } + + // Clear TIM_ENV update interrupt + TIM16->SR &= (uint16_t)(~TIM_SR_UIF); +} + +void TIM14_IRQHandler(void) { + comm_reset_flag = 1; + + // Clear TIM_ENV update interrupt + TIM14->SR &= (uint16_t)(~TIM_SR_UIF); +} + +// Check MCP73831 STAT output +// Low: Charging +// High: Charge done +// Hi-z: No battery + +void IRStop() { + TIM16->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0); // Force inactive level + TIM16->CR1 &= ~TIM_CR1_CEN; // Disable timer + SendOperationReady = 0; + RED_LED_NORMAL +} + +void IRTX(const uint8_t * data, const uint32_t pp16, const uint32_t length, const uint32_t rpt) { + FrameData = data; + ByteSentCounter = 0; + ByteCount = length; + TickCounter = 0; + Burst = 0; + SymbolCounter = 0; + Repeats = rpt; + ErrorAcc = 0; + SendOperationReady = 1; + Protocol = pp16; + + TIM16->CR1 &= ~TIM_CR1_CEN; // Disable timer + TIM16->CNT = 0; // Reset timer's counter + if (pp16) { + TIM16->ARR = PP16_ARR; + burst_time = PP16_BURST; + } else { + TIM16->ARR = PP4_ARR; + burst_time = PP4_BURST; + } + + RED_LED_MAX + + TIM16->DIER |= TIM_DIER_UIE; // Enable TIM16 update interrupt + TIM16->CR1 |= TIM_CR1_CEN; // Enable TIM16 +} + +uint32_t adc_read() { + ADC1->CR = ADC_CR_ADEN; + while (!(ADC1->ISR & ADC_ISR_ADRDY)); // Wait for ADRDY + ADC1->CR |= ADC_CR_ADSTART; + while (!(ADC1->ISR & ADC_ISR_EOC)); // Wait for EOC flag + return ADC1->DR; +} + +userdata_t userdata __attribute__((section(".flash_data_array"))); + +uint8_t flash_data_buffer[1024]; + +int main(void) { + enum comm_states { + STATE_IDLE, + STATE_GET_FRAME_SIZE, + STATE_GET_FRAME_REPEAT_DELAY, + STATE_GET_FRAME_REPEATS_LOW, + STATE_GET_FRAME_REPEATS_HIGH, + STATE_GET_FRAME_DATA, + STATE_FLASH_LOAD + }; + + enum comm_states comm_state = STATE_IDLE; + uint8_t ram_frame_data[256]; + uint32_t ram_frame_pp16 = 0, ram_frame_size = 0, ram_frame_repeats = 0, ram_frame_data_counter = 0; + uint32_t flash_data_counter = 0; + + static_assert (sizeof(userdata) == 1010, "userdata should be exactly 1010 bytes"); + + // Reset all peripherals, initializes the Flash interface and the Systick + HAL_Init(); + + // Configure the system clock + SystemClock_Config(); + + // Initialize all configured peripherals + MX_GPIO_Init(); + MX_USB_DEVICE_Init(); + + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_ADC1); + + // TIM17: Carrier, TIM16: Envelope + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM16); // These can be ORed + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM17); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + + GPIO_InitTypeDef GPIO_InitStruct; + // Configure PA13 as push-pull output for IR_OUT + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Alternate = GPIO_AF1_IR; // IR_OUT + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + // TIM17: Carrier + TIM17->PSC = 0; + TIM17->ARR = 38 - 1; // 48M / 1.25M = 38.4, 38: 1.26MHz + TIM17->CCR1 = (uint16_t)(37 / 2); // 50% duty cycle + TIM17->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; // PWM mode 1 + TIM17->CCER |= TIM_CCER_CC1E; // CC1 output enable + TIM17->BDTR |= TIM_BDTR_MOE; + + // TIM16: Symbol timing + TIM16->PSC = 0; + TIM16->CCMR1 |= TIM_CCMR1_OC1M_2; // Keep OC1M bit 2 high: Force level defined by OC1M bit 0 + TIM16->CCER |= TIM_CCER_CC1E; // CC1 output enable + TIM16->BDTR |= TIM_BDTR_MOE; + TIM16->DIER |= TIM_DIER_UIE; // Update interrupt enable + + TIM17->CR1 |= TIM_CR1_CEN; // Enable timer + TIM17->EGR |= TIM_EGR_UG; + + NVIC_EnableIRQ(TIM16_IRQn); + NVIC_SetPriority(TIM16_IRQn, 0); + + // TIM14: Comm timeout + TIM14->PSC = (uint16_t)(100); // 48M/100/65535 = ~7.32Hz (137ms) + TIM14->ARR = (uint16_t)(0xFFFF); + TIM14->CCMR1 = 0; + TIM14->CCER = 0; + TIM14->DIER |= TIM_DIER_UIE; // Update interrupt enable + TIM14->CR1 |= TIM_CR1_CEN; // Enable timer + TIM14->EGR |= TIM_EGR_UG; + + NVIC_EnableIRQ(TIM14_IRQn); + NVIC_SetPriority(TIM14_IRQn, 1); + + // TIM3: Red LED PWM + TIM3->ARR = (uint16_t)(0xFFFF); + TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; // PWM mode 2 + TIM3->CCER = TIM_CCER_CC1E; + TIM3->CCR1 = 0x1000; + TIM3->CR1 |= TIM_CR1_CEN; // Enable timer + TIM3->EGR |= TIM_EGR_UG; + + ADC1->CFGR1 = 0; + ADC1->SMPR = ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0; + ADC1->CHSELR = ADC_CHSELR_CHSEL5; + + // ADC step = 3.3/(2^12-1) = ~806uV + // USB: 5V + // Batt full charge: 4.2V + // 5/2 = 2.5V -> v = ~3102 + // 4.2/2 = 2.1V -> v = ~2605 + + // Powered by less than 4.35V: running from battery so remote mode + if (adc_read() < 2700) { + uint32_t remote_frame_count = userdata.entry_count; + uint32_t remote_frame_index = 0; + + remote_mode = 1; + + for (;;) { + //HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_6); // Battery mode + /*RED_LED_MAX + for (uint32_t c = 0; c < 1000000; c++) {}; + RED_LED_OFF + for (uint32_t c = 0; c < 1000000; c++) {};*/ + + /*if (userdata.entries[1].frame_data[0] == 0x85) { + for (;;) { RED_LED_OFF }; + }*/ + + ram_frame_size = userdata.entries[remote_frame_index].frame_size; + ram_frame_repeats = userdata.entries[remote_frame_index].repeats; + ram_frame_repeat_delay = userdata.entries[remote_frame_index].delay; + ram_frame_pp16 = userdata.entries[remote_frame_index].flags & 1; + for (uint32_t c = 0; c < ram_frame_size; c++) + ram_frame_data[c] = userdata.entries[remote_frame_index].frame_data[c]; + + IRTX(ram_frame_data, ram_frame_pp16, ram_frame_size, ram_frame_repeats); + + while (SendOperationReady) {}; + + remote_frame_index++; + if (remote_frame_index >= remote_frame_count) remote_frame_index = 0; + } + } + + // Main loop + while (1) { + + if (comm_reset_flag) { + comm_reset_flag = 0; + comm_state = STATE_IDLE; + if (!SendOperationReady) RED_LED_NORMAL // Update LED + } + + while (RX_FIFO.head != RX_FIFO.tail) { + TIM14->CNT = (uint16_t)0; // Reset comm. timeout + + // Process one byte from the RX FIFO + uint8_t byte = RX_FIFO.data[RX_FIFO.tail]; + + if (comm_state == STATE_IDLE) { + if (byte == 'L') { + // Load new frame data + comm_state = STATE_GET_FRAME_SIZE; + } else if (byte == 'T') { + // Transmit loaded frame + IRTX(ram_frame_data, ram_frame_pp16, ram_frame_size, ram_frame_repeats); + } else if (byte == '?') { + // Reply ID + CDC_Transmit_FS((uint8_t*)"ESLBlasterB1", 12); + } else if (byte == 'W') { + flash_data_counter = 0; + comm_state = STATE_FLASH_LOAD; + } else if (byte == 'R') { + // Read flash + uint16_t buff; + uint16_t* ptr = (uint16_t*)0x8007C00; + for (uint32_t d = 0; d < (1024/4); d++) { + buff = *ptr; + while(CDC_Transmit_FS((uint8_t*)&buff, 2) != USBD_OK) {}; + ptr += 2; + } + } else if (byte == 'S') { + // E-Stop + IRStop(); + } + } else if (comm_state == STATE_GET_FRAME_SIZE) { + ram_frame_size = byte; + comm_state = STATE_GET_FRAME_REPEAT_DELAY; + } else if (comm_state == STATE_GET_FRAME_REPEAT_DELAY) { + ram_frame_repeat_delay = byte; + comm_state = STATE_GET_FRAME_REPEATS_LOW; + } else if (comm_state == STATE_GET_FRAME_REPEATS_LOW) { + ram_frame_repeats = byte; + comm_state = STATE_GET_FRAME_REPEATS_HIGH; + } else if (comm_state == STATE_GET_FRAME_REPEATS_HIGH) { + ram_frame_repeats |= (((uint32_t)byte & 0x7F) << 8); + ram_frame_pp16 = (byte & 0x80) ? 1 : 0; + ram_frame_data_counter = 0; + comm_state = STATE_GET_FRAME_DATA; + } else if (comm_state == STATE_GET_FRAME_DATA) { + ram_frame_data[ram_frame_data_counter++] = byte; + if (ram_frame_data_counter == ram_frame_size) + comm_state = STATE_IDLE; + } else if (comm_state == STATE_FLASH_LOAD) { + flash_data_buffer[flash_data_counter++] = byte; + + if (!(flash_data_counter & 0x7F)) + CDC_OK // Ack every 128 bytes + + if (flash_data_counter == 1024) { + // Write flash + // Unlock + while ((FLASH->SR & FLASH_SR_BSY) != 0) {} + if (FLASH->CR & FLASH_CR_LOCK) { + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } + // Main flash: 0x0800 0000 - 0x0800 7FFF + // 32 pages de 1kB + // Page #31: data + + // Erase + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = (uint32_t)0x8007C00; + FLASH->CR |= FLASH_CR_STRT; + while ((FLASH->SR & FLASH_SR_BSY) != 0) {} + if (FLASH->SR & FLASH_SR_EOP) + FLASH->SR = FLASH_SR_EOP; + else + CDC_NOK + FLASH->CR &= ~FLASH_CR_PER; + + // Program halfword + FLASH->CR |= FLASH_CR_PG; + __IO uint16_t* ptr = (uint16_t*)0x8007C00; + uint16_t* src = (uint16_t*)flash_data_buffer; + for (uint32_t d = 0; d < 1024; d += 2) { + *ptr++ = *src++; + } + while (FLASH->SR & FLASH_SR_BSY) {} + if (FLASH->SR & FLASH_SR_EOP) + FLASH->SR = FLASH_SR_EOP; + else + CDC_NOK + FLASH->CR &= ~FLASH_CR_PG; + + CDC_OK + RED_LED_MAX + + comm_state = STATE_IDLE; + } + } + + RX_FIFO.tail = FIFO_INCR(RX_FIFO.tail); + } + } +} + +void SystemClock_Config(void) { + LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); // 1ws + + if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1) + Error_Handler(); + + LL_RCC_HSE_Enable(); + + // Wait for HSE ready + while (LL_RCC_HSE_IsReady() != 1) {}; + + // 4 * 12 = 48MHz + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1); + LL_RCC_PLL_Enable(); + + // Wait for PLL ready + while (LL_RCC_PLL_IsReady() != 1) {}; + + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + // Wait for System clock ready + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}; + + LL_Init1msTick(48000000); + LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK); + LL_SetSystemCoreClock(48000000); + LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL); +} + +void Error_Handler(void) { + /* User can add his own implementation to report the HAL error return state */ +} diff --git a/hardware/esl_blaster/FW02/Src/stm32f0xx_hal_msp.c b/hardware/esl_blaster/FW02/Src/stm32f0xx_hal_msp.c new file mode 100644 index 0000000..f9ff1de --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/stm32f0xx_hal_msp.c @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + __HAL_REMAP_PIN_ENABLE(HAL_REMAP_PA11_PA12); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Src/stm32f0xx_it.c b/hardware/esl_blaster/FW02/Src/stm32f0xx_it.c new file mode 100644 index 0000000..2d5562c --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/stm32f0xx_it.c @@ -0,0 +1,159 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern PCD_HandleTypeDef hpcd_USB_FS; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB global Interrupt / USB wake-up interrupt through EXTI line 18. + */ +void USB_IRQHandler(void) +{ + /* USER CODE BEGIN USB_IRQn 0 */ + + /* USER CODE END USB_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_FS); + /* USER CODE BEGIN USB_IRQn 1 */ + + /* USER CODE END USB_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Src/system_stm32f0xx.c b/hardware/esl_blaster/FW02/Src/system_stm32f0xx.c new file mode 100644 index 0000000..410809c --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/system_stm32f0xx.c @@ -0,0 +1,333 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F0xx device + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001U; + +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80CU; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80CU; +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFFU; + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; + +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080U; +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFEU; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000U; + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/Src/usb_device.c b/hardware/esl_blaster/FW02/Src/usb_device.c new file mode 100644 index 0000000..a787ae8 --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/usb_device.c @@ -0,0 +1,101 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.c + * @version : v2.0_Cube + * @brief : This file implements the USB Device + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_device.h" +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_cdc.h" +#include "usbd_cdc_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USB Device Core handle declaration. */ +USBD_HandleTypeDef hUsbDeviceFS; + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ +void MX_USB_DEVICE_Init(void) +{ + /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + + /* USER CODE END USB_DEVICE_Init_PreTreatment */ + + /* Init Device Library, add supported class and start the library. */ + if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) + { + Error_Handler(); + } + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) + { + Error_Handler(); + } + if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) + { + Error_Handler(); + } + if (USBD_Start(&hUsbDeviceFS) != USBD_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + + /* USER CODE END USB_DEVICE_Init_PostTreatment */ +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Src/usbd_cdc_if.c b/hardware/esl_blaster/FW02/Src/usbd_cdc_if.c new file mode 100644 index 0000000..23e5ac9 --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/usbd_cdc_if.c @@ -0,0 +1,184 @@ +/** + ****************************************************************************** + * @file : usbd_cdc_if.c + * @version : v2.0_Cube + * @brief : Usb device for Virtual Com Port. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +#include "usbd_cdc_if.h" + +/* Define size for the receive and transmit buffer over CDC */ +/* It's up to user to redefine and/or remove those define */ +#define APP_RX_DATA_SIZE 256 +#define APP_TX_DATA_SIZE 256 + +/* Create buffer for reception and transmission */ +/* It's up to user to redefine and/or remove those define */ +/** Received data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; + +/** Data to send over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; + +extern USBD_HandleTypeDef hUsbDeviceFS; + +static int8_t CDC_Init_FS(void); +static int8_t CDC_DeInit_FS(void); +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = { + CDC_Init_FS, + CDC_DeInit_FS, + CDC_Control_FS, + CDC_Receive_FS +}; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) { + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + return (USBD_OK); +} + +/** + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) { + return (USBD_OK); +} + +/** + * @brief Manage the CDC class requests + * @param cmd: Command code + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { + // Since this is not an actual COM port, absolutely no fucks are given about control requests + switch(cmd) { + case CDC_SEND_ENCAPSULATED_COMMAND: + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + break; + + case CDC_SET_COMM_FEATURE: + break; + + case CDC_GET_COMM_FEATURE: + break; + + case CDC_CLEAR_COMM_FEATURE: + break; + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + case CDC_SET_LINE_CODING: + break; + + case CDC_GET_LINE_CODING: + break; + + case CDC_SET_CONTROL_LINE_STATE: + break; + + case CDC_SEND_BREAK: + break; + + default: + break; + } + + return (USBD_OK); +} + +/** + * @brief Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * untill exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { + uint32_t len = *Len; + + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + + // Add data to FIFO + while (len--) { + if (FIFO_INCR(RX_FIFO.head) == RX_FIFO.tail) { + return USBD_FAIL; // Overrun + } else { + RX_FIFO.data[RX_FIFO.head] = *Buf++; + RX_FIFO.head = FIFO_INCR(RX_FIFO.head); + } + } + + return (USBD_OK); +} + +/** + * @brief CDC_Transmit_FS + * Data to send over USB IN endpoint are sent over CDC interface + * through this function. + * @note + * + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { + uint8_t result = USBD_OK; + + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + if (hcdc->TxState != 0) + return USBD_BUSY; + + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + + return result; +} diff --git a/hardware/esl_blaster/FW02/Src/usbd_conf.c b/hardware/esl_blaster/FW02/Src/usbd_conf.c new file mode 100644 index 0000000..0f66dd0 --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/usbd_conf.c @@ -0,0 +1,650 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.c + * @version : v2.0_Cube + * @brief : This file implements the board support package for the USB device library + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#include "stm32f0xx_hal.h" +#include "usbd_def.h" +#include "usbd_core.h" +#include "usbd_cdc.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +PCD_HandleTypeDef hpcd_USB_FS; +void Error_Handler(void); + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* Private functions ---------------------------------------------------------*/ +static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status); +/* USER CODE BEGIN 1 */ +static void SystemClockConfig_Resume(void); +/* USER CODE END 1 */ +extern void SystemClock_Config(void); + +/******************************************************************************* + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB) + { + /* USER CODE BEGIN USB_MspInit 0 */ + + /* USER CODE END USB_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(USB_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_IRQn); + /* USER CODE BEGIN USB_MspInit 1 */ + + /* USER CODE END USB_MspInit 1 */ + } +} + +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB) + { + /* USER CODE BEGIN USB_MspDeInit 0 */ + + /* USER CODE END USB_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_CLK_DISABLE(); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(USB_IRQn); + + /* USER CODE BEGIN USB_MspDeInit 1 */ + + /* USER CODE END USB_MspDeInit 1 */ + } +} + +/** + * @brief Setup stage callback + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); +} + +/** + * @brief Data Out stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); +} + +/** + * @brief Data In stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); +} + +/** + * @brief SOF callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + if ( hpcd->Init.speed != PCD_SPEED_FULL) + { + Error_Handler(); + } + /* Set Speed. */ + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + + /* Reset Device. */ + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Suspend callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* Inform USB library that core enters in suspend Mode. */ + USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + /* Enter in STOP mode. */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + /* USER CODE END 2 */ +} + +/** + * @brief Resume callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* USER CODE BEGIN 3 */ + if (hpcd->Init.low_power_enable) + { + /* Reset SLEEPDEEP bit of Cortex System Control Register. */ + SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + SystemClockConfig_Resume(); + } + /* USER CODE END 3 */ + USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief ISOOUTIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief ISOINIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief Connect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Disconnect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/******************************************************************************* + LL Driver Interface (USB Device Library --> PCD) +*******************************************************************************/ + +/** + * @brief Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + /* Init USB Ip. */ + /* Link the driver to the stack. */ + hpcd_USB_FS.pData = pdev; + pdev->pData = &hpcd_USB_FS; + + hpcd_USB_FS.Instance = USB; + hpcd_USB_FS.Init.dev_endpoints = 8; + hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_FS.Init.low_power_enable = DISABLE; + hpcd_USB_FS.Init.lpm_enable = DISABLE; + hpcd_USB_FS.Init.battery_charging_enable = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) + { + Error_Handler( ); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + /* Register USB PCD CallBacks */ + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback); + + HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback); + HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); + HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); + HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /* USER CODE BEGIN EndPoint_Configuration */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); + /* USER CODE END EndPoint_Configuration */ + /* USER CODE BEGIN EndPoint_Configuration_CDC */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); + /* USER CODE END EndPoint_Configuration_CDC */ + return USBD_OK; +} + +/** + * @brief De-Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_DeInit(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Starts the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Start(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Stops the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Stop(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Opens an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Closes an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + + if((ep_addr & 0x80) == 0x80) + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + } +} + +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param dev_addr: Device address + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns the last transfered packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); +} + +/** + * @brief Delays routine for the USB device library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/** + * @brief Static single allocation. + * @param size: Size of allocated memory + * @retval None + */ +void *USBD_static_malloc(uint32_t size) +{ + static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + return mem; +} + +/** + * @brief Dummy memory free + * @param p: Pointer to allocated memory address + * @retval None + */ +void USBD_static_free(void *p) +{ + +} + +/* USER CODE BEGIN 5 */ +/** + * @brief Configures system clock after wake-up from USB Resume CallBack: + * enable HSI, PLL and select PLL as system clock source. + * @retval None + */ +static void SystemClockConfig_Resume(void) +{ + SystemClock_Config(); +} +/* USER CODE END 5 */ + +/** + * @brief Retuns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + USBD_StatusTypeDef usb_status = USBD_OK; + + switch (hal_status) + { + case HAL_OK : + usb_status = USBD_OK; + break; + case HAL_ERROR : + usb_status = USBD_FAIL; + break; + case HAL_BUSY : + usb_status = USBD_BUSY; + break; + case HAL_TIMEOUT : + usb_status = USBD_FAIL; + break; + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hardware/esl_blaster/FW02/Src/usbd_desc.c b/hardware/esl_blaster/FW02/Src/usbd_desc.c new file mode 100644 index 0000000..10267e2 --- /dev/null +++ b/hardware/esl_blaster/FW02/Src/usbd_desc.c @@ -0,0 +1,268 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v2.0_Cube + * @brief : This file implements the USB device descriptors. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_conf.h" + +#define USBD_VID 1155 +#define USBD_PID_FS 22336 +#define USBD_LANGID_STRING 1033 + +//#define USBD_MANUFACTURER_STRING "Furrtek engineering" +// USB uses UTF-16LE +// unicode[idx++] = *len; +// unicode[idx++] = USB_DESC_TYPE_STRING; +static const uint8_t USBD_MANUFACTURER_STRING_DATA[] = { + "\x28\x03" "F\0u\0r\0r\0t\0e\0k\0 \0e\0n\0g\0i\0n\0e\0e\0r\0i\0n\0g\0" +}; + +//#define USBD_PRODUCT_STRING_FS "ESL Blaster Rev. B" +static const uint8_t USBD_PRODUCT_STRING_DATA[] = { + "\x26\x03" "E\0S\0L\0 \0B\0l\0a\0s\0t\0e\0r\0 \0R\0e\0v\0.\0 \0B\0" +}; + +//#define USBD_CONFIGURATION_STRING_F "CDC Config" +static const uint8_t USBD_CONFIGURATION_STRING_DATA[] = { + "\x16\x03" "C\0D\0C\0 \0C\0o\0n\0f\0i\0g\0" +}; + +//#define USBD_INTERFACE_STRING_FS "CDC Interface" +static const uint8_t USBD_INTERFACE_STRING_DATA[] = { + "\x1C\x03" "C\0D\0C\0 \0I\0n\0t\0e\0r\0f\0a\0c\0e\0" +}; + +static void Get_SerialNum(void); +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); + +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + +#ifdef USBD_SUPPORT_USER_STRING_DESC +uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +USBD_DescriptorsTypeDef FS_Desc = { + USBD_FS_DeviceDescriptor, + USBD_FS_LangIDStrDescriptor, + USBD_FS_ManufacturerStrDescriptor, + USBD_FS_ProductStrDescriptor, + USBD_FS_SerialStrDescriptor, + USBD_FS_ConfigStrDescriptor, + USBD_FS_InterfaceStrDescriptor +}; + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/** USB standard device descriptor. */ +__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { + 0x12, /*bLength */ + USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ + 0x00, /*bcdUSB */ + 0x02, + 0x02, /*bDeviceClass*/ + 0x02, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID_FS), /*idProduct*/ + HIBYTE(USBD_PID_FS), /*idProduct*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ +}; + +/** USB lang indentifier descriptor. */ +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING) +}; + +/* +// Internal string descriptor. +__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; +*/ + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { + USB_SIZ_STRING_SERIAL, + USB_DESC_TYPE_STRING, +}; + +/** + * @brief Return the device descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = sizeof(USBD_FS_DeviceDesc); + return USBD_FS_DeviceDesc; +} + +/** + * @brief Return the LangID string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = sizeof(USBD_LangIDDesc); + return USBD_LangIDDesc; +} + +/** + * @brief Return the product string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == 0) + // USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_PRODUCT_STRING_DATA); //38 + return (uint8_t*)USBD_PRODUCT_STRING_DATA; +} + +/** + * @brief Return the manufacturer string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_MANUFACTURER_STRING_DATA); //40 + return (uint8_t*)USBD_MANUFACTURER_STRING_DATA; +} + +/** + * @brief Return the serial number string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + *length = USB_SIZ_STRING_SERIAL; + + Get_SerialNum(); + + return (uint8_t *) USBD_StringSerial; +} + +/** + * @brief Return the configuration string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == USBD_SPEED_HIGH) + // USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_CONFIGURATION_STRING_DATA); //22 + return (uint8_t*)USBD_CONFIGURATION_STRING_DATA; +} + +/** + * @brief Return the interface string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + //if (speed == 0) + // USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + //else + //USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + //return USBD_StrDesc; + + *length = sizeof(USBD_INTERFACE_STRING_DATA); //28 + return (uint8_t*)USBD_INTERFACE_STRING_DATA; +} + +/** + * @brief Create the serial number string descriptor + * @param None + * @retval None + */ +static void Get_SerialNum(void) { + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t *) DEVICE_ID1; + deviceserial1 = *(uint32_t *) DEVICE_ID2; + deviceserial2 = *(uint32_t *) DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) { + IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); + IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + } +} + +/** + * @brief Convert Hex 32Bits value into char + * @param value: value to convert + * @param pbuf: pointer to the buffer + * @param len: buffer length + * @retval None + */ +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { + uint32_t idx = 0, temp; + + for (idx = 0; idx < (len << 1); idx += 2) { + temp = value >> 28; + + if (temp < 10) + pbuf[idx] = temp + '0'; + else + pbuf[idx] = temp + 'A' - 10; + + pbuf[idx + 1] = 0; + + value = value << 4; + } +} diff --git a/hardware/esl_blaster/FW02/Startup/startup_stm32f070f6px.s b/hardware/esl_blaster/FW02/Startup/startup_stm32f070f6px.s new file mode 100644 index 0000000..d1c1326 --- /dev/null +++ b/hardware/esl_blaster/FW02/Startup/startup_stm32f070f6px.s @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file startup_stm32f070x6.s + * @author MCD Application Team + * @brief STM32F070x4/STM32F070x6 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* Reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hardware/esl_blaster/FW02/dfu-util-0.9-win64/README.txt b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/README.txt new file mode 100644 index 0000000..5aa2e67 --- /dev/null +++ b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/README.txt @@ -0,0 +1,26 @@ +dfu-util 0.9 + +These binaries are for Microsoft Windows 64-bit + +They were built using MinGW-64 from MSYS2 with gcc 5.3.0, +for build instructions please see: +http://dfu-util.sourceforge.net/build.html + +Source code: +https://sourceforge.net/p/dfu-util/dfu-util/ci/v0.9/tree/ + +dfu-util.exe requires libusb-1.0.dll. The shipped libusb-1.0.dll +is built from libusb 1.0.20 and can be replaced with another +version if desired. + +dfu-util-static.exe has the libusb 1.0.20 code embedded and runs +without any libusb-1.0.dll. + +Notes: +1. To work around a bug in gcc/mingw, a small patch was applied, see + https://sourceforge.net/p/dfu-util/tickets/13/ +2. The dfu-util-static.exe includes libusb that has been patched + to work around a silicon bug in STM32F42X devices: + https://github.com/axoloti/axoloti/blob/master/platform_osx/src/libusb.stdfu.patch + +2016-02-11 Tormod Volden diff --git a/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-prefix.exe b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-prefix.exe new file mode 100644 index 0000000000000000000000000000000000000000..5ae088804979feab4339592abc9c90e694d2b516 GIT binary patch literal 178765 zcmeEv30Pc3wtro?-85UeV*rT;Z6hS0fdBylS(FY9X_6)oAe%;^X&QoIOD|b8DzQP+ zwkWQn<1%sA(Q)FERgI9ukf@`GTioM1jp!Jc$;9Xk|KF)w7djZ7_ulv3_r3T1?eDwy z)H!wP)TyddrKE{$yzW(w zL~Ngl8>vWTM>&Fj)vT;Kt=8tYfp}EHtqd2*oP#Uqm(QxZ)0_(9q49{Q#&rrVGp?W? z`0~?Q6+T|ZHbhdHFAQQrFrTI8r>zz8D8DXT#8-nW=*RhLTrMJg8IIc~3jO@oM*1}< z@_1cu22T{Oy5o5vuRE=vyppIZ=+=#k@^|72`sK6y?lgBJ&zJM{A(Hs0LW6!vy||oq z(0JP(LV)U+Y%J(U`A*GJ2yIl(!?=iVy+Tv(`OGk9YDOMM7k)?pjdBR!3JQ<>IN!7k zPOzT=a0q-80c)rcM}C|yE1MIljQ|D|g814`z?VIp^X(r4kPkis-~*%i^5;yQp3eE! zY5>Z>N9EW$nh)j3RrJeQg7|9iEd_k$1blg!h+u594!3UbQD2Dx4Ej+yg3#ZB|BGv2 zkN$Lcg}OBT>Fr!gi}%Z9i(jLuWh|q=mkgQ#)dC$x!h?~Q(3yr~T52F_LvG1=?zKpC zH==y8_g=@CpLKM*m+T-b3Al0~vA1Ukzrdg4NqX!-B(wNJ5Za}NG>J&;H$ckyMDjDA zA+RcjLYkd6#=N}LeYJGG@{}2cHpW-Gm^saRy z*{NVM``ZFMU13KzB@E*U&7K69cG z{ITFS`*nc};0?M^%v`in8?s`iMW)I{OBPpHHhg(2W!=3a8o<(7iDbUFzOy`H@y|}? ziS>mjO~*4Kj5#cRIf>kW#h)+>wP*3S>N38v`je*JjY=D9$=j!I&jR0$KqxX8dfnm+ z9Jc5mpJwUk_IzydXU8K=##er=_o$?Ap9n_37UgYUg;1~N=}zwUK;zNzAa;DE$U`|w zswq1LN$#k^jP9L?Wf=#C`T{pm(|1NEoQ7#f?7f?aE4GW6eIbGP1RiJmCrsoT_~Af3 zDj&iOJYMtaEgZ`v45Ah37iJt7jMbmc+WXy8ydO#K$=oa~-fl_1)zEg#c-iMB-+q(# zu+(;JqDgPwKlo`KxBT{g&)C6JM(iJ~mq&_Zh&ycYX_g^Bvp)=N?2bEPPFyZ+C!eS9 z_y%{M=4lMnW`EM_*DzMt*_bGm*uN_7`7G4x8whNMt1RsJ)Z%*{jq(T>^w*vbW6gNi z;*a_;Fb}bo&Q{6d`zCNDg?;AtQJRAp!0nPX-0M)D^O>kfe{?K@KFv7XVI1vmK$t)F zpMGHdp2$Eqa`S7B0JUt`OV)M%g;f`rmYXivGg3eLZRW)40SydYsXv&<511}Ii*gAQ z==cEbw&Qf*fi)zM+eJqJL?{`}b&WoPB!LXXc6`;VC7aN9yaEQaANtr;p#!^t2>HHO zhhnGQ#n?a&(YhdG0EsRB=zf4+E#({dE5@#YOAud}@zuZ^{~8+d^#oj?b%9^;XR*jv zaZ`aA7%2l=ei|C;qK=h}j+Os&|MwXQhiI@y5P!!Af7fxpMHb&@!SzEp@-$k!v%6>t z=T3)}|85>x`2}}EZy3>3cz_#0K_d^vmI-1w*s76Ws1JdYkr28WFBs??gHWgD7S#9P z`=qIo--rqoJTrg7e#jYm4QbDZWNW9T+O$0$b+eP#56uC1AT?RbvBH>rFQW^`eomUhPCMsHmb`yj^m796888%&A*-*uq|>UCP>4wt7$bN}-`kleWw+Eb zsMBvfV45~zV{u-OXTan;3b)XUJo9=zk-me-G?^D+DE72F(5ZBRaiotwq3?D8-}BVE zu^UPdM$;Gj0)a+EbD~QSO}=j+G*Bt%Wz{>#iv?x@-vN_hfjJ0ubq$X%=r@HK{idg3 zc|*JC_8i^ne5J5nhS%BKMq-@fl2(08Px@56&cq7XxG^8R2!a3^bnmqO>b1jr5=UIGqEOM_0A zjDW8|2X_B_9opHnofs5Tt^(I=LVX1WeMb*Qvz>$y=Z4)pWbY3go5Dqr5Pkb+;DIRn zd;^yNd6v-mIz?u{0CD~bgS1(m1U;8fvOf=T=%q;fZ zXk^nuV4ZI1aOa#Kt({g$+DJ!><^&kJrbOx~ZM8;LAwsA%Dzf*7F#UBh+ME}}%p+oG+?@g%O_DxIaO={C3r zc|TW-x_B;y*TujO7#&eRQ$Ry!>MX0a_rUV2yzzAR#UoThc>A9*>M*|P==upaj7O7+J5joKC8Ou`*e2cjzidLbrTo}ai z?Id1$n$LnIU9c#9Vjqti$#j>%qtAzc(Z;et5p*RNl>OHmQLwwHqxlowMVJ?C_X(2C zQ<9Y;89BJ~;jg+z<}>Pi4uiPGAMSe#x;*=SCjvavET)wjFn3j+da6o^M)s&99oo>F`hIGBX0fM-x9gUbBN zUtq+#)xFkx6rOfG3hOU0oLvxa?WA>hFK) zTFi&+-GS>UIUciM>8bvxy3%=Pj1IpN0?Q ziZJI1oJR!O{~@zT#=3;a$$_(}uzvJ740eGcp2$kkntPBkkPQNt4Z>|isHH6UIwKv6 z8^7lJ1%$snWI%<1GE!c&ZeT7|658^nZvEEofAGc09#J4_eI$Ql3gylhObJ-h`Zarr z&{>AM%GX(Zv0Dhm_R=TR9(#iPlVU$G(@#oB0yYnZe0$s}9q+pJ%6jSGP|QB>pyWA% zD!z{NfPnKa9H>Q*`cuZcgCV{>ofTL%&UzCi=<|FtxI0L`UvtqVWQT6;cYNjFt62=3 z<{*RZR0PXVQpdHl5E8$PZnb0zLF~SHzs!dpzK%+eA8-yd~4y$ z2YNKhCOWgN1w%){Ud4O)5xPT9=7-GFI`~luX`O8 zw`-bEd~koz_<#oBI~c84=A(+2UyR-#`^7a7>Q9)9s={>I(z)m$*+%TUMDFOus!88| zFLkEQ!b4OGxzw}ZxGnxg2eG7wJz^K6Fu)BH>wX<%a@!q>y_*Zx{0$Uh%x*%USF`6b z#=>RR-K%*PA!;0yXg7i|q*HnM3J)V_RDwr`VrxiDXY?!R`a`iEAVaaQ_%X*IA$(c6 z5VSxmHl-~7!gvU~lvL;}gehuHLU3TM+9}C?y~je`CwKI_$0=JGWTC_MA9y+n59zo{ z+;UZW)r^}DKbITg*7mXxD2$oAdmQHR?)+iq^DpG>pD=JM<(>U8fxPeBA7V|6N_2;y zpLqA^K=OPQoF-6=90zxZ{om2{2z{5LDi%@YK**GD^@jGuHYnhuu205h@l_@!f2$u` znV63I^2A)+&58L#eKZs3$@PYNh9{{%z-Z+A%5Wai_{{!JxVF2%ba(sWc`1YgKg6n7haSXhE zaxHMZOUa9)u9sS2@6}e+{|dzuUys7TIB!5Uqi5cCVUxt-cf(ybawgP??;Y&_24WEr z=*DgI_!_i7v(#cw-LM`4DBm}&zFsUTul){<0()oz9eZ!yZa7?+)Qip-D;#ejF00f7 zTz|!8FnV{xO?JoUec{2N@pj;FB+^oM-m7o_gyeKKHZcn}vx|LSSwmCDLuRqB&|vB< zL?rY}kH*x2t3GD^97s*2B2i!Q0#XbxnQ^3Z%#CKmUVkSeh$0z z0oi-#M|WbeZ@?NF{S3HG+w(~bB;t_?cau*bA*?#ttN9&y>0(-&e@jCgELYu}9x$DX zvVJu%11&fdd-y6y=#0J-Dq`YyAzuh+sz^A*>JT#@F;>4hSr;%-WM}j#AfVO*nLxX` z7MT`P71I+I?gp#<3FDC(<4>%`_a*YAJqXiOe`M92k zsl)RhIvm)ETEcjCCUp{j!W052d*S1djDBP~=%bpafs+$Y!Ekys?6MnhkGyP>*?($b z$GiHDLgZlfSIC95H3{=~{sT!=t%O1IVbh1K^pwl*!Hl4(25VlBSHzQ7_{v?y6RAMk75S%)TiH{%GDyp~q= zP~gKWsXKUHviehBLU3?ATr511cOOi0PyEd62a!aNSvBNfAPLpn4%}~mSAO5(w_t~k zTb%D0J+6Y(_LHCvjLrkD5^UD^7X>W-l0LIvjyDaxG5GMX|K@c-O$`;gspUH_?c*gk zZI`+7$B;d$;G8JPrD-V^QK_Uw`q27pUUe`-}CKeoM;k zd7W~IiF704Dcu{Gy* zTRQrAHM_U)$f5pWnfYus_7J+=j@j51>GtF!In_(xNSvw?910&O*YOBahYtphpZ$}6+5HJ zgA&gbT%^Q*gf>&Cye7|8s4tQQiS^3x{L>hCJPbwgJ@40ST1{TklVs`m%56lW=9L5D%1h7^%v9 zZxyF}NspI(Zw;pH3kx^<>SYT$tG_IY`nj*-`%p~o;h$3i7H_Z4SMZas;;6;@FQYq? z9&mcJTnEqdmX0I(b{DF__bu=5cvb<8k09@%*!5RnAYMWhM_CSjO8SZCTVpZE`9pj? z8$Lp`al;P<1#^x1_E*5hO;vwYI|a#H^*DsTZ+9TfZCc;49zoTvPZOft z7T(Qlh!S=^Fb!dPo+>)f_v4fjd#($z$`3&thydfr{3ggIdnoqH<1O+}L_0W4<9+is z&;on0#WL_5B2-5rp!z%vjr=%o4lEXM@A{3MNJn6u}$m z!Ya(tpvUU#`X1O4EZVBpZso`f^fI^C7i!XY^45zJymfC@>7g z?m;x~{M3{7aFZFlL&;y{{wMJIUPRVr z5ZwqvL-$yVf0-fh&RD|UMVIh=4VCv$WUuB{0Q&W6ZV{oO*u=}A&2373`88L7jtYq5 z+4gE$fKu})eGu#A=yjkB#m=Qf?{)~Zm-JXo@x((~%aqj0PtmW%AMKt$F)BpJa4@7rdV#>=BFUz%m1s z>Zoqb1U&OG&*n?%x(zd+&M7p1B0mCa!umQ0>$3P>4J4yB3BoBte9Vc7zesphDr(-l>4!o}CW5mZ;V+Dy<&PU*+$d*~8 z4p!hV)S37JE}az?NP`qg8F&!=8X0|AY|ozsg{&z(#ZtEkPn5K{<;P$q(rIS#?w7n@ zK#`amP)U8s!XHvyS@U}E9Nej+5hCwZ=Y-+9LXK)Ssy$;bVT5F+3Zwm`*jVUC?MStS z0S9`i>pj$uPEjvF^`qZrHqaw_zGN5aQNA~3{#yBZVMA*9l#*FQ$qpzb>le+B1@->q zBl(k!a7&nqPP9;o(ef6wd?2VaBldKn@<5+L=#$Ye>N*nJRH96n!u14lxjM!A!ag-( zL>|=#(rYL^T-R`O1*boX8KhdAUumw4OYvXn7!2>pMJ){PZ{T19?R4->4m?Rh40bUH`f~%DuwjJ>Wls(PI*xKQ@IL0V zG~CAoygZVqhiTP41rdQ3PE()6Jq!}uq3?7uH@Gaxo(Fuo7qm<>X+e42ZaHt(#fvi}Yww&u)|VpUB`EpvCs*aePT*l@4Qd zmRAwbx6}9>B$x7~aS`%8n@0MZ85<>2uo2+C)a=*15=(NiZn5~=d4;s)&cNv08NDx? zwr&ExV}U8~mA#tZgOPsQ&&3T@ZBZNFbfF1#?)&?|Stu&m6Q4umRUFoLw1VQ#kIySm zPI&3fPzcpIWnc&*m4fVpG_&t-7W+ObOR==il4$N+v$&*zbepn+d=aSXMf zzI`9aL0ahBX(I!g9GgbDeG%xVb^G0%37hwr7wOw?gjh_LaK_Ekh_!Ra8WhCpM^%tr zbu>_g#-2*z``wrmj5HaY$|*nrN$e#MD=NzmalM)kFm0uun!ua-8YmK)THo;!vfmEZ z%LXPRgxZfEI86k6nuozQa2rrs_;d^+fbBT!wB5w}kheR;r@0y|7CZWg)jw;u)i-|bvmg4WzI`l$9sQVtet!|t;pdL&)m%gJ@x%I9gv|a&hn)qPg~|I_h{^k@ zG;jqF%s(|_GAWO*;AgQ-w;ZYT9YqjLCenT~0%m{qIiQ-n|AOL=!e-3=*(sbbG~}Lc z_8l|R);2$#@Hgxl__GrcY4#oU$JRqJbIM`tA!6=KTKT?7>G4G$1_n=pXE_L97>L34 z;im}Vq{}&l?XVom)nZS0542v*X`*y_gT4>+owJa?#lFYt&+0X`os(+yW&aUe`i?9} zFU09Ci3`|FTzC% zlGT?~Oss8}(XpcjL?18Lt;+ohxmbNio~GRBkWt&Q8T$75;HQ+ngZhqF5#iN@L6|h~ zJi>}S^=i&(P!?Gkcw6as9meWaMuZTH zS1}`L;3H7$x_k*&Ai+Q~Uqy7c- zYTPY$%~r%&^0Io}mlCtS{Yh{gQ9PjRZpi2cb%y&Cwbe}eU2g@Rqh^H9<5g;foos?A zt8h>_+ok#pxPN2dJk$ayibwgg`5{@~?CHpo?{&d&&qkOG*9v2S@DIH|&VbFta)oz8 ztoKLg)Jd8Pd&H#RT#_%t^GgWKgJWfyW$N6M(Fm_{rCArOL-Evg~)YF2=s z$mC|*7eJsgG)+J|P~M&}uf_@%$sawBBp+~}s-`8$II$T`=fhC8N9Zg{LIRi+3GYCA z^qvqj7>Nxk?G=R1%=%E@&Ub_15opGr{Z2G0w;uWOt~7Y9FX0)Y)M1=}uhZ2*NzxNa zx###b+YyKQ{=0(;Kf3@r&@4!EH^|sl_szbB(k_M$N@qR--gO`q`;H7GLtMR7!uPMbH(~qAOeOoFo`evL-=(*ztN;J+G`eE%lk z2LkRBaI1h12zZNtmkHP`;9?Gk=aYU-aSdZ5`)$}3xk{5mB)&i#N{SQdv;rQ%q=nk& za{=EJaG!u%1$;ojTLipPz|{iQ3Ak9mA^~#*oFrhJfLZ~MU_QX}7w}C1_X)UFzy}1p zg+sNx$Iah1d`S}`JR*4ER1EtWUzvO_S$uC`pDD35@Z@_mm(4CiuCx}cHPIO{OFH_3 z@+2*zKd=#<66fH*7*8y*f8`*003g86GkYV%TObx&FITWSxYGcKJ;P? zQ2O>;fO!LE@6oAi!Yy{$Ymp8P9SZDxiM*1g0NK)`=X^Tgf&;L(lUqRM)LB=w}yZF1_AK!k9QBxnc45Vl9 zOBG(8PvFpBxC-tF^Grp&rwaMqK&|&DxW$nScuEL|h5wG=Lk?sfH z5+(DXh^lCPdp$62RM9cW!HSIp({`AlI5=F340)`&Yv2MwIhMFii85_Z05_%M&orRv zt?_8G=M|Za2rDvAAC_rA!oVXhaC6AQxo(Re50B}b_-SBPb}|kIXaE@O5KlL{y7=P; zY&27%XBO^_CY92{3e{__~aPM5p>S@Mc~Rg<5v;t;_q_}>^q?DUxS(d+UDm& zuaTchAEEsBgd+Zpn5SykltU2w~6={e<2=Qf&AD1 z3-K-y|EY)<=rE`hp}+k?yj8@HuJ_IVrd^1CI1>bpLx7X32>z+^)pXgb@_96E%ut<; zt~ZsBGvQ{Oo6m#k0;-1*)%d@N(|#&G8a6i6)Y~sg&B#fsZER#!^Hx`tJL(%;Zilm= z(dKeF)Ou9YEpplF9W#uzb)M8#r=zZ6t?~SpR(C^7v+Dw5T3T9!(U`izn3}r6(byUu z9$w~bXm%Uj^i>d|7@Hg}N>5yi!L{1qbRlUFqr)g@#%51bjl)Ttc5vEPIP5Epv+5ce z9p{9H7jVp6vg;swi(0S2>H7p3l-SdXmd8WNU9U1HqH`(bBsn3URi9c zP`I= zy8~(K9cj%D_te&@YTBvp2K!2f+cj0Oyn>e2bei@dPYVnZkbepb+%?>g?&X+ zL#=xX#bg;5t#KIVv@|z6ToK28jRq!IU6ZWIPno1Prb{CcHsqBvDiMtHp4ulb;jx$wKH5Z zDy^)zd9|&vq1M>g1pU?aoB?*V-z;nK7@HlAS`y-Fb=Vu~)){R^vgc-7lOuwaDTeG` z*Xl4fd0hOnISOBcqn5#98k*}>YljF*$QHDy6f~;SvC89s*&zqWVC9acmeoONxV`gK zjLrXSXejzuu7Y2QqjWPxy#L?u1?RC&@Yeh%(gdeh!zUp;z2BZ|7eY~0diGA)c({AAh05W?iLut z3bHZu0^Xrqo;vu|VUr>^q>!LeJ^YTx>0m*`g7O07?QrqT&;{))SZZ+o!$qrWa5izv zuR#V5CrrdvYfNfTieTgh;&Q{zcn=-XzopgDEL3)J9i2!A%TmM!#i(hh4=T6I z;aEwft-*NG+)N4RHzJqBj8qHH9^ECVVCqPav=$mIYIb>AsVl<3gLu$=>fwP=nQ9L_ zVdP@oIfJ68E23XvE^JgfZcyBshQ>zz)hhI;1}E~vr>oFaJyh|0;3LB}|8E2fq z%QfsS(Cr*X$65@b)cb{_Z0Ugak)M>8@}s!3_(h+ont$R7V)-g64f##+bf z20JvMQfA@tWtp?3)`K}lv3Z2H*wI`I&lOCfq{wN6$I83ujPUTJh6o0Sg%GbedLsJo zf48KEt(jsQ^S7M~!*3hEw<+wp?=Nc2zTZA@@6EM$Wo~?T%zfM6TX)*P8;3T&-T%9@ zty{yNUH|xHVX52ydVRukUA2a73EvtwUu0Re-|Id!-{*_xI?mza>mh8q`pP2LJfv4Zi|KXWOKWRLe=~@0^;VaQ^zPD`l ztB*XI{`RC9?1P1E3*XuwXX|@z%lA*6apvA97vFaC&R6vJKfC>|?IFp!jhd<_-j3Rr zI1u^xRqI=(j`bdJUXLf4c)-Ka~tF^1%m7X#7-+Gqejjw$jkFPp?%U13EpFa18 zX|Hb&+;bpoZPpL?vdlx_x5VE%=A);hFS zH4f|RKQ6UBQS$P_Ei>HgnR`D@fBJRP{U6SI>*j;AoA$nX-;dwF`PxMT4Fx~F-JDgl zvHnke+pFJkrOM{d5<;g{StI^Ay2}(z~)Z?mgE@k@ip8XV%_y&P7ep51n_>#gVU!`Si}A z@Ea#T#v&fSE9_G9jrzm=_v)@%@vU^)zjkXIE?83Yj~DA5ZL4w`$NyEkvU&BXum9`N z*{}J|yZ9Z$OY`2ZZ~1V?4?ldp>)L`{+fIJt+RfF0d*6KXvKwE$d++Xpx#iz}So%%< z)34SqdFFxlwOh`epYw#}owK74T2GDm^O1R>In@`-rafO*f4Jzw`iH*0wmDnj(aciMBLaE@~}4ij&pOy40hCqImazw znk(i#cXQ0e+dqEn?8h(3J#}l;?br6-5WVY-&$fO2-ug2>d^hs-{@1RY^YQE79DVZr z70upvPX9~Xt_|l;+HvHgHJe-3%-t6M`FXmHtrzKsUYMz^TOKKm9lFbLUBhEFM_(IS zX)AoCF>dY05u5(jAN^LPS6;CD$To^WgM~$DVok`MaL};PO|Vm^(1EC4IuT&pvzg?wv2B-}q$31NT0asLAQud878N zzoabrpz^u;x6e$wxbDgA^K5%VPF-=qO=q{9HGNm)Q+Hn*wdd3iHRpAH9g!1$Q}Ke7k!Tl20uQao-0O_V6~%KA z$A6`mWz=CDG&*g~^%%I7w4FjXC(b$M_RhbpmH#gKZ;Meu^=vKE-HEb~@ac*USb24?AJU&`{I%p`kup@8S9q*H5^j zKrcbPtVvyylSLotbT>3%l(aQ8Vx}XOv|^w$Cbja#Qge&3p$RMaRF}g}3t(n6E^ctT zJ+{V$9tY;llo-0xR5nRWj*T|Ax*&oSrPi@;p{B!-;)X0WB_EaS_(-S`1H@Y5Q_J4! za(HT6Xx>FLby|GmL!<5%drRZ+od=V*V5Hswj^fv!~CjV>h~~JoKNS=N-K(& zT9;K7l$Mtl7N}cCoJAdXl}!*Vm4nuN#BhRmyDFQYNJkU+=E>M9v8|+)snMpIH3>{R zYj_#SY}k9K_q2FmjC|XL=NQZoEPO;htqw7l#gu21>=DVM5(-r0@{8$@E6fQ*v@Xm) zj=Fgi-Zg4J?a;d8`A6fMn~#rY?0DS$7($nQT10gO219%$ICY+ACI$9{OP0c)=kIr$B&AS8HF20 z;fF?*w`&wWx1eB#F}d8aI%A4)j;8@`ux6dHq+(e`CUxhF;0aQU*=f_#(wXub=Fj|J z#{Zwy|2O_$Z{OeQ=ePPnmmlu$|I_yHpYI0gjtVxagbS2Ec`5 z@o8^_s{tRz6@~C-zz=XtH3s2BfFU@pn~X4hlRXoc1>t zk8n5OSRB1>N7x8>(#eRYFrW!nH^OCrdOU93kFWvob3C3si11-R(?on%oOl3NpUK!y z2)6-FPQ>@#uV*YBuo#yC;WEGuT=58Z0e*(di11;+s3gXwAZ!3U8CN>OM!++1Wg(mn zsGY=EF7W_HPDU9i40tZCr3mK(K8&jx;mv?g;%Y>=8&FC{*@+);0^UE z;Z1-GGf`HAs{voYbrj(~z{- z`2Ih_)qwFhx!j1b5pWZ(^#~K3cMfA4i61bl5Hy7I0c&t=N4OQR3s*P71UKW_kFaqr zbjQ_)a5~^jT(2W+urM}#K4aIwe)0j^aNS3?1b8*BgW&o9<;R~f%Mz34z-|fF0P1y2 zFO6fm^ss7etENou4(SUQJOAJOj@}ZE!k~WlS=Y*t7)kve$FkOwD9$FpJ z%4Mi&i9RQY9u>x-<^-4E1ZjiilALnr5L_2jC&4@@H?J>(5n2}E)TV2y<<`)$kZvhL zqlxI(hK8nxR4Zi@bvimd$-hU)i3?|O8@0@UkMl>akeT*lQO4kWD1D8fQ^Ox!?OlD!3T>Dl@+0X(I_+^b zC6TOhk*6V?8Lk-J@~9`G*PMV(d6BJ-hN`Z@-hlr0`;{7)wRt3R;|`1=PhgySe1x`q zCw%ggBY1G=r>7JwW{U!+2$(P6VgVZkTrXgkfcFUalz=Y__S_Xzk$0e1=bl7ImLj|r%jDPo%vnke8D0cQv}Pr$_j)(Yqr@Ja!HFW`LwJ|W;U z0`3#APr!Es{8Yfh0v;7GWV@nQlz=e;P7p9zz)S&W30NfH0s)r_SS{d10y+h}Sima; zyjsAU1iVYYhXi~=z-I*9E8xol9u)9n0lyURsDL4`H~K{h7$=}Y#klgDeetUJ&At?i z`0uu_gG@OWRzMGm?Y71Wv8Vk5E5r`Gb2OQ~EX{Se3p`FIHt5ToEp|L8XRrL6R$R+o z3!+x8pa=ILvaumZZ?(DHh4hqxu_VGv@I`g8@NJ1g@0L4_|;1rHoG`kr)7E;`dvf=c@#g5U%v4&b5 zw$(o)vt6NlE58iSMd(Nuo^x|wWVdHr&VP}l{(j9y+JYJk-?&796vz4+$&c&+>4r5@H(h1Tx)mmt!W>I6>iYuzvX$g|Nf2$P{Vmc>_K>r&4%vu_9nq zRRvYz%$2=L(FUzl1Uk0kS2MN%A)J!Lp^dc-Znh9uy~9mUoe=F}<-i+I+m7bdtb)QV zHC1(}DaOtN)`&v~t9d-uI>22Hca^QRwMse5P@_;hE|gGtuEUs%RoU!KwT;c}VuYGp z^;JAub`7htE1^3O!gDDHV+U9jo&`1I4UjKb6&-Ux@JEE`-`22xl6c0b%qF%?s>1V= zm8=_(PUtXZ52+F*sz(TieOOya6`3siLkOv<$cPE8qNhVSS!`Npm8Y4@cq_DuA8x{G zS+>>SYz{kFMmItn){nBH<8-;Ml@5W{u{?x4ZabU7p^MFy>v%5b5QLV+a-ER2Kt{b% zHL`UwJscx>8)Tf!vbVy5u9k&BcC8G7F2-(_A&9fxB}3uWIN!wnAoIggcqijg+2wZH zSD+=Ipb+Yb`rcC%Mm;gMjY7@#rdGCxLT((~VsFW-Rkg|W&>ZQ1_?ll>zM#-LEt4O^ zMRqaB@BjMMrcwUL`d!?U%PJGx-WlIk+cAZR^@|$(; z+NR-y8M7y5q@_1odV9~3riA|*pYoNn>ZQ6U8dVfb`C-e_5k`BlBcrN#xv7Oq7?I-6p3 ztajkg5Zz}_w7GCNxn-rpIdQ6*Xx7wUlsIc@aPG6F4i|#b&O*Ukar&jEp^;89{o6V^ zj-6^tQD7FPo{d=YkgCHfospVKr%Q{?IQ&c}qA)in7CJOC!i}To{1`Sr;V_J5`wA`9JTWWS~9`vZIsZGswWY(tIGPAPMGc&X6@}}ATd-TZt zRXwt7nRS`Dj%lgc(`xckv$C=>Qfq8^_SD*(yxJ^VmMzCIE%(1kkF<6tO=|A6+Vr}d+Voo6bgqe!_Y7Fzf4ylk(tlNxTt|A{bX!Jd zYE50uG_;K)Hx(_Fotl+fSDT$~%gDCn@wQPknKd=YDtXtKdYrMtl}uHA$vNt&Fx5N# z2Gtsvf9M>WBz;vSMCZe_^#;tevz8K?M#L9KrmBKSmCcLQTfXf75-;}c!GlyfP}Cy z6)Jyl9EFv5^U`06SMrmVsqyN(Ic&5bfh+unE>QW6VxIjA)yEY6E2~ugbiw~FJ(xPd zPm~AiT+zOxcocd2hvU_G{Jo?2R8*07spr?_<*rfVyT!V|`V0Cg`M-6k%5O-?=UM%F z`R~HVK!yDX{uoukQBaY;$gA?_3;qK^bCuvEO8Ji5sPYHLQCN}p*iCA@AuXS?n0`T? z!vE)oRsQNsh5sU@)A6*yHzoi2Csh96I0`HAr$6~i@k)MYKc&X^W#w}b^L|yo3B4+R zb)Lds7R8hO>?ZO*sPd0yQ1bt7INmr{kwr1oi9nB7B175^#vSBN2_S)Q>REn%Orj};ng=cr|?D}R;ULK1on1P9H zYs*yZ(<;ZxQ?Ub-THoNF>T=pgs3ReYpDHfLT1T24Lr6Zarr;4MMAF(<*qkhsj%`=D zS?HP1fG0#3hP6XI&gSFhX{HT7oIS^8BVsfoF+>RU;NI$XQrh{HHgpXMB(#P;^A{2l zro4oCyck)-rOApk3d_0&kXqIyP$D_(cy?VF>BqNp5qAQ$B;9ZVULIN34mp~t!lea; zWtGLH3#xFwytLfRZk2x*o(3189o`Kupsif_*6?{65#vCXLuy0P)4TH z$+{e55sstq3n~kjRzFd1Iglfw&EG>8hA-8Go<|>wDD)$GLl6#NQ~8?VvwF%3+P50kq& z`5`%yo}bOZ%R2TIl`TA<9v-tfIHm|6ci?fmdE9m-Zn!IngnM{o_o&F>w0n83wAjq#W8@v83M{5_ zCdWzSlcFdgljEgC2i>0>+vzQi`t%Xd!R^o|?UrFBVXhs>P;C(8t zXL_pcLn>Z{{5}UVmb+`6T-)NIN0uQ5nLB5J%DM(UVWCoA*sFuuO6J?D`{S(JF6Nc(|jAPw|p?rVlSRY}~ zWHZMO5eB#QIL8i00)u~kf@APlK;faEuD%OadMd_wp2e8sdcQI&k?#tp z`O0zKTf}S%Ux1Xdj?xFuXUa;8F;OV5Kv&-qehVU%DazLHEQFQLgaZTR4m}!962tp^1`{r@OP%*iIhR!%o)euLHUjU z5qA<#QXziJn50NZR8C*O+P01%pBAS+`Ez4U>C0HGVv)ZPc2ac$LvyJsgVz z)>vobO6}#8cu-na=x@3m-6x*cVVwvzVT$iz0dN3RQ5QiifkPpVhhiVr&fBB&zI0G4#z>Sx50| zYZVn+3)SX|ktfAnHwLX!VzaMkXoiVRj#HXTnfaI2iL*{9W-^b#aE0R?uxtnH5@#Xg zlsGbHSu4z{vZZ2OQ%y^wa^^=qi^uB3LIUD=B&40qBcinQ<%-g}Qht!f)~I^(DLgNO zwg77{n;q6lpGmPJSt^e>Nv(z8vdC$1yHQxRm}XO@smfeT@8On~FJn5nChlu0sW{#< zywtICMKCf$5hm9vrBUUN5+Xa|9)=7xi&DN6Gg;NzJR~>79We0Prltm23vEQiuKITE8KzffAI zI2sqH#fNPt1~*40gw+z_;fOJ847|6znj?u}-;&TZT*c(DODSe8N6rfCC1f2(ri85| zp6X4n>DyOfL03OkEpF5^gU*r$}{a*oUjBj+l&aU>rD zIgkxpfH^Fm1YE(9qObx=k+QJG6mumUYBE&K>aL<>L45z)eb;)rPB$GB+G!hhz7XyMHq5iR^U zM??!h!3BsGev%`ig`eU@5G}lgBV|epZ{^5RrG>X~q*`g=?OgN~-!}W$kFs_6E0=_+hgd!|wnEV;fTaBr-R#X+3tkyZE zg85k8o$?S*`xx%0?7@u>?|ibsLlAoa)My%J4pKDDve>DX;sq6zrUeCsRagXR`hG&p z1Wz+g7}hdPA1#NlDjntlDH=QIvW^6VmQ|LPRapxc7g~chrr?q>k7HqDNd>HDe~ss) zaS(QD74k2yTvS%Pps3WuR_IQrcL68ZYnaZ+XG#+qTh+w@)1C1?)YpMzcDPo$TUwcJ zB2f&WR5rM=X49QXc>ILgHA|T;kpvhK#sH8+;Y6ZySFf8ycrwK)_+-MTP&_}!N<)u} z>5_?>PF%s%6ryHll$#khin-f$}(9-HavrJe~;jS%i#sNmAn>q+e8K;zb+?Dqiz}-NOUf$oV2gqa7Fn%KqEK-r3*j(}g%T`B zf8;QiX$Tf9V_Je3atm1)h33$ngpSjSE6Plj1r`=gSYdg2X*rAFEVSJcNg?P`jPEhB zC_)x3n7^QO$pRKlh`F!;6C*1dLr8H3GjI+B#wvkKc9IgvV&gbVE{jnJxh$3wAT~~+ zAapW?_})r9g-{(8s24V#5ZaA7g#s0(qC)yW+fZ6%vU=sXRqQC@5lcIkZ+_W6456eEp^Zo6$%qvMV-H zN+60RLwdp&^C=kmC?QHs;Bzg+xU9Ue2z`OVsK&zb#bj4)gce(^g>%tp_!G|&ti)6? z9~_F*%4KDRL;%V{tI8G^EoPA?%a~IDDJCSIc6ZK@BX8(~Sx&$ln;%e)yixeHDjY?j zqw)joM5J-+RDLrOr<~>#_{9=mK{WZ#|&X-l8ned zdzW)0`-N0N(YvA4;pVqvQSw^sS~S;X+cLvtsS)mbneILz#b+Rr}YkXu@_Py(_UU^ z=qbnzt`i@;Q?~38!D)qS;qZ`v3C<)EZ7 zq_^O_CN(hW51ax2F(7T?w6iB6`hMv#NGI<`Y*VUe0(kk^? z67u3d>5ln$5Si*&OP^VyPY*L`RU~XnDo>@O`ut&sNiL2pO>LxQl;kEW zl9r{8j9ilEuMiz_y^*EyPmyBf+Kdk*)zayHCSAabA<>7+C$(ZdEv6Atm2?l*G?QA( z3ROzA;-+1S8~vtThX5@?rrnD`E2m|7M9Te%jAbKTwp1=< zvaAh){2It53OOWvh~@lQ&_4h@>!qNyt3=uiHhs$2d@g$cJh@Ui+L0Fp??O-)WYX>G zQRHII2959d3aO{xC(?aSsz~MGp~g*$ploSjcxe1EvNSx@pduk_jNze7V5qdJD*nDk zL3t%sx#T67^a0h~W+6LG96ONiNH#K-*VyX182tq;T5ILae~8F8L$4VkJv}93(not? zj-l80U6$9-Z01|c3q5$tgh?OMld(hKpP7$aoRMUrJ6G{H9;EN6vn)dPd3Cg{ge?Z? zdm^nP5@1)#loDUILk3jy5l)yxN-#RWILFJ7IsX+Ri_%8+h z55(_8;I9Z|YzD`)jldF6r_*jipn?K-A#fK0b38&yDwl}jx}^+VjShv_vRi@|o`O5j zAIU%u3I2&xbNESjTxEn2(|{*EN(^bJ;G83ZYcul5`B5O$xmgjtMine|A0;w~!(}5< z-yfE`pBU;$>LkI%rJgMiE_DV5DGWCAiFL$Z5EbLjLK;Ix9LEg2a0GWyu25AEG8eqO z5Q|904APRLixrVkoARMNkKj(9`}`$JoKB6yN5-q{{Hcw!REd(+C_Y!=GZkqWO=m`& zl?5-CHMZc(o$wd7M)(4HzQm%fBmi*@O|4bp^)4wjhtqHpx1q7tZo?cz%2L>dCr8b} z$+(}T*Q+8|)5xnz6EB-ZUP3hhB26S#W1CfRlmy|?BJa*dW2De5>gO!v+F0a0OTZ!P zF2KE*%f@I}RfGL3EJUTrwBxDfi1V6!?j~g_B~V^hlQKwI{U1>s_d>=zVqe=(Wnn4Z=qFATHUiEY+%g3Vq9w%G!!UDsUYZgla&SJ7K)HQ0VXZa8Hj=GWttf6r z#o--FCe5WKczEc>hZU3g8Ea!}L6aC}EHuo7hqnC^Ycs7o!Of&%T8P4G$`qkcRMD%Y zvDUHH-s&EHjZr!;2P?(-N^GlL8EWgOlF>1`g-U8{D`w9$6xUPX!$Wl<-cnUkykPDU zEL*S$wOX+Po3m(cRf(z6f~6ai8mI=WiVRBM=yuiOWy>m@Bcbvy;Zvbe@n{qgz4Qdp zE>DXZy=-(e=D|3gvX)8b@tBg`j4`?*A1t{ogfY4zA1gT@6uKfemZ0_-U1OdoF+x$g zB7e6)yagzLetM~R;ZOiWw^SxxJQSeB1Q~Qm%S-M7piA0QB0(Ho249IE6uP981!xXf z0bcIpK(a32kl!LZ7l`*b1sI!Gk_G{EMP6Bw2SAsUQ_5eYkeCprR@PfXnC%A`Fhp`1^d$z4yKM{iYN|XX=0c z^M&T!bMCqOx#!&VT(u5)vA+^%XnP{-uQ-GCuFqI`!3U9)7d(N#fBP9LH`?~MhcYtu z|1-{GBzRVADvpM^L;IoBX~#3fZ^9IM4!;xG6ZnLQglk>~>}z|Os>(a%`v{xl;||KJ zqgy4Z2%t}tH&ogU6rltB^JZ5RVIdISd)mwU_cv#0bP|V1(n1{bDWy9wtmIZ z#xU@r#VD% z)u9dvEO#apI1OHQnWOUlH5M#cqA3_`iw(A{Nh70R%29=dhV)X9B6c?bQD3=;-Duuv zfZ}zEw47T?Hq5*U;OrlOu*G^vCKLydBw-B3meTLffcxoL_j2;Qw{Oqx5DEXkZGM&WX%Kc?k5_1^$W<4x9|7omA(YWTZ{(7!baxu zFC@~P7DEFlO@sILy>VXt&*#^H1P4rzxvLP01^*!H)7_50m}pLF)&vF48mLjDgbOh1 zf zhR{7v<=afWg4C{+)Rtqu#o|pujd1E!o-~DI2grZg0RIX4@95m2qR40yO`ZJ8P$Zz* zerxl8gQ)XHBHKU zA&kEz7Jo-t6w+e5V<}u3OWwpkQRRQkP>e?Ww}cd`{2_y9Ps{&?0j7ZHo0`ZuS>^w; zL6aX|HDQC(RDQuiU1$jlKWU!LAyeqi?JQO0{R|=N8X}cUU-20S(`p3j{|2BeVRbCU z)eiwG;@C=b08vc+8D;=F^m>|=a7M6)q&#cGcc3xQ(Ac=1mU}V0HHa)_9D|~<3Jkhc z)gmMO=Pe#&Ei2fsf5;hRO)S`Na+fp6*mf|Vq(m z4s_FoS>h+dtit|gFZt`W6@MV%|}R8&JI00h7cqY&^=q7{W1+9&#D5_kf9IPDs$vyBPF6519Ip{gnH?KcIZx z6^JUYk!O;CA%G&&qYoR+OwODuz5x%1fAXYpoGT83Bp>%YlyfD~svszA?ra9<@D(rR ztYTw04*FSMQ*$#;jA=|BUQxo4K4%pxRVTq=h_-Hn6KohP9F&l&8FC{aa!_96kw=p= z&O!0kIT4C{j3%xTJ`9305wvd+hcTH~9G(6D2EXEa;q_sN{eF+aQL@6wa%lY07UTXx z32fl1;GyJ;r?}0(@Trtbl?kw{MDm6X-II;pRd?us%CF+p)^k z)rDmm)Lfgrlli(NfC}5c6RNoXhL$c=L>qg@{m5s3T#+X=rO>I=Ffto&CwLFQN~w~w z84^R$gLM*DC5CC;VRFjpBsKKV^0>FKfz!p-PI=2r$b6WPZ((xe*#_}&I=7X#rUH-F!oZVKQ{0WQAIoo3Vh0| z39EWJMjNQ`s6b`Tn#vwEacGaKHlK+@t0xY9>%8sit@HZ7rOG%K?14DwTUsX>V8jyX z+$d7-ciaXU%zh1PpsE_fbXBf|SE@{~!4jBF@l#L;uZ%$chmco33PNWpl;!;r7B~KZEedUM7&A#$eWJLPP^02NOFmhKVKaK@> zBNm_>Ig$Vku>d_lt>JjSSzCnjw>@-l7Uu^>BAh+yz!bD^X zRR}I#k6lt(iowR>bHF(V5MQ322d$xdB$b$RCbbZxAeG!G_FBHkrf2!iodqV{=TT(- zoc&i8qD$&X?qnntg!K-k(Sy#Nx3Vi^P0ZkJF7BifxxE+yk&rdpChc0pvq~DCZu6qa_(`UX69e;Ox5kayE!*>`TNj$etkCUl3|61>)5v z^RI!_`TEo7$im>=sI76t36~!NRC=qSB$wX^@@omV+{;#bRLS9pp!D0u-Jd*#9D@^_3Fz&TLd|~|-_guRRk==%q%$)~OJ`PU zU-tEN;tL`2N5fL8=1t>G-YxB8GERQIRL6vAS&aSIiANctQxQUh#|t5W&Y~MsW5`g2 zW;+FvZ-6MK-%?|}iV(HS$v&@>AeSxs1*L5U z&(8F5jfcJ}z1W~x?7MAjYLkx5wvHRjR;6EvMey}7f|8#O)U*@~e>QGLrf_UpvNpe0 zWYbj1Ut*#94AL<$XG3%-=B(79+0CbEG_`3-mBBN?6O5ZJyH#kQwVyI|L9LCFmrRZV zl+2FYrKiUN-)sZllo7Zg3Q)2!a+h`*H>>&kCU;D%J4SQ9akF55(ljVo$%QeJtBjj9 zHUVrUHTG(l2hDlTJXLaa6i7{^7HKhTum^19%y8NfxcH;Me;Z6Pj>sXL<5pClCA0+i zlL>Hy0bYHY^c)T~gJK+UA^|=Rs5H@EHwY!by*g8}&hVgi@>yOR#a4f+0VgVX#fR3;LY%UI;80^7FOq4!v+${H}Bp6iWg&Emqr+Fa? z#Q85sQ=Ftt<^ZS*Hz8Zh2|0WD!rsyHi=`yG)>kot&84Z=+>CSVY z{Z!;(2SM7yt%UFpb=u%ipEeQ37-)?IJ8b}lwTr6in4J2e{KZ%qdh$e3xfeUkfxEA+ z^nOFbf%kU!>t04BAl2hcSLMHqk;J@nQG3oLBvUxJP7-K0$+#G|O~t$Hdj7_pJWPaa zf+t{Pwq3IL46=9v?VLKhqyVo0F7GjMF*{LO`|6k$QW>_#_^&r*!RJnkyuL%nD{!*8z#eUZ9zKNK7@DY|J{8>0Z8uKW5=9 zbrSA`?=WoIhy!S0&EM!OtFB{gYB*xx&)L5g5gSgwQ8@j1RQ#~IA$8(ELH^>MoPOX; znM>R*iqKhAy3&wP&*i`yxl4KTTXi^9es;`Tybf3|Rr<+lO~s&m`A7U;u>Pg{W8N*+ zyW%VpbLnj{?+dN>xX}BdnD@2TdsgWEOw9W+>%BVk{+F2dPptPw>pkhUn77hRlJdH& zcWHjC(1Wb^p|D^>V&11%?_b!FL;1v*w^YfAHl!Ln)KTgz1d%5H3+_V5(p0yY(RN0B z3_dCEpvgyyZF;g@iuWfxr!dsCE9Lf!74zvwU(QaMk60k5XYdx_Y@feTdOQ{OB|a7*gvWV>J0+jR6He zGC(5&EYblmGA+bGhkfe`F-qOHS>^xA(3}OD{6EHkg504x?H>4iC`_*JV1q{Lh>Q|} zJ+uhNNcnt1VwFSLP-}?FCHJhF7ZHQ0nyCzMZWUGoPBLWOKp;N7V&2al%QPo8%UC@r z&pyE$dQ07vYtMr>*GWnxthrIha48+C%p9rJO`x30Q{e?`7WiAf9=eeK{6iJ`?F9YT z=~sR}u>9xrFYm;M|NJ{D?DGir>y)VLkg(500RU7_+JAj*f1nDQZLl@Hx%%7+M}e6&+5 zAG)pbp*vJQ1R~`_C{jLzwDO_LDj)4O$|v%OG|e1K5uxgdN>e^WQ2EGLD<3+0E1wiY z#*`1?Q27wB%0~!|@}WDXdTVqa);FkcnDckIXqHs zFKjv!9VC$Q)*aLoh3tM?5T>sx!Ye+o4AQs=rhs_kAa@@rZ4{sCJ1jUhrJ8|{017^x$G9SZ{ipN*bfCT>0RZ@{xSN7 z5x@yJwE(7z0$9Ef!2D7G%NGKeUkYG;wE(6|3t+*80+^5yz(OJdn66L&69@$`flvSw zpa2#M3SjMk0M-r&U?G73)(8k-K~Ml|3V7jaT)@~z!BacYh&ao5`s-CDc0Zar1uza-urn9#I zPBLUn022-cFaaxoh0q9Kx?=*EU?hNJP$+PBqdFA!FmA>9hW&oSbw0aZE9V{>JpN002q0I??1UNUM#w%tV z2J+%MH+;REEXc!@H^*p!Y?daX-rn526|Z50)VZ3v&gzUWv+QaXb`g*BGK;+c2dVi6 z#@a44p+zaD>RuMgTV`_YY1_W)Ur;j%*`PhnnKu`jkoN+k_pmY~zctWD{|hvL7j#gl zzlJistupX4l!1p3?qy%W-{dirK~|^?NRQF@5;Q9NsZj=WYGoiD8p=SvPzL-`8ORsP zfL|&Dezh{7ODhAxh01`CQ3gUH%7Cs=84w7S0fA5%5TG&;3MvEbfHKeyC<7sZGSCPp z13^$3XbhDBU0NB?6)FP)q73MWDFcF58PJ`k42UqwKs&WEpxY_~xT+akaC$8V_K z_X095As8hTGi+wW+ZFERsR|bhLZO*(vAFMEks5)qQ4Fn3fVrO+d?I-RMt|;=Dfagu z3Tw?!x?f0r8o>+vUKaP={SrZ06eezQ-~D2W7I3RnR^SEI$W{=uxbN;x<|9(ySloB_ zB=<-bjm3TU!vY7svAFM^FK~fxEbhA(2wdhHi~H_{0$2IQ;=cP4fouFUi~H_JldOnZ zUt8RFKPKQLA7=7rcPaOxWPkWhB?ycA?#Bf@nP5G@PY5`jAS~{?7Yld_!Fd2bDPSGJ zl>k2_;4I%*+;=aLl;-%fxbJ>i@-`p91m*4(U>N|Y^nC&}060OpmkO{Bz!c?vMu5!# zPE_t^1?cc;ao@d6fSo=q?z^88V2@9W`|jleT;$W@zI%lLdwp8mcRw${74QLYr2q%v z)2iGr2yhc30I*+xLq06-yI&Od13oP7y9dO5#HYo5_bLIN1c1^U6yR9^D9zOZyZ`{D zxkiAO08CQuwF3MCz+~lKC%|hyt=+rV3-J5Y4y+g`Cp*L9zWZ?UW_ozW!s3uRD2G_eXP}d_c8H%K>LMVNn6}^9~aLf8J=O-uZTA+?&pZH zeDC5D(W!F8s=oKhA0g{G+Qh#1scLvYWxTBw{hV-Uk{JIb28^ugCniJ)*i%Y8Dxfv8 zpLk3_ZDim50|kP%tM8UMe?UY6h>3jnXU;Q3L`L)7mmLP~6S%)~-eCWPQG3{=!qxCM z9FZZ(`zR~kboRqDLAtk`N^CGhbia?&{imVJYg{yQ#k_hBz3S(|0%PF5?(k|t{xgWC zphvlXkkks6_cYN27Lxmub2Ge<*R*i%pCz?~HNEf7^Dj54D|fzsm_d9oz3(pY89``z z-#yLW0?I;?--~~JOHln;8h*mU`KpjY={XBGLS$u{dB^6!S;Bw6LyY3yZ0-#s_U+AlijxHl&^p{x7GwwQa1 zfM7IjMBlwNN(@5iwj>+&Ad^O=-Y(D~La2^A1Ufnu|D%X7~N$dCitd>o!ZQ)4a z>%tkzuW#EB;+_^A zcMqgEBR`5cfA?VOa*2rH6S2WkWX|8cH}xVs_4wz$)Q8~K-8wSo@7|w!3K>CGqvt@v z2;2u!UqqOG(Y!J6eta@kI!ZR|fZ#+~Tjchi_oB#7U@4m-^h-oTRfN+{?h@+YLhIm+bnbzMN1G&)$PGh8{-coiZ?ENU12!mh&R0XWxQt12%r-ix%iQwuz4aGx%U z1yGHr(Mro-F+MMSJ#qPz`>~ z;CEnZrV81vtUDt(s#)3n=dElEM>ysM3uhR6Ov+n#y^fzWW*BWLhEse*Wk`#~nDxYV zTFqdj8|8Bd`x-2bhHPnDbPRKr@}4!z0li5YVP&ghYsS0am!BEWRbRDs*RwgE}aGnn7|A8Ts=D{le5=X#jsO`TjmSEp@ z$ptTCK=)=P&C?la2G#wNiV5&c1SjHeun2!rUqfQ4?fgR*w$Sy98w?h{G=aH7jbB!g zhar3pq-8H>#M+GCU+@JHel~2=&4Lu~ zQhufQmF29I$28WqbhgihU2^3Qs9+l+Bo2 zb}I5fn2WOnF|&EFj>u&W=VsJFpC|FhS@Aue$M`q1hA6SB}^)B2tY~h5+*l~pd@(-liUNa zaI)!kH$xz(zN?W|ox!w9oQ(C$h_$E#USCFtqI2PxGZc=G!tpIQiub`$%$uqGI!xH% zCM@^hB;?v*Cgf-6V95L7D9NNRWmK=hrxIs1Q$WXpAZcCq?!U%UcV5n*H)wp@rvc@0PEgjnNY_;9YquQT}m#`>X{I2!qW zB$M(gZ_r`1ACx_mfiu2H{M55?KRH5It9{mmK8-uKG6xg;fmc%A)G#IDk%JR7ep!g8 z{Y80!z?n>YNVxcKqN*H&G7M;h0no<97=$fmE%c9AgiGTwn~mH4D1i?d9bU;~K#fFc zpFk&C7bZ$Pt|A}O`1uz9wss2dX5z35YU?JQFfv$pkESa=DqYNS;k}x!z|al+F^bB6 z&LDL^Qc9?w6&!bUEA}8;X zj{3AVL$gl!JkhzYZu~D3jW_B;T4}ag?sUgy1qqr`C0NBI(zf(i8 zjbb@yqqj#Z=}y}yCgT524ROyowoyzl+9-}e;YKlW@r~lFM%d?Vk>}A=P2#4@!H0pE zHcZ_7mIyFyvGW%32(WvI$0TpP4n740@QBrI1j+()6CiOr!77yszKEEzIh4-XxEikl zE^g}Hj8#tvJX#J)1rOnGE>n0Kjz0VYBzr-g-AL|iYK5(4y!?z=Kc4A3WF^Z?kn-p3 z-wgGekIX73k1=h+s3u>s>*O)J_YiKH0N?B2`x}8K8ffGQl%TU~E5;f5^u@agg|xX? z$Sh!8q3@r}*r&*>euUY=9x8?oe34q`>q`YSb%+3^k-yB>gUlB$=MH31TaZ$5rJ(P~SfO#n6L58f3+5=_pH;DNC^_OA`hH|KOvh;N7X&Xa_yx zu3m=1O@UwC%O1sF{}?B;lHtiL(nH}cB+o(?8ih-zKAA-qkLk)6C$sqF$t?NeWEQ_X znZ>U@nMIdAnI*XJWELTFGD}G0WENfF$t(il$t(il$t(gqnI#lFnWY^#nWY^#nI$AR znWYgpnI#CG%+eU1%%V%5%%UqinMFWOX3-H-xCHIVEV|PaE)hoIYNtM#MYlbfMR#~I zi$J*jIh;_qL|#WopUk4mp3Ks2b22OPh>l^+u@n)io~X2wSw!$;mVEWeEINCi%#s@x zv6ET)HibEvMZliS5<+t_i|&}hB^W8(7!)d8;^GQ7Xl!ZYGuw?F=AB%pd?8rU=>kKh zP)eoGUYk}g4M-C6Ky@sjoX_VvC`kI+_J||2oDn_Yvk4X`~dib zok&=uJLoo`T^c>4<(b*E9VRnpPWXwUe-)} zY7cW1UVmPu$@g-VFB#lK!bJwRk2pZm=@XxqYt2E9EA!E`V+sk^*X3gw+~`<>KY=yp zu3WITzHycEKU0ISu8uDG2S%3&1#==@Fb9o`>lfoG+(x|dw_rBpz}%%P@FoLy8f%kP zh5ey!Q{33Gn~KT7h4T=(O3jqFMfm2G?E56E1s}xlFiF~t_vTe{NZ}D=p&-Sr>Gn1* zN2=t|!jlk9Sqh7xFs+#!CL~pxe zt>x*WmX|NIJipZP@`aY?ms*}*t>x*`T3&FWmM3JiypV{Nrz_O*1VSxOAk^{%sO5!% zT3$P#<+TG^UPz$jH3C{*5Y+M-LoH92*79_PTAqMtc{*ZRo}kt8bf;-~B8-;TPOatX zwpyOFllL`!Zxq z%M%VS;}Eb~UI>krr#q(Q2}W8z28CLlxVV-t3Y=+IgZYY^Hf)eJ>**8`s+i|*Imwto z5a*#gd)l}?->4NNHrUZY8(X_uwl!{_pqx|4zeTyu+_xB2*Dlxzo|hiae2J%+FL+?d zegPq{{V`(21o*TkbgYZS@aeWDyd{pb7VC%w1kn;5armaf(ql!v9RZg0$GMb#1JOgv zoSW~0yBKf((8R7tZs%4VJ@$?DOHO!>>v?9j7>|)`R?h8|h6Q*A6(8r0vk|jb{o+XqpXTyf1>$RJJ{*Xrk>C8#gm|CrVo7a7}e?N2(R& zc%5&vbGJCLr7T7hwmDKK6nSikWWZKV24oxTBABxlSo`3%)Ji*KY62JW=j?CKhDE$> zU3esPC7qwI!Oq1%uotp?=}$r7?rRvd$qckcU?5m^z5ylzn1T?4c@0)|)G;~$%bf{> zapqy68uZC{s4o~`6+$&hsO32S07{zY8+5htrI9)0y$1x<9G?x@*3`L$rv#|hr6IL( zp?jPoAQ`IL@Se9&vBTCY=ROV&hJg+4CmRgI#oY&%!%Gc+2=#KvB+*C=e$M^^EVYdI z9=yJVGLQHP9IHmc@f$e44@b>8Na7(AY7b&|`Z&MN0l^i(FB}CswnUD)4v@ER@9xpJ z!*L_fqwj;GWHf53U{swX)qzqiMM%^X%B%*}8T`4xk7+f)4k1|1s8}mOtr~NU@w!;N zfU8qgKQ%a>y0}HhiT5l_?W?N4#Jr!f-gVY{Z2oASBZiiCtBTrYUySmF>{b$HCAbz>_Y2Q@7O+3}*Y3f0QG{|W1!&GJ)e7Ib6wV&(iy z*mZnkM@#DoQ>QdqAtN#ihK0bT&pHJrpZ|#t$)B_Tqu2nb-GLW}xOt|W?|{!R((&qU zs1t$-+g7$TBl+(MzG*a?kG*`OiRTEL?=nR;28V4 zv6`G*i`shn=lRS)zN8u`s$9>0oqjEuw2WYIGA!WOo_gI!5*t=gT&-VF)UbEue#u zZDnNNKWb#iTh*P$hy4BmViBHyA?yyRak}Ee?r_k0AtMwIXN}PWdzg`5Iy>{(>){?f z5uTq$+M{SLm-RVnjyOKKd(7h|%sdc>Z7u!z72|WJ_^iQ`GivOgVmXxDg`E}6x72VM zO=+ruSSe;l1D78`iO50-+)i0St`vVgUVJkFz^bX=gVyDap8}VOi)roIsH7(m(O`AFbg#4HK zkaJS}+*VGVGi4?4{O8;-B@Z9|b8b92{o%SPwZQV9bG^C;sV7t$EX*C}b6z{UcXsoI zCoE1ZEe5OGH!YKgkV9P7y`c_YFpRmZ`)AN3)D_1+-_1CViFdU(Y;ED@Yr#03&6%iO z{_bH>%u0#JRS8)dc@#eXm=@mfS|^l)Pm7dE7k{wW(1uS|?BH+gmQ)#ZOb{M?w6~;& zp_j+d;VmiR6RBrVGq@$i6oM%1Obqt$>;!Jkq^Iei?mC6nh zK^3xmK1@G zz}%7|urn~XqzLQ@%q=Mb7X{{)6oI{gxg|y53i#k+(v_0VLHNimDf--m2;`O&fkT15 zB}MlGfxab0_mRNdk|OXV0F>sS#Puuyl;&yyUI2j7TqD3s0B{H3S^<6mKyFDfg4Y6b zONzknb2;2mPM_Ylq{e`ylxIBHy11yKa7&884kr3!-jX8vrbM5k+>)Ztp}0?Y)9EpZ z>;df;cBSx^6ayZ~@C?I#MZ)5ilxJ2i=b}@2X7%#d%(`8@oB)q-)5o)`m-7*MB4F3R zIZYkKKH`pb_#$>r)1UBYm zz*(^yNe=c-104TXxRLZYGNl50Bk4cQ)#k_oy55m8KVMr=V!{aTS zuku++T5=QrMo8bp26>(x3s4DJoiSZXHVA|?VYgRu~oXQ z8^o?EG2KL9Z|#6<+mb~20k-1XJC}BFBSPV-5+h3*WO!AH{TMTO8KbLssLAe(yl78 zArAJjg+?DdC&{)rh({+gFM{E!QUkmS<*L%J&=G^^suDr)KzLOtOiZpSvBeKEX;kX% zNkWGRp*rpm=m;T{?@oc9C4`(D66hsDa#e}pUh4x$t|}3NBmgK^l?WCHC|8vTRtYFq zl?c`fsIMv!uG28GbiX9DOvA|30|KwpFtYV!fjcyej2#wukA~%{663>FC1GufC}CX( zhOKy2iK3|}c2$WC3OIIEiJ0PV;g61CIs!-xD|$NR0JK{kX zl~RmUg`R047mH_gkh%TfE|DmQqDhZhC+^bHAD~JS0V_EXyb5>8^+@JTIFj#U{dmh( zEnU{QsQ&c&MX>=Xmb+KsHf*x+B@jZB9gC(fBP-3=+UQ4>aakv3p=HO|+9(gVHb{>( z-albhT!vL=v$a8|-rAsxTO0Dl)&{@a+K?}{Hu&Y%2ETf1gD$Vk3rjx1KGr*7i!3Ae5z(NCeeKD8se>>JWDo@8w zA{I4fwr$Xp5~q@b4^@e+*{$uHWS`U-K$KHCyB!-LOE+pE&Z!($LI%>yt&|&oR>31K zGsJKP(c7yubGM}%!{O_EJs(z1m1qX##q;J2E*h7XZ>*qJh61$y6E9V28dD@xu z6>#(C?7tc(s|IrV=zM^)$M0heX;3{j6VmS`Hge#3AC|)gQrtW1sNX(=<-$R8TDv-$ zU{|N5)6CP9(?r^i6ClZ&Wbp@&S1{?tld$~s35MRls$B$InS(nBw$L|g3Rc+9F!TJ! zF~7eOOH4yxS9#hHtf1Dap=TSv+bv#I-x?!-%Altj@+XYn4=r9*|0+iQdxM^2$kq5d zsgE4g22-7+s!ud1W@dyzOY9TWu<6F{d+@7X8Y5g5C#+S~TVj4&<9-uV^~Ev2i)^~g z&jdC6>X=_x3lm}uELS#K%o2%mPGB7#GJ$?AMM2H(zo0Mj&P8gp5B7j2lPcwHzCjnZ z3aBY}gZR^^{HhMD)nSK+`tt{b8y9dzO@jRdUIy^EOmuiR;@`(O-8pE2-UT;* z&i)yQ9M2+~v%ZabFY7U4*C4-|;l4tKdjnv|kxwwPk7J2iv*1@*G3T6wBK^T6z*Zkn zl+J<$6Y3<Kz8jIGPNt<;zbQzix|H)sMx<_Zqb2%NLB_wHB|c ze;p%##Gp;=)y_nnL#F&MaX+xzpqSrVHag92)hERKiV!x&a@F%B|GY{RQIx>?501|C;)O_S$Snx2J+ZwrNtss-vu6!>$b) zyCYm3RLRiP>$wtDA;Z{pVag*KZKCsKj+Lb=itMC&hRn!&@tSc<3DGZ zysVl~FO*>@;>=sJx@z`GCsj=zcfz>ZsOR5f<##Hz7f-5X|rhfg{Q)(cJ^&;8Eva-ePOjwzGIVqtUarq=H9*x-$@k&FK0 z`43mQx;J-jz~bjRQ^#jPs`7VxiL52a5vza9zVMpM71IA)YFH6p8CEh>abVLQ)=P(V5y+vL`UDest+@f!* zCO#nEF1%rk8E3J~{t0YE40sxm1X&nkG-FA3Q9CZMF5-E@#JT|~6sjOg%mv7JLnWF9 ztVb$US)!A15~ID%c&rzXp{N2LtVlEqSabB;$jVS+gXCyT*2<2i&KA82)*`5JsNJKL z8`mv%NM^HSC6DXLDzS6Gw~>97#eAEr>>6-4@)%^{-hPjarwsla!RKZz-O&bPuB$f7 z>obXS2OI%)fkd#fWm{7R4l%Z<#0LdkhTOHQG!l^;7D;}BAX0{hH8|~j?UY-rDYdJl1}9s_*y%H z29LuegLum!7c|PLVr!{feMNOJ_mF~Iyl;W9)g&rF4tedQ50kMMHW(4MswEL)hJ3yA zA_(#kCC*B0kdXN}kl8QF>42qQk7#3PJ_gYUSr}Cmj!lH+P|nEL z5d2va^c)=(GFgR%n{uhHk*uyWk(qK`VMS-!zQi|6(G#9BVzl z(OGmR^us7?zAC9WLFY68aeCH^PcmNVXfy=dpjQDpah7L$ORNlaEW3ags>C zZhH=kHt`g};6~AQK2&@z`ETl}7*ml0{Ykps51~Dr%lBb5Z6KY4$byyk8c*`Fp|3Ki zmq`DSM@dhorhg)hzUU+a&NEpqLxwAKm$-V5M zlYH129KGU|e8e#u&O0k0Igb0dWgEsX7`ODpAj%D|oaY`wDPeGRIcgj~yWt#wEfVUQ zT-$RK~UXy7o&z|9bha(Pw4z|vU%imy%lu*z7 z1JngBj5V_Yo;6H=nsh~_e$EQX*mrk_JcQE!V-7?UfoBJz-tIq>?PNdByLcwpPH*XX zpZq!TdQj?pY79KWL8;l&^Y$J9)(@H)C^WsYf|SP?r^dGQ5))WOIt^`$<&ke9bW#Sc zewmXX5N+GR_=>L5x7kd~Vn(K7#1d4&kp)BYdf|7@(v|icew}}RzfWO!lFf^zI0viz z2l};xn26@}TRW8hWr1D7fDQ|kAk?`P)DH@r6yK&!9{uzm5>x;bl!cZ?{yzyWo4BT( z2KTVwa)IlDg_TDH$|HnijtEo$sJW|WoAMtOxG!Ls*YqC~s91cJ|F}RUfVOUIl1zO? zFlE5BZ*OZ?{u2UM0LCE)<$qO5TuJYiZLJ%W|26R+Y7iWT`cDdKxDGN=`A_xxB5J7y zFcQJwLHS?r_ZsSHy2@g8(Nikf)9~#UPAOyKC06JD)BV^e)+SE6&r1mD2lThC#Wh#k zT*dzI61i8rxT$$FZYwB%M2T)LdrcucN9EUukDK#v=#&1)l5>&GM0U8@uyWV7_3c|% z$)Qw#l=ueOVI<;-sv0dGx!HQlW2xMdZrWmgVLP1UvD%Kw>Kwn$lc&`0%C9k4b zwm?{OpBb6+ficMSC9floIfEHZv!tjbMdfeM*|w2pg!EfV?nl5Zh8~2#(gOKmI!l-F z#tG(G^Xq5Msb7IT^4I+RC5xd`vlnY#|Dvh9#Z70mcVZJ|OG~F&vQ_?p680W9dvR-9 zFTbnA&ok8`2XFj?I;#e^AbKN*yTZ!9TD$|}y&5x?@DUwNaE%b;W=G4pwCX19rTlBf zvml#`Y)d!l1g{fZadx!&=3ig(XXLpo+c3e*tytj@dt?3$LR^&%vqdd2^o@cZiuynW zEX9>t+>L45v=S!sTDFBXag)?ijjoBeBf43LM(LO&OJVq1#A}QWpYC<5c#YGcR`#r? zvA$T!w~2SH4%yrLcJZE=eMW2B2@_3nr^__Pze5T($+iX;D3yPwAg3Cn=3+4UAwf^i zp1rxHdCN+Qo4W*4mmMal{4YsbbFwj@&D>b??-swgCSIIKXx?Hr-<5xlG|Bw9-|Y5n z+i()tzgN7LMcL^HL)|A{4KXhp=zj58m%XUHX#|sf7T#4=&IR1A^3b6`^a$+g2n+6sA?@D%+aHE|f8L2}c(ShRJ4@?!nq- zw(KkWvr2h;5aNc{+Wfht+<6bQoSP@{SjlR)jQ#n7E{NoG=(9k4ieo;p9bx}8@hyvd z<6FZ1Lh-GP_#+;4Q7JV@Rp^-(aaM^aOOu);8E|6+AQsZFxuXB5oa>l+0 zr;ctsqbq)eG1oFcaV>K&p#TJ`}DL&yq-telA`7`lvM`@56jfgf|NN?0QW22(G1q_Y1n zjKsm8)d*Xe3x~73q7@jH+U=_t#`ej5p zn3Y#eSZXgS|B##F@&4%Hw#ZzQ#irA~_f1^LS={vpmv48&UB`s+}T6HyRd0UKBWHNrtH zdWWH! z66W?IfF`X2GxTFz9W=1%ckl^`g&OU`_RJ&w!)j-{4k=^ZSfe(twqt}WR>^L#Z?_0@thV6 z9-ObVfSIoXR@cN6tO-NVg%M|G_lnbJD(9=zvOfToRMIMwI!;R|=c)BbSyvL_%u3p2 zXf->HVL!gaps*M#Kj%AAQLE;eiW-|qAeFWQ-co6Y>0qV(2oC(l@nz@u)tkPYC6Djw z?&Q5y^GTjaL|ZfNo!W15vHA;mHlaoh!074tEn05FAZ|SFF1L4Z#cSP3byBKjC?J1X z{V`eWWx?a0;Bzz!9?t=P6bl|V0v%cK_ydXFy# zM}}RDBx(#Bi>fMdN&>^-EOro;sH0nD;r4SQM1e}oWOjnAjhNA>#4L)Af-K$=PRyo9 z8S(vS9nU1KzK@#KzK@#08c3j z1y3nz2Tmz!2Tmyp2~H_$1WqXm0%sFTGzP9xy7VbUy24Y61mu(=9kEl21nntBy3NVh$uNOyQjkwA1xkx+C>k&r&6NS8gOsNLq2V&oAWNt|OTB2+z5X{Qv4 z;3-A<>Qjnz_CBT9haqF96bXl?6baZJSE(KUg;4A|?3ZS4($PK2rO=k}!5b~LmL z$EOxzI>r9lWn_C@fK1+8!u{$o@GF@E#~0uzrAOK6fL;cKpC8*1 zbUg^s6Ay8r0rn!qr*#NSN=Vub(vQbT2VG%+{U9BPBVQ*Y)+(F}k~E7nS}v z8~LE2z6H9UKWG1a814)fu6UeW@d|Q3nCA?f$65Z$#Q;|j{0a$I0_@w0cfp*mP({pM z0*>OHDd#JU97ZgQu_MkgC|P+s21IPwb3jEi8;wv7&?p*th{!l`qj25VevM2GSqeXJ z-II)TH-V;Y>svSVwD+JGg8VI!uwK~=n+<|!S%!N4FH^V&Q58?1Wl$YBs)*WlgBfbT zhG}&yv3dr+zfAMRVExk1XSTz-UB*pz{9Z<0`E&MvHW$_3$QIQUHOm1Dcg%Lk9=8(~_L%LEKQ3GW zSomX(Lk9UN;Gx1Ga~yIASYjy06ll0PlBBz@W?1`HH11r7yivXqGj6b`3LW@I+%j+cXHAa?gat3sss!^1?-^W0mt#}^( zE=OCknb?!ou+t65t<#j`nBQwkZ(l)DSY|9(Cgxq5BN4^Dj~MUQ5PFLCPI<#jGpGS| zGox(qH63Py>=@5L`K%}dyVFt#cB^3O&|vCtHDInGqHMa&L_~&z%@5|a!P{4c&l+!E zRZeNUn_ZezHPmHJ^I70YqohcZJ7*ofbD5jGw zQ9LFRebo>#>)SMu^p&GzeW1Ie3J1ss71ir_*?O$953;0?ds1_khR%aA{Ymi-=5fQd3v6yLfm}siP+U9yH`ctU!H8{6Bq?ox@R%=O-0x#nxEx(>%kuD#Q3 zuE$8OrxTW3kC9yW5SCnzm0aHeSm%0dnCn~LORgtlDYIiMPG2f#qYM?iz02#Qa{H$b ziCS5Zly^~vuZ)4t(tZ~jzfsR2f>%(&(PtsdVAUUD1xiZ`qHPYAwW59zJO?^MfO)aJ zUEelTNUYQq5{dI9;3dv7)nD|Ma@v;(tyLJoNPt4yVrfSxlmy8ur-Kgi=)}CWSWH=E( zb7XUL$X^(Waof=M`7c;C-dc0E-(Z(hdn&y6FZhr%VPi*6ce9GDbZQvpLIgh%RnWY- zldBp0q^1#(w!V>COjK+QBy}Q}8Cu%5EAz?PR{#T!RH3`IVv#?AfNj;xtq2`6zGUV~EMy!LCk&BxWh4j91 zZ%X{%Qi`hJ8pHo@mr`<3`1n!^;czL1fL%%vLbH@YcWfzzV6>DHgTkd0;^IpweHs^V z-hy+rTUs{YmL)FJZE7(msg(PH1dl9x{|@fVGrJbR38)XF7z*@=H$jt6>H;l9A>T12 zdK=M$hZ-ILsTDt%Fv`!_U#J5^ZyhUel7VZD?7}$P1bzTot1nN#hc^O+&{De9OJ0sZ^My&2GRY(un8uD!@5RomJoaiDP++>3znkc-yx?tCC~#Y?@6N_ z{NUS&p^P!u2;QNdiq4P-j)W2LG3WoU{hUH)SWuMX1%*!Etb$S~grO=Y=M*5oTqW2= zI5}rp&VnLH&V1nM@QWNT$jJfTcK{~)Xd-_>(Nwf|7Qj6EX)s_YRI`NfZJ6vn3f`#h zoLFFhxh6pb#!-%b&WQ2_MNA{l2R(S$aWq^o81Q(+Ti8#L2E0WF7G;JDVR4a@6DHQL zGzOGJ38I~u4YWB3!s3)m)(~|ClV{@n!}8`3tTZv8E?C|H38{?*MXV?K53E6bRKjOa z%tvafN_ue8VSZTUSTVpNJ{w8u zY(x=&>8OaBaVk9==0B6Aw4=r$!=xWku45aW1C}3SusI{j$q032m(P;Ik2OglGj16+ z)1tsOGvlL>3yRXh;>p$tMJt@ur42c2B;ONq0O0DyBsBpQbpk&w;7K1p-vJv=kfxse ziSr%UP}nyMsZD{0q6ZESSQ?xx))YA0VM@-tA)1q8AOfRySC_IurZXGNn9atF7y_+v zif{69Y7TPIHw&|BVw9R0%fB?>EKR^jXUF3pVvf!ro%PzO)ZDP~P^}r2GcU@mQu8C= z)N(f80?ho>X@l`+Vcd&Nu*e|L-kNqXn|gYATb||`rIr{(pgS*2siq-N(jXE7(y~?vpeaNM=x!Lq`8;I=gCWU|^$v+5$M&1t%ns2f;;@f7 z>Fk-OIpj0smVC=1Y=eRr8x>j)h>3B!v!Fey&_#=m)sr)EC+Qek4nfFkh80mCRRkJSE0My853KO% zI~@FrR@5Cllv-#zEn3iOtof1{o0M8^Ae)rM*n}-5VhAl2=ZiF%)<4Q5WlpRC*;=vY zqwl~>W*DTCK$B_5WwXkey}_0-sx4y-v9b~J-hy>koHzh zF@TZzQUQ!_a+pErrL+uAF*Oc($ABlAgbAYLQ)AHrJgIjyMv=v|gYIh6GP}|AG=y}u z8E@aSn8!>>nbxnY*!1lXC8>ufc%YKQr%2xiR`8`_K2m4dcEFGm7OS@+$xY|TKBhvb z6j330F%Y#!8EN>VKsTn=x`nZR&{uoJrK5~J()vNM4V@+#Pc3JfCDFjGR1e(BqFm_8 zFVC#liuB5lYo))grZFImRikikmaX6*<|7rHvK5>iui!NH%ZakivgO7=)Mp=E4W=LG z#cDCXcZ`M;S@CEC6Q|+)tRGE@bt6w3!s8FqbHDH!ja~L&2 zK!np5jGOda36mx(L1pR`FKYV4$*6QmGOtv`4F~*`v-x_;QxL_4NmPsl^|Y!8F@zZ? zj?bU^g$0r(vC}Cts4F!yDe)_d1{2ut?A;xV0;-4_gz~+A3JG-N4~X@yff~)h zP)xCfqeByQRk~;#tUDexZnfs*A$sI8G)hxTuwn1e>oV!zHIv8NESga3c262la06Ie zD~rHRLQ`6hW{1@;tr?#_gP(Ham0^cSeNYMEI3T7Dzzgy5looncL`7lPCLBN;tLoO{b?TGm( zqv1@6dGyxMHJ`MdBFm1+g3MMww&aKj-FGdH!`77$LDYdLEmBrOX6usY#Iv6p>0C58 zIVdk))oB%t3s_-Aqjd{nAS${rDkhsD8V$s{pV9tCh4l+l>OD@#oF_$`RHnNyd*eHd z2GX=%C~f1CIV|40k;_=h%4{3os>=A-L3)@TJ0J%^SjgCv1-;VNB(!7HHB2|kvE%dD zs6jLDQCKJ5njV|l3)qZ_NPqf9PFOz3;^aqbi*Wghvuv{(M4rix%ak0;(z%wU`@~ni z@}i)S4VhI`V5_Jw<|9?q*N!HrHNs`B;&kSv-oQwMb6Cpq667lsN~J~)g)35JrdmZ3 zmK%N)pn_{v{Uf;*N_3K|>rj&a&)IvbYTqJ_PX z?-_(sGSl?zxG;hqf~bm#%nlaaBI!ISo-fS6qT*;lI>ji#P>`OOrWIv^G&PL|-Q=V+ z8X!)N5b@3_qBx!+v-~%zQL8I)^G{T0C{2Y;tu!@*ExR0Lz--;OawJSR^vShjuRc-V z;MglK-mQ+ZDjgp_^^FgoilTV1wV}siT%Qj6Z+z|)>u7pFWxHT`%ty*rVY}cvtW}4+ z(|Z~@5Ug!_Bzq3-)>_F%uqtXQf`b9Zh^sBLk`0H%`q9vcp@+d~y4`R~j)jX@ykGz> zUtkFaYt`BTo@bQkDK;}&e2$KoiV}s(*BNV|M-i}*AQkZn(Ha-Ie!NMO>8!&&jhIl4 z7QQUUWowSp+!G2paF5M4WpN)p=7e6>SiAn7AC(Tum;w$9T^Wl$eXWQniu$in!kB=^ zYMd)ws6p16S?EF?Vx8+4Egv6up>5;iE`a@QV=+pO#!Vv*h)ECO&VgF04Ps8y83qkI zIIY3ZgQE6%_mbeeduk~WMI{#-n|O@XnZ1ucI66!NL%WNlL2PLI_>5EQoxV}$Oj{#>42gOo7$NGkP_Ypc8Rdw@7`-Zr_^Kkcgj* zsL;B2Sd63N(n71{nyAAtcO&CzXklSx6MUgu!^U8GDDr(NMOybeAK^9;7EHiW$=C_@Y(dN29cj_?Q~KX!~~ ze7V<)&YlpcwP_SUOh{*7 z?i}H*J;vV_ZVW~|{og2Ct&+^rN;2a0kcEY(kIL=B+_{#yu@M-JeJy+2Z6h=SrY%~> z7W7{E17D;ud^v5yh_;T~jOwB1hL(+808m{! zTHD&XwG%}E1TPKpCEM<<4I04FU^%daN@(h6)i^xpN$a?`iL+?g}EnNhrB6qT^~Nk#_P_tajl@FVeH_4Y(Yx-6mlTU@gg21$Dxe-kZwtQm;GS ztIlcXdb`GLdg`gCz0aNZeAlK;R|l^K%hr0S!`{|z?^n+AJr4)#zV3bYykPI6-jAK` zgWh%LxkH?VyMp?U1$TJU4*$aI6I3N!@B3ab4hrhl555lIrQ~UF-?D3*x3hb~Wk5Wi zJRgW_cAf8KH+VhWUe35f*B$)QM_zeoO|W_GLu>!#Y1p@OAM$dZ_j*o4gii(w7wp(^ zA&uT8Ur)ArKT_SnsVAM%bKz4@1*1N<&%1JWcjG^|Yzk^OZ2rhqcY@6Ewgh{h9?PJwIphK)Uq8(|;|kfzeD z1}cVV*F@9Vp}NPmww*#Ew&0O|b>i|y;!@Ahir|QwgWSTSV7~GA7MiwSFwSf1KFQ17 z=yf-&^ERTzf_>fqV9UpOo4UQ72R`8qnC`7<@CJ=r<>fYbn;L=-U$FKw-q%#n*IV2W zT=hdQwb46goOjmwYtFcEE&t6pW3AWK;0^A6Bsh3!uy9e=hqtfs%7O!4SI`hFWEK2;%zT9!n>Zo&Tbu(0z81%p6t{zzMWknXe zVfSr!{ybRxA6+|Yzjs5hXM1oa1Pt)o4tsrXyXwQi#D*Db&J3RZ=+tX~_Po1x2M5IQ zEtr{m-w$qf*OhtMhi7bBbB5QA?lIllb((ih_v{_s_69F!`ulfwUK&jFRs_#q<&EFF zFu3rH8Mg<6r!CwZJh<}xCriUZiTd-y1 zOtkr{or^AbbD}Ow&+m38I^OS9x0mnMI^Nlby^D9FlWsY~#Zg;ffJ*(WMj+kCBuCd4Ap0 z_x*0{__Ms7_YsuqLu=No@p>8-UcldSZ`b(?FWNcr%DRyY7w)@s`vu-Z zyI=N-&cBR(0j%F=uh+Hlb8Ft`?K*Hb{&}hC-i~o~3wL@guX{Ngy`GIzXRYyeH2}Ze z>lx?eoOV*~w~UiWqd(_aZ5 zTKI}P1Wa@)7|c~Z{vNG&ya#26-f(=BD@@75UU(}lSfDg%>JHj9RCjQP-4E`V>VuqM zSKBkh^eMasJ@cXYYiqB1uxriQudZEt`YCJ9=;8k}Q2AcY;a@ELoe1(gslq1^__$Z0 z+SJ^<4c5Zmxeg+sl~EzAf@MQZ6%;#*Umbt*;*F`P-1$E)7|9qPo`Rj*m?{VB^Sn)kDaWrC!kDAcVAsfLB zvwm_f7M0zbk(#6m&U~9Hcn?`(VK6M*x&b%o_#_50po;LvRlooHCi0#J*6*=}qI$-C zA=uA-XTI&-UkirSp#re7U*HrMx>;a9R1~UZE&l!;JEYpMbt|v)nW{%Gsj>+dImNDr zv_?pCeD&{}?t5zvwW+JItEYq3n{6?5BEuH*LmdugIO^c)8usOXptY?Kt3N zci(>drl*1#UQ5I6ZUL(5zo&aN;`WDm>6_hyeZ*Cd|3kC~-m*b^82%1tdhgI0u|}g< zE*MeAQYr5e$64l;?+wPR^{(H2+m;76ul4d8yq(YY{L=-aF88_)dnM0%rH=6Ae@{g> z)5dQ&l~tZp^ux&7-?78JN5Y#rx2i;jG9>8drGHf@>_ z%q-eocv)~}aJ5(2?auD!wFKus+~ei!?YS8L@hby?9>n0Pzqibv4U?f8J0{ddf~R0) z9W$%Elv5^+{7nF^`V#*B1Jpm(25<$dWh)HtbiH#!u+D33dCIXcbc*Ys6lG`*SCxRT zj(>^b&m!moZHIwkS*bxT(*{z<60Nb${0@Ut%a55;LNjSJoLXmV?Yo$QpSsbT+2EZT zRILqO2`=(}se;omO*)K8KsUa7gGCnvCw=LHX*0G2n=UxG;gr)C1=|+B;SMeHz7B%a zUT?=??{k>=4D4?4dY<=o1c$v#+@Nnz<`o~nl=`%TYdlQnHhMQW&(HWGoQK=Il8u{! z3%u;Ti!uG*=;a<>&AIIPCL=do9^wLJ_pz*y(Ref;(0GWe6H6Mj00VY9bdWDC*d(R7=?Ce?K zecCzfa`EuLN2KlS-q{_~9dC+A&Q_D-Ybzc?$sTV2v?sgS%IAKd~DN4Ie6 zx8tzFVc5;Snu%Gkv(!DY9&hcb}4M_%U5j2i~e7G-vVD(Rpotd zZY`lLAwq$w9So(Ef+eI-N@0p7eL!1UxOudsP`pW#n>03$OCEhdg$e~3MGabJP#F>( zRMes!WRy`H>rk~IkB%P$sHhzUWgMKZQyD=A*IxT^&OPVh^3kE1TR)oKvLZdXdFXve75g@~U6HO_k?z0qxj(;P?wKne-rPU1 zs`JeB;Pr6!y7gzJ-?}2*_3ZaIU7ntdembxsUD^CFHWhYc(?iduPcL7%Hr;h7ea@5V zi}$6gp8WCy7q9+6|2-q=z9-R`*!D}m<<4}+VA<*LbBh_X-snj>Jf@%CfyaXP7#Z#O z`v!L6pm03kXL3Z^bo7+6;PE$B+Bj!H*xJXNoOJj-+!RreR^0xh_I|!u8`Db6IyRkg z^J#yZzN&g!`pCiZn@`wu>+;`yea2wAabfy`!E}CCx^f|QY!|Kq zN%@Rr>&mx0j$N)5X4JWQA;5*{$AasBlfHOGdclhHvW|CMRxX^<^O|eZs}7~lUib() z@{07+7^LpLu39$c(^r=-y!6(ur0)Rw1r)a|1h_E$N^pI;@6f8vmzD3tWccb8%bFm$ zY{sD^>6=s6m!HvDJ}Z3)$lHL#9fL#HE=+$ig+1d#>Fr>7eQE`& zK##H+$BQDb1`lqP!MO4|m5a7b}_fVzn(5g+H>0e&E0=8Wu#JAx^M$;Fj zuR4^Tbm(FzVY1ZV#La83E-Oa_e#&e_V|w#OMWej7b)0)`yg6X@5sFS{+#Li&LCLX# z``Mu5{R9K*jUvF&xr|9f=hdRCU=}-)O8v!|XvlNUOm|eTJ>!D%E3QhvZN*2+Z=Cba zFO|=!JNN8O?@Vv*_+HhdA5zNNpHd3orTzwE`Mk(7M7Ec!@rFns5rDf zy=gFAc_^K4PFIvyuRQKk``c|?j6%a1YC=}mV&l)fCdCFUMV zpLYE{BM)_^2L^YVOHWS3j`o#MYZ4|@3(-^Vxy|73ocPecetGnLL+RGx^xQksD~HoZ zK6@KBjZaURrSeJTD_%Oc{L&u8kRjhU@oDU2Z`ysvJ!huhQois5u)6_E>Y?0F@9pJN zp=)GV6U*O;f%6#I&rg*P$=}OvO~2jj@28;i#K+R74&ReL37g)xek1+d zwdGafxbokYpLtWd`Va={+*6moh*jm09dPOU5zarm7FmAgp^?iv(>>LHn?B`w!+08o zP#fK{!(X;<;>d{E9Guu8mnXjZmt`}jrcY^pD&1mjC?A}7Yr3+0&|F2~;nDI9xu;BN zg}D2D)~CZ0(Kek%Ys>&1da6^Hr&rvWK4Dk+P0MQ1Ex4ofgJ9P^-$+j$9QtB<)z{Ns zL6?0rSeQQT(8akk%a64zQT6Hfb*48Ck3N*1T6RV%{pIUW@#>C?2ZpxZ`f&Qsp2P&9 z{K@pB6*7NCgp_YcAK8q*W)0Vgh%5_Q@%IfHGE66x!5gch@XbOpUdXpH%Yy0n`$mcy z*MRYVdtV&e=tW-jVTT~>+LgH39Z4-nl5QHRJMvW*)xurK6cwqd=}mIS_vvzcFf9Fr z&3Br`qPh4#fBv8Kz*K1V8V)S%w^U6zqI^`MABW)0q0b2@I+#PW;_LLnl8TzLdnQ$s z*G(?Vo0HN_*K^C8YYntq%S$S1%a&A>2kW%FTd!A}xC(+r6_p<eMHTx~>35e+s#s9>U`0*c-iq0E->Imo`)5}Og~$6r%~4lTc>@fq>DKGK z8GmYM*GI&z52qJZRDEc|qKetKh+Q{{T{j+4S5dp8ysl!|4M$#7aWIwsx74JHWw5Xo z7A}B=HL!3tEUbcs(-u7jOCJ}Hi{N5<&cwBS(33Z*YlRpG^xRQaS268|G+F{>X$PU> zUF$VXS_0`OQm;mD zTjD7^bD)bfN&hP*PwH()J>Kp#KQ#sp_3~0r^pWes%6GNl8nd^rz`*6!K#?c)4r)D- zBS$ek1YiCp*q}FCG<-_Z%TGky4JgCCIDg3#8$i#SIZrA*;`0{icQ;ADyHWbx4#^WY zOk7ft@0o;5@F2R{Ui823phdrnOz=oW`C^lM6ECrOO+OTQm9uJ%r2kTRjJF*k?}iDB zkD6#N6!XhWT*hm61K#&IQ~98M8j$~2Ouj@~$;PG7)t*{wD7wtwSUcqk+G+9R!dA1% z4Ru5h;j>%$XgV$04$`iBK+k&ybt)Gs?pEQn3 zJM9B~t@3HLY$ACf1Kc{L+pTn2%^zds$>CJlA4}#zmDi;FE8kITFuyO%bN+aEql||; zWIV(I|EP%#lOC+wTlbwsk1Tq0(PMSropQv2WwtvP^|xt9L?E|DZ&!N|pJiNe3a-TeJ*dC?%vvc1jDr&WGILFlez_F7&I1qOH(FCG?1H~l zeGpe>zEC!(`SZfb=nZBlG<~*Md@KQv(IfHYv9oH0o!L&4Gy8FLyv~$eR%B!rJB3gD zd-mXSqvRjW2gvXkVXKgJrXlN8BI`)Dxip4C{EMB!FaB+L+KJ>~j9WIj>_P=iW@f$k z7u{K}Q;8w6*0`B$z_*E zeTZMKDgR)8Eg*d8!TdGj+&UACW#EfwU18H{ApKeN8C81u?13CIo`P^0reG%TlJ5bf z`=BKgI^`?m7khl;U+w~ZGYFSVULEBd|G<``Grg;B@=Dd0dc;3T73yK_+p6@^4oP{e z3HaeDXb0Vyl4nNcD4n0m{$^5<^#MZF9Fix5Z~TiGUi)UshT?4}47#;``~wrv>#*ke zODcv_>B|m(o=|aK}cwJhll-27+vB&p>BZo@5R1OO>ucyq>p5CE{y%;rEwAF^lb2myN~v#BIT+ zzAcTZrbHIwf23PKvw3O9((v2d#x~D|mc#PcN4}jl_+afoQ0k-G(eHHgyX=MEb;f&$ zbLP8h4LN+0q&-OZFm)E+Ucv{xH|6XHn}+go9?S*C2d3TF;s#UX)81gx*4LiP=KIWJ zg+bw$r!Vuqylsq%@RqQ^cXql4x0;s12UPktcIEU388%epHvrxEptbq+MIfaC#BI(N z2R8I=#$$RN`1wY*wHNPbH^1c2do%W{7ZzoC;ieoq38EfsY%LWPWZU7X0z=}4WwUsC z(LNrHXiIio-0RD_IyYqG6ISh;8*;4!_{!Y|G{iFK*_{izO*iV_lxqjS9<#aKw6d|S zwYz&gLe%z`!j6sCCHJk*b`166a{?DdzvelBuDiUqqc7OR&k&F!2(??=@1zzoDfOvX z)5Fozhdfz*-R*pmB8Yx!*L((baUWiWy=73tE=r)^;*ERBC6v6X8Z;q8A-m+z>+q?^ z{3T8L?c>FG#I>~zy}4^(u&Zq#$cO1=O;`UQKHsE$Fz6yHNeG)lzaU)jB*yZ>@?h4k2sJPT$#A>C3{IrpHJ%fzbln2k{ zpu9w)Z>i+Hx=1VwYDNg3rz?LbdcH1xAJemtS?=LqvU;?D72&58mkJtws^H5Zir^m< z^`>A;F!$7v!x8$d>YvuCNs7I!H0D$7&^Hw{k@ZDt4^W{Y7GkZ_3pf+*aGqH+OF58Z zDp*5sWr4E@f5Hh|^Cbo8Q`C&>KZe6a|0cd{V)>cy*u(Dj2XQCOs9b_G@wH(N$)xA+0T@6aH((rGmyd zrz8)tNm(61Pmmr#1I0Ok$|I$OP5qz7XCIt9^)d)-HUhD`BkAgow`+BlJ z#<5>RkPL-=eFA&0qgJgIgcDmW5ePVum2u8@jlFUuo0))&*GRCS~z($cmbt>6FiODtK*(dP>0`hA8^) z#Sj(OfH&sqU6?iy-0o0bXRSKE)-YP2XAEHkf9+6B1b?F_+c8+0e1heHv`g^K4pmR^ z7)9B-aqX$c1x{!^!GCk8)dVTo_8^v~IH9Wv77DHR#&ln3Gljn3gsve-F|E>VPfp=$ zcKCPlb{;^~7nIJJoeGXWcJASmg7T!AYEx^3qK}AV?K3IVQL_q>B54+Fb2OnhB0NR6RkOCB`;;Q9)h< zuHssPUvj9`1gV_xT06oLC13#*S2e3VsGkHK;hXi^#2_DB6-@V3i_?{Xj&SI!dq(%L#*Nm-m54Za4dc2ZH|!OKPk!*vh>V!M@aB_ zMOi|YUJeNfF8MQC*AlX{TCvcP;HC&6OP>h|34SX=$kP7`2?-v3Vxef3PF5^L6U;^k zS?UN034S0#$kGELA;BL;2w6H15)wQ?pRBU(Vd+H0LPvtwoR~~L9kv?vW#SC*16DJcaFx?au-|c z2xb%|HAfZxTu8>KoZ~`c9pmqk5XDGivqLjBEZYqz-|BTSqXXaSW?FrZ>ym2-(o$*o zW@q<4XZIR{?1Yw(rJp%7*AS$+mXM{enYAb1VhKJrei2tx7(S2vM<=U+;HRo;jk53=!9OU<&M{be z^9)Bwuuf5yFo+!#TJ9v&6MWgBRuiNc;Z;Av((g~IHCz#O1nXv4lqED*3;s}Og_F=s z@b?b2h9JcVuVyE-Zbq%)m~gk~Wp&``%FCn*78W}J^-C1|szYVIrr`4-isH-FO2dtX zL1%jXW(Bu7REFS>3ahg4laP+!&mF3sAk9oncPFTpv<;b=;7iVcCK`}-+%p6z1*=nn zzY3`c{?4Ji)S1^yw6rX!^-@?)X}TSo3_-eYZZJ@Z_3Si^mnZ-6h!B1)T?m&~&8)GT zrRUA^r0i1efA6F;6MRZhM+5`YcTPC}l%jPXa&lpnbf^Y`=Q>m)!Al&ff#4>G@=~-B zi$6yz01XJ{9IBDvZHlsHvh>-Ikl^Pcgj#SXvg>jcGX!@!R3kx(L2qyz6xglj`(3RD zf)6Rms;UKd;#~DIS208I3WsXkrr-{T$`A~d@?1(rv=T|4;09%s4hF6pVPTWw?y;i5 z&5mRp!4^eL!6y3@dEE7_+pv8^ECn9tuI82MR3YQ#9%T}e4HlB|@)jjK(Q$KRn+oZN zmF`|WBMlM!nxc*j();UcO@XK{08!kE#i0QM+I1sPLREqVl>n_6%a6zilZhuv6>dVVmYXwWcsa92q1mCbU*CLjeRK!9Q1&tbqvEDXw&9 zBQ-i3!NQ7ubWjUYr-C+utawE5+X?@9>|H6(0e;=~#JW=x>Sna^6?%sC1lK7l+0quh zx;v~$keSj}WNBr}QbK}Oai`lAI;3Z5C8a)6&uG-3uhv{2Ax_?bAP27Hd5yR^;k9MF zM%=>iS{1JmM=ingv%F@d_J`DN#>wo2%7CkdhI_1SwXOs2^d8l0ir?RHA8YPc(l@Y2NFUSWS?U zkw*wptSHg!ln5nq7Ul%sq!7iR#R&E|iH&4S6F@~Ui<%-EM6_j}Q=vX?i;y`U3LIT#f#dX?FcJQtUiw)`LJ%F&9B3DU zM=DBgmJvQ)aYqFM!OjVsQO@{{qK}*4xDcGKs8|g?IJzRNL9jl##ubY04Quo%_@NL* zaHpbTVy$}N-$wPs!=Xp$B>7~39Eh9GDY)06G6bJgR7Ef_p}-*{#Q!k7zOC>&@jrJg z8|cI;XH5gWv^qr54eLV`L3$>x3*B^kSmgl)_c;`Y4r?_2-l#6wF z4>?v|r((UC&e%p8duQ=lj00MnG(CyaV9U=Lpa4kAKTRKHF2D+?BQ-78L$Ac-Ue zkrS81NMd+kj3D?66>erlEYM8}Go7C*JxR-gd7jd7nuHxBb(|)_ zJtQfJ@3vq8NhB!<__(Cg)q5*klh=$8W+P!uNJSXr3Cl!sUZeo>1wpRe z?HJDzXZ0W?_<+{6ge?7Y$dTYn5ki*u8wYSC$lpj0$P*`))Fi< zZf$~bYm%>Fg$iCCqG(ZPi0W4G>JUYHhC`GJ zawoQ2QY(E#sl;T$cRAc#*Gg1b=m>K)D6VFoDdoa1sEW_%S$Msm@F_au5gg%L6qhgn zkfhd;WUf$fV~BDdP~ct_cE6s{h6MlBq1I5PQ2d%WqhXaX;$$@toTP&rW)B1>D@w9U z!w5_BLqdWJ9IAmJe-UTvvQ$@m2KQ@K={2WXrc>E&bL=zsD)_w+^^AfCL)7mStZ?Eo zQx%*MqGl^NKSag-b(<=~WsbBm;Ww!ebKi~5d9NacknnYdge>eUASC=~At4J#t9HVX zFpV*ySva|XkT6X&geAMWilE zzYYl%awlK4da8DdtJOr1%7|+9BP`wK2jASW!KA{eUBKoz>33Jq};P|+Et0LRa-gtZ9%gQBdj zSmI6-^dk6HO>>rzCH{mLgaqFeA!O+y#e$IFr4d4wnnFT?mq!R$Y7Yqsz9&LBwioJ? zyih;ld!atb3-u$u7wVI|P(MO1taLip6Qtd?pRq*Ku}C3EyDcG0G#!Kl3%%ekQv6tG zPVz!?f)|>TywIHBh2|tLG$(kWImrvnBfb}!lf2M8;(MVv$qW8!=75HMI5leccSZfq zb&^JcuR4@>bAk*=nlK144v$a(U4Y=*6=gdW33;wkV6L7~k>FX1dV?$0DqAiHq_-;S z#*z|A#Zdtj39{lbGDAFh;m!$o0H?fa778=GA)T4)1{Ic&%P6T`Ns=<|uwJ{u?Axa~12Au{*t>&^sJSBSG>`a7~Q(A%d=+(b)5}M;AT)Q&yz?S=!n!FRti!)9# zuTm52X)e(=%vErKL)8;ptte|TOP>r0@9kU3pBZT6FW{Xz$j=L9`ljx6!^P=b;7DVy&*2@M2Ut0K6@ zrLt=RKa)}Ru_}9Fa1CyI%@|>Msp1pj{Oc-}#(;z%xmHG{pFEu674khbBWE~y; z{Rdxic+o;6p+69(1gYd$uHm|z^oZbMQhuxoC4~^{tW^M-5d4awY=g6Oe@Mu>@$>PH zq@Eymy|7LsNQT0`euSlvJx9Jc_kj8#Xih)pr~~4-s`-f zmE$G_CIlWysGE45FrNdM7`!(a#4jRQrtETyKRGo*47Fj6xHo7>w_Xrwgt?|gn-ct} zGp_$S_iPij09~B@n-%dTJ>v;)f^)an(-ZveZHpbNeC~1lRue4bhj%p8C-GaY z)!Zp=K5jeF`s9TWQEawkLq>VB$Yyqe(I4wWG|&!OrGzSE)B(bzED zJ=1(~Ysi}$GKfB(k>~S2Q?XP7))NdFts}U^DOvCH_EO9qrGClPY9M$)%HlAWCs?Z} zn^CliJN-tX1+HR~yQTn1C<75oFs#)WuSK!kUO+8^zt#byEVwmZD`2&Lr%ye>f@u39s}zj4!&cN4s?U|P~V!qOi@LV_DKiQ5#%5@!IZ;N1kj79nKmw~7TJ!SAW< zmLp3)c0=mB3DR0iIJUiOX)i0nyVK&;u2lDY(V4o2*0Wl|&q+S3wF>6E1i$M1y_z7s zgm?dpUdO^_=ZOqK3N&k#Q+@VXHec7}A+>%|Ziw}x(~6p{E&C10awxm!ciXoS$kV@YuFuo2u?GR+=2 zb$uYzm1eS_3$(2tVd^yf8PQCT%!RC& z(@t?tTT8H@nwOp?sFb%jX&HjE6@_GL-OU1%K#JjlWRvV2HXxMXh%t!ELUF*G3m+jgKoxci`=OXLx;h zRJHg=Jxf0){G8%o`*M{<*-7c(fXaKtsn9^MY>IV&?GkbK_!aAuD*C&%e#Pdbiv9*? zrRsCKp3&_I)|6D$uUMZ{(O1>4*ql`Ha8zBJRMCHGgNCdKZ6uf}X`^4UKB=N_qhGN( zsiJSAUvX_xMc+ndg|})*p&jGF6(^Ag-alV!sJzY)ulxURd8(?;1@e9^SLuZ0Y&~-y zGj1tg27A1Yk2QK8)$?vW|5VTM`Y$X0Kj?X?&Ib72*f@RsMXvF8pT_A=URG;Rr|bD6 zdj3m2e^Jl7^?a|M`F>8mob#OJme09*=363RCC-^c5{=_}bKmP8CvFND>Un_9h+pKxN>Nx#FF?v2nU5x%emHuTt^SPgCY7d`|=0nzTc~>djpq}5a=V3kX z)HD4buRm5h#pyqzd6J9XjJ8vYp5yd;l%DsTNyod}ar)0FVwax3tmm)lnd8ILT8^LQ zsk}eeGrtcSzdN>8ugB|idD^Pi`DEigTBbb@7ODS);(x4XE^|3f9aKEWow$6CKW|fi zp2U8jXWj-ouZX|zQapDx?$Pq!>6!g%Uy=IHD*oT}d{EE4i^cv_uJIbzpZ%*+ud{z$ zS%iLv;ywi$K5JdyOwAaz-Vd7EF=!+&%g`L^^EHt* zhR1#inyN84%S`9s7<^6!&4Cg$^1-S89NyCr(QpxJZ68B=GidT-(DZ_4bPO697ly~6 z`2=VVz=;w+a14%Jz&vX(;@RqMe9owSbMT782+dbPQ;EGeTMIP!I#mCld?5l2?P}r6 zhz=vQzJpr($I$2BM4u8g)$#!$VTMCwrBm|hiB+b|Kh^E6gRNQ+o6;$XlIT&reqewY z6F;e$EV^^`mXHyIfX@c}o#d_yP@NBHL`pif41W<8u_KL(l5OOFJd2X_D9}`mLBmHj zB&yP>2TlnB&hE%12>3YrQHDk&`^Q|x%Dv%qN@ljU^$RH%DvfOMrBgNd>(gAUG-7c& zbpU_;W3AFu;8Hpzvl(f*=#f(z8GF(x&X}S!dC=rtRzE#@QA^h-pQ8<*DhLu!g$KvV zYk<0>Xo_Dt6mg4X+VmtV#>mSml-Q%vjw36vROme-ltZqp`XSC~;HT#Juh`D_M1a z7|&=Z(9F;)(UY{rXov{X_wZd7-hFo`EYVA=UCe2bLuL@1& z0_GnneOp?`=_5W4n@IeM&v%*rUIo~;DO<r!|QG`HYv zWy#p@A1{Jt3(%!xNk)=9WHd>wK{(ZUj3gsT9548v~Ki}j3jxe66kblW%Qz!q!;XW zQCB=8NglEp>2B0SrGkU~;>W<*ej#5mlqr2-&wvhSsMcqxmes zsD0^R{ZL2sIrHYv6(5>RB9(&kK$D4JmPsw#zY6&@3QYvl0n8`{Lle)2Pd_kn^D(To z9hes9ABpF%>FM#m0?k1~ZU@~Yvi(x;tc1c^TK^To1iTvaGDJ?bY6kfGwKa2W( z!eu{bVC+iCcd-5Ao49V z#^30{oG=Wu<+BWsM1S;glv z4%ZD$@qW4wTG)QN41z>zc(9+o0+j8i_(E>4d`C9gPhWulWQK2|*Yk|!_j}M(mYC(@ z^Oo{`TC=8(_5#aUEPV*9VjAkuT?47&r=%>wUeJQ;CIcjB$f%RmxQ#mTZS-K&Jq@%t zH=RNt7>-doiMpR$$f)}Zh~(|NkWQlRO!PAwb$qrxye^PL-8bLPsN?fuQ5uQ5-9VL^ zuS!JSf#|gnwHOxq4v>gi?;>hWREU-&qG}E!qAEdWBPx%YC=?uws1u=rji}DHHksZ; z11dNkUX!^^v53l7pLf>W1@i;f?ncIJ)EZ_jgE=3V?dWc{7x>v2--R`EtAmkRm!Vb* z>f?l(%*Iw9X?NNCfkO)pW@D#MY}ZIg{Wy&J#?a{cYnqEgiLvOxI6Mfna7dcdN)3s_ zj#Z4qyEVtjmGF=_{5VE58;2s*KO_$Ct705}&L;py;_v{@W5wam&;&LPkAW;-oWxkm zVZ_*W(AgNf8B(R4!h*p$9eSy;7{{y+j`Z>w6Advq4 zVb|aN7!z^Q7Q-dlf_`2C6|A2(cXhY7wf47<&(9g~v3`c&*ztP&yrh|a{wBCc&yODB z=S7&hTR$g{jN)hM%VYWZMf4r(=Uh~Xmc)m94#S5n&WCOIrgKm0me7TUQyYTI#%fh^ ztm+<77|)WQz_j3CjuKgi@8^WJ&>SWHv14Tdjjp?=f<~?;&h!>HG|g;YzIZmSOK&K) zM_P@ZMp?DQ6Y9nn^qkUeSuG>l5>Kz>4L*((@%rF&TR&=14H>dKCxcV ztie@qa7~Fe71eGA&3^E)?G+s>7)hg`IWPvzgP^H|U3Nw-oSy_{JI*+1Zj`4tTVPj+ z`2)aFxXXCM&3~-U;vcz7eIn|I$M|Awi-b|+V2sIqR2ySek?T_6{6~Ioizb0SGJc8n z;lWj{vm#ZAi}YMbCvkXFmT`D9Z04^{LK=y~^IRPAhvMONfn<(!#Yvna$x{ya7ds?Y zcLP0EtUm8zRetsB^O3RpvuGNzD4lvsOo}Z^JZBCgo;SF7z8@7)so-Fax(_PYc+U3b zHuvdCfvUe)yzDqm+kd+ktpcMA?R3bs{=u$XL+O*QO zsYGn_V1I9he{6r3z8pQ+-({XD5t_8#sWx+ol}nc4y0I&1{bgwu*OsEuUF+Rwbcw8_ zIf<3ErKxKMF4U)h0AMvjK`>SLFI#Tu)NK3}3&TV0x;z6^Q9jnLx&@_Z zAZzC3mm8g}Ea4VCM4y>;b#;O*MkCjx5AJh)@bA#N?+|q4kUm)N`rt>=a{eJXv*Kjt z%(Za0PbN82f_lmCQ6Vxz{zMinUhc9$H!4UIKc4nI($-Pxw{ zRtejtJ-Pn=cm~IKi!5r}6#3a##aPe*8rNP1GYCv2TxMrz*p3?90Pa-|<44O%@D_W* zN<#+pUM2kF^Ggc<~7Z)u@K$b5~GRYyAN&Gv` zB1b;DX?*ZfU zl4$uHW<+Dn{k9)QBs`D&WAnyV$nqmWT3O~}W3{s61>4G!Jt4T@U@K=`E6al!o3rv% zK(2qlHT4I;|$M{;=_c~{Bx4TwOm|f_OkkAN+q*a@! zC#`(vwQS|Dq2%{vY2|-%t^C=TRkmnWTZhrgt;j95m4ASW$*r6}j8@+6T6r1xh=t+7 zR{nr%<@`WysJ-uu{#7PeE!&lo3i2nVWH!)8?O- zqMco-WwiSEY>rm7@Th-C^d1-^dgZB)?Jyk80i9(gIJVSelm>k z68j0i`xx8wevw$9u?3|~doe#8YfO>fE{wIGa4C|oZHt^IM-bxY{U!WNAAZ~U5YO;s zH?;P)cjpSHq-}_*O5?-gbJ6#LW;gCHhkJt`17-s~X7u|sFp}A%C9P+62_{1GRbWP| z$cGugN|zR_gH6$0wb#>vEtHiSh0W1}z58i|ik)3Rjo887{RC*B2=tkWzp}m!4`z}| zj0Iw4It7yx4#@yt+R121VGnniMM}+zvIRk0$zApCt}`XnS)g$wK18 zw||8`oC1zO#18S{rw_x2^6TQUM(VB3hrKZ=wkSRvJ`5k$Iv?h-RBtN`L&NBO@T&D; zRib}{=#!v1II}R1eF>P#QwlNP1g0f|`2jGJ%);^ge*-fb!5lFO^UMh5t-$0@Ev$7q zFuNm|i-5_@CXF8nE8rUu9vKlKoNL#3;ss$ zR|=^_)I08DMEwVn*Hwa!91>BFxQKdpVrb3<%@=B!MK4R7I!G4X@1ibwG?y$Y_eyLQ zEk2+Bm5aU7(izz)YI)Y^|QkW%~(6hly6TQ%xx<-1$ka-be&rVUzq)^~LRvzv3;ptlcC zlK`{bVNeJ@13tA8%)P)Ih+yO;P?_pN4Ic-_^<`lbJO|7UCtWZHfw?(?c@>x{+9f1G zInr>8lVyDfea^A6tgXj_CLh7P9hhNB9 zZ2oC4;9x=KpHa{tjI<9P7op>dql&htW<-@yYROU4zsDSv2K5Ice54>b>U1oy?9AZ_ z21tZXa+FL;!2tUFQYHu9AvsDEhI2tvJV(inh0RfUkB1;+266=Un(PeZGYDeeG|5r& z8w{JH-j&El`k?Gy+Fo#aB8}vzVYIf*Q3oL?Y8w0LPe5m9GIoDeZ?l;0%J|uBB1&xc zMKOM4k4PL`>i3nU;zu}}natB{(Xy#&uvDZmmv|)QCrM8FF;-dGw&9-G=iCb zJmvt3(ae88TjzC2Z}Oze?|dV&=I!vLPw}Mh8JF~oC;b^u`ZiB`nJ0bUxTLT2q(9+F zAM~WZjNTpf{QhxCU*<`F#FH*rG}0FHU+|Jn4Hq>Fu8MpL@~|j7xg0C;b6W z`Z`bg)1LI_$0dECC;dK8dXp#pF;DuzaYGBq*h^6!9dD8Fpq*snh z`fN}7EuQo_p7c9C>C?s~eWoXUhbLXuj1h0l-|0!O8kh7cPx>}b`gBkF2R!Ms$0dEb zCw08Dn{Y6juOi%h=Px@?6`u1^2Kj=xH?n!^ZlRn*(e)G7bzu-xq>Pf%P zlRnjxK0Gez&wJ9Rc+z)y(x-URZy%TRXFcf?Jn46N(#t&QqvMi(z?1$8mh6%KHSZ2j z`pY0t8ePNQJud0bc+y|=r0?{kAM~W}9+&i|J?Sra(r@vkKkG@qe_Ya^@T5QMNtazm z^|Q@~^MCXPN#E~DmrqGYWX;>=Ntfrblt$Zq&$w)V#FPGnCwGyilpB|U=J)ZOjJn8E^>34b34~$Ft1DCQte&-XQ7sd(!3Ycv0yqJ?S@j(w`rf?e}@o@A9NC@ubT$^s1ruxP#-8zT1<2 zhbMiZC%xU1{_?n_@A9PY^rX-8q_6R$%flcblO5OBv3GH|C;b*r`W#RCiZ@95U7mD# zlcTn&_V<~d^z%LG<>Rt_)RVr=lRn*(KF5<@IWFmUc+v+w=~F%FGu|NSw|mmNJ?T?C z>61d~`X=62F&_(`75S>%l!zQPz*HIkR3+YF(PtQg@D74hZz`yTWju}nU~0(6VE(EA zQ|6xSv9iz$Qn(dm?%5b(^T+EK3BL~Z?*?Kr89Vqi!hWb`?*=B&=yUHcf(9;vKDe!H zo^OaUleXf00n^ zPM_R4Istc}?42Wd54z7s?i_6|apy?H${o7xU}EpkEdvIKf`fPHCc}X?emYt=<_ZV^ zZs=|85mXq59fKQ&dN<;o4`Hlo=C5TR^wo9wP@ZLwXiB`(r_Up8N53fg6pGDAXUX#r z=m_8=5L78R^lsO@P-ou%D$rT`&b|`1^X}W9(5`tq;T&sMLOfgB&v_BeI0ntR>$p#n z@?+Vv%WoZbSJAZv?;)PM!^>Lh!bs5ZLf%?tG-R#$@?HbQXtXS2w7f3qqECeLIZdAQ z7d`3Ed(t!GlD^H8zS5Kaf+zhEPkQsXq;K)0FY%;5>q-9yPkPI^qz`)17kbj4@uYvj zlfGeG(q(Llw);F!y4=r?(9Hj|Cp|wd>D`|6IiB=KJn1_;>08DneS;@`rYC)`Cq3^; z-##ws?Vj}Mo^-yI%{^%_e~l;o=5a}H@uW}nq~GV+zQ~h4JTB?$Jn2(B>AO7Xb3Ey{ zk4t*9Cw+n^{Vq@XF`o3%aY=9Tq`$(kiCKN#9iH?*U_6cH`Mbv@J>yB2SzM%d&)exq z|EVW^_qe35^rXMwNx#LD{+K8I{&7iP=1G6nlfJ`~exE0O&$y&7@uWZFN#Ev4|FkE4 z-?*gLdeWcpqz`)1hdt^0$0dECC;bsmdbcNin2o~kyFBSDJ?ZkjiD<5Sd0f(Gd(!Xn zq%ZNL%l9v$(t`!@-6yx&Dlwm*=}EuClfKZC{>lU=T~|_1LZ7i#ks%+hA`4{cx*&X$ zJcPy$?jAV1l2)3pV-+dvjSow#B14_IiY(AsZGX0e?ObjB3GJFU0e-P|6<k`^dMLLhQ&{T*&9)`6|H!E3J(b0U;_Ml*n= znFkD?vapz1U>F+~vrbIGAtj612+ZATg~ePA%(GBfBGY2t56p`Wlke~99qhnGvxi@$ zG#>*E*E_b>7l6rYrY#Ew2K({Wp1ywjtSoDN7c_h>r7XzeT@M?<*xm&u&Hn<890+oi z^>biq@eTp;s+DB}ztBHNp)2rh>foH+(w%L^yL3<^^y-IJeoivfI0O)Oi3j+#xRu@T(1cU<*GWj(F@w(9}#VwBjyc? zLd-t{WAC0&)&XGdbFCxw|K0GZDyUVC{Y8oQkk3qDqTZMf40EP>tlj>8JM>rsX!dEA z01bXPDqn(X0q3xFHiKrn{)WZ+@I%0?Lr(}J>f^xFy4XPV;IqI?!#R|7KQKY0l^+G> zfrzC)1tx06zXS6`gyz41IS|q3SlMdDVRi1w^|a-;Lb7X}O}YN{eFM2*7zDQ6@d}|$ z_)bP(pEsuGPXwPG5xd?2%yw5xWGn^dfU_b$WWP9LpWP*&HJ}-dXee*wYKcVMZNNML zcZNRv5-_!q_<0lLNeqYjaIk-{Z>T%4zf+*?vp~}wX|Fn9!u}=o z+kx30k#&u5#{V#$KZX+L;a2)*f!XamFMPfZ%%E#8Sc;4U&pX?N<~yKiiPZWbFx*SA zoPP(*vWPx!!q0|kBJDL5m}c+`<9QY^uS8m~4w%`Frh6cllk8`oz@dLG1x;l{R=Z$a zE2BbiEilhV+Uq00a4l?g{xmRE&aT$=c;zl?wnSp%LD2C1Hn!GpfC;V0X7LW@Y*s`T zc>Yz;L@~!8mbn(Td}@Hcizf^I`ZdNXKtMr7rrR-`vw z1xz?|z`M@O;JwW8F&`D`?F;TV7+UcW)Z!kR)#vlTJmO?EcIR?p!G?%k_k-pj{)cVx z5K7Vm!d~z+F!J_>(9h2Sv(0e^ac~HjXCoN-VeNepOa(B*k$KB>V0J`om(f)Yn={eh zyL#I(#zmyB0L}i06;}ZBg6mC~IdsW^|_h5w0H#h+u1IdOMsChv|YYFA@{_?=U59}|(M3x*k zgXWG%>wFTJg%QlXz;GYQ*7_bW(N=yEnBC}Op*Ma9Of4oiaIDHY<#>#hk!U#!m=^fa z)`IP3XtclI5e?-{^75Xg?U7!v2(`GgWc67Kj2z*((+$joh!r0I=81^(zXIl#2<9&3 zBU~-#Zvs<=Qt0Q0f!Xicy+a$UX1-WTul}p>0fSJVSAcmDm@qb`pMYLzYEjl{zyv17 z$md*Oc11K?3e4SxhPAT5tc=jS2N)m;Q-PTf(fJ%; z_MKZ8QA>b{u96yn+2UwSmS~OlOv!X^zx-85r?|rO9?kAAna~-VhEGvDSGyqVt=9Igqmc zvwp4yW=TYPEieb2&cdfbYDM_80n-%m{8fT+d^#{)ZbQvlSIe|JP_@8@w%>$W8-TH+ zF!DV9AxA|t{1|9PBUx(%nA;;7ehrv)PC6I{4+HZ;1oIMIAq1H1IudWtZ zksj9$j2vNXZ1XT50%mW7&nJMH8Nu8Q%p(y??*pdlw8FmgZD4jsJpU9hvM&)@`X9jT ziL`}0lytyhvi75D!R--CrwR>x4F%Ab?K&K7;rt^O&H~MzNb6h-jI=>$dnYh*gqZ7q znG><}L%`hSEX`u&fJsxZC!)`%K{L&@U{*g=(-M*Xbd>=G?-litJ4Gfs*IV{{ke|(V1G61bq#h84z&084Q4y~ z`r9DYymPt;+1B2}pc)wJ8;eR~J}xYq?doam%w^ZN4&*RMC#uq#&u0g>=5s+$YcFWq zQH~R4H4k8@FLud%uGzb22ez14Q7WI+K`(x7)$&U&x-7f=lE$XGl`FGLmM&U-QFc{b z)3T)v4c7P2Hp%-glbi3U*{Fy*KHJ{M&wycHa!@|6hh3OP`B?f;g2nhWTh}JMvDRL< zTcmMivoRtNW4XAYbs*c;HrR(Ki)oN;M|;cWomh~SrS1Aw?7VtpHkA6h+jCpm^6o8~ zKArJnYgaYtqhw% zve^}j8?q~xH#VU+WwZE1WVRpQDIY+B$dW>k?YS5_<~&T4WVg@U%Bj{63+zL?VbMIF z>x%LrV!O3iokz%4*93ye_xE+;P3r^b;r&5(>%gGH$hU>hvM8CZNbzh_MfWH9VdJcs z-elWwKLr2JJ}W!ey1qMSD7*Vw+s!^jyivGOD?A1e=s8O@u%T}=zAM$y(X}OubO}{* z0M$y2FzO_5s4mAeQBq2t6Acl!} z7hK$QscS*$hFwVWSLfP;o~_yLw!Yp?HoIiyRnX?FyZ6)#9 zw!WTxcdjSbI|$YKbMnEhZ0A5nYghMBe=fMFF}t|0S8nV!BA-x zUcN47Y9bM{3yO)EQTLjW^STk0TElv|zqJbk1H0J3;Oc=~|0;awVJS9fITB)tJ_Iz0 z5Zi57tz`37nE>m*Xqk4J+fLwO;|sg}ef?V*y7-P@BVIX(eh*{vxvsMp%+K}@^-7?k zI!0xD&bL3cm#$uNX|`eM%1am9&bjoGCH`=i z%@(g9z1g~?ap^LdW%l*EjKnJ@Y3KNJ08tJf#K=K8Xcy#q&>79IS_HBm7sw`OIOT^| z(2C93jk&Ehdg+{k>um!8FK4@vW}szu^Za>MRbkND-tHLC1i`mi&w2FyXaVDyCk!Oi;MdZ9WhQzx8$H07-W_@t%B_GflK;&CFUfJE$>}C)ZdTpX9yhM zT<=hiOhTkPc6Y7sZ|&cTp}YsPN_^X(XJ{~oS!QQK?l9x6T-y{N2cze7_w{yWWrI@! zxeJ?Hd3?_mTfLpw=fn3#JGEe6ABR{*@0I<)eBVIVmhP=c4^R$o-aPN@dGpT3Yw&te zU-nZ7nvp?S$qY|L7*KhN26CfQYFcf2kz;Kr0}YvG9-D=}b|M>wb?M8N1v-Bz7Nsv2 zl`R2fMpD~Pqhn>(PMu8puAYC+IcJ{(;xW3eG|WYaBs*DKjx|9YDhbx!amh+Equ=1~ zMl?aL8{=Fn46~6a-PTU@%&4ASQZPhBCaYR7izN#;40f;S!UVFldv)(-+2(G{4X*CB zIilU=@(a7V(ekR1^fOFLV3W)QO%t13Wmgf|xi*H(BhU9CiG$S zsQ1vF4PM7FM5D~Vv)%c{J?$&aT38pVZoCg!AI`w&Ek~@H2sO>IO&esde7P(U6IR4w zwDB@hmP~>}2ATf8Hl%-WXzCsS8Y9b4E@(nZMo%5g>18$7?8|4fc%037Tm6<@oE^yL z+PXTr+QMX4DudW8gs!|2v$>)Cg@{PW=u3MCO`|e=H{@FLk?6HaC+u}JEV|N^mN$DG z?sCCu+NxYcv<4UK9>gf2o!2eb88!Ks{VQ{=n-ap^_S(FJ4?LLQBB~d5Z*D4ZtVV;G zuR3W9poN;c+BVvunYA6Qzj$SWD;{jNAwt9Ktp&ppoxX1%(%Z$aP$4nTq3Lq{UY9Sm zw_qE>Y_Wx=;1*=7F&1;4a1TZ8aMNm0#O@KJ9T&Ie2QjzTc|9r**m-Ui^QX>USqYd_ zr5gvhuWvdjf_b2?SN&=?`b_`E#JgRwyj2zy9bWu~3oS9}$Ie_Zl+-mvGL1foV_je$ zhbYxuOy-8ouoe?G_Le5IY_vQu?Xk0er+|K+Rbx2cmS-TEv6t;^x{7tBV`QFP(ULw5 zl$4IK7{{$dBs?>7!^|8@*Mu=&vdyZ#_Mz^a-O!V1f}{|u0o4sX8Qsc@M0`v}&%h=b zek5MBaW}QKbz{`Qf<_zHj!$hWEXjRT!0|9c*-+kYKUps%$F>>H%;vKR985)WTS8UH z24`$gv4gc0WDYyV+g&^>2gYh*5A(9Ug4tBzN?BU1NRkE*sT|JhBLit@Etj*BoeK8F zHs@M5R%cgi$~NdG%VKPC4CDr?i)_7!CVI=Ayt!53Y>KyjWafj33cMq1%!r=J^> zebF{_Xe>b791a04cLFS_Zm2Nxap3K3#C8bAUKjHw^-`~*YeRWvI+iR%pXKn3-Ky}? zTC_Df3%h|a1@UKQoTXTZ2%U@cm>E_=vgOvjnhoQ1D&lO?fsIilc_um+)2BAA--;$O zd%4t1ni6eCEf^BT4&Jo#g0FC1kKPxZxRa$7o(-p>SOLWaFp-Kh`$$faLD#4wnLDzB z;wHpqMo~DswHactz-!@57iqV(V9JPb#qLkpEvV>LlgKTcLwS7}ZRlwwmH42N^+Id{ zg1jM17G`UkGEfRicb3>3+4w|42i>VBx*{o9Ohh*8ts4tg3q|q;C%6dvf)U%qsS#$a zLgzIP%D5KiwA@C%ty{RRkbO|u;O%bhv>1V&Y1ZhFsl<}iu$ZwWeHhLb>;pEgE#xtLxdXw;qIn9;6-&+FO0Dyf wCT3$!L;Z0F`eVkX%VDd2*f3n4IA!fG3OLxBjU6-hbJG$|8QexhtWO932g@l}9RL6T literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-suffix.exe b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-suffix.exe new file mode 100644 index 0000000000000000000000000000000000000000..e54eb25d97c6508377c8c808a261e98292560a02 GIT binary patch literal 179276 zcmeFa30Pc3);C@kZa2-A?ifIfiMA0U(LmS(BvBd~(wHU?Ae%;^X&QoI3*DU%jY@3L z^t5Okbw+12X52!gTRWo1oV{ZVdouK;bGAv= zm(HnJTJJQrv^LkZ+8T{^TT@fB%UJC&wz`{)^-V@|Nx8AHxyF$c85tHQM3)vYR&)Jn z?4i!57cgTG8yCXZF?Jpc4+=Vi%>+{$t}w<7(SQa@luI`y9Hi(?sD=TdUmu{Bv3F{N zdAS%faJ%Rw$G1*wakMfTHG zGUsd10F;7{%CT)UAIg!X=y(4@#8-iD5#Y{K@MWhWg0XfTZr$Lcz7hi%@S}1BpuYtF z7uUdU{n=*5YLoP5D@JSae41eKX+A<9N$Kw;gJwWK20DZc1R{?HA|=%jwI-|h5?31% ztwEGG`o5bP^Rdou*TU^&CI0+ONbKzy#Ls_iEJ=^vhGZ6R5JKzKkVZygp8-;45Xr~9 z2EQqaLYm*%81rOFE=NkY#q(^!?(L+b|5J3EqkpVjXR%vmTBN;evS?t@ce;^{eyb(6 zcFlL;lB<9~kiN4LRL?dl@EHB|Wk7suPXI~j@7$-qeb+!PB~t67D{@~9py1EKb~gk>~_Cz@nxK-LPnqYw4M`^zGD&?eOi>aV>v>-ny0$B+XIb9)40_6nIaG6 zNJLV!9wfOU3R1dvAeN=<8|?GfP}6rsel`))j_CU~5La{yF?)mj{s}zJ_79lI68K^N zbW}cs9jl~x&8xrR*l9wvBK`7|eMh79XS0re*Hq7YlIuKf78Xypq~Bs_KWV(?W0QBU z$#YC!9=xT_QitV2j^?Vd;^$z&k;VKI{KeTwCL!&$b2K`N!!dO$@ zviKqn`^O{J($ykaykGbiP}pmJ2c?WUT;xTrJr>Vy$)5?jDf{hfUoP@|rn|V;oQN!m zGx0J=^RuzMBEGwvKy)5RzDO(XRN-EO)u)-pk?3S%{wj^4qY?CK#^Da*=y)B%e9`~# z0qb{%`_~~ipXNAF%bI7&x-PxE@-ovB(`CDd>qo!U99K1MMO-4Hym3y6^KeRVK8 zZ9QWHnM7L$8T%9&n*e&Xl&^m)#;$>@5MPk;*}&`n931ra`13(q2Y$t$eM8LLoB6{q zQu;UlFgUo5I#vQYR_>4e-*cQFvYG!)J#L-D{Od;i=3BfU1=bJY$kS-?%-Tp(I9D>P z{I?gAm0xx@Di%gG4IbcDP|(PO(WQbI3buA680js#>)mS8-q}n<~OMCqwkQW zN`AvCQ27R6@k(H2Y?Xpyvw&_r*J9yoMqvLPSrGlg&w2u1@&!<^W(Yz2I!wTc{ zzKkvz9kZSYJ(jN7k|p~e7JZ%{e!voXf=?DKdb8isB|nqWk9)i2+ixtM6K7cTg$FG& zCVrQLVy=XiN4z8<@;eSDz7KNBK1=qYGx|O6PxS0Eu8q=JJUx=d^W7P4Aq+0@5#sKO zTs@c4u8uSA(L4?cNOHTS=SUD`<^8e<4LWHWsGjf7aGg&6kW3Rz$1K^AUhuoyj}Aae z1())r$}sTvB$yUzZPn)hX^ zcbD1wiYwXFRWxYzb{BV9brK4ZS&o5^r}Q35MJckjuGM5YP62!qjc??NZh`NxqyzKIMN9LC^lFp^t}5k_+sdHwzdM027?5KZ1M zAk<$W=%rQL$t(G10^bfZVE#OW)~y>FFJLDHDgCCWU`c~J>GllWYQ4*+TD&jRdRHa& z()bE@2`(J3O8>C%| z%yNTkGe(u1OZiaCN6W9EzvrZ0f73q^Fwxk_Gqc!tp^@j!1J>n|j&O0r-kZ!)d^EQO^TjuKZ zTNaD~V>lRl-Z%8T7c0FAQe@BjI_Y`DM@Y|S@A8(%={xN_L19SG5uJCJeoLWN>Vq>} zeF+-Mo1b9z1|nVF=W4@zxgxNIz(uY zlMH!MA4HrFLNEwHDq$)J7(HV+j&Te;N%{^KHJA@|O~WeY152Qm=lzS?Pmb4j+>EfV zJj(3Lk2OhsrtH1?n_op0cJ}K#-vRXe1N@QDLbZNAws7l!t@vMszMb9PJ^HnOM#aNc zw^98gVy_a>t6!Ul=EXE3r5~MX6Q}As_kqi5|J-|(fyUejP`P3C3By7sv3PfZ{|dy+ zAUm={i1!QB`4aRK|E(ayD5%wMHel#5d47PFry(^$LHdq)2%*-f$e!;)^f$|Bb6yZL zkBFjibSh{x>3J8bpiTUXkmNL!x?>z7eC0+DRa7Wd)Je=f|HvD%G^piZ` zA)(Ks;ntzy0;^_V+WD}XHVGE=AT;aEHzFnL&5xqBmwsz$P|y2e-tq}M2n{Ze&3;~g z(+Xrba2amu{1x&g-aHrSJ8g;(s#OTVFvxb$?dWdg{Ynw);+ZMDE(X5CXovcl2^u<6 zS80{S`R?lSAQ(Bg>(yB8P@&rI?SA zoY#(S8H`>FHfU1}0vuotO;NqQT&Wjkt4f{lKggrcIBdYanVtM4iL@w`hNPuEbo(Dm`iGK)?ml_~1 zQk54nB#%Y|rIdS-cJQ@)i_Ly z7x?+W;{+ZLJi*enB+gjmJqY?_K|c?U`Of3y7OY+Q5vJ|%sjTM{o%f5i=D4YAE8-Hp zyLvt`Adp0XSOlhdclqlm#TWjA@u&)T24ym+%)fm3Myx|!ZJrbGv}d5OzI?+4`LWh6 zT37eth76c#JNZ3AVfKunFvjt?opTXxQwMQN9PC>APYe^9LDU-XBqB~5)LVMIU-X;^ zg>sWH-UFQLf9o6W)EU~09uXW%rH{#;CRdi-Ii zIx~sl%7Gm3?ExCsGhpcP$5JKnYBA-#Eu|PKv8qd)<5vz;_0|pS4;BGX22lSv4j|CHz*Z&3l{XjJ;OrgD50NOjC zVNe0fcw%{(SS|ufK>Fo6g+GiK{tO116Cpt|OqwDLEdSU@58osJfDQ zXN=6g9s+LU)14E8d}GJ8g4>0E5a}$w$XH@nMhw2lD1$h}&%NHlRMS-aGkvyIchJ3*^5ld8`CW;7MrKqc1oy8liAr#w1A5eSj4)9Nk z{lHAWDh3B_1`K+4yQXx$< zj%DM_11LeC`-`Ky0_0;q@G7!Hm-Z{ZlJC`A51i&8M?0tpmcjVVH_<{!{8GBrk|_kS zo96j67k>EgROq-Z_1?pYcf!jKxeH77ZY(;#ea+&X_!4n=p3PNuMs{O=p$kni7=33K z9ICH|f|nzR?x?^$gVEOmC$40y>Y{HUzO))3Ut0L`fu6ZpQ~qX2dBfuUrzPd@mUH%4 zvfp)~VUJn9?X!3@=1`7aO~t5;hwOdZin6FcvDa?q1Dj2vOspL|-BZ)@4-F z-hyKYwkW|9gVDbxFiZE!bqT_zGen?9Ze^R{=~> zlZW6yo7ySKemy6HU8i^UyT&P78DybD_V0fxLOc&qELXKx&AD^n=dyxa+Flj}g)wt? zjl(?Nl{+Nl(#v`KPdwvJ$~)sU0@+`=4r5J>N^}LGpLllbKyrT;n8sg(9FJ}n`?;g- z5&AAdRdiD2K*-cD^@fhPb|~Pbu205h@m9noe5oH>5toenlDI6~&2hPdeKZsZh!ZD>dt zC%j=8&nA4yF#Z?9t-=7_`e0;#w|MuW)dK5h?+6B7KUo&I-bLiaQP+#Cu=gq}>VK)? ziElw+V4U|No6$4x_1Gk__*`(;4V(#e;(ZhQx&CNG_`7i%J-!C)&n&Xo6CYm<0hI3n ztG5?R%A3AIqre{S1|55Eo^Ci?nA8icQC2wK0$f(92e|&ajbQZbf}8A)&HluVLF17B zSUA#BcYapi@d3%{YG`B@Y)%(>KeGlW7C~l_x4>ZPEkGpnOOC|U$X5{;VcM2V?ATzS zaR@xfRWqJc^H~#ggVE=DxnP&eXO1&>m3DjHe+Ikme%W*6dskeMcfcAP`6)brX_08?5q8EJA9GKhYNN zr^u7`AWWCjUSd0xg|nKBXmU~hc~pIOU?VaY*K;s+c>W{D{5w!f7|+tEllUgiBrxS! z_&B&7`jP3Nk7|yRM}iZdg5mT;$Th#lJ^Y%+esH8%DY?Ib0r z>X6Wf{hV@G$Pugbp64W<2rzwz34-+32jT8HY1DUI#RIwe&dU)fn$m6ceq!~0j;&2g zu!L=7Dv-CJ&p)3QElQTH5BfA=C|t^0DaWDYO|+_q0{R=MJGfu8`VxP*9v%1$xL9~1 z&mNfM?${X_Z>&PTm{mg#29jXS3&4E_c;$C2J_~l}xW#!-(&Hyc?KlnUz~~+TS1~qg zeDnPlUvZz=C&!uwUqAZrkpJd&Kurx5`l#i*uI}R{H*J%-@+Xl!s^Gm~iOSJM3$E<1 zTHhX+jwh7Uo04-hw_vGyg5$qmhK1;?OTgi6HG&5pRHV;A#>P zJn_~xDr96$9@S4i+B9G1E7keUU;+8hAp5frR_8l3{`sU?SR-_=w9mr$-tD|<7Mc}R z9EmE{-|!alnFW2@^&LM@P(yK@uOXPyza2e*`Muchfc0VvD}@?`T1STfj~wh14@K4a z$Sf>n!GKL%wlaSf7AipQC%LyG=)M**$)@}nLMFE6TrNvzKd)xjW*#}%KO{4k&BCrh zx63gLyCU80TqLJ@@gI*-Rf2oq1LZ0nLF(|KVaPsa!4G%4dS_w2(Cs>FXdK?ncQzDV z9)>Xg{_h3{MYgJrw}?!jqrP(yEF&O|8*#`=0#&gynp7z9T*3KD{Cj9Kh01I4B8B<_ zS&&$-49!1{{>MX56z_9BP2URglJ0m*=VvY>8r5PVzqAEZR6FypLKD&4AWAKbQOrhZ ze5dhpCE~lH?*;#M>Q&aR_~YolDaS3|!+1cv-AGmDeWPf~r}Vhk`^M3vJt3iHZ=GyG zXZ4jvP(SyUe;tg;J^b?&zs1w5^XC8HEk9xL{L|=4r3aR7E!V;QoTc-)zQc)X@P5hr zJDycQq=dj%T3iag`26{teWV@QBa4Qs8KOd*A!u%e3Fgf1&?^Re%v1P z9X^uDZQ@;cnT2j%8W-l^G!z*xwG18+pNE?sM_^eLX^wGyO|A9!mbC>5T@s&q62+B zPAReb<^Zca4B|i-7>DOK0XEq~v7e5#$UhV9;1G@X%{xK!KZ`AvfoBk*IuZfZ=V55% z_h4Xy(Ut8`#5eItAQp_OX%=7Nr<^p)0kF;&KKMFqV7>u^9s^@>h0;zsOo&#Iml}}7 z{WfIXPRaSouktc1*{YFL89!*?#^Y3<=2CEYU%|u(g2H$sU0#Wq+>TfVGw1zcG4w{Y zVSVhH>CLiuTWESPlPkI7T2fM@r(C)s69{-GN*v@H2BW`1H1GV>lXi2HIeM3pzsUU^ zScvxpWUUu`>U;s>4k2zZdZCiVqr#NN`wZEyxx?mqY5k>o+1 zWc6^i5JwhITFx_Ayrl;JrKfRSS98uXa30-n@s%R32g~h3P>;Sn)SvkC1#~vniboB> z?lCxb0S1~u+zsNen?QZ}G^dFu_+~uqmw}<k5R&uv)C z*RILNaidTyqm=YVU#40awttaczZE-JU1lj(zqLqv6%KRHc+Wf=vGd^GoOlCd?{VKCI{+_ zr}-245m*z}*8$i%i}zK30!oJ(dedUhL)muex8^~&B|*?F4+m>pyF7mACbwI&HR#+enQYfYW zkLcIP=+h#5?o23Tozhbzb(`=+NsC)<6lNk_W)|yu(enuuiTX7vsV_nJL#iulb`PF| zx9Vtw$bPkT!cbiyM>QMOp0SrOOfpl2(SA~NJoKY>q}sxO1HFWNsvn)Ao}cPRztwD@ zNA!HjF4CiXAIeda@-lzvgy;n=1UWx^D$$DhU3Dbg48sS(5Ss6LQBn$p8{4K-I_`V*Kz zs>S)4=1LjaT#7$AMSEcjaLBfKHon}rZ~J=uXNx>h%cJ$1=+5EwjU8;1aRwSKz@85I z7Y->nXQov;JNhv?yHY+Abrw%|l+S`?k~;*`7qnw9R!`S{WcFDiilsxU z`6>QnUa4gkot34nl-SlYENcch<_Tq%L>}U?EB|Jh(qjQ}(c%%i1H! z!3Nst;F}zHl7txSVi5FY`8Qz03KPm#GYQafloS4UXl;z)KFaUmkwiU4tL~|Y@Hcas z`XugQkZ5lzncSgip|T(s^9bmXNlO7=;<*I8H^xy7TD-T#-2u1*P8G|)Jyy^kLeT8H zKW-x+He@iq58#*$LNmRZuVRqtn_;9bl%$`YZhKAhtKBLL^H$e)J65fAS1U?krTI(dxVE2qwfx;<^Gwwt7z@OaBt&f@#3J zRy+}3L^)>n>O0;-dbFr}m&x-FWN;(UBKvbVzNE2A$FMrfF8Av@XnYQkOZn2c2>I>} z!~M;SjgqO@2yk6(_G!*Wx#(2KSr%UhuaNev9E{Fgkq0tp>&EXr>7NQ;*{k^^8j|qa zb`fr)PX^WR0^^O z(#+n!TkLzNEJe~Dldn*R(qC!utd2`&u2x^^Hsi!_?@qILA0A<)35c|M9-P~Wi!Vxy+_@43vHDOIWLKT_RH4z!NPNEwbAsU} zqf|0`C=!}l-}xf4-v-yq2F^nWwI4fhmI!z?-_hLt zPN1~#={$-6w&SqVb{p?Qp6(#8=1rOs+tEj?zL~qM-dTTNh9o7VCpd9-714aQJFpj( zPU5|q`$#I;hBBWT)nBuU@ih4*er~XXXG2|+x~jh8ZEPZ#eUWuYPiLt*P6O_lH3KNR z#2G+*(JPTXZFq$PqvBFu*Kc7n6LExwr`AOB)R?&54}9hY`i{E*J^l+G`iH(_EP|c= zn1jYa4Es3y-pq4=Y)8MANJDoz+2bWJyVPnv0Ko1aejJ9Z6x87@Sc zy(fIpzr6y1DaU#>g`kjD-Y=%~cq4Ox!IR)w4gwekqOg6KPHFU8E-dJPr5;df(M|%|!kd`);c*z1P%!VWQQWaT4=#eP=qP7vOZ4#06|5E}!B&cO)XQ z|3zh!K;ID#Mx0N68mVxg2_^a4~nNHEZa z-oWPbvZfyS?ScvQ~e&EzL+UWYFV%g=LxDd&Y?!|iyfOz=ny5FlY z6X`BA%6SOzM(JDzeT%wQNT&9|L_9W&K?EEUwJQ7^^)H~mqN=iMw1~50r}w(9CT4xd z6W}_octF`zpVAF#j%&QyY9{^8H~h~~Gs5TbDz(B+Hb9hBI4GR$Qhf&8ztMjQYJn8R zqx@N4;S8z8JL?84Huzo_4EHL8$#AVO76?D=`923W;{a9Pu?u27-$SP^(p=ahCIuIX z{5$?YMHnv8v(%8^FVuHFMU}^mXokLX6A;DxUV<3RjUgMuc=mH%O&Dc!^TR}r4ni31 zTFO<_d^m=?T|QE-LoVt_Ibj;65eq@^2jOIkYDm4BZQv&|x!I1n5U31I6VMKnw>!k6 zxeF|kFY<2|{h4ULGgXIP8^=cpiwe@mO|1n*`Ek z=nR1WD|8FYtms9Y5&H|^w_r4_q7-Ogs6w6SIh7mhyWx2FHxd7U8b26c+l*mp-C+Cz z0Sg7p6mYVDF#>7@Jl>?F`&hsO0`3uTi+~Rb_!|MQ7jT7uwE`{>uu#BE0VfL>BcN8m z5j|F3V;3^wCekco$2vLi z3*AcTw#eEQxeCukkoyYC1FKRaCg#)N%_`ZMti=-8v>YKJ<{KQ@jo}>G3KvHzq^rLrDRB2#TgA$cBa24DR#aaSm=PI!? z`BCd4UkDAbyl1xz%;EgOnjWgr`rlzsk9NJD~h0|jXmLCFJAJelV1^BH>vvq6lW zLf-fArnKB@!GMwmp^%U~i>lIf{;cr?&gBgj={tjJiQfH5Lvp_D@7F`R|IHUrKZ7{Q z{y6BK!C>X#hv##w89s(=^_)GOEq&!B48wTA3m&i=qcq=P0i6r0^>)Pl4iYFn-Gr$G z5$+O%nS`ttNHQTbXYp6Q4&AZe4%PgZ!qH;9Tk|ZL;E3fZa!`)?D@tDsB}kd;-oQHW zrGOYBCL(gAa-<4O^y~d7<i%j2&MW!F0gbc4zK^KFdRM6SrQS$mb;{Ds7 zS2vsC0r=wvYls z!OVZ9b8<TcLK3bD|N)FTx|2_T_@e4%!b`ekAA@FAx$TL3?Zxivm ze$(+=yq)X7wt^^A}I$W5KyS^2mVy~ zYP#s8`DziCg7kw3mD8@#IlhPB{0&uNxv^tSAfYD(TG-H#y zvD(o}oOW>9mpbgrj5BNN8ypvghURn3TsYq-bZD*>al~%}zpbWbh}(p40I#b#fY%J( z8b^b}Y;Km{|zIKCb0z}~JH;VG4 z;0g#>K>}7dnrfO`htezPzf4|3I#co*$BKHpV<@?T{>$X$NbYQL*o`ykK9rg(3qpNu zz1>C)`tyQVa#A)UD{#B&8+br8MMAuDiZR|9CI*(JE>}y=v}w*}cdOk|+uT~`NNRGp zrnO8{(@t~M+m|_9&S{FFN2J#r=%p}mTD|_IcjZ9#&Y}8#`+r9REkNX zm~>-Bb1Ob5WL(hPP~&I{8}aoam|S72!(l9Mu63=nwK|NprW)f?o6~5@D=)FmuPCrC zHqI?EE;N;undVk34l8YN*qjbytD~j46(22f*Ex-7LSB%i3+y?z9CJ=f&WfCxobnuJ zP6b=s>^3$z95uv5^;loK%4jo^eKy$|9bv4bsbQ6303+%&xh***IhpH1!4w-TxP@|b z)F>5Ju5>D=+ipi+sdYC%42)UHh{TKjcq+bDM`QB}aB_PUypMh~I2iI@ylx6ecSAt< zU&(U|UOQmHe~^ykM*IZ-d7zUEVZuK!?hzQOhAI7*p-VFKDu%AXs6~W5DIcM-H8eEC ztR3(`jm@pAjBpsv`YRpA_!?vNDi^$5WV|!<(s($r__T(Gn)rBQd`c<;A~r1EX{>2( zawLVZcxR3gqVt>Gh^6mat!%A_TvZU+164f;tdO9q83wYHYzo#N;1XC-(+XPyx^aM) zaMsr~*<9{c2MZwPm*pdGhm&X4Xmi<@vc$mrhl*BP-`dD6y&5*;Xk}#%Ta7WkUMYfN z6i!!7eG@mdVf~w198E%HC)cqR>FS&66!m#6p)XM}s_W|l%I$PGmQiV|Fjp5&6Z223spyhs;IDSy_+zaxHbBDPi*~Nf(SuEsj=Ky~7!XVX75=CC4a!$!+n; zS#4pZwp9(yXfCBjb5P&HeGlj7ZgMo)TUWKfQyJ$jDm7Y5^Z)&9e=Og)tUeDNFANR8 ztf_e=J`Oir1lOt-)y)Oi(~sHhZ*Fqg>YJQsg#S`4<%BV{otek2a z^Yo%p43;}w?W+rN6(w6o*t{cnyx`r$i`^EU7Qy0`N+&w@J|#&tim ztmew^s{irnKF6<0mPk>D8nkx%Ed9xEB6VGRjZHHyH`H4{G*!Lcy1ee*S3eA%IeWi6 z=O3Ms{mV9oJ#g}&%^3}MY|1;Z@2R(PzkB-84;l`px|bX-cqQ_{+lyzt`pBcnhbHH+ zcjvXwdt+~mt?!x5Uq5-yxz9ea;Lh83yrO^LuiMsd3rf(f)l_ae6tO36ApG$gRyR)@ zYhAkNk%_jRS&6k<)|uX3pu@R@tk_HXmwyDy|I z{X2X)=%LWx#NILHy{96txHfTCqwcp2HMdAh>>qzUZ`rbHTf>Bd$&SvstoqB(Zr3(k z^?-C{&)2%^7Cx*0X3wFGj?#gxr+u<*r*HMz?LQoz_)c|E;+xT5t$yuBhjst=i)@>U zU!J!)$Hkt$@BQSb_M09!eDNE%ADq?r?5p>G|Mh{_t{AA#|KU(mdg0o-Klg2`defOG zn?ITuoK|TK`_sPFk?+i0t||SKDd;?dA$;fc#)y6Ko0l$pqO;i;y1#b&Js;X$9`oJ1 zm*27P(3DAc^lg0dp*MO@pY_DzHIYvy%~`)tb-&-^ap{Vl=2>wnyp zJ^S@f{<5S%`+Vn3`8&6s{`yTDtNiyJIB?Caum0iLT?ezuzC2v=Mcq@c)-8Pc!FRNq zFPf9N$@1m}kq513hW+LE#le|XSIVZ{pI058f4J_U&u?lFO2upKE0v8 zIX?6KrDeCTjCe74cKB1DQM$d4YVz6HER$_{Of3SNb;l z)*qTW@v(O=-MFjf_mjW0e|pz_SGdD&Z47!?8+zA8nPZN2)`hf=TgWumUHr`LQCDtz z|FH`mzbfm@EfK%JssGoJJ7523>*sH;KIiaT;rshvyFTyz{a>7T;+>^Uo;S~aDQ4%I zODAtX{@%)s%`0bbjs5r%-P)Eb^n=gO(AF*qm&OjRcide6SoMk52AA0iUTKJFdp~T$ z-}@uqsPM>hcRdlDZJS*8$8Te*`if`Q7rnKz>B5Vzc=fTjFFA0iHvDkzu^9)amp}IO z!_TdM>fLK!*))4#aC7p6FaP@2U+voQeDbYNls|ailX05Nz8$w}-*{=t!gnj4sXKIT z(v`JOY`fU@Y|xoYFT3r6=JTiT41e+uH%06|^RVWUuFr!Ks~*VZ4x)X70uARWkP~q; zwbr>C9au!xG&jPh8y&5!m_{X-ONvcJbEgbPJ24WtX)tuHGA5K4%|;ymm0*@pi*eA{ zYHO;)z^x=NSx`_`Xf0Vdg_YVcFxnc74H#FISz%ohUjjAR9ma%GYe{)ImsHX0`bn;e zAuh)KGDcW;gUcvpP0mKl(3FW1tu7FW;$RR>m_OI7YM~B-Ts^LLC1!d{fhJ7BXzZjZ zO1v{6zHX{9zHW-qn9%BQVO}!}2s~`W_QAo+whaz;<9ZR-+qgc(^#iVA)XU1mm6_@E z5mr}yBSuMEeFJ7X7y;-f20CMW3tt>HH5=<2u|iLDI_$IvWJcqH`c{|Q)-ccQz`U6f zLwB0W#*4|Z(dME_4^1l|g$u=PC>@3r7i6g^`KV;aM_`Q@AliseEqja8;jU?>c^A#p zX#t9Pi>uk*+%U8!5MP4{xbpkCbk&$GiP`-Szp9t|y;BwE)A`bp@}fo7#g+LbWn~5V z6>1zob=*}pIk0p_JN%1yvGP#3L^_(lH=T#A5Zf|Zi5hLHS(Ct|^M^&+8ZpauH@jhs zd|QR*7|0NqIl_XgRhi3T$}>v#u;ft*1^Tbjk0{J3M68>aJA&Fb3a=WqAKJZYB>!l9 zUDL>T#zx|4ZDg?~5-m!BM&zUsk|_{N7v;t!3&?-+$|7=^R$k?9Si@Yqp! z@+iDzRQ;8X(yt|Xr2J!}{3RR3pF9e0*)TGF?5OytQMh3geq>a6*Nwtw=jZ1b6UrPb zQl=X7-1TsS)vJuf<%`QxsXJc*PcX%pk(8E{%#_~{f9n4-{{K|}U-*B%eSfK+U+M>4 zeyG3yPus(P>QDZs_4!Zb|C{;?H~L=(I1M4;qHnqz0OyUxr`-{*0(=-(1i~8u-^H2a zD1?sy2H|*j0>bo7{#0BRgmVE4aV=vYcIk_0Jq>_{XvAg0mn|lcjbu(u<%^Qen7Ys@LOEETTq5L#?HWHK-dU4 zA6G2GRe+mu84>OVd>hwPgpUCJ4OcS4#{j>=m5wlrXY2s3EaCxtYck46VL<(P_%u4g z2EbLgst|4m^x$ehcpc!YxLSxG@KaoE2p_*s+0k9O;{bWmkm*6@`{Qr;q_!$COVsak*0KsZNy^iUnaZHySQl)Ltl*-*feW8Nq z2DoPhl^~D;OO|MXxIuaiYF+^K^i$&DwTA>8eJ-d0%&Ufvfp5)#u z*(KwI_(IXl1NsW$kPzY4A+frdDIipt4~3v zJjqr^LseH{Z$N+f{Y(wa+&CP$c00zNO&IeZAEqtY0iXQDFdi8C;YkIH+N{8-0_F<1 zK)?n8R|~jKzyk5ZH33$JNn*@AXz&!%?3HYXf9}0L(z!L%nZBz7$ z5HL!>2?8bvm@42*0Sg73E8rpls|374z*YgT6!1C$efjeZdV#t5iTF|Pb#U%V=Qu`k6U{=4n#AXCnI<+MY~Yu+Hq!we_R5cGMK$cT0BXfjdaw^78ykf5R-4mRKu;ks zpC-H*XUG~H7MxCMaG3B;646Mw*qFy@W}=k4@SMWkQq)x2Y+^o6S%pJ-jTP9@H#zB` z35D2$6jOl%RXB#xrckBu;xaa!RaWL#DrdRs?Ujl)Xr)5Xv0cA{ zvAGE0lq3#ywAH)VJYaPW7d@3iw3C$quSab=npUuK3O83*)}p4crU2G}LkTN*Jk}_{ zoeo!}t)-<>IqOiZP~1+GP}ntF$YjyAZ;2D+goy zSS6knHQ~*mPgo@#gFx_mgy`S)7`s^F8KW{A*;c6%&sUbQZa_N0!!CwrU)4VyDaKMu@}uQC4)E zF4wluA<$ZujgZ@AXE_`?*(|x1=W-!IXjvrJ3Tbm?)GJjZTP4%OGm^JP#>p*v3oPhY zvJl8_k|EH^*zGa|aklj`6kdVzPwXCWSF3#~T5=PG#3QyRDU5nzY%7JD z?2RpK7lmBSNb`ogLRFhw56zMOhp#yWWpfLxX{r1eF0zY4e*d>$jm{PJR+m~Ls>ok{ z|66OIYHaQ)RWleA`jNPwh(AxnPd;@#`{nn4cMbF@?OG+^ga;Kow_Ab#cNgv#?MK#t z#9~3f)jpa|`(DYXpc9`3*PC;Ln@KO7G*;u(JJL5fXH9aqHsv^R*t^l@Ol+*Tw>CR* zpg+;x+?Zo?HYTk|nPkKqwZ7KjbS+TcCQ&lG5HDKHbhWyjE}Ap{o5Ip2Q8FaN=@&O0 zB~nlj=zImTaMa+9mKB&^)j6DMTwrWL8xqpl6{}-~1BZ&}K5LTAiNnjy%N(tfrm2Z$ zPWwrTGp7aSK6BboAt>!k6ubqeW2);L=%mxXtfLX^R9lJyGcomS5bt>msdP?aBAq_P z+bh*LgR>H6j%tX-fkP$3-0J%Z{0PuOur#l9;)oDh5+_xLL=Bzg#y>t6)y$f7m4n{q zNY9v_n39p6nV6nt&q%ao)H)KAle20Z4o6x|T5a;x0oC(g*Jb+8>XDX_l9pASZA;9k z$%Y=a)isG(j?|h&TWWfGa%yTuZFZXNzekU(pVcGXmRg&d9$NqTGoG)9!V)bt4T_2=JZVa^vuMpWJgM3dTLsBVs=J#bz)XpO>%8! zO>&KGI@iR=dj>4+}mLs`#x-BI&vAVW84Q=DdN<>R#B&KK8)?_5xQZj7W zyloUsW=;#RO5Qc5jWBk&l4+_hxllbdrh2Depjrb{5eVXlP9cf;UaCgr7zy#+M({r! zk0)q6qB}a5LyQglcVu=hhY7(7KKibtZ%b0s9~0>pL@JzyIk`Nb+!b2jUC}omPob3j zOV3p}_XRQqgcbf5tt!7!%wwMp;0X*)020JpWh#GQ9EFwmKP~*JcqPBOMQXe{Zw?tP zNZ<;8;bkiSF`?g2R3B6LKfPS#XYsjQ(pxk@pW-LV(>TOGibs)`gmth|pGU+z{=QLs zDyqo)0Q)DxUepKy6?yBic30xpiS>c?C-hVJXI-uGA4$mNl77DY@--^|F~J`-N)HuP zptI8i3M`1-?)NN|~k;GiiV)_Yr3V-y&Dt~gS!heO* z>3G_}o09)acmi|k`c>jPH~mz+lHVig&T7{@Qa|AjTM4W3*v4V^T5?tEi@cD8ap)0o(ZL*t2!F1+3} ztIpBnXsySK*o`)9rOj%~%1orlI%8r^PE<%j+p{1PYS0_NBH~7EH&wD_t!3+^4}4qzl2? zp$=#FadS7(h9AzRW3v%4n&B8C1iNu>akWy~Ig~bdB?%<7nm!8|6cnPoq&ZTItl`pR zMH+==-GfLi>n2hnIbsTe^rlg<6tsC;=~ztm}XrO=ZEN{DRVoqLR6lIDcMJ zW@dNDzYR@-i_i}3hUe2(u6#%6#Tw*4OfGD&VeeVKlhfspWTcUQ7mAOCG2Jke`Yb{I zedtCcH)!Ybm+SHF1Kw4}wlD^xi zC|Fd%`egZ9?YR)DElsgB;}L}1uKfd7u{2e|*Kk~?ElpGK>o{)EmZmGXhvTu@(hLRf z;J8s+nyKKO98b`SXA7dh*K4UFlC{Nc`Oa1*-@wsyZMmZ^AEjBVy%4ckgqneRIhsRg z0nlG@bS9yNKz$s&kkHvcZ{%n$q2)lkIGU#|5EH014n(E0hl<$}A$lFO|%% zD4L7JPX$faG8RcSF&}|3|FLTKfp;^NA3(}IFZQ(1v2EtOjI z3auM+D(;71sSBH1YnZ%@dk3b)^I4bMsn8lYEl68ot5XP#T2e~Zmf_W}R(zlVy{n0n zG+O>7xTJ+%h+=XxPpB2d+FCrzVsZ=jH*n_k%(xscrBgRz@^a1_F(eb6w3U;_Xw5d4 ztwf}D^3(=S8&2%voKZuG(W%{>6r=jn6+B(6f>svWoXeQJlG7$=3(2t6jtmdkrrn4t zHfk3&HU>~vX{nVqgsX*yueef64YfgH5uD@Bk7If8{@M z6b9m`v)NZM`H|tw;ISUnk~wUktWl|d=GaEUP#uqPteY^D?=KwdBMh2sqBY2GNOBnm<^$G zky6%C`oQ^2X-N?#3T5T!>YGDK z=|&)CE*&b6H;ws*5WGUU0`0<)5qXsr%r1hzGX+kh4Dv?Kc*b3n-x=TIPU1-_#BUxG z9}bDi=?hrfmNDehV$^5<@>Y%$=iV{&cW^O<_4p_ebucFH^d{~`7wNIrm37; zQCU%x$Fk(zV+N3BcuHl(HYt;zRTL+eVPBSqZ_Y6JIW9`4kgWBMI9(v`;WUG`++AHR zj(SuxxtCL8&mgspT2m`tb!@e@u9^?WQre91gSyO%oF@Sjn1)&=zr>Y*Y3ir|5kfin zWnP|$QWbw?%owcrWZmar(o_}|n`ReOnoG(nEd?gLrOI;UtiCM!wMzxPG2LMGo4%=^Es7N9Pb%g>e#s=7@466 zlWUaHsPab%ksUD)Lx!3~315nttZHo@k?Ujj8F+1S(_g04WyssGf4L!s2KS(lIygqT zkt4w&uTo5tl4r=v6w}NRUC51uv~VOMLlF*f0#e|TnDW;7h=ZEwXvWg>9LzWS8B}bA%=)aoe zt2mMz;wI6nIg%Q(nb@x8qSHgpr z(^N4%S-~N+67OI7p>8v(F)@{se-(2Qe6lV=|C4Qw`SvmSu9!zo8*cTxc^R0}>gxkr z{hq*9-@uiVl~(@)M?|aN%MsD)_i;qD`u!YQx~N`5Ma zjU9HBr)2mPEh+1WEmVwd82OaJtsEkBlH4CtIu5N}KJ*PP`8BQu)6(%u)r0NlepS|v z_H3_nTZtVqyAjgm12GMdE$hC77OFoV=3w$iJa09o!dhOLZ?anRO!;%Lx*PuxPx~0| z<9Fl6hj%{N;30_J2Wlh@GY2V}W?Ae^OVQl&3e(*Df=VocG<`oHW`es3Ck$(trjM3G zSd|X(fE0-xbXi9Nf=eq(N-M1e3ks|O8&hz}n8&e@v7`dlvp>gk+BgV1vl982Rm?9f znp;?6VoP;r)4PBZ?A1(X8fa%V82kPrUGCQ2hT+J;^H;E_)P%7$OShMNQ zB|LUQ&B{eg7e@k&2x9<#N-^5?}Z+T?$dESn!BS)ump7nhvBf zT@h8YtV>1{PjuPp@-YD~s>m~y7ciOrOeFO7aWRaYHB7E7o^P!vs<2?4Yc4RuEY4nl zHSgT{#R`8I3%WZN2^LgT78I9OELMVZ=Uc5zB4SZ03*s=H1rsbof8;QWX$a;oW?F(6 zatl}ph4N@mLdR)E<)x;IdP1e7TRtJrx0{0!uJ_j1R?Y1&Y4@Xa4w4^ z#9WY%iIJ6!A*3jU88`<5W0gQEJ533svvHgyi$y7fEEdfP5F4XV5IUVgd~YR|La2^% z)C)U<5Za9yPl0k%VF7(GaxpuT(0nC4fx`343(Cv|h1er8vx!7d_Fm3Xf(xn4XH!^g z@WxRXOCv5jo{;$}HkmM*0aX+g7qDEy@~kC!%tRr`DKHhYJSALGhIu;6AC4$6SC-^m zOy4jus~p3m0wR$pm8Xyhc$PYwLu)xUmMj#+*Kx|R8I6=8yCNf{1fpm%s3&{@pMs%} z5~9=uef9;6i^~cM(HAI;YAh&QKz7wmXpz-gFdL1AKYbm>icRHnz@bR3SX^2_1fVRq zvUEY=0v3L{j5!66B0^$mcjp{A{MUUj%L$lc^8?D^w+f$DiK8fVRKA|(=i#?)1=FN* znl+H|hu=-#B0sAVCz$D|wsJ5YQz=k}a6GwyWd{)8F@xB-BqRKu4bS}xTF}u^Ye!8!o%?BZU=I_E(>jN`*b6F`X)iB0csz20>%<4~lr4Ki za9Tkd93B!d!5L429N0gFrb=4)3i`1B6p}L{%OB-+xsum>%Buor-l;T~E7>Rq@PUyO zc7BapIbP(bY-z!nYE-F{Nq0%oW=d+aQ<$17-nN2*M4fC~(ZHnj(i?DIlk1su4`;xC zPe>a$?E?G_gYpLEw8Jcvwm zw9#jn=+nbYS{@GDlFAb4s6Kz#A+>VKyhJ)j&m&GD>oh6-kQ|hes~S{WpjX zy2Z$n_$NuRa&5u~lxpa7Ka(!w#gMik*U2qdPm5`UR4LtyHO=If(gKxICADH;o!m0F zLZM)yD%m8O&<@iuQIV>p7chxn(@=s+yYfPTbPZLedQ#UU3M<{^nSddV3LIs~<;AC) z)P5GoDHKe-0&!_q<3_)KOz>_7Fp&fZq@Gb;(K_>lPJ&Ih!*`V=VpCR@1 z`$f91NfoIqG}yR75tJd#3k{APLKcMv8&o7{r7<*^2@I81S;^nm$SYv#4^2_FhYVHW%+eLXl4|74waiYPdf3oipb4H7RJoi4QjG596_9`J+^+75zr zJn1aPE<6VEA|$-3_Go(dCW7Dewn28Z5OYl|NF%Y~iDwo1+sP4u|WARmq3+c~G!ekV2Is(ibby_ZQ zvB`*ofZ#BHFf*?d#C(M)CBx{XRAee8v&_{ZG6i~=y#ld;lgvBw4ndfS*!24aG8;&j zA`1p8Itt5tSVWg0IX~f z3*~tPclzAtFI3`mY8*Z~UTNn~ZKOp?l&nVaxeA}DNQ-GYGwiG^c)6^h8DI8|OJFstnkrolPG0y*dP}Vu+wV-u)trlGem9Qef|d8+_y?_-ly^2_ zWF2LIJe4SX3YSUw6k$=O9%yjo6+Wqew4S3*N$_GL*-GWoq9#-v-l1gDY+8bc2Cscs zF_|B+Hnik7iebh=!%S#!`%kep(Yh1dOe&&6hMX1$^691^K2V(9N=X?yyY(-R zZLtXD4;ygeDnDmQqjQxrGkwWYoZwmFTG6~j{da~${LRA>9Nl8HouK|=FhZ**vi^fJ zSpW7Jt6<$~WEHG?4)_1>XRLyTAN#9^GDbcBA9Wr>rn6#MI2sld7mZSnIG(}dQZgxW z@?W4H$J0^?PxuhHM){s5GyWg;-UPs^;>sJZd+)oi@9VwkrZ>8wX|`r>5D*2lS(<%c zv;kw&bT`lf-EA){ng9_^j7bb=T;d?2QKQBMcSJ{V4QeJai_RpIM3ShJWRe+1;}u3Z(-~2Ws=tl|X>0{AGnQ3??v8iS0j-KhVi*v(dd=^p zs8}CjMo0?zgo%ok5i<%EKNru0t`1(SFH|wMYOG%=L@s^dqWWbkX3m^b$8c@!jAcG( zr7xJea$2nq+A5*jCz8XU^Gptlu{IIO!GL}a21E{GnWS{9;zp)juxLhY{X(pY_~EHD zW+Ps4U#qZ&rXG;D_Wc35Wxi?VDH#~UZvm0TH=61-HK;9t zCDxcMtIkRHY?bXFksk?Ckl7xHa^wzlz4?TKvd*w_wTf9t2}nJJZ|ysTm)tx(8xo5B zP#T0W4_e5$KLPHgUw9W&+?>6;cINYo8rBkKc%BR0$&YJj@F{})&V~jnu^^K#pWM*! zWrVe5U&?0x1>geKdgyGhj-Nm0x6U1koN$UsqbKp00ua&`GuLV)+9Kgh2>`s^onZi# zeNH5yB-#_uA<-J2PW3*fuy#(aFdIDoc>uSg&b{Rtm9U=1_GaN_ldm9|)*KyMhvW}P@+DR^(pfbsvn&$#t(3Sk zBXPe`<({J?)kam`&HH729KXNJhwIQaM zXa3Y=Nx|HqOG-F(L4~zo+TLlZ=q*Dj$@1pvO7B3jdvr3qdIda=d`6<6? zD9G2^B#LU4`7;wqzCNuZ6V9Q4FMFP@H5=PBJuFOT;1jEV=<|1y!Z9sUg%thS1M^Q+wn>-hB^S=yiS-hI1^=7!j)pHQHn9xAi z%t73eO9587!5qXbC1My5{v5>ZL(B+Cq30lO88M@9#{B>oNnB6vy$wL6N2eof7q{PU zK#>udj$|ZHM>0~TBk9rUh~zM6H0r<{{OO3v!Jm$p9D?acChHuNq{Fu}>8jeLk;L;C zVCv=PWo6(iG=x_ytX(*L>B_~+v5^zxltuAV_V?dM{haHORdzj3{s2P&Rc1sMJI%ZT zS=avqA}s#Nmd>%RKLC;(+@?_04MeM4FR!tq5t74iX(?+tJHxUt&axXC8*wg6W3urr zBOIKwma|cH5u9;oA2K*62HSiA*7w}>2i-fGTc z^0~m6dXdoD_iu)w_E&|v$v z!SMBIYVJfsv~qL|f>r5*i|C}L7P^P9yz{mZtW01qNRwR1l$bsqsFA$N@a4v?pg3i9 zkUHViEQv;o7+9U`?S!+~q|9MyqOh>l!6?`X&9t(*nah%N;LzS%2%L!%H+?CM@xmH_ zkV^TBs&xGkioM_pL|q7)e%U4-&4KxbD!SLeKSC4nz$NflWoWLE}hno%kIj-SzQ&kp2 z3QLs8%5jsdzt8`^pMgST%U?|AS^6qN7UkiZt)%X)z#94dei* zFcDO*{8{@pqZ11%5LJZJM+HL>*uua#1Y)@eoQ=R@1P07Q;64QUejBAPHu?0@*(mGw zItX#WJBa#Mrs6BafILJF+GQx~4dqgn$6}fhJy?o)$Ev$&Fw3!43??Vm@*%0Idb9MZ zFPgj*jCJ8x48XB+w+VBs{0xl9SQ!(vbsZ+ks_@=Og6AR$O2CmMm>5aW4b)0bp9^1z zB>TPzbBIlrWHQ8FH|Su9%|&HPE;QH-aLa)wLPW7pd643@*o)LJ&DP3SfwT4_zij== zvy$PVG-B3jS|Mmb8o6N{wfrucewViHJ7!9F4OQmP+IIsQwU5r^K4x+`VZ9G%?4Whu z*Ey660=&<~eKaC{dSg7b>BIWg{XasU-y{ZV?g29SS=756yP*#f7>#=6K!GUhA%erD z7;H{kBdrl@!0uxln{=rqY8YhClWa3mjif@nu($@Gg6A(V{?f}(9wOjBL;NV>M9TXX zLohEkl$7#^K!?V3Y9qQ_PndbIdxzm#7~x+PA!+NBDw2nmXAHsL-f zw-6jd609*8?UGs53nq3rVvCMPNT;Tf7Uh*`W~fBgNGz1dKO2!!RnMDf%5Kq*4M2Il zO6QbtqVmc?{JtSN8!1G2917%9vuJyjm@*tkTb+ef>~b+o|3Qnj9IaMeOYwP|0`Vfi z^35&SU~XMs?~B1Z?2JD%23^$2o#)?D$8-N}3`h9X5?!5Ogez+j^r;N-H$WsqysQ+N z6uoXpS@Tt(5oX)h>GY~-l&MDp>d~R2ISPu-GI$QA&uKjDRnh85wIB3zJ7#k8d&l;s ztD=pO3|;iAEj#CQ6MFHcEa6(%U05QdAU znJ}CA2ZlQqHX}l_)Pz~FKWZ9OtZ;dRq|JocVq+jy(qbEfBWsG)hQtM*0sd?V$tWTRTt$sUk%`_uSq^iy?)Yw_lqs7sV|9vFEKbbIluMqPUk%Q_~ zA)luTe;6jJ`n3s5@xKcriZaajXKmL=ZYi~8@mUciQDwp`{u;mdKB>jeP=&+7M1>Q> zaM7|z2LI@1u&ak!8?6dggsH05o3K=%(~m%Rea3`Yf&MTUkl&u&b!8;Mt&s$EeuBk8 z1=wAjKCzcSAF7F>+fA7D{-PvL7L!8+IUWYI&t5y+01~>v5pwZ zB^cuTS^L&wYBNDkfzFXh)n_pBCx|Q0!1$eGy$aetgc1HENJq4nL3xNdt+QxPzfBl( zpp}yBP&wvLWfe6nPTeSfu`UZcdAgX~&s*fc-dj`jSwq8#_ZGzKQN~v{X&!5`DtRnI z5{b@4>sjMa%uh{xn<>W5#|eo|?Tz~VP4--@Zok0OFf-dCES}jH4AYyawOuN3KH!qt z{xy;d*$Kd7&)3_g_tVYTGxuCRl0;_%~?T(X_ zHW8}k=cePR{q~?F$efdI?dHrY{SgZ~C(<%JaIQI4MNb<%Ro9UaU-gtJPlWqr13;-2 z{ltVR-2bHu>M7hmk0kidNP^L*u8f8Qfod0BRQS6{f_NpG4?k+nrIJA23i2vzh*i{@ z;WTvyZeDLSVp@-5Uco!U*Q|=l8s?@3BM1JheXEeMk@T;L zq|ZRZ56T@-Bk^P8uTn#LLo(%E;vO-C*7BkOhJY zuScSP>POG?qsJYIL@V7T31^ufUG#b+x}P7tC*b^@Nc35L^id-es>DuhvLZjF>Oas@ z>H;K@F8?!b9LUmCmpH4ohVYdNM=J~;3HIrk{;Ik==2eBMrtkXKf5x|4leO>Sa9vx& z38kNt!o~HpvDTy>i|dn;PZgvcv8GIR@Jfq+>2oG&x5xUgx5%2L{UYnX@fWN~zIS8) znf5gJ(c}?^Gy)vyfN%^S(&2`HtifxJJ5fnGU6wy-Pg#@1@3Z{z=2(-oXK4M`n}{-`<&K)y|XRF?Y@}G!3*Chb|KTyrBCT#Qy|qX*d=K&5oT%sB#Zwadzt^Q zu#6uZPB@u&2y+gJ>-klmgq+8`OYqnI4~T7KwLaCo!R?@lr=?s5i2-R}^JDz=PI4I} z5nKi#y`${)ux1|4?wiXX4C>1u4Dm9EJaHL>PhJL*CoY5V$;%*o>dPPu>B}I33oe5Y zGM7PwL@t9c6kG-&5L^Z!5L^Z!z{?;)!OI{zfXg5{fXg64g3BNpfy*F*;AIev;bjnp z^koo+g3BNTCtU_1!dwQ?L46s7VgE7+!~XS;K?K6fAcVrpAcXW~ z5QhBAAUbR=gM<;`&5s#AMTn{;D(Nx^5xfi{PkkAL!Jd~v(wQ=H8H8|f8H9j;8AJ%p zWe|oVmq7@Imq8*>a2bTS6I=#yiw-~#Gt4nJ?TX*(zY#cp%zq7ofj?{Cl`a+`#0S5o z7+!&WhonP(14v@;U1P9vzHgw$ZOFz+PoB!L1~K;oNSo6%pavP^d@NL6?sfw#29S+x z^02x+QRQ3~p~<;60_5IffO;gDuM=Qqnuqo7y=(F?OWnIc{A1R0}x2PM`z#9I=dbj>r`(8&5rfDWJ!7nSY8jvt# zT|gi|y<*BSF+K%A z+Shysf74E4e7wN;kRHZ|+k0uy3&!{`sErRpG(Pf#@!^xkN1iY~eA4*vsf`aq+V}`A zFg}Eg@evX+J`4rMhd^L_2n5E50F94O(D>*8jE@e$_y`G%k4C`w2!h5(V`zLB(#D6O z!1xdl z;IOzNKWpD~kmvr$pbvsYmBEAC{M3GrU78pxp9`15Wi8m~@H{+D+XkUxU|A^O@{{b%uAE<|&6b1ZS z^r&^sUFhG~NffXfC}7gt%9j0Oj18lJV+d*m%n%i@JfVR3qym;F6fmDuz2%#c>V zf(sNdA)|nWL=-SXfdVEFC}0AC0wzEOEEH70IsgT%15m(10tKuQP{4wq0@fHRV1~2; zW++g=1VjNd5K+JceFe;Lk^&~eC}17b3YcME0W%yZU;?26CKM`QLRtYc_H!hr%N;45GuGzysEhyo@UD&PndC}85E z3OMZ&O#5P#!q|=5poU^S?r;MWC@;Cg9Yx3;Zcp;Ki87q{fcs5O*4G*9++ilL=`5=! zvD|cWvj0(N4;tDG@5g{MLu!00jMG3~59fxjlaU5}hy{3K1=3lYka|mF<0gD_BB0LH z)N6d3@fho_DzS@rikDgZYi7`zKg3+yh9&e-%Bpynm2%n**N*m}tNs}+6I1g~J@e+; z5O_ak>>gHzc>&14>SgDiZO7I!oKD?{EeT)7^DTpfb^J+FGQzu zoEl@mpf(0FpkWN;31h$~je$I24EUrm;8Pm|hO{vdTwn|c8Dk(MVhk7xi~)hb7!U}I z0Rb8Vp`bC)0T=@vfH4pf7z2%fF%SfefyU4nFrg$=3-=Tiaxe*j?^Fn{B8js zG4-=kuijvCc&i8ME%ieZ=YYBY0qX4ob(+I(Rq7i}z1VrF^|$t^OK~nErb=+0pOe2|1R+*B+qqw__eq9Ne0DXny6oU`^E(Q z%vPv0&+#h3mKX7BZ|{ufAXC@)wYPW0cL|Heuf6?gfj!swwYM)3IM+3P?d{zH7rVx< zy?v>`6|V7XZ(k;Gm7C<(-u_IS4N>iCzxMWL1svzX8U6H5WnUiegV>1#;n&{&oPcK% ztOa<5fRhQruf6?w0nZ{h3*Z+7tRc7z;1>m)<{H2D_LWl743~cG?Jo&$vjL1z_8tKi z1As~2D?lB9)0BOc0BZnDQ1;aVYyfb&vcD`qyGy_J_B8@*bLrRKzE*%;F8$iu*9maB zOTYH^^#bg1>DS)=iU8Lm2EYvh96(Hqvj0wiJCFf@eF7YG;n&{2QNo8@__eq9OZbRO zzxMV`0vrW^+8hwz6#%Hs%>w)r0MzCd0geF}r|ho^@CyLrm3^xK$6flAw{H{RcZsc7 zF~I%L6u@_r4AMR)(eP`ZAuj2i&!3J#l_9?CoiF?ttY>IP_Rbe85do9&fxhZ9 zf~iSt^aD&7`mT?S2@&vG6nk1g-<5sr83DB`d;5JV1ns@vF1FrBMgoWDBbU(biX%r+4b|M zE}d1&saNeR_&N0Kw=G^x$oVF+$?aD5`%+r&lI{jNnnH1ZwC+R{cuh)Y|4B-V`3~;w zS?+bFbY;(W4>O4?4({zaE;9%m+}m^AjiAgU`NR0vs}Rkfrs3y(I7j7CDZT2$^-x)< z&eX9va6x<=HX1~=_^#^hjWXbsyDW57Z*LNu?JhU2>g~;<^J1>=!w>_eRjWZa>Z;yu zlZ0`D)aTdX-=7@-{hZ{g-o8+1GlM)a?m7gO?b5-m?<1{KQs)XTa8+-231vZ$7~`~C zP=&sV+#>0UHK<+H+gk-!=BBu+x3|S_L(5gTaP1zts<*et+1>}z{Yqo_UleDPW2do) zt9tw5I9osefMwqqUyq^g8V_FfT>?TNwX1sj>tSI~LU+g6u?JW*8ucE54iZ9h+$+!# zLa5(;0=+^AoE#MB7$In)`vp3l4hSmu0fC@|07B_LC}6ID(1#BRSRo)(;==+~3rMZ_ zh`==(21}0$yja6v>X5)|Gz_*L6S!T&VC=BKyEF{e9v66zr6rcyQ6$(>1rW&FMJwj| zuIlZtiGTw3UDexn2qtGfW z>Hl42+AqfGW8R(CyuPJ1m?^v@lA+w%)}{dWvfyH_{vN$JUADg|I1J9kJ#x1HAx>ZS zj`u@wn70NZ-vm%9dm^X#_WlIl$WP!j-#(DIPBLQpSY)ykI?cBqPP~ptJ^y(m@hOD$ zunwK(+m9w*1S4QI{OCrIfqf`(BhvH^-y1#WCud@%qp)c!6esH1EVuuh*F|>%OWhQr zj}Z-15xjOfKYbthWh`6{7ck3LEW@TO^=y%6^}7tY7O(57?}T$5UU2JAH7y8y!4zH} ztV))Ptd?Wvg4Y&G>M>>4-&r+YdD_}Gw&4EYSbs|V8tD16_LX5$T-s>j$1O&YFZRdn z8F($x_t?g>bZ76uoqgcka9ty>CQev^@rGleW%CBrNG=)3qn!S%4(?QaI}H*D(BO_5 zy*P44UcbI`T|>*J?hY`r{+OZqgJeKP4&d#f0xGm|<8;H#dP=~rD#4Ad5cJ`rjr?s0}IyW?T%;X1|3^CX$MNMjv#dc+F zqAXVoKq(tqn?yvd&7AYvduNxuZ@7G0R}iP$4(J-Ivb@1Mln0Jj)lU3{8-oqyIM-gS z%9fev`8wLF2A(vyPZ#C_sLI~54UcMjOFJGDne+yewBApu%D!e$7iko7X!ZGc+(ca^ zQA^@^pSyh5u1~7|M+|-|Ud>b<`;~2H6h|c+yU(m;^}!6sd?&&h#1WHl*4(D^Cykj# z`xJwzKEgUAKgtdH9Kf*#f1ZI@`aL>=oF$y&W;viINj-d7wQp+P+>B3z zStB*ITB^Al)UXzErSxC7#!`=r=D|o^1>T5S85yBGO<po zWRk0#;_)ySj(l;-*{vA%C*+I>zAObF+_Eg`d}TG!Cz+?~jAgYlHingRbV~Pqri`1< zLb+F30)|s<_YLv4`hiO>`2GZpaa!Dbpd!g_xm#E|29YuEbo}+^<4@unC@isse;C3R zy8f;OlLg;%z`H_~TU?rrDSQUBY)6+d(u>wDZJ@PkP;N=-&zU?UwBV7*Qi=33f@E{V zxr^IJ@VOy=Iy}HlgBI^pZkfatXDpLXR;+67XqyS|-^wj7C9@S7(^EcH;r5k?fhvCD z3b_4BS>F@IDtD~Z%{Vr;O0z+jiL(R|=XCHv$Yl=ePP9SR6Zm5-{XXEV2PH_Bvc4ff zeo7*{T_0~-PU`G-sI(P7K;xj@X9Iz~e?MoQQBc;E%-J6@qe+OLwXZOScN{6|N*49W z0RW}AD_Pvb1f|F;S>(R~%yWm-NZLE05LB-fC@a@sS_IErA49JB?T8vO5P^#kcz}V= zATVVR4hHN+pnx}1d)Jt>gH2lQ!AZ)app%pqq9o-Y1PW8>izg-@lyC6gezZV)e-?mI7e!PSmWVd zaHhtuG59{l$Dnu=8u|$olW@vz*J*Sdj6IBjH9BA7)GN_AIYL*hW7Y&Q_1iX)gR#9K zD+y;}P!jRr;53b29N_8YQ2hK``URMTEnqA32}OiU;}Oq@ zoBtq*_ZS;q#$rH?Lg}AC7g`e(N<6M2AJq8SKK=u}0Y1pW;eFF@n`FY!E#O0%uHb}p z5&wV>Yr0%R*Y~@qD*svi)T1aVrk>3`<>pqrE;h?YPS?VOehf49k*(5SZjXEwNU{(iJmL!`$> zaZL;fu!r}*r-mXM#d6R_Z;zHSoU~C)#Q&Ze;+}J4qnKd0Q5=DSjbh@W8^vk$&Hg@< zs*2rl9puoH&ojsFd`}dZ_KSI!M0nUe#3viSek)>f3E)#vcM~Y~%uRsUJp?OM!n+YU zrE@Bsv2F#vy|BY=0xUqoD;Jk@0aKjkH-ip}O0*y7$b%1g^IyYgS zk;7Pgogj}c4)e$Y))jhv)9A5$v-%ORg*{YE9r)d6&DR6R3?-Hpk*M_DG+8R0f*9L-2`dX~OaYOa%ASW)+DYW(y2uwVGWl4*h`n2MtA#*S?A>AsRL9;exfKd2ud^$u z&oXa8L6{}ouJb9OFCG4iJy`M{9{lGnFZC}2`cHSerJe;_G40xl^p+{ZlLSt|l)F-nT;xS!$ z;$#+|Jeeg=oXp~rC$sp}C$kvRC$j_>oXjF*PG$*-oXlblUW+WlUWSulUWP}C$k91$t(sU2A80JGK=9PgG+=l zxH_m$W-;ua%wjk=nMEMj{v1pwSR$_>q)%osll^?UN zZ#Q3~wMyneB&|-WSh+qSuu7+ds-ZP9uo>jf+IKC28N7~$SMN-%4MGq5{r(d)a0+*O z4T<3j0-7zR&dopN+PA&4xx1-tWJfcO1w(7)nrgjh>Qw^8YU6Vbt=*0FTN>)I(%+@* z;%86;2QNy#zg9oyhrq}D7YQF}_q!Wtn@$huIds6EN#v!;N6h6**iJt+z$6M7C6(+ni%VR-?}({#A^Ys)!<*ypc7 z!M2<;h<#xa!+KdW_QhS~D7gN-Sd;JJDqq~YgM{-9ZZC0wWYEXHBG;O|3|rnula49G zY**Khb+E%@3GNuSoV{$$s@nSH%DuV@X>FZd{C#E@3tr}8$%@&lUr@UMADpenm-OaL zhaQ-@XeqvYz@5hGctu_xnA-$5cKl7nc>lav$Xq3+$`?HNWhvSBiB}5Vi{Rmsv&@qu|~Ae-U@7DM4$Gd@U2DiT4O!Gai=SiZd-(L)5Pg0u1u zVm4ltw;35`uwCba>C7$!(o|L~KD~&?mWc zpv&+jIJAWSz1*t!)FO`L#6s?7#itd~&w)xTXn|+T_{<^}>m^dY*BhTDS!O0!K)9eA zpDpOzMDQ76e;qhJM`8*hF&uyL^|MYDpDVG&VJtu3)Y`on-&sQJJc%t!_+LX_8cjOC z=pj_NB8W^%xj-T-6RC^B@r9D*K$UJ*!&BNMzNqLSG)Y|UAmpT2`6l+kHOCR3dlD<3 z7g%}HdpM+!h6GT+#>z9Otvo}t^74e0=aW`mp0M(K(#rFxtvo~8$_p;A@`Q|)7ZS1Z z3vH*XyqBwR-U22$`cSP&p^b= z6ZEY-!%0@22xH}SP+NJ1eJjs!VC4yfR-RC3Fd{VRGkl5=RZCQo zl_!E$UY^>@GuYG0_hQP3l_wlr#v$Nac_B1bp5cg&a9Rs(|Nj`I0e(U<}86x?8zDU#|@$HrO#h>sz{-H`i|&qpY(izxkQg%=eg8 z=XUrBo|T->Y{{p9-^sv|{TxCN`;+8~7vQs;rH<5T%qJ<3|3GZqj;3w6f9=Mxs4 zEbA>uu(%J-rS$HF5n62Bc|XDh_`(id?26{LzOJ*!zOnvZ5mF*u zTvf>Q*1Z=Zc~QM_dyKEjv~hpmwXFAnFGh=Y5TY?E=7(1hc4+~`yOgVM^B3XnX|zqT z31C@Y!-jXU*u!ssf$KPPCSEo199 zkh{~RtP+GKTKAyT(h__FZ-e!q1hJ(oP7^j;(k4`S?1{L?UXFVd8|)&OvldwU;I`B< zf6CMVDdNxC*Om^Cc$+)%Db8gKrVYi;MPG;)Sib6Kps@GW^*h~6w1!|JSh3UqV*yM+ zivGL?d(5m2^rw^2{y6h6PxU)5nrfo~mLpYzq*{XW51^!bzJ3>)SUQ;l@7*A%D zQ$#&6_*wgMvD7l;`-qx?IuH3N0?#n;8w6$zgIB(bP{bEZs>R6J%Cdf)0fOs+e+&de zi5zw-AZPEMox|@zp!aaNi+u!vOA)9zW)iofR*R4lErmL(e!0VHgoTTNA902OwhF-# zX2n+Vs?~@N6ZLtC0CesqN&J@WNPwDg-YQRp|a zrqrnG49RD}97wpvgh)J=fGs@g&?{Kt5MOop^hnFP7JP!!^bmB%>(+8KE8G63YY!|(e>@kEvHSKQ12@l(OGaT1Sx&RI%b&oJq9Fy*1peR1E6{ZYDb{oC4xFJu@ z46f%+J7Qv{DE;e~4Zg1c-(5&Iv>n+Gy9N*|IF7aWfuTRZg4->r!Bc*rKlclbSEJB( zPFUzTmLm<~j;xU~Utv~HTANU^WH%Ivr9l=jz&f-uyD^45xejAYW}h~(xmW?Up0ghF zGrQW)>`_0nA2PE$Pna2atJrB`I9mP*xrodk3WmcEBGD4H%Z~yhR1asGTJxNd^-F78 z4o5x0!^a}>PbhmB-Q}`9hs}_{7j}-g+N7BU;-If(JU?t=R!huEd@@Fj{AMZ(!C-~h z^)pgNSDLCXR*E^$Ams-SAcurA`*z*tagTrxg=e9CxtO>J#=RfQA2{s=5XMOF=+-$LCs}M$F%)hc|o^6UM=%N6NU3KUi#N#Um|p@HcWxsu(uL3l2W|x1&AmUYK?&CVTko1a8hGt_NAJccNQT%%C_-lX6Sy2ozO?O7~)3 z1=z|+z9p4~q+WPS>T>`AkDZNg2`b!@BJ6qLEh)meUU*B2aIqKOk|JE;g}0;#S9#`m zr>XE~;^ep53vNjf9OvO`lfETY0&pTheM^eqnFMRm3RlDlP9~^tNfA7YpuQzVu!f+% zB}H(W7v7R$Ni#fiONzYB27u%9d!(X^0pP`ZuK;xbaB%)A0oDMJTT)E30f5|+BGB%c zTT%qJdFGZBfnA=tB}L$J&)kwCu*WmEqzGJ(7+g%cLCQIR7`Y|Im^+Yx+>#=2(9^f1 z7(V3bTT%=k@ysnL0!IO$HU}iHR{)?kHw*Aj08pD-1ULo&cL2UBz%KyEEh%Pj+%vbN z2>dRS(;a1H^}HoD0wSdx6T#laMHPixQcQLrmX&%-is(CHStqz9#h8Q9nBb<8o6Q?TNNO~1;4$1rBU+y3jm8Rj*KAfX+ zSW9|xllc1Rftchq)Ql5fReBV!gfhM(SCu&Gl*dKS?#^@D@JVA_RU*#zB3G4IZp`y< z?LcZ<<3zb0w&L457PWIDLgA_s6UGfPxT?f)3?-R*Rf)8jL7ou)4oRNv@$hMQRf(x{ z1sA=l#KZ+bVhomUNnGgbsV$0v#hHSCyFVcorbJszeBy0H9n|BA6?nTvZ}iA)s7UB3Lb;zN$pH zM#Es~Q7LG#hQZV!f!AmlY&|A$yN1EoVS#sPSgtBDKU`H3(WZ(L(Y4^%idU7Wn(`x8 zl_;QqBUhD(Dfl-2=o}^^f#gtv_4CMGC0=Yy3ud@USChC}CIuI}_rFYDpUUUcG{M79Sdqxp! zn;+eNuxkYe_D;P0U{5W20*efuY(Lo3iq;}y<;nJgJ+p|#dS1%*gFQ>K%=D7CAMDwJ z#&kt*XTo-vW9arAi7AN0MD`Huxe|+Mjh`;MiD1u@*fKK_!)`}3>HH$9k%}NPDdhr* ztn^a1AMAyaa7ii^wx&pf~^fgW@|%8WNU+=U~7Xwu(d%T z*xDe#tqq~z)`kvXYeNUHwIL+f+RzAWZ3u!}8ydr{4TkjA21B#4Cck3-a#cb=wl)}u zY;6#nZcYp`oV2w;gxT8ALA|xXu)npzaIm#OAl%v@6mD%0(pwu0`CA)0Y_>MSh;Scc zhEEZqYKcnP+8|;&wl?Icw>B8;xwTQsl##6s!ok)C0e@>l2+h_8!;!5Gg5lOi1PZn` zh>LD*IQ8}I_1H_VU)PGA_C)o$kjFldf^+9!p@F-;c$e>U57s%#&cRM17B!}}HtClV ztBjKmRfetEO>OICpVTTR$|{@QhK-O#>$DQ*s~lEB`ZCHclN*1&fk$3uiedF*v{Po@ z-4?A2rmwU0`>?Vq#4;!+%A3_c7p#^0hYXk1&aRgwcKJ;MB1`)El3@Rix0Uu3nK8QVR92OCG#2v^VI{r(0lF%5uU zAdtoT^M4 z9Wpb-pe6S)YEY($`#u=0>=z+i93`w)m6IZIo1$@JRORYO+~t0`uZ{50QMNRfR}O}mkAH=hVuIiUw7I~()$tS&)PQynfKEtNx3DX z_p+WL_8Z_=3*2)QxV2c24kYq__f;RSDxZjuKV{G+_sZ`? z;{G`r2XXuNNZflSPKrUCGgeoF9OvU-MC2-qB60jk3*-E8P-fyd4ludkWx+hu@d zg4a(CY2J(vpz3ZJJso&lx;0&%Lv6Yvg>;)Ht!~w%MpTFSiVeFq=J{i!+(& z8bdjp$D!c6-8>SLM{ox~b^%t8Xho3!tidC`jtBo)14mqe2me`v)I)e9h^a%xn2K1l z7Otq6e#RLU<42t~s=8w2<_Y8Qr>ncQdCL0c*5;0uMt}_+jT@$Hn>b-4BiC1qTr{>~ zWM@~?6v*%yXTW>GnWMSiIa&_1jodn6+(;~Jj$Gf;H5wbdAvO##el-8#Dp%KrjwURA zR+~1y09uv5tFb!kFMj@QE_XU!3`SF~vD!P2gXNg4p4eaDqI^uRp4eaPhanfNp2W=2 zF8eFBM4#kJYb-p|<&3!x8M?Ci5i6FX=B~NY8oSbBMsdBLP`hyX(v|QH`w81YBc{#V z)Y7_9#m*N8nwVzjlI zh_w~tPI7PgrgB@%i0?{n)NDJv!F(ybx%}pT({UN%%;go9@mpq zY+Lzvz`jZ&--ea#4(Z9WzO*Y$alSKY|92!zBH9%OMjq%Bo;* zsZ4!EwSP76UM9Y8fwYw*$_0m_UJ3lD)pAqGEdUo)(GuV)d}ekSz)8l!OVi7WZhX?HIw(5n$!aIuN)jk5z? zh%c-)hy@@664xp2tkDUJZU|{3XnqW$9=b4WC>)yz>Y=Qm$C3PiNqUja3QSgD;ig2I zYbcxRMKDvMTWly>tZ5RCqu>Y%Gg8)YQvVsKKHoMOT?ftn8_l9MrZ;9;vsK}*Oq>Ve zWY!B3r|C*0qtOxUgB}&=z*(Lx&5=6PunrX_k9|QMejC)GhILpy89d{D#um-=G*I!6PQc4}%(1BcqZHGd69~ZzG`NxV!-z;v|v&y6r`*+JUnKgBwL#_@Uy9DSx-0 zjX4!1@KuxTF7$_W-CnGw^<}UhMX>C$ak}Lx%ZC2Ap+89a%bq4ZgPQ)DB>Mb>0cRPO zi@|WI9uk+cG4Dq1r5ITPybGYLuSp?oG}{0vZB+276XPo)!<`%9CB-Nrl=b9jb5x|X z6D;AY=Vq8>iKu`>`I>+}ByJ5RtMI~MX!^5X+8UL4#GkbKhhOoEKV_K>=ekm8j#EBw z*^K!M<}H6Hg2@c7oM#?Hehd?e*cNyH4YUO=j5V?W4j7@ID?|{UA`TSIfo!-)OzVI)^>q)8e#Sw@ICZ%Re z&)KsdSl4T0qQLdaQc|8|o*LQGi;ZCu=`yr0mZ!dj)Nz@(y2VzEK)7uO=PSBNV@++{ zYd2vdD|s_5jf_mhjK!-!APtV>^}_FrMa%qi_%-gMy}yX*Njfi@u5W2n?xEgoASR-5 z?WT6+J|?hD7|>yXVuU(2f%%Psb&m>auud{oxi9v<5v^1O7=>W+pxl>w zA4fY)R%vW5MoJ?)8otMe6TXj^NSnJa_hzT~K5>#`cr4HL81MHM*IfPXDsTrE%Dv(R z4UHRcTS2))3Uzn+*A#+tRBn~T*cm^=m~@90UJN#4>A_~hvhADKwryH2hf>{P66>W0 znMfp>YPdvXrt2+_MeTe+XxL=72;C7@vGS+tlpPVk;JyLRe~ z+NIbdKkn`;TmYMzzCg?Rji&JyG+fZuflZW+%^haRR=N8NIeP5$1ud;T;%<^S$25x^ zym1d`Rt;`W_>COy3M=(H>}kMYvLnyD_cn zm%(LT^X8x>?vPfh(k<~pM0X0&FrAaI6r{gPqDJWS$x&aIs8KrAvhKBX))y)HZi%ke zDSJlWBhh2i&uwWvZLBHo9C?j#@0E&;^Lv8}l*+wNkP{73OEHA}pr9wGPv6koxN#ZP z&HaL@Ne_xt?gLWRjC4$BQ#aP!2PJN%$rmRQ8aJBFcjZ1LT{1fwH@$81W}F0eAC{=a zAv^6ssz)TME)wM@dQ@W8q|a|_Xo539c{_Ix3BMbH@w;?O1NI3xXi>e#Byv+a#cW1P z2MjiE6S#*9=_R(^A6h*Ji~D#X2bHg;PDpSi29xWZgbbRra5IQ9jp>8T3nRT<620gp+!yRQ}Un6&FXi1Phf zgcQnsQ_9YYxzmewgRsZ7Hg`r5m1felHn&!AfsXN)aCD{Mm~3j%F05^)%f7NZt%$b= zp>BAs&7E1qop(>`xml8ruUY*qV|TWob3;8H#LSVHf=EncN7$V!vBhC*bW7NsC$VLr zd_PC-HgIZo;tgbXQPFbEisF(4un|EM5dx1v6@wVI>8d$xCs;`>fL146JVO!h+KF zY`P?hrO#~Z*xJy6k$^$j(h8rgf`=vJwL*8MK$(!Gu((-*%k|~HXL0Uq;oGm|2?*wt zeg^E|3=#h3)kEX7U@5ve)WcTsa|MvM)nok@L)!)~3a^{>q*;l9FYefkkYc>qzF>yJJg(vPQm+pw4bIvn%)k zbFOBBf`Q~@G^l1o;L|`2P*!W3mm}%Rkv#sf@ZT0vX$#;K{`+sC%5un|W5V!()6iBz! zvH|-^C(LB4RZRydEjNpK%_AtSH=C{ZX@C`Mz*%9l!A-7BA%^J+C<}M={ z7z6(KU282Ff5qhXcR?fk2xlewVy$oOt*FRtsEBTWCN@BoNKi8+$XY5D{Ju%gr7>&6 z4M?jiNI12Ezc;kHfU5`{5tKG&e z&r8_22Myup0}cvu(YVbEal!49dx5+Z710b`N`{7sd|gI{tU4`SpJ6^f2bq?x&r-Td zFdl^AhfMy*$nX_LvQEJ84^kP1KrF6}D4_!^z2@{9;d4U3?d9NBvv&&#q|6zHssamU z)~%+q5l(HS4Tdggq&b}n+gkZCdA>)?X`SBP(E<0i!UXO&QVZ@fN%jT|d^(S^xZK4%vGTLN zD-HDwvX_P$nMxpy_9mjG(W+*fMw^EKexvwh=jhd&UVKX)-PzT_d#mOVKb?ryM%+8~ zpYa9i&yd-eN-swToVrEJ&6vcE#@*$%cCL6;pHU;VS`4Y+?>D7*S?uA#rH~J#QtLE9T9gJzJHDszZh|}7}gC`MeM8? zro(9*ASzbFuu8-2=X$6D6`M+SytH+AqfxPGR2{i#yd@l)&WK|0n~ns+dLl*#ld)M# zfk4KwNJjvd>64 zrN|=PYwlu^Cpo2<8JtoieH>pyb&&uE$jm842K6aL`JO#aDasS46#3*SMS0?sBA+~^ z$frJ~$j~&Lc2l0Vlw%qc}7kyDBc1*a4V1g8`U1g8`U@RXuZ@RXts;FO{c;FO|} z;FO|9;FO{ucuG-YcuJ8WeM*s`;FKZ(Ii<)z1hs`O)Fd{sXIK!t1QME)Rol+!%rxfL>Pbo6k^ORy1 zQ$|iH5)Mu&67Wwc3ZXfr$Z+J8BEj&KVgw3KDH0bwrI@|G5!-23aPU}bAcQ%1O%Nyt z7n>!J3$r3#c2pi#el~Y^HFJc(bnW+*+aZil{_sr$%s_gzH?+33Vl?><4E8hgHfZ-S zM%)Pq{&C_-9HL6+;6-O7c(HC`e%8u@Mw}m{tK*xQ(>g>KG;VL))GUq+1h=0!m`eek zCUAiPM$d(YXccmUDQMN~p$0;JB`6BWuaEc%5$$b0IBFii&aDlY7vI7WzZGzAj@Ri% zx956b^3Fo;SKolR!Wjr8=Hq3B5yj^KS_%k1*Sj6{5w%fLzXdO(t?;DSZG8vGoOPQ~ zziukK9G2AmVPKXoBYXZa)pd=fwt^6zWGDWbYiQ}o4ox^ASXjiy*` zfIUd@C7l8BS*vOo-UAzW^28Y}CUzz@lhm-$g)1iR(q`zVT}?wU=>_x}(hWHv}3suWec1 z-PVn22(o@LknmpF2%imt_#P1D-!heZ98K{&dIrs5Z((cO-V{|nZc+_vtiFlZUna%k zV!7hvU*@nAIX`Fc6e-?40Ump#K@aj?KC{>Y(rYK{Vn}+fPrBxWq<0un zmeyuUV-|g@C7W4cB0=(7~Ch{tq`^6@rdk&hV`1!VCu96uHT znPE{vAQA&Pr$EQekRt89RfF0#p>tRQU-5u^!4;P^TWAx`fh9G#g!>XKNJo?hi0gXD{x+-zDfvb`wX^N)Ed6 z9~nwY%CtbP=ZH$S4}U$3!1T^aLH9aNG-Z8daVXHp5?PUTG;=uI4~$_uCIjHsLLHW^Xi;PZpL);W8N@mT5Xt%$4g7DLP& zUrx#q^;YHoW}+#c$8|JxQHL%->V2*%ubr-867_~eh)Tp4ZC9~HaZT4x0DAWYS!<)({g?7z_x`N&cpLVZLTcG;j z>nDNIypX4};n2oU@M(aCz~{B&6(OmJl8oSbKs!$OiKR|^@RuNQy;cl`k(@HLHmO*l zZm}m!ixH3iRjf$k4@K~}!-5-L8h<2$XO&`obe|o&Q&(xEe~t~A;Y0x4k)N}!a0Dpu(y3v%3laQSG(qEr4z6bKk(fk8 z()vbX0a1}Pki_X+W@v8RqRb<0y`^4(u*B3)`k~BIyab|;021QRJsDI|(r(-$NCWJ@U-!BPt8U1i@9 z``@J$RmwGn|KBd9WTNuXr4+)!QVIcoDMbj)QVPS7r4)kUQc460mQsj|E~RAE&*6Iu z&ed*gZo(}~T&7#!Y)(=s`}`P>EIa=W>C85}7QhLp52F|gjEHwZlSArUtwf>U@k;ao zss|rxI0RB({osXBe%8J`ofvlOWQpTUtY+0nBFwYphaFp3tzJC+9^42NLThP0hnG)} zHxW(m6&wS41?Eu&-$7s-0+^8pX=5xT;j|mGSxE30N=TE!;lWZY{D*LwQ3yMbaDHK| zgX?_i=BW{D(GXRmRB}4JnT?m)4jToANk61S=Qcb8gK>nxW(+BzAk-9JH%%&!w@9G| zGj=hy`NG6LGo!s`c--eMu^@(H zq^rkYaft=*4tuAevGT9(wJ{waa z2=vBTuHobC3~^JB z-4Hmtgxxm>@1$yOfBcyjjbazfHwg5%rd`0Uo?OzJt))h(g$Cj2o`aLuBm}CwI7Fa` zKn3*iRutt~sY<{f_pzup2$g{Jtgi&n6`}<6F!Z8wo`?(wNt5mml#EbRtETb_hMZ}l~Zpo2fG$D$n-i}rz= zth?B2M$<^IB`Z2n-PAA%-J9vD9hl*FU}mZc%S!G8t!JRbeN}=^3mXDmrj0~iC!QQ6DEx-UoE=+6eO;vAow&Ur$?bZ_xxcJ)qv7wS_7hIpaH|~OEDCg$r71m z8pIgn>lEjN=Y-cXthsTnZRTUpT2#C@}fcY?W+OPw3)-K z2nr&2JxTcQLU<|iHK@EAMXQ?pVq{FZ6q#Kl>V^|~>e(FqN|PJrg_op=2K#-_y2O87GV{73^QI(m#o=Uv13sd`k_K304n+MPnE`RUmFWRS*2^QKtFK1m zB`TV4>g=#0SvB_81CJKBQcLmxJ#!hDDieb~WYne7e`Fz#_F4GCtouD~A|VYBacwL- z|0Oe_6={0V{L-7z*JH?2X0$Q}Q5H7adLs z%8oX5QbXhFSJ2StU3Ruv#bLYWh1Db&&ITgG&scwB!g>cK$r?mbS%s0@P*(J9NDpC- z#t)edBw0P?F8vtQ%t4VKMK5EiDz$H1-&98D4l=^@+yNYTK_z9l=vNkuO26r34&hJL zjYMbo^Yh58K@0B*L?_yt4!hd%*p0E!e!50a_;QfOmmh5{g5@b#3*pF^l=P@h$?!!w z(--Ni=*m`hm=wApwTW{5Cd!M%NE7w)XA`sS#qe!5G0{S>f~~t0*r> z6O(8#OwLH60piRM5gnW|grg;r<-gF3`nEEz6<}JRO+`$7ZE8ja2MQ(7A1HckWk{M} z>XYfuy|Tiw!MRsJ^CDksLX=)$2<-!HTe}2=)gUA+Gd=m0~y`GL8m@0zC*pGwcTY z1d@&#rOSc}#H$UL*eNb#A`>T`G~RMaS3o=#cgJb{7@6{)CKsMe^;b)#Jx zPZk~SS(uSULmV!A`4WcG9cSvMfF4gk9EHe|W7? z1!FY&B8GnDBs`)?GLu!vNla{*4wEp^G{_BoAARH0cBfZ3IFr^0phLou2tf!3EhgWg z5ExY+|U>%XCl z3dywf8=WMvAPprpkgljmon*>J)eveF87#g=G4IWut{4^oqYH!K21rETOL8u#`)i0| z0J3}o5YaCF3t(ir4>=3#DYE9PqNF~hxJCLDZ+JnUqD3ikk=WkJ&0pvXS&{Byku};3 ztN{3hX`wDfUeVV&_GMJTL={iph(MS{bkQIrx zTAf4z#F%6O=FZXBWK>k9{~L9yZzR*Skql)$5Mhz&6H2=Xccw4g;kJ?VqZT87+X$V2 z*A{JKb9=7*K`xR6K1E)lB9HdYPgWDr{iHzlK^C2@rFL1dzmAD!{(tz_3s-e)^{<$f zSk@o#ifG}7>Ja|eZi^LC^0W3$ILbVFGu-}67^i(3;|VXx^>BbpC&+Tr>9nz;@e6sVI&QMy81_h2t!%W{+ojnL5EqH*}tDE;=rYin~uQ)hr~Y}?GF z0lc*fUvoF5`L}A20nTX2RTiCBBZ+j7=XG@mhmBF5A8x|6bsaVZYXECaw#uy$sde5} zmXmnfa^AA$UhHfiwf@ByUv{qD@mlBl^*4KOd5c#$iNnsOF6UR)Yu!(JYhH4`yu;h` zwDS|I>wt6X4tsz#Z@X9fS?^wF(&1k?SzblVc7EV^qhP?k{>iri9E;CI_^$1voNZlW zt^wk;_$5Hxvi%Y#z0T?Gaxz98y!F5Xm%aJKN^ireCszIQ%kaEsKjCD&=5)_RhDW`5 zbGB~1l@&{lzVyWxy%Hox4VT??AIL0cqqoPY zdAscs_d4nO@AbwGZ$YX55Z{BCtG2)G6u$lHdS{=t-?@9|CC-m_>|ap&;>uNHorE_^ zhin&PU@nBfR@ZSLoM2RZWRX^?vwPjTmTizK{NNEBorx|$<~a0*^XWR=w642;9b9(- z(p0+FK*bbonrJcyRM*Is*0V^&9z4>!MncX|Yo3$gy=`ZJS>TV&GWc&P%Nylnu5-HT z&cDdH=n`k0x6a$^JcqR|XLZ+&&bCX&I|IC~Gghov;k4CxpWeOdYUil(x||tx-tKB| z_bPAqC#IacYSol;>z%cAPHvaC+v%w5KKD|mPu){qfA7WB-hp>M;SJq=-pt)EzO>RQ zIPA20b>8URW4zJc?wg#ouX!)paWGXXI_40#{R>+&Xent=ep*~NPB=VGqxsDoB=DQo zZ%(vq(8@k8xru|3ge=+Ix${i3UT0YswAa|xy0wq{z3}h2D+ob*Ls8If-+A|a|Kct9 z&(5vY-@o14wZ&TvH3IzR!%nZeZ~C-1wrf=Q>>&1e2ZZbDfL2rf+q&)HxZGKe4UjDsQZ_)O+nFXY`(V-lgYGxyS22 zY2F6!@nxSleY{iYjrx`3_QM_C8xpwF@+wv@xDa70zAk>#ZI>fAZ{yIZPGa3#9rJg; zHUG@BHs0^$d-+b*VW)GllQq}*>W*~_pZcZqs)Z5b^>QxTdGy7Rqg&n@QQhLzOmZIH zIeEA9vf4A>I}Zbx!x)44jKeoOckVbk-}$Mv=PH)vReJ@`?Dan9Y(MN=wWIE)?(To} z+TQ7Q{$0HWCMP?SySx{juk5tPTF&oOmy=^xTh4`tozL$?E$wNR^BxW(TF&Qo+Etc4 zr_^4Y_PcXHZv&(@{*c~=e;v>^aakg zQEQwb>*jdpU50vnYURq6PIukB-TWps2MtM-rlRW>~@~m`G%8!$u(#f zr?bw<+T(PtyLRPy&i4He;-8b4>}(xXGjE&I{I-*^&got^aoS2}dmZpwobFLh#@sXN zm(Lq9f6Al2r8EeepkknDf&y#7Tcht>aN#HZbN$U{;L~?8d~XLTgX7CN=M&w{&bFgO#z)1S z9B)tlZ*R`EZM4Fl(H6G){Rgzj|M}$XW6rLOD1Hnf4(Dajxe@v~5F>=)R#5KcqOp4l zQiC+X>JMmwkHHcvgUR2fCfwxXCpo}?%EupD{qC<@$j6#Kf6N{V+Zp$j;J^37<+kT| zJ?0B*u2qm{r$PMCP-vD_f8AzLO`A6HI-zNLjFRJi!TDB!?V#Kt(j71Sb<6#D-J#ZZ z)^~Qd(|eR=*ne$+q()yG0EVv(C(s0HPz|bs&6Ba#SO0YNDyL$<({%LS^LOvwa89+8 zI0{=bYWmstc6WQvJ9%E+{^>7vzcXpd1}ER1U^$sxuuB);c3}r)Z_Mv`O-Lt2giu5o@L+!^XQK`20vzh;9ENA4Ha+a<5MOA-AHGvzqZbw4wt3t+Q(Ffisx8W4Ovu9 z!YY&o?_mw)>~+r6I_GS! zVwLx%ce(RR<;}%w(qX&=bm6(jo4?yT^9U);aUN&GUY14=i?G0zqPr zv-PlZEna;3b~QWQuQ^-2!_Jkq*UKw*3idm#-rNH#9lXx1b8fd@n{p$9hg+S(b?fm) zp1x;+(;E?)hvz%}@lv&RKVIubIa}wR?qpAPwoRS^>``YS{=L5AjVCX5y1h|e^>6V~ z_ItivdDFhT(7EWSGiv|p4NlqH&U)|Y2B!!weA~UFoxAZ8wA#r#>^!`~JKE7b$N7?V z*ya-9e~(Jr*0rrGVmsaymBz0koO%I-i1~Lawfsdz>7&|`9t(n$-RSHVa4@??Sbw_? zD;!4L{I7Q6E!bLQpI-R*ZC7_YXOF__!BJ5&-HA|Kb#ka%$_G$#u@cx;LGTU2i(m-?)WqZB~4L ze0AqdPM`fNoeghvcdlt0z8o%@}!-hM_sxpV(}kg&SPH(%}KzVY}5ik!07482*1d#9g-h$5?l+ua-sF`|%iGTQ*PMC(UwhvIUsqM-eUe*BC=db^EK)I)f(1)R zp)JL!n)Cr}DR}c}n?m6xO>WZIJT7_k0Tp5?54Fw&EiiDD{lW$d;jR%8rX#)8V`IQRkG>a zThIPl>YA!)siOwUZhgz9+m`?K+czw0KJUqa#i_>KsdEQX4GUB69!TYOrz#ev`pXtx z29mNF%hr```2lvhR+v%e+JyiYrk)J8|2lQ)iqwJ?sb%f&T~j8UQgfSXQkT7yx?tgc zbmSGOXE8|Kb3>JEzo)J(Tll`)?n~VX^ouBNSqN}p>eXO-s`sVKHm@n$g~{->E0#4v za_Nj|sXtx6B6V}gKz-NZc2A>H3AKPnB#>VQ+p2EVq}e zKo#gwI^$$f>bNi=K$2FxIhf}$IxRr8{69SCrkA zn)6cX?CtlCJl>J&AJ}CsJv|va+E+oXDVR_#L{GW*c7wlb^5g&WtD_$rOtlQB=G>K9 zIh;D`;O*EnKBvSil}|5Q@w*Gl-q(#7GUWRvKZ~90O?%G0_q^08WeYzHyX&!}9?TB* z+)*|ax|Yqj^E0XRupwSCx$Hd{I8TuM{F1Uk`Mc(})Z5MeehGA*{AB7K!}q36$ENpf z-%h=7eOaYAuIxX`&bv8P^%4f^>@!!qj8)}P?QrQW2NqP82obT zvIkT5q02rIEKHsK(xut+%1*Q_QT5pmcBD2Ak3OE7T6%6t>Z>=P;> zJ&g%M+0&^hD`ftP2r1i;I;shO%^I!)Nvf(F?q4#128&wJUNtN0yCBzrZ1QbLevdiVkKIt@v8Ku%x`Y^xi4u zWwl3_=FCayrt7)+_!5Ai z725SzV%J}$7L`|ibkd^oSv$q9o5il1j;t-O*-=(ozU;=ME-61$lDZKVE`x3dEkUl}5bZJ9^KH`}>mCu;+c^dEckfV5f!NSx> zi-lM1(Ww(kiiF?Nqf=9gU$<&FJNLf5#$f6&QH1 zq@PH=KyTIHDLr$b$s48r6_O|QhER_;Ld{Q+fkVBV)DwN=db9FfWw^%d?aecAxiwJa zNxi*VPvpo^NDsl69f5wV^cp@z>E$OR?$(syUYNh+i4CCVZJwu<9`U(T`rXaa?{1QQ zw?p#8jgyy@=enmL6FiKr_6Yjl_t2t`A`|Q{FI#MKZ{j63ujz*(Z|uw(Bk7MSkMXuc z*iNdF{0L z==@f*$qjWx58*SUd^DXFYzJxAy`bmagj$u0p1qB6C)dZ6-!Xc9q1HR3_!kwQ-;ah% z(tk7MjEbkDh%d>{8ISkiP_753ItT}{U@WI(NrksyY z8poxb_JN*z)h(u0)ck>TM?kk zk1o9wr=>@it})YCTg=fcmo{A8m|4)){dc%3d?Q($BkJB81v^10S< zF??>4{G<5*86G2SC9=*mWSt6R9mzKDi=hzzVyEznfAyYrA~_i2mK|Msv4SQuvtImL z^Q_mQ#E|*{1s6#O6!MSY_fCN>x^0Gc>zaf3y^22}h96V>QpHQZ5I*s5&q1%4f7(4~ ztcYP29bI}w)Q9+GoAQr;)(vsG&IDsA_##?Y*mN35e-?dm^J@Tw-%100BM6sa3TE;y z`R-A=j~Hq*ekxxfztrPfb7764oFCFRfpE#utD<~|l`guK=>78_l0D>Kpnqj80^Ql zgYe@5c>%lqO!#v1wdFZl#Z07~|QAgikk35i#udw4)x_A<_FUWv_dHuV7$};>k z^=0zeZ6}%ElEyO@_J!@yj~P=PdEh0J<=bhE9-;_@`DIf(|koc;mhCF z2z-mxeU91GF1UFH?%0Bt2RdO%e~@YE?(fLRGp+%CsnR)s7YBE%M0}?&{4#VXX0iPq zw6Pc;-_837xur4Hl*nTI&xh*=K;PHCH2i9~vCVU#<*+>V`EjQWKBe0q6#E=_^b6wr zVtoD=r}2j5toh^0su!HrQ7-Vzr00#N6`R?|}Wv`g>C&TJsR2wQa7?w)EqhdmG^VWze%L8+4hj)3+(x27cXUtGjV! zLu*S{*LsAd?IZb}882_{U7u+m?7_zkE{T3yv>)Adc~5(9u!$c0yqbHK)(ze_mWE@IaM`iL{>sZ$)cy> z!;`to8}&=fi}Ao~ODlSCXa7KFYk!anQ_AYjz5#qpO8Z^VNmh~sHidpcxZt^vf!^LA z@+~Z(Y7Ox79()%ODI@gsM050iWxZ#V`7~XRlmzJu6s!wTaSeVRtCb3J(?;U;3^HC* z9!Zyj@)C*uK_x$;i^S5PdW7&ry7Gsj@6yHZlX@01%RT%{R!`)yBK(ZvN`m_56?`Q` z5&VOqjtI5{bKWs>I6@Dq{wb}Rq}VG;V?H7eeM^Eyvc5#^0V*`aLacR89%sVs&NHje zQV!%;609b;GS69rKj{Rn{)&S1DQd=bpmo2dl|h;B_o=F&Jdzh9rFsD$O7DoC?ZbA7KG^ zZ_SY)9zU=)$2;|G>al=V7Zs|nN*L>rp-9E61DuXW>Xi!iNN@zoE-h z-hjnLRE8qfuKGotFYTS5_guV-Or zD1u;~h`pYORIDu|x+&n7dJWzCMFlT)>{q1~T&3sI;DQmtSA}Hj6}%%vjVky#J(mXO zj}ZQ2NXEFL{!k;{29K&*KXjU=$>@QsGdU=4i0Z(_GqMl&dp}f?MR2{*eMe4@gKs}BPD-!&+L#-l6$+o|;^jt_t zFkfh$H-qqnHc{w9j@N2}6w@L};*1h})ery97~%m$U0&(jStY^AC(b#1Qc#{=U1e&G zP}IMKS`ef~e+Dh$ZL~nOsc~AR3I3f!H4tQ5)dz#Y`7;ND8G1T@=8WH6zbW|L^{4(W zSYG&2o-2?41buwNZ0jHLX470OO>+KB{FyQDw2*revM68jqyI~#QA55c{Fk=7^~s-K zWKo~c7e5Z0nBa4Y`mbnW@@Cw>SxroS>_`9I#3y=ragDZXvz}!{CA`yxL47H=$`Pj){IFfpTA8@Ef zfIh!xPz_frxL(i427O49TY?$8CiMsJ7$JIFSc4!{z%-KJ zu8^vbHY*%S6TzHA)e)pwVr-Ka6|`)ztGJfn^$xX)Ae9qdYe!h3goKIEdCG(ONzf5) z(rc50TyRY=-BT@2R|-1Tp)Y~EA?_a5JN%Z3bD&{G+F(qTf7i4cQyWt(g4e#4s0M=D z6=egCrQ1(+gakjWC`-uF?&*$@-~)=Xge>g~2?9ggpj4VAtAv{5ki(e6cQ4=H$uqLH$%c8b}%^KlkTlc4)?i zWxE08TfHu3bl_XvM5{mGy5wqtv{c%&$=Q8}vwJl`c0x+p9ea(7?^OgtUti_>dR5%lA6J#X z5UNfv)U%OIdugZ?!7Ci9k=A@ZMA4exhA67u<5X|-^=ypmIag!5*2Q@B2;t?5E5k6| zU$$$KKLUMP`_KKZAEgN%Qq-iNX5q{cmL@ApjN^WPNHZkeQ!byUIX0bDxX1A6 z?*f6%i@6)c?S1k_Dc@Mecf z-=g3HA<@Rg~ez!V+hC-6aaHbf`4JFDc4YW#QhCj^NiFs*WJdOiXvbj2Vj1qnVF6 z0~%?-KRHyIAf@1@8^Lcm9nu6Jbto@&*61Z#S{l@NDQuq7EOczr1nIsxL4O6-v(qqM zp7Ez6L-_SnK3rBgv)XQ!UUZfxWt(#Ukdx9x@C%AMGU%VaYtp;UELiswu5Owj>mCcCntZb|d(pLp2cGt0>zkS^8c`Nbs=;Axl4Yg!KduI#dI}-#An~!6VP8 z3FJT`A$XcY)f2qfp}Z7rYU9sw3cyT)S%+#Mc)OyknJj%iBqaES2%#3-iR?OE#WcZP z4%I-AV$d5L2L<-%`2km}p5Wt(vZ`vqoj6xr<0_^JUg=N`+Z5d4P-%jpQl3l6h*qL) z2yReDsi6Oc5f(N%?j9=|+~i2s5o}h}G1z23Mjozx>o#m35lew5xvM#)dWVqla%o0Qqf8L4h4w50CaV?X59|5#q=IJeA5j z%}@-2kl zfQn$q+jHsD%KLRaV>(GNG(|RuXv;pQLS5VzA#*$w zIIh$JC+Rt1BK#x0^wW@ppnTmz4zvrwqZB1K%Lt#WxMPF8lK9Eh7QDENp& zr3pT*sPdqHQl3Lbi2qS|eOvx@;(z8?*3*fV&YF69X;p}#8`g&?g7i#W7rN<=u*yRU z?sKTLwKn{Fle%QLb4>$5dJ6;izzA7A?pS%9iuGnXV;gAfU4?5g4rp=G^dwGG5?mEp zU?Gy^`7lnxs6JKoD-9NS-78L$Ac-V-krS81NMd+kj3D@P6>erlEYM8}Go9y^o}{J0 zTud|c8w>b(`N z$?-IS!fYh038@H!JYktg&WjX4z97i8yB*_M;;bHo1Rv76mXM`?4mlG1U4)P&{-OdL z3Gx>imLp5=a)VPn!8;UX36;Hfdbd-hjv&pEigj+AfnXzH$DlP&Ei>QAx0tV7_r{6O3D%WZc>W7*RY`LUX`YWXplL_DLaC2NMQDvbc%+;W{ znti623%{f)KBs5l^`gRO>WoKlgm)?~VE`aWjU!24so=&CIw4qceXA|wS{MJ|E4Ov z?o>;6DBEq0efsMPJ{F>$Q}9rT`mKWHPF#Abf-^$YECuI>sJOpwS7o@&kya*rgbFeD z-RPVTC{hRs-;htp!oEC0!cXKAvT&SgCmadW7$cg6Gx7)t(?mna0vo{?6SFwUVA?h# zPh~dfm3cVA*Ermq5t>WcB9m~a#~d$dPglK~^_(!Ly-+VLa3pDh+;>RmfH|eU+108i z_)&*iMer{bWuurS4tbbD5&T(Lm*CGMby@nikWe9a@>Q#&YCB!6MuJpERI3|d>2^n0 zNAO=As*xa-v2|GrRipo$YM)c+?;Ni*!7+zwAfsP7RGMJO+gtE)?Bp#Jc$MH9m)sf% zHYv)s2unLdLY3`KZ_`V2^ehobc(JRNCZ`P{ihE&Xp44Av#<(LhlQ}2Nu!kTgETAG7 zs!&fAx||C2aTQR}8KwZo&-=n!1pi)9)>kZXrwMuye5XN)rH{yGtF3AgZBfb~vlDtqiLNBazI@b}T z-L{{xMANZIAxOI|AxktJgaq@w;4f1ASZGS}LQ{elnv%TGl;DM?Brh~2c%doD3r!=w z7n+j1&@|$Ep()7={%U4S!#mS(%)Xe3yr zsN~k+5LoIe)+u9mdQqWwI+6y0lL;1Viv2BZN+A z1>Ub$Kjb7d#Ywn!W#WM?4=6QxCzuy!oMc{wCfKuGqOG5!-~xxLBe+UY)?$`E6%xi3 zC&>pLN&035!&(etS9yt&wCXuY@iD!|SB0Ph5qwQASuI&QGG+OrT?legog8*2YlSvf z(Mx8h=p`=DS5`yGf5tV+%a0#!FKPnNV%6=v5= z6ICcFgji>-0?>rueTuRT&e8)RA?wD^Cp(flg534OI*}k53j4YdmO}O%`QqFI>W7dc z$lAiIDS?;Q0r?Q!r=6--5&V*(Qo#pq@P<~7n-rK3cqE~2;&sA&4q$TdfnWf?h-8_v z%Pjtkk`ZF44Qs@`K|{Lqf=DCGH7(kd;K!VCeK)vgo2Uio;_Q!C#8>o;C%g&L1!dBH zn1@VH@VmDycB1mR*YR6LFrOdZ(NLGfZIx?ge?7sVnImoF}2-tWa%evNWGdMt+j;X+q;(bvLd`YEne*^ zb2+~VyEI-A%zfp*O5f6CU~Vo)f4=IL#-xQp{c`WLzbR8+OdoK zkxJA$CF%%LGGdHiqmx)i@O6h;MUY}eiMkP%UQ*S-j^Lm2w5=Oq>0?u*Voq`r%FZ46g*yJIP{Q#F{>Y&key-r5 z5Ot-BTJJ=H+Z+wAjV{a@exM-Tfp-C(>-FJL)#88XS^7EQ7ZeBEm#ZwwPD%%3D(_XN zLOsFKW2^&gmx#N^uUMB<(ci80D>fxn^fx#wRG)M7jBZb`x~Qst#k!=5zN&u3rlg98 zqw3nEivCj@G-O3+Bf)f08~uuPNfmt?{fbRV6@451iffZ9`Zh8vyj4RA?HCWPI0+t3 z&wa7RPlXMU@;Lwa+a1QEryl&_{_o#v_2XMX z`0@k(ia)L=UuM7;7sT};U;d7teE2qi_%Hb5_4lhj{P{kAh0oWX#Oe7H{NYor9e3)P za_HADOt;tX(=+`{zh3+{dp*vd?R@bW_Bvmn$+u<3>9;B3Mm_J;Gk-V0hxqw(fO!40 zH2&x6`7%9o3wMuB{NvB0^1rIzFT0+l~m&&TNb z1U+-Z`cy5)>p!CSAL{vOJ@WzPIQ`=>dOoRKi2gs7{uMp*$(m_u51&8gW6W`R*C^e9 zo^R3fu%376nf{O0AFrL_^qOZCUpXiwjNsc>*6wh%a zE}!Gcsp`+u*$?#08%-A#@b}${=f1(cTK`!GHuW|j^ zzbf=P``1+k=yxdoBYM6~&+!{IUo24nL{)&Bhw)9hxPFf*;z>QfpyyxdnOkVwFH`h? zpZ*{5KvjDuJ|7YU?fCzv*Mp#=q_q#<+{jk7MiqR&7E6N4AfGl^sSNyRI0A=4YU(9EYY1tPdf4i^)10G@~aJr?~_)W8?72f<~;7 z1+?u*IbdqWsr3=iRF6Y*4`@cmp^-TPY$Dm1%Lo*po&5$&EwvNzjbJi4s5Jm>}2<%t3<@&sKHe(?)HZgI66!Xub)W3ha*ATA;z#q51~o z3lV5&R|{W8bQr1iJ=EGWjz0ejG<%ECRLRGLgc%Nzl`4@>Ph4io{8QD|GSH$0u_;v| zQ4&3>*7x@lW8$Y|CX4P|wIyT(A>gwCf2X+X0#xNf8j+GJS%$v|i`bFEMaeeuKb}QN zdMs!v$D!dv6cSabl84R=0?r1>B?$O{`LTvZB>Tr4#me2s%XbW4>~ zJtQNE4{b)O0VLjx9+Hv9fU+5B2#{zNJtQMZ9;_KnFBb#b4N%PwE%K z@+8n4!vAnIKMSQAwJ#N{A8fChH+TLV7pq2(i$IeGWO9qaEE7H`hI|@;sl+{|5YrCK z5C%hO0ow|Fz>Gy`hJdMY{*icwDtgf4e*>Dma8Ahi^T1T1`7DP0)Y>I&u^M4CN;c-q zep*9I%{nDQ68KqkR+IoGX1_5sk+G{pzJu)_-+_jmngl(uBX!gE?UsXv;_XjYNO+kbb(Qiv9E--va-JjiIE{Prm^{ zwx3>Mn>EVD^wWPwE8Bj$5Q*bKkB{`z9O{kNPn%KG_EXsds*Xtt0_mr1_;35^Y0!sJ z6Ou|lt;UrKpi(7%o)b#xr(-S-3-{A~(8Bi9We_A%!-M_wRiJD?#TRmW|C(b?8n*s&Gll66^)d zxNiD;f`*JbS&iGM6W>M;M%}YO!?}=!KrkGmbP{!oFJ{zz2qJkyEu@pEI}ZKKMjf9v z53dU(qr*EZ8FhSuD@r3#w+E?Xj9IAF z%vuKXF2NLuI(#G6%&qoDYORr4sE-q@Wj40@i0!iX1Bd1v%*IZi*shU~`f(WbjiJ%? z*EAQ05@XSWad-%5;gB?^l^PO<`&Tj!@6jA5SHeT$a4SYM8;2s*KO_!koX$A>f=>X9 z#Nimu*plPf?06%7{?Z!y`8(hu*(!R7pJ!l#Z2g>^$HdRohvDZRqwiQhXQM*2Bt9HH3?E92 zSs%9I`_A1hTS6BaPOS(o8>^Mcv8sDSVLVHI0@J*M@jUc~{G8Ahnxn)&cC1XG(LJK6 zppmPIGrh(2jWe5;FP??#(i`Hl0;(>3r=y8&`cssmxmW0kT(69Yg24}BplMF63^qc>1yz?ZMp?qP$70mn+7LCU!01~Z5A9xn|=oDZJT!V zXZi$nX2cdzxj5l12S)Ii{a##B_)DMq|#n=`JqsYM+ll!hV#wsJ%rNH@*`~p^* zEomOkRjsq4qym)moN%#+#NmrqGY)Ts&HNn*DQs>z1%rhhFMb25{vmUu$4}=RNuG-E z$s|_y06ku;KIvjreuwMxk+ECuVTeVkl2d$TfRT8vK8$$Y;NtlK)Iz1agE{Jcs9@tc z)05rY-P@M8OXKEIkR_TX%{JahY)BBAI83;IA*z{qR5#n}L6Iov$RT;-NF?6z#`iHO zY}=v|^?g6fJnHvgV)I5eB7+6-b8`_t(}yoQ9}aZ&BPZnN1L1WXhO{x`!^%V-3e9Pt zsgOO4pi(3GTwrR7u5PxpWm*FB%UUzS2AK>n*FtCTvl!vL1bl`ZXTME93z}$GeIspJ z;o4LpHhQqXH^D!)zx#7h_IH_QN`xk@cdE=>V&#%$xL#;3p)`wYiqYt<^)Rzv(mKw_ zT5?5mgbxaNhn2OY7SonIeewtZRv{DwQ;Gkw<%V5r{1pqsLv_9)4OD1XcwHc+sa;Tv z2C`;eafQ*@$`WqTL-d(hTU#sGLNszs`e0QL``|awy6+TpHTa^|)( zm^0U+Bl~2MGbPx^%b8cBy=*_71SUQo$(i>-g3X!HyAae&`top*zASVyud9T`c3w9M zjAX0uV1Jiq6m&k{+0z+)GKKwX*z`DQ_pm;pH`2dEAJHO_kBQaASBTxk<7aWL$SzK^ z{EF)FX=(N*? zHVWtPy+zucZ7T11ux;9%?dywYaI7tmMQxiRKl`c}{o6s~+RI=DfEjbS7u!(-8^HaL z!}!s%61>Hp@R(S%BxC?x+2tU?X5*Qm5QUhHH-HAtP0q%eMMt3~Ivr?gKn+7XM!bb4%56L9|d=@jw`Dmx;XeBiyTGB3BB#u#t9TF{%xo9~O zvV3upNq*rniGRmgSV|^2R3xH=Ml#7>SZp)NFfh?xz^IcKdf2E#SI)HO=2VA~hhkqA ztHd#Mxk9T6B?%mjo6lQ}w2rh<^mro?RSm^O_r(085w#1Bv=IffV+SKjer+sQllBUv zibTu1Kfq{t3>cr6M9VFh5sf$Z8#;_gcoO-?=8dh84Gg z)UlN_u9fA%jLjK&Dj?g}@0$7};Blx(D~o?VB^~S(jRe=qww8Dm+X%5^Vy*0ZowK+* zTq`H!7TpmN8sU(%Y7_OOl_y=#R{j=BeqWYW{+es$&&RB?MYGyEj8?t`xy82f4^c6> zmD7jO%0sS|mw}I17#?ip54%>*^=Aj$de804cJ;QpMh?CV9u?YxNxexpJ_wp2(ijm3 zfLX#m7-0Co#!+kkGKUeO=Rh-t+fd=!;kUrlL}-pcqveXMCWOy?&*8kXDvo zctrcg8;Lrnp;^C+2I0Xq{unx!?SuZP%g7vcktws}=)wFWYjbJ0r1gc=kjVV@c1Gr> zksaEjj8KxuT!TBIHvjw%?d=~jS{->dN2?mYtDuTR@7OreD^Go-VK|xtI?GJRKV(EZ z1q3$2<=1I`gv*FlivKVOeAfF+fRS7$E5z|~-9AK>&2_J!7Q!p~$E%s?|qgReq0lmJqt*jl`z zf#T;sqAy!Nw?&0$N&H+>#Lx7hd^yYdP%3uA%J5*{IUFBK^hqC0^s_!o9Qx4q=1`J_ z#D_P1ojyDU9D#@(;=}ES;ln+L;lm94V|~~YlVXeF!`xx`u*Uf?hoyRJei#}?AB0z} z4=WS>BSfD9&EA>$dF(5|j72ct0jB!Qe3~Bub0C8GcVKczZ{aH7NIbu=CxUq^Fg5SU zr#T0hp$O&@U@B*k#*c&*@C`)e9qdhq6A3v~E!3NsMQ0*NkZ|C!WqDF8$SgVwG*ARI zTktn}zfveAqHep75%s^3ysi;+?1IUQ~BmB1`eq+QQ79@H{i$t%`nGqi?Z8Plw2*Ok&?_j$hGLayD zK0oiO1>dxG*XLWR&$bpPW)giC^#3--M04@afg=84h8%FcyCXY*A6(=OGR6U&@SoK= zxp!}F>Fbf`JY?(wjj6Q>we}z$r4)ZEh9M{~lFFT9`yk$()Ya0O1+}bUg(4NSbg%F1 z05p8O@(Fr+@iYlA%?^V?@Hz0Qj9|VF%-#q_UdvQjMOjko2f#Q#3nF*{n7f^H!5jkS zo(SeOU}TbD>=Kfo3=5_jC(HT}kvq@IvbLTmG!e|(foXOa#$gy6@CfnjcR7>4IuD|Fq?Cupsl#C}(9`LpvieW1R*n! zUn6JQ(era?Y~M7=QRl*eHb=cTk&pC2+0V4S;G9Gn$x*{-ZJVPGK~U5*_S1g>ot??p z{Z+lqV!A8iXUIg9*yW32{74oQ2N(N&WwH1X&Soa_4BPZ6;U?(FA#M6R*5>2Q2CG45 z+p7}weZ{3MK8B&sw#CMX3>L)C)kXa5`6r+^#^??AY_qdHsOpq-JoCaP^m!Q)@f@|q z%zF{?BAB^5;nE0Z{>hjFC`L2?t!$k)B)!p-F2D1Q$eO#ulYWdReRx9B)1LI_Jn7p! z>7}0ZJ0>K3r6>I7DeZMDNvS_3&=D+Akzh^?ymw3`2@uatT z(tqYj-!mcUHJCbx7ADEEzg`V{LJ?V{}^d~*(dnY7)fhT>pCtbe85^eWK zJn8!;Bz>+Y{ccaX+)<56mtSy3WB$N|q*r^=@ARZE^rU~?lm6_4q|f%G%Uho!md>5) zNx#RFJ~kogvpnfLJ?XPO>34b3e>EZLGd<}$Jn6D#jCf=IE>HTQ2}!T?q;K=2PxqvM z*pvRsgrraRqz`z~r+U)2d(wmXb_RiwT31qsGrmvrq<4AJkMX2m>q#%0ko2jZ^fpiW zBu{#uC%s}q(knda>pbbNVvZDzy7zn1r%g!uF`o2BPx{NA^kz?b<%Fb{dD2&U(&eew zsO?Rj^jQ;|_yMDtv%j$(_i8vl)EV_$ zPrBUgih6#bC%tAu(qHkU&-SG6_oSciNnbW0=`VZIXL`~f@ubi4q^Bn&{g5Ypx+nc1 zPx^FEdeelYzvxMy>Pf%flRnjx-aH}czw)FX<4ND`Nk7JuzF|Vr4|>ukdD3O~DH`*o zp7h*=q>p*hU&WF=B5UrQp7d8hpftLM-7+ER&w0{c_N4Ffq#yF64^2q=v!3)9J?T3= z=?6XOw@ygSuUrZ)G^-R4P`=dqMV+kJRKw(s|(Kjldu z@T5QLNxx%4()W4N_j}U2Jn0X4(nlvG{Si;Pyn$D}s-AE2q<`I$e$RxY@AafV_X-$BRl|=}EuYlm5VjY`@==ezzxmi6>p2 zp;ryH$L*bv^gW*RJ3Z+OJ?U+p^nDYOzT1<&%acCWlfK%Meqch<@A0JX^rX-Bq_23B zq~GmHmp3_Tn`(cb=}DK5ohXgA`?C|Webke_&67UelRn#%J~kogcY4wXJn2(C=`-FW z>34Y2yFBT~c+#hY()CTeuVFqGJ}dG~xhWAjs)0FV{8O2Dhee-Z48l7IQoS*+7MAfi z`h_zdcamoqpeT;N$-|VoXM3zH+;=EB6*RW4A;%wYe*6>c> z`*0DB7dvFNn#O;TQ0Pvd+&Oy9-8qu?ru%&4&QWubJ4Yf`?$8b4_LIFsw+t8{@($ji zI~oqO@zdV2F`GvKa6?Z^x1ho}Y#-P#*t0PR@?uppK!u47u`9|$N^EzzPbd+QNTbgq z4WVBYdn@z9P2s?%SWyuDQG59BWrX zJX_o6y^LlYhvvd{+$SmVW7)IIZyk46(X|D=df^T)YpwILmb|shXvkXg<-G=q(P){* zXn8}@MV|=gd5xa*mp$pf@}yTzNcuKU`btmwi=OoTp7dE0lD@^0zQmJ$(3Af6p7iPo zNgwc}FZ858=SlyPCw;+$q|4Y8ZTGpJbh)1&p_%^~PkPOSq<4AJXM583d(wA!(w9w0 z`UX$>Oi%hFp7fk2Jv|}mZJzY$o^-yI%{^%_f3+vQX+qMQJ?T?D>GylKFY=@}Pe}SY zPx>*Q^xdBH*`D+b6O!KKNuT6NzuS|3f+syUA?b~t^jA4HF{{tL)06%OjHl5&zhy$w z)1Gvh#YKAe++CjZ=RN5|6Oz8tlm4P7eWxe=Nl*H%6Oz8nlYY>XzQdD#zbAcoLeiIb z(x3CBZ}X&o#*==>grwJa(x39A4|vjtJ?WzplD^QBzTcDHNxx@8(ieErAMvEO zdD6Q)>3b$5eXb|{Ay4``Px@+4`U4Y^UhPT0-;>_xNw4vw@12nJ*`D;>p7fQTbot&y zG}rB$kn~xe^t(OjOFZfF{fnsd0~3-y)02LuCw-wO{nbfMx~`<2hCbu1B11l0Mdr!U zb-@^|_%o~`VV3n_kyT`pmdHf$@0a}5G!av;SkXH>v!QJYj>GL;slywOUh8y2%pOwk$^vk{mrYK6sI3(P@{I*Yjln3o+U*VoxI(2ie!m}jvnRr<$4!}X4> z^(A0xG)t5Q{R4e?Yfo>VeO8vW9t91bODPR9c-O;5XlL&Nljfg5BL{+9Wyw1)EAb8i zX%j2U27bPOjzw4C+tk51v!yH35(EoSBlPMSpy3?A@~H-fvq6hl1`OZNW-%FH_G+7g zbE|zTyS(CRzSp5Vr6)rYVJ@`B@vhN$pdH|TQ2%jf_c_?D(^T0%{ z_zf^mMQHvA%-#r}6J@Ivht;_|+ufSmik#r$c~iD;eQ$p@7zP2BX|NQp5ZZ+AWCZqk zV|xBH@YxZu>z%+1xmqG)DKPwYRcVkLv|pUD&+d}XYN-{`a2qhq5N)LkpWA_X2<{Ah z_!VF(Bk}VDFx3vz-O`2r1RpxPgwJ!J;oJ``D6dSqtT7mNZHk|0nIA!oMXWf4TC*bU z^(rt2BeoxfIIWJ*ycHNefny`#Oi61vLc1;irYq83mje^_FQL8$m~@2mt-=TY!+0J= ziSuwP>pozHBU$1xUxZDJiPZW9Fx*SAoaI+W(<1tu01V&qWNA(Z zrV0GQc)kFbS8*|H!OMY}i}r@ej8is55R<0WHNXMb0&j&`JSJG$PF>b^8>wI$fA*` zdpl^jI<}nO4Gibu7E=!le?4R|y};b<+Dl|y3rx;gA(#&VgBHt+ggbz#!G8o5dafMz zpfoqa=YC+CA}#nRFwuy54j6fYLU>p{FAK);Y1RHUE8;`(aV2V?IkeUkV5YlTKnJG? zO+@=#Rb;V&Gm^tHfnK3^Ja?!!wHQDZ?wdKNUhBC`6VR-}Jj4@@|hz}wHv za6ZlPF`pUg=?!i*7+P^BYH?T1>hn!t_B&Y(UD>QyupnaB_ds(1|HHO;8YSryVZV3* zm}y`sTrKC9fZ66a10B2$%>5C}vB-1Hk$KCh!0d=vdLA%x*dB-e-r3WJEE;Lk<)9gj z=zIk*FS_1@nM0?{$Ev|6)VWEFVG8IyGv<4 zYTe^(7tCeA$PwC}0Y>hLhq2lX4EF)dOs}W4I~NSkv-hB_KDU78&PeNg5}1V%%-4Y7 zK9a5VC@|4h{%2r@(GNp!{3kH7!vM!>{LDNVtsIG#Il$DwkG2+UH$$WS{f>A;-Xt&Y zSxQG@z81B(vt;#Y0!EH-+}Q}sq=*$C0_LfR^uGpXX9V+ES~{L4P;3C~Fol2O@mt1G77#;SylBT$u0GtASY= zq3Hw$h&<`n1M^~p=A*#ujQHnofvI+Op?Yv1FyYKoFy95{kw~p4fm!J=W51KfI%gt$+Sx!fLC4K5DrIRt#eOAXL)y>I9Pma{d_JkOCr+W3(Q`pv+$_{W>19A zdSDtOp3e!!@oC3&xfL}lTrJb?K-B;n+I|yiZ2-oOxybYQ2R|brgc^PfG^3HMb(hqN zX!uQF);Z~57(5QlixJF^fSDTc&mmxP5m~PSvnx{TSp3?XZ_KtHI}?~u7aM$Uyd>2y zuPy}5kh8sAhx|kHm;o{ao!!~_bAx4uhHY^%YCRY6YNN=C#C$6-a)hyQorl>8%p(y# zp8#fN1oH)8_D3we4;a4h!dki)m^~5CKMjoRON5pl0%kbU7Qv~gu5ox^O#t8CTPYYt+N6c(JZvR9T+)6%=N&`j##=An7f^&8LS*IMGA%^`g|HR z(_9N?^g}g65$S&in&%uJk@^@gcSdAA1x!~2GX_lBwIJr$UD+PwC>IIB=ifmyaIF!rd# z+nzBNT}pWjB*mw{<^mI}>-z=WBtwM$m-@K1!# z_d&zwZAybpI`JKHwqt~qN`d{2A#|2Pa1gclG*oHuTa>EWvg-#sGA(^AJssJ87CU>| zdkMF!U*DJA#8OvhPnK|dpFF3f9N>O}vQSs7vc-4T%zJJ-dp5Onb+)A;t{dA(eaq~d z31M+!2?7}q2$I=HAEXJqVIyd2swf4H*B8@AXi4lPqi^B~q{h8L* zfnG#eOoL1t+FLg7#Da`0WY@P~=hY*#q14;emfg~tb8pe~>5Ly+TD#l2dJ0@Ll4KLq zlVP^Ildvrbw6YZQX*)3;TGQEcSy*+$Ys3%5Wh@u~p zSX^7H&~kxnN+^;8!u}o08__J1pDRpyunl+ZwJ_Vtuo)ziS+Tf2vvPSuBYIONgHJ?e z`tY6dek6ztDFoS;jiF=C!$e7T`^>GJDh)CH=yX^#&*!?Le2Ca?Emq|avQ^cAU~+xE z9eC4vKYDmy(ACmE;4t!S;qxs@rYlmsz*N!wNq*QkW2QHmR@@K4{|nB~479B8${Nb9 z-j+7AD-mxLZqy2oegt~fQuS}>-Hh)_wYPU}$sk=ql`KHD5@Sr~#%$MCni-a@ovy6G zZ@%Ul7p$p6XC>Gd>&yRlP75P5Y>-o@6U_)KeWcdjejo$VQbYJFMx;8v!i zzrCfiYp^dHT+)zP+}k5JcI&gPy?t$hSjrBOfJ*mb%Lp%D7c(`Hh}n6?#LTFB&B%FO zh)S(tz1-K*iGhJ#tbbrtf41*3eCS~*HfT8#Vu?NoG>H(~tyryOa#ooD>%VB3cADEx z;9}zoyZya=TN%3ej$i{`If#A_V{+Nf3l_}J^bPh%prSfPWqi)JFW8JkDi&2;biuqi z7x_(Dzv}YF<(DnZq#Ks5TJpY3{nC~1TWmY$(#x0l!(Ap*xPtU%>yn10%Vd_>+vhS8 zub8Br<<9{`IeZW!3+13)knKiiG;b#m$bMWPlbqp{A6`K#HfJ_wx7z5XbMmgY_6NM2 z=|Y-;mYL1-=UP>TK}%bkV?YxG-)cSQ(f6SlFshL$t7IBiHn`y^{}u4(id5XI&a9T% z5JtD4ekPyAotB#)e;dskU&exM=I;G8dy$FUbxl-Nn6qwQX&Z%n~jx?nQLO zI4#|hg<@ckUh1?8GRylf@9mM8lQg!xXYpWPAG)6*aD1~pgWWO-k?z>lxxTNZZ!3oK zZpp^|lPa$YV24y8PJQZO;Z& z{=9h?%meW_T~`|B5=4@ntS!fypca(`Ywx&Zq?yrg@OLAcAlrp;t_6nKNR)1CCwgX7 z&n(FsA|jJjEttiUh3f~pR(E0o+0wPDXR~Z`H)ID^_1GNI=5qPPon2^o)kyjorX{dR zW`d@PO|G)5h)nXFGLs2IoC^-sMh8QfzY^m=GB+}(_+l$&CEbn4sI~o&pA|^sLJ}F) zDB-dKV-qG0{U-CON~)~6^`sIg*G7gik%7pra}23je7Cg1TI7vRWFbkc{TN^~z3pOa z>qZ$9yD|Hf3!S~|Gwp*t;tbQZbSfLKA)k`zL)J1$y5;>y&HaPx`;C1WOhx)-`Y6{h zi5ZXw4(LRTLCC<^ zXO}}Xw!6Or^It3^sd=aFr78hNA?$U;SRiO|0}2!RFnZK`=*|YO;~1h*=HHpF+~V%G zm1Zrh3spDXhpZ20VDy$FR!xMO=Gev!vRA%bmWT-};xO8H87WI9!6AcmUvDeYKR7gY z^#hHOWl%;6@f|X$+}~_Oenz()$SSQ~HJkLA41OWyT(3^dEY9@jvaOx%ovmT!E0#`d zN0=jS{Yq-iYaEp!(Gl>T3eM1h}KAh z-2)ghv?sf@J3~kuh1G%WU68dh+p;Mk_H7r=Ni4yG2`-{~VPEGC0|#!jp83R+wg8%| zv9oof9j95_(fTV{X1l_XXB#3k%-&}(ERg|v`y*Xn{0bEklOCEb+voNFVjB&%Ap~mjghpYkL6ew*k>b(br+My z!4KAA_Qu}QXx5OH2YRku3OEJyW33v)xz-#5(G0|FXVX=zE0vKx43w0Ou@=XjMC3a& zal^zME7yb}Uy{vby={YCS-YPnvjj;RRwfk;eHY!yi^O%7L+(*Tb}IuV6BjzfhKTDv*}JLn?>U`p7sMTFcd}RH-$q; z%Z&g_s{1L-bsTql8n7FJq1Q#ZNw(Ch;L=bYnU19g(Pue4V|OaNL>6t0j{I(5OhNpa z31=}DB0{Gk-DZN7kY2fSuV%w|oryS`bSPsKNoI+TM*7gE^;^NzWiJ<-NK>NisCk2+ z*ui^NUhw5l>(Tq7^LDbd!ZYDa6bqoZ0H#inW}m+)Fw7ctBv(f^P~3dj%pvk8w>Coz zvR;TyIgmGG#lrk-QwB;w z@y-&PA{(Db=%71wM;9b{Yl+BSy>(;WVxd63;QSV0pEpLEI5onoRp`9tIT_dDoR!x_g2L)G9_L}bk(*k;zP{l|9g+0R> zBF!2dGL=}e8rCwlq))!tf_=WmwS_!|FE=1KJv0x2xni+7Td`$c(o}5RiKjpAK!429 lbTw?%4;zLH5~r;FK>-I_v#(=jdv037DTCXGi1q2<{{R@CPJ;jd literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util-static.exe b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util-static.exe new file mode 100644 index 0000000000000000000000000000000000000000..fe7f875326eecc3b6e8809605871001701da5abb GIT binary patch literal 799602 zcmeFaeS8!}*7!SY2$T`aI9?-p~Ex z{&D$yNOx78I(5#eQ>RXys_Lnly3&>Ha=CK&pGde|4Ls#vh5GwH|EZ<8_keZ1UC;M; zV_<_j@W#N2bFP_RH1EdiufFlh-xSqcdEIr_2aB$nRdi$Mx}s~YEAm}5q3Ac)&zvT-z7-Qhd2wMJn5=s{p#BlW3h>m#Zw>_0-WM=4HEV zK|U|bRjb-f0sPO;q8Zt)lAi&o9)grp#QseA;NYxr+9={S0CV}CS{q# zS>Y zaq#GiCrX_;@~0X&0lBLyTt(yH;9S+Nf};-<+^Vi{BA59$)_}t4Ti`^-qGK8Vq}{WI zI2q4$=UEG!$oo%S;qphFRqj=QXSwOzmC`QHM}7wGoN@(s?-U*nfpjX*$2xa#g$sN` zhAOx%zm*4#-YQQaqT`=}8~RI?@yumBYJr=^^VY6#6{F7jWtoC|XaJ90z!mY_(G`w% zhdK29y-{fI;c_+eZ2uWJ@7a{2dct@ z)&|rmGL7)w62tPmIzG!)zO}_A27}~AlIg^z%)}j;i7PJ3a?M^ktZHg-A(gJA$SnBF zgIO-i6=@7kUMreqUv`h%WwbOU_-8*I67${lO|s>!C1QYUTL~y3@zOV-NU>r@0%%+-Z^h{53r< zGGY6yQ{QH8@JHtsyQ^xxsBHQ?J7C7_>bu-7f8;a6e3edl5&&)aWhiU;`-au)V|(45 z!sR@-VeYq21Cp-)5Wf0;Txrs3lM!C;w!4w9dp}sRr84|Q?u9MBGij1;G|!w4HoNRM zN-RABB9DSmWLbFu{xVz)Ge2N?&QghjG6Bv;ldQY~UQN$2{6#tH-T|3a@Z)`?wuX+f zAEGtObAY6=bc1NuWtU$uU7w~;U*91gZH=#ZM$ChvJMu$4Vq>#h|B^xIs6gZ+`faUD zH}(~RP^nGCCKDom1lF+f{>{VgL22ZRmTsaGTI5Xt=s(8T?b)$r5=s2#TZw`Tin3j? zb0u#jICeTXnt8NzQ-l8%L>aq4LRvJ;cMbDRK|Qg!gz=3ow*Uv)|lOX}<0=>xv(emP43V4GwvH;yd5LAs%Qt3B>4z-pX2{_;&??T5vOlyB9|CPux_-0yRLZ(j;7zxM}i zMI)60h-(;Vx(nu-ZFVm(__Q@|XsajpGpvh-`Ayp}gT+O9^cuH4;0%m!qi(j`{1g`F z%99Y@cIs|zaXMCYsoo$SyuBfcN>G>*;s>O`5A^*&SDJ11!-GNgesF@=r^lq!@@N;z zq>QZ?Y&krj%{_+yNr@md%!k0k8;q3E&@b1oSijO=o{0Yytk;6oe9!I=qIfgui%Hwv zCG{XZwz_{(duJs{)f?b5se{J>B}$MYwVbrm-@oK-W#{qRrN5?>C+J?<8zG3zjk>wr zzVi;T*w^Lz&bY3S5Hhy2WC%X8^HBN{BOz&=?Nmj3AT z{;1vY7TNwtq5(o(e)Gpl&A&lgJ%L^sI}8PQRZZpo=nZb$D3xx}>a!SgRW z-%ifwhWWK&?zA6OAPY~|R{M&L5uV_j5j}%5tw6CavMKmMqTs*@GS(F2Eei7Hcad7{ ziAkybbz^Ge7Nw>3snuC(-;-W@A;q>E{uvC8zgK%}aRt^lA6|S>-$>EeAz(9VwpZ0O z+7AqJxxBX)kAR;o+6n>$i8O}{_7;2<5HdfPI1JK+)C9-AR~;pq4gwVC-3!FiK?adY zfZ%zYDh!E81Lo)PV-(k6yW0r&f?q2qB=Js?+h`K=k2IsL4is0|@zb3*!>6sDTU=3T zZnWDGiMD!Tu|dPHtA-l`GA8`Y!B72;DaeuIA8>6tTDs{Tpvz&^UJ6M3l9YdCei1Nt z#m-?8q5OKV*;i8Tw0(W5ZEf|m;tB@3y(pvU@lMmuaHLPmsi%g-luko}j%ztS*>PJp zq&iN*8;;36oobotK1#@2L#;biExiFEl$}=K5UJB{yp@+iUd+SxT9euEUSYuMKRsDT zrem?~sXA}aaBK%NrkX#(huxLt=78C>_*`9EoyDm3>b1Xh4-DRbO^^4hs%gC_dSXwC zvMD-gbnUG@DZ5N}H|o&}x3_u8M-6C3LT0SX*3+ncT#~(y)9lHN=CC&w>N44@A)QgZ z%G^eq;r1Rc_MnP3Zim@6CfY08SK8?FLg9N_U`L>4z5PW!tnP4HWK?$eC!NOs(!Dzv za<#ubn!$5NG4mCMZM#-?jz`9GU2!8Vpu=-{08m%_kUYtk5iRM*<(af}qF-|ZB%DkK zo8e4$8!K{M_UJik3`E||kxHKDM~kC#hr*>azrG)>YOBY4ylq56 zH_~HbB@R=jt#+sz(Os(x5hNIqt1Ww+X9{EO%{eZuu3DOcff>*#j6i|Q6(103TzGnz z6rQi1W8GRj#~?K$-`lP&Kgl8P0*JF*!+{BH4OlaaX9TjZ%-8B%lU`}M~&3_`}RH3L}Wb48lZ*#~( zes2o|7Gq%^wI}x!q1}Lv>B`X*F-UJ3(N)FI(5QW^&k_D_$kbN*bL+4)-$_&SW*Y!v ziw*HS3}fx2abw3_G^?RZK}3<;%dmW5E-a=@tg;x zhLvkzsrwk#L`>Aa2#zgS8|l%thR}COiQr$Di_3?>N~(>~Qc*#nT2}t2-6%a2ZZeu; z*=h~vbbpG^O0%12L@U60{g_;P!7wG%$vv^l7xY3v7v)x(W6JD{2wKh7%`psBB%Z1* zIr);)Q{MW>TQ7O*E4nSZuC1={fcID=m&LOm&upHB_E*H1QdqRrjZ&$%{e;R46dTE$ zUUobD;@Cn$kydxPQZcdApQN)(w7Lt(MruKiUOVnMw|-zu&#d4HBIWAmSpo6b$p3s< zT~tdm-KA@~ry_@WxJ+vL_+vz0a+E#^ zk*+Epv3V=)|2|pe2jS;){&etT51;LFVK3&or3a42e9XmgM7}!=-lZGFoOYVb5X}P7 zwkznAk^7Fp?lb!r3?MKqzPE1f*UcSvJ?v)sn)67f`|0BE!7P!Ay)+TOFO~0Dxa%15 z0qe^As>o+r-IXfwl(LxRUtpiMGE@63Ur8=Y^Tm_O6Bw+c4NK2gYSU8UomP^&_*XDp zm7PuSAd^ZIe^yLrc%$39Z!xhbJ>LkwnqO&d zsC4fQEsJc`>b9s^wu><`&zBAfO-)T5sh-l;x&|_C8?fW9b+!D#WDk>&3(qo{?RXaP zP!_1f9<{<5eA3D0di!o2tnX{)Cx=95`q%YI&aro=S8cxn(3xZZv$XRZn;arW}vrCXm}#CTrJ{=hTun@W?~el9yDi*c2f!ns!e%lY8!!(WFb{8zUQOG+VUg z_fjIxCMElg=+I05K=9%b!r*B7Oxnj0ZKOoU+w4u#;eKmNO->wJ!z;#Gi%fm#}FdL6@{cyndxxkCzZdsyR=L;7JBc&hv=n z^-Qmi*4rh*xHY!SUO|`eQe+?NSc5VYbclry(Md@LyG}#kx?c=loDCWci6XN z^fbJ826lyZuPI`EsI9)a(6B1Y>@UUet{L0+!06-Lh<_#F5^eSTe)Q61$Fl04(3?MF z`|xLUz7g#ol4y!Kvv>+7xd=_3N7`WZSWORZ6GN+9305L3ji(it`Amdwp8$0tgBgw; z?HYei#&bLqy&{f65y#QOlusON>#_Su(F*suFrhU?|uE&GqI|b zHL+lC!|GFsm0Pz+mc6GL?z8;nCwl2lpV?dCQ87N;_Mzpy8B~Ns3JQe}%(uW{zBf@( z@>A>YXGuFN$u+!n8Bch)Zp4KbsAo0p&TZP2?{hc1n@MIj?J9J)b>+8Hbfv7;dmf`t zt7FOIS|>Y8_EWb)i>T>(t&Y(PUFk@ZJw?h?&?d5gBGdDi+ljHR&i9qbGKY zU8m;1{s)h8%yB`15P;?o%(CwSU8WiSEonz>gnsm`Not9{9iOhX!=5I!-i^1W;uFd~ zFpyfcHCq{?!x%$l0sO@hT;EMHfz}hw!h!9lH{hGN*8Q136c^dq^~!v2T-Y5gCnzNg z(~A_H?8BVYI9hhCN{~Pq6lCE_F`J?EWfBR4A zd8Mbw4SE(Q9VY0Rkfdiq7kY-L>CrRk=`?eaN=dO z5}Z+ffMAr7qeY$&P;)nf&W;|dq_$qGpDNTH2<9hYZcwyk1+QSm<T z9BOCFP>kk%wp#ed9LCOuHU*_REjEU733%uI76{Dx!H))hBzkWF8-F%M{h2B1Ph8VM zeXF1w2|6bVb`8NCd1C>XjDjtomr?<^W2mT`J1b3WHZeH+3@WFvzu7%0n`1Mu|5~tr ztPIJ}e+Yn>gulPwG%xc{B>;(cV=pTZN65=ki2N{<67oPnbdQ4SKPv_BLmE-L?Gk_x z02%&3(*HA9Lio%^U6zinfaY%&^P;V3lf8i+ERb*nU)Abmw@IRwY=4Zb>4x$atQ59~ z)gJZ)&#gV&Ggw}GxO*^=j9tEkWfJwjOZqTSJcIzjTZ!$d3ZXaEdQ~c%fC`nlLMIc- zSEdTLu48_P=KWc^^aDm`Tq3KhCAEc=bU~T@0f9q#8z!AmCLzf^oXk;;0K5$DQ$0ba z*bh)o1>55Pg{oG-f@o!4KX5u;bP=>FeX;)nXr{`(NZL`^Cf=x>rE2R961mI_Ek64K zls2a9Wv6%?es)0iP2OMw1TLpgx0K%Bm?cLBM zyU_2UhH6vPiI3EX4LAYLWRK@%bVXoR17j6T5$s!o#a6*o-jrhyv+o0qBTF)5$sMy> z84$X8Fm^P=TMKi*cir<$FfHygMh>JRJ#+4SMw%?%t)Ut@Xv^E#$)SG=pfX~0T!iZZ z%ha*Sq#Yfb&KtEJNY={R^ju0q`@^fFp>AMA(R`WbSGwriLhGgCUDOyA4Q3@OS=d>5 zw=IIiZL)LMMnQnU@D85l*Y=e-j7qR_Yz@KYXmyYA274z$b4tV5(DIjmX4fGxv`qAC z7%OW*#cP?_Ub=%P6M<*6>R@;`^OMX9R$f2w7}lBl&J^v`B4?5r9dwdak?Z|XTXsOIx=mlEEz-MaDnTC{*=D z4tvJ_Oo6jMOv$B`;AT#==WyVN`F~>kpLFLjFef3w(6QDkB?jpvAY~XW0Eappw6Mdw zVDt0f4lD0ZY*7lkF+W1V>3!XmoZ+@Tn;Hi@?5k-gbA@#gX=fZv;!Tc^^j{_QWGDO# z+H}Sb5eM5IBvrS?#k;*B1!AO8@3VV3<$p=rW9Re`Tll&)C0{>dN+JLI;w{3CONnHo zZocg^H~Y*tW%8YSJz}aE*H`*YlrfM!E*I6q3f!fp#ZYf5enW%yc|a-`OLp^FT{tVf zPUCUuUg;G=arwk^av58dHPw9?m8EU^85M<<+10rtivd7ha}9c6p|<=X73F`vxR%Z| zSj){77jmJVTJXFqoSOS_7G;IIZy)h?aoxUoOuMU5`+ak1v-WZ`Q#Wp}7P(pN4g9G% z0zmEeZY?6GH6^V6JB2%M4YlOyx@8A zR)LZP5W`(c?j!#!(ij2)+@9iUeQh6VK%Vkw_uFHINLiplWF!oFA>lzlwAHJMAK(e1 z+rgl%eyR8&k}RfQDi#CZv@6%$*7TozpLy8bE}4I(wCO*E?slm5v1Q%#8_|rsYlV-) z_H(2J^?gaye{@h!qf}v%=KdrYcIUg>Byqn=6uO)3g;XW_JEl>f&yQ0NP!`i9a3pQ z)2D^*_4adfl{C(j=HIg)B}LRf)XN;Xcmdl8|AIIddkJ&3JMQK!#jRtzFw>%(0mxm5 z%A1EVBS^T&evrAad{dfZ@(lZyFEKB?h~F+7aH1;6=@} zs2p@cOXfxnghYcHpFz<3uVr3)i2?o44_Ru==Pe-H@y}!**O~pY;V5(NJb|`dr#t2K10rTYLVIYU{XkTfgs8>uJ)CeR_d6Y9IJsDAgOf zZZjYGJAS};W%>GVRWLBArCTUWw=h(-5N9iJ=o11bYXCQJLN|TB-u4N=yRn7f>J;B} z&Lb67ML10JnhJjfa|7lk`;jli+!87TThgsEL*iDAqf>lV-W(F@faH_VVC79BiGO~& zRWMoJn2axU)VG)P$Q8eq`5#1tq9p)xJ7X9eLy|b^)=)Bg>EaSLKkH;@5dIJwxzk?G zjsp9AR$d;UcA1buu7RUrdG-Wps8PJFy}U8GOVOEN&hWM*Yw9=P*q02|t;ZXFLBN@a zW+M1Shm$JuNLr|uq=mZcn$DfwPTJ|VBfL5DU6Sm`U#OKP`vOIFOk$3D16DH0_DV)8 z{dXr#*#R&x;$Pq){eQ^me{s$-*8+W>p#Ou({!hZl`SDDc8$lPVc3}RIgemI+vsz#V zIWWIdFwn6x&2lN=&ZziePG^=q&?ky1r`0nXeM1nw&#a$}KTE7+%UaP#`w4Latz+1o z%_m8RvGX&5wTZ04dlOR)Y4OuL))R*LmSK&T&ArgKhNG*ZGjI0V&k!@n{ z(F;7o$LHL{c3>q{H-)||Z%m$lGtAcYvoqGG$$0RkfW05`#0L@xwF_a=un0jrLGQit z40HA(mbjV%^R@Vw9rSgXeO&8LTo1jTRb`4F;l575_Ea zFo>T@wo)Oj)Fu;C9DD>W1Sv%YcY!oOpq_~0OgRU*GeGpd$gZG)aC_F`uu-#0u@ipP z?JqxIxVMGd@r-eH;hm|Si0eWO+*-mmGMle{UXg&`f%h@2S*sIgIXdR$5vOXme<(CW z3(liK*)6Kcxy^7lCw9+X>90GWMP89owptge-BT|(9lQ7PMmqp4nR};0NMjI_O$~5S zKQt~;5ITVLq6PDkRmC&xBQ*=Ase)AK{=h8M{*dGBI`K^Xw2X7!adi0aRN?tAx{lG>Rx&0ML|KW(a2T*L#e=xAL}my?B)I|Q=irfellF8I1x2=J zCeD?^vi7ti0=F|*YKITfA_wrbW#b?=5`Tg10((&nl!e>fAk$RP;n zhdHVro`6PY+K*M4yX zd-yyE32!h`_L2IsEjbSijUY-P@gc@C!6cy>C2VH}=pZ?8eG&;fZ~y1@8RyQ1g1tIj zU(FX&2zomcqpSfcm^wCQ_1-utx97%DJ!U{_%3z+-B8pDMH%uE3doU#ZjqcJ%aHh{>yp9}dx^XpZUv!mdr=0G zRL|k^ID%4)+VvpdL`Gln%`Xy?GVTvJ(Z@X<@lEa_^SDHy*_)t&ncIUK$ zrwENVHyJg3>kW5XVwV$NiF$5EIhl?fd&j80p-cMOF6o*s>8rY=r*%nR)+ODwd`g${ zE4rjF&rIV8bnI`+%^G7mdu;-l!k-r3WSOJom# z2a*6?*A>?Zz=L8@Qs*~bl+}vb|K{NJ7Oof-oV-sQiY6m^0S6j>G_+AR_nM3z?J6*Y zv9^t9&MWxy(VSZ2;CC3);|y)g4r6%#L$|nH!379=#x;T=?`HMrzng51?0a_}w>7-G zf4I4*zHcrEJJ?D-bX+KjjH%%afsW?&l35VfqG+S1oE)-frfFA}G-ZBWiBr_)av;Lr zAIHIpuv|DG>QB!b-n<^bhic>OIOlyP6A;_aNr2c#)A1kZ^$!2e@ekRh_>>|Rp}}qd z%Q0NK@)-i8Y+U*>gN z(cKis$ZXQjIkCRd+Z2lFW;>y^?X>A_2_2=vJ~+LwkSI9&OLQdH{*+)MJ@~;FBEwfj zM+ycCH)==Bwu4kvna3nE)mgE2ds;F-<+1okJ34bAZ!1@3+{NI+$yWVEe2K)%^5+%# zGuymj5c)scym@eoPH>y0z4>;FE{?rxw$B`2;xk|6dFkmb`iYW<3#SPIR%Nc;q$ti_ zD`uaK6p7EM6`M7*A55?$mHRp~d0pqK#c-1NJ&Cn07t5hpQddF%E3vbNIXV|`Yb>WS zn`BFgJvucYt_EtPB+b$JTBHg8b)BRHa%r=AtJ!MrzD%JKBwF3)z<{b|Y`($(J|lZ< zu7lGq1f4Y@-`(usoRH5BsO9-}p}IP#7PrjLuJB<^TYiKW{Uya2jTtq~bn+)SqwHq6 z_eDp2ABYCrZe^Rz=Ch9$wPtHqTfJ33Cue2AyD1c_UEI@$u>Q(0*CLEQSMA~+W3-3_ ztZEnMPSPT)c+*yo)3nu>V5mmk2Ox2qrcVmpOkS7dF>$$>xW@HzZ}v8u6N zbSHRYaz12CH+LJyF`w$k6;g9_iOmY=|s zWR1=DzNxMF0;z+7BORCIs9+E%xJxl6n~bbf#vn2{mvXF1`y-zLGgzw&N{3m!T zRZkB(QmvNi|Bm40iiyad0+&C_o{6b2GbtcLxUolfC|)nW!{o6do8`lRf^S? zR4hiGL6CC4{V*lNMUQGgA_vn(?)@v8xQ%R-LVA5gKAyfF{sAicP@6X*_Tza&YQl2( zPgf;!_2EXmveAP=~oqOREUK zI;(Auwwf-k&TiV>y~k!cPUhoG(ZmK^>UPyG6b*U|%34MjQPb5jx^FHIZA~=?hI*P4 zPFyF+>>w(|M(+w=u)<&$jsLM8RB#n*KtKHS}0ghS{Qsx-3mpyDjjBb%M(830)~-?;$^SE!~zV zIK@Hq_9d$IH~u4txEBa_ebR{b*|Su`NbmVF<6ltA7}3-+uu==~1p!}N5bV2aap57qS0 zEY-9llMB*Kx7&YI#lx-3@|9S|rnx*M`zg0l8XFHfx}x#l$(9poB8R72K1H?Maq4b3 zX(zs`s|NbtmaJVcD%k>-!S1hW#lFUgqk$_@AV-q)3CQ6|ihH?l3&@Bhh%+X(sIrbm zHzw10--E#EmJVfE>L6OC5Doq2^DI~F0kxj&{~z9!NUusW)=}+3r`knS69aeDwM^?B z{!GfBQ%-CTb360(I(Hc3)v%g@Xum*Z$ELnYGV;Yb(FrZ`E@BJRjK)%r%{TY^OPd1O zqjP;{j4iZ#v5zPlIrjs>+0DWF+Frbw&76!WnZ%#cG5k5*$DcFu>p8|byD65-b0DyT zc%Gb0pF;X{(#6U2siaHPX<^1D`KKlGe}Q5C0~?Me6YS_-`dVzNt7%WJxt{}3gX$+1 zpJ_I8+LxEX@>0mlS!T0+wba;e7s8wz4RxGB$N#cM7qQF_E+ihMMUI16;(lk0E|e2k zYTZ^u11^27*uAua4>Lu_^Jn1s{23&NfX+-r>yI!^coImB^kB(6E1?-p=KiMk9uRjj z^F5DK?DxM@M(rP{sCb&HxxUV(4eeTEPo!p%n?D0_ty-I6ec=8S+#C)BBRZd;QpAyc zs@X)cxG9$3WEYB%lo)^0YDhnOv6zUVPkh>8Yrc9YHKg0^Q4^%t zu{C4T<86n1I{BHluMcU*_7(Eh)&F(ky_U|F=WF41JgldYT)3UvPg{AB`B%0BnebV_ z&X+K7G;cqR*)t)I1HgkxpMp}`6P@%R(!Y?j&q<$7`V2`Aank5W-e5@=leQ+vebX{Y z7N}%#vecOkVlFbB*NpQ&*3ke7zxF5NF&*m2r^@^FU&wodJSG)Do{;3r0&+ew?O0!1 zHxRcL9Dfvm`vDN2i1aSfGG*g?U81J!W_yWLmrX1uRwIA;Vn%iU;LYWYyiD#JoX4Z_ z*pN1R>EUa;>zuVi`7~b>xlf-II%jtHaCYcSE;H-lO*-Kf%>-3BP)UGi`SIq;yj+s`Rj z&#k=}J>i8#E{;=$SqMUv+A0V)w1d?Z+~b7BxZuFPc@iSlG6Uo2d|!m?0dl_T1Km&7tdj;%3=lTx!|aj&=9TT z%Ci=)6_8HC+wHjUN_dA-kTLTL)|M%K=_J2E^hyZaBHNOm*v&}Cu*P5l#^oDc;u2HZ zg1;DkOGT(p{Jf6&PxmgYkdGvc9u|mJv;h||*N66$zb_ct1Vd-JtrU6AAwP_$<^3t% z<6ArMi9Rwq3e}N9pG$o|g7k5jX>K+ZWu_@F$xK`NAkl3lk4X}6z^WyCgPzz^)6x3i zG=(LXNfqaN6m%Ap#s6Y(p0*&!odlh$-v`ls7Itlzim!x({BF?aH3Vm%A8o!_Zb!YOzR_i&u?7< zZ*necij2ExUQd|_UK*=LuU0of4aO$>dos-Rv2#fVqIsJiPSO%k$fxfjUhoL@WTUJ| z*)~x&jXe|2ap_BcNZ?#(w?B*^Dr+`4<=ooF(>F?+16H&GQE(A&qtCO;W#4?E_;3q* z>Cs*}OAkrS#l0HDT>46PNuE*jmJx2wGL{~evYWbl#B(WaHSSfP88h7bW}AJp69u=u z4_j(2x6?ir;$tQ*3#9jhboB`*-j9~|Ar4Dlb6zG^qPX3uC@ep~LB8_F*fjFe^0M-t znB<&d`>mj}&OCu;T0D1>i6r&rIRR)l?X<& zs?~^2-({aOhxx&(Y9+AB9N{UZ5`8Z69hQ=BfSsf=pHT)Y`Mec2w~?^ z-aE$wlk-o75%pv8aMcXc-)_sdbHuZ(5JmKLiU+3jJ7ZJ_tbu{yS7NHU2eJ(j;^C3(DSf zOkUWg<)_Jvw6K6nT$9+X%w14c!47Bdiu(DbYFA#(kMMU|lD{X3)CqT-YS!LAA=7wm@`Ze!_ox@o8R6l>iQp;z`kuHkMU|xGXuwB4bA9PH-P^WgNK#nS*F(@#4nhAS#G*c` z6)<W-!~H_sJF}Di9dk}bdpj`X^y-AJ?d@Y-A?@`cmXu>|Tl#6D zyBy@rc889W*01c;dQ$$goAw+P-klw8c56?+7vGVj>ADA1cMnL@^e78kho)D$jJK4& zmB}n+z7{;*-pQvJiLPNFqw^Bx{9L|Busk1&&Q&~)pES5ts-rV@)MVdmmnuXq_J4s-+6tV zqPIxVyCqo8iSLsPs|U&8u}1WA+{X2}_Nl7PvF)OPUm`rP$ykZq54PmHV@W1C7m(6E zBSvS-S}_Kd<~#O90LcsmEIph z#P@$yWrpNyZXCToA?3fYKmHN6if^~=MvaZ(C*Amk=-ws)HWFBPkaztLs<{CDlK zc$@UJ{Y6JxJ<@H_#z?1)lQP?Ir`vcZ!~gA~pB3WV$|nUtQV0@m@>CKOK^0Z_P;RHZ zqqNZ(i+W-Crhv6Z=6*FO@5jbkmrQA3Y$hZi{wNAm868(<&m5&xoye_LcRbL}is*sK zVyQU40hp-4%dAwwV`L)SZ)aU93OsgD`PM3?HFJJZ%jgo(M;1-;un+5CWQF4KIZzjiy|ykW3RpAps~B&M!U+MF0Vv>4GF+e0VEWW|z_*BHVJ z*ckI0BaA2I-5y*lZu{_CszaY17(I*#ne6ceqVp@TYSnU~;?N`!^VkL!sTdrr6R)N& zi|Yo^LeqX;8|Bq#!E;BI`w6MsFZiPpf){5?w#Ly{zP6C^w??BD>dFw(ZK#Y+|)vaz0WkB&`tv+iQFA5lB}6d+w{MY9ya;34es15gz)Y!STmtuhcmMrs}eXc$(Pd=&EG>RjNLpVoT;a zIJhSP4lQyR71cSlDOy2>l1nv88rw?&vJL)T$@W8h3Z=o)<~~ji(}g*~;Q+km0K6ms z=%hmMCIGR4wAW!TyD}`krtMT+nu&XrRQ)$?cl94r{>2O`&bdbsRYFCznAn!m{Y$8A zSe`czQD9Zfkhu>RO+r$Mws8Bm!Cqus2PreePXy7i_bNmmql!rs8~q8FtqGc_p9yV~ zoOVflOGV^Ex`+q+24W%9xg_h`&nPO%9Fek}{=N3~PNmpjW$bE&9+pf+)S2bf=}jHg zU4~`k+ZBMTHAT!#1!sIZ@lEl6skOwZ)o{O(C+9aHFD24!DkIWc+o3|m_NyW&(??D_4SyY8*ghs`x5bO z|1Ev@J1P`ms{RRm`3`*w#S*MZk|?$QuqR~F6~bQZw^vG*EPoJ+qD$6~mZ!3Vw1tYa zZTi8teFLFxGxpuF>uHY&k@bTlpG=Khv&U~($Fym_>xk~Pl;}d7;}0Jhu%ue-RxAE6 z#gndu}cp487Lf~KxpPSfeShcmHF3H^>rwf_i6tk&Z zBFXlP)NR1HB;qldPo=%bB}+UM)~}uPXW@UTVYCA~tgS{#Qavqp*lw27{b;8{0gV$Ot^jo&I_9!e5(I+r;Ob%P|;(;fXU{hG?9|C8i&jGvVKmBBsZZYBFUShb%> zWShDmlj?yIh|nD(9#0Z+YKAP5CPefv*}f=(^!NYR{w}BQTd^@eX@9~`+Hd+s3E`Rl z_u8M~v|sXb?Qh$gsS%2Qr+sl^L?iwm^55AXO#8HQ={=gaB1-60KNmjv0 zs|Xhqj36Zo3a(+XIOXikbG)o8!ceRgV_{E}O0vLXeZe;xct60`#paTJe0oTvQ-$+nq`iy4@p>n$)Br(_)3poIji{4%&PC+BzTta zAn%rHnMs8NBRW6dzCX?lI4*&IVz0kY7CGV%%4Vy)9kQS1jYSFD19=mnf<+B>cRn5( z+gF_FqNswW!T$=oCIH)>``Pl81yV#BunJD&OY>Cjryk*aVaT-9gE*1Gcz2=7WY5cU zsERvPcYp@njqDfQso<7OWAG@4ll)JlN14?Xx;~WjL)7-B_(8RKyrN) zE9X__1HM)U-WE@Sy-@jQn0fVN80KcRROV>4mV-8W&j}vg4(fIoR}J3RQq%R~emDR%!Y97DFtFA=E19=Yd{2bPoQJ zq-Ut-A$tl>5#&SXD8>E5uVAPzB&k(jYI!6dIGDbErF{3Ca@arLaZF2BD9yVAQ$YDN9cqj}y^{QLa@Y>}=UD`}_hW917Eez>$-nTK0|Y$wsQ9eP z^L$0ECTC+5(eihcvU`d;+A_@kTSrPW|KYFO{>T=u6`X|qE2tyuH}!e%j`$U5p0yOo zo3I`oQ&x+ApHR@^|5hIMDlkE76tpZe30?L7HLrG5L^Zts<-Btp)KP$Iq~J3tz}=E} zk?&8G;S@^#kCfq$s`k*kzoauH`lr>2It8NFvWBlIVie~Gyz>i#C&0)r9eKEf5fPwt z;`{$WRKu?=Qvl~W03Y9(0k94L0lbkqa1d+sz2{)bP4^B!pd#9b{^}TH4KlFg$|M(k$QU2E<-tINynL z=G+vvS^%k)SK(AXJ)?3rsodiEbhx7?v1MuffH)D2y~4hEaYbls7i^l zEo=+w>G{+dNdNtK`a$XPl!CH+>H^tLYP9bM8N zbxH5)l8$vrf6*n~-X$HP|1$X*+a-N!m-P2t>UX98$u8ycefUiLfy}hpAB%bl7!p`3 z?hkYs|3&H}ArcMeq96LEv&F^nkvUxcCu}-<<%Q7^rNk02_M3tpd--6Qb}mrU&XC$A zIj-Po^4(;Dz-8oZ3ihz)CL#D#ipKIZpt~rpO@7=NF zbGz+Kq2A#|E+MEh%&~RkX4Fq+r}R(c$DUOmKOc9ldkq0`Kqh`+2fSW;IHc7r6Uo&c zUJyE^%52udyWLgpHaU=9S4#n(Pt2d~XO0RtW>xZ^&0hIrpr8z%L9Lm=)0Z^xyecFu z0oII&8WA0*Z|bWPNzl+crLFWJ_$kOqw&Am?e*iYeZ&v>h|EtW;-)Pt8k|T}r4dkPZ zeesnbsFnr``G!EQzsGw*OYC}tQ{FgzeW!Td(!H(Fn-1xjQCXU-70-xEUabCnX7q6q z_SJ(Bq!WGD>K^aGJeA;M*-LW8xP;n$mV)BM>(|VM*a7)E-t*!=a2|aG$NDS<=x6V& zOg1UCWy?VUfnWN(Uukz-MM8D}$e59%*ZxqX-QJHZK3VX(6FO-6B*z{q6j)X4*EGs4 zWUWpY6s2Do?r;2cpXufi9Dzbeb+zb4^3duY_6Qe#!tDP17Qcj~B)QAkH}*I1EF!%_ z4IG>cSm%dx+e%rxcD#Sz!hEs!B4)PKALq5Gs6Z!lqz#WFAWDnL89IO+; zD(I95UZnF9wj0DE1A7M(JnQ^)m1kC}*+$Q-0_S$yu4ILl(`EBLmopnedV0u-LnE6u zr8}6sHgXq%Ua%^PBq%$yo9dKY$j@a{i(34+&tha!o~SZE516wW{pP{)#uh(r0^bTS zL$B-R4~E4#4ix!bHq2`c>z78;ZjMOoxA&DQ_2HDh!n!CI8HjIIGnue#cYyEWYme*< z75oZD*etLYz@U7x!aX8Ki(Ew|65Zq*@ptm><9p33xs%Vj z>$PZzR(Ba1;Ry9R= zWPl_8GN1RbwjzsFVeR2u?e?AI)*kMrE&Gz34&zfo2N2;99KUpM5I^~zQ~d$AUCPtn z#=#|RId?rU1RLYi9RJ$8Lt9Y@9%(W)zHR)?)VTjZ`JQ=0K#oKA01BEp*01|eh@Dhc zy3KIE>)x&!;KYKA^^0(_9j;^uJj&i3O_ZSzQS{+4SeDVl%Qp3nS`&kDUBux2&d(?P{{ z@noasV&zj}3|MkA=ha5itpA-8h zX6B4g8ze;D1G-mu(yw#SlKgaD}l?IGv8_kl4)MDXL~AsgnM2B-hc`rO*^hC~;S0=<`L?OzQL1Y)!__059iV(tX*} z!F-gM7B)va`XkM3+j~^&jaZEu95U9o#Yr0gpITj!3?mcZR_syum!K!Z$46Jk8tFaWFT368Z~Ot5sAO6| zo}-~u4Jo^2XKLf2g&i`{4k26yAP6o5L7W@Msd054X~u}GG6YgAmOv^@8T8mUf;5&d zL^*giQ!jP`)F;#5OZq6%9jIFz)N`ECpV4KRc#jvn5{67#e68*PvSn_H%>)?)f3QqO z-^@%_PXnXF>IXYgtbTyfID64KFfG6OR3h>LK?w+AZ-dk+ehxq}9+b?YB>uSSjo5GK zn)FC;vZj*dyalP_Gxx<7@J#7j>@N_l;^XPv1jF*&_Yq3Rv2XuV2ol3M-WQ1a`S~ta zqPjwMye)D$1Nao~bLd8Hos5w$ShmjQz6IYoYOLQ_znRRyY;(fT7L21H@N+e)DHzwK zz-PABZzjK5#g}CXRUsyt>~sc0ps7*$cutq~*oIm}wD3cQUV|ubAR2m!)02(-1{>!zTKq4G%mP+Xm7Icj zPfze0Q0(Jh%f*hxHzBl_5T*D{M?;qk@blR()YeQ_-*9@4pr-PcHwJHEh${@ucmhcz z=K6)~N?epLSah>deHezD*!BmYFgZ`R-@Xe3n1=A)+O)$c@h|EiiO<7okQ`wkin_}{ z5&9h+obql`2jfjEm5RmJrtL|W^+!FGQtJ=U2GBok_1ALnn6Hz7T*B(?E2z0mMq*MV z_IK|j5*6p&QmS@_wD2Q>hTnr^wl<=R8byryT4fPruSxw_7RD!FmFS5{)ktuGT#Z?N z8?`c|_*z8TJ7gbX+l@8cA{FwTJ0K~>7QW98y!o}lmi};%gV5Y4(j40%O&Ohhq;5Hz zmK-(!sSiACdMw=_9H#{;9(eKu=H0g`iJn;ha}wmQ`_TS&;1JC^ATJUPbx9>f1SuioP8j<2lh%27&J1_KV zaH`J1FyF9SN^h#bC>>Py{&n?{ztonJBZiy#R@9=hmhKpH*~94^I(7UlX3w$~xq`!L zH2%KKXZ|v?jQ2O4^7MGCfS@ZNh=Ilx0gk39ms2>f=<13o=yvdIE}wkM7-*Mp_`>7l za3lTsE&9yF##}Rv<=9d5CbU!}_j7>$)^5S}QNgw*eJe*&`C*`~Y8KpYPnXF%3GM7U zDl5^k{_nj1r%u7hnMl9v_o+jPY~;lz_ea)_{|++Q+RM=YP9DN|X8CRi&9z9GnT_az-%*P_X8JRhg>PaS$<&KDEx> zgl0MuuV*kSrN+2;**9!WDkVI2)Jjg#&r>P>hNG;1%RGNad}VsKwT_nGo-!yV#q@m1vWP z|JJ%RR!-{oYB0J)Fefdhwp7(v08Vks!kdzo5o?IVM%auj|yyic0p8 zxQAhwem*kxk;jX zcXB>H7a`dzj!)6LL#y)wf;ngf>kqX_1#T2m_y=$k?3t9$pILouTIRd%KfFU z^n2aAflp9^OCi0Jmw=@v%svjAvKe%g!|5k{YBMrHVVJawAJfv7%_jkchjs7A+6wl# zC9y~J{?g;%k~l$S&FiXTd|Nm~RtJC{{xMg(Z7R0SM|6XQr+J{t3iNL0o^HW>&wQ{#(nD?v~otYX^An}np$j^)tT;b7;!iE**~M0^%4EPvluKZCyOPK8$c zOSVRsqnB1i786p&t)$LC?3(R-exW=`eE(|&M4&m5UW$}KlVbhwKaj>NB9a!Aoqw9f^c~I zCI#l&BvRDRt9US3(OS{^3Im=mOR8QjS+)@1(`lnQxFzT1$JR=HE_cxrVL zRjRr@k7{aGj;Xse(LDLx5GiF$D%KocJdN<8+Hx51QY|);hGgIiJy6)6wm2-LHv7(` z$nmlZc}vRUM2DCVsM3Arpxg60=+qDUh`sK5UPD_wioN7*0kdU9R%jGIemSDsP1mYV z)Y^9*n;fnD4on1!8K_mXg4J@qiD>VWJwWr9YFbF%*jtUG`J&5tr40VE9sYX2 zUr+Gc&ldcIzZ)T?gTMTr=kGX&-iLXl_>&Rp@OSHLKjH7sw<>uE?i9SV@4yEH{(t4~ zG)Vnl`O9(mI|lyb41@hv-=FYzAEb2fSEhD4f6{;Q`#;#2+jykt%}LYyr_Dd%ugMv= z7iYjr`wo9|1^$2KZw#a+`AeOLUb@#{Os8BRr80GRVZ@Q&!Qb=AuO#IufJKdHSb9=U z&@$;F9()#nFM_8gaIpbumbPOQ%F1#JAmR3GZTW}1Ffs7qxk+;C=M8=7CaKsJtva*o zOrOl0d_|{6n?lHk_(V?joeJ;5-_|Z_;xtOVLR!`6ZCdQ9_cxkN;X_PZx0CCOjw7zM zY4PH4EZc}q=BWCPw_<_lw2S1oTe!Vi81TO5ug~WeEVlsp5|M2F__zZ(gbAjP*~&K2 z!fyOJtt+@4Kz*a@eC}e@Y}%M}lzgyIgqAe);-L|5X^nrTI-qM|`6j&TO)`G0J6ma& zFSz!!mdZv5o^!7j^(OSN0*Nl&$BW_RLObVqKO^lD(R-KX@(8`10ULV>JN@(brSR9E z-hxW;8wA+Pl~UEHX-YZ>ITiet>1``PZ~wYaQf=1<$8a6JqI|1aW>3ORF`{D)t`%?! z+a5y_OOtRkZwJ0qr?b=tTf{IWPdZLt51-$r=DRNO2j|YxRB%1#;F_y&1(NF@_T`@h z*MZTwS@Jt#W95<)+n&Eang+x1YAC9(&r6bKm&=Rt@wpHZn-7f0Uk)&K^6!&BsNUtg zJQS2W6l`WjRf{hpdc!kvY>E&o2bQ=PgN!aW?Bf-4hwK}j=Imed)DQUWA}#WF?5y7k z^+MFXH;5Uu_;(>um%h<&;|?7lP@sPI-T8nOr0Vs4+x{)}ISoUfRB#r59%u0v&ymAS zeN_IK8CB6SQvzQ0e5NYwRXb!OGx98W{nqpk{CJI#M@Uq1EyRe9$*sa|tTZPzsI)ms zewcNNpgShrj8SB-Zk7((uP0Wi1KmOjC&3;%4O$t9w%Hus{S^f3^^@4KcmV8=@lUP&6D#JO8qvi|Us`|it;h-g4DIdiJfJSc2wrh14VUes0 zO9(0T@L3lR@^h%Shwj~UYYw|RZ&bno(CiG3gL<|C<=r&+e_?K{oSOQ}1hP`}?|>?y z<{YSS#0Y=?ZWTAdk*UG&44|}g1nA{c1xSQL6R3*GeU(WKa!{$V#oquXg3SI#dD@=> zsy_K6T|em=5tR%=mZi7A?7D4LSLGkv-L$70w}P_$&s?)r4u7+yh&%j@e$5uSDxF=` z!1dxye;jUBH7qWQ-sw7b7GaYLH*s|`wdIe2ZfVT5YUlzshqH7%K84k6J-A2pLerrE zO^3UcZVtER>*k~nVz06GO%zOcFiTkABeAIL@`Y-uILOqkzkI(4#k#ntlQU#ryFo<7 zeKO&v3Wp`Uxk&mo=H*>~nUG~7HkenDx{@}RF)FPwGekD#B{O1;v`V1Qd@Cl7Gv^i3 z>*I735kkIOpa>ZUA<40G^E0fDl4Iv(d_DZUt1AN0>kWJ7dcpXKU0#e4!Cx=s$*n^> zysLObQRox~PxsAYP!35Da%GzmIsu$g1=E^SKiZaBqgCxs?BP6>@`(rJ+~SQ^csN>r z(@?|8hO|FAq&>&Ki3}DF0L|g_BEv9dk2nQ&_0FH6)$N8ccs*g0EHp*M6uXX& zY4zVy%0(2V5ro^H;Zrw<1{~bO8R8izg~5#)b9?EV2EVUT_Xj}vHM8^X&vM0&t{pp! z)j0REyc-25xWt-J!pzd$8a;?iW^c z?2}Lg^*chrHT-HBCzGm`nk~3V^==6UGDE>ilDkU;t!xUA<6An-U!CQP9G&2R5q-8%1gH)+W6JDL2V#Y+`(*wU zo2Y(8j=q%Nt-_gF#C)AP{(NbZ&}!|H>P#p3ws8~$w1g!?{#jw0zihet-`48>mLvV} zwz|z}UnGEX!a>1mb^oG}gLGno0@1rgQ`tPJ^llAAN3{n}P1-+Tv3pwKR#b+=6ZEny*C{$UHXNIS;Fh~6#AV0iDASs%NyBgEH!!p_VeRx|&J zGO*8+`N&cf36MiQw2M$qLMYZnIZBK8nboH^x?R_tFP6&Wz~!ulgL_b`c4cLnx%}_m z?wGOCxA>w(_~Qhp=1l(v_72}hke>#XAcx$X7NmG|YM0XP-Y6tg@#8vQ%NM?OoGbFk zd)ujzMGa;bqMEXnMPe>{`zy}QV%>3KG{Z;O#(Q2SH`#2wMObH{J3G9v8@rBs)%eMK z!NIi}dzb3QyFem5?%`&g&$673XJ)(*Og<|tQswHq7CD|Ya&u%EPRf#4&DRd*=N-(` zz^sU4pbrzwmI7_@w*dw>bM|3$nJxT<&ZNPvshTwMDV0g1P@VznMdemSUzA>|^s>=f zY4xkL_$_pEe`WY9r|x7PQrEdE#SrIl06WSv;)XrLDP7bU`^hr%Rw(1!j- z7})XGElU_>B0a&nTSUNE=QpVRt;TRgKR;mxC4%7?FmUELcnW;v`eklJcNRmo9$w_) zyNuX8WsQf!fuD`l$je~!<0FJ)?jT0lzr$zwH^`(Jm0u!|X&LLhOPXxdIqG~Pk(+Xi zhZd1}iVfNJE1U(v?ED1UoKA5U`4Jtzj8s=_9L7%Q zyXQtl-&AmQ=TW#^DpW zRiOeKZwfwZ=>B{7lHR$1NPJq>C+7Ii(&rh~dPUDj|C~QyU0E%LIeK$7t3?&tG;nM= zdx#UZ-}cfVQwvJOG)0&=I^R$SkL5=$7oiHo8OCS)4kfk1!N=f+8JtZM0K-@%Gv>fGy*Hz z6`ZI!#Qnd2=g0>Q4%y?`YOCb?(?$00Urq+!JA91P{ANvXh@7KlTUfByc-_%Kt^&yMRYkT@C*UBoHoPqA(KgQK1c9TB4$f5Y50$ zI0Fd=HHr#K8;f{Hoe{i%gEIp;9>-!;)Yq!CUW(VEtq@Ql0nLC~3upzjRis|dI9@<4 zAOiFK*4}4s0sZ=apYM78JP(<3&R+Yr_S$Q$z4qE`1Da?C$NBpe+db8V%V2I7k zl=FcuXFg0SO`HEi2}<&6`jGvM=?t8+pRtdBrsZKQSo76YC`CB-QoAbtd;5h$kPS-s zsFkM@Kp^3C`e#Lv6qA`3fUY=rf5n; zr`5_Q`$AHk0B^y*@$fvp2{&SuyO!Bj3A0cqJ|owt0sNA=pGN#qOF_KA=0FO+x@?8; ztMbH+4ClQ3@zh#i;P7hPF0^eo%l0dL~=v+yqw-|c_UEg4#+_cLTjnYCGSl?Fq#{^g6pTqqphtLXXRg*AS^SGhSEl#&`|1 z)X-#xBt73~N8&2gjstVrF=q)}O`5t7JndQYitha#X?`YJ-#}w_$NglOlz3`jZagC3 zA5idkV>$q)0Ho^|{+FMBS=apMcgg=iUj8n22TdV{`K~MS2WdYlP~>TOu!;+%9JU#? ziH75NB5=2oCdRYJ`Ms>ZNOU=)03^D(|y6DldznsL1SE+xyNVz0))rIouS!2hay#yk06R(7yla z*_5qJ>zkq(?n2xoWedQo=;1O36Vp~Az~_1RoX(Dm^+R>d39$Oeoel+jaH;BH970eO zfEhrUZae=X?M(g_eUWjTiusymj=vl?sN*1uy!Bw_e5s)VK;e_x>BP?nlv>SOu_PTf zy#Fngfm2!i8>YVeN*xx}?Zy2-^RzXAPlxxP$tIg`YaW<2s;I{I-OP^UC#rv4{DHm@ z3napsT3r!Lm9+CJ@^5Nn6Zuy%7p&R~n6IJ|zv?&l1};df1*HxvvCoi8TRAw{+v*{T za)l5ly6VPVvg!_=F9*5IP2AtCIgdRVaPYA0GKIADj9PkJ=f5D5ag+VkPRXgyJLufO zyA8{w1}7qe$$aRS{4<4otP6=zNO}P^UKi3}er``eDx-Ry;<+55ye(ucAJbQjd&ye^>Z#2ZNo!St4TJ%0zswLe^ z3*=3f9ZCVQZ|*0`pRk>4ou`lNOVyLC0luVFQq(s4Y`$@T7#lnHSD2$F^Pgwc2fDJ6 zLY*F^HDJ@RHE7F&W4JMu;l@#&Z5P58gYxk#hCG_#GWuhnLDt4q?X1FQc%d%QNriW7 zo0(^YNJ{aH@X#V@ca8eRo+>S*%_eP@79YhsOW@?o+_+&E4M8@I?Q8F@WQVIG*M6Ce zw>y-f-|-v8Z2mI^8Z!SbTl<^^iT$aa{-t9X9Q>RfF~OH%%~f5G-6w--)T|VvW3Yd6 zMp}M5p8}T-pSF{ARvFRU)NO{WCLoRdFZsfMwkfR8-u$tyXoBh({?R+6!qGEitv1@Q z?h8qy#LY;vgGmG_koCGpci}|3kmH$X|N2=~S{6J}AmwIqqjDh6^7VIXJY)TaEp7^e z#1-tJ2ojg@3mr_gm-m$iy|8#eKPyJ{gnnK?1MOW>OU!DQ=R4(l*7SIw8r?~W_;&QI zAMr=i{HKC`nU|=cIgRcq;c3r%CaryE`A1qm?KvrNEv3$rl)9Yrbb0YtBrq-o-=Pcc z;D@DR)f&#HRWkB~0<0@nb6?5mqp1z?cEtzjg~a1z!K#!*QL$}n9K9EuH|PqMWCwNq~L6{#jW zP6O@bboz_o99?(+}aCi=O_nCs84WUlEY`m{0$7asI0NBnK}OypvC=k~zo(e@iZH9PD^c5|rqVO{OTYL<#w z6-`3T`I*!wJfIn_Dg_0WP`Tq9vR{3s$(lJ$4LV+^jpl1U^G$n=oMRJ#uqy7`O}S{p zKU12@P;cwBUf{#>p>AKn>7AAVb*(q|Hb)Vg&$kspJQl@m~&t zQfwKd`OWej^1eL#E?b4k=d$l;OsV9{_h^^ z;_~EES^0>05cmf&@YKgx*~6$3D|_;Gw%LU~&iu7vF-OqMmqb2i_Fxr#eD(zNaTcGa z%wscPXk!cUhGu=|-A9U5+?7o)z8U6>5+k;}oky=p zj_>V*Dbt!SRyY>3XBe^hPzYdL-eKuS6?XINGG#3{=jc?il49~hQJjHJ|uG*O0EVSN?xW`BlYOuq&W z9zLxy_*J~FTFS^t2!1A+e@SK*cA~J$)`<+&q{QV2r0n>lKf@hD6hRrqPd+IcP1=5& z&#xgjz29sFhgvh)d(f@-$kIs(%iWJCF6Q_b?@k3uJv&}y69_ZOS+tS8%|PEBo%(}E zKBVM>I$^=}etaOra2>3Dusn*1sg#FhO|(p*$^Iw9r#L*Tvr#0O)B1YNsW8;*L07rg zoLpkgDD#>#)L>b@I?hyAOTTdYsemIG{0_C_@Cd88qZj=&x5b)>3PF9AcZx z2=!d3N9bdQQai7!&B}LZ`ywq z=r=S=2U&IMb>vNj*eDKVB1%E!WUpHP?%{se%K>Vzi1tkN%1?gRJ9Pg-XF5;%*w_w9uaU8NFrMVBJt+)a(qdQ^-q~ ztLfpuecS8QtMsd^y{t0L`_(x8J>aEX*sr*g0R-aRw;7yHHE5U6squh^;e|a7g8rg$$d5H(G1DZGXM7} zFCYIIf4xk9*gWC%YRX+5?1oFo$AlKSQ9MHeerw_&B6;632=B2EgZ&axfpp5K`5`cU z`1NJMZydB^by5ruw6hQFY}m^_KMRIqkQ+D<@{D})vxiY)-;X{jR_ch9m(`$zh-m+9 zbS$5Ka`B<`CM^oreL{9eb6QMMIMOR&&rNtZ@Iv%{r9PFuFAIpH_`ydo;#!9dS}Go^ z{*I3-8hdp#9ES&x8m-mFjxAoZ-P5u2NTcKPf$XVxIHq{n`=R;w7wky*hiqc=$~$DG z?~0B~Jmz`_a!0~k*YQ2yJ3K>PceVPdn&VP<-OZ@-nrpRd?B_iBE_+}0Cn;ODz*hQV zgZiiaWY@DkDD;H?39??ePR4D!$9#|v3sZ;7gzLFDTDy+Okm`W;1zo_ zO8R_On25d>r)Vx1(v+ZCO_t^!;c<67r=UMls-<$?ZMZ$Q?R{vqlN`lzXa_?+gyqDwYe;=~VyN1>GtG^ViKn zLCKGE*ONoV^PU+n>>4nc?5E(<`og>B#<|6hB)K&Uo#FFP?OYxU0%!npi%lM>!ZDJ| z<-~o?=E_RRO00MtKP>$|Qa{Bbo8{x- zKVX0${N&19%c>C@_VG@E9sIA!gj2Nd6)ml{iel%*yQ}enlj?C}=;Nd4D=mnR60<)| zkof&uv)YK)vs);e)ap};vp4?^zR+3x$mfN`<8+e(ue*nZ#A5?-nSqfKV5A)s zl3XetcD`p)?wwb5E2!~36Bq_j>~2!_05_Dij5Q-WFZQ;(S-#yN6xfpzpun{EoL(qW z3F{k*Nc@I+vhr{L`+1?-7j2qqn2lRq5tO_F`!?x;%pz9C|KUSJY}hrw0NJq2(MKNLK}txz;cvlO@7vlCEAsof>a(%1(`TOUHLF>NbFpX9-=s#PnkZ=0vVN7@>xznus)&4JUub(8y}Kl>>toe5-xzXelHt)m3&fcFS$nl ztjyAH9=*^0qLm`jBp<51?lY>#=1hPuoM5E|#BJE<{BD-&c-NEAIYXZg>kt_vIb+^I ziea;>&38g7 zwJVRO-`g7`1Q_nhW;{7iD6Q6kNC*aZyuGIlc@WbC|wBSwEjDtbZ4Grd1o9U|D zAnP{=aEiQ{&@fl_Kwp`3(}~39`dMdT}XhW#Rw^0yO@v zQK9i|u<6JSd&O^MPJoa2C^bJ4pMp2RY8L-F{$QE)OsMvOj}>9R>5AZ+250O$$Zo;# zFNE?SA8J!Fw6PP;JeFRz5K-1M3xLe!Jt-@q*7zTQIHD&y=$>r#OwI-lQRs;;@h zZ4EreV63i)+Rn0!a$&APwP#1iu9Tb5Y6nUyT+umzXY_euFZ_#l7#A`7HiJ+AZ(+Cs z-0V#KGR#&(aY@QO_EH&veSiyh!on0X;&nr%pd=^hil6&8jTW_E%5FerLp!zCZWAtB zdlzZ&Fbs`&=ABFxpVBvW-N%*LU(1z0u_E1|j(_*ia|6+;<_5oNZWu!d=c1!fJi?$bIJ+JCV|>iHVIFqrj^og9IrK$$6wOdwEb0dpB#TSyAR`* zI4wJ0a!?Yhy>qJ?EJ33c=s6UAJOvTdsa&OR8l&jx?uP8Nye39jvb^eo>kYp_>PSR1 ziNBpEZzg1!rEd#(R0p0nX!ER`ifH`^Y(PoH9H|H8d%xDY?XbU5VuP7X4%~--5!8|_ z-r>VJw<|jByF5yWcvx2@jZeNMlb;FC+}G4_PBFyNynuyeF%q|Vp*&!PXPC5APk^Q9)ttHhZ!CoR?9=Bz7=jl zW}PBCXaB1)*7sl9W7)3KxK;Y;kK^}~%?iI9_mpE+;3y+rrW3F8@TY&KF#P+k91LG^ zi6~OF-|>??Jj)OE!FS;BhRpimT^<7$DztBK)(@P?#W*hl!RJt~&mmrYgop1A>G~Xj zU_-q5=&>*Tjy^V0ii};%y>qZMRga%x^<}W+g0O}%hOcpM|DWSmWA%@N{$F7A)nETF zuzD$2wQu`|LEfkY(2wJn%>lhX6smQ908SavGIIk8Kn2pB_t=?*`sm<*w~_gbbf=Pa zjQB#kkWb=AjUP4|EK0ND=wI+47LarJB|;;yk=vLX3>GITV}oPIFgCGab6A?OqWXy-U^EA5O-;DM%d^h`cY@r2Lp!G!R& zrQFjPGZchg^+ana=tb_te5ymFqCa`9N$@{^IoicSulb(e?7Nl?qebRnckxD~ZrEd@ zKjo$MKl>$GoCs#*Np3wQQV-|9btPkBMPhX-@T2$mhv2_dT){FA^mI$PXR(Z>MW@hh zPO_EJFh}!SPE{$p=UiBU)ws~!yB4&-bQwvtT(ZC9gECndc?>o?Uv+y@?pqj2-HzmZ zEXU7VjaX6wPtiJ7b7L)Eg*CIyvs7wB`&t-n_qzOz73TLCKvV8Tw2l=@2|-)uie{s? zSPn|Le@>yQh4F%7L8G9&YP$;Jn#Pa5pN!ES-6Q4Rp}RTED~K z3=QZg1S@&y*clbox4CU!jK0MhPGj_V7R!m%3`@#An=;v5T=dW0 z969*way}N)*~kW8jAi!GOB)Mp%hZONb08ot!gieA#}7 z_JH3-gbP*Y3bXjVfQ(?FTw~#6enkIsCae*UOOtKiZTxlb0Lu=mxQ=&OdBN9d{bH$H z=s;Ul66cVr@lVNj)hYbG$4?r++h=F-J4RqL_l;oxR+R|vNRNOlZ!-Jg;_qsCD!A{+ z;dXUbvdXHSgx`>~N9|9Nj&JHk#6mAKyUA&xZ22m*qWC+AOFWuU8s5X6ZGMpxq)6=_ zMR~;bVV6Cx&dCCh&fg_%YHoX!&w(?41wQZmQl5P{{Cz4giC{sDv)K^q>w(Q&xB-^P z6$<{s4v)nxHG#&)mUh((F)fXW9oCKAi4l0uY71XKPilMx>*EpNOdsu0?f@D5LRJ-) zaf?Lj3JDV0@O(%mH!@fec~$uE7LFvMr!-jO(<+^Ve3zVvoYSd(Y^-m{2*12qWeJ=l z4bd$sT&01^j=3n|2D4 zy)eG9-S}>rXFd*kM*Xfgb3CB*_PLzJbZV>zoMrx75CjL-!J_5rVRX+{|4SaAp@UZehXtdrl~>5JXTcaS{%8p zon}b;{IR0;O#5cH@-JQ~v#ogXk)NzD| z(~8u4>tNy>1))<7m&Ugq|72$TwL8%JnRlULs;$-4UVXh&t$3^3lcj2wZmHzc8ThQc zw2DLPAvd{L1z~?y1syw2QH`1luj{#Ro~+T0LP9#~X@Gwo(?BK!l@?N|SC}i(=AG-P zxrlxsZR}g{Prd$l)fIMOGDIx%uMIO{D*36JFUb#o+#bQKG#e}8zBefnrVo*fsgSmW zXI7vgdAp4e)!7x9$DA@+X3~Na1fLDDK`YS0E)_@*1_P!aksg2!NrWRo_gT%X=L=0ObVXM4B-t8bGvDa+y+M#Tk%k_nHi*#?OB{zERe`xh-2;@$ zCW+}h(irkMb?1UtJK)q%sLD%c5j|K}BiVAZY)LmPw+2x4BQ=PX&*NIoJ~^wrQL=|n zShI50WZc+1=7+ARgfJ!u=^|+}Va{{#mTs;gv4ye?Fgv-ZIad14X==U<?4ieR zLK}XbG8GZ!n$?Dt6yP7I0+6?KEB@RCKn6Td++sM(u1jTWWnbH4vugLPIDl6d6#tU&$N z1r`4A$`K8*2Zj9n78f<4F0o@f{dhlTJDHz@7=W?6BWq?I>OHL>aE>fL3p+%l5U`IA zql}u>!EZb&gx|_Ce|S};C;WXy@I?fwu%-ueyN|sp&6?_Hv6_gm9K9i1SJ2q9hPh%g zL2yfQVW3!SG?R3UwS4Hs8&e-^L zU&dXL?#pA-vwdOvKcoLPwyY;)BpOT6@AAgTKRMGU0Y}2?`qT1;@jpt}@%rUiPJO!6 zA`&7kbhNxhJ^}C1@Hgea_xmaM^ELdjIq)Cc@Dt@<>$K;xYc=u3 z$yx+Baaz$7ES8z=MX|e5d-v|$vF@nXXKxAdFJPPN#6M#VrLs#il*|PkiLxClLm_Hk zT7YPEd5N1~bi=u$!(3OePBmm{0d@@|ys>-35RSNS#Y|SXQH~0#19esFQ|>n#WSz^t zpDVJBBCXy;ZYqk+b}C;zSk;{{JE-ePsfxml*qCl+oNCt96~vA3dz8J!5Eom!aK=fl z#pm?rR=3{4L3;jn7Imk7B?nU6_8xOf{5;p<0o{NJYzgfu4g8BmRS)Twx+XvlM67Zx z**+V?m@Aanf;>vON7G2NldD8PR0UL<#_``*D;yi+(l~yZavU5-e@|A4&hZGpS$^*n z-7}P!E8pj(+@FtCd!0WMMbKkzql(pNBdQAJP0(39MM_nx^eOW+#Cu&Jyb9tZ+M2W9 zIU{Xr7JWhn$kQf&^?f97rT5(M@kqJvgf_&F#u_$=uBP4QcgEjPN9?|87Gl3yc31(V;MZ(>RL$&oK`DfK`uEjeVvxlrDkEwd=vGy7q$YW zmdwa(GU|qFQxjBplEn*t2T2HvE0%OOpm8}2pIqZ(f&g3-sT4Tp&ycW6s>|R6) z?v@f3OEo=uHi)32wJaNG!cn>j>*1@4?3RH|X~*nqQ8>hw!1Lo8^x;!gYyXr1b((yx zfPT$@%>(vE4f{t8dvgZXDfU=k+vGWMu#AVc4^^kf!YUrqNgbk%i`~BiHwWulZf{yn zhKAT#BmA>FM0=@vKUaS_)^Ca3CvY^9a{TVd`dJ4fC`X4sM}1kDl<8W?`>C9i4SuT( z^`g9VREB@32ri}nL(t3_f)|9ZNV~)(Bsz^o;uexho+088XH+?zdNEz{3LP3PY#tPc z$l(Nkz_L_iH<5|Ws3S+D++RZZG)OxvS1SXPUTJLwK@%vL(h{erdQYR2EZ(K^5~&;{ zrjjf7A0O2EbrTN97(e_iJ`_0)l_RU`4C^L>-A1CaS_n*ctRmQU#VX;Jd)92@UZbd3(F*>L&Rer>2Ba}IaS(Qs+tc*a zJ)?OYFQ(xEWL08|7>=*#X#2Gw?kjX;p#{xDkW^n*oVh%V5^ ziu5wriD@ut6+@8N!(7y(um${nwo~EvXS%{Qzs|?+Hv7J-()j(W(zi3SQC9z8)*$3> zpgBWPMNm}fx2uGrWbwY*D#6Y*JZ)#FWofNUZB_%T=(L^fR0wEYYMxkNX!KZzdT1=R zwI_5-zf|jY8lFmS$=DOXlXKV$w2Z$M0Z)n;e+szpP6uMZ*>!{=tUT zJycy3Od3|djH&H|G=!Y0sQDrIzNo%xnuw0g`Q`lk$yu0d6q|TO6v2Ls7DU_$_pTJe z9k7`H=jt87&#m5Ic{+xdD~;I24Gpm+V()|cLp5AE86*sH{Bkg>h98BVs1FLLD!rIByWzf@Xd6dl)Hx)T+oTmOeeHMa2`I&2awt|w4*c#G&@FT^-$L~po2~KEp$1eg+tK_gw5urClgru^;}5rk zrw$p{GD6dbc6ASKHd>lWs=XfLnY4)3HVu3#CTyWZ_`zDW)#SpI-`N0r)N|3!LK zACMk}W({G~<~#;{25PI`#~+h<)i4i#3FS(4sJ&8vHGmN>Dpy$0udc=C4$*F!B{dsv z`I}_KZMwsrr;1laYUn#7lrB}5*#VscGVZomGZrQ=h@XL@bLL#wkZS*3zAv=h6OeIDU8#P+Bk3a|1FRlMq}$r;T+)CK#LsREWQ z>fP1owyNh&zND5Ii@W68i|0gczK6*tTrvk=`TkZ@(|Qy$4EI@%OUuQ2_)pX^z?d}K z?LHKN+I?pjLbjUgs@@kTyc>k^5K};mp2-1XdYe?|nnPm>1atzwTp%1Py-&AtDhZ9T zTV6{mKOWbL(LDqS9;>J7?r56LF88fH3Ic!OMu@55uNcI2I9IKUR3X^}498G4|JpjI?ifkKn-MRg#kTxu!>8f*eMI39HP(e^I)9 zn<}}n-M*0roVaQ4nR+zZF3v~}JVs z!t~jq05*B8ng68f!+#++U#~_v4PPWA*kD~(p{@&3x`pcdQ@DqRXRbcd73oHsU2{(0 zFImDnZ*)c6JlFo4`OC>G9viK3SNga|(A=VUmM3+WSZ7)ML{aJq@aG*=jRl$opQw3f zP&M`TpxFxT^Qp#@+tj(goP^v%os-=TX{}Po z?H!i@J_Yb88s6#bP?}DS50Iy8Pt&V6`(?83zZ=BRR-W=yUakvjqM%IEi=^qZq~bah z2Y~tjlsJ@Ukj3nOibkyVC^rf(R1x`Fh>n2(@>jaJ!koS+9-%s;!YbQ?rQpvX0l)`p z@b%a!GPMf}wF?ADT%7@W2HQV zmlrMe#||UfgQd1Il!zGrtgzv*e2{+qztYRR*aIX{6q;yzV{F7besiwCxgxfP ztS>@@aX-dfAux5XcHly7-&BmJpGMIc7eXB!n~VM3>&vRv;DSYDrEY#p71cVRT!K6* z3_71&i;IxMs|pp_|K-@Px>L<#4dh}>=$9$pZ*TCTDi1=6ZD(v0Sev{d)} z+C6_ILSj@2`wBSDr{+mz;hof7E{u*$EoSD_Z(TEUy>c6S0*#+ z+>ZwtuvxLYf~)ix15fxh4omJqZ-yJo?CR9nSCCyzQsMKrku@zNaw{dW)b7fV#T*&Y-^Kzv&~)n^U4VWi*sohaaPLacs_HDIMY)Vh|8?AAcA z#G2KHtDbWs8*LYB5NvguwYyi&0Y&z!!Br~xRc1Y+7q!`VT+aT=Q0g3ikxKNNTp+nV zQ0~FL#Z8NYxGcE?EUs^)qHz>P^Sj2|Wbq@dv`qCQ=dbncKdvQpWmC+N5{Fbb4gY~0 z`#F558&QG17?YL${d;wx72!MyO`YIZCOf*+h(7@o zAEk8j!db*P+f4g%*25fu7RceFjOqRmdyGfQg%=+_AtkG7(!~W%-v%he+QNy;wM}}*(qNP=; zlEwv|PVZqU0&Bp04`?kKC^+HBVo~sGBfPihhM{;fA5blZjEk|*?Df2S424SnT+935 zyg6bbVHI8#+1NUYC@~+%`QV)l%)a(KPiSW0F|Mc_0tGd^b?0q3Z%QqiGOvpnaGtTg;LG^4k3U8(PFd>W;(*}9XjJH0-m9(HT~GicJX-EIrh6VFzqhcXaJ6gs zm{ep<(00Pkb6D1E4SOH2dkpY9wwr6s4Z>)JM1L!aO!wli|BO~Fhmq7ZU*-?qnqi9o zcZL0u9xIKLPKY>v$0tR0av99f{Gy@z;H7-U>c+7T)SGhqy2nt6Rl)*EfOC|9Q}T@% zBumnl9+jeuLi={-;o=IKQ)sWCZp9ta zK@39Ky^ zUHgUeQNOKWf8iK_xswR3*5HlLAq{@;#K!IQnLBoD^TsYO^bPrXWUOeo`JQ*k=iZv6 zYxK&RxVg#|c^x*zD2V(j+-#NAYzUl(+2b7$c`4<&Zd*b+4fu4BYCumKpzN56zEM+8 zp>7s9M?(TSI7#>73#nW=ZmNNaTuK4T(VT-}*rtlFr6lQPbUhncYwfH4sMj4AQ-ZlM zu?c9sex_78dr#fB>$*E)O&1z=jP$eiXh|1yak zN2|m!k|=7t)E$)KLGn=EgDv{w>-(XM%f2C(mEzUqn`K{1^AwYf@xuw5*)iF3qc zbcjVAF0dNKH1&lZw0p-eb|6YG!0hGcz#167#Sc@5L_6bT{~>JiQmUfI8`Q*B*h~z9 zwHPtgoE!)*5Q#_8RwapSIZ0JHndJ=bOF*R(t^5t20VT6CPtCeb4&in4L6xQ)0uHvv z^<_z3^MknW9ePVURwZ3wE(_Bq!;G3!XPxC*+@CHjJxbBxN`w^qLzuypUTlBP?rmsz zLGX<*cWEWpK=i8r8u(s-bNdf$;tN{jwVK%`qX|}!IM_%=ISEXBo3%KF299#dn5@ef zpI^pJl;P0B$hdb=2}meV2T7{dsNkQr`GMGVAWkuIh!J${k-{$P1Bjwx%2Gl=G#I7O zA19m7ZZ~p1ypxs9`51+&-Vg6AcHO%wHu2Cs34;%mv73=6|7%7z|4VAIk|b+N_x8lcoRM_%~mxcFM1kRBi4p3&x@>KRxKK!q_@w>u}1HX_0xy@W{BdIcj&nO)# zcZumi>$oN11yKmGWB;8k~e*OtChK4cSYZV6%>xRf{#}zPE zdl}C{*dNILFs(XK?E@a678jt%ZPz^rPA&Jfl0WV}(P2}fbs9Arr(@hG9Y>PAW|0tB z=@?aw>@}1~zIgF4KFB}x()3n=*dwy>)$3C3SB8j=J83hjQD3M|G(`;b=W(c>|Hk39CL&$76tR<7BTmCPBZ5wO8gd?RI$N(5Gv>ii?0WAcIN^zpqB7& zZ9~nc0pbkQS0+ER@27PfJU1Q}Hf0T)O=*F%pfhQLIF4AQ$C8wCZ(XQ1FB^4dtkQD% zDm_8ImiFO=%w95c^JKhu$733s@#2K@WS1$1So#1Q*!KRJY2~IRkk-b-)!ciaJ|oKQ z;F-={O_cmR`MEb0EF|xnw{N`1(hjmy^GIE@v#2?lr5A(rtfXOVvJO8X6?qwUA);v6 ztN9r&Q5lZV8NNO&w@C?|;l2C}$Ege_=nTvAGHlctcIRjK2J&`AM(7N&ybN)j!Nn8@ zS?NwMRT;+W3={J*EY=yS@-u`~h6{9tL}`1_ zO$YvOIq*!4LsT0k>ug=p_Coirs8@22&9v_v=35TEuU9bQP)J++`Du$)nko7Fr1O_v zJCNz;KKp1#ddFSSzkCnC=Ri%NKc(YU`bjzIZ%F#<>GUd<-ajY(pOP+AsPZ46(!V__ zTmF}lE+eSYw;d$)znzo5SJE#}r>|4#f5}OA?IL|lI{kT-es@lKg`^*wPQOc~U!Rj+ zCF#A>>DQ|Cvvbl%O8V!h!@B<}{iK}qvnBoYbb6Ia@1K)CNz$K6ryrowzm?D$;9rvKUW$P!6^h(D_Sbt?TYIq6qPx->$iKd;j7&ZbB2ko05I<=>^!uTQ6U zx}s8aqPLUoHVzj0$#B}+9}yax4+!*gMt<7WD(xo8{sw>a{5ZcnOMkBDI>wHSnU9Hf zKIHM!sd?~1OTb^2{+L*n2mfRHtN-zSST9+J_am>$D2F^7+f!>T-st zJZ(L*Z{?o0!?JG`=`&{vveMJ$%BBtF?%eEKwWke9oG!D@(^ipvGdyiv@0d<&(z`TH z?Grq0rP;K}p0)$CZ&N*O2V~!-dD^fYr%RdPX)DjXSs@-hZHHt(w5kvNvmeCw#G`_L z>x!-W)dyL>I3E_M4+m#IEL0!*ray#lo`5#c4hsEN(RN1cB|Tzus)+>AT{Ht{-1M4w zAWJ=*^a_pHs~7;ZhP~Zg(HjsDYGs(e8x1Y~35ErIV8`d>Y5gJ*S@nnKGaqow6Nu~w z6;&C5n}OiGoItF|e5lkP)@D8o)gRu;e5lqRKFEBi(;v2EJ{bDLXPFO8`h%VMFhPI# zPv*m9{h=E(Mi~l5P3`(&n*LCjftaB`6s13eLtsvSJ23N24Xx^8|I9Zvy6T&oZ(JQF zqwAnk#*Hrv_~MF+O$vV#HGTrhWbHhK8K-T6jwjK?k;KqsDq$0mAX_4jmJg75KkSc( zs+E^EWJUYH&7p&5Nu!)uQjX-}Qj)5aJ&;1k_!@~BHW3vm&&NgbQI1#<;|y>Ym+V<&ZvK%VTk zMEnJg=LkWQ93eP{BLn9;M+gqgkq`PX!3cGjz{8xCU3Nddp&rab!Dm7H?+O*#A03uK z`$zUE_z)=#K5;4|0g$_=rUQUv3)kTWvS(6h_X618f_bEIkrPpD!lp z3c4#XpuMrWZuX>SAreBv7!oAM#L8|pw~G+>ZRTyO^5HR?ck;WIcktG{k>3(m>y0!c zH0%5VtNs#^60TM;>(Q=Bnr1#dnZ{#j!0>3_bcXElGZI({x8gdQZG_hvcZnLF25U|T zV1uqyiV1M+`^hjV()NNk5S zs7aJKl^XPg87J_x&wgko{#AojWgWs17*DKe4?**MX54SxfNMh`Hli}dw@oCwLMRt=(SV0u9VSOmZx^SnQl?j}W`?zayfu|-O#MIb#kolfHYpn8`cn^%7-Ct4kI|^fLK5Ck_ zN7RDf7H-%&d5$$ld({R{ks8$t!INu&oE{@wi$`bY{@@Tvtr8;PCg!wO{p`Oll(EEb5am<&jPM=Bjlgy@2vXb!1WBy@ zW@fhR3N}}|TKCc_zZDrI+m5)V;7<~jQmxUK#HJN`V>c8ka`3mjWgi};K_Uw~Ky9@v z@+vt)GusdvUp1Q77_R6SDeebQ*|VZ(c*vCY0Q!gmQ;;96V= zx>gPqoRp3_AT#A<+gwy>d-`e8FJBqapsNYVx|@@lpc=LW>tz3QKsVVxjfy`^%00Zl z!+uKq=(5)oh0DnFp>V1?kE*h4$S#-SnW59T3`$5%u_1`e75Rc9nd|oUaF&4Z z3{J?-k>3CCv{6Zc-TbHj9p)ps=xXXKJ418eRo3)N5)ppI-}X$$%l^9DHZ<=R&`nfb z)$XtPhwCQ_?)3@FxS|tZUYr&N1~qQ$$YTphR6YKf9+DZ{Q*Z}=TIIbQm0%WmQ?4DA5M=s z<9EP;YWyN~(s9+X=+8B~ks-TY7yB5+Dk`)ur!e(|q0hIQZWjmw!YOh)^Y3Xid`9`& zOqNs0Ldk7ADK_ygfH)$2z>gLQJ^89df}Gk?TsNz4bkV2s_*weo(7mGOHds^H?|KJn z;OHBkwkr&CCQNn2c_>q(@06HGpAi#@Tbu^U$O+XL)+>^cBSXT68e+kQCd!i0+GfWN*RpVW1-~6<~sK~SMUY3YPUywh!%QlHoNZpT)?az4E@ukY8;p19O_V% zcoeHu^>0oQEcBo_DczGguY_%vyP52_bV#3I8oG#?x`-PnLeUI@I8(+^x(ugzrV@nG zyz|PXZEx#lWNJt^I*Q26u~$%Kuly=6*Hw1kUzN`d6T^xWklC*a`&K&##Deg!Qbolx z+fdC{@P9PK)B6sXmD2hnJ!P3ITJj8scG&(?XSmCMCGb2v-SwDJQUsD zS7G^VTuk>t(cY73uP9HVhg zpy@sCn~-=}+;5Bjrso1rXlM87P5dpq{^tZ`Ys$oUvg%-g5|}NdW@H!-PC`DZ_U#`` z7O`wDC@{(^Qb9Jj2N-AwcLWN6!e!dm(JMp?OFI2{_FJDk34Q}kGoGS(=ZSQCD~RUB z$x?4@d^YMnbjgq{Ia(i^;ejz>4nAt(k_~nN^Z*1%TMyZo6?@>tSPzKl5<5B zFq<}dEh_RNQTTEkSGgY&&d{I^1`ji3d0DiA_+a@5gK@@U_80$$h1vhN1tpjGp{?vx zh~?&$GC0dz#JpbSGmGs%f^v40eY;())zS{O@V}Rz;wOJD{6$7cVZ!cpB16-{1;FXW zp6Ft%1htaosAD}x*uQ!NIJ`gL#H-=E?ZnD0=Y2E0SY&TT^J;{)PRFtZVD>wIeW zY%dx#IoQ_|x@AydFEkZCDRfx#Lqb_fkkcTZ*;C)9uq2DSh8RH>Me|XM(gA}wompHa z+{#qB;Q#40-ZbE30VnG_S-;6E^{e$=Ilr_N>7dtlmHbv(zTK^(Bs|%EQ~+Sxgae3# z#$#-^KQ<1_AWOUg`{i#0tFGvsyikOSrbK+jUKu4U2tmPgK7L6dOCsHRZDEdDV`b}d4eY!@oq}LiH|HHS3%++fV3DN#Z&se zVztWqfe#5;<$*D&_W)h*vcZtNs0x08ken?%cvL` za6M$*6>BarISi~E86>`7nla#xqWM|4wq2COz#S0KR_%mPwO+1L{HCX~Vc^@TB`NL+ zD92luNr(%pbS}BLkEB)m7Al`+YuH7!c-bZ34V3Imy{iK2;*N2wc*gkDH}~BX8~&m2 z;PxGB!8jEi85Z)WjxozDI>Ye(O+`?PlgIl=X5IP|K=*9h`A4!N?VF< zBk)9un1*!)%O(1eT6CxH3kuzMe!+|$+dX*nZo!MF$r{exj8q3d#4!{Jv~0U#ZO=jL z%Z0M{J=1p#Gb0Z#jy&JreSsY6&_|+Z!hX*~y?cYKkGhhoO`I>lvgRciOm@$}UK!?{@xMgWLM6mpjNE3wHYMEa~+9 z_TEn4U9&rVzoP<o-gk;PY&CkYbn;0T)}5zpVf}d9e_`HMuP*HcDNUMi2SUAFY7ezb z1eTiBH}vpxpv2_-C~n)0A#>&RLl+hWA+$gr*45ircJs6r25)Wy9e6ywDyW>aYN_x} zwUd+>popV6Y#h=tGB%*3VaS^BmYv~UCD$$Hm*XmC zN4ULYoHd|V&Dt}~0VUUcm3&CkkHuxYh2~o8oI+OV{7FVl?oB_Za4%8Y`J1?&`ljUi zyPeGdPoPz4D-p+Qi1WmS><4jx$W!iG;+NajSxGgn#r@lH9Yr+STTn;a%E;O2YiEo* zj+$cn2teX%>-4?Kx7Qf^&ZGIZ+90@IcxSI0`f{^tFX_1a(dcRiT}Oki%NXqpy1EB1 zPoqm3#!Y5Ob4(unvk2-Bg18k@A!ro{DsLFF$wAPoKZc;E)yh)v(;YN}9dG~L$@w|h z>Ap8PSNn72+s&fu&36N*qUy(HK9lT?LC|V^hF}kanKtI@Xf`SL#kVO(Gzlx4k=`Ob zyn@zAV#W5fh3GVljyT;4IQX`#03Uu6)*u$5&cG_X@$3)&#yh7bSJ_3^WBCyGZD%c^ zwiqa{i#}*TN$HWpukHoR5Jv2wwW_XInIxL`maCtrp2fv?3rIX#0cPbNt>6t&qTk}` z4r!ebMP5@{@ufOPbrxoUh;RNGW>g3O7&iijHx({4R{WV#Eu!~}E*UFM=(mNurQCO73b8m{T(ra#QG(Y8?@{87o!V!7D<9`+hL!lzs=L%IE#tMlkaEn zJ%iMUcpQaiRu>1@sjnvPenr^s!TGF8BNm7cP3t#~e{o;CyOgPS7V(%Zk)RpGAem_t z1kSL0BdGb8{7{P8!Q#>{3PHzq;&7ZYM0z3$GI&mBwi*rl*=y1*Vrt3c$uqUFeobwt zmHp|!P?VrW$}u;MvKRI$kv>*=F=F7*$3THCu+JNe#)XH5`{7v_nmB%d@x?De4X|f& z2*DNI4zFx9_duv&MO6q9UsH*uu;IRH*KKD3koZv0X8D?gmMo0B=i_U@Y!;%*5(tu- zsyJ22y^7Q(i;osO4TKKRJ2~hXmEQ`Q<>PR>ob1MUg&{ZPKEMJ0w2y$lvROcsQ>`qt zDtQyKQQ#c$=Kimls`O|tcJ)*4OZG@0x0_titsu>cNoJ)`auCpNy_&2tdlhZEB3G63 zZmAca-0Ulb#tX;?bwkXV%2YMi>uMq`q&t~7A6Ntzv_o<5p~_uAURSgXBxOnXk9s_Q zP##otP|>l_tiAde8T||$Cp_fK&==)aX37nY~SiVB3a$JwTtiB*UQ|^{q z1igXM@GFv+5)bRg@U5|jvk&JO&{PkYtefFJnSK}dro*bQO1Zb+=TMn&OKN6N_0O~MmJv$4A%O*{zx*)hCG^4N}_?0?~XINp8Cv@i? zx&!a|1{KjUedwMXKu@$2hzJ$s19GWoN3n<6Rf~%k&~rK02`R>-A-(~|&fm*2PtCNH6G&w)1y*XS74!xRCG116XDPRyv_7IY>!7$+`j#l1YTh zt*!`1UclWny&)qsddC%f5E_kx=V`78#zNuY4RXe@!#+q-t>zhG|G52f2NIq?2`Ja% zmqfP9-8^bj+W7}uLr`3Q!S0txYuW@ z*ZepAp6s=LGr^8iRrr+<#dUW@<_mXdiOL(+%!w4oDk6jhqnJ3~J>lPwtsZ;E<`6xp z&Mg;{3@45N!`QKfGqh{fSQ%EN_BofSbRNzP->lINwmeX(?hU_P| zE5pyqz!9K<0k#(&%BYH%y$8V=-L5kQx$itp@PFQ;D5Qc`(8Ezu;h03BQ%DC8H$F zQia#*ZU-)v8j4S#25|Qz^}$lU#(N`=V3r@wB0E@}9WphNDvG#gsd&$cddB7rI(&C} zfIgP6*ralFJmHG5x`__U#C$4rotU%?b9$NUj=cz?@b}$Zcizkpguf@O(iePLCMR1p z`j3!a3z^TYWD>$h4uZec6^mN9fJ)?F!bjCP^CK251NHEGkx6I?!ert~UWMcdw92pc zGZaN(sG8b}{fp$npCqWc{Vj+-^aTW(WI9;1ZN@^VB5f1__+EfTvxO78B2mEyMWW%o zSO*}5f^W#<)SWcN?9k0f_`R|>q^Wjy0Q@+w^uk*tUPq92rPYts|C1s$p_HTO`EVud+sU5FwRQ<(rn zZKzs<@1fG?VH|g%Zbzm2Q{u18N*}Wj~4xRLHw6d_1duBW9hZMAO8*8li2sff} zG+Y^|o|HKnTUvAh2*@E2p}#~0W;shKJKPv&Dm=L&PcWeyqhGor5Aoo)eC)?uR2Cw{ zRrFjw;3nWJkF*Cbbk-8)i=s%ZfVhZ#%&yNiyM3#}=m`k0$zJKES7)ANv-t<3)sX4^Xg0ZUjfr=J(qA2e*?Yr zOs{OYu%W~*(oEGA87TEw59y@tiBrE7p90^NsvAFp02061MZ11PV>?Vxm8Y?Zh*mQq z<$j(kIPx^Mj~PjZ&wMO1d}#r;9ATKD)#3?wJ>+O?Lk^}Dk6^c_rvEmcHG0T8v!kE` ziy?>hh-s|_^G8L-koSl{YQ$pgC}TWzM!KzI^Q|B;4K@JXLbZ@Agqw2zVH*dByMsAb z(B3{$)w+cp{F>U_9LFzc_ZYVWMSs9=gYN4ZMG=0sG+Y|za3oI5B|LC5FFsX6(V zE01b7x#((KeUI1CGI&+p0I9rOzOijT>q=612) zuY8F$+TIYhlcDLyHO#wd82cHL6T?s;voLpkrOJ5$7@;CD^(YE;DEcPJ;RE&gv+3-w zGPCJmI100AHrrU)Qp38`5tQ0>HdRWAAJc{~rYw{X^tBlls$9pG?)G0VqR(8%s7UoI z-2I^|BT>O*w$$oT)|{pA4lORy{AMrR%v4=$<57^qZGSD?d~SHC)7v{P`qVv_JrH9=k85TV6w+U~DDkit6bZ4)I|@OAnpU^Mnj-PlF!;pc?IQ^RbJrNxOKWRlfa zBAtieS{K_)woWxK4(yy0V@~icU)`>=)YANR%L#3Vdj;HdjJI1Ii-ngP#$>SA%B=xpcbL%_@5-JXhw>^d|(I zFj^!o7gwAGUSsU;RE$WR1|MWGq*uQzYJSd(z2rg}-RJ`P3KpN&-CvJ6LU>kN%or$7_p;fT67m~31@m1Y?5gR?!h}}0- zk;zcSdf~U<<+gu&LbYlhfi2x*ur2HHN5wrAKd7pfB|lhIyw55fb|HD74Idzas}oU=<~HrgYdPt@T4(i|>5` z`sIFt)^jgHlI1!h~4`pKNy`RV0K9Ti9cfPNH zM)3dc2LTZkNm?K)q79^Ys$X-3-{Qd^XZYo(9=Z}VE#Bja*O#g1&iVlbQ)d62y^6*4 zlRQhA2-w0t=5L5NHnGpu>nHz*y*H1Ks>mAtJ3vENLZcGJg|XE{76}9uC6Q{^t4gNZFI(&VO+*_6gM_e0fB%kBCfdLe%rVpItr-t`#n{4 zyE_f|%=7-<_w)PXeb7$bTUF=OsZ*y;ojSE#{&w`NNhPQVKJz(2)aWS+?qN9WD@ldo zKwjGe<0sg(Tk?eR7eM<`c@#|%Nlp1eO%j`EU4}wU_}n|B4eT1$Ymr&!G~=Q2E~;u; zy{Mu37)C?RNsAngQd}<6@wQCHmjxH6CA)6S*UXXvBdK#g=K$oYrUz*Hikt{um`{1a z<2Wp7=}0=nN+l9a_Yuf#oPUwmYl8Ad_X|jf_eb`Lwu~IWnelW%utUp>)SP}&Y|`@7mILm3Ue&)U3Bo$x0;Hh$|F)8@u=IaF%t}uR%a4MygN$~}tCNX9f=Q@+ZZ(ssqHx}GRiDY2< zZ`*T^&^syNQA&_W0ir-CdhKgAui9K@Lm88TiJ#hAclyH#2(ABG!PWz->aT&{u^tCB z{4Itwo39;+ykd-YE47RVe{@XI?i^RsN@XQCEtkTh2KBJ8!rmlxkC8P|a6d|Z^z^9i z73V2E=V}^;BzhMAKBb+1p%_F0AFgc}?w3v!r7jT3xvV4o^e4X<@fzPY@dQx=oD zak4R$?BUCZL)nN*4_9N!^DKmhXXs~PV|XIZP#Dk@u4HLLRYn{s`;)1PoE9g&x8YBG z`a7f>eHi{XH6DSrQPNzDmb)IL>{MPx0erH{^=!}MnyLF<#8CEElZZgl_J#-xhsp$VHO;3=1r5(gZ^Qjm$y=Nw z^^J>_#1{lrZ{%F5Frn*5s!U;5OyHl_9KVN!5z`_fCcaMO-?dxv+osN5UGu-#87&Wa zw5db;N5cPVllvB(drma>G30LD&T5V~FQ^VQSV=--6#dPgDQ0yO#;X4CaYv@4A(fSl zIbMiHec#Ssk$+hN2%krZv{LwwkSVQXW)bIV1vyrVHp)ROmt|noDClKu3j7ebmZs&P zlz%bg;g3nN_X8$;ze;^amUXk1{N(~fc)tqUZax1$_x%xdtSi**Z+zP~P2H@eKSDC$ zVPyy1jp#X^>_un|P%SpPg zM+;B&b;91VN#*wSz-HU(m&x8G2W0QH>~?ltC#E9Cf3X^+tW#c7?%DiquB9(h4LabL zFDjXu{IkpfMg8fFOFPi;W%=yaA_^4Ln2YifHeh!gX6>FU@-K&O^AX&@+t_WpDR>rf zdt@}pFZN;|i%Cput=5`&;FivzbQErfwBW{ukEiRsf{PEh)s^UX>hWds0VA9&L8vXH z*7wYqprhEj(62U5F4-h)k+6Lum+Jm$F%+Z1{b}reUzAKiroio z?f)IzJ4%!KAiLO&8DNbTB4wjDH>1-M5%9RKyPallh+z9HhhW(b(s&){KyZvkPzi!K zHLLcES{=X?mgPn0#m&!FnPE=Xb-To3YEJEg@?h2z-Du06@NRriggxP6&|3Gi+`v~{ z^3`#+R6z9E$89_nB>2(=|}(M z@ZZpS%izad@WWiMlq-T%$OV?JRe5P0@C<||6SsD8A?e~eo76JL5vUxehGXa4l) zIRGy6Wk-)b2f$QOodcLoD7o+#t8)Oggl^s!5cZ|n)H#6g34(VSd|=OQh`c(NKv z!WSWC_WTEN%jbIkl=8QkU8z0)`bwqnX(|)2*9j#Ga7%8oBh1_lk%zC%laj2{FT|9Q zgC5cOl5JP-cGorj0L7};e2k<)+4~y72oN07 zYhK|1LHJEfrD*v8oTRl}yI6_OV&g}we~=mB3BLrRy`ifnlQr_GBJL+VM8-h0t{@j% znDV4o%R2Fi2vXB}n)%tk3P+l{Q`>NvE;3K|59MD&=xWTiBTgbhb!K9l zKEbY13m>v9#FYdcL<4orAiUfySnj!CT~ry@GLpdxr6_hk!%jWupJ&L z?r}(hiXDN^8rHYt8=6U?|ELz`M!2Jvj!8z>uQQJKCNd#bN-34$NXgWnDcz)QOWJ~_}?JI&4F4&Uq=|VG%Pdip}o*=u?9i6u1CONm{wrjT~w>_DPJ8a4A z*u|T56{7;TLUSwm$g4QvyU#jl6ykXxyoZXzoZCKD%=tThaho}(aoANer;^4~3Z|DX z49(etr$UI7QA^CtdE3$GTf)T}Teik_aU8ZcIKiQ@od`DgOH-*Y4V|<@K_06iU;aqZ zaa2bxfXK9E?_$(<~?+@pEu{U@H zqvVL(u-wh{+#h8)cCFeB(iB~j$smol&#VKgvA+&njrzhd%>5X_BDeJz>PNY&HoF>& zXe_3oj53^!Bg+=df}o_^qq1>AaZ@z@tD>MK70e7CK!hWyxv%R{nau}|P{7^9y}M$* zdIcx@f-1oi?g^=(A_n`HtgN_l-=L;;xso@PG}VI$gAIG=ARMVv zjHSt`q2;1tIQ`t}TgK1bD&w%6M`HMJHGI+%_ZcHGAm672u~XkTH!SDHHv zF6g(1vjE~(z2<6kJI`3F!511fB##N5)FW%dnBYlA)qNA5A-F-?t13jV2a-IsvNItMhuj)5a! z-8mqE4|nOj;#acGN0*d#2Q@AXUOv<|?ZZzaES^wua7;4yB0GMe_P>O0Cr*uGVe1El z?Wqq`Eiw{H*0or*54_KjaWzfo2){+!;RM=FpazX_FS?LDpKJR)fUN*T=R4dpOnbBM z_%$Xl&8dGusPIp4=dks;2Osny7YDzHLngpN{VnE)Ty%Hm z^<{Vm`9yJO$jtz;S06vCvN0%teKS&^+&IiuefDh&QEd!=@~=6DnsKE(`#brjKz9HN zf?uv|r%FDEpl^M|DuPEVs}2I;oChk%ZMqolaU=3Mh2+DO)q}XOs9guBPdSlz?xPx` zyRA4LHLF7@PD$Z&-GN11T)gihnRpHv{HnxpCGw}d%fA-qo94;-^&aUVDc5e`ob=#{ z^rVcvrL>IN6;!DNGaPv{T*4C!YuMM(b)5t5!arBzH^R~bF4whJ6GQd-Baz`p1qOVZ z6idz(zf$lcr68?SIoGb6IFxc3<+E>srdJ=I5k5n~;2l=R1k|y&L=p9Zh- zyh|5xHKu8hg0>*HXpoi!kiRRC!5ZX6662)m_Zp=8?zYu0S0GnwklWjWEY%=A5FD~anUU>9SwHzZ6@*5*TR&YUuB1rnZ7*t7^=A|i zrsH<@;I4M`xOXS>S5Y0pZ}e_*nAD#zfm1$TXO>#ziZ!>a&^vb#Wqt4+`XzP63$h;5 zB!x1%V2DRj-zRGDHqrEb+Dj4K&LY>o$i(VLzNDnaLG>r#V&20?xL)7QoTq7{pN~(c zEZ4;cp(gHjDCR#7YYqi6e?s-@L*QR;Q$rj(gFf8e||BSjcUM)i( zPS{B5HY%^QmvbgrDNlshKS&WNPLXZUPP(h{*RDp9V>+n8vhlB)KdUr>))%pn!=nro z>*YO+^qUyi?fE?8p*=JvjE1tM!HkBZ00@7LaU}P}3^|HAh4&H#Y0bK%tED7{8hFYO zWzD1%#*f0M_4vVKf&JK!vqTna{qmifMH+Z;9GTVt0c}p1Kql1tXs*@wtp1f&@vM31 z!3Q72-@!>y*R{ilp;0_Pee~Lw%^k*ivex_iuOZIS+I8>_5`OxQ30bd(4egjPJi3A8 z`BpSO(9y#TwsmD*(AmQHk|#DD#B|Zb-1B*C3by=P8DsAvliK0l;{1~uk5~leGgePz zAvZF{I3LTCPF0M!V`sph?^@u`mttn(8oXAo7C5KEG}}X}#y7-;`)c{SRgILLJ;9dw zV+)&~S}t5%uiB(A_!Dh{xx7_D;G;CAN|R&~Yb7uE%sm8=R43@g5Xit%_ON})(-7$r zSPf=|-iCcH*L9rjQlsy6?3;F|PxRgTXCOCx)S>fhdCi^`!IX{c`GC7UUDt7=8;8UA zbg=U>RQH&&ZcB@jwt6DFt>+f1Mqlur>V82SE!rX`zp+lNs&AMsD%VGNnx6Sw@+R4u zokawm#RrlKU8A(Mp945q}}2?Nic=i0w9XQFb!T^sbM9sVXsoKn4uc}b3}5B z^F1OR;YGl!z7h_z?v$5xRfqbndBLkXwB$ps2*1{TO4Pkvn-ba1mwb~&P!X!m^T!@4 zoVxiBC!F_#Fp@fJiwI|+XH+oPg=gRtQuA9%PDV`g@P&*g4omHKR3m;gITcmlYMMq1 zlh`96(Ww%1b@MOVrFi(=$M7L0l3E(A*IUtiFEGae%Te)ITuql~++Ewojv%)60dlY2 z8Ap(-DWV!Ibw%6QFtJLe02myP2nDfS6og$$dP3q8DsdQvg|iSGz#omr4EXUX#}~TT zdlM3W86mh|kkXkPtNZKENGQRh;DtvZPb@x7C7ve5uQl)wBoxtEWqDbbe^)}{SE~FK zQvMYgCr+HGE>?ohtE7fzLMZ$0yJ~S7rHJ!>1)Aj#r7>1pWZ>gZ+@2n~|A8b7frWQb|qHssB>27saLiBB|p0r`$0rH6t$dAxV`jFr>~^ zsjj%x)7h6AzE7u)Q>ouQ7pu`50vpt+LsaVPajCrp_HvzioJxHvF7-@FEz+s`RgL}> zmpV#P2kF%QuSN5&r;5~bb_nK^ z<5Fiy>MEW3xJpfmOI;zUcj(juuLa0 z`s|>&N@*;++aV=i6?RJ;x(5W^0MKDB+=4R2E=U27J*HX7pa?HRwe`^(+l;H@kSVwX1UCMXDTz$}=*kB|da?YyhygTPglGq}ws6AJL!uCAYvnUTpq z-uk+3*~mq8uEu5tZ*SQiCh zN~uo+rSVbV1$V2~`-zPhX8NQG>7xp1l3IkG5&Xdg1JvCy$yBBikGH9UIKw<7#}5sVH^L9lWb0{|DgN|GWiY+~&UZkOv+$sobwKzW`ua_&|oo=BoTY0EP4EkX{9e&lM&#|?;-Q`mi(Ub#_df# zRa20Oog%5bQQBrd2KC&UrR?_tzK7Y(vt)k+fcePwRc<)4k(_IfA_j{kl6p0=fLK3A zBxw#cRzkCpZRz#aMZ0D6hx*xI4dwp;1DirLZ9#L9oDBabpw{pE3BC>1-`Po_Sh9)3 z!m5l7Ry}FL1Gz}Ixx?au&@C;ElEj366ux8YBGTEqbqPKZu41y@<5i+}N;HS-IwL>v zN4r^XVvZY0O@kUa-W?WF8uoQsgOeJT<#c|C;#{LyFaF${we9L4BRi+V-miwp9|5*!TCN~yOJOAh}E*{TL7KzUKq zr>@44kQUC=eP_sQ=?0>yQXX8bn0+&SM>Sz=N9^toWK{`P_ZbSSC;T953vNs$zEfcR zP?^~IUU)@!zVOv#iRyd$={Cu#%j&*HmDT6aviy`4o)3juxb-DD*8m-gL2pGnAQoW; zyaYBzbs_?l2F$xGn;$ynHVlKqm zq);-+$GoAVR?xOlfailNzCcisb* zHpRjPR?WI&>)~?$?%?&Y?{mt#x-8e+PjwSN zjZ{GLwT+AjC8dl0_V>oC7joVr5zVr@D;M8MYLmR;1L2A)fsOH> z>q`}eA+O64N~j}uBXHqozouP&mue~Qaq79Hp*1P+Bc|ewLI((@Tox|pQQhactF>M5 z`Q~xl7&YuoYP3D@UF*g;{2}LTRxlx}H+NP=>rXk`jZ?of5D|lHEw^ua662=QqSi#vyZfXmLJ&Zjz&O2gmvr=QBJ><4~iGJd(9F zU*5RFHssu+ANNI4UlBCTDX(HTMpF0l5=njWG2GOGgn^U$R*19QrvWOqT+n%ykkFiu zC_0bkQF*FV1B>)E9BA+7)_eakYQ;lIXjJ|!IZ+#nUuMgzvpqAChN12J9b0545WeMh z>~}nn9%ZCT*4ycxxe* zK{#)sm_ll;Kai)#=kwhph1j5LjaQlAN$_2+!?Na_%otxw>av9KNv^v!8fdb&EMv(K z+Fiw3Np%h&4%^8 zvc3#(F8Up759?>DJ7ZpcB6yms=5Uq&XYJV1;KD( z`;>L$_N>koG+-R6MlSRYfWY-_aQ;cOwAw1oMPcuVoBFI6@PRx{xNa5btzR8w+uZ@TklvVz&btbRN_#V(iVX>Uj zP#5t}5A{ACXvUvZZ}6+=TvM!p#Sn|K`Vsw+#FHi0;;|^IZjkS=8KO|YyZ2aY;S#Qc zW0<|7LQj&Q-zIb%VDe8y$Bi0#S~L<$ydT5qzD`%)#NV!0pPm;wQQd(dYlL~BaUIxj z>S`LQUM@<`=Mcw<=!|Y$@FYHfrjtnsUDN>wKvPe79G9$i zr9Vl>V{7U5f@g&YVI6>>_O6xVkdWPlNgp*F=usGA?uu8@;kvdRe;W?CU5!_$hg?_F zWjqx0Td(fBV;9kSZ+n)BWyQqHJlmQemai_d?w=v&yJsSfy9WOVkvBXApCO>0hTNh=HWN^Dn%IdZ3lxmk-7pi3=X^M0O%s zuEwJw2cZj)tB47yI%QGBN=*kow(&;m15y30cpyy;2`lK4%wD#un(MOw>~^PkSnyH% zB&kO;b|N5k@2L-QaiMUa(zWua!r-?B!5sxlUJ%AL?kI41cX<14ys)`LJH1w<_O=2& z2I%m=Da^Gh4hA6h$F>2I5yJ*LL4ejvy>ZLQ#G)miIUw@&N8FkrgQuwT-UJjfd$m!# zMb7Y5f}(xzG8PoUG+qq!&na9BI!6`CjJ#&J_iMPh@XKt$oNdHqRF|s3y zGuM%GD{y{a&TRso3%Kyby4rxd8kh1as%W7~5OUPe5S5Rd-U8o}bG-z=i;lz3D}AkL z84NOOr%XF^RcsoMkJ0FAnv7(`!Tfr>tYU{bei2cdDHRWNx+3s>o&FJRrehT+TXgJ; zB0=W7byWMaf3*`;32qKKmk(0@h;(n$*M2u`J(THAi}PAyVY|axNE1nwd)l>eYt^aj zU&hCUnIa*nb>v?odK^Ea+`r1&eegrp+t;{-Wx=-!`hBH#M7-5Ha7(AodBK?-$6;qEQmycdsTlg zU@L8N%8!&CNqzf%439~|I4QFAQyITyI^gzVW&~dhwF_=o!jZ#>d&&M0BSyLPc_SsN zuIn0sP~z%p5a*5(S^t^ybCsz2`zbLE6 z#*pAtGVuXgrq4h)21l{MWhin_Q6FDfOdf}k=O!MFJo_KkvfN_J$#=)ug|8x);CWcf z@%Gjw%YGc*f%8*+sAYIAf0ikEb~XBVRx-`v36Hj1|I?uIdqLxBEG5avby%E=*hhAu zSDKuG8{?#MCXxE{KGE}jaWYvTsb95~$RQH%Cb;bKDEm2TkJXwbVpeHozYqd)^{?CoWcRX zU4i$&tLHx z<|&W`v0|h8lkX?=@CJ)}SnZFcHq9x8D(7f&wsO^}eAATAd88goZ0mc`{v=jG<25j% z&dppW&^_e*HA7SgU(zNrrY7K5$oa8JLN_}?&Yir`aRTq+gILcq6#9?yhA!!0U6U&8 z+(nn*qe#su&r4#9^L7IH*W$d*JVjEI?}3^-G`~X5Ylw#d$EspmoHe`(i0*^Tms1uJ z6G^QXpk2$Xhs5i53Bs-6t-r{-%>K2&dCNS*_=L&e^-HpfF;o5RzJGr3`idnBdv$Gx zy8=(clB}Xj{hgUcY53Mxge!6Oy@uy1f3ES*OOpHiJ5t4de4D}B+$~txT)4GwUMRO) zK^C{5ZJ3|j-ivwtLS0wv=)Q$nTLYgAUjKc(Kf}l)lWA+)F;c62$@5S0hEmVQv&B@p zVo5gSoFMj-=n)Yw|4N z56Ay{bW|C1`Msp2r+gvh&$|U2E_UaLBFJth8a?^g=zQH=#lu0Wk(${+e^uZ5La4U5@udO`2 zV@-+@c+s%Jq<2C~mQgYk@8UBWi1zrS>~8l$wA+n;0g0ldJnlH6pYdf!X{*T7 zM*7~4z$bAnV9Qfs(%XS!T0ch^bp7PBCe){A$jdY-&9`7bH)ADmwC(H z^aTIyN&2Cn`J~rO|KjSq;FnjQQy6MLc$;W4PjE+G^GVsBeqUyB`eTR3HRg3T>=u^o z$l5vvsG`s@MZxxkLH=$Jye@a($aE(^>$AX0Z4`Q@J?{zr(t54UFRi~a84PdQCcVw} zZ}9y9@pLFB2hM9!@M1_98fq==LC)sX4O=AePM70-O)j1p?t5C7t3-+2gRjGC?2hp; zNyQaUU&EeJ=F#LuFX47Z9oolhj2!_TD+hxrlySEN!Ryn6gWljRX}1%u&EZc`a7!Wa z_w$$+x+iS~Ar2YF_b_)J@iZ*xtOwQ_OUY{Z#~a0mVZ{#QE?x3?`+X~po6Mrn`9*Tu z_#To9nlE#EosaBmI(rDO1qt;dW1iIeJqp)k>17`kFN1~DN1*;Khu4u^%Umr|78 z{XjmZzLjTh7H7m|4n>OwHhLOD9amA3uL$ev3n^U%I7Jsb8QSJfg$`_)!`d2 zA0wwO1xZ`@$Xzm{&LS^ISu-8}x=_k5gW$)uKxRS1)jb@p#u-$p#kq?}`4>mFK4_%q z3s0fsxFkOP(wwqslU<`r(Uz?%YdF=btett6dmGj%k#P9AT&ht$ z1~b`XkBNoh%q$oO(ZpWC9!%22?MrKi z%-jE=GU2?(E^;+8hZSQ9pXyW1vgc|(6)6nC3X!WO76Lis)H)FKJN(!Lu_kkYb_5j^ zv{!)EFiR#OEzU;(kbgEnL&n|2@cn>nHsw+L>TD9jeRzWVy~4jU4?*WbvZ>Q@GVy6* z`)34q9GS{cSN4_-M;yfEP z^3UJ1#W_{*^N)2O^OP5QII1i}X?PkwYv*bBG%0)yFW8^X?i+=|uhFx(=>`DhY8nY@ z5s^l|9Zw~ObSKu+a1g>Drl`D7&VFv=MiU2FmWx; z%RnOkvRZ>5xSEIY!soaPLua>m7N4I{7#y;QT&||G!Opc5S0^b1DoJWB|JVre0AvK&-}MnSQO!`2z7f7YMjf)L6T zusNULP4)(JI#HzZbs@Mvvt2_3w-8|g`G*ZZXCpJ85z8T0&^G)GO=!oc++Y-}(%vGz z79&-N)o7D62Y4P_`M98kn>h>GmK|#4m$rJ#oYLSM5kWEGwqtI zNOYF-hT2slrKlBqr0n(_X2c{StacpNum!2bIh6boEo!!LGzj(3bQ0|#Wd}MnI8P!= zQYc0Cr!XF$Xu}HT?uhK(XK3Dct%q=w1bcto*T(QJ)YE(9zHUJqSKDjk^}Mq`bTuk( zFd9KD{vi(ns&-7MuGD%%u=n*6Q^7cauJc|8l+X!L{^23#Qqth}5Ta?H5zru3kaI54 zxYdI>Qw4S+H0aLE$8FLJh$;yF814(kWs4WI%MLk*6Xk!-Fm(tot{ZQl5ZL+MI)b1x zmAH`eWd34)98&dFy6Unk-sVcM_m_P%H=7=ZhkDR@Me1<7H`IY|8aOwS{u{DqFSc9n z%3kBe)WBPYi>N0)xzthDGHj*L8$&~C!IIZJf_bTPB&2f4X&y14FC$PIJC{OLx6Wf* zR1q7W^ZI?>Z%8r8;dGMVOFOs$Uj|FmG5E^ctOquHHI!)w)KGU2N6Gr0Zh>VrRC!rr z_8RjyhFlg11wxuiEreT}?c8nBoze7r?R3_qmV9MNynIAm7XFxp%5H&3s^?~L%|!fF ztaN3{Rmf_4M)26+$PQw9dnB7XlG=rA-ZjzBy|$Ni;@Ib4nf04bzXp%7KmBTd^%e13 zvPsHj4c4}|^nI!=BRdf7X#LZ&=zbO{%oId+{ay%;aJT5yxKT%yE-#g0R)FD{-vPeeTHX`)?uZ!6dJUse415aJJt%W{g$k@v|i87f;))_SHMM?pWxq@*9&;H zP6lobenN-UL|%31$-0?1>rEk}IrUq?q-JcE^$~F#oOxVSQ2bP)gP57<}UohcX6Fz9dKb!CmCR}8~*(SWygcq7H+l2j1c!CMr znQ-roy8Mq#xWj}SP58J8?=s;ZOt{E|vrTxZ35T2TOcS1G-J`>0Lb)hvdIGv}X+I?p^C z2>avWirAENreB3>6H*$GYO&8+BPNY4-_}D+Ej;TO4;-xxbdIl9fulKPGt(RH-?V-u zHRyb(7bD6HMwABUF&&wmg(vdtSx4y(bvYhzPXf0VikTWUlbdv=MtthaJk5fH8K~@Vp+S#6*432DYkl;1`1M4qx*h#(?qvvt{WAQLhBNnud?ZlKciyN_0 zc;FJHPQ&`U8f(EJ{(?R|q@lMpyuc3d{k9Xrc1l>EQ!TMIZ%+MWP<@McD0L~%*q`z@)z9Ce z<^@Tnei}j;@H8$0>L=?4h7ea{L|2HLs~9L7w&FFCb=bxG`}WJOub|> z!*>*QedI;e!%6;-^JgTts zyBjz@I~DG#(mKhsz#BeD*My##QiQ-eZ)GD^*pk@hlwu&cCBfPt6V>LFvAkMO@r;Ln z-msw?0xvGA_8@G?`MD?b2Rh{ibN2E?7AN zN$p%W9xr+587j}C^P#cf7jA*N4D1lrolJ_Ym&$v?f?Rw+R#(BABJ+OhbRjL|{31!% z?9F5Y_)u&1lTr{DK_Yady(no73q(GCp>0@H?7>$NbB_ka*Mg#z`7+t=A=}^`By3bj#r6!q(FI`JF z5&@2BC@Je|4SoUOxD}3r)}hu8&VNJa((`pyPZK)1=acN1*#E#OOwL|bp@wuCNIV_6 zy%hNKPiydxG&|NxT~1b+Q{JY(%G$?@n{}4uWRV*M>B!pD)NfTU5qqV%uzChcJ}Zi{n_a+x8!Y0}Bq(2Z}# zx0CJdkbsj|Yd6x0Ol2gt!O=n7oVi|CYs#CDD zjRl6c!SWc8;c|^-tzc;f79o5E85`I8*Zt4f2T$Y}b53t{ruk#MyIvYU|axo_|nqtNbDYUBdJ_*0edPyk;kW82WkXg928>ap5V#) z(RIz)s4hBD2bKruTe>H<*H2t^e7>ZLU6I;JNt$I*8E1mHLrLP7J{MWpNzYyivoU-P0s9d$6hilcW zqpd0cVNiym-1La`tAw}29w)I&&!et(yQBE6*SJ($I*e2EU@PdX4234;^IvuAJiF{5 zmda149t1%0-m7qE(RZzUQcHec+7Noa1A#|Y2{&4wa{@T7^%enb%R1jIxmLc)Fsutc zhUS#3`cUelWQWXJO0@~JzNcs@@f5m&wuP3ERr4z|%CCO`*@n@ZG^+G?RFmODc!N^S zS~0FgKv=iDm+0-7C$KskLGwjY&&P)so{R!k><-@rqxI8nk|ofjpQsO`U*mah_&!hMdRq6h2Sd6Lu{nlli`% z*mKr;`es8;l4N!*osFP1#)R{}D))h>%Tb%ckL=^V|{f(#adQtezDc__4&<}tu#!SUr6}2V*h!RC7q3A5> zE`8F;eqfJkw5NX-qAhe=wCT3uotLKT1IaY&9pv~iw;fmLok}jihYI-98vIHUqkxaH zLxuRCfR77 ztb1z}rtX3n(i-0o()9RugFH5;vG|Yuc;2kB6x>t z-8W8!t!Il-!1p+i*x+7I@JH*7Z)uE`h@f;<^?g3+x#1I~)k4ns;7#CR6E9#Q=HM!jo3+T6B+>ki7+*(ICy!PPbk&#qNZrhQ3dMHVVTcCc3{4{aBo zQ1Sl&S;cvCdthQvnrl^~5m#KET`JD=9PMh_E>uuEFHIN%k0|~I!M9{xnnid*l7GHf z)zUFUJ-=G2m=bJ7ltqU)tj{>xFAcw*7tiXI#H~%bj`$onpsb^%r$x&MOlaH{xLEvI zQ=zUs)Nx0tN&Bgs zAbcG5p#B8mss)mF;iGDEtX*-k+(?#+EWDL`3nNmYrhvbKPIK)Op2C~?Ln~&TN*(Ut zJ_Fk5Qh-!%xEMpsv?AuBSc$Y`qnwOXf_M@vh#&qtf+PHp7E@48LB6&2#6B{kO${Zq z(Vo{55nhSL73HE@Rw82lG&IFlUl+3w{JQ$MdbD1jQB^J4CO{ zPoVyFH`Kppr=FaU`m!|kvvz8)gwzEByWCD)kdV3r^CNtXoytoauH6h9!{wy9R!%-n zSEVA#^0%$2uq%8N$=2Q~#msR;s0vWuHi-5jpy3mBF_=qF(bm##7|_pK$7&$v8)i?@ zuV2!`M}om>Z{uS|+y>uN5QJaELT5ipC(;;$L(bQD3ZI1*S0waE06AakayuX@HBmlF z-J~wEQL4%jf>fiRKJrEH4XUE54{^#lcMGl~RfAe4Rhi&D?&OFOJq#PlAqDfCZ zLi#+D-unpYRVMw^Bc%IG`iF05`jX7M9psybeg-}ImiA z=_8H+Uuod?90A@=FFFEzsezyTU!+exLi#uZ|L-G|?>FgXM}VJT(%Zjzc>Z5%(q|t5 zKF_4rn{@LU4aSW_xv=xuSQFC|-|c+=FNYnd{QBJC|1Yzk zP2G>;t>u6C5#@^$+|q{`~@n)&ta3DxDkippxA zJ?_Nk`M>#mB)XzyuG9M4eoxeYiSUV)Y-a&KE^;1mE5mlx2^}fV$ zc0zsWOkcLUydsbh@K;v3r_|K?D{HFjr@03X9N5L}&Y0!S$e87;s_oplb8%f|wcqWZ zRax(r8221sy+BK@iR7B+tE&ezE~C$F;@s7NIWv59l5?KUIisfD7tKj7d3TrlW&~!s z>;0vE-yC1Hzh3fJk-v%xkhze+T^6XTBduzoyVUP5Et};lcjt|q;4UkzEuB#%DCSj` z`Rb!)Fc^GbDECQTaOA0n{}c<*`B7+)RFy7t*Zaz9s>|y;kFT8LbNg%D^GhrJ?is#{ znmV7m&R0|GtFEk`=`J;txJxVGJugze)TdnG6C&Ni=J`-2b?0XftF5ak50v@OpEAJ2 zmCzuuc=a}|3*>hmSL-XQtXSxts6Yo5Ye08FUf=qD?wSh43(W&5td_!ROZ~Il!)65P zGiqz<`~#(3-2>(E{3tS&g{lZ6W58tqmsQMk52L;nl`~7K>&}mr@1Ny!k5KV}x>Avt zLkq729)YQF50k%#f=g)y)o`bx6lTOEWE^nyzPifND)%rQmel(Zy_v$EHW7#6%Qy`< zP5~TBQz^JhtNiX^{7I;dr^;XN^ZTXo;G@*94S|aLGZwn5OKJ9+I=4J(p;jFhX8XbI zuPd#tukh7n)K@N|f#q+E&4N?INC`6*`hE58T7+Z5xZ&>c22fgU0*C^&RW+sM?qL;` zRbc2m*2halW!;?lrHENYUCkU@zTj<*$tJLuMqv#Js+hJk_!b~UemagRMA2GVttk>D zc_3kwt8PQWq`FE!MYo|rljl}6!~|z7;B`KjiM$rn*9Uy6hGQkhU0*q~y0ofFak-ji zpYQ7<6{@VRtfwnW;q_8@MWEi7QCeOOntB>bKTwPD?!1b?IG=k?O}TG?yWVsLe`(!J zaNGImimJ8hO6P-Fl!9Fs+D+GapnG%;0JXJMm1RnA*f1Ksg6caEGWtb41!`ahF%ltn}BDUn*J?sHP#M{SKdh*2H;L zzWnU+?Aq+I?8@xY>~Y!t>gO@_@ z7?fI3&E++8*Rp|K;!zCF1jXQU+~aHNXcG6tnyPYNwSpPv_f?cek#-p`qXuejW?ktV zH;*Ihd_MQMnhL)XXene?X}#MseB7AA3FGq%FL93^WpiMyRL+qCg(H#)Km`{aG2+TBlgy%p%vh3M zZc`&FNA!IxZIQ38#(@>!s{_3hUsh2V9D=B- zuRA_nU~YikDs|UI>3HhVmhSnLG^K%&&INvDEeW7f#A=*_w=qmgW2@+RlSMR0{@Af& z#tv|o(FaC|5O<*3@jd;FJp-g*6y;b|z&j zjm;mIKVIe+^6&pAxp&0NyAnYq4@%||CG$U!NQYybF)gq%e09|rxNbYP;SZ~sAN{| zDW6T;AqddJf+IcJ(c`t28uiob8KmnN*wNN7AYVFkwtJ+Q5%KCQrWxj_5yMDu->ANm zF(vxa&v0D#NXLZg`arFWWzZ)~fkgq`{B1j@8murb7?Ea_mR&Bdbw&*en1E<4a7f=Z z29Lur`qfBe5I@ID|GnR-z^r>k!~BErHuG%bS(xx{$4fZKq;)6E=RG^2?3B27XWX;E z-V{e`6VH|AeIRM!9s2jT*CLSz&2Mttv&6~!(fnkB>M#N(q0BEGGLLkaHqZ^`kg1PD zPjJjc#u4jnj2v`CB?mk@^w4SSD~D}VIu!Gz_ry$A)0hNeEJ=4PFZGvdV?rd~NDJ** zJi;+SnfhAN+~onKVzmwD=rR%;z*jChyUbTP4{<3)2>i^9uv^kAjm0jdO{k7q_4d$i zPcbwuVB@9@hoP%@gveKnI!B%@M5+(iltrtp>v-6-_yN#ep{k&i6Cg_Q_f5yHjvo`F z5q9@B+z<^V+%p8Md?vimwRZEISAL`L9hLL(!`)u+Y1=aJg z(aLF|`m(ypT0gy5NsZA48q3OC19hchHdD(rugIBs{7C9b?31V9BfUI>QDGoI zGCPcICzwX636kjNDN)#IGE(Ho>j1%veCMPG7^W&_s*tv*P!H0Vb52dKKNZ8Q%CDki zwr-+y?^Q2RDU<$LR~M-Dn`xys^i5rq;G~zEiMnbe`zYONu?C@*PElAq-PFYfO{?4?y441w|72u60xq8{AP?6ID0Ox;Rl#>ChE#Ki6V}+gga^v z*^sq0s*{OQ(nwU^(KXc>vB6V~_w+QeL&VIrxnuViqfHaDiHt<&^}5Dw^w?qZ#~Jm2 z{HJ|cztaIKy`aepc*wtf*QuRBG2f8k@@&wRCOFt&8`P2 zA-T4+j_#oQxEp6FH8J=SdRrgA9BUm zhH!>rUB&>n>MU*?#Hir;K0NYn8@C>fE9XeRsi~+CgJ1PD;0^!eHADU|bBr3lFH}rC((5Y%OifKQ z>OB4$oG5d|TOg)#X`J$OrP#j3_FoJDY7CMdFCAY_XeN4vE{ z8RDY;80_jLS)dfF5PFd@sZBIa(LP?e0AmFkmtb7Ux(1rzitOl2%-DF~8Q^yGr8u9S z>N90`XlqOHUzpU-R#?&Tu|Tz8)K8#i17?vzh9NVBGi3~n`LeL&V~#`9h20sYI8fAN z$|j0Nvzr9}5AvsKa7vU7hE`4dq0Q@vlCCLNZQQo~Yz&f!fzC!D^QHf2yqmFih&Q%oEBhz>E(=r z%+f^p0HXYuv_ibl4^ZMe$5)C;Dv~9BXS>Y|n;c`Lrn)yM={8dn_uzqpOGN?2gkMAS zwGqvztS-f$XX6_nyi&g7L@&9P8%`Igf2iwvUx^Ln(9@F=tsG4j6|jxe=cse!rcb$S z(6sbw?4bazU+IpjRmFZnN7TcL3SweLh^|W13|7k`*=`xrw44>2Ug}?1>vLD)6!t4K z$1T1CGjJ$g8MTi1+D$$ZSCvu~iar_dwJMo|cCW-=&w@#x^s+t!v<;4%LuS#a*Tj-g z9jJ5LQ27l!Q74{SDv47eLb^0Vlt$ckMaq7SM#Tn^^s~y{3*6~vm&?RvNV&UjdcFLI z!bmUgpI)9`28RbI77xOlSuhA*_Z)jLa_4{XTV&EN{V($US9lWBcV2uja-?6pd?Y^G zj!we7{PCUd9@)V5E zP|iS!o=~iC+bEPz65{quI2dtEJQ(T0&&@BBUoO95e$)BY@>|Sr8NY(j6Fr3md8$g< z4zlN$;CCy}88WUMtZfY_oz%tvjE%#HHX>PB&M>UaJVrDHAd=)$(>8{(a%D?NPe)=Y z*0zh3J|5X zlLOra80ESmT4yTa?Uj$d)#x=%aA=w-qMbZ9?}R9q%#WWhPu;!rM)_-h|2D>HM=y zxY~r43486;>0T2qHKCC|sIHM_u!R-j(l)p;j~prK^_{1rvrQ)btg5Q=^mKRn;4^v9 z#*?E9Gc&Q921Z@Yv2j)RwshOhLadcRz|>XsZDpIyl66k$;$r012P!Hm7exIAv8Xt^ zIxcd=*by;dR_3T9L;M`}xE`%qRB~rf0EXUJag<^G>WvA?-%;Z6Tp#Ni}iquxtA*>+XQeB?0rg%k0d`R{OrV#YB=%kC`ZCG1fB^6=$|w$*IX?Cx@; z`o?vE-xLJO9zG(^=zU$wvnO|vQC;?}u`(8m(>v4JLK(boK83XFuQihy=CFMZ!Q1ZnM-$dzi0J(3x5}WWB1Z` zcKqp#!j+w$x$?2AJ7ui?;*Y(bTUOp!2K7{oq5-5pSB-1YG;Rwer-zGarskS?mck-Q$wn5e|-3x+n(N)yMNuopH#hlW?<@v z`LCwD`Q9ZtuRZi|<~yfnJ3hF0@x^a#J+^fFb5H&7fawk0jx^|9-&tQmAv;jGCI^)B6zlTop9ndiNE9p~;!TIb$zd;cD9d>d?f zZ0^ZVt?YR3r_cTUtevZ^yS8;&aQ1$O>xTO~-`4B)?jJp!GW+)#IdhW#R8{`Rq^V_} z|8Vi;m(M7zI_d39U(;yEjJ;pq+Og`2dy`Jw@I&%7lQy~jz2%)1zT)tzqrY7JZ0O3R zYkv8#_xm#nGTu%7{>s;{_Z9B^d2;FFMXy}^RJPx-?(UB>pWf-Y_rnX{y7ldxIh$U) z=jR{Ze0_Gfa>Ot1RG&R^>CAs^Up@WZ`iu^FpY?8kR!L!(2e)0B^8T>7&f*6>?fUfS z(e>GD-QBjOKQ(L86HPVl&O0mC{Qc9?SGw>2;IiAdz0>d1+qbWH^8UA4j>~!Ck|ilm z4m@w_GpqhpwRXL`VfEK5pLp)i-9BE~{?9ue^Jk5EAN~K9Q$7V(Ot_v zX*{p|mh)%NNxA>h*^9cq+WphNMmpcz=MhJj$Ntvos=S+Bdv@HNeBG?QNxwU|v18@5 zNi%+Wai(wa+;ggq|DxmN)$>l=d2sg`uLmz(^lp!rE_{Dx&4+9D@BjAM8%8|4>bN&< zSTWtY`^`76zWKF(Y})wt(6M_z9P{1Gr(c^nY282H@A%XO7oGFC_uVs6-Yz_`%cDPD z*#4a9i#m9o|91L^6F!`I|F<_(4_^3e<;d%wD1GsShKhB|chsbx^YN^)x6beOQu|R| zpI&opyHf|9?ws)Kd22WK?fT5)H(mPV869RnG4;O4TN?+zy8Wrp-`*L}`;iZ(tk_uo zm(%x_eRb#Evjbgjp40Auj-Btk;GFKQO*1>y9W%+{yyn8^Ztb~f^~aB#@z@nZPh8pU zFE{MCDdpKWK3nzedsm+F;jXSbcf5Y>@Q-(Xx9^GfXH_@6d-BW2KD%Vf>1%%cX#R?t z`J-0#`ux)5rM0tNkr&SESTVJ0(ovDW`EIOyWX8VNBbS%vzgl(df{(i_|7J(ZTjLu# zjNbS}`>fK_XWsYIvD3E~jjAlzHNX1&3unLf$a|N*`A$XG4|DgN_x8Et9$ELm=D$7t z!S7#vd{j8{ROU&0pLymF8`r*&dGizF{(1M4Y0h)Duf4hBTQB#U^uhS&X1;UUz(o~L ztiG^xQ@ayqO}picn*QfL+x5wR+|cd$6F+ob+Wc+1jLPbY8pnLSh~-eTD~H-O>@W(? zQCPsFb9hN!{_qK-&?QsEWsVg(r*@iqihq_E83lRMn6;EuR#o~JvcNXa$FAq-e5DNY zXqtPN+1h-5R3ByhAO2?}o|1lM`M~tdbIKu4e7)0Ro5Sjf!N6qI+UypyBm7eiMp~yb z*X7rK+QG= zJTq@$qn%9X%c|HmfM;@+Z2yR^uQ9=4s;{j=V=sxH+*f|c1PPYtj8s~7*ntb!ic*~B zvL4`;F`RD(rPu0}4FQUg zFKg%&SXL@-4b#qs#{g(HD~uKNKdFhm-$iUQ7D1VZsj~(SC9ishq8pF0vB%5&b*zq= zZLk+0eHuzPzIcvhTOO_4RtAaC(rE8tCnDz3On4DzzU`DJ2?vW>p>(G&a3H?E(m9Ax z!0oG5(qw`ub+n9;@V@DQ_nbbD6 zxPT8wwE->|Jsv716pznOC$K4!c(f2@sqJX@8=jm#g* zsye$R4~Z3m^Gf1Kj^-cX89gGuurP)^nlf&@r?Bu4Ooy;8nm<~9n%q=)+yupZ_aL{4 zh-Mx!rl`0uU+UDq|Af&OjUF>;bpQSihr8}zWcmO6{;%+$2Yhw#+rz~~yZLSBx1Qe$ ze#`kS%he8-M=N5vl{8E zDk-mHAg)sxqAEeoCmlJx4Pc4ZqVez*Z0DC#I-&*-TfX?y4wu1{ul$uITHPEDUhguV zCA;u``=7ywqArPQ@)E#GjOtE=j+U?7Covd1pGj9c%nwa<7~@Q^%YL1heU$(&YX^r- zFRv+4qhCV)Xq+iuDPYONxq(U`*oj>tgZLrrQ0dxMI&21mFHntV={NW-^v)?=P*Pc6 zQ=)g=m8j)myS{dMn>3-%;FokU5lf7TC`syHT)J-U61Ba~PS*9SFO{B)IMToxXe77QM zphpF^p4CGVqzD@jtD&wm-gcI)fjXO_L(_d|t~k2uFR!ev)y6}#TCxT$))mnQ-XuLnL3Z1<6t;B9ZV=Az%9I?h zvp{OR?Arcc?7azKoK?9ue%_gPCNpi?rgWh+1*V}bDKzagP1~fjki7|HnP%w%#mP2V zAj^c3>fC|XfT=W8>7b6!H5j85_i(Iwe?|IHS@B7Z1 zNsE5>e&7H8Kc+o-mh+tF?ECUM+&R6_;UX+2uft;%IpXv^Lxm*AxSM7EtSFJ(BjKZ1`%#T*@Vih7q6Bb?P?jnM&g#N2@=Sx+Jy z@spz<<;oQ-%bi0WMGWgFQwb^;dJY>}Dqk#e)w`ZPOayTzvz6w|trzmlwzqE+s;T

h6}@b&4Nclp?DXzfoPsf2i6ATXe47;m%uWF)P^8wOM4Xqie$Ek z&c1t)dD0Xr|1-Bj=>x!}e2t@hF8=#V(oZ)bRfT|>1VHDziUK*2ZtTSQ%ofhtJ z)m@8nXG+Uw@QfN^+zagH!pgB}56QLzXH0a(a`as; zV6ucGaE^6VRVv6QXKCVXcl*$#YM)i1ck*@mINCR=W_HC_0^GjKl)!|51hh*D*&eB< zEgkwOyQ3<*g|2t9?GT!lsqIjy+$(Wut(EA?ilSuwlsrA+5k+cEnlmYTRuq+5`%}z+ z9rj4lXy1j}1LYotDoPEu)UO*yE#!cl9y+pWJrjMqy)^8QO@*d*FE4OMAaeMr8-3f~ zqiiubH;`P-3qVFI6% zZ~zmntgfc4 zYE3R3=EIgoWgmFkXuE_K|1}RMq-cksa#gL)I^OxvIvcHb6J*A+ARo$;yDzv%gly#I zD!GYP3ixC>4FoWAs@oQ&OHOnn7wERS%7!v*S>d>*zJ!Ydd+i}yRzbgjkqnw;IbtCB zRogIGp`*vmy||Z?=tdVI7w<#rJTi`XU|_=mp|M5+2c}gIw~~Tl?}N4B@HHRpQ`Q`P zof@GWBn~(Gc$@<#zHz~`m+p^QLBxq;KH{hvJUwl(no}(B#d`R#O{BJ}sJ*z=V#IaUvsAkr7BMx$1;SV1JfR+Ax;` zY}ZuX^s0WrI-kunZ|uqNF-_SZNjXoDDIcXs%Tf{T>QnX_Aejc^s==IWE8n&!S^ch= zcK3dvKA4I_<8(yI9`@y^fu!!2?dLu?%9MTFjq_tij;$ox*s*h&($QggW?1mbBU0FQ z%mjQCi|THI!|2TJ{EfNUq+iiyl+!<1^@%LfpDIslX93a1XAb4%lYM-LYr3_ZICj;-Zr>8}o` z+G`{4N8M4%E7~1f7j3bCL9^EPrS>R#U0W^3P&ak@qoDD2Ow3w^I#wMxdimfjnNvxI zepCBPP029=ecsYRoa^DAo~_AonH-M}hO*1~ie$As^q`I}D9h#65!fU*Qk|%e4V2No zkX~Y-riDiGxS@hQ6*)WAcg@Mk=GcJtMK!Iq3pwYN(o^eIhxu7d`lRN{I4v#T&LDrv zy9X2eY#PR66?jMmw`{OLExmMxhg)ZKcUJqn6#bQ4MzEV_^ng?K!y6D!xz%Ect34>e z=eTJIYT3}xzla{piD2o-8JIeHtIo}&Xb9V_ese~5(DJ-B(y2tgP+6q!euBlTIgZHU zR8=3I$m2c7NnJbpWA}4T*`%Oj0Y0Ix`w6~`L%o$;h2TXfT(Ct+NYI5eyq&;m<-D2X zc;Ic#3uOwUK&cs#zH;1VuP0eK!go4sej?V>9LKH=jt)6yjOB8L3%x7#Yjl5<9zT=U zXs~p{ofEPdl||lwK^buPr8QZLS(co3Y5PwRku_myn_ZHq8OJOS3rKirPtBw0pc-Ca zM0Y%C(S(P$dc_2ln+|4SB}osO_--MOyX^5iFXZ56C_Vq<942sYPPxD-Zp+hJ77~LR zB@7kyYX1f+>@t6_Zl-;u2@<~+h$?IsI}U{q+5NHQ7=z+s^`y#zG@m3cq$;f%1p>7S zgV#xd$r6-S(j{c+451}2LyPyOUiH(* zW)_Q$HH}qOXQGZ^X}J}14|zR3oA0ddO7PuPUEx?}fCtW4h@&g=v>%4Nqr;AJ*RbP)xiz)M`}g+V&k zrtkak(3WJ?G9YRn&1&fZsZe%`l!Xr}bJXOKv)ZLkFDYV^*GgT~;N?~YwB#tF1JOo~UR5DTD=CNeR3~4n#MKCXYk_B7*q>7OB;E7J4Iw_+NGn#j9>};-Tv>{o z)pP8ndg(BP1k^bUot(OMVBkit)KRyOgT*xGqo3`HCh1%jlR9mrDD~T-v#X6?ke-}1 zVlt~J1#g?hgZ$>ft~NJqJ5mC+i=-T~+$C{s*GX)pgI*U+;!7oy*h4*K_@~!ZX>*4%B2jTV+IEnsI4M;@XOm*tU*(e&)D_A0T!qnrvljn{3A_t#VCq zvj}!(QOa)&X5ecj)x=`1hzXePDA!Je91e3mn3LK zH-=+nYT!to;3tOz&d^dfiyo0~jbh-b);_DcTF#+He5<@mYDJHv&=t`r6q{u7Ki(FS z!l;9->VjV?9=5mbaT5AEM<6)*IA&o@GBl$^uGcrHk*Q{L=Fz;vVxS?@ID%c2Nc6RK z(Z+VAe(Y98-yt)_^urtxcc@nmkL zHU7|YD5(8=OZnVGB`)sJvp=-Op?qaqDeWXqlSB7a34$DL#TDVg^u|3bRWSk;27@;vAh70m_5p@aGX6RV0 zvV3z+L6T5`LL zNq##XamQCR&_?5G*&uER(PeP?V)HhPD$D!&>rv>tW3??8V2Ga-zTrRr?MMrZN12It z|8|7Bj2iq|BP#hXrAvH@aWZ_B6H+`QiB1Ch!CaLvK*k=hb^4N04B0$@SIMnWvWlNI z3u;%zi24b2ZgS9?zD#y!*F7$Lsa+-2BRS=9xyx=F?CIG{vxHQ>9yQ+TjB`(-t#@Tl zS8IP?0?+5K#B_F5tT$&cu?qc8Kc0$O)st9XkXsO5y|OtG-$R`?f24qSBa_0XpSW;^ z&>6Coj`E>;W0!Qc+_0ZALiT(^AL_Q}p*ZovyJ7tK5%QKM+LZbD+3u*tQB{E7zQ*IM zmIKO6Jo6M{BI)0&V-QOHcz!p#7qP5~Z_R)Ozvt ziw(}`s)2|cP^BIQb)hulT@^gnwM%q~R=`TpD+c)au6EJPoXw&U+)|-uiBp%S4YKmm zn$G4%nl7rJo$jNuYJ0Q;Gq?>r&WZK*;Rv337)4w{b4$EZm}mXT-A-*QSQ2r= z%jl>Rj!8y>nlEQ(dJY2NZC(n4ziF!ERW4G2p zX?RIV5y$!g6esIaHS4U&+OSS%9pU7MMpPP6r9;cf&#Iiabo=?(m*pi#>%EdG^=j){BTuc^<-UQn+GsD}YrP-o=0(SAJ6MXbyD_%A+tH zG-bd^9(m719|%!dfCWTduBYlxHXxXKz9Cn1b^bZEA`~1dJGQ*4hCm?iT}7q?U3o7p zuBkkx6)w7vq6WWQE*w!}*La_g2g&ScZS_KQ$k{X5b<1)7eM*=7=8xO?)cwtrdeq9E?g?Dw<(T1j_C!_$ z-hcSr&SeB-X`3?0I;l*4XsDErP^+P(e!4JsLql76a1LXSda z0(#iV)aiy*Yi{)|->55+rG&htfXH-WJ(kpYOYszhKKV@30$Srvh-7>0=&6L$@uFP~ zya9l&!II>bM#paIa8mlnCP%(1z*+?DKhm}WeCGj}tyQlvi%n7oowZ zZ>YnUX&em7Lt8;z8Qt-AFd`K@>MKi%s?fJv2eh2H3ch@4K+nLZPUlYC@=-0EDnqo} zgoHwxVN5FlCf9oZF=?(%BP-Fv#!)eVi)&;2)R6_w5}?qh^gBf8@xQ=Hfdh3yvHK!$e>T!Fy%Vkt2W1 zJaVLFA-)-Mf~1M}f6{yn{$B_)3;x$Mh_lWTt5?$&Cyns>1-`4cR;&&a%#GINiu{$U z85j8g;e2APXH0Cx$g`QyHDY^&AU@(?x2Nj3s=E;ZqsB5-ekdNzNAAYEJ>y;!FoJ@N5g6*sz^&%(Uy3ryrorHS|n<#%96up z+gZ+S7Bp1VSC*FJ+kR?Crk>8CVy#d{G1(Fdk{R3R=+0ogv4{XDv|UPl+HxD}p&dCLG-X?gFQayK%gfpCLrx1G zOP>`JEOyi5LfY5%zADrf9h{VwR$NlrT8e9N&I?-cdEIkjd$qzOrllx}OQ|tAJ>*w< z`}aoV+lzarisvLbCFo9%NpjL#S2%GWu~Kg&sE8D`?Lv`N<=zUXios-gS2(AX+a{o& z7yNnnTefF1qiB){%aqU?Oq9fpIB~7Q1znoWt~9aDah|Qni6;@;LFr*z9(j<^kvpd1t>F zFTi38f}~YLo3v@q+i>(f0ZcXV262o|&P?tB_%xW-V9$D0|B$56p0sme#UEQfL1R)r zQK-)O>A>ODd}h-%F^om95JKlB@Rk^kUE$J=)I|Lb#wr+API>+S&qUD^*3^OTbu1r9 z_ZU&6PEtfY`4E?V#Ksy&THOVZH+M@;_kq!_8$dEih-p{B$wKGWa>d=U!)4$Ka~47MKt% zg1+cP6EL|g8K$*542;mh$g^XLjnP|A3+?e?`x4JzqnKUd@S_iHotmw{N|&MJa8LnN z-#1Mfw{wc=VmsA-R+#pO)bqM18@x@0>6<*3NPBzr#j<|b<;Ss4Wlc6h??(>@-%da2 zm#xBiiZJP%ZywTcFr%L51%!)&seh-r+d^y+tzUc z+u>c3zDXy*A?Va+pES2MIPFow;bR*QkZg%$%qgGhM18XKWGaPw=L!F$@GAXSoSFLW zn^PYzMAChI5?5YNw%1#VvY~a_Prji+^-#^b)uTM_CyH$Q)TuGaJ}I_BpcioDG2TVc z2Q()q9djn>n<8~~;{%_G7Ci8ST1yT!?Jnb*4>j)7^z2`9_^?im_B|1m4S-W`s!&A?+^KKJYpSwq`6n;5Cf)vU1&v9U{G`;?_Oh(mWr=40?zAO^#6Mcv zkp0opLb|u(&hkfzOOymC)8uM_V46H|(qwP140F7xwUq&7()vT9yntbsQp=7IM|dWs zm9|e+uR3wIHY$fEtPkl*^GIiTW!icGjiqqE7U8k$fYquiTWL>WnrtIQ(7of0j?Pwo zUMj_N9lXv7s!&4OUR~^V+1l=tE`B>a(C%?N2e<2y3N!{imVH!?Trm!8w3qhiRF9}= zEM{1un{}qP@c<;Jy9?iff)tL?VbO}jr~a*KEKX@zc!iuXH7Pjui$azgQE*7Xh=L&n zCw?yFMim@Zut~wNfCVQ1>*`D?3)m0sql?{TZU(b;{V?cpGSpbvkKomDttQJ zg+Gz;iYORwl;NM4ko>V%C2Ugm!wQZnc<|q({lqfqZtQhQ3k4(ZDSIU!{#QxI74!=E zYgFMIR^ik9_&ljMuJU&xAnAj@lX^0KDq-Pn$uIn^q{mgb$KRIp*eTL}XrY8Uf5);V zouSLmucdta#}b-C{@PXe;_mRJOZO4wKJ1lrNQF0F5mhcSRQ_eCc#i#5#y6s%mJchriN8qu(UnqPlj4v3S@MSzeNaK| zUc->ezfol$*7WbC`=%VJclcBZNBlr&;+DCknvrkpPh!z++^Iu;3@~ws@ z=N|dvpBF!Hu;QAfL$kkd@9H1zn|aOe)1Mxjy>Fg4_?-WVS2CXb$=%`Di?fGM7NfOa z+wz;7z9%<4bJ1z#*L>=v&gNe{cxuzvWxF`^h=he7k^XD_Mg1K(+KbbPZGAm-aYWwi z$}X*~E~>0qE-Y)>b;3I(*i+aW%C5)Vb2&W}bc~g@HRZRUv~zvMXF0xWD=(s9Q3+=& z=&L?>5rn=!g>C;(Hoh@dU(cEv_$%9~r5Y?L!Qa)u*pj|HiiK}F5GOy3iAgMfGA2#~ zPb{%v7Z}eP%lC<0H#j-!cx{soL-%L%2^4JNVV<46v;%v@9m_*BIUc|$YZC}O9KUG! zkt03XM~;la`~>E0n7_cJgI|qw*`2d{U7q!&c(u}xFL=;TonyxHVzi1u8#Meq$()3| ziz7mztzG@}1Pia#siS*x3a{TH#8;m5CbD{@40z{DZ<1YG57cC;m?lWBU0v8>2(IHp*MO@)Kcx`fehOSDcg-bp%k{rK?D}CR5 zD%t(Gi!OAzf5T;8;j(|nW&gH|&UeX&UG%#y`3V;tcEvBQ`bk|V7P#!^y66lS9Xd5R zzp{hL>2=r@zU?mB{Z8`cl9COf?7G;l)hj~9gE*f-&-hi>@2JnE%?dj1y*#vb<(ieW z>P$aNKKBFp57Os@^6OdR+K;8$TT1wIP6a=s8(0S^Pd1#>O%3BZNN3$Y(~2=J)|LOc$93{Wf*;)lQq zJ`M9W@d5v^M2L5Yzf_1Hz@*=RumN7N45Gk?0Dle>20j7!;Zud!2z(guF_E?9&l`;9Rtd2k1K4|jHvxV# z7jnSI0N-3I#2D}i!1LCDCKA1*WB~7jsRBL%_&b;e;1htWFpS>`JPi06OdIfVz(u9V7vLel-7tHA4*@<7 zGX#7T@Y7|8Bk+TOkHcI`e8S67Ob7>jXtNM^5f1n>n1_K+06tg&Ip8CJAB_m{0`OtL zpVbL5PBMV=8-$nu9s+y><}biU0jnF47N16501m*U10MnmZWUqy@C?9%FxkKfZpNXh zjU*5F5=<5Falp4=nt)FLz6a9@Tx=I&8cZB`2H--NJ-|bN%VCCqhXHrO>;v8ecmd3f zz~g{7!yEv95b*0TcL5&-T(ARW9e4=vsq>Hyz{dc85AyDg~SK+wFnUbo&neo(+PYC z@Fkc5;NyUowjqwh2Rt)|@(sKYu&5K^2Oa^urAvrsfFA_>CCm?jPXK=G0wLZ2J`8x$ zg($bcLx4YpNxupD0jqI9ViE8N;QcTwfR6y?_rL%z1pE$674R{@%{UpeljH%v1Jg}> zz|DA|^-|&k{;eNn4>*=?#I8Z4Iq)ICU+qE}13m%xSD0r=X15Sugn0q@2;lNP2s7|7 zV8&jw6~GC`KY}y|PH@vz$iL4ZY=EDDSps|*@MBk_ei07%%104q;NyVzeGF*}d<3v~ zAJP+e1n^@p!z2%Q^~X_82nW0cW(4>_z;|H|0~gl_@$2h_coz5s;G>^JIDwA>J`eK_ z@G-!fhY?QT2LbPcNxvEX0`9&6?J)2mz-wTZ03QYvpGKMkC)fZ}3cLyMO_(a+6M!8z zBF%xv0Ux{>aREL8_~reG3-D3ExwoLq0}lZnxE*;3{2<`HFwc-Y;MZVYAbCJ>2g(U> zf|W3D0*?TO4dwx&bkwR0M7vIg$V(V1O5ai41650`!1Ai;sbsGCIWl} z@Ru;#flmO=`aJ45@C?8OFmd1^z$N#fUIPyUeh%hZ;0FPl?n8Wl6YPO`7{P8;2HO${sJ!q-1Q~I|Fg&oz)w7YZ~z|$JpMtr2Oa{f zfXN3Q0c?RO1s(@{UiUM zR5zF~@d3wRHUcMj+T(~1@G#(BmI=C_li%fR}#{;R8Md`0Dr3-vA#6 zEcs`oGsy$q`6AK<_y}O{ODOZe zlMLYcpJ3btyb!Pg=0@NV!0j*xfHwi|gSiX%FyLXB`+<)Fz6tX%@Cm@v{}o{Z9tOM+ z<{98|z%RnQ0DJ^cyoS01oZxPlao|IMGk=P@13Uxp-Jc=vNal4Rz6CS)R>TYNrhh|P z0Y3zmR-~>nBLRlqw!0-PW<={5R1CGCqwgNc8!rvl}zzK$ahxP$D!CPS>zz+icW&-0k z;1ht4{2qAFJSvTL;R3%z?_AKcmsGCa5v0ffDZva zaH1gs2N4&*BPYQ>;NoOMeDf4TYy>_A_|`H*YzIC8IDD!h27nXH%{IhUzzYGt4Kqyg zfKQ!nhy#QJ?#MC3Vc<=GUtej6XMv9b)~rIffkyzBtTx01@G#(6xdKuccp>2W-G=BS9MHG|VFR84xB%uL@DSkXF!ult1D*jh zLh^tWFo%Ih0Jp=80&fEBgn1Tt9B>cJ81Ny$Q-=)k3h*#sCCoVR2;kK)Zvr0%{5i}7 z@Cm^54fFT*c1J@!Afgc3iay`-wcoX3BFwX)X13deaNGsqGz_(%E06qcu z{4i*e0sI}zJH!X{++c`zfoA|V!u$nz6X4%q#GNRgpEAVfVA6pf1bh`{F7R={3qOtc z1CIlK9%c#f5x}Aw4Y2}v1aRR^h%@jezy+T{8Uhai9)zg^PVnqoP!32QFz*he3GhO| z7MOj&BR*0{#l-Vc-*hr`%6Kv{r!19%2tCd`{8bB`gee9RDcVV*t=I0myHb3KBu!n{pxKluG$O#zfrVVJ1b z#R|3n&I*WG#vBm{r#1QGzKA*M84D_zcR!E%3pa1fMgI*$b%~(ce(pT7#S=D~AU9{4m}8tQ(!}~SIIeh79BK?pv6`-5KRjk4_ z%`c`s$+0uBE1?X*%w{1 z6t*iJVWT*ruKaSlb?PPm{HD+E<@n07S*Ob8G@lQ7 zsB9oNBh5D>H|SL;f_-(KS`#}5%2dyJJV@)&^NnohF6u|QQw$%oWmyl zYC$Q87*3qz`%}ov@ax(q!@pqK)eF2UN zdYx(EOs{{${jt(g#!t6gcKoJFQ+N3wx!e?K=`N?*UFP(wGre<+6Ld|sd_;M7<`IS4 zoyUJj;g8ZcJC(kv;zqjr9eL+WV_62SR5eF9PtemeUXxBcHsJIjR=cgJn2v~`BniMzw;)cyYjT&I&WEL3LuU1J|v&R$RIbKGr{ zlu7QFrfQF68p*L;s=7N>J#+i%ZXewCGQXaB-*sUse~F)}U7-A(YAix&s{0z9&Z**> zD&1tbTPB5DwFTD9*6PtQ{+cR`?lel3ziyeS%DJ(1 zug?^IxGa8a@vpg3j=;V6Nu0nSJAspmqO9~h?MbJ2rN@x?W zzfhj)yq%FIW*BD+JJ;aez24!Bt13faS-(iwYvJ)iuZZM%#e!U$H(UgIomUisuYU)@ zE6lfP%_kU9{GAG3py0&{?o)8Tg7+)Bl>g3A=#s9>FfEeh^Y@LB~A zDfqC0-&1g0!3hPYZIJ#fR4`A$QU#k7+@s(=1rI6sgo4j2_^N`xRq!tg9(RWHXPJV9 z3N|R%q~IO}KcnDn3f`mOsDeLK@D~ccqhQ8H<&T0J6|7P4LkjLu@OlMxUf!bUhZKBV z!RHlxRl#2<_>O|+Ch6~d1y55jPr+gZ8x;JIf}INXD|oSjS1EYCg10DmNWuFR{HlUa zDEMs!UsUil1>aWi-xc(nDZ`tt;Cuy_D7aF=bqb!TV1{sw&1wX3b zu!6TJc$b0?D0o=Grxbia!5=F469s>v;DmzjDQKQ0<26&k1qx;=%AJl)D?jO{DnGPS+f0+*duhjoCQ9@VayDR%}K1=XBixv1tVRuY? zRFvR}zJVBjZny}iaui*T2mXq1eni?<<7& z@%_oX$~N%>2UmVW2TU>B1NT+UiGi~I{=R-8mJnUt*EZN4qo~&4Y2|G=wr+D}2;uYD z#GCwGE#gu@)Kz?(+0q<*iJ?fn^jO`TxDY45$fkY(Zx#&3=`q(L@p0zt#iu5E8tA2) zPbAYt2?`V2e4cC?x>_$Rp|3sRM3L{=$xqNA?oW960f7i!V<3-Egg6+ne(~fa8|yJl@rt(&uRc-~ zaH0t~e;}EQ5KhBu+A2cmv&=erla7lZ&P|(j1Kmi~^1)vIuxJB)*g^P-Thbh-PdHL} z!skcC4B}Pw^<6j^*TN`H{WwoNmu%D%2#vk;x)9DWn)Q|+*AXrYM^aYZN&LoM`Akt; z*`8LsMUO8(ASx)OV#KWPj>Y2QD-xFN5s#VmRwg#|S(zrDFdJh1Jze;o9zI~nkADjB zq|K8)i*K0?-3iJx`mmpP(VWs_@pBUyi=ZLqZK!2^yklF!HcfA{=!oN=km3U^UF_SnU7x==L}shqS2Blz6sDu?``0z zHflvspUT0<^9Z|yr~%f7Z;15rqh4D;b;Jhf6%be_aC<+>uYbjQcZqt!`&y#(&ZZFO zg6hVTT)WikU`?PC{LWTfy|dLKIrvHx6?%GSgASobn_GL@x_iaNzPh{{)$#?568 zPRucz2l~2j(%D2a3>RqSOc~?#X1nsP0NCI_tJuIWAvT%q9M&@lBCeawb}M9+!0B~( z@?ZnGoHD*Yw5hCcWU&+>Mj2WglSaI0?ru$Rj3x~Au5fW5 zo;b#j=HvfAHs_Sp)s$6P&qa&5i0cQ&PJ^DruGanmegR%&BW)V%%j)dZ(zCArde}6( zFs0Ir49U;wi)TG?j2@n-pC1STWOuu6J7gCq?Oluuhc% zIAaVen4x3|dFC^mf=_Z4Fx%r^@k!HmwehSyJ=Viqo3d7~3}@l(bUf^Z_r^A5H8zyz z9w2gRZG}hCCPu{_OZ(>u{V1Mt11in|()11h$zG9h! zCtEi(Cwf-yTAhU#t=)WRGcKi zP@n6GwMFo~A&lBOVhL^Mv@P2Mhcs%gitUPZhq~$SrmW^fW$&)O3uFCRtF)tytESYr zah22ejjOCkklT&)RxMsXYw7Bym+X$2MoHq7S~36|@!@8k9wVq$kQV3U&{rt&RA~#| zSlf*^<=S`#jYq?5Y5heOe&S8Ngor2LkdvXD97~n;{iE9YP-WYutV?3}D$VM=wd-?M zugzPRleeaIZBFyr_E-)+Ow$&N#n!Z~X%AoKNS=Q@EbEUNjx}pnugPyIXwF&NR)BD{ zx3uNt$8y_pnsf8=!nwI?+Y8n-|JQ^g|ES@}YtC)Y&5y0gS-YmCASW*`Z*@*fb3toP z+q#0byym>-b+I-1|3%?gx%#LfS>3*F{kqom>vHnLvDG=H%Yq2mi#WZcnrINeD3bz8N(SR~~io9>jd zaVbx8H5I;7r98b)k?JSqA3UJt#U?3#!4&bA^1r@I%g2kQeAN`;m+AGlhqU}?xs=~J zL-21{y$2|{lIQ#@{d?|t?LO2XC2w*HIdCcesTZ{TsFL55>^gayzuVTTI$_c28w5{af0j?e)Aa&8@*y=3#41I~ zpOn8Zq2Q3)a63}*xl+r!?WMlAEqguBywfeHXsPdxj~`v%&QECjQ8jO^nj(DC z|Np!}%V%6I^XKUCf9g|OKBVMvMJnY_>fd{_mM>KD&rMN3Wc(K1qvhR7rM?#}`;2R3 zc#EdcC*^=fMURr&kGx3#=mK!&g6J5$+9|7xGr_G81+zq5}TzQP}C z`KFtsd?elNv!tc|lDD<|$Q@F?z(_4G!`uD`E$^0+`ZoMg+fN*l`p|%+{7Lz1-?ilL zlJZkDUqZ_N^Ltued_l@*rqupl&pf;onU~H~w43!iV$oDuyIX!q3I;UpTHb(ZVl!@($t!%}!356UU=Lp1O_**-h`-PXjdKw)N-cufjj3D`I<)I<4<+Kjzf?vU<53h<6{P{f*xPAYo9=wKG&g8wBS5;Mr7?Y<78fGxj>n&obXk3&V|hOYm}N4cJ0@=g|CIa0JdX z{569;EwO&QZ7#p_3IzvP!2;WjbH~rTH8>qZ=#U5m%)mN$5u~r>Hk55|5M!o!h5r;N z^+#4$;4^H(9P;16L5$=|`ol~I{E;=1zLMz-e**@&tH!Z{UJ8{{Aa>8pU6^>A7^p{k!2vSVR9ppuPYGdZH$ll>+s=N^L8el1%cQc zWMT{iVsi%*uYf>o4lywfB2SoiGVvyewZgoMi3xvQ7XouP6Yowt97KUNrf+^t+M3PL zNJE|QujYn|)na$f{}hvvt+n_9hWQ?~4(TNoMRmfQZ%~_*P7Z~+z*qwR&A>O{QF>Jb zAF&o@rSURR6-70rRb|4w-eAWhFWvl`@e(OuuO;UVgFH)jv`e*(4V5);{FrCGUx*o$ z5{*D+Qd2XNT9uj9_An;WBPkp{;fX^YEhql^qSdQ&^NU1=x!HFJw7&`;mNzSW(}4?r zMOQ~B0_}SbS_2|oikfHpcENTQiI2i$(1t>$E-_YD489jaqlq39msl|aG+`=%!^ny-O`yW%zkFg^q1lT2DQp{f?a1Y&vrb( zl5;J`sMLeZny=f_UF>dwB%^!=z}(HeMgDRs*t#O4h1}yGK@x}j+k1K(+`WFvrGwLT zq|sJf?5B)6h{rJ8scT;1pO3Vkd(bfN_1}Yb!C!%GZE7a&V-f`<*3sO$SD0V4JwuCi zzn_Z3LGl`j`X#1Dh(dBaz|<&Fh~I-ujS+>Aj4(A$6q>CsGc_?C6x!#9m_myM5-s#s zn9N`jjpxHmhL}YA`3RF?CaDSiD$|9MMvxw5IwENV>M+wyl18w;#&lfL2-w$|9+EVI z_88N6XN1c=HKknc4KWV|^7Gt;&M)sCsK*f-VSa%NC}`x5cS!HV1<>aA^j}y>mPhsjb97p{^cP z{gL2jU@3dpX0V}zS?yV=JPXoXy%L7G(;OJi$%Wq^vqwujXk8| zFG-uv$beIm(RyKVGtMcP-(pn($*St=!RZk5+sw=G*AKSnlRquO{0?&$oIt@2`HTAT zDU<%@{=M|6<47O+52`XRuuL`vFx~CK{3i|sie`W!kgft}evjjm9?|soXUhZ_y`Yj zfMdLftYbZ0D4pM7`z4BjZ6#qo%dBP63F`NA^Y$W@vO&X>-WWQy=jT0-blNCpQF4(b z*DkN5Kd$MZNS~DE=6C1KMV_QbQrSEXmu7(Mb#9ecR+Z`Onrkkb|H+xio$BV+&aPe* zu~X;E?2;q@+IDqz64A_N8+2DV1cZ_uL%GDM7IXQ0D$b@~6|086dj8>sF837Syn~aUt?^0sM=HCk) z+KXDAiWODq)Eqav=0BIgsmVqELYbCnKSB97yXRBq?n&!F!)W#};Z4IMf#~C&Q(%6LbC4F4VTmh9<$h1!;##V1S85X>CLdG7(Cf ziPqcP#l(`dKakSh9K`Ij%gAOA6Q`wphlssQtVp|%h>Mw6nRb}mT*5>+ZID!7%0zD3 zBP4bitIkV1jchJwB0ud7a&rX}8`G$9HHVleph*t&kL4$wYZt3Aywj0Wn0&gQH%>ao7 zRquwLPj+tgP!TZ97w1RjAh+x3cp#nq73L2(6v9u(QFROULvB}1zq@7o7cMIctYVj> z-F#_&H*}kUKOhvkJ+~!<`E&ML+cZ?wM@x#Ts)~zB&cW<%;XUm30sLL~H2!e+&Vvoc zp!PX%XHYlu3R%-AOJr75*3>r?)s&P)F$waG{RK9Q2JsDNe8ki@M$;k8N-Y_%W?+Td z43GkEq@gwvtt#7ER^?cjLX(VfoJgBZLBM?WXfnsmfwIgf{I6?hj8xW?*A|J+z{&I$ z{G!$t5eV@}X;F7vPYy(2@xLPY0kBGAi3f_Q;A+d_I#q8x}JmxWD_?`Qcmu2;^u*iEblHF80hb6 z!F>b~IF0!E#OLLaXmw*%LuEq+=DDS1r6?9BZ^fLqrmPW*5iPkh$RSAQbmAS&hFi&_1)}cN!%ojd_B|C(lAiCT#kw#cCtw{u! zS6Lq^YAC4?L88j)>T2u6G!~)dmg$5cER{ty4I-V0#+q|#YPZ#h8AOzpm0)00C1w&) zxmskf1d!Ph$rZ;*Bu~s?k$f>%GV;YdW&-Km@JEEF`49 zsJyJGuC8c@$Rx5v;)@8UgPNsf8P(x*PnJ6TxxT>~T6cGkJWkuDZSmL#H7^jO8+oG&AT3dWJeWS2cOW3S3Vv#B> zQ%;PMaBpNGQ-G)> zVgar0EHS+>6m`|8&H=XMUln2Tl#mrpGS3B66G`a9f^x} z(;U|GoQK!x_QIp3Y8eJRS`=J{uX1X8acZ=otXO2%43rG^_v4G74KYmbz7VUI~Ek14@qz2#S&1YMVy8^2J-e* zG#i%i=W+l7oS&(QMFw z*5+ZLVze0F#UMhgLJXp<@&b!-IVGk(sa>QZYaIB}_ zfZdwQ@P~eDJ_&>-A#3gg5@%lCpmO=_5+T;Y-CCp0$Q5}XR_q^uT`k$3;1RLzLB)R! z{Ja+&ZZA@9SBv#4W*4&VUqL3{s6#$-RN`?Jna}B?=#?yn5FhvrT(7@NxqF9#V&JKd z&`2>$tTna-y$dX2d(fMq3D53O(97ROVaZj|DBlk%scXP2moCW(<26dV5v6;j+SWG? zWQT+(=#D2YMtwn!;-(s9|2VO4g02n9J?)YS<7dyHIC^gwyS$*Qx0IKdw+!M&lrUbW zow0GqpHYZE^FyQ))j7&HV2nRfWx*TKqM)6Ym9WHMyhE(L#Og(5M$2RTiNg0F%*HFw zCcL2niekY(J(e+uMMAcfy02Srr(tL78}MWVqNCB`pE{xb0KO1C((AIL9(tR~wv`#_zDG+lEe zka|LH19BUX;z6Y)hg9J=1~qH$CD*WBce%1XLIvp>MPw|+=LsN&-1iKiL>yB5Eb!MF z+leREH#vk!@G??fG82l2=N1w!thAeB%sv@GE{EMT6H#0bM3l}wu8^d}GT1?ZciNj? zQMy|(OC-|>qtF?-@YD#4b(bp3)d)xF#}&~GNh;p!_AACl*yi1(h|M6ble$nqRYei& z?p4-xuwFN+VsbtazfnXl5g95bmw?D?R>ZX+UQxlT6?s=E_RU~V$gt!aTSVS-4t^lS zVI=;#*A)K{@>;6*_RJlbtUE6bN{WdwuP=^a`t^aCieU=2;N$WBt#ad5S1Z&-Z zP70mPIV5Vg7sN%svxWK)yW!Y?OJ`^f>LgdUAe$k}k!U0x8z_`aZj~z2RYL;{ZuGg$ z-zMz>+792%j<)iyjj>%?nc9lSDm+p#cF=IfZmcSBnX$XCh1WovyU`ZV{*stcMG9co z)f11ZOM^zvI_BY<^j+O;t<4yN7}KT37|2VI#%c=etox80cS6V6B)+FB+ANF>`$0?UVqu&?)GV5tJa37$lGw&4l~`*O zVw)7zwzoGr(4FAON9opL3zpx7QRq7bdw$o>Va4)xCEw;0M)Aq8F$3fQ{FGKP44aG+ zvZ#_x)iHnT7`(-b`D-S%6kgY?s!R$>Sija zn+bY{rV{O?c_*ZWQAra~l$y~ZR*HbiaP@V!#rCwu2drze#<}Y-Q#?o7##?E$D~xtZ zWK;}wm&dY=$EAG-MLy^aDEo?Nb!E-wZJ4%T5?WP-8CY@S=4f?MLj|U8!swzDsM13+ zOxgz$ZMYa5#f5H)|27^9x$KcC%6fYW>%?H6w%*~k#yA*vbN2}2T(+rx3JE}F`WLG4 zc^mpHkC^^I^?BfsnZB1qS&$YgxH`V-)gF_zaLJ5UO6nV5l5Rl|_~Ouw#1-4a${c0u(@C?GTa zqt$d?jf}CbmM_-wpNw3i`bUTunb`xPISU08vjr@i$g^9kS6gSdj(KcLq*E|(-l}B7 z&Yr~H#JaqlojAXmwQN-GBLsdlB-UNsIHoUYv;%-a^8KkJ@f@0m55E!3p@< zvHpV-AU^?-;lr#$cuUA)0m6$9ItV`n-F3VpjgFq>UCtf>`QRU z^qO3vvtI}84ZMWE0oO7P+4ycc356hdlx3W0)-n#s`-SHoWMU9=aJ7s>s9eS&jFxd2 zVi|`ZE#ol6G7dpn#vv$|aR`&kILxz_afnjOI4r`;ID}ctI7C>>I7C>>I7HAg4olE7 zjzqAGBM~g)un3lMBm>Jh%%Ei)$)RN&!sIdzVb(GZ5xk5;h+`RtNWF|hc+xTsG1M}S zMCCFL;d&W|aJ_J|ln8qnhbVg)hbXy>LzrI1k+@pMu`TR1n^G-dv&x8-w2VUxTE<~0 zmvIQ4yo@uQTsoFI;pmjuo6N37-jr9>ZWDWw`H{*Pt2ivrddiPYASlYwN*TI#LEtyiFJ`99Lv8~76ceFA??N^G?K{7go) zEtY8Q?~2oDqhMOr?~&@hma159$3Uk@I|W|>AsQ=AN~U3NJSNhX5Z~~%^jK@>36Zvx zm>%Em(il!Wbka66R=GvmX;dn_zTFL2j7qfQ(Gl9HO*@^qK3_{~TWNWtK3kEtg1BiS zK!KA3QIi_Av@Hv8vLy&f+G}ViqcxXGI^yQym6kOWVU^i%NJ0}!dXjmiHC44mSoYje zQ-XHTRt)jd8qQzS&1DCy%a?3bT~t$9URIC1AZ`BCmLe@RKf0}`64kE0K?ITo8Y8xc z!DK7d@?y7JB@<>0>4DmdkVd|idO3p#M5q%2y*tv^-A$R%M_UkEC^=0jh5e2?5(@ab z>Ur%>1nP+nO2u96q9U;MKoCl3&5R0+2yBa>dVs~Xb<<~SHYHu%&WdwE* zneJkDK);Gzo$837_l3V=e7n9fSRH zZ8Pv8DpB+4Y&MzGjR$V*^+O?GS+`VlChv8zE{Y>I7d)b@QGG2L5;@ z3B@gp&%F?TAvwf^2OWQ)m3rKe4+mp<04L0-SkR%wCLz4Ec{+``f3KqfXWEt=!sNw`?AA&y_zV04!-Q3nj3!EZ2=S4(s zk@8T^RD$z}7xK03E~zUK!39JuQ58-EPoMiqsku2@O1>WZ$O+_LAG`+S0OU4R$j$uDV4u2W(Y^Gh-P0Fs>R3 zucTyE!#GIVVdsgep74p;Sc=Dd7Ec4Uc1AG@#G6XSCdxeHCHQz8CKI43w~lLzwKwDG zqa>j@{kY7I%hfomWt>GNYmQP;$faX0ze*F`CEwQ)#;7q{^@FYP!RSC=v^%zXo$%a2 zDepZ42Y`;-1BwQB^E{qASAsFWC0}^%BCGi=BziZAiaA*Oj0?}_Gr$+eQ+}NTY{4HW z*y4oF7!Gk6hxB#MUU2DW9LU0iec|`is){EeGJmD;nh=)!pkWcM#fHa=cKy83+k`w&w?KXE=*;;z}hN zhYt|*1mNLGGNaJyV0~2>*HZ$AmE6~X)6Y1t5GO}Y=1jYuvg0-+<;lH0Es!VjuORVs zK^tz52xFKyo*T9=rm??q!}FjjF#}&%?g;ZvgwT_FA>^%xsO=07Vo#d8Ki&T%al3tzSMh*PNKPbkJ|LjH^cyCA;g zW?0>gFfTa-5x>OaD*K;%Ve5T>rG8I7SfEbK(8$I zTd35}p@khR#MCPSXRU?Nz^#{ZEL&G$TyFf#a(X#e1?6;z2yrUUl#SOZ+uRq6jRS*N z3O-q`@Ug@uw8BJVZSVEh5sWG{z>BffgA>!(j^S3)c!N|uik5OQ&Q0>LLs|TsI=}^J ztrp8Asb5gL^Fz?|NChpu8NZ~lhWCbv%R{XLSax``6yAAn7{5Fu_lbT*?Y#Gfp)07Y z2;(h^fcJ(sFJIhFryJ=+A+3e}n*6^Tsu%Mz;@d=~p*k!^tBn=~y$aqj6vl6ezZiMG zxE;EFOVm6ZR#H-O!ipgMj?(mIw&1Z9+;=zc6~+WPc$fJ7c*+lbJX#a(YmMJiQ?Mh$ zVWYcU;}2x@(b;JIDJ;C&XB;v9_COJIVaZP>L$tYr7Bq|u&uQb}K86LA#aLl|k39U! zaY!v0HmtH?{YmjD%}%GHxAQ)!3&)v-G1s^R@=LA*e;is?5Hn{#sFt}v?gnxd)*)9? zL4HNK3whwK>kI^u%WlbhRhlmYvVtsEQAy6BV*C}bPMr2d=^xc^swG!&LB>9n(z{UE zM@a7l6m{0S{&=N#1jq`qwDr!!f>>6)L$6YGuVM|8s=cphRjVP+6|Muw3bM3S(c0RH zuR2u8AnL%qu52bqd=~scgkuFUbAABo z2~a2gT8X+;t$?b`XYZ9EeiPpKP!!0kU7S_aYGONY^k1aFB4Y;@D@PT9y*>00B6E$3 z19enOr1PM6LOBtcdCF(9F45L+Th=?2_0#aYnXR`_t(EO`=B*CLL)x+TB^d&d+4v=i zk?z~I^-s0#6R&evBT_-{pR|<-(?H>{vd4BS|BQ0uI28WO?kL%G*lSa1Ik?V zkPHSz`!`U>aeMX^mDpKfWj$*#WNQ_X31T+d36)>1ihU~BVP+%Mm;Feo$n00v1+cDQ z>n&7-vi2)}DfpT9IdojCbqp&V@Q1b;Gk>InD6F5=LR(%{9%cPTS=W-nIbV@%8v2ZB z*&!us517ItbBU6q9{-n855p zI)|;d^9E<;KRMi8pxp^8LO)a16ojnbE8-#|W<4Uqa~Tn5C}JOo%oasZNWY;~R{U6s zi>zJB`qL!)yGJFPWPhb)PqDl|qO5O+?3&vSOWD~dL=^iQ_FsOZiCx;0MCPBA6(#is zW$k@S#a<`1ahAyRe@*J3l-?o*DW$h4_7~w#=5|HIAv36C!s5gmzb>5)gAJ8I?{8HR zrLuw2Bo>~f8Z_)ZXVxqHQE2=&E7{_?l#6Q~nlqpxGfg#M6zB;Z=mjrJUv!{7fh8hq zo|2@2d*%#P&A$uH^U;?eDQGw%vQ{e#nF)%Zge{g*LGN}IVq}7{=1jO-5mbA6wd{3T zHuJj<>+7`jLCbpDgEGYA)BW1I#merJlr>l1QbmwYuV~r*mhAb;Iuq8J7dd22bb4Ii z?K(ZAtP3E!h^=LvzD@DDPLDWr)My>fI(-E^dQS;a1bVcPU8iS`$oO%cE>r}`epbth zpGXOj)u60jrU-o0A^R;Ydxj-@i?V*5Wbai3CCu-&Y^^2x4Q0(?_@N>w=JV0XqNs3( zxLCE$q+>1f(FpF>Ix<@v*5_*LQDsd!u-l(`pAw=%eudN>^xpliMS^}*(5c`)ri7>x zeMV}c3Cgz=o9fL2lI;ncEwcVi@u{3=)~Yt`Hwfepqz9hB5s^8e_xs$n7PGqiQU3i}prz~5Fv)DSkXkZK6$eYFTt z#L)s+^f)b+D+|i{m;Bsn&PH0kn?P)KIt8 zs>HG(R>@*~k|y&q#m@(yj%vwbphE@M<_-HU_oH|!xf00T?3CjPu9n(zSSBH5^r-X& z1<=j_ULi0xqK8m|RDfQVf>eM$q1cpx|E}E^zATlB%x^l>pN!K_oc*cPzvxiEP70Fx z#j0JWvV9)2(TEQ#^@ua2R8~w0)gY#smpfcsr(Go(O7?Vu3etq3YMi!m=onqZwF z^Hs&Bs8%u?QN7Zt>)U-;89lO4Wd2&oQARW==a>Ne$)Ob*J%Mtp9F-eFTn!msIhw~a zK1@ZQquIDUI?uyAkoQe9UlM4Au$a|C&tMxlG}=Q4qz~xPVr73{A7;j@Xx%jEjc6OW zxQ4e5JB6{DlmxvM$#!~9n=5s``;;soYn4m2TxqP4*6$=+OUJx;ZRAObiDU^iF_t20 zrO4aKB63+;Pj=TynKzSVx@dt~i>#L-Z=@2TC1^Em&X;22Q;G3PwNY>_aw6z0OimTO zw6a0k=BKiiaXLdvgq6fP^#pe`+A@e&=y7;OF=hybthY}hOwTpeW5sL$FE%JJ{Q+aW ze&1Td^u5M9`3Sf}DL)DhoeZTCypzpZ0H==_`M~K7ZUttZQSc)#&OE?)tJlF59%8qG z$m9&cU<1vD$#|N48`eUcjHlDLUOn@zK>Ec-K{4haWCFVjjzEY^;KKz=0LTRPZfF4@ z<7x2~9D*R3zy%v#0E>+0JYT^Uu*gh1xu6Yz%(Rm>Y=tcu&$+%0w*Zpybo(}Z6V_xr z3w-PKTjUz12R$1efE*dm@xFpNkRubgtRM$~OyDCME`co>&k4SQYXQjw*A!d=TQakJ z>-kA|{*zH@6nq`_WM-M`OJdCjH7^aNeoyyj^Mu)V?LZC>+q z;`)Ng+q~uq;--mdRA}T1q)G8Lw@@vbZtuog+q}sX1?Z}VEa;k3=`tHl##$f|m|TJ4Ka5dodF&FkC3 z$tk5`_&y{F1%i5;*H=$;P;Rr+Hm`5%Nhn7_Yn#`%?M2qAwt0QqDZi!#)i$qh2a)MP zwax20m&lnx)lK`(BQhhX*PDGii9RmH@=Mz3Rn7qyF`w*3=`9XV|*B2$u@j=Hn zudj(%3xaeoDuX4!P|&%}>uV!kHicjKVlTi!m~g$# z>udiuSouNT=Jj<@$`qm!QnJrT_s`ftDJ8dg{WHG{MFLUfZC?K@BF&)M=JjU~8IY+g zw|V_(>DWvNa<}deeiq&!(e*a3e>zzPg1mv@pZ&kcd-M3JsskBkbBKN0-uvEvZa$E#^-Swo&wAE8?0!h6FfV(XH`?_K@RVtSW}7!! zL|A#A+2)OwGS*KkoD=OvgIDDF+q}{41PlV8PRC8r9)t{$@`;u)%xzwpu_G!KoAmls zP4&3vgOKA6W}a;0eJzOiT@FGh z>`;u3JBvN*SDe&>_ZZw^B)S0LE^XvFluhINq~doy+~F4^)uS;8?JPShBS?HbqFr&m zLGN44O_Zhpg{K{W(>;bRtuxLxy5mXu0Z5B3FG&&YjKF$s66j)#dAH;DTz7b}%nOP! zF2_uKQzeH`QJ@_zC10bmQa-Lxa>6#ZIRW`Jd#uq?*<5Cv}D zQOtopW*sGOC=o{eMPF)o9vFUT(|9PhoT4KYe=%S$ zYpzZK{5XYQ4fy9afnAz_Q?yCZ%wr#P!w{F1M@&$tzzAHXRI`$DNjsE5YxrTOXppi! z3^pE?ptWIyqGpBf1N<^8?!`>TxyVs;ni5g@`z_J4R{4_eDH^mzH)@!MeBY9Oo{=Yp z48;$1N^TBtJ*Z(?vLoEsShMtT1^)qHD$FTSw?Kthg%9YkLL5t{dR~c#qmAH?ySof* zra~Oc3UN#?TOowLwwyIUuALoA%3BfdEZ&dL`{40Gx1Lfz1GI}&n`Mli+}l=x<*Wkt zAZjYeiu-}>*az+2s%G%6WGCvi?b%@}$SU$)4=gK)<33*BBLx7alDO6bk$SPmPm&XNzdmnMM!=k+ z&(s^3;#$jCVN)zB(`+#-7g=;5D`*o;eJguaDe2HfA83Sr`ha0WtuOja!SvH-4Va5? zMKx+L7R~zt$AJXui{*l%l>uw^!5Xtl^t?jZ#u^scP$;@ifh^&L29YV@ zvilV)=G~_eG4I?Wi|Q={seYDO&7wgGOkl*9tySfpTPN&y)!1zBpzSm3WXZSxl zrWcM4VW5M5o65g!q8+mn?eg{~&A`i~xz{rg$^X%DG@9bG{ z-pMY`M&J^N{EClsdwmRn{2y80s~7a-|HzhJN8=CwN6zS#k3ak$IZdvDhMjNFnEuz3 zLf$X-L%C1B zMg|f3Ki*2nnJ&uvwdN9m@Mk?4$*H7XBKR3JjpC7362)?^4SY-oyz~`d;{W2>K%ReX zfb_UF&;Xx^<3zV!8(`2}8(@gn2IMcU4e&3o4ai?y8{l7F8{l7aZGa(jZ9riDwE@O- zRwE>GZGa*F+5jW|wE;%_YXgk%+JI2-+JFh*+JFh*+JKPY+JFJz+JFFfZNNZyZGa(j zZGa*F+5jVRZGeHmwE;%$wE>2+t_={N*9J_`TpM86UK?Q8zc#=~=Gp*bnQH@#nQH?K z*=qwPtk(uIh|C>$Kp^H{8z3xrZ6MDc|HnZyzHL{(s&Ny}a`D!Fn7$dB>^?-_v`7DEPm{+6 zVOMA8K|r3t$E-?4VsQZ<9@?~u2TfaXxl#qzyQ?|XQi1cT=Pu;&?HScHe0ssc`3K{s z*5W;odOQlUVBx%K$IWG(4_1rx+C!$NO@oc*qq4M<=(OtjQ|Hy-r5(Hln~SI906vzB zr_y-eaeB>+h2}v-yxp9W1Vv<%jtFFZhDb0)PG-`a+V417au8p)Up0A@Kq^zL7|xpmEmn4XxM`;0sfmuKzLjeXfW=Iu$g|mlNpby*@Ou0xm3A0RSFF&YXrvX7UBs*|!%@W||7)U(ayLLtR7b z&|e#i6$yu0th+>Dv1;YBZ|H@}1rth~#vD{i#4Fg6b%fpt4GGb}Fl7yo=ujbz z7T_r)3_qIJI-yYli51{2OT66dCoo39@dBKj-?ZEbRfYONRAJ&47UZPRA5f^Jey;pw zpr9jEgsMa5VK`v2HABQ{wrVAUY>8gng|W7rBN(_unjhQcr*r4)rGd~qL3v_kYYtd= zk$`O;DNEgDi6G!Eej*uHI#zJ7f{)91({jPVfqa}3S|u7m~L^Yo2vto>F6; zCNWPry4yD7Kf>Bz>r115FQPEi8u~rW^A5&sp{){j3UC~{KCpxq+9sm-Eb1RAif&>> z=?+)mE>K12jLyE}@1^v)p-+ zoTd+5EXYVfV;0g0T_*6T@yIJB5-XrXHf>>bx<(-JL@OQWI?>a&-i<-)-QrvCIpigB z8S^b}9Dkj04){9$fHu3sI{-i@hCALyz@wgvX;UYLJ6_6Up7y#Bz;HMoMKBzH8!X{C zAFD0=*0uInpSwZZnGIO1ue4vC*?z_PG3<6`m5cRfIMgL)Nj)}*ntENbm(*i}35|5g zUQ&+@AvER`a!H*_y75JKWAf9P=f2}dRYC)&i+^c{q#e5Wmv$IU;0A+U+F`U~7hTPb zAI)fCmyNnw7(a&bE}hxd#gAn;*~R!y=F$!`Q{0(F6R&5uq%*xTzKr40E@lBYzMQdc zo!QF9S1{bYGgr&vD?fm$<(+#IzKY=rYKH4LeUXRZ4BK_u`05gX#&yx_ILvMer9o?V z#aV1DTV`5CcPQH!cRVJ0NrLOw;XzXDQVW1#T(-bzXQ3*(0BO6!s8bS+8nz&@>NxBN zHfqk752L(d+@u)JKuIx$iik0c(<=@~S`o>z_HJBn38)l$J4#aTPSAB@76D*}x-6SL?)UfZs1!#1KBaNOCf z6B|H2bmeNibvEZ}aC>c6Y#WA-13q2H9^+}ChqZF$elA=4c@+@Ois;U}Ua0TdHiUK2 zov+bThe1|-BR*E)E}+kS0tS(1U<(ObSP2-nV1#TDL9Y@d3-(7bx_l6#ymK#lE+*(L zfDT>V)XIuW<@a3HGX=2Y^t}st{c9I6ux&H9HXbHNdN5i9R-aSLQzUdc%Wo)K1FUA0bjXTBVRKj z#B;-KdrpozmB%ZlQx7O+#DwBAoys38ygT4aGvb{QzgENmAS!!n4n`odGeA{2MiG;M zxH5>CsfZdN?llN(Kv0wV0OlEs5gkwJZL&h`-?bRwc}g)$AuR?|!>J`-{jrQ2|H`TS zB7pC2@K_{MY{k4jMlL{=Yc;$Yl8zBdoJ89CX4>Ho#G+D>4eS3E$15q>wrZGFW{0q` z+EhH!F9kLf465Rb8fI0z&yeJKSNf8*Do%1LUJfw5t6|E0(U;rrBL$xfEm7dIx<7In zoZ{%dCc*M3+~~p$UExL70NiN^0v91Lih&&nEMcG-fm0b+gTS>2^t)R5&k@0ML-Cz# zAI2cdUI(Xle_4OU?}~8S&TUZyhP&hOdz>t#IwR@Ke^v>+XzPCeYHC0~{yC(NB20Yu z1H|wo6zKEB{WWcT2~lrgsr2MiD0T4+(wc zEUl84Aa@f$nW-!BwqKomiHkF4;yLGRgCAa?#Oyp43Nd^Nxpqbr^+_>#XAi_w#x=hr zJK2!&Ew9R>6wZ42{j9W1y}VuVtd|u()d>CMWew9$UNww3h?di2hvJi+idO<$*6ef? z2Q4461_!LP*1HX=_A+1`akMMXl`GVEL{GNpmwfbw0Qy*q4!xO{+&h)l^yEIpqRTD1 z-}M1*sDpEH7KP!(Y7|X4{svm`o~J|HePEX!`YY!!4m8Ypy8iA5Osap1zn$O8Z{sBBIhhdm?yp27ISmhxqavwCW0zK+s8+xyE1XU7MuE$YSmi8*zX#)7;M3Evs1yB`DVC!xBS|q%<1urf#5zY`*57|objs~n=vxkfOR)!-q>)4yHmLud>fut3Tv3* zMUBhx1tpEc2?!2X1aK?>BW_a01dxrM=eGc+3{A>uuTRuuJo{Jnz8w z@b@K$hu`s#Bc}%<-%hvT8V&9)l{nZ}_zE zAZuRfK?oVw$*s@4ZtWuFbW2|Mmob`DjrFK%UXO!dMz1o$r5W4ST`P1~X9BHZCSQHs z69C8AZG9(gV)jd2lfG@At%KcXo7Db38}PEvHn|A(ng4N^b8-v*@;{D#9?p}gxJ$2p z3dW?C$1rxq|NL>2=im?jhx$cQ{D2kzC%R3(0<8QWnje|G18Dva%@R>~ESIAAr(ose zdqBkh*q%z;bF}tv$CKQ2X49_INOv+XA@hIeSJBBu5Xt|cp^?e21IGWM5s^vlZ4q`b zTZEGzhIafPniEMk>kgs)+i{yac_ifVf2cAtc_`%Zf2ce%`564=|4^SuI@CNRC%eu>jON468Sw4@cH^*_--!IT-YgrKk}8-&J?GC^1yIV3^4&Nr zr<$)bw)2U`+%HG|+uMX*d8Vnt zCUHGg`mShBmT1nVpY-G!&S>X~>vv8VZSQ8ZzW>8ZzQ<8ZzQ<8ZyF7L!scNp$TBq z&;+n)C?wc4GyrTG3V@r22Et84hRmiRL;j{ABeH48Kw#65QM+l#aMq?F0lH~uf@af@ zVY_L_u)k@@NM_TJvCO6+V`kHkA-id4!n$dgL1cCar&)>&sG6XxO+x~vV$)FmnoUCn z58gDCSIPpLhUP^wezgY+hm6=wLm|{nLxuyJhKy!54FfTM(~z*>reR!{y6hr)aMO^! z8JXxyej6Q`Qw^ym@Q$4&2gCfQSUPV@)_>%Iss36ar7Jc414h}f%D@0 zvPI%s7s{i39tJ~!J(M2pTaU&F@oD}tuDm@K?MFDadxCF|Mf(#ND#%$uj}F=fFt)O? z-X4n%CKP))S#OU;hY%Wbq8yv)p>&pgbnY85z}q>Lo(;2y(gRRPGKbQ$VOfXLb5Z6{ zdM-3@C_NjMb11!iq!Vi&9ypYqO^|gcJsV{Yr6;VJcqlzKrwYZ4O+RxeJyypa2Jx&z z>9M&qC-#9zg%{xFkq8^9^Ud31vH6VS`)Cx*9gNtb2Fz{?{6p!nqq@OAoC4j(h%IJ$ zbtuqnjMx%J69t&OU;^jFmNMG0KnKvVqZutMu-h21V;Jw!k!r_|WjI-oy)YX)jviH9 zklAC4)e}-u5ZFJd>!%gYiFc#HD>9qv@$Li+3hb%Jdk`{2$|qjNFb}2EjI5q` zKu4Yr+JJBM(Wmmd-wq{XJXm1QSvaxkdH56#-hsq-Q`{K3k@*-z@Z&h47(al6@j~6a zIScp!6%Q}uHmq-MShJojYH5eEJj{m+&;o429nGGU?{KRYm%fbuZp1s+VvY{I#Fho% zmQR6qC}%uj%BVwciYbKF)UEKu*5#{4a?s|uBPhl_6xhz#KN@irGKKfUBv(4Gai4Yf z4om^;I9%J|kGs1+#?oEofbX*|d5T9M&Nq8OP25(-@!}ZcZ-C=3g6ETQ08lY}t=dWc zP368(VNQ`2VYM5}1Vvbw#ez$5=ZX|4(UP_}$$=U^0MZYjZ4nn>hQE~-0y5xOF4k!< zM=q`mu#MGlxDwfhUPu88X(dw>+!tVgct#brVMaTb+q z9;EVLMH;hHnMy;3%iY}zi-vK1j__q9W09^ODa>M7$xxO z7}C&aM#4jiT?A~Ek9Crr1{p3&KGuhm>s0WH;PFaA)>c1pr}#*PBbDTF8fNj`AT%hx zHG$%5LBTBxFl^8;3+@+2C<-pQRlzK{H#992Uh!#`6|QoLhM5-Eam7`x4WxyooZ`ze z49+2@K<%xP)_t(k9>t#{Hlquy!ZKG6xmD821}}6NPpcx}wwA(gW;6Ol4AISWqpKMG zZJbfgdfr2{C%bVTZ{JG!y~m(MY6L+G#NvAZe@#n5$yW!ZB(Me<{F_le6#pSDJre#M z``BH=o7zQKv`0-@jK9MHo2xLa+@I6cDgIbx(C`I=jXWA-2$B+G?9CV>lQgRjOQDl; zkh`abSqgK6TdGfmf`iqkH%DL0OrOsXNZ>t5gw?Y6NPu2Y_})Gshb#Lz2=m9?y|>WX z_ItGLQ813N?e}Qg>lhW=o=@8zU{q{-K5aW`Y{0e`QvPN@#J0~vEFO}#wq393(zZtc zCBEOAwjJ?r+x85VLF@cL!?f)=MqZxxUeLBSX=~eS0^GN2n6|xDxW%>)Dfl4UGBaY^ zj!u~N>TA5V886N8%~0D1x!2PKdsPZABlE}IJqMc)#(l4+iEo3Ade{d$-Rs%TJTML* zU(An|biht;6`CuPjv~yM!M%~cq}+Ut~N7nC_KK*J|^oaD=jrK-1BRe%2{qpFjf zq}jR(=wDd$Ll#|pl%nZ=$7`6{|5Hez{Rc|QOrtg@PgWv&S?8`|8MdQmDwtkYX~66R zlP@cr+RZfZJntd3h*Ml-ZGq$~0>(Q@NRj-w?BoZGRiXzWZ$OPk9!DhEpb@6@s7-0D z&&~@iXx-$3T5+?|GS_Emn7KY+lilU>Nv?|@2{1etVCW4ul@>6b!|-Z`q2xe-L5TMU zJfamY*PHz`JzlD#=k(@Wp~=R>wq}}3S@m*R$#K7;=Q@WP_gM@E{71Er$5E^8Wg&nl!Eh6H&s zc#;EE54!REBJm2TB6HE1ESAp1UECS{%5X$+b!qsp3fC#_8fYY)WW9=@m!B9EA#Qh@ zV(G@a3>G!(9qZ)}2hev~^a&O{;Ae^!ulc=3#A`m%2)*VXmhoG>CNw-n8*{sUKu--n z1HR-?jj&GihyBr7uuhCsFzdu517@8lPG#gcm8LNa+(GRtR$Znv%l*M$XKWI5mEl5P zmnHjW*nLnD0V+i0Ghu<3RV5^^+(}RgrZOb$}%FAmL`Df@5R+X1hC3 z5EG{WA&qf`jL08He6aMAm4eTo3cUEiAc^lnd`N=&G`n+0Aa(ro9}a){WeEu}lAkAZ zFM}@WDZ$@innvI`cHGXIf^SuXDR!lS3`pj$%4jZpC~*u5Go-NPuC{lj5c?;3D{%83j@&NUO=ze1FSX`8NI%v$U?A<@{vw*=}2P}dfH+GM@y(K3Jtk&TD(Dt*f5=@VKz+X z3Ip21D|`mi9JeVEU2l((O4qwe!F0WcR0+D?^%?mkk7}4Mj2z^7Exv4=Hi4zwStzM9 z)e(CjJ0WZVGOx{mU!rhMWV$Py{li{`Gn`w${lX7B$qvfK!g*fBVe2{BU*Rm#4}3Uv819seQzTnt zThzu;>8(rfmX|YBtFeqq>l@ZJ$ZXr)CLaI1@|XH!r=Rq+b$OfAgx4G}4 z-n`2AgK$ju6p717uG}>M8%q&7QFUXW;^HPL(0su*kPDW+aUB($9}IQED;_rVW~*- z5p64t?!XI!GFUNXlZ=lx%CPGGOo-)yx#VtzGo5#XLNpzC-#Y=4a9JiDam~nKMlM~D zkCjOsst#ll7lhd;or8Px$#NxT|5ay+H!87Hyjjt3{N%YBX1za6NKx9-BpYE_?Am$YRI-^PQ?LY?Z zFpA*$u0RH;`a2m0zos_TufW?-_MZDI;=2cw?gZ2g{V5#G;N&HpDrH;QY@ya6*mpZ;*>Ub^UrW(H? z%AJb1>0du_>&B!+!DK%Tu(iDx$%_vbzUOz3Xl+eJbCQ#ll;eok45{?9?05`~)WB1) z2s~R!>8v7gqDsUxE6&B(%%~;U?m6xkqUkbapC1+_VaE6RSu=hiW_${HF=jLzM;_^$ z@tW`?(-?ojOok-L(zN<(mXwyLtV|a^RGT z#`Rd#bnp!LJ}C4yL|6DNv=bt%sTQym3q&#&R9pf6Sb*u=%QbFDu-(u(R;=1GdquTr z?7`*35BQo-B>ExJ1>baOe5I`jwpSr912xDedL1M--+_X9*PTcXZ?$ykY+ zjToO2tFe`c_BCZKJ!@7g5pIjKh^m#C`90JSx1Zn3m5_FuZ3y$cd789Se66Bkn*skv z!!ogYMkDOmwrc|D*~=V_Q}UuDxiD>v<#PVxB}rs6AX7{iL&G)#lMA_8ELJ-z_@h-UE}86KxM_oUds z%EAPWcr(ssb<}6@lFqIHbOS&LV!@8Vz91v5)m{~v3W;~2OZdY;+a(+uYRE%m`TJwf*BVVc3dz@{gJhXC-$-EtC+JwU;;p{-g*_ z=8}~YOi|MvUo}+N`+48g1SdIO(Ht0lW6&slR6CiRVz{4Np%fg)_Z?triBM=QLG>N5 zQE5gq#jP6Qykn-%;3O{&B-P-<(Wr9W?*>J3l>5B^GJEb({G^hx_UzZN)Sd$xp+`Sr z`0087R4_g7cPf@kb=@W!t2n(-=E3ALnMw{<8k(j%N)Yx9nr0M6fJ#BzjyDu}-acE^ zlT#JV#On+iSuL(rFoYFv41_NUgdfU;lfTt4^LdL+PZ<9w!!~9;zE2|W4OMcr05?GN z@ljpc_Ge0i3~Ng^TCcUagAI0LHda3*J7k}vx-J{Jt^s2J#~o^rYqOE98*l)i1!tUb zq0bPk$|hKkOXDVQ*r7EP%amfYef`B9NW@{fSF3;U{3#DAuf~Z|^Edw_K9kzovNG_9 zsfl;gQ>SAxCp;4)b00%3m@o!MMO&HzFQz8Ui>bV22o(Pmj2-`V%yIZX@~ddo#c{{s z{|*DjWFN@PKiRE16A1o~Z5i9%Inj>#wCah;$H!NFfezYEC^KYIZbtajbeLR{?{!H(JwVeOeGo)uAmH+tk=>PMBqgf|K!!VG4 z?jcn67`m>AIrk9i`6rqo!hQ45AqeyhI?|VIUiE(QlszhIj4!L$vzeX3#ERxyb*C|UIij5&QYO~J!e0j> z{`cq_);DcB$!}ukl5@Y(eK%~iz7_0U*e1!XW2pE#FwY=?uIuroy2g#`8gY}}T|h_l z+CJN!XN%K-hAaS~pUH*HB<5q=yEdcsY}$mm+#(jb*Y+hqa>zvEJ9n7pE#0G-+=q~o zM<+px#g8=_=;Vcf%EI_!3Ta_;kzIxjkB7R^E$dE6b-~k&oMQiFmC~JQp`8@s@tk@<8%$`jVYa zjltv}3?$ztVs(_{ulpb^>Pzx_Gs%}8o)S1UUYE^sagb$~u!QmTlxP9B_fB>2rvfum z{23nFfqB|4mBeAp^%{<&0lrS8!UE6xnOe-H;&J`r;|4gzHw4)3({LHso-)c{BvtfU zKpIbfN`|Inw8PBUDf%eD8;Y75ib2Pml*u2pTB%`bHC{-dRcS^}K&yrTTeF6#6>l-H z?nA4Bw2}OCc*v;+Oy7ZW*dSq%ou>pW+1-X9&s(O+IYmEFG#%2G)#>RrhICS@?xrKl~r7Z1*#+U!2)9bj{b?9;daX&w?s~MyV>!S{Tn&S?a}_Y%D$TCbn3{l!{wd-`?15n zIcnIb#;8TD=Fk7>`oBGDI2Eb<$D@YuUF7Y^m=;taHIHNDxUFXKVpmz2^{r~D2{fsSKz|$UItj&{foL@xn;$88(!?&K%5BGT!_@)fi86<`cmH%*jzCELFAC4EnJfk03bUymFeE*Do zP*U5DrV3&HxVszBS$7upp=AF#2FIO6#4r(Y6o&r%9;__E97@nEfV%!@N{Z~xg9TV| zGbg{3SbUH7PI5ghDW_fKFj5i&MSIE>;R+!6Rt0~X6R)bIf68j5hHBcio*F`WEe63#n&JpX*CAT8iVq&SN1lN=cJYhPBzBhA zu&(Q0rlcgTb~7}>WJr$h=4QxiD~~cu_ViUw#_Yl5)lBDrCX&e(4;GkgNs<4ET8s79 zQ0vza^|Q5>kikoAwi+4Til}Dm_^fQL(`*fz+J3fv$Z{I_-)AfMDo0xV)#pT_YM>(5@N^w^eKSddEM7HG&jpq^XKF_7m7JO*`$)JwK*uXM#fots#7AbOn%cr z1|@JdUL3i`rO-!?#jjp|vrG|9KJg5o7JtR3}t?*Sf9;CI6?7n;$%F zEDXzI3agr0SD?Cl`}5`F(a>eh5#?!feZKrrYR2nu@-9KRB2MCi-%1ZBA_ad2Dq^lS zMmoL#J}3G(oFvkT;c!InHAV^zjN~!wMErY=k^CP45Rb^( zWu)_iNTe{5eXlXn^%6kKqSrCCB8JN&=00Pjl(BvhGdXc0-Ofa`BH}+19O+KLAOPz0 zt(Hg+LWT&3j%CXT8HU%I_dt=nE2w>ZEkGSij`(7=gSUB*cCQaWkw1G*{rrW~r`KR` zkw3e-dfI#&b@OMXmrTJ$bb}2!9n8_6fQ0^sqDoRi-Ms3c1dUn=8VxxK=Gi1Z_$0C} zt)3TPuARl(&^~i*-BiXG&aR$4b>5P?1$b4!msCLab3(uSC-UcA0Z|?67Z?a5$TATH zEVT8@*R5;98R#pX0m9|4j%H!`iaj9dw6O&vj_(tUC*V7;+_Vy&!*lpp!DeB&ZWs*9 zSFXg}Ujym5s$m@mjtgj1lLY;uUN)@iA;59>2|nh<^ih>tQ}87&mJpV`LXs5Y=!16Lwx;mWVeaYpCf9n9-T0hUm@E!S?$Ml#?hen+6U@~D`Xt`zp({UFL zpeF8ufw^2oOugb*mF1wbE^gEa>&ht_W?gv`ib!2)^KEUeE^iMoToPdD291Q_iU30^ zK<4h{WdXM9HOwkDQP`x4-Kk)|iXDNhc1tTXAKJ2D#EIw@*rk()UhM(QC2TC*t0AwW zIS0Fh;YxO5?$PXp&rkJXRzZW?vUZo{l^_Zya`81?PuGbBw3dxXvGFGU6Vo-{=#fN{Y(57 z2R|G5VT6g7KY>`ukxEG~=NuEp^imW1Io7*^QEAXmhO3*^OCRCFw2pTO$NcFsY^h-Aubt;7xR^OFej&q9{8lDh@@atiX3PAZU+RYW z^9)0Av@XS*N>;mQm}Y)iwPRw*08JkaGh<&G8f2`vUx4Ir4bx)$`k@r&06zn!a=0^` z;&g_|8OdHGa->nF91iVHa+|=MJPYu*;UvQd?0XSnLpM=jX#sXC18a->&M!&N;m~GK z3?ochfZGr&xn3#R0^Dzu;&YeX&Qcw0KL;3U#4hkQbi@fuvoJW-WgGe?a%iT-mh=rJwO&dyC6$oa!?hD! zCH0yqzT$bFh%n7l$yP=1vfk}Rwsamiw1|cYhbK!e2v9tCFa<7L{ZuJ#gNzRX6yifA zFDUk5U?ZKx4oJZ%`9q*al^Hl4|7``+@kc8;rv4RuHE+@%A8Iq&g10<0%v!KX7*Gp> z?He6)Mu1^yfZ;mJusGoPwB9-;lH|5pZWP9O0q!>}cQ83_QlB4SxJkn-z2ZXkgI#`d z>f}c{#kXXbDjw0WB)>0%D0xN0%SW*lGgfQQY+joCU2v7@C#oO73qzTZcGY-> z(}ptL>ty0*+c+MnZeH88MaO9M_%fMa$TzwNRNMea;E%g|DFmyh-zc8`=gla_{qs|T zA0fYSA*u+TDRYV2r6Y6~lzglt?C0` zo()W%w_o+hW0_Xj^HPx!FQ5=7*pp56Z}cR0V*88RdAhhgA!~7aLiVAl=*jK`T}#tH zvAyo3JM$ce|2x!7FekRn@Aw>d0uE^{U*(wJ(Wl%Ah{{Tw{Tq7>`WW(hyvN*#v!fg8 z6#$J4Ml^2DIqQy7yP|P3GKs^nOat%!J?c(q+K9$We#L9t3G1308cuM`@AwQ+V3i|E z#gA|&tX$XB+~Ans@xxu`N!UB=tU~+nU!4p$Clmh7h5Ygbrm9@3m2F`un*RUAW8weX z%k$r|9v>QTFESYBwx%B3a7$}o=G^SNyCZs5!{DFag7GC5J65&wMuo7HZN>UL*Tu~$ zw*k6~V^(f=%DoXpj`Q4cEXWr#1v!3v`C-FG4I5rQbbU+fhK5ON8aCk5cqy! zNn6K_89HWk`Or1xL+6YvAKKiqYSNkwtza6udPCFDCOphBboD0eFAbG%;x%jnd~;)S z16JxmBAvi%~z z_?%#fyC_&3$A(YjND&o^p_kdzQr^0uxp55+OP7-@9FFLp3};}kD6);hL%LTK`R-1{ zB5|r8iLYm}Ir~P?m-@@`f8a!BR(g^6CuGY#bQpb$P=BK*91gF>iWk(&-c^dkdt<;C zi&G!Iw&fH?m&^wwuVph%*spY=OD}>PiEfbi(JhF_9bw>?3FEO2X9VbD3F3twk4LU_ zVg-zcopA8oY!s9l%sd@#pV*G~qtaq$*}aMnILgLl_bOg-8{!?}kvQq{Yv;_K;pCON zOd)?J-UhC%cJeN8pM^RJ61bQH7d(Q1(=q1>ZV_|oSl~PTizm1X@$7Z=?1i(OFzNH1 z&|?uW;B{nuf}26}1UEx`f?NKMc0B&&6WsC_PjK@upWxkeK{a)!MybB`O~ZCiAMaq?Sgr8YBPytqiguN*?Dtj&%vjCU7K_^ z$&`h)N202zuGu(wEqmU=x&^31?GljLmVMZlRlj}PbK zay~wsi{`tx{>O*gL)u4iBe_T>8u++yG#5|F0embMPyXyL3&(RwC?cCAFPDT;G7pk> z$VF2^2AzKpI{5M7gOK2rj}Kdf2+R8Ta2NGr9OT4TZ-QTF?2>rZ{RPI%UH^z*iPzn0 z(1bf(zra#-;%$kzNsM&(@!`aK?j1mel35=gPP{KvVGH%Y7@PRJAR-n~XFooi_*f9p zWbX0Q#HWIYCH*r7i7zC{I3Qq`5m@3&0d=5OI{r$0BcMbw`*XyJ5Wb*_4k+n=jyMq! zNT+1>=ZF(=0T(9Q`5bW~UvQmq*0B)>d{@-tvf#m=BTjS;U4sQ%W5XihP#boa2y9rL z^Eu)~xnM$F-=^IwCE_J>K1ZAw5~9gr+#35i;>4js3hUX=5hq3oB$mwn9C2cdfa6K? zIpRbWzA}wt1zmS1klv&a2Rx;It}twB*u*aZ2VJ8gQ62g*9KmF3hKSQ_)k*}}61@VS zBTmc_44mYk7gG}R1m%gDtvT?n`XT|_JZ3&eoLC|VIFO%6#<`9a9IW8uGXAw(aBw3Z zhnK(w7VkQUj=fg0RcI}GDaVlTQIJMiHEhv0S|j1f=hjddcI7vl8Zh+itS=EKb_q4iIW_nVPV*(=#KnS)By+w*oVZNjQR9qPN+g!_zeJq4Mj)t$ zz6BE3iMGBCZw%V-7T<R4Nl_w0x5K&tT~bRcc=l! z_(k1d|HK{MWdIa2T<&`Rh!$eNysBYE>l(-VlvP4wSexC7ZD8*+nHS_WU`B|~%{6Xp zaJ+wh2eYGip4=Yc2h_YTBLEco0PJqBJi+n4dJD;yCprJ;x5hx{x+JW~fRr-il5|{h zZBxs}b**daSFQkYM2J&Cppr+0ye_$V-AUXFwSx%oB!p-2K^SE$5XQC1)vNd>72Y*i zxx(=Z-4U3ZZX^(o4mIIrApv)GPXKr;!7EqPV>+>^UN)k@i5}@qE$;40fM`#QhdfzY=psZ;0@{=L7NW)yCD0Ec~H@ z`Kwzmg=>Tr>Ipac&WZ(P^V0)qvLV3Z)SOfU^q*_$9S9EL7>8_~q0UKhAqH-?va zHEz$&aDU@0wUQ%#iFvi?G)qhtPx3Q<-W>M@I#?3jPrW|i?#-2+vJ^^h!c`9Qs=GH& zfZdX~QcQP+c^q%P`wE!Lt*z``XK#VfR&;GZMer6%q%w(FDD%C@y%VYp=_+|xEO{87 zY{n@oR9tm~CGI{LJ7vWN+A;5F8Tn01E^ldBj^h-NcZ}p_ak8lyOTk!Z_l|Qvg2x}@ z6xGlyPka2xY&V97dut?ZHA|zKW#zi%m?N*kcigm>LNOdK8pMr~>x`kPj^nM@EH7`x zac6VGr2d44O&c24)vrSG4VxTqgJ^`RXf1G9alGO+JuHM%&L<(Bzz$j z{e2A%$J*JS9!;Gy ztFE@1Vh_fd1%q~`TQI@2dK%&2>DJWr?5WkYwUBr4ObZ`cg1>|h(jikY{`|(*&$nyT z?`9jDoA7MS$`i7`#-2!A8GZseOzL%{#8r}Sr|S^(iHWNv5>A@y22SFK;&pK+Uq`;a z&CnyP#vN+}mG|UyGyritVB_5Ypha^|Yc+o5IlqoA;&F4hTLO)Nxkvfw!d3sSIrOB08 z?Oy?VIEh!p0_Dj}pO$zn%yp{@G_Z2zC-Fx3dBlfzoyNi4pG3mAWR68K8w$UN>`X*{ z*^npbIiCSwR=sR3Ub%eZaAL!v>G@d1sY_3(sjXRni%7Y+ znR6D@)h?XjxSh4STc(+)+FFaVky;Jrqbe^*Pn}tRWc9q+)wT80=GCAA;t;W43)VHQ zsb7ble4Q%SDZ;^kRiJjxjQZN@Mc|x0XLfaa@EqsQFdUVhH@gNagud@*P&Kos&&l|G z20pEN3Njh?z0GvmnUP9jbgT}_MdFL_y9Y-nWo#SExB^`~D}!xV{7nPRq3L?NZfNPe-MPqTfZOio`j>#HY>hniOB8 zbPBy$Bhew}VdEQJ)og|xy!x^g0}+XEw!mRx9OKJIe0%}hr!DpP#!w%Qh4OUpIvhkBLxFx9EvsE45w32ISzygTIx~+4&jol>%@(5op{Ho91!KN#K zd(uf`P~#7rrZoP)M{BgS__Lo8fQIq?>~H!gHB2szti?C?+z;7XI+%QMNEJu0sy^ka~f z`y+Pxx#OKB#HhUNlY*FG92i?PYJt`##S*V_iV#R0ljJPyR^vRCX~3e++T!&_7V zA2ras6R5Sw5Jt(FF|y-T31TB=6}ViA*S!7Vv*R5psI4N-2L~4~yraEmA$2FD@?z>* ztZO)4qxT+Q=RhFUFqU_`Q#=}US5h|AdG8VR69u@#OO)d)!Ab6iXP{?zg8|)>%o>pU zQ^ku!t()LWoIB)>+OHMtT{^SK#ojB}hrkOJnojc7d&HZF6!#{ZTUTKB)Ss+5-Y>l= zK9n-8v+l54T-jf*zgK6-9=3&8s=*k{tlPRg)H zm>@!(+eQ0 z1Q~Zt6=(e^<3tiwoRv=M{p}W5#t<-kJUSA805v@lztU1YODg^XkW)1*jUm#5^~Qq# zfUrnpZ7E~LFXI@h>;`r!k@))-&1w=re+{gq=>U|7U|lgZ926QkLBe5{ur-@dqM9HR zkHn9%l&m|Vs!i-Pi(%C<80r5a@vAI`?w`TPU;`rWw`kS`gXU-znBQ3p-QHl>f*Ji) z_}?rID}kXAGby?YpgriVl6}Y=fp8?w9;pYt&Nk6A5f)R?=cG`}*pHWS0mLf0#L~2p zh6$801aW=DHm4%eTbg8!0#Rig_y5G*mjLa@y_xOQ}0PJ!Qli5jd1(Y!v0d{tx6f@*!EZjXt?(4qX zJy~+E_2pidk^6TLliA2+OypwGm10c6nU1^3OZLr_T$3q|Olee_(pV1~QyP_l(x?oS zMx~U-u)+0MrflKihtObQJygnPNQj41oZ<4&q1~Zz+?PCVU)a+v=aU3K?(UWSa4+CE z8uew5;g7cBDRk}(ATFmD=8kHV&5*`bs0puNMG1C32}8{{7o+Dlp1-GA9weD1jh~n>J(6q9fQFA3`{}bZwL$qPYNeowLt|H9*eVk<_(nzJlyJpC*W`^F1tKACO7&B|I%>pT!z0=}_J0RJ2WV`~vO z<`f7$oXyNLN*c4NJQCUl^3*`!ob(SBTZT+r3@|bhYAJW7SgwJ9Pt9AD66TST)49CS zh%DmM6wWlsniSE76-NoFpV%%hCsc&LLB-w#L|;Bfk{wm5ky0CcLWL`+VZ&@?YqoL*D1jq5HuSC z98L!X?t-SbDw1V?o{w~VA6tq}u|3u=?B7XQw?~ z_~Y(=7xJnlOY1%9@#kfU2<}O^J4MEUgJcY@v@&+KD?_$0F!B(jvp6M5XH+=eXEzkM zh8)a=sjit%uj~^o3J(%wXdmjSVFmMwBFEFqhf$-UAjJ7DB z8D;QVABGj-w*5{NZQ>8g@kuu&!2X;3xKr~^gYeY7z>R$rzs5k!*k2-W4COtoKX*~Vc-~uCGIm%Q*CBAkNF~MH%&J)$zQV}Ea}R0+cC_e^@o53b6-_Pa zKuHIwy84&20EzkR{mCA=5(Ckk+RnvVE0;}%O2>DGz1i?P*J@0vyiUOA(T<$;AR?O*n9QE}&$5zbgd7NY}W?U-fj66=X z+7S0ErU5+-(6E`NX4d4Hnz^>>eNBqZ1WhC3I1cCLW=5=tErI6cq0PhL>IcojHsY)X zs?s_$>pCVSD*wu8jy9zMW5N*^v&~p96yCW|&2)p(lYa+sbA_x)#&{FH>o|vTiPYUF z@iP&x<*cj~f^c0XK1D=Nei7D5Yij%Hpr?c`f_`Ja1pHy}jQtRSPUqouLt4nPkJj(ABFtFHK@Oy6b)UBiX^{sQN_9+Did6a?F6+Y6caN98fW`-`i6yXnDT0$d{N0E3pC0-Gb*b^8kLy6b7Be80d0_jyC zbcfT$N23%oHbXO!=Y6hDsZL0%$}F_liL$87@V$9C){pt@l6D zX}e@JQ>Q81ZBm4nH;%G)*d?QxCy~<;hcoAG9&x?TM|@Pi#5r2{4dT4Cd9lcwaRFj7 z54yx-^?m?xvC|H);_(@4rxyY_n*kJaH&SwENhEh`ZSJZ*RE7h_m9<{Sn;rAnSFUSu zuqx{uOiPSV;zXMeKFA0gm$$6N@I*8&JkFGi@4LGX84U|a9&YitC-@EWU_9d%vBf_3STi!0DFRK?JS*ux#_#9c?2#2}45o%kEl?BI*gt;2>LtyFGQIY;L z#H4)YL1>=0Ov|TEo>VOfH)`VPnHunp!&?Zjk7-R%YN5?>C%sIuT*mp*$2#c~72XM4 zNhDynoT|$eZfdyoYn!-~{5iJdO_5SPDbnsvl=;s!Twr(J7;lVZZ;vK)k#D@~##rNx z5#trKS>ufr6B7-zOj;a zK&2e%oAZHja7gZ#1IzH)u-&9!DWL6MA}!Y!z|=&SnUX$41?&L}o8x*RslEg;8KNxn zxaQV~_>>;XLVGwO*L7N_u+P2FOlL?lI--Ec+#%I8YC)%=VW3887o)V=db0L3$YFfv# zDD^%Zj{z9Nv&RD2@p6n_mMg^oxCUJ}UI%Vjm%LdqXm91m?cj6ZK><_?Q1(Bn331+_o%%i|eIZlPrZ>mnvNY>D@<~s_7LFDHsnAzm2pXBP0 zE1-dB-j+#l9i_57q%%_ z@RV}hsL9H3nd{h9?<>LcUIG2EXiT#=Ftu8`k!jBM@qNM`2m%mi!Jx>K|DGayO81*QdW+fsuNU>Y3MoD z%#5ULVq$~mtqo9iW0h%~`0d=#mL`lzxZ*u#H=xh07LWG6k({jPx%3rpADA#0uYbR#V(|{g_M;er|LPC(_YqWVv@Db16jLH znWpAu%?=pkKEC_7bW8h{c(>mcbxqm6>~ZPK?uN>f%(lDZJ`pB*{P*F~(p)_$`(%$X zZXd^Yp9*uIyu($PEy!yB&t(t(dx*1%+9%1rfS5Ewl@N!|4yoZ}5%~C(fZ@ll?JtK< znGEZHR_-`Q?S^x0QUX?cjDU}iVvK}GCjGxlEiMoQyu%E^!>yD6_A z;G{<>8Lj=QksGW}R!K2<={ISxkgHa?*aH4Twb_mxh!qOw_C%M%ZM#I*1oCP{&IZ$A z7CA(a@I!pS-C1zGlGIo<(y|$0&X+43xlF&Qw9NTQ0r;?0DN&L+dceTHHAj6lM_3#f zE^W~mWoBFVY(VH_g>y9Uj>6Hnrl%{M&EeM>c-7hfTpMS!C|pC8nF>8Xh6?#kv>U=f zFVz`q{g%d-we_1D@r(+$AskuK-Kk=KDmj$qCvAICH^NEF*C^FV<{bl`mBZZ=j!nn@ z08o9)AOOA$;F;*GF|_a^>{Izgu~Dn>u`+OmBW(Kq0TR=aM8ByrH=$lPK2kkO!#Ij7MubMtFVH zYumG<>aR+5>~R4w(iX!SJqln}knMmsDhF%ykpcMm3TKVJ(7=N=+Ug-~)J6wp#g8oap;tta zOU2&5CM9sncuHlTV#;5ZAF_m`{D#h5n_>GZi_NTBWU)PD*{UW6*qFO-O{q}TRh!+V zIo(N{Er`sYhQgrD_Q9x5`dKZrM%0KCfHIPu^y>N%PZ{`v_Z0qx!Z1Xe@}a`mgr>jH2;0p=;A2!7L{+X9 zhaE<8Z0Dr6YerZ|#~bQkL0bowg7yb@>B|DyKV8!}71DmHa4P-%0Q@P1(~S2hoSDyC zW6GMDe>y;4rf|x6GXq~TTH!R}HwGTta@US%d~KPNUZ+TotV&S*w5+Q3DtsE?3NuXu z>!>sh2`9=rZ@UC;&YGj8_TZ=cfYk0f^|2#d+Kx>{)l9VVGV6Olnu-tLHRia>gOM9R z)q0(2ntv?(Um+&Lkt4vC=k2n!`7Ze0gEP<~OY62b!sRuL`_hjEd^!d^v=0`J<(I^J7X+)%Ex%#^DuL1Oi2dm73cmB z2}j*2LQ8?+&8J)vcB*y-*rmOf`ktlkeygsNJ~@!f5B`V5d>34Bk#fagN|vgbU!dkx z4arLV+bz~h71sd*%S61P)QPfKtv4Ke4A>1v+0pLNbfB{QxVyX6SZ@eNIq;n6z)kpShSz1+$ZTblDv! z3LQ{h%sw?U6-U_243x|?Lgf+f<-_YMgkvA#9CZwm*uWb!LuAYI>NG=UATl9ZcYI33 zrpq-z&wAtF3|c6HGDW7$oQ)boZ=d>NuK% z)6@Lc?oP>AxypFdH_X|!)-XH8Fy|xd#xSP|$Ap`J$6-BO4CNPle0c`@dtjweyc}XM zZ?{$9XibNP=>imV4jRVNiD703Jq0a+9fGV?8MMzJBSZFx&Q&<=GbIB*<`#uF7+9bd zp#?*1u`}h#0BhAtfe3AiT4=f!=0zHla-9D}*fu7CBmVA9Vx0XdV!dz9#j~tAZxVB! zcr(l?n+`Y2b5~y=E(RkZCbd!1{-!&wGlffoO#~{(V3tk{))+Jx+m12H3?|Jrc24HX z&WRjgwHe5|kKjHjS*TOqWBe@q)6c?_l7+>$sLDiO7;9DD7Et-UgH^V4qO#xgFWr-^ zD{3^?eyxVtcO%@lM8&(5Wbh*YzcB7+B$MwlE}8sBB%FSSW|EBP zu52c^s$^#JPM~r!Y3U@BXJ=>9S$c~yx0}11LT&dBi+hNiV|rfYZ1J;qIaY_wsO%6q zMAh?7WJkKLUc&JZ;!R8Dp*on$Agb3!MybkK(O3QOAqCM4}a z4<}0Pth2Uz`^HU+mUSvHldmRp<|bch$=Ce5Y`&%l$KMc_e31}+j?LGpDv9}81XNDG zEM5Egy5(E)m6Z?k0zu9_A$O%IpM&x-7W+3QA1fsv=iY7eu}V1l-J|&+A&vsse0&wi z$00!FNqYCE#{SB1hi4qi-F?GR&>Q19o*Tn~$r$60LRYg| zvp2@on?vqJTyB}V2C#+zIrsHgjOV`YVO&-d9*=RsqxXFn_~ScLxVCCie?n5n-rW;v zNtk1bp9yRiNTqylL&7+f5iu=)9Ud^KZ`~m8Tet(_!#A0X3Rv0$Nv$wG@5BH?uLjo3 zH9xl?o>JuDpY*}n!$w0H7X{GP9f+-)kBM=#FQzp211MCha;ZLyU1X`Q@ToTDQhgMA z$Wr};RB{r1k5cU~Kx$va-XaCpPG19stetjvfTUEe@Wd2?_}dYrpT!~zRI#B#!K2Y9 zC`F1CCGmlz;GBL5DGn#a^GeZ6B!Q|dKFd<=AXR#cmOfABtpf_a7C4!gK1>`GTNJs& zB2QH$O>vn)qKo%U@iRqV0rdR`p%=WY=wGPVX4w8+gPZTbTD}`FOIB?vSAxf7joQp0OD||b0QXYWc z8lbNTz@Jd~4$#}W%SD=36i$mwRC?3ebIn|q;Qw#--aJ04>i!!)_uiSw zoh&d3dk_eS5Rhd8kxiBa5+EiaF#!bu69@sK2uMK04P2^Jt%cSFTk2A^T36K8U7>2- zTesS}wPLF+R$H;|t;_HI{+x5}+?j;hKF{;}KL0%Pddb3Dn_tYu+rSDHjH&V2rOmIOr zve3WS%DInn$|oBcESaZ($}p1ENSbu2r8XKa*5r3ISGc%W88mByj~Sr!O{s#jIV1N_ zi%zuzn=NwB?1=t2r19w*jdcynTkpT7sodM0u8mXPbG1NYYVj+Kuw5w@-mEYSp2J}Cr`A0u{9^=;juoHK>zACcwrS0}wiRu-Aux*<3gVva>YC*SL`KTWDd*%Z?%iXO)Ku2t zf-~WINvhZ=9`%2Wc#JL@VmlF9vaxOTvNao19vZwE5mGd#93L=$@ZAP?Cg^zRZv=zt zL)r`-sptpKsnXfAEq&=rxi}5P*DZ8g*5RMuyqPU32W5b7-mI3Zv99H}>(R?v^vziF zmw3o&c>py0=2a|{r;+3*vD;aO{qfe-Cn@unSmD57+?qBeKZ#?UWqjE{yK&U-{?chZ zkhA}8*4cl{ZAgaS{NXJFP#^fso43r|`K9ZAxwV`4g|oCj^1!e6wzK?%))VMPPuc&1 ziA(Uis3w_~Y06 zjkEM(VEOf4a$24NjNh(vm);K$zqyGl^;euqMAU+Q=;obSbLJJz_#bg;pK`bHUpTf` z8+8L$2k91GI0zLl<88!|gI@yj-@Lup&u~UBuk_W<=p)s_+o>~pS39G}U*L>B{Nm!s zsqZ6M`{Lrr`IFFBMEs%n{jcAT5bgPoNw9!GaCDh8LVTe~%8y z2dl)z`FpgunW6%Z_OA74@1}dSkN8FCq+(g@z4%0|AIs)DjeP6SK6ezvNK_ou$MP7D zD52LL@UxCNE5wksu*Nco2mGu>WbjqokN8wS+jyS$FLKD1L)Z-nbq&Rh|DTZeuS5t7|6XcfDBe&>=XPpP2vk3NL1Wd7@*2G9Ev5GCdDGRfP+U9< z8pne`4G*Ilo2;VnUtL>YKBuZ~j!LSo#&q^7J#Lz<1) zR1;DK-tV0uSbXG{Vu|9t;XJ^mmVX%|Z%M={F#f{5ea_23x&>+e!o7EeDq^95OK0zW zK}0Pg@aK#TWhN3U$n+QPeIkggg1}$6_qinL17iJ!dtV4Bn_5-q_qBLm3n;fB-Cwxp zx=g1_LEtakiwdM`LAt+i&lhl_fUcKkguN`o?NN^4@&g}xsV0>27ggkSbN?CGu!nFM z8x~3gHmuC>7w#1a#?9wuls8NwUO|SxaBqZ5lf$@Gbd}0J*c&aRuwFweCQI!rl{Z!( zSq16-!o6_<_VX7ofl2Om2ukEnX2DKzIWF}M@{~G?3ssC_uhK2RY(`g%St872szxHn zlxP+57Vgyv234fop2RhpgFUZ7P@Wjs8Uyw{O29UUDR1H40zshq1c{`o)?&fI1_3Tr zyOszJl_xZ8&Y#RV_UJZEzRU zF6FfA$r4rtJk&|K3Q^vvBFcxT7K&o+u%h%?Jst-P{EZcRXS;`EHl|JeEm78(`h1Bv z`7biD??`Qcbx}`)+`)$1gea0<#q51wBGG~jm*C!|0*~qXcDY2d3Idnlxaq{kf|eF! z)VoHMGKRW7Y^WOpL-C!%(SFFH%^lv|9yAd;%ffvIIpS;JaFRuZsvz<lSj3lyN42wi_n%+)02Q5)vZ&gX z`^9De5&=Lv)^xu-AG7YFf|Rp+*KtT#oB|n2*CFYIg0QoDH!8$sVW1(833+`%2WR(g zuJFw7fH91D!nm>^?Cjo6I4+c0OJK-5tefvl2KZ!xTf)xn-2z!wY$?!>(;CS=MDkV* z%yf3|_I7B*Z3dg>?A|>{ICo^=P<56mx1aMKbhygkQqJz(B4OIYb}TJLUKHpKb~tN( zq9AZ~?+zDxJXc_y-Mfc6RXyRo#RA0Hy*onq_65Me*}XebFz*FrAkOaHq)6T0Gv%|@ zKGBT2FjkPt=_&g`?%@(mII8;)_JzB>k*III7;bi}oZ0!4S#S65T%j$NQCAPA z<{?VtVxHiJ6=*Ln?orNb&~ya+S7SJF=S!ZF1=bUgyad5r;G72Qm)T@OgO$5b)-e?Y zf%kiNk>qZEf%P@-9_w6=Ca_3#zn*4#%A1SydNG`IS4iTwG9sJ=fzzuDxq;2_xJ7^QE5c5?$fr=OTA~k#RaLAnO;ZQm!Jg;Xbl$k z_ranfs#zyG-P0s9(ItitfcDd~2{}nLfAa=&FWFc-?KpJI|(@wR_l$ zcCd^GDJeLZRnDJVIj4~e++aly>;XjtYkUx4tv0v3Y7Sn+g-$pUn92C)XN&jxN1D5* zG;Fj!`g@yoxwy&}AN?7SbRYfcNb93N9h!0le_AFY@X?=+&_4RpVb)#orgU)NOaA0^ zxc1SX4omaVpN_IV`ZJ+vKKj#=9?89wMNcj)fKFT}7jgRt< zh`>jAN0jza-VttnlxLgmkxU=uUTM}qD2Hu4{Py9XQpmbd_%wgGL!~k}L!*#ambF-T zTgclU@CsYRzZPS7#ODZ}#h%GH6L)KG2B9y`#N9azD_>3?b%e_a4#Qb;SipfsoQcN= zajfyJGx7Kk(tt7KOguhR#(C@khMbAVhus0f9A>F2x>=ceI4a9J6VIN(0mp|k@$3rH zC_R&CSJ{;`K*V2XuBBwpWIP54#YB8gQX)P_i*(1_s@^@{Ij9%L4X&0_SNzdwUm!gg z-!i~n`aQRMR=*%?dd)aQdPj|a|@6GP=*?Op_$WP!f;^i7592HwUKy^_`IWi$dgz0VN&;O?`=S@D(Lhg9rTXWXt6DFJw|1qVzaXWVYz2ov1Lniq1$?H&?260G}80}46g zc1K6p*gorN>Uald+-|85U^*P6mvYAKP7MoYDoRQv&uGslR(36VZ*Hx_&`!XlBarH~E3@EkPJ!eh{eL4Tb^vzdg@%$}ur z)Y7o6Xc~5bT27d7pCuffPAE~6AQO-H`5+Lj*mgu!o7mwN!=|G#GJZt-c^1R!pTfwf z3Xy9pnk_-2c?1N^MHa(quQBYwwEjl;4VH$DK+}ks4Eh;B`>?i3_963Kgd_6$kv^<- zwx4zpmVB|!Nud^U94zE)#VXp((o~a%2^2B}aXcT3_~Q}jryIB341)^~=M;eZa}UyK zVi1JfVjLiSci?;4y@*o;?*R}L(f72D_uql;+r5ZIHIUv$-EA_F7+_{DEo(P4;q6$f zT1&>^jR@R4@VfSg0K9JOYHlkGaqx2wHt|lF_mj7%lx#%| z0EL+k3^qyV@gUgG^4^Lu-`=^PJcJ7s061etxV=SB^}V-atYkwLb6upvhsc5p5thu5 zUuuLDP&gU%F}(E}8Y;Yh>eN06Qv0W*re*(2(m7<+lGQ74H`@DGjJYyN{VSBzzeI={ z`VlPRjPjVS!#6Y>B2Ryf^4Nk8!AeCrqvg#FL$YY zVNJq3#-ls>V(t?;V?FM}4Z}6+Qehn)hseu-rVgk8q>T7v&e;tBF=F?)ik^q?p}G?oe^Q#J=ldFOH7&Ilz4E}gLKA=jbhhin0LlISS zNjMhqxmg_XxgkDAXD)344`+PNF2k@%CyX3=1Mvvn-)PSh9ESVdi;O&D$Vv^_$55{n z`CcpYzwd#h zk;@P(VTC*Fe#GE4+X%7ah0NcyI}lSArzHx;GolY6onzbuy7fak!Aq-DO$ z%!l-g&MRc-FIIh(!GXxd>k<$JelJ0&^alw@3B!DEXi|INVc)yx z>=n3V`c39}isbo^T)7OChVmyilz}EcZ&3}M;agCg`8a$EkBFRiNPT#*^!t@E z20*5?b`nbNvEj?yPJWd1txVqOJJ{yFmEDpaHkQi>BDr6l%KZv5=-f+C>)S?sr||I4 zIgYee-{U1>ZLmu6DpopyLCL_ONSmr?Eg2InyQnC&n!0YuMrj`$adhKV&WBRQiA`nT z!c-c49zV{`*GJ+xS1H5~r9Rf7>P{0EyB|qCIQv1gZ0TA*5(xtzLR<<`$9FR>b@*e4 zvOYvFS#}yT^{Le9iN8Saijw_IxXanQ{sUyVm(q2*s4$()^eCg(RjgfKI>SMcbOtFk z_+bP-2Emd?5O@cH?T;exdjyXBB?8YQF!eEb)gog>9ys1atfChJm!f7=3`F2w1S&@& z;BDWsxnd#$!=J!2uMG%1drFz;P+5rx9xya2&B6x1S~db}nuUPRUV)$K7vkseQ#JWE zpq;%=!=cdN3BWf%Uh+W%s-HyQ4g{t>g~0U)%zPRF@$!Sf3^G={2=IM~RlJVCS;j21La!#GDt9tF4B7 z6GoC9Ag+;{)~a^bnL1H+*aoK5ti9lUU>Nw9BgygLpME|98&B7?Nlc-gdgpo&Bp(C( z1P~OHhf7mCqwaCnXiHBXA4A6@NkCPYis7z&XD~ zak*#$m3jDyd;7agSNv4}+@u~yeOWhDYkN9$J~Hk-V;;_|5mz`hycMsiKM&FWB%Quz zj+ROK(;#9&bmI*k?z>knJwxa4JFv#)MMa^=HtsM`n z+5MqZCTRM|#%*4V36-QJq^i4ZNohpa_9&wR(27!PttD`A);Ua7Ums$B@SEB9WgEl5 z1%SI*)lkY9GzlYx8T`Ox(3n2&K&Dh@rW7whO$jSLCM}bqct*;qI$`*CpeU*|KX2t$ zk2LTb0dEudk&%thIWXRQ;%irg(*1@so2~B5EqK8_!&Dlk%H}|5^}VL;F#GQrRZRBZ zw<5wd?^M%}Nq^9AEvS>4x}G(UHPtqJ*1Fl6KBJ6nU!baULkcz<*&CqaPy?q~&JZ{q z!O!$kR!t1Z7Ndg zH#Q@9rHZPKhl*8UxDRJh*9x0ORr^th_TSJU<5fl@Ho@sys_Pf4YGqm>OX6Fdrj|4# zrWE-O+cMF(qZ_xn%xv6<;9z&96~V037Ka*0SUuf1(gZ&d63mjqLW|2KnQU@eB-6M8 z75yW^b7Zw+cE4KqYVWi~PqsYbv-a#VNP*KJ`Nb%@^Tg4ZesI0-WV@SsU$ZM4jTUcu~v zKw+pvOsR$+8Df-|w1OkO_D4|%=erwM!SZQ4D)JaWc-c5iELnC=86}}^>5sFsThdy7 zm{@)#l0r$)z1nb>$e#fqGvHx}z)OIsa<#`9QLLR%DBKfS8mX3_o7%%_!>4zp+EA8M zn}bxe55i&P54dOVlt~`8nS?(L^02?e=AlgTpkB4p`*N4l`zFNeWO_ft<&vCJ(neW{ zRk-Bk9J^GO50x(0F%OYm>f207(cAvT8LW-7BsTpuW01rc8l>46WbX4uubz;|654=Y z(_1+cVG8NwJ}^Y=vC0jh>9PK4n;8o9Boxt?hLqjHf`C-b?fI=T$@%8AblAsnK423n zHB?E=DX$gEBc&e{8V>)bBZ;Yoh~2{jM%;RIxhEUAE?YZCvpJPwEwlYAXG{}Otg@#H zi%7BJ$+6u~k`|Kq!78c{4i|IBLl@^nUA`vq*^Vw?+@-{3jP4yyl=6KPB{0qK<1$h! zE?KUV2iXpO-4^^hDfl&r>w;fz3Vw?z_zkAu_n)B){v;{*Uz1)6exoV)_oU!YmRQ5@ zO~F$i+{Lo<^w&bx8alQ^Yp`@;wy$gp34mFW~8^wz#lzOdU_VD6Fkchvl6`{3`a_}mLZi| zod&HgG(@aK4lJX!QngPRczPvDvqokm(tUvpA>0@a7jf#$&H15}#$F@-DP2o2h_oJN ztH}>to@e|9`#!?aQu0?Txkty;HFGv_2rC{GTi{xYY#Sr zo%Ewt2dOz(xv7;(^bAf|OkYZUrIGblQJO$n;`tUB{r8P7WY%Ab^1F;W-wVuo+c<01 zUrOs6vDcbaKRNq2YZRmFxVwF>wp#=7$(zx_tA9s=ud$=cIb`#xNrubp?JdM<>lI^IHeGFm}s^i5X25b>kJJ!H^ zpf9qbWf7(3nbA{@K0E1}-g4^=?|4a)mFf@#b;jRzIU#x;S*ER_*o6BU!%#jm?3xO|_EkPHrOve!@;xY^P0hsZM4%_$r z)@Z{nsV7j@su`;b-IHPE*X7$~qBpyxk(%Bar>aL7FvT35E~dfOds#ZxHW^COTriBu ztQ{32r4^?d=RiutpP6kM3DuTHa;S=)k8oOfXFOEx-0NLsQkfqZxd+C$X>t&AuN=gb zyrnyj`^8+>AXf66VPX*<^_NftM(J4InTc){LF#;MpLZiVWoKt(8WOhNrMG%K4RhbN zx_nzsl+H)IQJ)fBAV)@=;MBzlM^Bp;Rdg#xvwG4I_dEG%I6YlSd z7BBzBl=d*dF~u>ZJ)H-5eT{~R0i%RXx>s z!AL<1mydJ3_l{L%57VP6?=V1B2EJodsbqkvv>{L%x!}K1C9?4b?7GnTv*={BnamOk_I1hcoz}cu*X?SGgRb+$f25H(h!$>;r`Bu8^?{EH&)`a{weKUXBZcUl0 z{%wf;tqgX(tWQfmX_8mfZy3fa(W8828DSty-b0w4s13SbRMo>SN@==C!-Jf5lGGEn z1a(f?Ah^kSSx5@~Rzvy$q^R0IhiDH>CwARuQbTpEKHs!27VdtN0h!07RR?e5UR$kx zW*AroL#B#O;WeS{LnNVXHlgZY8ZK7G8Jdf&i~GW=`j4hsutQy}ky5#_CmJfT9fAoK zDW+veI`c#3i=yUoOQa#h`rLoU3XN24bDAAHO>S)}ITn+C=z(3Uj64w)FN`q#J@B;}=LPAY_Zwv%M^W+P?7XH7V}eWqUX&*eeuK_ptUN668;=)wn*I)a z2hqxT$s^~dz?RBgo3sl(%K4r5Q=pG}-wqWo>!CuX0=t2UdquV@8t`4j@nPfk5kzIf zt1+s}444&Zf(Gjn#({!u$C%Xx`;Y4lJ?qgLp|`fSDM``RTV6JaF{<|35SvsV={C|> zLfuBOgQ;1>XWkt7^{)u^oUVt#B}q zW9|m|5ubO+q;QxaDV$L%T7z)7a4=!-^kS7WQwn64Nj_B|56!RzGE)j<8*HcxWR?_2 z-+v%plZS>iJ3`t!5ijL>G)M-XO(Ks1Q}Cg+es#$DuL2YIuCmsD!ze)O9}E}M*C%uFv-(5yH|HDt zfmchJ4|6pwX>V!cVivi}u9vmynGs6EdwfslLjq?By0jgM>)^>)nw2gKqP;&s)I3Gz zoE_nVH@5>+&u85B7(LM&$;a6qxup_@cni3{fGGJp1adz`;0XjO8F;`3b|KIPNbRRa z$iJCTdzd-c2{qPYoWuHGvcsxNx{g%IkI z{TcMAGXf5zNBnf|T4XD4Am=fhTxRN__bz6_xKh`?QVTI+wFQr#yHg^|fs6P{@EhfG z>d}P=EfV)W@{_aMS!8|g*#DegIE&j+kNI_PUX<=cCufgyEd1oOtldO+Is9w-Hp;vS zuQ+d81>e!QbSe&fauvbNKY|Q?y=P+01n`^lkfX*N0kzbngJ8w~L2oy0YyKNAH{aLA zduu;kzE>B+92s72yn}xQhOTWQgTGDrox8S)42c7oa%~eSo=@Wcz_m>tdX8u;aBUOK zo(e#gacvXL9Re{D71uV=JjNqR=(TH`*fDED46%h3mO)(G#1@gk$6ecqPxa%*wN2JV z4%xErhV)Aj$XN+w9&Ff!P*UE6KrW$y!<*pwbA5r18N|lgS}%2NYHmaMoW_~B&Ng>J zeWl!PYpAO^5W0$%kMf@7V^@>*ET z-up5KjiH0C0{{1TaTksrme#bcUV%5b`foTtWxf+|Fk+uGp1WyntMcCxgp)9yNc?>c z-#6%zkjG~;RxN4An`7S;eJiTGdo$wQUVCQqPJM!2@Xzr7JojnFPrH^QmW zh+s@HH^OBsdDc5Ko*FFv|Gp7!-ME>{)>19{N8Z5t!d}q*f0wPBYAb8ihV=W?bL#$+ z%huMqw*BHw6HC@_Xjc&_>4wN|>|t0t2g5d9#nn{Kt;CwH11{sfb-=^><`qr!1=n$& zFr$3VjLMoC$O|sr2Yiil%WG;>;94($r*6Rq9`*uUaEUz@)ZZX~`bw|P-rC4g>_K$M zLgQ@s*=wTx>Z&`L@yu+ftZbS-ZzkqXo#aKZR+CQjhTFNOV=5c!n(E7ER9DW$l+SjI zsSD2Gm3FRwdE`!LnZPsmGU@rD=&pKBWmj>9L?S&~(8u~$ORIo;M6-eq@{HkY`D*3g z7I_|mBL462+vkt?DdZ0T`|xMAuuQ7VzdQ0g7DVhr%y_2!dj+I0yz*kS|3HNOq@M^b zt@*nn-v%U}kg2Etu*9-^eiuEk|Cs2St95-=bWH@gdLhDw-CgJEcM|EH;0lcwl$HOQ z*r2HA18&BfA`SvRU$f z1|WUv9P&0G4WMiEEX)CH4f((0ZNQd{y=U(a$l`nj^AhC`%%a&;&pouu(5!n9i3H`Z z8JaNS!Fx!{QstLsy#U6D|1y62aB@>f?m}`E(xjQ3q1ljMmemDmMEvgf?K2oZnpfER z>gLpzbt>T2ShMTq*4NCN)l_*@CO;j z3X|y!;duzlrU6GmfUL_LbET8O3DW0s98wAGb27v-1J}2c7 zpR;joPxoZ!HXypde@Ru-jGDR`)lIcnh0U#-Q-yuDFc?dx8uqUWvn~v3eF;kSc}zAC(a^>I$6X8*L*XaMLY^7V$g4wnAXKvj`e=TcU%rh<|~2My41O|2x51cB~V9a z5yajD-b`l^ha$y2iB6nFlmPJrs&WTs5kx#^vTi%Az*)p}AYbnJ8@3=PvK*1U3FF2g zAWe4>L23I~-_l(~oD1-N(`?dRM6f}9*4-@1J97~sZP4i+q?hI*LYkwadjqzbLN0sJ z8?dQK7qQa<3mF3D$M}o*>=+{cR!j9DsrUmRSCSF`Rz&)+wOH_z2#Z9vkwP~2Le8NI z8_;q=|Efi^afHxR(9(QvY1l$E4ZD6VCrsE6cu8wnI-x{Of=nFef|imkMpU(lt+g1| z6pfLgEaIPUF|70{jLc3T@>+{#{nuztP=R^GVp!QVhW(b--w6M`rD4_AG-4)$b^z_e zIx5+R%p!#0KoP~!hjq>N=Hn3-3$V^fp%!w2P&l9I8CkO}%@)!SSjZ5>ai2NjuR`RY z&(YBr<;;2*VZ9%xa;iAz;*K3RHdRgy%hK=15k99*Pg{z}mD6w`mAUOMQBX`iv0uvQ`kD=amP9=LvG~yBMmR zT`^|KITJ|jJz-aD2NE5EQ?@$#`PYjoeMg(Sx%zRDqJhF1A6^x zGySIZrhsF9mNPxzn6EjsE%j))#%l&zTYZg~XP8Wbu*ZlQXWR0&mL=k4-RYLCzF!8N z@m#n3BDXt#3D)8AAV{}t_6#FGgTsfeu$9w8=Ap|GA2HXk^{oPdeL8WJ$)xV+ZRdka z!x63kn+?m>Af?ayBBj&{s$Ds6%ChPTrnru#|C4ZjiTDsq49o!1b_zTjycJ>N9})(= zEucgDQ`L7OoZ=LHj&oTSbNnEDy{mdom$Z|Y8dZiu`*WZKa)8H$k~bOfM1X&+!Cw0w zVEH1jSXEmTixOAnP# zql^h3j;HJxi|#kcYz%A|#cAAFu~jTeD}N7J)+X?yG(o?A8WZ#YA)auxCOG8cGLb=r zZ$a`jK}cy!*QwH_6Ag16n3FS2WHBNyYDu)3O4fxC?^(nXs62~9>_``nW;gitAdurH z>M6G9uJW0=!wU0Jo;OLwaMl7aPI7yb6fhh1ErJ@-vSHo2*468qcyy+mTO;hx#($TU z=r&n5N^|EmaLUt3F(ygnt9(kHfG&&P1I&KE_!o2Pqtc~Ba7e9Ft{1y9J$TlTuui5i z%9FDp(sJfT*>b4eJYgRqFFC~fktH^9%?9}0I5|3L{Bf+S#|a~n*9+mM}> z4ze}tPN`XEp(g2?^>a!6O~fZ_m6db12wC_qf|PTQ#O_B-S|26Fy=GJOrbzDhMO!Z` zla!_w!t~FZf3sTRBpLTt6hg956=rl=b!9(|GaY5An8KWEw}G@JS@h>cyMWhJmoah{IeQUsOg zG$89sPWk~Xza6o9#L6E;;9LftMBuLsyoA8muMl_xf$t+w@izoojmW7S8LLdBp7J+F z`%``|j2CZ!dRi_5?$=PIatqLNfh+$60uBLaCYigLjP4@yn&>Pt3R4rA)YM;r=G(@~ zdr7k>x*0;Iy#x4JAer_D1b#x=WPhW_N;KljKm)ts9*-(H!NA)AH!!SY*cgs6iO&W* zKhAs6BL+g|FyNkq%&JU+^2306511p$5hy<_8Wrr5V$R5a3Af%q!oI}^e zS!>mU%i9pU5wYp*2yi?( z;#>sEFU8MZfGf9vXdKweuOZ%Z)J&Rk*5zf)z1l^&Ph?Gd2(T$YmJv|?6k_d&mH!rj zml2r07lF9V9N$&uZR^Jh1wsnwR|5klQv7n3}_l3g_=)x}qPH0fM`5QTapLeqe+(_20$R z10#+a&X>$(7q_%Ql-{$)8<9Czdm9+( zVIGDKc=M?-{zU95uW6DUKj$!iimq*FC_nO_`cawWw|=k5KgLS=+%yzZ9&Uv?{rtxv z?D9CoSMEho4<3%0&IzsU?Mqf*wmH-P6|fHgtNXoKK3hy#HZ-JHL}#`eqmz)2v&ipKY(~694w8^Daj&6j?t%1|`bkT%m=wvW2FnVw94K1@%%a0)T58T- zQ*$s^H(b*HX)ZiCuaY}L(th?0(kABX%8Xk`#%`=m&!nWy=xgA64Gfhvd8mOg<JOl(PeoDtA-6{cr-X$F~ZvLJo% zW^iX4ZfbX_;ieWp2uXcL!^8b^n$UiMUG58Uxu_`ru56U$D$To6=Rij1*(P!|6k_Y; z)FxSLswcIatmR7SZ8UJ^ecd;tS7z%%=~lxfi@4iOge&6fw1}LIAE}EYxnJW`NIOnI z_4%Pzky<@y6kwq&HE>phmqLm?Y2Z|>&!PX`5Zl7t+ZhT)!zX-I@?|6A7RZ>UWkfc9 zreaVDciPcS3f1SKlurAGl|CAnv8Rx=JW zh5KUX#O{X8LJ7?mg{nb5`UhQ(2dI+UGOFZ}Pa1BNaPpraNejP8(qkFfYZziYj?prebQ&6Y{O630ansZ} za;{7?N@Q9YS+{HRmCDXmgH(9t6G~;8aPI1m(j`GkWhNypdwN*5Y?|3=$+{)0+wmZP z+=5=!s`t<8WlFopNH2qqIv-Dt#*|oetrvNhpwAx5rzcRa_)JlDE`|!pXQQNkI^vUc zLfA5haaa9mg7k5vb5!i7%zmDp<{T}F$_V!g(t+PQGl!nab=e<{GTS(8EQmcZ3eARV zvLWCuBT&|1ix87_*gUSo^nmlJ;oL*cE2CGFlZ&w1K&z4#%g*Ospjewx`lUmzDw9mJ zMqnkp$3!&{n~>0O^12hnmE$r|{5KF+@{u89&ydkQ+T6&{wa0dkDmluqP=QI1Y7|J$ z2r1AIf}ayg;=39i?z_{Hc{|+t(Cf_jo?*Vm2m~y7rGa%h2)A%k@Y0_eI6H1VwPmr$ z)OLW%XH^*0c}0?QrB!At_DnI3x>_4fj0thh&hI4c>gr6XN`tzX+0BoDz=mRv=^%r4 z;|wP)%2{BBRV|%Z)hW=khA`DwcB@JAv?$JC^ zu#hW-o*DS|7$n>P)Lf)jek=m-Gq4hYf_$zX5P(x7QwsH$7?A^vfEkv3Hi)Y-u}4te z5tNl7r{p#xr<3+!(~^=bvLy-Kk2XBC#X_WO8%V2xGn?%xc*zC>e;RO>efw5e)b`q` zg9^;JUyVIyXs0RtfeTeg(#Hg^${EY?$Y9Ao3>j7EAToTG0io~264#W8v}3hQSi60! z75a_{eH=oQ(+nB)F9m@WoSbD4Osz&EWIohr;J*dD)iPY=sH2vKBn2afK8=yim+rmS z;BDf$vW{45s8)qKc+5!FFuy=ddgVDFi+gKr%iJDP^TUvuSBA97 z0gEZGl7|hvld`umGs<2XEK`*R+gs&R(W5U#z1nMJT^QtH>|vP7IBY$RS+1XhxGEES1jS^CC^^E2=p-99nT%{;f5z~zMEfI2Ymy!Y z&MIJF>gc^lbge;*5At^=HT4Ry{)VOv=Y|BfYk@p&ICuwY!}TGYI+{mtyE;gFmeLLb zYEE}Zd(7ae#xF9Y{UwA8Hrsh(*R*`iI=evKC>3kJA?0F~A7|&=<7~y+C>85bq$bPk zjk3%h+rv?F z-b608YoynHl>@Zbz5{=HM*Uku^&Y5h??9zW{GVv?rg-(F*(|oK4pP3egDy(Ww(NvW zKXKG#*9 zB;sl*&d%8rt)cH0A-#GUL*EnUzSiFn)$_9Z;#|W2vX`S4;G{?P$nKAGkBp9P4wZA8 z2jbi#+Xs@#>4`rmh*%%pIXon)3@tRJG#?sZ*tR=D^+rY3_{0QVyH7_U-Du#fYQ-t| zj3*4dT*G8WgR?{|u&+;*$G1XAvmsy;lp=ZE6p1;74Axq+jSMFGqg0~Fr6Jjm9ay$X zUJxSu;=qKW#6z}TB(rZwsXi9wVGBPEzjp1Orh9NgQ_|b8*-imw)6*}SSbD-@ zOvn0hv+T$ujfCTM^*|;22;_QHyV++YTa03phIq5j`f(|va(;D-#QXQP4f8g+D(7ym zXT#hj(tiSENtH>0wHNu~1dHwPB&29tf>~h5IE2^H>5W{w%-~k;Ya;F{BWX|2Yur8A zD*Ku!`#KU7WnUNNZafH!jz+eW*L^+!liN>M$Ulg<2N9d=68naz&U%e4vi0jWDQBNA z9m?a7kJW|gP^K(dg&VQUHZ?6SCM9j`&%lU42hT{MdhYlIexZ`a5ti zV34fjYASo$*9>GE$-ndq4>#THl_W1Rf?2Sd{Cop>j^wfUv6lQRl3y1hFDbcED`hGL zdo;8rtKDK0?`dFW4dW_*KDR}a;>H0QyQMOf-r`W+T6R_bV$G_ zIo)t^K1n|~IxUsl9Fo=>mIeHP(&__gHs>6O#%V6y)r#g18kt<$&k3+_9v@2UoNq|$ z|Az|2UAw>Iy5BX15%p@O4s}Vq9aZ)Tx_P$!L%m)9f`8ULmHi@t(;OxbFJYn4${0YNV8PZ z{1}NW;P&=7>B8OZ%_ZOKG)ecQwf`=~aO*un(!Q!g+OwzH{2n1`k1DdwwK~q`x&m?0 zr8dyz;eVqGjc|bc2WLXdM3v`^ltqCVx?)QB~60U|EN4y|SwiZW-x`f_ZSM zbsc61(d?w*!KRgboShd2S%_w{p zTL#Vovs&k~AUbK~43Y<*noXjw1&Mx8X6-ge9+i3(i4Nz}7n)(>Ae1Pd$w&Mil;{q` z_4&x)Y@UxikGOQSPB}Z;U1m-o>)$s`Vnw~cJ|cTOQj+!W=!4Dr_cR1l@?1mqX%#vE z(7=GsY?Zv%fZ20>&wxWu_t=!A=h|rc8kr1i&>OGp6`wUS*lDwPSvIEu9=#b6eE5jj z!(~C4CG!lNJ@2aq4*J?d44nKBuX_{Sb1>i1b97btw58rBXR*)+BEknVl(MAJB`*Fit9!C3a2w7v0r(5LZA!M6D>iHBNW4p#6<453e6@!#w z;WKWxggCD;$n{pNV=UGkoc9}KyN??h2F@n?e~Ik`(<~#+c2}?wrFN) zxJ9>?NzT}CPc?9wu-L%aaK9g-PZ~H6h;B0Qc5E%x8TcLzlYu9>+5oBXml|id~RTm{5GLLB)}Thc(@kBZ->ON-VIrZrs1n1!=)TC#5dLy@5?4suVZ8O>!V zoLX$EA>UYleJN87OUeuTPmqy_t@zuj&^Q^kcj^?{O0qlM;A%>dDTF_ z3$p7?3Rp?Y2W@H=bPG{XSNLC3Bbq|lHOkncHtQp~ceHwSYYRq(%d*!R`l&&4eQ7pC z+cT8QvU!H`2qaII2Q@Fx=5l_}FvR(KDA{?(qmcrg52!R#O28hNu}|{WkbRzn-cT!C zr7fLUsJmfOrH>gdw!Wmlt4uP^$ltXHX^Q;~oJ}rR(4)yZfNph>)L&@HsqAmHUftxb~ zvlE2%iabuXNX`wGwJu+>VU=7>T91tyhXt&?gZXR z!idIi)PLbA%KeWWL-{WHg#Y7?pCTLZ;1V4_d3enWIf?e( z)HyEXy{U78bni_$X1p;s;6nE?3*6tsuOjxktoJ7O4QCZinVado$$d)@POkCZgm;f) z1XnHzQ{J20cZDiqp^Y1sYPU}A`+|sCMBu&2{ZJ6G+)VFH?k9rC$_>0Xxt~jtJ|Nb6 zllz5$vZA-oMWNXS^`6R6VZHU2f!y2oaPoPS|A<8mRz%4 z%yU{5?IDu4YG9^YsAzA8M%-qw<`$XJ=^)|Uk%6P%0u}A&OopYeGPsmmsA!Qe?a4Lm zPv4Y|4tCg!Jdqo?g^CUrdpwtGCw$REoy#F{uLX!(sOSjc+ZO->w@}fMf_X0}191x# zO^Ve0`6-tIwlhPqjTNMF^5ynU^l*vd#NJkLt+Hy4Ryp-Px&>{&8p)8#HGZL@wPG

m_r#=c4_Maxg}QT z2s@_xwe^d0OUjHL)=@;Ft)HE%Q}Oev;^u&iiBjg^kylf*Eyw$CZMte&b`Q{nG}Uqg z(s^0ZzcLO6jD7JjOd^!mL(O_`Ub61`WZl~OdATJFbnD06s=m~&+8&Pd>0iN9Lt<`^ zAwkD&_`>P9j=Pf`mqi0@llu$Mx~u!6q&qi&wOV2MHo}A&BMKZQebn2zlSnoZI~&oAgv?l1ZKcvZN1f)qn`++BRP&y? zs%P__Bi#*snz5TY!$$`^H2@TC`W~ZwYHV;He}1#S2oCpZfjxoBt=83G8GGy+8I@iB zNssZr`oJEBT+tooQ3k?a6LONxI8=^M`5-L|^MGNS=Q`DZw3zmeTw+L#b6;f2pUaU5nlWka?+B z=slz=Da*DR=rOSp$0*a*+uTj+uSG)rT&_v!+O2;eOj2xG+1I5-W=d5wU_KOjAz|f+-!M@Rsl@E|nEgTJv zcC6@I)EY98-w?$jP00ZJ@_{0>>(Mcvax_H@(wlnh?%cmnsr7^NZQ(B=Q(Iq}9>LOl zCRNd!?Er`^*2VMC^-Xi8Uow5h<nM6H->bJI+ZZqkLn%kqSm73sKq7%WF^^tO@`3dQ9Oe{@vO z|03L?x5WFXHJsi3$##|*{X`>n0_D zb}WOE1j~Y^V`)C^?(L$5!An*5g+O67@g^k96VSZ$qE;=Mp)x(UN~W5#e?kT{Yz_Pu zG~+ju)6L!}g{<*~Zyq>!<1Wl>=;5Yg?$9seCjmzNFgXBXI(r$>4p9&UXI*}otsoCV z4**>Ohz4oV&7j5G6mApEKx^*EZAUA$_3ge*G7IVkvMn=qN<)=CP8g$z-FcN@`g!QF zEw<7-5Ghpgh>e@5zrTa>m9*zW9$oFR&Y=u@vDhs=a6IN?F@_`h*)iy@-X`X>$7F_R zmW#GsOQ#g?JB(>(_Rl(FoiNTC#Q4N#?6D5bvGbF@<{r|iewy_ql%?edsG{@!WWH_T z>KO6?vm$d^^aCwYp%Q;m7PIgm_NjxJ+Hd;v(pj3Xnp2p-U>&cUzD%VyZFxoW^3qpb zK%=Mi>6_~_OM2KVpE=W8X6o6~49hxtR9Rl*RyeRHRY!?B|0*Ulyu)2|Xcc==zDzy5 zJ+sW%R^~nsx;5INMP5|1Y%gPUU!inJ=*r~Ok?bkoCf6`Dcq4Y)wYiB0CVRYWxeyk} zY)9xNP!=f9dIB;@RAa04m{5IFGv50`bS5YGi8IIkG_`8G094zBxO{fcId&mw;f8K; z?XXQte;IbE94T;V8|-uq`C`iPD3(FodavBZZX(adk{EO(P*@U4V#VhQgRzVo1@(7= z8q2s(;=i!tk4b#3BI(avN?|J*whdT{4Oj|6o=Iv}6_AA;HOAe!+o>e}C0#}9mmP9i z{~E~ldLe^iyY*Lq(%pfoC2g-4>WTGQFQ~n=@BvnY=@8Ik^JE|GMV+O}$E-l2%|@HH z_FhWF*`(wXJvMIB2ejbdvXYBsRZ%~VXfq`~yv=)NF?bU0;MK8pYB;b{h{Q3VfesY)~>SN4X{mBV4Wxph{E`G z-0@rgu@10VA6(DTjFLI<+3pV;AYaAA=wBbe$#V z1orXL8Acf%z^j!Ze(jriBGU81dT97-=;brP%Y^5b}1 zasrPjnR+ZIB)cg_Rqk9&vKLKWN?K?2IFlaSErwRP60Ag68qdou@EZuhk9;cfplwsvYP_f_qf$l!H)OgRA|AyZ7>=BO>{X$hUYi0OMmtGyY#(p%Rru@ z>v^5oUHu>SgaBehZuJ0(?-w}$*rW-;g{nRgb&HS{cZO|o#vfgbzQ^@g@ujy@kiSv9mz(`r>j5g2Luh~1~QfKGwGBP?Nsr5Ig0|Ul; zP)``WP=~j9p6)^&5D%aN>x98{7!1V5_K7bLr3fDzv}q7*LSjd65@)t~mUodD7$2Yz z)P9@V*!5krmDQFSvTs=TO@r*jU~XP$f#I1ATEO@;{<<3Q&ux^>i2p_W}mN1~U=?+=P0P1dr_mj5O#u9XM++PJt^zD=s)*fq{V7=D4Gr2#Z z>;nU7r?#PkAv&HhR1m;l%)|BFB@^hH6Q$2fhWgau=jLC-C&gZ?afCA8J67~Z%h{BY zh3SQgPtIXZ|B1~fl|QuxU15vsl3whNNwHf*3@wj9+2#7b;0Kj-Z63x$@$-KExA}QI zE+T@TRqImxlso)973e9x-;lP&_eWwWetL`_rc=*E@cl-cZoFXZR*p4!W5{D#lH^>H z=aQ88eBz^>_#zgXFdR*25tsrxO^ZBDMmW(&i#~?i$J|_SmzrRWJ%JdBHS=-{TdZ`o zjTv9#&pprB)6$vUVr5b=mh>2_9qo`6?Nrc(7D`*ij*mI&qu&uX$IY}@uAanp;#JfV zoL_i^%_zOE7JXDejr|NdD|V8S+E#7NmBQVTV5S3ez2Yq`cr7a~zt1dX?g{=48=QtN zSwFl4_nmw^?%x_O`x37~KlG5=FId{;zN(#n-0v&kCOke(yYuhVE6p6XnWefbK19Zw zkO?2F3OxYrHOLB;^KT@yp1T;3n*mWfXu*edGx*g^bnMNK?0(C-QzYw*g?|FveJs32 z+V0G^i0Nj=!4637(}*Lm2!6EdNXcNj013IwnK;*;|NgCT>Ard5=X;IUhP@+v`iybK z)##Ywwnm0xEaQV)rTxO&dGMy7RHwzKQZ5_b88-ldS^xZi9=0qE?4EvJ`~8*nFr=ri6ZGqBn0!C8-$Nds-!Jo67nHYatX z-T^@TU1dnd{Yn7DB>XvQS1v3EbdQ3{nUe(gDn;n1 zwMYO$0Ce*Q9RE*e3E?-IeX?|P1+>yuF)!MNb~zguzyb+JaJ#lfPMc)clH-r!pMHqk zverqn$2T4G1kZ0eHZWM&bgX|c;Ot$#jAat_zf1ZskUN$Qf|nDoClNv~sr9NLoQet+ zxI$;Lm9I<{Ze7>>5X<;AZM5d;R3|&D>m@avlypIX^;VW08!w$vAX}0j53xH#P7Q9Q z^~s)~Q>@d$Q=4s_KSNauXo6^E#!zV5UbGipZ7=#nK)b8#S)^^1%_j!-VcgEdZr?^2 zP{;}mVt=L1&gP`O?6Dt*pB<2MlNUHZL9(TAI|*eH57XElWOw8f>%ixn#uvZ#l5L7! zgtp)GJV#QF*rU5iQ^gPAmyOPu7pc^AQpppR!XwtlFr-(u`P6j-F>`sHrCsyCbJk+1 zvzBkHgJ`b5=u7QR8sjSZTwD8=v_`qTv5e1XiC+1dbuSe0g^Z)6u?jXyt^7lx9h~qM zZPjM%(KhV1E@RDOAG|y$R_ooVVuR&0L^A~5TLF|+0h^^Rb!nRO*G*Nw zjLETJTB3}FotbgV3$VCbPVU+%2(U4{htN1|RScv~F~5IdzCy5lwaD*?(Y({(IjLbB zXq6UzU`3D^S|<86o|UzbB3fV^&EG@FMBqt#2ngbf?5UPmi32DZdgt|ae{i5wV$MPC zY;a&+{IS64V#oVZrPxmlpx@YURnti1Z|n^)M$%aX2aIESpSu<7cJClh$~Zn8!G=np z&rP}G^RX&i?TBs>vh4DX^-p|6F{;HziXk&ImOoD=d#yzSNJ+!zk!{W#e5948%bho0 zZ0sbM7;6S|XT}DfUc^=u?Icy8P5V5&pZQ5<1v6tPbaZo6=7XZ0T67edv5}{nCFw

8QWMC&GQ+r`i*_V_7v?5o&^84l;J5?>_EmfVENsh zMQ<Fr$s=ubdJ|Cv!3QBM@XIs`}I49Ei1l>92S0rSGdy;v#5`%OS zkaASI92&BVyKP06cfsN3=X=bI2d;(~&5f5L6rA2I@1pWD!|h&;%+xs8W4%O0-B(x} zNZaG!@5JQ#NKQoXu+>@TP^XQ@j)P_0EvUOY#k;LYg6JvIhpeDo{+pCNwr>w{gzq!w zX8O*Vo6Y|rc#Aa01!;9g`ikFp)^EHdlkWi^d6mm$Mo2fxlMGY&RTAo2}o6!pNJnOR(v8Y;PK1}K{ zdtZ!QWW2us461QGQ^yNlDr30>B?%ygyM&uq@vjN2Cn12_lRMM5=>#xfPkFSgGla>0 z(16Kk81llxgMeu3@6P=dA%t#&g0_B3?n5M5OmE2*1K+YQ-QC{uQKsKG<~}N!zoxY1 zqipw4xb|~o?UO1wX$Kj-9z#k<-w%|K{skeW^C(r6B<}(8TJ~qU+a>W!mB@CtT1PLW zleG0yvwcNv!NDM12$HpzT*l5M48_{>fmI%TXO8mqq;ZA2tona(uWpB%HRL4iPH8r{ z5pXfCkAN-PKqbCS=`_Zchjjr6awL1bctx@qD9qF1*|`nk&n#1%`e0GAf_`_qDr;)FWd+`@of_ohAOGnSKW`)6ms ztUdcR0@Z!)43oBZISpc9&vLM{t^hkZ<5u^=nnt?wR-ki}b$z@lS(n@_w(IKO3u`E8 z+dkzG1N$F)g&E&QVNV!UXtd{>A7flERhBQORl$&{rE17d)$rS5WyUxP9QO->6AS4E zPWYzJw_1M^fY;(Hpw(l4)4q@7ofhRX&2wt|E0`WIc3F=c6m!c~;g>Rkm0M+OXCy?X z( z5!nEZn$@fFIQ)#r(BLkQ*vL1mwVWt$-e+cH0BRKoE9B}p8m8ytZB*1O-qrzPOzu)N z3d-HQEy=p_Q)tL7DKEOT6>s=&0?tHKh2WRGA##JyM^Zw)EG5*Lu-#on=99L&t%jIA z-#KhYe*;#E?TZxKaoKb9ZNy5l123GcW3*D$PpHazej>TMtQ-hQ|KmbQ|K|YPz5h?R zf&LFV{qMk>*9)cra`Blq%nf?hD|1!klTbAy6`k2g|H&IjDq)T?2udy|)_v~Ock zFM=-!!8e)po&9IoD|vBKHc-~1;s%;0aypwyk`CkKr<}Ektiq3DPc@`n5- zyi^YNLjTqcU#4;cWY0OZf8DQJRtc)eF>%rH%RLh>?YoTQz%o#Gh5lLC?A(9Tjh$O- zx~)&0{opGAdo$$e9L7ed)igmkWDDBf^gbY=s7HLE6d2ES{*? zfX({c=0>RID=xIPQ-lYn!a(d#xxaTRhVY-9T1uprCMPl1rpLyG5Tz*VE{F!$sAos9 zO6~!^5n%V;YwaA*YUXI#s<2*pw`xv!ySudTi0^~``)6vTNC?h)|Ez%Xwhe+l%v)a z>h!b-nzr40dWZESyhv_x^ZfzR7(}P4GhE<@rYEwhUsd#%I;i3q-XNG+0acL1zJ|Q` z7q+t-p;FA+)73m%9#MTU1Zu%2SQ>}l>)#nt>ysYk13TB1G<|bP@ME6Sg4=jbw#$Ru zala{dzGA=irf%$i_QRg+zfC%>Gmw-1sPflrBC0;--oL<*pHMmxUt2VWMH)*Cq+%cL z`?bfLS-7ybvktbyF|Tn21T zwn1E3c4pX!a9RV&51}LbP1@rv6nL%Z`BZB+S$o_Tf!iJ|O%q3I(IfcUa&QnY#$VvL z!14gEhmX2LTB){vY_6~An{&0OT!N5(Sfu*lQFyec{rEIvpLHD=-4&^vbo`$}7dL07 zHIk$d&K1INvQcESdYeVi!-cV-zZoY`IsfW_rYuU1tW4H*$V!un$V}?o$G~!n>6OxI#95Fkiu8<#auSM?TJy=03}QvJJOEZF*$wUj>!Yi zsNHRo`$_}kyh7nCesHLVCb^a7${IlR{VrCI;iLV6a!|p^=vMJ{OV*so6&ZJEoFt|g zFH11F<-JUf)CN2&JAb|b&l=@@CELHIJYB-lHRS^w3T;#RdZ6C9Pu+jl6}Q4sH+cyM zI5&j%LadU*4A(RgE*UO8lq?ru-)v-ekGo|Pyk z)3I&u0K2|d`nq1}%3kROz0&h~rLXFh?p;2&SNXNQ(${oP;|TQdZ{asYdH4(MW>(ss z3^DMPyL7Yf&QAd>afyF0KP5n=?RWs9c}P$ljwL0T>SeAR3{{FZlZlIE%Nkh$$+_xG znO#rCh;Z$$f<5WEX`$0F4zqDtjsqc($odtVc?`Y);-9asdLAT027AV7FljGQ&Jtx1 zjj-Aads>2hq;3E6AH=X9k1OnNyN!>pkexjM);a*a*A;aF@Ss?fdF8S8F?JhV-e_f`Cs^Q% zl`*e0Pm2Z8-85oHQ*wP^ym20_Y<9PFVq|vt#+! zF9#QitW(%u<;}J0&V?T{=Xu#0G`6c*Vwkjs1)c2GyhX9fJkiNicg2oc+noI5?C~ek zw$403Y~8wU?_%)6Nr&$#e2K)<@_0rbHOBQL(f=A_<>)pao7+s>#w%^UY>CzQjZ5?V z#&*IhMzr}(lRR8FO&BoC(ye?d(9J&1xxo(EpHV9|b6kHK!ID(o*YOkG>}tZ$kdXaT zI*T{OUmXpuYyqt6OT?Ix4!C&Z)TqD4Lg22z!mWU3(rJ-yE*={8NP2}rX%)7@&*EYIWw)b!kLh;PE3ICf$`WeN)) z)3mkU5b?>ofT}XRvXxGL4`-CqEcc<<@i^_&o)2j42TJ&yW+WP65w*E2#__cE;kd`^ug|Di&~BHTrFCu5T^EL^TyzQ$kcxBcCKSSk8@UIOv&?`X{>RB8iODo zv(8bRRWV9xST!h|(2N_iwY8@*C7G9G7QLk1c@U{Xf-4=D^;Mfekl?ar4G zA=?Adw+X{v1D^pG3^}F!>Rmad9kPxpgI~2;TJvWFFRz%0{3$503)-|bqv&3BtioU# zp>nn8E}#OH|1xgOl(UwbMnYZ`tKCs7MxM?l@h`;9jTJw?ObsSHQ@OBqF@>_vl(aOHopeS%lZ!o- zO%am9qvh!ZoJBhRH|jT9<7=P}TOMkC8dNmhXRxC>vmg5JA0Su!N^sOl`uhg7o8_mq z>^sgkpt*-w){KCYto?W~*v&B{SmX<5S%*TzmBHL&Jtjb8W-Oo;HhX8L*sF00lWkc> z+P0cENlZ+O)p3DzX3j*aQ8V`Ysb&sM(K%h{?CxBj$eL|)Bkv`#C)baZZnP<;u1Ya= z)H(@x-8@z04}`BIv)_Ogzm9H8WDT+j%~OPO{=P#9@m?UUJ0V5rko5w^imR{4v|D#- zimNrMFrK66Jp~2CG}xxMq#M1~V3L7D>b)FA@8>CcG8@>PIo_tH?lPJ=BOswbUrq^@ ziNFEPut6WDrxRHvcGW+@S4Jj>w@XuOnOu~r`lywrIGbo*m8ryXNvf4!$a%^KAjdC- z99{7jD5#nfDJCbTYW^vJQkd-0-;lQVcmJsB&uMV5vnD$=U>U5a!ipcpiKBuUNsw{2M?l8t{<9Y_7^%=;vP2Em1dT_Jo zgcf}bu>~rpV5u+3G(IWKZwd67lI}m}l5A@*=ZJEU^GhJOyE)poX)rOPm76hnb9m%W zZ|0 zcDBS%p!H|r=CoJ?5uIO1Ddxx?ZnTihZHZ^LSlJ>ZC5E%D6{-qa7XN{CUzXLXhIG+z zHLiX^DmkwHwUoFrfJd!IRk3Yrrl!W*9_udhWuzqs$_=D#+t);li*o+%{;$2?Yx+3y zd@g(x59@Ix7e30{PwZvLYAAX;Arn3e*hbj~j%9p8W!49|qCe%MNuPyMTd&yZk)+R- z^fo&^g7i6(e$q~(BN?M5{RnBZT;4Y=kmS!)GS?}!XM=bXnRc|>{U7sqfTX=v1;zH2 zPnGwhM)Ia9I;R2hs3b2CkPDG%*ZSJLo_%Yf@e2XS0YH2r()&oul#TConVPa&t;AWN z%ORG%S0hipm@zXaxU#UB$mK(VO9`4!3TZW~k6qW_r@pbk*A!aFef;#$n40jhKA};( z%yGT=lGUf&%wGLP`hd{eHLE|~mIk_e zd1noNpR&_jhu^v`c1!%fXioU3rrp!b)@l649_+143}3+R={mw$PB_^K&vU{vo$v%F zOmo7+PuqC=ov_0RTb=L;Cw$lm?{dOhoUp+O7dYW8C!Fkr=Q-h-Dopw>vR-2|kQI7{ z@gyB`he!JSD3|IPR>5WJaMU`RegI&R09+>kW=0ip1!G+)8LZa5GR$Pt+TL_2S2%JJ zofCqo3W-bi+$K6xsEi{+(I(?$$%x=Q=+1FHmj^t4Sp^wyBr;LJf~&geAKy=~E<)zw zgx)PZ@VUHpndiJ7FZ*eEpudV0cfRwH!zT<(&o;@3$(cz>x^86sO_H2hy>H`otw){n z7jxVgaTeuc5eZ{!FrRDhni{#rp2UzH;ZAqx2r7H0@S%L|cok8xPrUP!W^9d>vkaf~ z8ZBrKebU+5Z9XwQ&;C)yb+DhkU()7TPg;Ds&WPx@o)})JI!F@y*nhDj&NFqtzJ$s0 zPHDx)^B#V8)P4AWVsE_=V$HslMf~R+A?5s7Ai~>9>^)OXa`YHolE}*XI};Q)ScvZ3 z!u-?bggX*hX%q=m0juP!41pU{MdGlomSgfwwm{)Wdg1H3@r_>iPkq=9z381F9eYUs zyj?fOeTmCJr}phtaZ=y(jn7~0?WlPL!96|3VVrLvr0z@2p##(xE0(ftf{3601J*R_ z9(bg^8xWNoOvdKy5#7kTO|s=?e2W(OjWj$~x=*AqUZlW8sGD>4*k3g$pvY2+$v(;o zXe!-JWKC0qJ=Z{30LQ&eQJZJXpIxp2eO=9Mo>9c4b7;|dL{X$uRr^X05%t>9qlv8J zgiI{sjG!<(j6@>q#;5Svgos+Ee@)6-cZN_X&4$=PVIfwEDtc}qs?L#B4~za{wSv5R z8a&b78WQbJ*-z^!{DrRk)cY!)N){MgHVWbzr@=5Qq2P(wuV6_En5|st|C}$xM~#g; zEJ4wy!FSnXK#1H&YiCP8ovhHo?l@K%HFj=t&JTO*BmB-q6x;sI_tVvlDwcCOL8|DyU-rjh zIflgVOrEdCa^j@pH#zoz^1n)YaaVe!q~~>||0QYlG6fp&=KDRzyWZ>kRnpxJf|3tc zYyEPx^qd^+%$3&><_D1fBHI#gqA@7veyZucl6m?xin#BQXWgxUkcqLEV|Ocy0&5?S z-u_Cr{jRxs<)}{{g@DxiTEJ+NZ&Q3qr=SmSlh0mexEX_sNNMIVQlG~Tcd4FXq&^ENH=zR-y+UgFaEcu^T2LFhBefM%Idn(1pRr4arK zGH^9H^d0QmSRmkR*vLEt47GZ$6xPf@UV0+y!HtS=Fvwo9KQ^;Dy#E=#%4GEo@B1>C zTV})qeKJM@?b}!)WT43Lp)!-#fQVM-g+2W#=dLY#9lU%a$J?BY*dHT`SDZ>)55_0Z zqlv5sHb5bkaqxO^>aA87Z+m zl+PeyLT{2Fe;YOqH2I0@criogkQO7J&vbgU|Ejxq4qEjCzjrd_!wV|;(m+|LfWl-kPDOM)gm{lNQoA`hDcd{Gw%uo zjDN9JtoLy{?@St{?baMw1lm~D;Y>v!$Kw_Qjh((UA5e|v9I(7_jEAAw7-vA+7XilY|*C; zZ^eIzh{DIxL$%ua<7si3(NVVgSrJ^MqfFB~^!(O~V|~-?Lq_!i71%Stj(BBFT)AL^?%~^2*{ELF0|Z=>+U-iYDCl zCiN7CqeNQx%$_P9m?C9 zJ--?wC4cGaef|pKRvqbFD5yXhtUDisvNSZt(*&4YxW?#rHK{ayXptJq9 zANWl&ssgd$M;N|ba53KH;}e^_ z@VwzjTN=-xlq>A>-f*qxzURyvCICPmCeS%9*Paoj=)n+}^o*-I2+CvDjzR%D8;r zWS!DyEmBQf=`>$ZA)3_d3mj5GT@5q&B7&pW@iD~lkCK%RaUer?cGJqli3ofkfL;E7 zH=TS>N)PnZ$QLAUPbyE1%}wN4+t{*-KSM#%kT_xTe34EbraJjeHdvSk|BbfE%gkeV zPhinsB&+y6O4gZ!X zGo+SS#v%!f9G?oNWG1reDOQ7DUBOf;)A@j1ztUIJlLM^r993%$T+&~F+{u(BvUdL$ zL`}~DN0m-7GmCbI26bLy9?xfR@^Len=IpzGp!@@+m2p)oVly72_X z>lOw1B9NW0=;lnyT3Bx1N^a*{sqrLULF5*&8#ub@6FScHECE0~h+mS~WhRi9>6zse zVVk+7>L6$dpzcO<#T*XJ~iVs-<+z>ItxOiug}rb5K#%*WFU3(K@WnUcGWM zZEMvwOoq34Y4A3g53dGW!xp^tZQ=tHTk|@(^RqRN&q4&(C*3h|n60-oHAnDX#GY>C z)qS8mz6|P7?63lVmTfxuU@w=Zcgg_UN-M43Gp?!VKv`wUBp3?hx0La%FHY$C@hBOB zCld3!vV+fuKZcPZcOj(qJjWi2tO7+X+$(5Eml>ky<%ZKzvf`dfvYO=l#$G~KmR|%W z`$<{Vi$wKpX))ozS8~0Fe9~?9ERm14!JjEt9@LWE!KZ!0!Kb$GX`g&wC)qx`WxCU{ zU3SYlobG2|W@p}!lC!;-C0x-nb!jm@uha8Zx7Kv^|97g}4(hbx2a$$~C=A`kHA2tKAO)m`23kK#cloAV#KtFUKx+4kf+`YSWlU&{F8Z8b}B zKW}fb&T#5P%Dwr^`CE;WHzxwLabiz>dc(Rr#o#5A0`51=)$17WaQvpW;Zjt4_VLMK z_iSp|&3+b*q9(t2G5WNVEB)xx#pu&c(Wh3%UPtKtZat9Hr+|A;=)}%{U@YwR`DCz! zn}?V>%cM|$+!y+>jn&i5ANoyw@H97fer?6K?a8Gx^j92dS zef|~iz;T28FjqqJcS@S;39GK*-BX|Ona}<2ve;=aJNhrLDSy1`{D9e~aFvKni6&~Bs9lcI|qxrvW~Bm!2U+-*J^9w z&EOF0F;ytJhh)_~k^<}JDld6pvx_X*n^Iqa?Qvh7yMdfH3b zmvD12k7>pZd5QB6ME$0HkC_b_=Jz<)mWWN_yCC3N9}fgkrhj&$w8%E`1C2IR!>#B4 zOJz3M0m&}H4Cn-L|DrtuS)onsj%Es(7ni`T$LVk_G` zzW`8v8!zO6sP$y$tJjiIviJy^D*B{+h@$dCT68HnW=VF@6#K@U=7%9W3Y6*YG&3d((sAr;9MU5T~q{7X__Mdn9wOXPM4gNSo)Kvk3Sl5yGQ(ljEkVwdnIyZ-1KQY+^`1JAS$oF+6_+EPfwJS@=Xd ziLf2VPTSpT427H14A1R==#`9-fH|o(U=&{f+wmE~Cy<8cI*OII8{di0g}mV@7pkHg zwm;TuypEs7>HG`o9;W@$qzp|Ns#@f&G#Q{7L&2B3X^|61hl@MU#M#p#CzCL<+U^tC zXwgBWq`5NIwe_w^qqvep78?I|z}42*BcvytqeUJd3|r^?;cG2&Jke+eK4=g!@(T`W z^V|Uf%rXXUbz*+=Pbp&|YT*linC1(A;Evxy0{_z^FCFu)Aa<5*x_Mw}QTc+2s7Pce z5x+U^0&;!fZ(#gS=#1Yi&Q}?UMDT~ap2-UoWrn)#@lSRQ%yGFC@;LxA>mwxL&p*Uk zeVEOa@kxG*k#UF=mV~n$B1{8(m~q?(M7cS1L1_fdky`c2oVUnp^ZZK0$*-u>ct?v( za!b+HfH}6!*L1Xrht83h`Hn2iQD?bH;;a9F9_N^me*Mt#4HQTTJ#AL zw)(vQ8P3AkdS@Ch+HQC@6V>kgqhx12L7aYFccrlCxtkPbSIv|%3X(JBJX)~%ax$zm zZVDw8sm-$pc*zzstKJ#4r>4{B2dO*MKkNwr;x;ob7RtNiW2UyI31x1;W=y7H+V+^- z?a9dj$fmFt?ioF4^q;(n+O4&>NOI!XceRMx4aOpf$3Jdw4#HhXy=o|Rt~GMDNKOs& z1h#IC?0yNKFcq9^dgK*MU8>zDtJ{Bcbb$A?pdT+)yRa;cE4 z6WJ^8{yrw_vGFWB;3iMRp1K2Ieaf)Fvywm5(qn%CczIuGzF^S7up)zKdlFjcrOL5y zPWf+><%!_~A7onMe#^06+2O}dxYr4vb;8X~_^1>9!U=D8!W*3MM^1R96JG3u6P$2_ z6Q1IP1D){LFP-|GaIX_S>x7$~@KGoHg%jTHgf}?hkDTyIC%o7RCph5x7$~@L?ys%L#9B!UiW?;Di@D;RGif;e@9+VVV;jzTd8QuL@a^+=u<3 zm+keXY~0=ExmB{%0x~iDVF&&$C%nZ88=P=~6V7tN$xe8l6Q1dWCpcl66CTDl6Fu1P zgdI-U>V!`?;loaNmlNLNgbhx(zzJtL;bbQ~&k4^|VX}Qa{JYf$j-sJ_{zl%0jcv(o zR{Hvy@q+cUx8!(4eb+)awx~BOIXvL3?|G={u?N&kot(_EJ}hAP*oSX?5!C(&bMX#_ zDg$J$8URFe2usFnC!8mtyiPM;9-On^#7n_ER!C({l%>|wfmlWvoBh1ruz!T0%#*{` z!$zDJp8o=z{H#R`b7n9t@)7e+*z$*up11smEMQ$@z(~HDtC-FB>>Qybe@z9q-MJGi zx5-oWSvURyd%gt+&D9x3Ilf}j!1(`6DmOE&7brD6Hx9*;$j2JPp7&83clA! z$~*<8}Wlkm`K5gWoMah^1dcN)SOMEC+m|4AdX$WmyCzkPP5bo8$9vs}{s zBI(2jl0?_jEV0$%c_bA9fRg+&}=#e(E=jej5XK=bhulh z2-yi)I(X)T%10EKBKRH^al_jL(_$;!PWx;O5r7zId>7ewbDF3{5_W@hcNu#j z;hm83fZp`Qh~Sw`UyRx)US%-bX_pexKkl>JBMH@xSJ5H9JH|8UO||1j$f|Z+LqxU1 z`ZI{^F8~+6MW!Uv^W_|+0PFH>1$h2m0azsf^7pI)X7OGHV87SQ=5Lv)S!Wy*pi2Rg z>GBUS(KH?@6o61>_UG;ZC87~bV|UyFrJ<@SKLde3Ipb7RDHZWe5%uA7-xir_;_|(6 z^|GvQOJCAz+a{t$ZTuBg6v=HOU+JB#PpkpYqz3EnEL_y`;Ld(r7zS1LNes_7tA&au zL7+H%9=#|1k&}+D5~^(;`L>b#;&r5D7`r7=p{n%kWl+QSg0lrR(|YXZitoAc$*P!{ z(zivK0oh}6m_6GmS^-{(gVzY2&)5+kq{{lsw5rFy5oItv%cTmz_f*44+>%^gM*)++ zjbj}zZHr}`Nz(EVx8IOyVNXge@%lh8T>Kn|MR<9BqqvnAARaBU2fp-}?HyZBy(*io zd3X(EtS*OihEuP9*+WwHGQJI~RN z)-sv)P0t1aGj%Ra%^YuCtSZu?$Mu&?&;3#sULpGN6@9~|d?w!`E;#`be-{!HZ4yDi z3Ogw1Z?vep>2kU6aRAnEp3q@s*-+DgI#O~n#$Y7I$jtf&he|BKHyqQ}yajPH>t!e7 zV{J_<8PFJoMYLX2zOqLH9k-l6d83cFPO$l0bAjE|Pj6P>V*%&#+x4RrWVZEyjrl62 zf+;V@WGnQETv0?aYu>ZPal5poUIAzPK}g|BH?`Uz4*{aBPksu3FCqQK1@Pgms#~7| zu~fYyWfg!Ekt-fZWc;Z5Yq_mQv$V)Sp--G>rfX7rpvW%7&X${>qn zjLe7jJ2>&kUdmGKec0y4knIvC3*SaWrREBCqzb0Iq7r`;)h90VfpxDge()p(6bg;gqRhLq$tyRz9nnU~OkC~8H zuk3${Tf2K}DW5hP!#=-=8$F;|mezZ7s? zvM6I8nqtrGIfzpAnw3Lo=XNaqP^Jwvc@4)xVD#0b!Tt}a_(w8$Vj0G8xZJRUKU%Tq z1ZxWm2?X@@P2Kv|)gdA$_an(&Gm*9?`yIn?mA!2Dh{u+}y^ynhtjJ`n2SIvg?K9%3 ze2(cs0c3RiR?)CkU%mpOH2-L`;->`yd<9Sx;C#q*>%AMmPU`w3w|1+Xhff+9%A*m} zen71WJ~0HFCEc0dO4U;1FouB=WyYm|+VUz$$?G7PJp}!gP3p57yV`24Xh&!*$~4=? zb8`X$)}@l&&eVsf;|a!UBI|;6DEnLtuo8FtVFYc*_E9Wg>&Rh_S_b)eBYn~4Ip;WN zF`>74hC8wND*)4lC2lh-gFJC-!oc9xMEir^=J_Tf+DgKrl*cryct$Od-^O8R)WA^Rgf-q;jW6=k{?-Oqa+lYCBx-&0lye< zI?cR+Uf(ExMk1+O*1cQot~(o+fv5%INJ$#+x||6V=;^tj53L zKYU50^Q4OKSAF;-(sNbvqBFlO7E-$ zPUgQ?g*AKrTPx96##6%7vQHG)1_4XWe=xf-+d+<5c&p$c&#Vy=HnYf^IJv&VI_4;p2EXG;+2pI1|9r zzYTbf19+0SLa~g+GM*kkq{tpxp_(z?s(%3=hxfhC;IESo2p|1Yi@s?)PA?`QUH}66 z^8RR2j!9`-zov|xpw-)sBGn!TH`<0Lb3Z1thA-DfT3^RN^#A+s9&l|!P zwaH)iu+^2lyMZ+meJ5zqcHx57>2#q9od||MEcEzeP8Q)Q?%;Cqs@D(~^ZejCB@{!> z66`xQIjW_1iPP~JDuBHDJBm{3!1oyn2*f-lr~lWyF!-3QrjR@b{kE;Aj0tdnEK=e7VgHz)zj^?fNe4UEg#elasRW zZ=8|D;r58bf>AeK98jj+>pfsuBR@<{^ z_AYDBLAoPr|Lu4jy#GvsD_S=3$eA{AZn0R8N`d)+t!iq`p?@-x4u zyxJ*$_qQb~#+29NSL&ql9sJ(qRZe-q_mnSn%Ex_Ad8Jc+;Ct#%mQVQ}{8|V9(D&dc z%cp%0euaZS_kSp#_dVt14*qA~Q-9DYulyc-HnG&N&+kf9*jv6=+QqIPeGk6hDQ|Sj zon$JQ<-}Hg4}N0`@;^tC!NO|&Cu(Cu&OPnzIGHSB?1?O$gWcq&!7uPOWSoxz-h3Aj1TD;hG?ZwNk zomIWCwlP@UFlBK?V`Fu1InQaVSXe#5TU8Sp6$;ia_Fh%LG+0|-*Lbye^ytw8z1~ra zyrV`fs$RTwz<>cW8*1x<-r%CzMz7>}msB?jwm@A5)UxV^Mo_x}R(qX1Z(V4~g6al= zTxLTqsBf%JK>{UdZ&mez&_Zuxup(H!q`EHHDDaDcUrYl44iI=NLk$g-EnexZ2nH)E z7gbkz{Zr?7D=U^(ELbcgmep2PH>S)W6sn<6RV}d4@TaV*RM#)9uB)wE=&f)#@mACzdlFK=w5LkZ6DGZr zmQ~kP)i+!)Vbaou`l?W6@PeyGI(gU9Azk?@b@f2lA5gxuy0W%rrS~$0dhSdc(Oc%v zYs~l7*C<)oGLXuaQrXgq;3Ds&1);`KOY0kgqorTHqa}JlikJeSDI&-&%qe14Yfh4?!kl2o>%eEr8u)d zZ>UC?=xbSHW2joSaF*nF8*3NVRV-etq+Cb0FRwmZ8dO_X+sIIs${VHfnowi)sEVp8 z$TZSfc7#^U_WEl=<<;IL^;Oj)y^YRb2v#&Kgmx01p{RPRp<+3d#V91(LciH<9_^i8 z55m%=i)$;D-ALltX1OEkjIt7d}E_xukzb zjT#Qh^m=bq?ZVn%Bkj;kLe>2)T43Atg3(3FCQhkey0W2m;i91Tyn=#p zqj(f~FRyM4GJwk~7cHr+3Xb&Z6%7@OtH@qVhgZPw42;^e`s?Z$u9c$)b|+C-0Exo$ zy|e2Z=o0T`^^2>j>l99Tu)3xqMRee7nKdwT3mYnyc!^GJsIK;w*VhDlQwb7q$YuJBHu;l129YnE^N>?;P&TwGnj^w3Z(X3NVQ(I|#@Q82i4!nx-*)`uD@ z#r!U;9$i-*Ja_52$wr?WtgXDRI@owFEx)2Zhfr)g{UaD}0bJE`s6%eie?wXlXTvICQ>KIcp0XoPo4sLR45V=AP^N^YR2eRXQcp(6>{d1;Z;d)#N>#*?<%{Yx}n~M z7f{^*d8xo*M7)kr;{>nMV88Ms82s31X;$r$rHhqQ;>FT19|`bCFCJA$afu}<^9M>@ z)eQ~kO&5quIWyj3?{J`PEJ?_%a{K4h(@>4+J<7F%U^cUi=Ol+KzpW7bG-C8JQLVW%Aq z11i@M2s|)mrkWmGrR;oy3cIcE*8Qogp`US||Jdh39uv=_xy zo?|1f`r_W&GE68`EWkucCoOFNv_8}bRAs#=FI6Vz30GxB-Pz2=j&fb=n>=IIZ0Tvy zVLG~=p;i|XrAl?DbXvJHM9v=Gc=kY-NCnDELUl}`$^%py>9V23#>=>waS3LQ#kt_i zq@C<)Nq^V4PmPCQsG&~GwKKKhIAA!3*Cq!}(qFRkmxNHF1sFHw5Y$#zxqMYWBJW!S zu){)Qcxs?`w_0k}AKu6$-N3|-wMGD?GN31Tr-~cV-JEqBzP|q?r`EsI)ChyPUcH^ty6XZVTkmPdevRrEj_MVTyR^v z@%lI7_c`fnC_9-e1@iyJjznUw^M6gZxa3KCGXG_P>T(oJLRnwBWF6^p`oQimmn?l; z_5#OQ$hf*j8#4z3QRx9umpyel{*^1~RJxS#W%P8ptWIYVh_fWav8p0iVLKC|`Hr^G zpEIYp<|tR+)--QbNSRpMhjR^_iVsj-B{sXVx^@}rQh^c#SsCHC46k)OcBySnUCOIZ zPVLDhhD{6HZp()6;A`d-(XTGhjIsWFh`EY)ngjo(?;eFF5>s3s`m1d1~JdBgFm zyU&TKjO6fkq#+hcq~};LS!OO}AXEpjr+C@lCk*Q8^1Ec-QO%O7v4{5T)S9j zbCuOC!$+&4hZ-vzYL^BX#Y$@&yChDkh$y8aBbCD>*>$$?YC?6DVh!n|E*jXsY8LoP z5o``9G zuNuXyFq;1WyByz6C{0xhB(cv|rEss7nW9*dBZV&dT|7L*G*z=uh4e*@iu@n;-UPm? z;`|$*bMLuZHo}sy1mqGE3`ige5E2ATNCHH&k%Z0dk`)3WiCI`xP-|-yEx47oRH?hx z1s4>TDplL6wU(-Nt%}yR+SW?dwsz(HexI3hH=?!u|9lGwi%h*19dk1>@&9qVv^i5i%;$*j)iMkY$gGH(dTfH;! zL^s~2@bYLuPt(@4z73TS69ndxT8EKhZd)&AF>zkek9V|pwBZ#4zxXlbdU_DzYq+<& zGqkR66~=GoeaLs|r^tn0mC?c&N`*?x%Q2>EP!;v14Hcof(uEbOy0oDoB)F=tC@l{y zsi~{4ZLBD3)Y_G*gJBOAwqV}I?7X6lFt3HnT~c9U!Ft)$$7^~8iC}m<)jtcke`X$9E_cZmQIp{VXgs~JUG5X@_lNlYdiRmeB6=r)L$wMlHkZ@#12 zfr)oSG+4HJpldBMz8}%$U>gy~t5}CIB`A$02m>*?;0q6)HXJ7*i9bN!%O71Q-d}m;|Fj z)+x{#F3}Fp#LO5EdZq+b4uWgbQ+-U?l^$(L{xg#%IUQE`Jz6Ox7`7AW*??K3;A_ZC z;Y=7)BepDzwOCy}ujpU5s;K4GL$vSYKH_rb0Brq$DrO@VhSD8H)`C!h`{BUDFLsEGF|I;ZKmziBPrgP5hU^MMz!W1|ngsKw<~Okeid25>BgawH+|ktpd!D0j3iC>A$MIHjU2i6t0MT9d zwS^pCN>5Khx^r~mL>Jp)+ElM9$v*XrX{Tp*VLUVd(=VH&lq$zh=p*`&744uz1|d2r z;bE{Wi_8x4ou=zqooS{0n|j)U9WV;_%P=QM+kts;NM4z49o5$<@&zzeNmn7!NIt0o(aPG3w%EnwV29ms_PINme#3qTz9likT^w&7LQDq|_ObktY`>x_$}KL(X8PQSBIn_21D%(2EOUA~@7 zNxU6-ibU~b7TS)PHhL0tRhTew0VCJg!&-t^YSbZ`eib1`X2^OZVP(qYD#M(P-QVbLWPAo*r(vBIs#Cvr3>ySD}L_Bh8hn_)O5Rt+%y^7$h6dBo8tRdn> zh*7Swf|!*-EQr7~-xuVF8AC~QmOOq)?$Eew&D^pDP;Ym13Gi?8%VODHXdfX+8txo6a zOxmO6d%CeSiC3}qWb_ZV&Z+Z@@ACLOTZ>mPhN3JCtcf;ZCTr>$T0|$R2Uek?Lv$LM zlbKQO_D4$u+iToI#tk0O^it!VVcde&fDt+))Vj)ltN<`m#u6mf@(%rJcih zuZNQsuDQ(!00X^x8p<&G)f*GU-qF_&^P9ZTBmQN9Pe)ms$~jQL_(?}!atTd=$!P9a z6%}q@Tbo$0o3S6Mi?d3_Uqr8rH^SMX%`JU0U(gxAoLXS$kwwKWk;281- zWiAyPUlfZ=!|27Zh25FBgfkx92HHOcsjRgfy{ODsrGqVZfTNTk-W+;?y%)o1n0F>j z(5A$&6>c2{(U=~>^6X4nOmfVYAq?5cXu_;<0~cOVWg@Y|y8=Zo3)d1m#?R241vOEP z!7)~N5IkC@tn{E6qIl8g*LC;xb#P-;Vk6z?JzKOZ(v-|`J!X$ z@4z;yQr*$ch5u&Za9`7e{_lnPTeGQT3D!WYUvMgMc&6F(-{sQm1S~hnR+ZTS z$5h4n$RPTe6VW;IpX3UHX}}b1c7Vf6WQVlN!NXy1tFuXGcfzNoH>wGIW<@~Q^UKOj zzpqm{V|fDK>fE=6m9Yp-?@Ws!(JMlV$mn_C8K2Xt6~B;%m+bNsH#^KF>Yl=6oM z7YDvE`iXVEuYJ6xXXXtp?_GCg>(vDpzLs+R{$Ff5=DnXEy6~0fzJ7eweSz^k9$)Q+lmN>~28_smt-{_Gw1 zoP{sgC;#(;%GLgzH(Ogw4qh2mw$I$)A#4*w%@m-^cU;BXTD}V9DHuq2 z^XN6xU)cZdwNLpr&iJbua_P;1t48fgdF!F%HCuD%uJeDrvvsF+TFb9LUc7c~b5rNo zm-E^#s8P)yzJH~+bIT1@#`iz=pSSFZA%FVeD|_4O-n)O;Z}&fP@mUu>@Q*jgz201z z`)b-pXFb2Yt?GrpFK@cL`q{<%X7{UyuX{W1p%+STc=M!}u6%j!x+i{i{og-+@%c6H zb(H<%m97~JE?jl{!Tl>=?aQ^xe>KiMJyex&>r-bXzdq+oPu;DhuH#Zu6Ce3ymFiWzFWqpQgO??IVH9kGn%9+;z3@?DETp9DeRP|5sLjXdUyf$GjbVETqzy9@uM=mXU|3J?B$~R58tf)#wrbhKH@@!OcjC!~cQ1PN_~e(XG7|3m^GWW)m7DF- z$3Iy4=8`v8-Tc9&UHO|H=~%G+o~9plwW&$t&RKJ-AkD|6aJ z&yq(@c<=`~iQl{XvQzFo-d=OhX*V5t>9PEu9^7~F)vrt$cgGv2?tQHFTN6KQ`Tg$e z)(j+EzRq=vH?aG}!j#`#u*%mve3|l`chaL*j@Z2a?K_UYYfDkaeM#TC^tsEDANl#O z?*HHyXH9tXwZs>md;ZJw-+tkbpWO5M>aO!&9siT`N6tNU;sbwvYs22|4GZrd_3Kmo z7xt_fa^&d~yzQqYT0@Uq-S)MPJDNXv{>a*wxMg@No#&~$1hHK@s;+(H%ktm@bavNJ08B}2UkDz#@3(Sz3{yw z`|`$q_`UC4^w@(>=UskJ!;RP7o8>7y_~7Ni_Ou%x= zYpY8uYbL2Mn}1#=oI7lJ3hT8uK<@gCH33CDZw(u(>8Rkh0|VO<0-Myxn= z;=Rf#2Mvref8l1v9L!N08bnj0tkMoH)fkpi(l2AMPRq3!HEF{thJ`ZZK>y9zB3`07 zOKQrUSU4|1nO;h~Lm26;2AVU8D@h!pWcTG{uY$RJ)udoB2h$K(QRV_c5BtpaBS*&J z*@kC3p51tE!}BnnYUIm?+zo{@!aEH(!NW)gZvg(xi!PYmBU2+RdWt;~8+K*YQw4)d zJ9_&EnmQK`w83npXNNMB4G--wOTeH9>4It3IhGOehgS+$%p9NcR%+qK5n4?Yb z_$n4pP1F5^6KGBxUKfXNi^KQC;Rn32`hp3u_^3GCABU&L;VKyGKQ#^?6^G}=;U#hT zw>K_+JDTJ2!9&mzDja2McN z4Y&^OZFqVB?}d9Gp0fZSfIAiE`o9D?5AJXAYzKT8?igGzunTYy?qj2rdKmCQxC)me zya1T)<9L2gI@}Mll=_(TY^9#Zlk`W#4enOlzcLo^Hn_jSlLz=P+;fk^1wepzz~x;KOiFEd)*(xcAIf>Jz{R;HtUE%MZ2N33x2v9=KQF$pO3v z?u&S)06qkF&3vV1PzLU;c&Y&Jh5G@XM!<*RPAgODG{AXq-@wxf_z>K&SkCML9E7_8 z&ql!8;699J8{h+QFRwrv0q=qPFrMwC6JCJ)BMkTMg-Tsd817qm?ge}p?wyMu2Y4^s zFV|u22zUqFx9Sl-W#Fba!UY_JyARJl0QW3WYUEPn!AGFOEym*qTmp9hPb%PTaDR?x z6yQT}|A8k9FfVHM;mHA<3Kw<_H3e`G?w|4GQD(VPf5%focm?tYPaWVqxZl9D9Pl2v z*Wqaeycg~t@vNpi4znlW=>ePy_aAurNk3I7H=gaJ!ySQV2jC#wEId~L&V#!X&o01w z;2t>*`36{>uGC*cs3(M1g5QLCLK(Q*o0WPQ@D8}8t*A4A>)<|!=P=*{aA&u{-^WM~ z++W~H0(=PWgYAe1-~({q#50z3xF6yP0#>WA*AY(^;5xW}z>@>`Fx-n*qh0~t0rzP< za{wQNdnzs?C)`rvc|$AURJc3v^aG|ly9Z@R zdAL~{kY>PnaO?5x1-ugOHazYO#iuZCE|l|Rq7(%a*yvk$lq28>J&@}7R) z8G&|yhjo;0JbwiG`YCwGr)$|RkL|YVEWg|1FCY{}^SG3!z{<0Hw(`}x^IR*f9?R=i z-ey;xwGwi}6Vz~Pyh_STT$#`lsPiB29<&d+4qK@Km3m%074oECI|$tgNA#U~v_8K_ z`J3%L_exif#4pLGlCF);1?XnH=9_pWcvZsP-aOAryT@JUI$$~aNiT?^GmlgJDy2Rl zFR;?zUYAp8+9Q%pX1BLi3jQPqw<91 zH9xMr;{8VJb;7Ghc&2`b-FP`Ce$2<-sC-QDcoLrTx+TY?PMfwA@1OdaUg}8?sPqfH zDit5JNL+0z@7pGCoG|Fpf3u+vRu6{;JVWnJcAHvqz;n=jNVh2yetaGLv^rgnvp;8t`k?&&j9`6_c?N)E|oP>|2B@Z)P=)= z4~@`%4_Xnf7Cab5d*K*M`O_jYj(@rb(lz~6)#%(w5S;pOA+CL)}LkE*~UG|xMvu* z$GGPiceinGGwzedJ!IU!88>x|(Qn*&#;rGQk8w8|ce`=FY25pa`=oK5^t^2F!^Zua zas3%Oyivx@GH!u!=Nq@txT}rZYus(dy~wy%824)9-fY~vjr)jke`wr;#(mYeZyWcw z#{IK#)mRU-5ZnJSajl15s+l+gWaj!7$ZsXo) z+`Yzq(6~<+_gUkEGVq6#65r0X>O*gJnZeO$;oj+f+8=Vhdv>Tld|E}F6 z;E*;iM+wQD9-;671Eo?T9G>Ndq05mp=Omr;k7|s=!QQxjb&P|x%g&Tu%~`He`0^vP;f7)?J~p(=^y8--@YTg@MY7Zn**J_uhTqZ*?*yga}} zr%#<0&Cyq7MI|uQ)YsC1*?q4g#fxavSq{c+a_T$>!+t|}tFgbW zvuzO$8+Epo!Z1Y|m78r4u!WG)z;mqwJ(XSU-KFYcp=`q8lXZvk%%3Z}H#PMYHh+8&Rm}5&#*mWYxuzlBK*Y|fKUJJ|t^hP<# z=q0tRsfU|Y%g|78G*Km!R@L3TcA&=*Mwa4Kwi-c>*}$=+3!6caFW1=(ZT(BSaP<)K zptWLSOPd@}L#j{;YOmeU+1A#h9XMd^^b=Wq6 z!mpf{Rv$VPNv=|}R47yya?Ue^bZk&c3qZ%_i1kX<0K%Pz*h0%zzZlr6wtnsb0=rMu z182o=>sqfG2zNJ!cu0Z9z)+|Yt$4lgX}k-uYKCyaC8T$jHfst_WboV~ciG_luL?D_ ztZVJ;Qkwzch;~SVRohjlMMJv*VgC<$s;5*4e!9A0Ay*-83I+IgK>7}klPn1snYm8g zZ-ua%Wvw~@m;0raYH@{3idF$)TixagvC67zT#TmH@e<(v-qwL0HNqX@A>qOqYPvf# zfE(PP?Im|eHk~Wwwe`uAkv19>cuHm2I<~Xy_8wmE*sh8J4fMCD+2Z!8xi&gZgg1{a zQd4QS8*McPj1mMC@uCQD2XJ=js|; z-v|e*pWSCX+-&OuXIOQxk*t>0$nV<)TGs;$AtB@^+vvT7k)KN4PpGQ}0*?{u?}mNy zaSaW0s+a8bPVzWF;~eRK_|fm8TwI_a7jLQ&(Eq>voLo^~Q&Ba&K!*ssFT(u)g*VpD&BS{y6Bl$~ zV=nd!&&^!YxFEMEljmQ%TAMfoo13|*tuOP$c?olHy1H#$GY-GQe^=k!OkC?WyAMZ4 zaoRq2T}MlAcONbR&Bb~B*-d@xrmoM=#5sKIsK$BKrTV;=4s0H-hMm*ji#y#o%Kn_n zrf1R{JYsh;?$zqwq)`ye3BPBht>r1F}VX8AQ4_^kEA(N)i{?hE;`cC#Y=* zR<_Q~+|q_yU-M_ooRynDb4FqAjOi^ibDL(ix8>&L6}7gtwM}oG-kx`MRQCM$ahdg* z@t8g{e|k}KaZ~Qh)?&n?y}32FsI8zix2a&pjJ$$^neD~XoBn6wQS_Pdn9)?wUQpCF zJ$L5x=HlELGiK!HHa8Ww z_srMwRi6@nonQaD+mS!8K+7*pR`NTrUE}(%rbYkN;XU=V<3HG_C9jMYih{NLWzRVB zJxjFwQ&BR}pq9^g-jOd^s^uS!7K(z$0(Pm#Uv}i9SORMPUtj+;z7FrcH^O`~ukghy zGPst%@|TW$s*!hpru+%Na^!mU{{r?UvUCD{Ifp}^UXZxx;Qxp)%ptl z9+r0)#?|`X|A)ihYxGrpO8m6^b~jdBwT4qm#Qp5_H(+&K%cmN7Y|$C?r}ZZU9QiyW z|J0|{XPv(9ViohV@~Z`_j)uRoM8Ylo6n#4U)@hD>U8|N~qdTRe;;h3TTja>c3uyie zpUT(a9V&MGA86O%o%EUU`x%Nyr>AbMmaj{S4_V_T{L>xzcqtwJ&1X1#=X)+0@q+)C z@crn?b<+LT!kQ()vf^TW{v?>Y4u|@3*Y)H0`P@})UAT4yANW|;1oPV5jYWmIWUdP4 z))wFk4E?QhS9J{(7ptVQ*%;XNbWh_2S#m5e7nYb@e9vH7UvEo<8iB~4W**!|IJE_q zwh~Eu^c%=!d0SRD^(r@y-G%y<``CveGx#%b#I_TqRl=uJ(tVZCzoi%s&w+H`|E+JXae4_{k)79INQ4dC-KD; zAus4`g07Q z(!iSz14dxlzQv(7vUx$WpDF-N1|9) zpz(7B_j~K6Yy3RHQ@wRFG=9F|qr7!9HU1^RgWkGAjb9*mj@PV4m;`^>%Z$kLR&Olp z>s9tw1fAh+Xj@f=)LiJD2W}D3a-d%obT-inpce@`hv)*J7YjO%=t7{|1uY@k0Q3?; z=X)zmz?Vu$<=*n%JY|1P;> zAU)ptrj5$JQjm?_`W7Hp39`*w-wNdGf?VjWZw9hUkR9Ioz8)03AiKZ;@=ZbZfYYJu zZwYcU6ad*R$X;)K5eie_{oeXwWnV4u0dIXiQge+UPXa+|_6Twi2vYMML0$%e)Lbjb zAs{o9eVrih0-34o>jgRNt?xi&ZV=>?g#7_jSSxWUmgBm6osUZ?`w{PN$#5G6OBa{d zD*I9Kw#QB^=f|DG?qKyAXG|MlM+n#AVw! z72d@Dg8i7gs!sdbxe^$9Gt*Z|C*X2y@2uu}?~(M`e$)vJk%Q{~iKLs;X;%BD>OhiP)mj8h&%azSI)W zl-GWKX}w4V611kgV==I#sD7z-Nn>RVJU`@`~<%r3r@q-RNL=9nfA9C;z!uvIlq0(LZ?bhxAejvq_YD?#AP}`q?;pZ^hKNQaJ zPY{JbXnA#YsG)ReMW___9ZxS{iLUVuU<@Gr5NhhO?%q~qua(|Gd9k94yTUcCQ)n)4 zW78^4Sm$M=Y;Qe|=J(=KcC@Z8A$h#Ac3j)T1MAA}7LQ&-lsjIP-6Q=CI&-dIHDHCC z%}Cj2ifmF?CmLz5kW#$mIDlSjeD{g(RG~#Y_lx9+uxB*t0U@P3{pot~H%gZZQ6 z%HANfvEBu&*iJ)654q917g-$iE?>7Uin__mQreT~BpQ9iW-kkBkEN30bJyPDO-J63 z*kjqZcyC6(;9Z0zL@XEEw+f01(zdFpWs|bM8wm_O)@@!^hdm4$nR>fmdx;@C?hxz% zF{JNK!448bO!f+Ph#0!9y97I&2n_x6-GZUV0*W5`9zjzDMdx|1pg}>=f9?}BPf&KD z_X%F2aYX5U!Rs`RNbMJVrN$Ah2L$iYI3o6-;M+8gs68b34olZ_cBNA9EtQ4}d82fp z=?gmh8+d!TeUnsB;3ywWxmhS9FX7l#TF&1b4WrRWop-qX125a|kR7O{8FKoA1_XVy3Qx8$@3(Nql8xyt|;PyRf zPWJ~GK|k~~f<4M_-<5IzKza?gA=r1P{D}yzxLA*J5hNz8`ig~>=_RjpH7jXnI}}!7;3DXuZrx)Q{IE0$dIavpOdhk&=F^s(Xw_v?%-1P4@8w;ljMeK zW&coUsosWx<_5Dlq*>WN66&bYjCRml+Ka0wdU4(B5_Bwe`u=leKO-_Z7{GM4EBhxB z2~Mq~RwfRHCtS&d8IL*=y%p+&guy`o-~*!QP(z+~ZV z!^I)1I$BVZ(>TN;p{2PKulolCcM%8npkOw!-cCqAB)C_&O}(pIk=G9k$qy1H3woK~ z{+`ehNNd_?Xpaaj2{dfbu^$yIg&2Z4AXqA}7JOJq+20p@7;uh29usVYaFzYIVCld* z+nXd(PY7icDBbI^#lrr9;A4Q}vJsSkqC`| z$fX?M2n08@p<1LpjeMG;hA_Lxl-A|e_*We~ppuTtbNk0>BTyzub%SvphELm1zEfHY zDyu4-;u>L3O#fO6N~aoMk?iO~6+13n7ndIS*S4G8QAlQvaPYdqHW1Y8Hq=Y(im)f8 zvpU;eQ>_}i8#b+L?(WpPgzU+}^_z(V)Cm*Xju%Ffmp6~qw%5wmpQcWyH=iP5rFzRS z_iDl?1#!0=_G-aft}uoa<8i@McCtl-;URQ z`EqypR-t3G*9qeG{fwM09j5PDa=Hca`?eG55hTfXJ&`j7N%a-dPp=>&yzCch+jU3N zC$v$%{S@dIWUQ~1$bcY0UkZ9}d%Yl8z7MH%gG4dMcQ!d21)1#o5s^)TO!2KHvRRO+ zzWwyGMUXt-09BtQNP%x3#m*MhGklZDIY*Ep-#hfPRggJ8cCPj|K}y7wXP+wy%6%nN zaGoFwd}Z`=zKAXIZ6@+1L8^QoP{9R))cKZ@^JPIAeYa4-R|Hw^8%yLuK~D2sK|f!W zqFJeiuok?6Qj+#HB;0J`3KK&)`=a!}LC*Fk4f)hE$9Vg&y*vH8!y={rZApXDrG9mE zsb3Ra>U$(|wl4MW2x3b8T0u;yUnhtu_3H&0p-cFNbdG{Y=@PzCIHrVe62z47%@Q3` z!nX)wO88bmObLHi5L3dp31Uk4c0o)D-yy0^3EwG*DdD|>m=eBA5L3c;ivm-^_XuK2 z_+CkZDdByB)aeqwPmtxhgzpz*r7q$9qI$J1;Rgii)Fu3&lyHyJcH;^ZC1pR9u7*ZB z%0UHwkCL?g6bqQQ8{T~S<<2*4yCMAT0sDE0h4OMkrqhGHApNTCjqllh zE_G#8xZ1^Nw_i-}gl^maA!6b5=Mf2I|4PDkIE_^ep|aAds`;g5Cu4Ru=4SDG2mX$E z9Dn5XE`tq$p!O+Hllhu?nQV@-RK}vpnuf;GnzD)zCPAKq{{Uy~Ko|BTwkpp-PKPin z4a5 zwp6Y5kLO(gV_TY)KPV%mv7J56LgNUfQlmT zEbYfff$@1uggu$`BGSd&=0BeJoUt1kR(EgEi{Q#Xg)i6=q|ZrIf%4~)Ha{w%piOND zZPD1(4gIZ^UD)WT{L_91N}W*f)gvM0k+fV$GVxRXd{R~_cTA@G3r;~!N7IzQlG$wg z^H9X&`kPjjVE|s)IKQ-^LfLab3tTxoU8!RtaI3Mf|Q$MLDX)_@$Wh)-0*k z@(IfI?NRWsv@ujsUDvomgEdR4s+2`yWr1>uJ43nY)}uX&TckX6%T_2aUA%HDl#kGS z+9do!t8Az%ZN#1M0b=@!_5=~3xh0Vh;!=rkx~e21OKMK8sa;m1l8Ka8lwn|0rBaAg z=BreZ05DVo1!|ZEW~kvJQlv&`LXk=n0@S8!3ZRjM#I`bu5VE5I`JzS>p*3a-lk}vIwK1JXAaXB;GMs?np#P6(muWBeQ^n zvIT0PxK#}>EG;64+Y1|DjD}AWTxF0xf#{eV8A5!i48hPwiRhf*wR{jP z1UvCEUJo)BV{F;doOrqE)A(soZm#d(_&o87`yrIsz)=G$f8w`uMxz3Uu+y2FyY=UF zF_Z!&jAP{jH9Lxc9@C|crH;gF-hsNL5UMQfZb?6K--zat6_WkctNPB|z&WhzDVNyk zHX)#FV}=2ZM!|`=Rng(A<3f!U^Holba|EHW4b!`uf>*+u+xF9UR;ZE(7q}(6t+kB% zetO$r!^GrtRhu)}b2Zqs<+{8Yqp&dUF>>I2*pq;%N#ioQfb6m9n zMTfg8J6glb8P0UxI@4K8LRj*%cAt!ewp?6&j~N~>2UpgaiKtsveXjEb0%i3IWpOTd z-Yct5u;sb<1UayN)*@>~Zsg5n4g3bGT|0wns(j!8GuJMBqp6kW0hD#RB*WT|P$%|a zK5d2(R>-;*bDD`gbrlX}rPYfU>%^X#Moqy$)oQXhppDQlP_de=A7c=qrXdBP7JUT4 zI)|C*?9?qaiM4j0KNhbzCU`_@i6ozYtZm1DoKLV|4S3Vf#vlHse+>X9A=9q|&?B@N z1IFi*SxU`>znNCORiI{^Ysk-oT&>Bjz!6n=r=hci`2$8vE>+=o5Nf91Lf_yP zo@2O2SdlI=NNP6jZh{y}-_?&Aajl_ef5hLs3=B6v{XPI%X?$~PEdnI>9!sB~5V0=4o~;aP^6k9d@S z)gVofWc4oGWe9V?opHTE76Q3M>p}%J4Mi2+V%YUy7alMvIi1M+2I(S_YErTV$c!d~ zYzOkPiC(RmvDJ{j4)S3gmm+Jin(~g200xZB_ zw;D&Jq8reyte}UCe5Pa_+w51MyO=LL>oy8ZMFtoC*+}h07=?c~2phLrz=K!OT7O7S zsb+IoMC6NW1zcZJ$yHPU9zHK0G6%w}+(MyYCvHb)YfBTxAl3{m79JdR zMSGKemdCIX*YnNmXfwyt61Ol1K;%GTJK;wb895q51V@!DmO zu>GgwZ>8wQ+c4A&dln|5)^W6WIw4}eri|UJ0-XYVz|G2MWQW{}?6?j(PNMk6j!=`b zX72*7vCYalf!GkvO`Z;mwNPx%qeiSH1hKgWYu(fp>hJ86#D{pAjbF%CR*C0Wtodyp zE{gTZIr-p-vgVHm$M!P-gsEBhN)oy}G8XBf2MSyt`m-t+>yw=!364Utu7p-s;;Ujj zb*Zd{oPr13?*>YxjT|M~*;BU8yk-{hH4|_j`ZUol&O0HktV&KqQEPUTh*CsU$E&-u zwQXZdPk;E}qjgFlW{M|kZV$dJ%vWtYGZ_sdXrknBdoX$?e-#rSaQh8^QK-7IX5lhS zTQCW&s=^Fx{*r~E>e9wVn7S#egE>&8b*!s6G`GK8Y7rBli`bl)I~gh$x@L zuh*FKfW{dztJWM$G*0RPtIixyG)^`1ijQ?#^|f&LSdUj*P{$|rtJN2S!pE9agW^Cf zz;RG$^{LK2npLH?{aQ zY}`@@5Qg(h$NSmYkM$qy!1~-ftla+12+Hk$9Do16@33-37X6(q8S$(C`igQDbkC!4 z-osBADt8HC_E zJI(AY-mMd}+e3Kyg=9{=9bN^WUO+tOZQySIi}>r0Gvkosx$+oPg1~2(aT3C29Ljr@ z>t+;U0JCmm#v!Q9ID}}%5f^40x-{d63o{N~nsMlAGY%nb#t~ZBj6=+raYRJSIE2Dx z93o*e4w0}KhX~C$B0)2b24Kd~0L(Zd0yB;#z>FgVnsGFRW*kD=j6*1F#vvkR90E~h z9HNdHhj5G;hXiBB(V#Zt5O&NsgdM|8Hj#)KhgignLrj}-2svgP4I48~gb}gXlsgg; zQUysdW*ib|#t~PWaR?r5#z~~lC^HW6uo;JlW5y9dW5yvIWyT>IG2=vGVKWYC(PkX) zW2pB@KK2`TxF0|*OeUNp9m%8ar%523bO|8W)9%+uAe>+>?9hj|Z8kL5G4?!|e*#sN z_*CTlP{We4GJdICr5J)#zEEYY+8RgEpK`><%AS6fdn{jtnizOB`_x1w+PDe~Cuzg_-5g1&*1-ce5>zsG!JQu!N*2ejgjcD2aAbawzsXftDlQT}Chs2|G1 z58kcC>dJDKSAqw3;NS`z7k zHrmr%-L$a|1ApAXf_(vbxbBnmG4zND4_^HK7QS(V9&D(Ab=c5aNy}mUmA~yIq%@DP z8CxrVJG-PJ4?p9s{HvHVC1_X7_SB?6@=MGq`7F2!q_7WDNGd`r3wiSaQn;JXNmd3s0^2wm>EjNEz|d%)|E#Mg()8MS?rE)SslVC5VzG>b6I%SiwJQTCKJF}TEkk~+MDpL zrWm2&y*SK_le5^~Xr0KKHQcBuk=ijrZZ!$vyHeUfeZU&(TwK*N5bEy^b++XfD%W?I z^X?O{0chApU>w|~xm?#x1tGn;NV%>jE4`VbH&9d!hwZaRxo%7aU5#XUoeXHyhm5uw zy}AvXxU6fP<9uD9@@MVN#Dsm!v&O38>Qfo-8Mr10lOHsUr7bpZPYK0=EVlB;!WQR$ zS&jK!lrL|(7ND;e9bc*6(L~3WJE6s;#`ujW13Na#TQXuIfo;4l-W&F!jGJmidk_M| zTz&{0qYDbX4(zMSx|A85XXG9P%%8P;40eu;mqNRg#c?&Va(vgiX2=u$Cr}(+Z^h{m zW$hrvwR8Cdj{U8jPXnvO41COjs5qZy;B$gXJ)q+Z(y8G0%zWD z;2rRq@gsv=59Ci;k2PCm{LGM<&Sb<~(z-y6c{QR(9m|@3*bpWw{j+wjhj`Z4!MXu) z&bk)B9|2_F4*+q?eiE)#H!g8xiFkNCsFn9c#T}f9I#1bqv&)7d&AJDAb**2_T0fkI z9T;L741&GZ%4(F}%XrqktFq3q-U@p?N1B51x{ZiBPG-v1+bp*DgQeE)0hofvYYU%9 z%tbFu9Jal;-$pd5&;d_yzH%IrUebDps_sWmIl;O8%`kq&7vL!LRui;I>euXdUH~p1 z>BfuH`VGe#?wyCv3AXgZ?C@?mf^+XYbdG$sQ(5n^pLg%vwv}~7S-)ih+&kYrXF@x7 zH*!ZIZK1zo_%}fH1TiE2o~RGaVFG$>^eE;kHS2xSC!owHv_sb)h^1k(l9AFARz&Fo z=IPgkA!94}?`+znti$y13F*DKI1KN2^d|hix3d1ou3$xK6vuh(S|5`2<)P^P85bF3 zSx2m?+e)AdCO=YerCrl18Z@j_*W^Q>J_Lix1Xx)A#sKdbhTPI|gOv^TCqrkR9nY$_ zeM&}>o@^Xl)77% zZff({0H%;RjWs!!)%YHe#?3bV*uL3Hwn|0DI+f9TlHu1;?;0ju^v)V-^zH>Ph0KWF z6d1%Z&yUh;RJ~$IJE&^Y%Z{pih)aW81z-x95mmIUjY~LNCoK|1Cvw9K=P)&HK9+gK z20I6qSJC(ufGK1~G}gnKn^_j65uL~rCeL3A!fFL2k$mt^Q5nCA;)Y_mv(>mCm_*TU zl)u@C;_+ij%D$GLBDzK7e>kAu;!PV2=PBmtjQXR84{Jj88U~P>Xsu zh@lRu0)tvFMa5nd%XtTGC?Oxn3K%PQ7zAs3ctfa+7Lx|PsIs*8fcvoVqB2@devn<} zuzw$Bf7P%b4=U9p?8R)gx}VPYNtEYpj%W9cItD7^0+TB0zQ$p{>F6H!y(l&k6>$H_ zVW~V06y7y_EVs(fT3`)B<xIN72$=&;oB??UY_41WiU zwTz`v^{yVCaTPp zhCO5gWVae51ISSH6Q;Z_H{|0$&J!|nec~-fMaH#;T@3ajVJ~JC%6!t$%R$e0)gaWd z+0n7X=s-AJX3PkDN$X@>zu^cizSW8AIK!@`!ZL$!=yTAK-DYH+p^wX-r!pFiB;WYI z(UN%MXRbEnQ>g807wAA3GIw%GE-eZt@sTKYfy3S#X1{FM?ND{Hu$RjMXU0FH{H<~P zsc?dZep!dgC}d7B$eBb=G|1UR)*9qOAQ_h#gfab|qjJ%AwIY>yqhVi8+3{c1WXith z$Q~OGewtxl1KH`%8e}Lc5mUc&*Ev_%SfxEiWn^EZ)iA4P8@BtmCiPBMTPLcFLL1E?})nGTGRKI}w#)J-}RC(-qB@KDS}NdP9&S`O8nzU|&ke$w-{r_&;>c$FJ&Jva!`>5S&)%kE%p$za zVK;}1yT-7k`Su%xA-(L#?h4CZV%Tim8Q+PLwMUx@A8FHj4V!Ixtgv;Pe%8>XO&^NV zQRC={Zqr*4(ByL?30UU{McVW{!9(?o(_&FPsd9ZRYhKiiw&JRW(pmh;4Vi;#${3LQylgI z!={dN5RX@l5G(mstvlep;r0^6A1gX5?(fbkA*$GjuF{$~LHW~pB_Lu8QBbKnG}+}p zNo5W{zl3DPdY-Y>^l9%SlF#b^T>c{}BWU`ezk>c3?b+V>QJnFm2s*e4}rG? zyeyF&?gZ;A@aImr&q7~i_~XFO*Lg403(xVQdK$Sh$bCIpPA0gH)VZdEWa4I$Rry*hDj*HL6xHhCeq5tIdRCBu`*x$Vk{;B6-H7RtgzOJulqWmwR9t zJu*gRWEeRX#7g5G6M$?(rdBjEmwy2)M++>aE`W?!j?!ethpFgOoQ+3D=QA)5ly%dL z7ZHJ(FlIILYGW(+aiDkssZzLL&{)~q-Hn;?G}=uAZs&W#GqrIIcipX4Rz8&k+|IXw z4bPd=7HFN$mwp|e#$0Jl*X)lkD`AK##0xdFAi#T5&HX_~F&5*|Eq_ugt>Op4=QG5frSBEje^XDiipN2o&(L7;uOPu^=rP5;pzuklEasXZpM(i& zXbN6dYLX9e_-{6uuz}+|dh6%hXcB)NT&^DpHkbeW?`$?X4}HS_jcq1zyFzSdSBNW% zUs8(M6(T&@72=w>5784`c7?cd-U05Gk1x6X*TAEP@yAE{Kz-D`7X%++?^F_=c7LA) zf&Kdcy8YMVum4k*dF{+TG@pR8%xfRJ4C27!mU-(UFNl?km^$jtTbksm+7?^vlS%{vdkMxbC!9dsL-UBd1GlY%e?U{z04a= zjauf7WyLM?4$f4*!Rb-Uys-i?%e=8HXPGy=8qQ^2Pwhv@qkyx_>#1X{0v@x>>sc(> zsioSKr=CLofV0f&X&@fZ%j{g{^(;LG^(YWt=JhP&VxbC{WnRy6mRCZ+Ec1F+5KRi0 zWnRxIL{kFhHSIZ-XllT*H+xPaJ}l`ybTgjQ36BWGF7tZMV2w%-M3#9yAyP&LqLz6* zD@hs^;Kr;zuDx^3_a>4T~Es!NJuacz0B)rB`t^XSDvR3+>7VZDSj8i%DWt)o{B-}P+3{Yr||Vahhu+(Id8Ez zX;cZQsA-2$>AsIw+EDCmw2CSEK19>LKC*;tl@ELF2(Z&J<~;|07h8GhGA~HSxE!W} zw0n)<90)Gdf&uqEcWU2|_hVcg%<=~(!kfMG=B-|p_A}#UA-r^om*ubzQQ`Wn=^W@| z)-m!eBZN_Z+CL0j4-emQ!gw$ehLsQHR+$?4uZX8nP73?s39-j?N2Q%?_?LtBib>U3 zpr2vrSA+hE6Tl7=fJ*B%Y^E_2uVJW*Nh2mGj6gmPQ<`k0p+5=wRgSus?hI!xjT~v`8X-o0pCk0F5mFg0dnl@bV_~~_)w|+_;d>{AGAW$`WH}#NwZl=bn^tK2{f?@ z+znJWkmh~hrevbuYsI}YRtsOE?wxzK>ITwEzt@Ay2BNITLK!6>U@D1Yee&|~scGpK2+N0$J^0teEtB!L;V+`>Hr#TtL>Ny8FBkf{OI7m+1!|i#C z@d%nq`-`a!3~{yNF~B48v;NF5_*M_96=kY1bJd zOL&Q9L`rz%CIG$ zZZrt<=?yK5d>VOIq=eF5GBAT4f=817Zn$I@qXg8*Uqw9NeaN@|F^+Y^D=(e#=YYn? zTRi?{yl41$3&&&I5C%H<-y8h2iMG#~Xa@(MG=ndb=J7v)NrdJ*Z?7Y zY(Qw?V*|v@tVTrS*Z`sMu>m6CV*^CO#|DV-*nmjz*nkFbY(N7zHXtH6HlPVOHXsBZ z8_*OU8z7{Q4G;<+8z3Ub1_(qQ8zAZ&8z3BWY=8uFY(Rth*Z^VY*Z|@1u>m5HV*|t@ z#|DV$V*`YoV*?sC#|9#d$QglhMom_}Bmu z=h%P{tWXeg_%#7#T63pSol z%~5<`JfD%q{f-MN7cS8kBI54mxFDz^RwNKFLM?LqU_mL)K_tYpsUgBnJc_-drfgAY z0Zv?0U?2J*p*K`isXT`v${K3nqr9RDH>~8VL{nONS6uXggki4Nt*bC)N%|+s%k`#p zCOS3PKtOT5BZ!p@(-KaIDA&8zCG2pMVZ`ERO3OO&Q4r<&ok-aZ6_+d;#s|XiI1J2& z`@36U<#v4}3~!Q$A^uqqUvhZd-)F@uqnmE4Zc zeX*`-BI-@XRY(|q^sQE|=|b@(<1S0w+#C*|P{{sd?40jyQm)yqET~FNx|Ibv*Yzq2 zbyPT2VKY#4MaXegxGu(UKqqUVs58l`5(LSTcySfR$;(>dph}eTlcYH3+}2YEzT&P=Ufc+0!lA6U6IwC(`d>YjE02NBCSss%yaYBD3e$7`M4L3apZ`9hx81#qxuk zlyGekRlFAU7gWV+;;1q!T&#@NIGY^5NDwP|Lt}S;Q>QsA%@$ zfv%HyhI8+x=-j(CoO?e-T0B=V-BOMHZxZK#FXh|Jvpd{}K^Q_fGGpo<7Hd-X9Z#xfSgc9iH-%K6N~KAiCSCv1yD<3~%6;GdWs?vCH7tB+hoT9? z!iRQ_OkwF!efTgTIO$gA5jesoj`gk;T*;c$8nBD8uAD`c3OY? zNRWz#nd3N2ZV5_*xjh_vv0=81RAwueeT-F%$=(Q(^>@6jTp{o?+Bj^1-OeJFb}7QP zrZP?=(5Ybw5?05l-*!;FzkDk7rQ;+;9)XeRR4OV8iL+Lmh_F18Wb<~Ty(KD2u6Mi? zb>9iO(M%!;Owbqx@A{Qj@<-yT7mLFrUP=svi$bFj!{(j`MGf{gSAb-~G zsv#(~=fV0h>_WkJSQc3TjsUn8z=UIrw&?b_)T9b}xXVd>_XM9Zh9Ka!xTJ z!Hh9!z`!>kLX(ijY#K*P?kbT;WW!*bk7!y8RnCTpr>qMM{3A()7-u0r8EvQ;cR5AB z)RlG8K_g7lD}UDRU1`{N%^G2y#7h4%;t#YB7VMMA8gd-W^=#Kx727o|eOq!NjqMZF ztUvCZJGM;iK{ueR8n%fpi08Jnek!fIrl`xqWXpQbG#ZOJ6ixCA3&OG$d2Br(`8 zBib|>D9_wWJeQO7OOU3u;{)huxQzUstHzaptkki4kyc*oIhB2zKDF^6eUu)L9)Zp0 z>|hB6)lm71$fj9u1S@3=cp^5PV6Il6w4-N|T>0?U7+pou<*+BzJ*u7JEQMSxU zm0vhs^FIWC(sG0Ri--s>ws-E?>{XN27|xIkL`9r=EF#4xH_pmlw-$g}G%9+7 z{Xb_-l(&rrW|P?}-q>t%9?sGp*%V(gFq`7NS|s59Mp(0HigQ)YD^Z?)V_@oiDXcf^ zLqpz-Sfaqix?fO^N^$D3I>4Y8)#z(o!%>T_0eQ$20G9!nPGBp56$JVKoK0XAfNKF{ zU2XhdD2f-m{M*<+6e7v)1T`UB?63HnWAEIy#S0+MD#qU;F{P>kR_6DN1|GDvzIioc zz)InWqTQu~ zbh>Ppf1b*DEy|aZ?W`yYJs*;W3OLEhz1tAg@tTY+jz*c9)NC@3?0F9RQQ`sf_tDcv?DCOPXOviOv@`lN__=uMhc2y=i#}dkQ;hK@#e6*s@*B1cXSM87lLM%8Gub{LJvOCW4j%McNh zHLD~iK0-9IZZmSsI44!JsZO@T28J@exK@rQ%%ueehOx~WikXE4hO-?yQqKAO5m7`f zC?lspS`^*P+cYCRilK+0W+Q4~WE3ZQBWqyPQ4AT^$*Ir4=s}sXyCpE@6^tfLjLlZn zK*mut9j~#ZOEfDu2Npc7qhEWcxG2ALlfNW zD*cVboL;KpV-^hw>P16BTr?CHi-vT$Xecfg z4e4^xkgi@dB%~J&g%(~kBxV*3MMM@2356F8iG&voiG&voiEznq zf<;43z@niLxM-*;Tr?!47Yzx87Y&KXq9K8(MMI*_q9Ng!MMDzIqM-)$q9I{t(U5R> z(U3@F(U4eV(U6#4G$iCK8fw@q8b%nA6~b~yB0{PlDQ3}-gfc7|imMk52_C&@D7TbF zEgI?@$@tYC7!HXzi-sa-77YnUEgBMyEE+~(;YCBzq8APQ#?<8)(W4g)SvNiNtb18E z&1zId^rGQWM7?O}s5EPZdV8fU%63}S=;|DQ&VnK1!xh7t@=|;qa&UH8RVkMJf`fWp zidZ3+N(Nb~dGZj}4(S0$v_A;$XLpXxqHle zJgHdAiMe~sJB3uA@^WluHl?%dy^G)Sfj-El^jMm+DLsk`O?p#$EG=eJdOS;SN{^>T zZAy=2#cfI-oT+?+)1x+}#|p%3N{?kZo6?h1x^LNN)DM+xmN9(GSzZar zW*Nh`f@o4QCNG%4Dc>nXQ((vu@= zY`zdFBa@?6)O;&R8kMZqG<;3OMkmK_O7}IBK87CkrgUG+Ye+~iIeJsNua&eM#$Wl` zh9jkUgq_6>Uwbl0Mai<*;akO=DM5>3{D&m@llL&E^rm!w%9Bu}kW|@}?jJ(bPBxp; z{i#Ipu~p`>-jwe5HDLIitZzjNuqQ#LJDbw|iDdedW!1w!bS=V3O^)4^?jL?Jk~h`_ zsC!L+8fn2~y(!&4iddFuaLPZL8J-haRQHb|VRF=(x<7-IDN;WEv4puPo!Q9di3@b( z`k*d+tB-XmFy?kd(#MSj&OQs}tEk7PaBvUgLTuOY;Wg5LK?FaJ!i z11fIZklVJduWi*j_Nb#0#s)ASPDT&Vi!++zs9$lZ7Kgrc{q4a$*ODCx<0UVX;affh zo)9FSq{}E_0@b7<){I-~nFCF&1st>~E1zntY2XgU`ceM3kSN?ACaE&>8tYl>z;PuY zD@EH5f7b47jHQRm2H$5b`bp0R&O3V{P2NW0xN(g5Tk!E);q%Hk5EwChty+!vgVFoe z|6%V<;G?Y0{qgh8%sY7}30cTwl0bm4hfNYdKtLS`0irAc0)keDkPHybW)>D#TxxMG zv|4SAEmqt&tQ%U};#zFA(pKBs#fq(6Zx^~)tGCPV`+d%NmkH>#?eG5V|9?B5Wad1} zdCqh8?K$UEYAe!Wtaf9Wpco6YSa3-cRwluTmb6F3#~Sxxu>K0#7IOin>Osvw4=~Hc zN-pNeiE#mMGmJYj4$+2Q2muReCG!k=B+x+7Miptph?M3-c)cMHm*5%SrSL1yUt-N@ zkWLR?$UUNSBz zictcujv)^dO-tBksH;JpjR6ZLB z3rjhPPxv0xP@SRfsgm9UNT=O~zC+TCMW7kWT!ZCQNiQ3`(6O{ug~RGCMY&l@@a-&s zn^}x*B=}8-AZI;412}};IL+I)QvUGiXpvgL&;zk}58#QU1QdUDymo9v1b?lS4>>n8 zrKg~LXZ_w<%ahv0ShPn?S%cpy;FcR4R_=Ecsl@M%3?}@530fW#V_PZDmEvUnuG98kFG0Ekt_`wqDI zvHJEGxM_P8)Akf3j!xUFn6|eNl(fB?X?vKUr0vyA+v8^h()Od2zZn=w+k+5`i{#z3 zZ8PCAZBGJ8%KmVsZT0(3+e?fLrp`^q&9vR2<>99NVA{GtyJ`EGfbV;an`wKu_?EQY zXV6EaEh8goo2Md7uaUacc6Va@jjP_=KFHd`B-n4H@GvqzR^KvgKIr1Rhe>=7(rB=I zVW+i+?aU)Hf%3%Mx;7g-y|d6<>2M4|j~T4nDUNH*C*@p>?#6(ZB@&a^M$jTP)o9kVYbdky~ySTx(d_soZYd%)mL~ z4Xx6m3~wrNr|&_<*G<$ix1n&i>44BxAq3vRhalL{-eP!mLYXTAJiLNO#lK^yRP`=b z)o(ql#j5!6CR#Uw{Jcxv=aLhr7&43BnZ`}+-w{@5|0~1FNTW8#&oN9aWranOGHgdL zHE5QyaT?7|F#a8br*?}pJ{I0*QbZ++-LydPm4U?DCaeg4W@hkXW*DYNA#Y5b0iFU7 zPaA+CeaQ`JljofWTF|=50kuT8;bp8ZGj7KEup8`7&!5CP@kGGGO92nVQB0);bozOC z)%Q?xIN(8;4+Tm@uR`0+ewrm-s$*CU=Ukz~g(Ggw)Q7TCa#%@Oe__d0lXX6?fd_u9 zzLOGewfqaK<(nwlx~cmMo4O}X09D)gi2pYM>!$Co6gT%o?6?L`YAG38S*yoNMYAl{ zH0+*LN;M1#@f`Sxk2QL*7_TgrQXy4jIXaUy(wSIm3em4r0mRXzs$(iGl_&}{k}94u zB3R1L4vLUscaNd681K|n)T~F6j5NZ3JV3tRC7vTCh&cFlg3^<29OfB9ZjvsByY644gq7DXF^7 z@HBdZzd~#h6v=R5q{W>5InsT6F&vimu?Wf)@!Y8fZwEO3K?mefvVIbsi%ChwLDVr4 z(4)lbkqXSl+W20|SRu@r2ZA)ll`2jd0a33y^I_35^jSL>7- zU4`=U)exVz5~8^*f9JCNz(#4$Bq}UCRtT%XxIYE5!HC5VSERSeVQ>AE`C&t z2fu^6s^usgyy+vVB_|m#94%8W$Cb;Y-Ewfx6COS9LKaKpS0_~b1$M6{NcS++V*hX~ z*1N`BW8~Q50o-E%=^cJxfLG9K4u)4Z6dAq##1ISMZK_99@l&U0rCHL}Xgpd%Q$(R5 zH%=4nhKUW+MaIpB>2mRa_V5PJgKmy@873CJ-C8P(-i-#$qPNc|!J@avmtXQF<7N>? z3}WFPPd2PgkW$tX-6)WoccDyS&sSQ;lU*no75(WwvddD<%G*@n7nVojyOr zt;^?1UA_S2ZTuQm)^n|&Dj0SUeiQ}MI!|C6%24BFz^lk`O&|-p&g02z9zkpDQM>Vkk;SJ!@?Y)c?okxnvdwN(&&Y11ckE*F>m6|G_4G)?lZzH7tF=`44&cqG$_P` zgVOht086CY4@ZioeXN$tBFM|iqz=^vB8daSY?OB3+WN00~ z+_+iqFA`SN`+83iA;7x*ESO%AF5b_pg7j>Zd0~!T2cSU~Bszf|oK_uuoHUr=lyG zil1OuIga>&W|e-H9gpUb8h9QSftMOq7FLls$4JC9%i&_IKWYiKd&+uSG+k%BuZ)P2 zNXDOya+C3GNyg_87oCjS$H^yq$@q>W19TYyH`x2+WDjAIl5b(mgKWFV>%g zu=D(}rq$h)Zj?6({%XZW)63!WDqGsHsHt!b_yH*N21HkSEwl;|*RdG5^$j8!3o4c% z9~0!<{)cO!r7Q%WECQCj?LO+G<$&$ymxT_?8qam(3hj;zy zJe|K;;_ut=H&#|S9f8BUetBNy`URZPnuA6w8#nVQ)tHb+E=8-uwZ)5PBoPYcE@;uM z@u52_VCpa$_^*M%aLi1?i6wOh95X^+tuP#a@HjqcIChicxX`a$j;k%B}du_Yqp9HHma~R&en{v@Uy1um?2L5Ljk5Hm+6N-lfCPO^RA7kc(37O zsMow(sNw8^mWsa=5c!}hvf{BMl-ErYmXhMH2AKZCWttmc>IGA&NeIT^Etjd@Fsb-4 zhRlkQ7-1^MCXc+_kg4*Cn#>VGMmn+ej<*JaX?ErOJfKStm@W=T`>1A$?Am``w4Xp& zBgS71$a~0@_t$_t#_c}?Oy6;t3Lp1ViJDa(r(w1d(UCf@rDx4(B_g{VW>KwSW_%}W z=A*~=dc(+cTdEmj;T0xmmH4b7BW=cf!MJ5&^`ZgTvt3{UK+pDVgJ#e638SR5KqU_O za^k-?ZuV?n79RAXNiVi~TK{IiLwJ^sIm7ye7gi$AprKoQoN-gPVQ6-wZT#ClF9r3e zxlSb}1UwxVkULL%V((mI(2T>W8ZEu^V&7|`(|5ih0kw@WxZl#ZdkpsCSa!s+5;O}*D8oE~D&`X~^3LVHGt>m?^H zcl*b6;$bV``1egXoRvHPwU9$t)?TZ|{MZmUnTwB`ofIut9ADL3*!%gsMymL6hRlKC z-!vJyk7_5AQw}ND8xD@+M~>08L^w<>LG>NeX?UhF#H|M4ykn8)LB&5F2rBL2(Wr9W z?>0l^DEF!WF>~&bc-FA7_8c;9sXd1cz!Lq0_Ro^{jzP2Jy==sCsjh5}Nq}L<^I&j( zq~cYEhe#$29l$7i%mD z$C|xb^MmV8X{fvb7Nz<(XB)3c?d@p_TwJY#h_-M8?}oznj@)B&@n!&J1VBXDDC zuD&sqrwl>j&wv@n{WVJ|{@X7^XMNmJivQVTre_*t=A2{Ax)cQdXKk5rG&|8ebG7QT zkj4M3OJ>anH~+IPn(=N1wus7>t`-<`%;LC+|ITr<{(v9;JJV-<7n1m&J$_aNF#OND zaMrJZ;lDF;x^GgN`z34Elc4iIyHd@>PelDE7EAwe`_UBg=6%|bs^fLhJrm6)KMMw8 zE$4sKhV&AI@^@R0{_}>T8J40EB#>wK5Gv;-qPDhs2o3o$lfmY`d1xrz5!H2X<4QAaT49MlH>q3UhaantE4W$XV{i_m^JR2X zj_-$J(CFbh#x4G`kpxn=0!1Zhat_U{e3n2$&I}5hKt-Ma4_+WOOpl|~4ZtevB2Lpt zj>hiJrKIbVY46i|^cSXe2`fhk1$Tmq%9Ye*} zKzR`X6t&@{x|Yt?7M!HF8dwm+yWYAW=4PixO>6+87s*wOB<5om6m_HZ?C8Q=ZZ$JK zyz9?EiIItcw_m8Qx3o@SaKD9=7z+tntd@41K^5!?tALe-@ii3EL$C=aKhZ3&C8B&a z5Z!5*do&^}Wt~bLKMG_~cT*$Is9=hBnhyQa3*%C7KExylV<8FpnZkBD3l8@@i}O!N z!avSGAwimuJSYJuP%6K~;8`k)s}1l5fLlDK0knCU@r3q2Kn_J-5FMab-iwzSFMos= zdEAyu#G5?kL|hA@`XU~`~BccPtNsJ6R;9k2fL7^%w{GL6Ry@VPx(}@e%+->=j1qFbMzicdIc$(H%dRvG%-KH85DTv} z!KvcU8!`*jLz;}_REcjJJT?B6aZ}^}6dq{2!%s)1Kgto}pZHC{+h2^E8s|a0(KvUW z)|gE~rAC|56%SC7nnGQQX9e)527M%I428qe)y7RNuM{q5nG9&z1O3+c9&$GrH}%uH zsS1wI9^{4?$(? zXY`d%?X8~|pgGicI5o>dugaQ4ZnvYE1vfudUmBftp?IG}?_b8?xKKnKBO*@0(4X(Y z$`Z_EqLu(vbnCn%y{ktDV8u;ae#f!+?hKD}JuNQQu40T7$3W4wa)rARMBY`wZ*B2v zl=Q4j7gEi=^OE?+!lQgs%@Z(8&}uHEnxBLcTFph&=^IqjUF)eMX4o1qG%+boBG?MB zxS1CoSts*ed+g#TE+ut|q+xy0FXkmBtfNM#T1QCCcl$>uysIM0D7n^G{UYWXCU0Ok zhfN@Uv}jnMqa|5>E47x?-$<>00MLupCSoS6b)(fna4SF)tur&C)oP+OzUJuBx|#Vj z@D=svjlvHBiD)CP(X)g>&z4^VSS@=HiL?o@1k!sKZKr;Z{orR~l>O4<%wgVjGCfZji;YDD)bbW!oL%TYP*1U_x zlAOmLRbzOQq^L`tH<9_!;#s9;33$wER_#DvIia~AZ?rvFX{uBLN4#m_E zHmPL8W7Pqnbu!M{U7HknZ=t_%aIkaotNT&3&MiP#;DQlJW6X+qSTb45E zeL5UPYC%#$(#h;L$zJ*%r2!sQY`m~B;t3Qq=$O*6J>RuXjjlCRpvJ5-?x(>us?z{J z1~5%~!<=~3IR+iUyhCPqbm-uo<@A2JYdyw+FnBnKZ%Z{Q5Q?`^@^ijZ4-tv(s zen#<-8P<+QTb~0RmvB6#V;$j*N|n6dlmFotqT}9e#X0J(IFCE}BoK62bRX|8u4hfL z)R#**CCrZh<5NO8EcZU=g}h19{mdvvQE;+aJK8r^$X9QBcgsesVO8)jn7hUt<{Db6 zM}5%!zyV4`M_JE&*Wb31icHS%Sr=m}xkl6WjM{IMh z(Jmn9s4NyXeXh~Y`V{7aww!CUV{|LqJJ)FE+zNza%i5(~_$UG?urtp!+C|p_TOPfI zp%v3zVe9jZb}6Azww|0QyX;bcm9}?Dusw)~@j%p@yISnQ#7q<)W-MDy%rUsFc{db^ z-9YV~O+aPq81cqxg}ZqW_OM@pBWLNd)XG&07Sv&Ik+Zb6cK%8iv~rfrT{{m4(KR)s zvbE_?K*H$BsFIXWzoIrM!GNv=1BO&CzObpQ2_=Vi_*lVaW>{7P9vYjPaQ0VY@|x4F95^;GQFRb37b)4W zNlpu zSbe_+E&eb_*P?wdeiDwvHw+WnMvO6Ve`zC9u6_Rk&G$R4A9}>C=$r=Y3#{5% zJH7%v2RHTdvG#VhLMzq*ZfitzI|zOmpgwwZHhspz+uf~G*${SvQ&tzbW8ngKH(1D0 z46JVEHf$=4&wPd^4VJQcNE+fx>7|rEHUb9)HWPR)jUJq(@mnS;7$?Zb>f!YQ@hh0b z8_=o$z|fH#*g01v7c5K)-}jM3tDrjYSf}@rns%8;a6dw&*4px3HDweYkug70Mva&< z>a7bltG6x~{FW-^Dta%PgU&0Xc&JD#a{#q^A{TzWv?6jhaw(Mjba5jYzS;#`LX)iFae8Kfb;|e z#>c@icq1Is;JA~H6XAFhj*%zB(Xa_A{1QU1SdRUZC{Z%TENn?J;gvu{q*Rs@VMo?Nzap z5Y@7|2AczInK4p`SS+whCl|fC2AFHvSXiHiygY3OyO!>8?8L0o*bAW*WG6SCt)RTO zrrGY_YeM)IqRbEO?ZcY(U_+&lNl4_uO`Fn9c$x{5vKCa8`|oB|KFh2eV8;W0VA|8ns=7Rer)y zCxBYAKfpS-KWoYBi?uRrMAiuvjmYe0G*VSwXLM!RExFeKEUzEal49Xtd1WR3ieWlY zmmh3r8DXx9A!h`#WItkd0!GI}q+|Lmd#txRFmc}py!AU4i1toU+gk7nPWwi$82p}@ zv4<37QFjOKw*CX#_~hBJcx4SQJV|Tr)o^9a&M{T|axh61e-aK=a=&3^%ufZ6v~&mE zn3w$3BupdX(WS|(1tobVeymKFYdrd^k_mxmKj=zJKC89yqmJk9W(Nd(#S@UYc$wy9 z!*G*vGYxS7TC29>2w}5T;xhqX_Zl}f8>xL!vque@)qJ)_vo}rb4|x5iaWiLIg$KQM z%nNW0W1e`$_mKFJ?=Jac!1JB1=bw4Gu08+B_mGIz`%xWe+)U>080{EXJis%;xEZlO zYaT=_F)F}vqH#0D`1+w_<`^#mx^h?xRbsC1NljrdVxO#)sX&3Yj<-7CIer=NZ=jGI zL*&Sh0h-i>oX{;mpYg!jV*TW+v#qe+W6#&JNU3&SNEV+n-C)8^}9Mfnq@(>5>ava^fvRX2BY` zG%0?VOlw@$*A1&%N|{V?!^nQQGQUpy+74eODHAE);(4Wr(9KiHRzu)ny?eE6={#Vx zh=vKqlO@*#I9@uE0|&0YXgKbHj9&#fqzsk3VyKUUYUfKjAOuzN-9U{h*LW8EHw>Bu zf0|*()W341iJSDtlii5+;4Tm2W-aIv52yvf_KgK|VZg(w0S~vh9@Yd(K2xvNFiCJ* zUEj!zD+9h?cYOzg<0kdh0S|W=H*+shV9LQxFE~@kPgaS$d{3267`Fs}z$cV^&$t=e zbt0`_Y#IEk0S|vNZU%py8~nNbgP*Sw@A#e)&N5wgSo%g9HwAp#6>z9uCFMhwiP65V z${EHj5vXwq$gb7K%?J!HWODS20JH0ifQO!dhc&K;ydow^my_4d-%Hael16jab8(u7^OYWl%K% zWoNpc)VX7z)z&NE-R%?HL69aCBg3Xjce=)6f7(MBW1zL-?Q}$I^e;`gH%X|lp&y9L zex=L3(xL`9;azgd@}y8X@ZJnMS{pM6l;pAIsItogECF&ZQqP)(U>-2^4iikM2>VB^ zolQ&#SLa?gz^NFSZ59<@gNjpW0BUWM2!uDIu`FKUtK)~YE6K1x8C_xM>rGgl5>{I< zsP)zs9k;18{K8A3BE1FDb!Zy|zLlYEeUH#)qN#b%Bp_SAod^kKE}U&$!jV_@BNo~m zLucaMA#^65D%rJM$AV4Qeji`?Q4^jN?i&pNA0_u0Hw*V)bwEe9MGpo%JQwgV8PS#6 zpuVhwg??x0b zFr5jy5y4k1LR>Y`LG-DlBWaY z6I^noOD_9HfGkP2#U-iXqmW@|!i!}2-&8po7A|Twa&^=i`w>uL;X_7`81rYj#H`8ZY^B>a5wV-RbmMN`E^GMS*4|N;xN4vzuBwy3;LBb~N|$M1^=M--`8lu8ZqcZjH3oWVvz&QSR+vQtHD|X5_d1 zj6CkRierzNdQ4Ttq_*kP@YU1Xo<4qKx*hN1H34kwYT9)C)|t~Mk+`v9(y}QPle&AF zkKfqdd)#pzvoP3arAVHx#O)2!5@$t(Dz0qOzdK};dG zDQ2qtTLV1#j|6~%7YðsD|h2C0Rz(O-xG>#j{I|GS3gOz`CYX8ktOZQG_k-C6HK}BP`HE+Rhmk*v~{}jlvRErND*f+zRRA+ zpoahU-a%MAZ#qlqZ>zZM=fLvc8eH}r{P5qtZ&0ci$8O1HeyxPs1H~e0E+T106dzPa zw6UqFt+AyY{ZP`R=o2R4Cl30D1|DJTn!;pd1Ka&I&qLPxehdBo!bs%(bWHEj`FsjF zZ})$tAP!{cy07E={k>8^esn(Er{(4K|9+()(D}&4{-*PxJEQX<;@__n{L`-#gvByi zY!`C4)Rdh{;Uc?@tsU!ee`vElNEdf2`?037TYYz-yyoD#sstUlt>@!OO^S%cL52`> z8n0rzX)#uLLWV+_$o$w1mYM=|M6E?r_yM=mcu880$)ce?VemiHF#mt1 z9S-+Fy=P(w_|L=;@}G$zq@RhQ%Y7zByUjB(KEZzzX1>eeqiTuD zcqWDjJ`*Fq`k5Fyk9;O3N}qveVhFFs{rmDv3<39<7-2Ne#L(?Mgrc?+^q+|dK;APk z#08&;$$AsRJ}HHfo3^4Eili{`3pQ57c(5E%4kFN+g_I*QKEpB`OW|}#Ps?T;^yd2j zy`5r#oW>I)cas_}H3QgehIJ&fj6B16-xl5q!<*y03OLv2Zf`MPCv^Pw1kQ zRq-$*6;2wh!x5Y2vFdwB8C;`;M)m`4^0}r0TR7;hPDw&lj3?zAck44Q|JrMU?`I?) zb~@RpA4aU+bx>~i>kRlJc<8!k@Ev`R&LGR{49Jhs_)=sl>!}%y)2TZHsnF;QD+eP1LA_6K`d2YhozuM>6s{q*=@K%11AYLOY^U+0v7%L zmD}nwD@N=hOdEhvD_L=R!HjQnaN)SL4$8{YlzP*Q*u={VS`OML!mPMHTw&Kw*YJl0uC!}9@Eq~h9uwiqqD+V?d&$#AZiyFsL&L&Ifq8fU^kJ0=z=NIRqB~yi&ju2rdM8m4HctD*;|D;5@t51bmHz zG~b@zRi#2772OsAs8*q!0@MRQm%dAYH2|in(8mN=2VlAieO!P|0A{GrwE}e7D{$-} zbe#ZO?G;S`J|Vz%dqp#V>jl_huUHS@1_5^3E4n+8@dDfc3V=@uup5*X&!&%>w)f0L13A0vrM`O@(d| z;Aa4iRiQls9JW`qK$%+w_)}~PCM3$rUM=@1t-y9dH%goeeKC3`31LHE?sj#ws?e9j z+wMsA{PgICcNH|XlWp9wOpsS-zXio`kpQd?L$#{HP zi2M5yJ-^Qg`9MVF%v;+~tHM{#K&8q#Wf@++3}5vsRL_~OfvZP=(C=JW#%^SeH#CV% z{v187TD)xOLKziBs(r+CjQpMyPy`cvO2B#7YQwrT2eh_ z=3G?}T4-NyLRXXkn9iRe_#U1pQYhvT{vGA zvQc`)g;Qv<)+||q0qE*ljJ0a#PMw0tht7;nqouDYWv6s>VfuTPRCr~tl%uv9*DAP> z-O#vEBif|Ri`XmDxGw>BFr&h>>t@id?dt02TGrVl?RAHEj2fgqh!EIaj7z zrDmwm*}|La$wa;D5>%c&A6Eh_GrqgUcY)x1&ppB!_dKJX_6jQDHj$gfU#SLDOB%b+ zQlTw^E4LSLN8PQPX!N#5Z$-*g*lXI_0@!U)ruXh_H`1v7=R}$0*lEn|pSq!QqfGsx z-B#$%=tfj^dy&3|J9L+TC}`=8jZNEB=x#qSG(z`8nX$VWG!pe*f%XzYa@;4-enN=f z{Q?~%1Won|bchgIq6Y*zoDB#~?&kzTBLonQ?t=mr2#EIZApt7{M3eZifK>vrReVI? zq=uo=qXO4!7)tFEc%6o!)?)&9Y8Z+=F7S2@L$%KfywlPpmaU_dU|d>_0(qOXiUkW= zdw8|C3f(RR6fp8fW9|@4{$i9{E#Wa&LK$pAOs^bzHp*@~w?2R<2O^SMv1(~U-IChW zf>ldvIN(sZq35I1&=T15xYO&66uu%QL)o?M%^vQnf{WOz+PAc{H?vIgd3H7?sGRjj zNDjRiT?)Zr=ey9ba2?p10ZL@^RPGT&p3tXboRR0&A4%CAyIus*euQY=!-{m1RP0A%+&6`)egK|;(7xDB@Kfy18=deEX5kPb-n29P`a6)9v$O%vB{!^EiA`Cyvn7r-?87|Tv7sl0 zyTC99QPyxa(}L*f61$=i3>TsruyeulCuJ!N*>Q5PrDvN=-S7@u$5|~fwwvM(iN6JY zeyqOoT%3k<>C@^FR(0-r^Z91#Q zXuFXm;DK{_P|ILi_JRp_V*nwYe|?Rz&N>@h*2=*xZ5!v|*%5=_8%; zyB2WZYG_bv5Mojb5!;m2%Ch`ZhO)^NQLBw(-q5Z^<%5itzta(fnWCA{s`6?>DuhOi zYB#=@hc<5-!h2#=dAA|+q5zPsD&Wb3gOR=zK$W4*Tk%sB+T4ksne_U&@tShIs`4)z z6z>p#G)Q46Y>vuF*Jp{SliH_V-~t@7|N0h zD=UkYHx^zO)d}n_<34~Y6;W@0@S69uc4G$3Rot~nDFV01H*V=*JpTSwT)D#lTdXj! z2%UT%WWDc=Jy_R~{hz*%!FIwj$W`IeW6@oN=W(ese2Jpl9gvd{auUt zIn}TjwQ%m@#q;LYoUH7`plWu^&J27zi}4lXEuFE={Gtn6=)Sl4by)ty4$@jo4l3=^ zLA>uS2d!+E`yj}&4J#ViTQ%a6hCx4~_Z+_m4-f|l(aAA=`?3vn?ak?}${sBE0v}%k z+vs^{#k-YVF0|5|mDu!Nw&B!tSI2@DysK#s8AN3(a%!+B*w};y12epqCU_Vsgi$Jb z^a$9)1~I-zqbhrf#Ld{US%dPxmOwG-<28gTz6)F9HI4|E^@(C@AY1N_MNvWHRDo^(C;HSs+1O z!=P%;11P~=!{E*%C_!GsARh);INDS@-ZP{Iu0mK<2Gb%kDfKZ(E$Rg6*YHtvE*#s= zhvPChBDe=2z6*{xj~ExPGk(VyzubcppC1LE_&h)def|=TM1TGgiW+?(#vv4UIvgBB z233URSx;+MdZSJTBol_>h7KR{vHE_CV9RuRb~E|-V09|BwK;{`Cu)g^h1ZxBUyVOU zSqn6Noxu+_*~mg?jXNE|#KPy9MpV<#+4J(a$wfj_RdXe9O%oHkDot7EQBqr5slk+D zR-*7sFC^lj!BmZ}_wX!8cv>Cy8^?Z8x~&Q$s(d2iFeFv8q9L^egRmt`g~5Ii;nH>r zgSXc8s29p=`!Df)_=Tish*!&m8-c={vRwz7^a7ee`}a}6d^^_mFO5g;O@4G z>5$&a?)Lc#X|lQBfNi>Wy;aDu{riUGnxRk@P9AmjRAgR0q&HbZ5zQ@(|8#%kHc?Iu zlMlx`F!6{^$M>oD&x+s+>51CW!m^ot5@76_n{3y3l+7HCuL|Is$e*k6DgzJx0UBRm z@ajexZ@lrrXI)#ms|(q-*R&anCHgr3JRI5RcaMMnxZ`~fGyeGjhBt6{uc1Q!b^LxC z#o35==(ZmFscU+Hh=*UwSkvrd#223s$i`*py2fK&WDsuN8Pznf4QIUHH zlse`lK;&M66)NW31WDN(9OrCUg_Y7JjXj&N>WK!AS3t#_C-9xi5WWh>0Db|C1%~UFo+K{NEQr2iD(>Eb6 zAvt7?Wh{qXgh5@S@rl<(Rq2%mxIzNM0r)??m=uXcvUE`-*8vq_0VDEe$sP-i%E+6g z;;4$eS+)laQek&bMxNz<76IYbC^K{@TZ>@>|055Uorxd*+YN)u_Tzuc7PsD2n|amRV8HGK>7^a8E{# z+Gq<+hfAmKaOt9%uKdC>i@&tYl3!S6@t2la{MD9ObZN^h!FiThgp6gDu!vOMbOw7M(|0X7S)h&@zj#XPHI7wagMmW0^&Fpu;8Tcenw_>u`w+ zcDPO|-Oe4tRHt5JRaV)_D3Vq;n^-wMA+XA339T^I8&3IHeV>3chsV({_0H9;0bT$| z=?-DoAHfw1?=TN9vRW|Nc_mGlk><(zj-7Ar4o7!718t7jJar}|MMia6B0Xv$d%V2;Eq#SE@azZj6%~<}7gls)e zmbtLM{ApJ+O(m5rTID_bX4JS5K|h%VkquNjgA(UikRnTj37qE8t^ukijEbiQf0rZveC-IHVDjN zx-N#&xjk@XsR5B_P07W8^XfNk>u$j+kQb5pCDbZ!bqmbo8(XzjwSvR^U$20!#NsWD zycX5Yoe$fI%IMq@*5uey?q)^jmCS))6%h@Ep~M3e);~$Nn~;DTNkmpp_B zS9rt>pG$-|BG!LVIJ#6sj#AlXHN0P%M3GFDc0$wjq!0Y7+u$LDO_VU_+US2!U%L@y7d5u6XF9`PX8pB?mF5S!1<@NFeq?e~7 z(908adwIGudU+yDFRz`tm#5q9<>~f%c>;bfPss1(3F%&*F1MH0Zqv*A1iwq4?{fI4 zTB0&~c_P@$%dhU`={&NRA4s2p!#IS!UY>y4%L}9F<>?Oe@&x@}J^*>WJaNHZzR0m= z-;BZ+Z)|RsHS0NSB2=9Ax13}gPcQ;AA3Oz!OQKV{gTw|qDrgEzplzwm)yg`7<+mu; zTJRP{b#KFk&kHlF)*?WoJ3=j2#VV6?;VN3-}tverpJKoXCTc6A$w0CRqFlW%`iIjEEx2SA< zQ)BlgW!=lxus|i~-@5N?crQtr`>XL-Bc6a%mTg(@0AGp}?IOg^s1z5T&~38^kZZzh zInA$1aP~BqrplUXS+`@uyVUG1Ox6A+Z;X4rSRH7fjG^!-KDG#~@d&95S<@`fv-mKw z%FWN|nrZWt)Fx^-L&7S9Yo>KCLLF4rp{z~TgW|-NvRsVX?uU zgR!;1+6T9#R=Pu`MwB9ctiBE;Re4)CUYcA<=hrU6&c#p^FR1*nAA%#aYt67z%s^`_ z27(n`2ABe1I(!V5W3XRKQXGKgR`qb$Je;hCofq_Vr2!h?t5JL{hy4RMd5PJuU53ir z0-<{^7)Ee>HWGK(;HF;Kx1sb%M(SIl9Wt7gthu%WMj$W^sebjbiX9i@|6d z+}*bvBsJyf$afGZx-wQeRd4CP04PC2x1hll~SU zOTMl1^Np%uq5VAQ>~dmNtpkJImNXx%l^nu$-)mL_ zl9g%yI@6xn@*Q2tx@GFj=_$97kv2=eUV6|{r|Xn^8x@ittM4*g zV_CJO(cQWI2Fe*mI^o@Bj#AyWGL0Q$>t(@z0;ylgTE5!IS%;*s4q0#JDK(`CDK}*} zzb4^p97z*q!SxtCjXxO<$<5Q?`09s2>V)Gbm%(u%9MvCzV3wv|8o_%h_(|(D*w0A8 z*$4(HN>|ds!gU`UlP*goB_1rbNKIS>iNv&EK`O$k&d^k@{aFXBJ6vI3cZI#_3M<_K zVJ92*Okp!|=inhjIbH%oNke=mTmijj!{4|h#E-uY5FHfA(*|qmiqjPp`0d^wV?~3`!D;e z;8j*+--)J_@lI4V6f4E7Xei}-cSAxfe1|FgQHLGnP@J|zC16VlmIrkG*kf3ZO?if! z^($*v&0mIb$>L=--n9Z%Y;E6@sdnjn-ak-n7+cW8r}0t(*4BZYLhSVWQM&mbYk1f9 z&$Hd@?`B>DM*hdnw~h5l`?f9tmC>LwN7zkJkm#(U)`JnEj+1j(U$JlxGK^rUw6H-=mFEqsc4kkBTE3d!Asdw^&*SiVk zn456DW^0<8uWDTq>MAuCy(mA{7(~Ual=$!NJPFFb=8k&Ap*@Jb3186=zOdNPj-RZ6 z;jfv5@RU?3`WVMEd~{Dqjke*>M|-EFh>ygkqS?nODTd(qOmi{VGpD3(09%1`v{O

;+loWv*K*7PJPf0ktL6K8Zq}%}k za!QK8UPqsjqI;jCPf5|e-!Z482pj-_*z6Wr2LT{9Hw*9|01%tc3UCMj&H&sZz|R24 zDJcp#?3hzh1pbuE;f}Hf9C=D=B8n8QThIjNt~n(|Z@VJ{`k#^_`i{teqnwf=Wp9w; zopgFiwA-g?URCl=Nzvo}enijjGvXJgq{3$Paset;*sNaulB&C_m(?J6n?7N8^>Pt} zM;ulS*lB7JyNG));|py7DytfH^^;y0u!*#v5>T&HhTdV@kmnwl;+Bs9?t!WA!DpUt z#Tk0TqUWr@i6jeqrw+{j6;32Q4W*Rho=Ex}AV=kSCz4(PoKN;)_%9fZpt3YP*@g2} zK4Zz7+=QMA8pLF-q2?U@sM4cZ2-B1R_oxzUopQM7+1u?NRU$6r1db{(+=%0z+Ciyp zj}m1&*oqGxRiekJL3&4(SdY<2_CKmb-ds;63V)Y07kLhiPyM4x^j#ph;87)dj(eU_ zS$f5D!fmHEN9nIrgWgdk;>w*Pk1FLONh=&2?a4T*#EjTIz>PHO;5kv|#coUG9p$Lf z8juQi^Qh7}i7nmGXVvg@-&`8vKqlESnLUP{AbC4vP4%26eP6#~jpC4yA~>Z3}8lNyFfk4ixG8irE) z1YW0MsP&k@of?K>j|;qA!*W!K@^Dm1iZ+`lDY_Oew&GDGHcdr=qe?8GfCERBh>5?1 zFD+pXJcxucte*#tCh=fnmN&x9IGV)O8mIr!B$fp9?iojuh>JLxN0W#{Ej`-Fq$QA> zzZLX@u1&p#Ms1{gS##GyytQO_jd@g0On|G}Y&cch4ClK8BS9&J1li%ZyyRCvS;pG$-|!s);L5LzlCMwk^#NpGdiCYoOn{Y(==B^6YH!Q19Ev{W%yErf)#d3E8c66eJhro!Q?7esf zQdmj9t&L)K8P|1T7FzlqTN`EG)&}{p#`|Z?ic7KTY_>M&)LR>Lace_L)`sA`tqnqEYeQIMYlALtYlDEdwL!q!+91HK4dLL{hIU|ULp!jw zAuQP1& z>a7jB-K`C}y{!!b{?-N|e`|w~-rAtc-P+J@v$f$9{C$l1E{Bh*B`RZUgNPbzZOE_Q z+Mx5ut&KtS8Q9t&>}_ojaJM#u(QIwd9oX6+=x=QVAa84fxZu_X9$v*=U@aR{8*m~+ z#i~w0c^r&Va7rB(8o29=x%}XJvCdJxT5lfAZEx0-604kp4^@t>+18GYvQKIaA<8PR z>A*(FvJJWs=Tr_WAwx+DmCK1gw}Xc)GsLilksK~JbGKz1yy5F2Js(z9h4c(69MsJk zUI5jGxJHI6YZs+tiQSz=E9(rId9F)BQ%oEXIex6Zn+vg0!|9`S24|0XS75|fi_L`0 zbBQSqJpU84p=|E0b?n~`TnX0sE!~}sxK}6LW#(zhY9#NiSD_`t*%{enX=2b9UybFb z-=e{>nwhj0T?6pj1k`6yP{7aHxJ#xlgGu*5VH2NP$H#0qK^mevjJUKg)M+!$bg z-k@h1_Jyr?Ut_I|^CUbM8a{Kxu(VG2G)?5R~ zBakSnUQdfxf!HJ;MSwZdag0 zK1*R=1V$IZ=a?|}e+*Ij#rh=WD(3o-qRb+wnl!D-#jA108C0!Ci2>}0jRr{>jfU4P zm**Q=kBe6$J{Mr$Y0z%DJYZ2LnqJV4b*pBrYS*l$sE&6VHtgCUvpc=jL1jH&iXlcUyx(w6;9*GI-EMwjb0*fH zMDyP|ZQ|=tkpI@0i9>7g(ZF>66x>yab=N+;6NsM%IOh3LN*zT-}JKRx~We;kvqpI-G({x%NNvYv-+6 zsH!3#8Zs%2P{mFwa{7?f5QV$XaWyEmEO`*M0cT9p`m}1~3?YX=#%0W~#WMRRxFcf7 zS0Tj7!Wg3oOS+430e<&l97|P^bwgr^R6&+p7a-#e6=@u@9-&lZNuLZ$3|_W{fryH% z7s4nc0WaB#GznOFbZum1DAFt%P0U)^+1QoVt6*tC9fQ<8TD)=GVv8u7B`bMcPgaqw zL%t66RTlL&s%#tbAar!HaI(Kwj4=%U9Kq*iE!%=yUN<&ul4pb>=MLEq?gA08GTqkL ziNkPd6**7PrO>X$jpF%3KFhcxADQfS{n2#9c%FF^*)ZfyrmAx+QqVpcBhITz?nV0N zuClNGFY!7ZdlE5jOk}gbA*1wtfvCKxv(nozlC;X#g6iHQXz(y58OBo%x!_S&1#?T~ z>LaSdtAKZM@tzI*jv!M3G~}_90Sv}Hut7oCs+K^^HRS89*T9euk+79$7N7aB$mm5k z-@26{s6rli@ER0i@Ui;R=-mfC4bqH{W5T`NG&sXFSuX7!co5W6L5<&NsKu}y=mAF} zZ4gT!1V|jGh|SeLOCI-m186=5k;3afenP=)!i$Hp#<9uRZ@ivkl(70LqOewxSBzt7U4DFbW+4SV9r!M zKF*Lb(Z~qq!4VPYf-Mhj6h_c;CA_kdj6>4M==0+62QLmu#$m*D&>815HfyElG0QF@ z4mCofYKVFbs6?9)_RtZ!CUzUrOGl8(zhFprBKGmG7@%LA5F2f9jbr?1a?By%Z405` zA>)G$H$PTi6$F)Sn%~;0XCrvOkoB_h6JklEpD8|vQQLUEVDw#5$~u?juk8kmsaOKv zG-B(yi+%mBEcC>54r384zjZ@W!eUuA`~?QJo%|nulKgaP{)aR8i^dsnp$OrcE7DU} zi5*PL?oR?n%@W`V0OcnbACg9!4A3u);x`=~UlFM8+z2l#MG$^j&m@~e{)4)q5}vO& z)novRN`+f=w2`kQ9u=1WJDGC$ETTEqS4*rH#u%!YHtIJ6ue__(DFo444s zT@PhK-jVa%y@(|u^zo$Ri@V|MpjbrINgur4K}-HgxRQr4cur#At>PYOr(jGFvR;dsHwN~!dK2kvC~_6;j4a1ydIQ>ubv2kHz+k*df}a)2G(|( z=*hc!Wd%9kW1Je;(u-6xiF6pUychY>*Wf!U16RA$iV*O(?Qr>uPSQwoM=#%?>~}Of zi;B#|h{dUZBMTSF>xJL>%T~H}_(}WG;;S({$>u>**ug4$UvUSRiD+8i+Ntcv1P&1f z^teC~LS3!k{=C3Zp*D8W^wWMqP!3S&EOcvRe?f5B#5Ha;xGxGW7r1U*nDQlo@(3ZA z{Q?yLYU=K7Q}&Yr4+MnLf@iw-aEkb*ugiw&v#tl432yOFbl zVwxmGB_S%iS*z^|?dQ`@Cmw~zEczaX5u4;dz8B6ixmFnSEPdt#d*p}hzQhvrso6_( zS-;67-jc>MJG!uma#p&_EZHji(+Sp|Q1+6R_9JMY5n9+Jix}S6yS1tYSBGmn%o{n} z6;}4mLUs&!Rq$O3&G1=a$j$bbb9t+qBi%S81O|lJ6Drl87(*vblLcFv)B$NM(Oc!kV9r z0c{O>wT#Q29u(RFBNrA4O=p?ScV#~$S+XcdtLbQK!wvEF!$PX})#>znJtCwv0g~(K zQK78MUfj{xjLQIJc5d$zeK&dacg5yL>=UrkB6^Pru{E2;Y<^1@I&7XMupdwGme@|W zY8_cw?9V4ysoZAjs0`PjGTF|1u%RVQw1FwtbUjP4hb1S#R-!sOmi>)HVGQ+gC70rQ zc%h>GO;J}#Np%~Vm!;8*WcP1?UXj{d>gkvv-TqdBX41CvAi{TJ;d3ba#}f8{h+R{1 z2^fz!)@IKyVWXLGtj(?!oY%&k_gl^)OiWppKcJvKods)e+5qH~RY9d)r9P|pneCZvMgCr@Jb+zE8)yCEZEnVF` z4V!wgx@ON6l9!@&OX`>5s)G5oE3uM-&Eyq0;C;fNTJ#MCJg|Tpq}ff>h^I*Qf{v~& zcxMKiN}KqCnO!S*^kh6%XfF^b7iGy0ZlT}`+;V?paP}h6+l}N=80rRHMjad~RhUAH z(}JbwwBHU}r42|?i#zB8&&QWlx(jeoCwh8QqOC#Cp+k%}kvMoNlB=i_W!oi|UyBk8 z$qR7RY<;b}vS&?V$+C{aBDR(~iBgNZHa9A3(ra*Pag!-7zL=7$=plYRoz(?kP>HMH zcE{@Os*Tmx4Ur{xgY+6^xuuW5QFefyR+N1cKjE&@&uE{AHY6bg!OJ%o`u4d#OFxCl zGJP(Gqm;f&>38t&j2CLH5=;@bF)7|_<(oqOMj;lyu7Kb2TsW-dgG%u8G=+|UBl|`; zCc!ZY4s85nB+R^RlG#=bV_R>ef7+A&Tg?B5b{ZA}%ON8!*;2~{9448tfT{KyP=-m$ zEu^f0SdJMcskex!w+LVb6EJPU;5DSyvd8c}oQXGru%wPZ09X7kG)MIZ`NQIrh81uKpk-HcdhkQ{IHS6 z#Nx;5`#x+XhGMO6{T@W56%o-1(98s=loFI?39?p51pi?CA4Z_orcd$ofkcpS{|J_C zN=g_yg5#LOLky}49<5fLp*V?y>>ELpWbN0WgJkV*>0s85y-DPF8`FOL^m4D&$$8mM zBYT!GGipuP8q%@pVr+CJ=w^0~V`g1zJakf-%{m@*_m9WEjCk}fW3^kk<#{m^_n=|C z($gSbfW%EN#R0dA?*sB=L_{leDHR$oT3gy&~Aplt|cjYPWQCk0d2KcVhSl)(8$wt~Bj7wn+Q$LhPNkY%yKoCCdwN<>gy zwNCdDWQla?_v>=08??PlI4PogjMysVzV+bo5UI5$+&^m%WN0l#^aX?Jr1wWk*ye12 z4!V#MDTVZMprnxALkA1#OK{-h6;d7-=OIa63fK=j;Q46`9;|25IZC|@tWJq%nG%Mf z8zauHo)xR-D(gA+viZABBF#6U^URI){Cb3}6NzyDL~1d-I%_Ag9$#QkC%VdiLlWw8 zh?j(#)Sp2T?H-UN(SAb*6K&wlBH$Rl>>NCLGmx|7$=y9&Jhy6oqBDqSZ^F4#_cyvk z{S9R{qP{T!qo)sU(XtJLxXC!X+|kJuullo+603Sdke`N$m@FP~gU1&@Iob^#uK<6P z8$50Y+P}f$9WuTD8$90kg&nrT;B99%%E~`~c}L(n3~!IN->xT8jMhCBkrN^q4rj4~ zs7R7-m4(yKDKrHtGMDN&SsO5;QIUCUItsFQN;pzOLMimkh6hnS7U2bxk%cRO$ZqeT z|6ZBqs_d@x*}a(K;67FtXJzZ)@d&Sn3o-Gz@1Jh2kTuGT%Rp>rDa7aWvr=S`_H}nL z$oH^P%=N4k$sfgQs5U&nfXrAa(y6T!>7tdQ{K86+zqC@6Usx&fmsX1W)mDmhX)8s+ zc~**qjFqCWh?OE;o|Pg2&q|SiXQfDhR*J$wD@E;qm7;dQN>Nx~rKl0GQWONO6g7rc zigal!MY=pIMFL`_NJqd*k)Ug(NOy*nA`!+)Q9HGjBHgZ)BHf;qA_3n@k&thtNJv{L z(&btyYPYdc^a;L6;(V9GN7WLQVWmg}trX=~TPf0cq?O_T`V3ep685YV3Ak2@!f31% z=?+*a67;PU1CVE>NLhlNF5A6=mB(6#LYR+ff1t-Rkwhh`nrf)iRkQb!8ZwZZ)wE1__M6>C+xv=iuJY0wC#u3Z{C^Uesv>giTQ9G zgrkIn($#>I_m0nP)^4EaMXT#C5vrKAKp6leB(;UgXN(PMy}@bOXY1CtW6_JDO;fOXgo z1N4D)C``UMG_QaS2+r5?j;NGwev#-;Gn023?z_}ugWA$B|3&X+Z zn4_BG^t%8{>8P<-Jbp-6ibsvb^6}W+fTeuQw^%?*?!oOEQb6WgEFmZoqd2BO#?6-? zL%S+RceEmN7g#JCOTj-HMO20X)IO z5{gWh7DRFh5(ViTB=0rk!yr%Bh{&(YdS1UERI11Vm*Ec7iNUuT&SFx zqnw#z)R5_hiEYz8Mi2`e?);#xYr?xq@v}C(t0Jm~Tpp14)eMP^5JgmvF z@VY?JaZXV~(gCJoln5zby8{J~lGbhZCCze~f|AJeh+(4YZJJ5y%28Aw8ro6;1M*?v zEq<~w$5tVnWPn?cb3){}6NN|@)Tt##%#*s((Mp)9j4Mo-%DBP=p<7j2QG8cIT~`rlY*l0l!&+y=RCwBa z&C_O>Xw!huv^K*;o2vJy>*+4ETh)jkIqV?H?MeB*8^<9KT>q(;Zj{s|}CwW@m z_>X9PEb^zb71o!^+Q3!=hC8O#56&DCwJ;)hv!EYU#z1FkT92WPe+9YoW5jU6nea1Q z4MwwqPD?jLZB{71$>49^J00szI~LixUH_Rh|J@F7n!AMu=HEX>Zli9x5IG8 z0TkY}%R5#fCJ0_xo#zR!+haJZT;5$SZ(I$=>nC2Lc{Z)HaiPsiNhxm5MF0(ht83Rm zVR5?uj^CZUc$` z&iPjLhR)ueCgtDKsbO3fBKRptf~HMfT+QH5Y&H=Y>l?8pL{R_AYFoy1(O02$R=+R4{*m=7rj+gc2yW-EaK`#A zrI0Cd-B8r@_gYHH@s?7^Z>!K9k$*3xs6kv~_+Pt}l8eX(mr@9OODP20r4(T_ODS{* zmQo1%ODO@!TS_4=xRf#=RmXV?>}tfFK$q{uZ1?MMoCpUNNj$$11`-P&G?u9ef`<@7 z79G67QhNCRM$?=G`T<-8XnF_R`8p(&Qi3bsze%T}Q$)aCPXHft{$KpD3a!yjQBK$? zv<7Asl%Q`JrE+pk00QMSfendSIkR)>iqHt>15bxtWQCoa9N=vWV03_Hvg?XwqUdA+ z%p*;M4t*iV#EA01*<< z$&;B72!T9^ykas550PL3)>^ee#oAUGeAKoU6t%AlUZrYVz(>99Eo$4_Yb)B;+Xok{ z+S~T}t#!`&?|tT+2~cbA{eHjii!$fG*I9e*wbovH?S1w+bB12Wuze=Ab}5~(_ym22 z2t4$Vvddvvmy6}B8;QBXQ>4n|-ST1FA^EHZD+V>DdkEAUGkS_1SN0(-2GX^EgejI) z;L+ddz?m)s3!UYa!Gzhaf();6p=Hg{okwo^Mxlu#gR6?+wex^vgHibYYM-73R&?(?dyL{MykUt4v-1kTw z2R&2AL54f>dU;cZ?HK`10QAP#$n>0XT-yg@gHwRy4@v0p3V-V|$c{4#*j#Q7-DmH@`rh5lhO!5!ukF}`y>3{DtK zaua})A7o%UK|uMz9e|V}kkfc%U*tNB{dlo4+>QQAyaaa5r6#sHiLRk}?6MRR#sAb4 z0(Jl8LeOLAiWCA>@s1K!vfEMO9RNMuL6PB&>0XFwJ9RwuP90C)5#l(_9U-J^-_#+{ z&pQON(siVya(aZ<8&TO*l##?f9$@^)#er1xoE;?n-iL!=FnWFn0-1Yes3*dQx$)=> zgB&o?9k6uTNtg}yw9kVF4bsqYg>i7p$l>PBHvDcNoRiXHtSDur|!z3S~u zvjCD_b(c2u+m*Z=GV`~MB-h(>#)m53JRMt%WBod^U<&B>Hh#ty(vI=ve zV?b(93``BCL1w^X+8%78fwG^81?ouSSz03T;vh$=dzK*dPAQB~S}I9(X9;qqH)EI=_SQAm_dV+2ovd4LDdKvEt!t+suLkBA$ z|61ol;}RYM6FftJB9hXX9zIme^%RMD65^EyNHDRP5T4>sh8MZn@?y_|!s*dV^k8w^ z&N)Y?^h=HRS<}lz7xF)6z^R@hoxR*EC`F8C#pI5mX{P3tXRxSzGhi%hx+x&D&JdED zH)%j!naV?JsT2_dDkA!AamCq)Ly1{JoUkN z>YF;AFa~K{^Ex9db$Ipn=G<)UUuTu)&Zq-SEKxEw<0r-cgHpS3us2ADcp`hKCz3g} zI*VmzSh@>a9TzkzY0yx=4fpDl(&m{)F%F#(o-n3*XL*WrmX;@S6%ky(@&d&(L+}D6 zYu=!Xov;~&kvlHvp!w%l}29<~$HiIK@O*CU1$pcRZ;kFUV;Oo5e~>>1%slbH9bBYxVRZ3mKPz;~;3MO?V_}BT`Nx_ill^PN@6=nN?{nA@H zO}aVLTuk*52g;egCdB)BMnTHjCMBl(n?T8S;f|SS@Opu+2)d0r&!qtehUemdl^yI+ ziHfN!9k&fE*UTO*tU8ALPr1Tu8Nzc&t_lXIF!Ja_i)ru#s zc)bD{)K#7y;f~BfDmnwH$h*>{jz2T71{s0zdY0DQlUF1moGqG5BB7OxcfZ9oQc@7D zX>{_U2662sHAhPXagp>LE? zw+-N(c4;fXTrK+(L~4BWN{udOKai7VZ#QyJa+yPcm$EO`PrKMN&(h8yVu3aX%wVLj zbC>7oHU-9!wX`JmO`fzOc2}H3-1TGHS(iH@#}kWZm=OJ>=3M_m@Eo@Zx}b4^)tfhbJAZ28w2Dxh#r5xIJH<8ZsRfeZXHuN%~ z&u2}Or)&_*>z>$3&v3WWKh||^H`;S&_4O!B8us%jO!{YeigeaDqdN;;7Bavy^af&F z&`=KMUP;q>O-*ySX~Mm@8ES4Y40CTVh&bO4pJUVa`XHO&EUG~s+DuXrdq9$cJ z@rS#|I44i^z$IHx&l$(;4D6S1ET+r_wyb0*lcX#x-Hy$4?{xG*X!qsabkk9eLS6%S z-c{zdm*Gq|cp$U~#*0^N#~@d2T5)@akYkX$HALR&?H%)(W-A(-z;tKKui(kGV)wiK zpK_63heVdK;FWq~3baM|$+quQ(H8u4H zpR6LBCbNcNKg%i7K0kMDwvk1H-xGrF?Y}`JK`SuWd!KKJHpuA`&yGG@FwDD0l_PC9 zv6Qk!nKHoq%SO{b96r2BNm+_>)LEX3hTVd+?IhJ|N_ z^WLx^znj&7XZXqNFDvFDx>JLfbDm9ajwHE(!Eusu|H5~tHFY(RGV5tqdo!~R-qXp; z^vH$3Z+c>?^sXJ85$3KPNCR6N>A6axQ3==4{-+rlGK~7*lEAZSa1%_L(DC-B;;vRU zcViDTfA*9-fjH>J*IVXpm!mK4c1cFyJz1So`XHqHBBc9CzILkeUaaQr?{`r)Tr|LQ z#;G?Ds|lVp^u6A}slm(h2CX!BEze_pDCwn>(lE1)>uz)8h+CaZc!mr+r!bsvo6ydJ z>vd1Y7mw3bIy!{I?JNpl?;S19D}31}vw&RqxerK;^2GOOcZAXADjISXqg%cZPkRO? zA2_#ueR=Ub}%C%Cg3J7}T{d7$LFPzD=47Gf6VI_|j& zUj<74v7Pk0U%E)Ha5hWnmaoaq&Ycl?jD!L_<%Tb>(Q(69C(@H_m%2P81vh;4dKKHH zMDPyIzi+MR9V=!U#av03aLyE}v#ArN$fhzfc%XRJUYYLLa&I8&r4QXebk|8an*! zopd)(#AdGz5tr#koVoq%^cUZL=4#|puGY_8bJD!*Qt_Nv>h2mRINDqDB@=pVz)cZ@ z%=nc_m;%V-ao${$^|IX2qP*eU(mJhm7j>q0-9^RJr)@~O=S% z8=g9aoMehM^_&YbH%ffBR@`}q_wV&|>DePlxt~IT;GLd^njn(Nkv3yw74G&C&8$?W z-k~mcPjF{b|H@S3?$^_KvtOS+Z%B}HDxmI%rd%B9kCIWW17!?1SjL!mO5Kk4M6@?s zxYIK3Qp$zG`QA3%WP#j7y3^!}LC6YCU}g>verS=VSzMub9y@R^BPRJ%%*S7{agsL~ z#ThKfD3Tg%*D!jp#rwdE`&bJ{m?z)6nZ-kJLb4ww08e(o1)%5oB#JZR4kynb6{XAt z{@X<+`Z!wn7M`cahoriHD1wZhaN&niY3t98E!qJZ&C7cbtBr+y!l znkKxru+UQ+9^TcOw-5PT4)!t0&Hw-J|2Yo~q<3qCt^c6aTqyKsy0i|_A31@`v#yxb zT-UUAlJga!iS*kV6PGt9CN?xCCbcv#H&lc8{3QBkQO#wojjL+uyT_AO(|dX^z1U@< z`64!x-E*?gp>q2U4h z9Xnd7dhb)K66)R1k=AGIrH9qso9(XesGo-tyVS#*!(&248|Ao0Mo<>&E&;I*!Td ztu4zYPR`Bam^|(Hr*}@!YiTI}>CY8Gy+s<(7ux8%=Y%N^TM{&;1g8WIozp=>nA)$d zt#74D^ydZD_4HD2O|EWDG;)N~A4ztDMOsVfv~jF9SEuM+jDZ>~zjRNwr{o5Q`RH%REnjUx1yp^!a!n(Cjg)^?}?JMA&* z`&M{dNIlt}xal@U5%#ZEM_GAUxhl2?+AVu3?@}*Wb|QSJQ|5wjaqcC1sy zV)h{QXnX8!wKcTw!5w$5Q&~F?O`O#D(&2~RQ+;>ur&kBj2*~Kju*cX7DD0D)6BPEp z2<1AMN8+2I4#E#O^nVZK-mH#UHvLR>j~*mA(;m3r-mCf_QP(H7+aK(=8^hy=yrYh7 zvX7{H)baiH9{Uykc=-UGvLCZo{PEW$>#a@P#{G)hcxw~4ai8Kg-gf9;RJq&UucYEn zHx(x7+(RmN{&qFcj=ijM?SnMHW9qM)?VYMKWOt~CZ%7nPyL0+N^@H&4>x<^c?Rd*d zd;QaI-?J@z9w{=|&VRbaj)o@g7)kPgi^)u>%buT%-IhbLOZfS68{lMC(Uc7O4QhhbNdw=JiPSv;LpIht)$rHo& zwH!XtHh1f)$|twjGb-OxncBC78TKgkd&@rPi1xsLGPpK^X zsKXx~JupLkXY)~#8YfGnsdqPrXNA;nNPo4Xoj&g3k1>>HpH~a*Bk}d>MQR{CC0p&;WFI8YsNHHKpADZ) zgYQ{NM`7z{G@wtC7M*GRq%*xIEuKaWHJQdqjXDLAE;>z~X3FztGf8z_3?W@SMvIb{`86|b>j2Rht7IwgpP>Cm#w_G=$dcrx#m{Y zl)ps{iK*s#l@-1`M7?MaomkW`ZF=WL_GHzcdf@s()qi(5chENb>c``}iV0;}`AZzWG04_-lIZg$@~jD3qe%D%@Qb@*O~<7kFGc31NZ`@PPa-j2Ujv}=jl*bz@APjq(1Z|aOM z?2Jz^&o#aaow@s}+S~P8bryA683+ebqU%P{(KiWd+i;743 zx~1IsHYyFI;YTN%dD_Y9;Ay70gBGFdW72T`TO_x2!FdrsH#V}skKL_@=#nI zwT`Nx;RT^>U%j$(;-rS~1%ud_L;Mkr4pz z&f$E6uzQD$!XiGrcayn+Vt&e!*2D9P2strLH65!{F&OAKeHh@ZF=L0 zJu174uQF&MxzZlkN_o5UnnQGgW@vj)vWSv%k;0 zJBPygAazn?U8MV+Eo4SJrgHgH~;JRbe^Cf2xSyHpK;YYrsmj%f8^*1sj<87Z0S^e zcDB+?aGcf)UHcubu8aq#+hZ&19<+zWRr5|Y+U^RE%Lz{%qN2R^9YxDiwT{u0@PyE( zE-UzRL44vQS{o)Sx%&MS(tB=p1i3TMB*vAy7Tv4b?2&KmXE{v?wVv1C=Y-D>9siHY zD`rgUd|jP!{0$X5s>bK4;W4!$U**)RR(l}LgZ3~Q|M^$sHRsvWCr(!*a<}m!rk)vA z&;?$H%F5k7t+kPdMTiFX_6M(}_0>3gq&>PbNoWlv$z>hWTeg2AoZpYv@0Wy*({*TU zrrMaW$F(`Nx-uSmr}nVQ+N}n3P*#npl6`9YzCHFMFY;PG?iiw)V?T4-=*sxc+i$q_ zoKJfJA5>eubLgG#B-_b%+T~ZM-UsciFaGRF)l8G_nRe`uU8xGgV?!#JXVBT~$s-oc z#gC}<`&4GWYD=ihdJ;tVQ}&$;_D}hM5@W7vDpc7C=QF=yL0QqFm3CY6>-J0bu+ElA z6N@S-wLI1ww>#Axn+~cE)p2#pri6N*7Ob~!>Y{Q7mGkLn7sg);PaDkHCiDzl5UJq_ zf?-vE{LpLauQ!m@xAfSlKD;48$M9t#Lb-(Y#b2+iyY7M4?C;PZD6UlN_Nl=fO<{F4 zrRvAbUQh!Fnw7cBOq0vTHL1S~mf}yRna7hq+5g^& zXH@T_Pj98}p;;`pbH5rEo=t0x6?XoK{p^G+@=Kl{OZ+hHbbLRrpdR+C% ze`%02@G=TB7R_0*|HVbGS3Em?VX5kSl=?U`|Jf~vk5$r8TB(}%QA}6vQI~}$(omyo zjhJfcvfofw+DFw)dti9tkgd}%kEniK_T=_AC_;{I4_`Qxwo&5YiG$RVBdT}38rGqf z+9OwWo_}nG8lJ1_Dc&m7xZQ89Yi%!TZvE%*6@w3juRp_Hw4El(uGfA=BGvO&EV;Fl zW@9@)8J;jG+=E=*=D7WtzuWC*F?Sj(KW9H7Fln56Vo2=^Z_ek;-ZWGCWm2dpJbAbp zw0i;N*h@odP`!YD_0H%!QZS=PtuLIpo=#sFQvG5ok!WqSU+lb@Lvz^fqVPq-Deqt7 zr0Z+qZ>j;unRNFM`yDkdp%!=jvGq>>f0NXNBZFHiUu$%(D&Mh=&@o^AhZVjcbn~HW z*7K005xJ|z{$V)MFFcAoKU{IZfBWzDymN8mEKD7bCK^}s?g@3PSr(U2$NJkpDpME2d0x)Z)FfN7{Ek{wsUI z`z`D8{`C=iOPjrD1^Y#<-lqocPTpisiA|3$vR}M;>Vrg9>WOxHrvrXKKebo&ldp!C z=BUhl(;MOoRf6{Q^3{ey%J8$+skRsmy~XRB@3g0=68lI}P3kJLw=SH%#~wxNQ+t2u z;>#|fNiO$YN7_#|I~T=DeKll{T(sbNR)N-L$uHf)^To>Z3utt`(>%ZPo%vVHSos7c zutBQdKGl-1`W32&HrHSC>~GYML$nEK4^-RQ5AxQ@I}`F6?Z`CsjrROb^`g}^->#xP zN#2>HmBZ!x9#CK1d~iN(p>*BJZP|JD;ODm6pH>_8sXI5vlC7=(VXr;Ws{TMRGny_C z^Aq+V_4)Sj6iU!mLiG>lh1B)?)Msc_-6uRVq&}ecD}~gj+i6w_&l?_&_E*2K!qJfW zN;?Pht5*2hkXl8_Iy|PI%BBe@eC{Ahwg2y-+V(2CW&M;dM9wcN+J0wSCnb=hw1nQlS*ImNNlCTT-xIH*y@#jhpX!~j z*5yWu)~hYA-cf1>+Wr> zZ=ayQw|CW6a{An0=f7<~UG#Q%3Cjx3Wf%?S;?e)5L4 zU%f~>ivypYFk_o)b>@2K>gh3c-I4GR(&I`B`moiLKGW&+G434D2>su=Q&E#xOTXjZ z$iFN?)}*Y~=^9qA*4^t_y{YTDk3hN0Nx9|Xz)_)C!P9dq^OE~p;+5a4tgM(3U)ak3 zPp5#OZG~SKop5%=vm6(Gmn#3SyU=P_zFfA;PvHZTNPP}r7ep$=1%pEi-kJ2(1=lZr zzu|$)C-X?Zi1Q7Pc~!BvwN9<)OJ2V8qXlT!p!Xig4u{DLACWJ@)}OlZ$lrbs>|@@< zl2H5@L2Pb+d2d0HOLZ6#rk`7M-d9cmM?UlgQjOz+McugIW2nT&&^@+Qwe*JLS~te6 zL8L|4`tXx&gjPNOV?AX2Oz&}}-!(q<*!8)Yg4J3WAqUXSl_D#@Sc|%gI+o>`Wd-gOOvZt%M*q(4Ux#}M?JgVufoU7N?%I#|EevX6Z z|F7te#HtqR4~cJm+x!&0;psF^%T_!>wos(s5eh}s8C~{-O7*4o-7EL6sH7VuYWh97lI|!Sykd-Ny|4)%1YDsndu&8sJ7e z?$WZ4_rk~hL-P;Zc5PX_p`l^AT`;I^zz%zn{eT*g2+ta#>gyys;v*@Q>>zgL$nZ#o)if|ZMs&^>I>Eu_a5VoGA&rdMneO&+3gBJ8^+`3it zgGeo>?g;kzNZ4}*J!LZ^93m@nsAs~~P>QSneT$k}>RM~pPHg61{B;d#qaTiT9(y4z zQx;MuORb*4e2T>>;?aMZY92*kujRpOKcYufuB=xDG1_VwSxGn4Z{Zu6g>>n*k1k9S zbnLR{ciNXf>D;|<=-gF1qhh|jy68RHsZxiDp?4SW*W5!FV`nGoRO=D7jvht0BTO5= zIco4u+KVjQ6<2hLS+5=m9if}`KiRx*jT&0tK$~}&T?^C@I?;FEd^L*i1n#6u&0Mvv z@G^QsC2jc5Ch9?T4gLG~%}1ZPfi_2T?Y#HsLh(<0#b?j_;WcXGL6y66(F!%@Z1&0u6K1yWxcv3%)jkdBhPs`lh4u!bWHoa4y;dDAaZk$ig4AU3&G^=EpQ$~m(CON&}n)$t#yA6c|N9(yOQhUC&B zfVfxuN)66cSH)C5Jtaam_vucCbJ08QPa%wdN?gTskop2^aSFO|WKO#&2_cISI8t9ogS?!-@ zZgJUoQAayw+>f3on7ALKwGr+{ryp-QZ0~B#+kPi)9I8IC)|)6*99*}2k;*QlTPSZ& zn?8Bc{KM;-TNX4-Qi%?7cGa>eYIvb)Jo;i=B|Wn=P_@t=f9x=AbZo6wtw+@bc79wn z9#@wfQAG#U$Rm$GT~vN+^PZ$yOE(gBs)m?4W2dT5gfAf9E+rj4`9(T;Y&8uRnJcez z+Nh<^Pp~g7?|d+ERbvZU8$sRFU8_6b)ngjI_ z1{N(VY1Pp-@s{(Sp!|C)O|$$Efv@26UG8|soAcEdLmi49f!snOJ3@t2h4cuI z9?FV*WW_FC*lEvFKc^~Rqblq23FfQsQ-Oj7l^@rl#zMc1n{3-7eIO_=eRJ)z*Ti`r(Wb@g9V z{bQ=EOEn#&Cx>B2ITa`<;B2(peZ;~O5?$5m5|o(#&Jf5l-t zZ~DCHRkUw>F1+IAjNm2^*W@^N*3$DZV&2Gx?d+YxjmgLc^$ zlUkXypvtF_vS)`w-^S>`J?UnZdz>cfy4Nb-qpQl^ z_2kk|Q8@qmX3Fwok0%#4sMWbosB@j0%CsyTX1meN4|jwQW+ao&=3s{NxK_qr?+K3` ztj>+Srk1)k*olnobjOeH+>#cFjKjO^6?N`y=|Xn*O|DP7GN^AF9Ife=_@USMam27H z+)1~u?3?H2(Y?W3^+Rj-p8cv%qV;QP!9MjA4cV8ie0BcuqPj`;Alywq^!iN=YGv21 zL-cST-Hd#kANtx@U)0jNVf$fq))87D(4FnfLSDa8gxD+S2?P3cuHhOe$%U;N`uv2Z z3}=w?o(o+SnO}UOBw$@dA7N_*eSVTneXI%N@BNYi?S6Li6D;l&M7wsB3cCB|KuT(% zB&nC7vLlb*Z&6vH!K#fPpMTxv2b&&Ux6`>;Bwv2ge}hTjNAyS6qU%TY?Pc%c4x>M& zJAd*$0U=uxKo)v|oS2=J7v7VZWf$}bH#rC48zIM~10oKZC*|2$k?`y++p3cCUOAuZ zxWck#W@Xs&(7KvQrjq! z{!Y8Ozn!+_Inn1GZRmB^5)a|ROzNoT*?l)^biGSrRH6*JtX&!E z+McIvM-|C-^gTDi%~*UL$bY2o%^Y9bI6k-Xxa;gWJ8Nn9sZ1JU&r_hjKr#1S())XC z$~8fvE5<6LBg=nNRL z+`)O_cFqg8vE4Vb-P<@XY~{SrY0u7TQY&aAM#u$I$pv}jg7M^nk>r9L$_Uw%5hNS9 z{le|Rm#8%YUb3*WQpCb1K8G za?*=6n`E+n)}#o1SXNB(S^9C(6uvdhI4LAiJib}Z(!2l`-$N1+o+dB|aYfnEfBA$<3;e_EO%~i`jF=i*)IM| z%~w&+xR~2#o*5+0xaRszQh%&l-B}+neV5QL6*|dv)*tmU$w(MG{$&0)h5y#S*`IsE zDzC?B1mMZn2O~(&SSHysGva7`h4ablv1lvSV|;$EoWIhX-{?Jmtef*ZUb%kWtcX+d zG3PVY-%a64kG~80w5OEZ3efXSk;DDSf28L+)`Ru_=Wx#hpOkDrf{oXT{vgDi%Zu3O-dC9&npwKNEV-(W$~^gb zv4`WB?d*!W`W2gel-BQmO=BltNI=f95?9VRGk=+W4&UV&0ax{z?J4ox#edz!5!1(K z(KwK&@pd@e-Sb~e=VQd*R333SzbyRH-;wYgy2GPpb?jcJalMfhZoM<49$jjc@p$Y` zKOQ#+sUDv6y2R9L;(DwPpWh;K%jJAZeqQTw$UN5}+#c6^Q|fU${Kxd}uBZ8j)$tII zgxg8^w-CR6_J)PiUw86(UfE0hc#h?W!+p~Ew`p}Z>&aQpHGJBYFT%meL)@Mfi#RR) zS=uANIq@mix3l_XxF@>PoAc0$Z2FML5hjTo>emw5M<}FA4C*B}j+rk{_!@;TrJw3N z{WPnOx7XZBiR!Q(EN7Rb+0blvygC(WDEUYW?Z7DpV)pS*c7xX*DAQ-Hc0K%Uvw;x|X@}o)CSgADnex zI3f9SP9GW#&W?jKX1j}z*(C4Rq#y27jY!rXXH6{QgU#No7*QmN1&6LQSVKu_Y+^e24SXF zu@B>HBz5N>rrSfvuKI{0=^T*<`kO+hq2c_2ZZ$-l@>MR`85b-kD)gN~CqMiALo4?b z{}lA0t)mpm%szDGltOXWg)IM=$p50qr#P*0f-y{TDOwBNbn2{MnZIjA#NjmS@Vqi& zoJ&hKC+|+6v&{FZ@O>sAm)VN~a+fx`a&cWkdc=rvcAxT8xx0jKyOHbiIistf&wSAr zdPJ^s{YJZEh0D2 zztM23zwelJ75(G-T~hzizxjHd_DvVk((*L-G0|S6DZa^P% zL2a;odFvwFoHg3{?yVWKlxYMx{O}Xm8e^7&00~nd}V3tYOA{1y@^NfvZ60z($ngR74%G%Rob|*?%Mi! zt7{tSteN!G&9(Kj=m})2x~Z=5B6_J;bL$%Z_FA>`^dNmjrP-<`0sJ7jRZ352G_GA! zu!^3vT3xp$VJ&D}v$k2cTtUxI(rJqx{%oeFITF_Fnnca)#%8Luwt0hAho8i)u5(_g zRo84edaxRFp6XQBG&NQ83$a8^N3{ht*R5@y-?(OFT{GHnjhIWX+A5)@n%k&4*Y5VN z9!aNX1NfUJWJ!xvU9-BSp_;#ZV^N*PM1tHSEtV!~mal|R)6A^3t5*}ZV{tlFoNB`4 z)+%4ak{fGQk-ux%6;?rQEjgy;+WM>L?&5~%TDr+-Ikp8{D1GFsueGTqPrEg*rH58) z5_GS&)aiV8;t*e*SHD6m_(pFQjrk16&SXZrIUf0CESyH!rZF8+Pd)2C0 z^p%F1<>U%_La1>$IjOpizA@6+R#)wOYoxV_kBK_h2Ts4CImavAs6s-PQ+!o7vANXY z^XXkvbsIFO+;8e2)a5QnhW$PHk+zxZ?+UnLOMyRoT)mj=B z?jtSqiY`)zSgB>hxNLdtY-5_!JJpG`WF0@o;;2!xjJ{A|>ea4s8em5-cWaA}of?C0 zYUx>>wQJVU;3cbA=@yG#KDUgTmlCx?>4frw#{iKp=DD2mB&efKEoGABE6BhWl1fVG zj?;bNj7dJVx@HwUzU8XUO=N9dZFLKc z5NmyX9mNSF$V>57iUfy+zx`Xijsmr=dU^A5E74rDriF$RXGCEpf2N5_Imxc)Z@*Np zaYn0lNb8#Bx_WWCMX`y{tZ!YjoPEdvQtf`f(pt8lW_^^>S6zY!c^=wz!k4ln<)Z2} zHLLX~;hNG%+#_ITHJjJ2s&*_OFMwX(T!-GTPT_arblK{H1jXI5)&xaLZC%T9H;sF& zlcs9iEC{J?$Z^1uE-lNO8=GjhsIF;Q-q`5rYZ2q9K>F1;dbzD-^Xt|$Bvx3Woz+s;;7sDF z11gY2prA}%G%L(0zh+k1ylbziu134AfsXoacXDd6>gkP|lu6xI*nPecLL@Sb-ib&< zgt$4ngxd|TG$Sb0lPohOH;7ZoL)9$KH-;snq_ja_z@^2A+Xe17BE8cH>~eGLDfMwv zDx4DR42q`4_3p6nCeN1EdZJTy<CV<*e3d2~|t-+!bTl{L1 zHPF`DRkiqzfmJ<+LM?igv~bn>I(o{~&9$<+NoAP1;Tq0@elO{DYm*4F%4i`>E4RAR zM9u0ZtLd6DT5!_hg_hWerZ|3sXnoGt;G|&9t6y_ z+`^FXIO&wvG_MIqj_f0atms7oiw(&y<}F_>Wi{m_{q-E8zviFP)$}txD=ohun|om^ zFA03PTo{w0SM+czz9L6v>rT|m9#O!r2`yxm{9NFNh6MOuLh5O)w-g;Tf-6EQ9E)#h#GGyA>&asC9uyGH|{2OvN~n0Er>10&u>^S-@Y=4OToR5I&`v zDGE>l*8L7vT6WOygGE99t^og~bAg{HjlJ{5ru}lHAD+#z3LJ?^sCYzF_MUS%JRg2J zA*;$?ok*Sv4qWYPJ!F*!Yn69bt5s^V>A?33Eo7DYC8hHax)jwZ=mFso>L9-);_~a% zA?%hjk)Ul0@lU!{{nuK7-aAWzlx`C$F#>)rg%PFY+q8~=YlP(L zh*GCv1pL#@-lkCse@aUP{M@I#j3^xtD(MI~?N%=%N)p*5hcU`F#;k0Tt<`-1H=f3eiez*yXabC1cY;4MwH-RVg&TM zIymx*WW;@6j-0H4|K*UH*{-)0n!2$2#FAX;$vd|hdstbqfY(V0sCzpF`6z@Kzz zu0IO=i42;MwFK~(CY1s1(}QTqKMOpfN5PW8628!$WLdtylj*+Y2542aP2kV8YpQ-B z@Go)2B6ZHwuUWNJ0IG^zswBx1){XlpC~j zqLXCUT&5#+&#tc_5EtVkxzM>Og*^dPx5t1ywXAn#^9TDdgk2GNP zb%xbK3!&jjbaEF zUp6EDmdz;qP>3WR5Ejyazh$$>ItL=GA(T@X@TW}!_ijc3Igc6u^fYj9pnp6 zuAMNUW7rVMKVpb9O9l@z3z7WuHj(@@G?6eDKdqBYIR+ZmXT*i^^pws!C-1TZoSk^BoSA|aDtW+#$=MkkWLH*y2c(u-l^tcsws0xMx&{YfUqvW7@OXH^89 zRRL!q3sFTl>+9NC6+veORS<3am7V%kQiYWzEw=Pvy}w1YV{|)xVY? ze%}lXz#aP9q}so93|ZB-EcUV5BNChi4-pAYf`^FY&!$8|L?KZU$)6jEJhFFF#5qMQn2}&RkuX&wc8K(VgwfaZ#9sZZz}F24VU8G2 zqrqX(;Hd7KDBvZc6lJJaH=}U5)-(pV*~|COQn*IeXlX5q`7Lsqz>t7#Y0Px^VDnSP z(4g&6xB&q}(hxHU7$OBd6!Z7d+v1r&84m&4+8J@cbA-fG!i$1`soA1{|D{RsV28*3 zy0b99@=Wt<&osaKP^?f|R95eg^s)y*<`7R+Gi_G}LK^MFwS`f@4k7in)Q5LQoaTao zK-wVy(9s@#zr{VQNdDM>&He^yRy=7#kLXB>0(#nhPjoGn@oYv@U?VTsaNOT8_mSVg zkQMg}PuG>75&!KruJ!lXf563h_!Yk;#+}ec7I#-`psrONtQF{KaF5cpqJT4nL_K#* zyyqX?o>TBO2DIlCl*TA_``bSj(uS{J7YYLCaG!QX6cAlPZU0s@hFXsqZa|Nw;8rp* zK~rjOvye=_2?R_~$vBjRMid;-1kDo3-yFw_zrA!ZG)sEMLrpttj-icW6dNFc%hK!E>tLq!sUi9C_SL&FXb}#gt^@HEAXzIdS9~yLVs#U z#Hlq;j?`^V+4B*RQ}Z=TK+1J;s;zsLgq+&0S)#ZIx>#TG2HJj5mfPRg`)N@`(;a%- zGf>NtzZ^NzEi}MqHK`o%%8*OrO|Oz9O8i<7{-gCUAl??>GPeu;X!td3>D*$(EQXKG7ExZEl8Dj$L^h-p*bS)?fc(E2#78DfN zg88ion4xP`1EMw!Dt`>6Nf&Tso6!gmR#UBS%Gm>k3lN$R7h0ZWloEb@*ej=A(kvx_ zyTUFP^&BAXM!T_((wRLpBVdV;Tt<}Qh7s_V6h@RjYZw8)n!@>C3P!-|4cDnu2w97v0d%K}k^9>H^^S|`i?mKv(CJFuT2)YiD)cL) zr@7&M;3RIDrQH$-G@e=#^wbh)^=GYU9MCAbB&g^Tzr}N<<+#=$x>8`mkah@sz>vQVlQHvW6TaJdBYIaFFUZm9^mr2=j-KB#~OCRzf? z^c<0$tF5ax4X2_kDbkz_7}umqz%C)VSp=nhh7s`j6h51e z314!ZDW`~p1t07n5`;fsxB#Eiq*6fGLlxzuJ_Kd!DA*=UZWQPm0)iEF=Xxs!`wSJq zMbCST3glog8IyG{qMqA}-KhnxuyuJr_^VQBq+~SedBEegdydw3e#us_S~054$Z)x7 zW&*rYNN$9q1o>&Eu!M4DY?C8(7T|4~R08;-PBlxO5}l3gK$b*?m=cDb6_*Rl(5hEJ z$!&)8Yk{g4D#ieN38|O0$;xQ8Mkj-M1Ts}f8qJhrZ>u>wWBY-P8KaXR8GWjP`cyq4 z`b^RKQ~^#EQij!JwUIg~pDFI4DJ`gBm1~yyd`lpDmIpWRk0f4b>V0YB7}4ZH?W}V6 z4b3=wMzo6_6Cn`B4FJDp8aTKSkJ4dIr%NF~bSE`%aATJ!a6pbM5ZKrrSU6`(7eE$Q z12%n7iawa9%`AoRS3L~^pQHPw6kgb;{U5mMSRnRR$&o_-4uSU=()W70p8Js;iR(`S zjiOP%8;HvmWsFjR^f%Yn9D4!X2s^zF{fl-(F{GAglaaJ^msg07YvtI-x}NU^PdT4& z2!r?yIT^MlC;v@G^&jP!QUSzEwI3D(&JhyJ(5(x&QDogA#~xN@b|}Dgmz=#{j^sYS zphaTnSLB#3wfcE_Slf5q5NOQL#U4IYYiXwm2)bWXq5;u$gJ060PThG@4L&DlAL?F^)!X&b zS#qQ)5b!chDg&IRNhN>>gyb#`Q2M@RECc*e3ZuVoM$1`{^niK{6z9y9d z{y>uggXv~D1%YfZ@RxP9lIH~)Nr749n6UJdg*nACU__Hj0dEpg`p!$r*?p#>-<2p& z6hO@Z&J~g?8zq=djDQ^}jF9L*juQf1Hv!Jpq;fzs!;KavQ9?^p7Z8o6dBy-OpRdKo z0B31Z86eu=7Gt`_YYihHTBZ$DKq%qXMZ5kZ97oP#RA&Ue}le3+gtMqY!-!i0k0mE)PRB@uf%M7VXAeIEQ`wMuz z<|+ZireK;!gWeTuj>(a758z;EVwJ)Qm_W@fmb1$>R}}CGO=hQgh=#EKT38Ga0!Y|gV6U*?h6aRz zn?@a=w_-dnM~;%#r)VvrfT)-zNSlOvi>_4y_<2o=0)8l@^iGAWhjqnbz}-S(rviJ0 z1)U0ENi8e}2m$O=V6U*CQy~o8Sz!92M z0(glg1y)i)PZYxwX3Mq|5Z664i~->ec202;C3u7~!iJEIs7ej+Zw@rDcVYE3Eyd{IcQ9w`0ZFapBIE+a~CGZ_mAkGqWid;^iMI^c?=9-PJHz8K~mUt6!3LTD*Y9p?vH3l zp!t?vDImIt#sy+~lc@-}Lz8smm1&v9-$K5A zfVKY#Q>`)$MN?+$DHt{~4H(8c7mLF8sHZN%5Ce_*fahxq%3wN19ybAu;7Qk&uS!$D zlOwqw)qbR<2mJGnaKEQ(6$5@Kq#m^ObWRdcG+WCG>{&%5v)1bjTLSosCY1udCL|uo zB}tUzJ!`ZwD+RpVc6-xhL@6RvVgy{5!idsl!w7h93Zsq{0WhOl>s$=ztr%PcpkkS> z7z2bKs8ayFvVv;>$g0w^;(*?Y!8O22sc@^V7)=V?Ye?`S_M=EI_^Vy}D+-7f(>yi3 zOSu0@*D3-0ir)TM47f)~Zdald(pSuj{e1!P&uj6;fDdT#r4Y1RU;LM9=(%PO_E=DS z4C1lPLsvL}XvUp;P%_#Ft}lY(;}AbUYhMNkfh<0rMCn3pQyJhEA-RkweaSEa{xpRV zC8Ka)XMeA_d7Nm+xd(WL(Rh}?2Mx)uF4y$yOKVRk3murv-{(-`m!b^w06(N#EC)o( zw1NATb`-uVd|bDmctN*qmER?#r1n{0GCnM=|42t(6!2lKLAVe4BLA|LZ9u?f&!CTwha19bz&(2{Cq#RRT|cS z_X){ON+|K$$N7&KU0^;T9&fFtr7qxp-C`-AErM8laT2BeT6`%WT67srb1p)o*XR~v zfT&1UnAxYU7EeRlmZ?X5)I3H+v~-}JGA$! z;O7?&Nw+RwsE9x-)cJ1-_wRJAC?GtWW(Zy@8sDHbj|Pp2&XwkNYGa~%q?vD+=Fm*G z?!Z9!`DKT#CVR0@IMdM3Ueh4p^O{r)2#3-GUGUvbqZS}E?m@S*&k3Yfv}k0NLKZ60 zddlAqetU@J3egYB5eX2ospIc!hji1+-AXsTTn6bIwHL|(5lJ+cK(^7m4A3-Jj)+0O zrP%<FE-eAPSCc9LzbGU(UHE+kS#e#l81M_4R0Zgj6r68);I zk$LYXIkGCiP=yA*zkxKlphAqP)NYFc!ZwO+K#!(B+cYew>CZO#HGNm)8m+3~9^;AX zprV1rQl^-iB}eifAS@?E0nr?J?`hp1XwV`0n{1*BIug*+>cM~~ zo|1TmFIg6Fo|d&3FkeXAwZM>1Q)1AGi~SZ6mp_<@gz!hKvl@Q0(P{8GJ({w!J;3#x z^n@jvk_Qh2tj5V4VIooQZ3>982DvH>lOrV_z~5<7Dc~_7xrqlQB~OUb)C_oqkX%NT zZZ(X6Uru2}=`q6y_+knpN zwYE{f-)mACAPk_~;a4@yYzQSKa_P#b1TZG&D4_!4@mseaQCevj0apphWke%54i!)$ zN74%rGQ;#FC~%!&14KJvD`5enO+`+GIJ9V8DhM*kPJK>5lN>wbNGyPN8*d^#& za->?{7WjfDl>&ZWlS%+z(xg(rS2d~RUj!a8BtiPHSI|?21rW`qS^vK&+*$hGeF@+Q zy=`2YC$PYf0Iw5L`Yy(I5Aak2XJFtD^xg9%fEjXglb-6UOJ+&oOnt|53E(&{U!D}^ zdWq|$@EI==1$=pe)@@J8JpsIlFx?a}L41>^eG~<}Pe?Q$?Ai=3!6gn+{HqVEq(;IB z12hf~?D1S8+;}vWh6*55pz(8?A-uuc|-*U4j96Wd*MTBO+simQ?}>>(g6= zimke0F(3r6MZjKRL5m=)NehbsLI4R{3hWhjIwr-_RSZs+Tcq`W(pr=NJ}ad3zCguq z=!(UF5Wv0w_6iI70>bucVKG1mU|#@xg#~>9Vc@2?0Q6Q2`r?4JeoSjo0ytV{iZZ}4 zLUP@MQmtVGtV>};X^ml&=Jer!pg+oy_ErH$=~|_LXqojWPNKBjFan}wmk}kSN2yjo zK$FOLM9V4x+%2T^v4M)_8_dOk5Wukk>=hP_jlI&;uZ$Ley(DR;*8&xPt}7M;LI7zI z0rmh zz?V{Fq4Xoe2$(68w%aI51N6$I6!5|nMwF%)MnJrvJiQrT5*5CqRfz(APe>GhRnYif z4I6YDsGAIoigMwGV{EH=*xe!iQV%H2!a?6JkTd>~<(EMhKvPlsvs#MoYlac<2~8>nd@`kOcY6Gr)}t8k zGg?+TAX;WUijyeqHjIGYMuXV{#-kg%c=lGGd0}km=J9W(Enq$;ExE!p3=ne zA#3QM$*0dsoTKt`om$$WJw^*aSoA-jg};w%(I#7K6$SjXCY1uBuS%>|Ysy&q8mJtm zj2->K<~Hkt&1ZgK&FlV@$CU#<4=$bj)B~!-I$LLGWHqz4(PbwGk(A8n? zR3n!P|ImJSeeyrw*2PJp^LXPQH9|xrROGXUfYnoIF__~nX`39w57)HP5FUzSnHA`TMJ|?I7 z%#Ap;X~qLwph;zbQ6ae+p!B$5^lJd|Va-wuc%deh<_er5$9`5bCCT;H=(~HgSmz}{ zo^NUZLIv8g0jxD#-Dxviv%~-+np6x3v)I_+#V0Hqq$|b&uhFD(Kq$wu;z^XyLYmF_ zkECCqA4d=Hc#+TF;J@AqekIe-M~`1vr~_XTt=;b))I0s2@k@YVC+UN|qI~AOh*O&a z4zREYq*A~VA-MsEQr&#b2zb4aTt<{OEzpdBw+P8)MCo3`2zWGw5v4yGM!=!hxQ)0H zQMyW~w8acqox+Gxi(v$OJcSXZ=M5v^M=6XbWn8PR2E0H>u8t^G8AiYjDU2v>F^quU zN?}Cl8N&$plN3gjeqk5^|C++6OHpl14}o*!=o*7k+%N*(n8JwC&4$tP{UJEBbZ`~} z{!){w0RK}+{E#C;^A|dXt9~pY`5PUrRe;BY#5E%lQCI88szOx0WJrj=-y0Gl4c$)9 zqoHHbZ$t`OUF9>{3R)e5)eE#a6@ajmy&uzduh2$T0Adijj3~8h11bPvuFHs$>88L} zmo|x3w`=X9fUjy&IiTs1#TauKQj~ZBzph7D6wo-f9F8r}VOtJpe7!j6>vF%Zmy3Su zw4PBwqh}eq_DrJ`;02mg25Z_33D$hikf8but$JBd&%l*%kHUzf`T#ld`~!T3(CBjB zYO(L`5uAapmyxkm51J_80U`Bp-U*D-5yKc94^f1~VTm2LuHUrWFU$@9t zm(~-g_&Xi2fyEON0UYDJ;TDAv;w2I_Mqq~_{aE@Ro$gfir-!s}%tg=i))7>O5Jb*Q za~}$-q89h3Uk9c^pPo8HO-}mNVm@Rr^cFv<;#Y(Dpi+q>UFP$5oWD&Pm45L=@=Hpy zXoBkzptM(H0izFy7FhV8o~O(FI`$NAU#z`e`k_F$ie`EwIi&tH_m|NDMo{!G0YTBA zpg{0_UTW>p8l}lUf$x|+9H4_4}2>1&jxs2U4`W4-1G2p$r(Q-gE!?KE#D1BZxS`O%K zG`O1vOCQsX#sELB8?69DGwu|K5?V;}l=r&7q`*{|EvH~<*op*FSWn^UtHneC;l9aMOEz84=FogO=D&Lx{E_lv zdeS$~-7LL)T%eWtB0a8Ki2<$?QZK7z#N9ovIJeunjk<0W5Ow<-4O{4;iUm3LAQ7TQQJ*4D6P`6iUIMaF8Xfj3q6x4wF{$L z9VMemv0nw0vjy<<47^!rG`jqfm$O1*J&s{Vi*CxEF_mv3i<$X zjk;nK@NP{i1w=Dsk(MA}uN?6_8g(1sAvu*^gK{~$P>v)UaFHgJZW6dvlcIn|sX)*{ z5UiwW5O9SEa$aJELYtNz5CwzrbRt~^0xp$Wed#tt-;d~T_$Jz50~HMp(Px{4>pW(| z>D3~{uqC`~IK5uj&eqa2Tbq}^OZc9YBPD7;JUmFh_i*5@h;tsKe>L2IcowifHP~jI zm(BKl^wE{W1L6Co)O}COC;|MbzU^NoC-q^NoWk=M)cb%Xx>o#vz!x+r3TR} zrF#q`;OA2qrJxT%RdjMi}V5+$@xUIIkpE+a~4pBMqXss!B`R3%m-dZKY|A(lp! zSUOc=$)GB+bgBe92<<^^w|>`t^eKv#d3UNi9wWRP_5Br5;U+mj`3(>Wfb!e=ZX0Zn zdi3x|Y-E8`NP-3dX)d>*#%SGa3E(s#@l_(QE7+pfwD5ZxP}zS3H$?}aw_-3lAOPGU zYdIh)_Oed&_~W35gD>0+)~!ujcW|1zQK`I0juZ-j*ab{)=~Ah%*Hi>VrgST!G(Y5W zQVUW=AMO=&T#npJ!rfbr)Txn|BhL9GXd}$Iy*LNj1as~doC7W2oLh=>pg~J&?;V^I ztpbN}LLrL)Yc#3U&)y`22Q*6w;0>Y>*$sHJCY1nwN=U9-QM$u00{%dgx>e$Stwb^4 zCS9ux5G_*_1EN`0qBw~XS|&z7qeNhu40LD;P+ zy!eJK2ek^tep}M5(fiAjbVKBrW+D8Bocede0%+++t73q7eIMUW1Rg4E{pcCzeL0E@?meilSEzFiZxrUupmex5WffyEO!{+19)2oIVg0N)blIIAKQ;HESy zou3OoSowF?{muD#((Ivw#S@5rDHy_t#&mo7ex5Y$0gETT{VieCA}Z3^@m`@EIimujljy<}iXh0-+-ZU2nF45@0mQYtJIAAhRXs5RJ}q@!MwEVRBm#br z!iZ9io^wh7@iS+xM3k;DjDYtF$z>Grfx~pIN--eJ;flpcl(rj2K$zn)qV%d^1cW&* zBTBG{RwIBg$7MtbUlAilK(BG#uhQpeRbqfJhg*ng)+pFW0m@ZQD0AZE_MA=J3b|KIY*AhBeFwjMqYQyTHrz*op#T z`Oj>?9m2-qfVXSfk0e~fr6h^crG^o3swR~HUY=4HrGoBPaPNvrA8FO14I*Qc79V|5 z;P(ybX9ABI()$9lbaTXM>a4!S*lt!F8lW@+BLS#nZb}u6e z2R)3yFMAnL=r7u_L|_=>G>yU-4Y@TPbx>de<-t(ubgG#Zc`wU8@Wb%CKt1NtAYI#$v!)|uSBpZ@3PZwP7=))AFJpbuDKkSj7R_W2AQmjd1!z<#feNd%3MGCO(##E* zKc6zS0G|<(>noJ7(?og!4wp3NGNN>WP>B)n$`nSFt~QK-`1J@^B1&b35wJ2vB1-t> z4r&_kx)es;y#j(>C{E{v;$+YZ#p%3IoD6!QIGq=YlkmcPZCo)R>}D?%CsBgwbnO8M zyIn?YG+v0M^Fl0*7h>tW5KH5QSUNAn(s&`3&I_?*&zyeVOCmPRGN7ZSd$P16bBU(LAj2NeW>HO(Z1D!l|yzyh8lBzFja5yz1NCd-j3 z0!|UqCtNWiVsSx0Edp*kX^Y^(tUwh3QE?!z5Xa=>WrS1+zKk#`jdaQ}O)f)AwZf7v z<95lpomxx@;Io=k2KXHzxxPf{Wy1*ggA_)TCg|WO1I!gt`rg457}gbwMX)~nR?vl- zr4$gd)40YjIGtVaA~Z1NdSJqgGnLb#nI8x`mjZ1=p@fJY>ta zg&VTdnCBOq&OE#h;e4HFOC}4Ps!7Fw-q0+dz0%0SzF)ze+V%OO$#kS3dO%AQsi>!)~ZlsMQq%cUsSoQ@B8*%^_`sfD44B zT1yF->z9(w+$~c5^IA*^-~&Q(tw8Bv!wC2lO^N~jHKndCS3ASx=t@Khw};Xg`E?QV zqHduC5Vf+b8+0nWfqn(o?X^!53~~-b90G0uL+HmKqE1`JsxC%83W zT+>pY0^X^OYi`%iHbD#G^NSxKgvaDa&%gu11vd8|twTnn@q1ufY>>#=qve$Ydgaku zEQ-^~E0=2e;5VOcJHh&P-9&MxKsYnaSb<}VFDi8-0-*bOT5vhwMVb@^yjYWp0cU7Z z6^u3E9xyG~Tm@ufLx!R+C@A3bv!q$5LDmBrK~;dWwUWg_*?|;uK)659wMqb|hg=%1 z2m_Wf;K2(0Zpw^e=RhN?FFg@_^wPK^mZM8Eeq9}wLZmw zo@%zg9;)51tHl5xk~Iju;1Tfao@GfaiPC=?M!*%4#N8B!5>@~t5%60nj3}KDDlr0n zUu<_JqV!Wer7i)4wJzhS?Ty1;R3z`__^T}z_k2y8S^?`(EzK8h9+6s}H80>dwZF>& z;U#|KWjhM%v?ro~Xwc#FD+*zcYDLSTC`8f?{2N3ndVz)}Af%_c&A(rC{x>;t_6DA( z+baVs7Lu|O?MW2wHhj?QJwx(a1Gl3UZgGaN;|JjRZVgO>5zOb0C8qhqhH0m2)7c}3 zu1_0Xp*Gs4#R4GIaH^sJeTWYbvF-4o03C@B5TWhxpJv@QPj_ zRRH3L-iZtF2ZjqUTT+Lc4N>~nK3bgLk5B^dxTQo6h?XhF0P#Cu#0B_~R-zmb&9V~3 zNtBL@Y9tQuzdhRipZ2~6Jg%!a`zoTu2?5lQ1cwCJ1d}?D2-%Sx1t`eaPV8VOitP|3 z4P32OD{14^?y|eGWqyiCfVw0U!53NsX%Qt*LugScq%MS_wt+e{P<@bs$p=9Vp%}>5 zit^{ADfFE)Gxy$eXLsdnd3e6>d3qjOXYbrO=bbY%XU@<4yXt*<^v;u2+N<^FhlRv7 z>QUS*Gtg?f8gec%mk~_Z7%E1?s#I&s6eIip%j}TT|_`ZJ;#h(--=;yn> z9+7r_TYfIZB>npOa0H3k)`)xUj@)eLKgv&42i|ggq3Of=U9rCvX{ev;@9#w3GO$&! z6uVJ4SQNa+A`y1z&l65z1#p*0tH&0+s!>6^TWbprHY#X0IJ-oi=ShwZtv`EOifRj9 z)u^Bq)fOCVRPcC2y|z(7d)J0G8Wpr{v;_wn6|`-%1+Q&X(6&*d z!ZXCBV8^s`rCD%u`oc*Y9GB?~>9YTG{QrOkP7@h)t-m108JSyMB)M+MrbT{8&YvMe zeUIe&z1lfBen9ec`D0T4QOQq}iOt!Pr}_28rk|FX&(+$Z^)-o(eZNd5VwJ@&_gVj^sa({8Z7$5vk{!l7CzBA2q38%bhOe&yjqi4bGu|GPI&wNPogOaEDzbEt`O8$uCPZFFo|7(P-W9&OWgX!@^pFqNbH${|7^+i1FBPktKUOSm)Gyz zo|od&@6x9E-~J?~{FUVTO;7y@qke%=KewnKR@AR3rtACLr!wWsl7C(Df0q3FlK;Ep zKapI&sAcLC2fkPGuSouN$sdsXyOKXF`A;N2Cb@oYD_wuP^_(nw@TW+wpYcl9udnFN zNq-)dd`9v#|G8WH9qB>I^=(P|o+*8&l)hpp{rWF`Gnc+^C|!U0MPSSEs~q}{r+Z$` z^63lY^gUVn!l$&H`ra#j$5mP$tyf?9r1j{FqtY*XN|(P)Y@-?%mGkZ<1W~ta{bA(536w7lrF9RPl0(YCCBOd0>RgD z>=ZdZRdT&@f0i7l%ik^ZFH8Pa$@NLDH2*y*etl%C8UIg&|Cr=@i}6Znk3NW{&vT{m zblj~A|L;gXBl)e8tNzpFm$Orv|AVrQ(f#!SvD1*`Y5sZP*W25aPj944^M6nXAC>%L zlHV!$g5*aePiMV?_aezRNS?kC=USns%j-^fR?h1~6n`qm+Md5_QvN=n{~yV9M_t#E zOG4LmVH#i8hi8dC&(VG$x!!SeNfUkFE_A(s@~3kANy)We>9;`A_zwx+4L@x;du}|{mbyIK-FE#@SIQZYg)^58SyMr z4}F)4T0@Hn?syeYW|yh?X7J1`!*h_(*S40B?h)@_rk?x3GuP9)o+rWtL*R?;^)yg= zTA=4kdn%C6S()3Ot&Z&>%1Zo?D9(2>5d}Yj=Zm>xjjaP^X_;2g=sD*}I1EZQ9=Q-fXwBVV@7E0ATUODDT_%f85Z&8Z$ zJP4k-Wq3;9SzLyP#+`*_c-}+xK#Al(Pz=&XL3zkgNVDC=Fkc$k8$1?Ki04l5bm6ih zmjX|%o~_nTbCkGL5L^&ZsMP1ER141}o*#fG(}JfPfvrxANN_5|v9-Y1?vC|O_ei#$ zl>=&1X9szSpSp)@HKjQJ=~$(QQQkcjR|F8$GmgKq=ohZ;O3XtjogG{7_f$C>XPr1n z(T4t~qo{H{89bR~c=Ya5@~X~`yPg{aI(yVwfVY|7V+1nYlY`2IMvxfvn8^epYp=f1#)MH&d7Y83V13}RDYg- zQjT6L^*q(plK~KEDo#39z7`}IEBB2}6iQ#gIG&GyXHIzn_0@hyp>|Q2B@c*``YN@XeKkI(ztmUB0_>}LCeGDY$3X%du+EN8 z$}jcREjT7MbvmDy%`fGt#{P`vgXdg1<7Z@x*%r3wz9Cno60r_d^B)G4HBS-JpQDWD zixnz0FFI^COZgk1_dpf#s7Ke3mLdw(O!Z_i<%uKPcfmt*;8vfeI*UQLO4h(asKC2mAFXDE`#_5$MC0iFe%lJQ-}T&|f~x`;My z=IZ3H_5xBi>8VlA)m|`!^G)NJ^nw|vg6!7W@nO>r?FF>zfS}+Zd;3Xy!EGQzSn%lV z*5@P7JZFn~=IJo@l+S=8^33z0RrbuU8hNMydFI6kx$K#@g4-tY%nHcMji*cCW6zwi zm4HH?c_FOBo=LkjRwVMwFXBIY=0d}I$TNdp)pK*t?1MqsGmoJF6^fHa^`}6D*fS^V zg`)47BV;Iae;2W>xURx!@;c>llv_a=SgR5?_SHMVGrbJY*T6Hh49{cWSz3nYY`E>* zGCaQtp7~{Xt_4s3GCZ#a&*CyXZv)TlGCUsvPh}aNFM(&F1J}Kbs*!6n|=F>npe%9yKo>)o5&@8m|G*0EUU! z!?U1Fdz48~>fnW=JO2oRn?Rx2Lri%)DC7|_<-MScc$7Op8S*H1fl~1(_kc2s8~0*) zz6#1p_y`mt=ya{V=d2{pF;G@`JapZD-s3q36dLDZ2`>PJs&r#Feg?sB66M*+ng>7` z$|Na6pe&r5q)dXc^xP!ncd68QNy_^`na6PB_inZhgy`r;H^DY$BH7*z*GVNiyU3(C zf*_h>KTUMl@e|16C+*$4;8Ad3$aC0dz>)TD+OH%@Iy+|Yca`Cz-d(P0@9syN--{A{ zqTYQIMm_G`dfUIxL$ixB)@bkk>x_SvkEnOkIKN!)rd1O6?k+O6Nz}XF0%5p!&*R95 z?B>0H2|wfBt?x7OtD@dLbR4~V2ukMOeH8wO&X!2py9puDyTgh6gg3qT7+LW`@hB^< ztMSv|sVI-590q09qudY5Vnor^AJ~F61E|xK1KP9@4HGp^G76>N#vR2M6EoNyzWxCC41doa9cPUQ|MkD_PXa993qg{ z%^Ziq5p_IM2UFR=eb>E z_ifN<#&PPOU$)QFOI+CJw<$!FtIr>Xejy0tp>gY3(RuozK0gGqYnNM}V!%r!^7$X! zu0H=XxY~{s2mAaVVD860UxQ>eQ8fO0%-O&OdALxrhCKHmeGTlu`(J4Mk`T|KtH zQ&__ zei72vgx@*dMIQA!_PSL@j`Lr1H*ScyhFRUGMre(>QW5(@F9V;Fr0k86_lC&B;_1XmR_b5?H4RF+5Hu85t1cN zwqL+CQpt`55G<9{pZlMq_L@ZtZ0duAtY?y^9}Lus{B#+34n+OSA1joT?z`*<4_pNG z5D$4toODJ+_g!#59gI)PFYTw)m${xTI76Q8C+dSg|G4(Sf1nw;acG(moebCGK6srk zj8sQ`@K(4w_rVuq+VCk;5B0$zP`MBGqol2h`d|;V%YASO+_oQ5AG{cIQtpG#LM3Qq zDp4Q&0P5jBXvbS(r#`rJ9DQ&R0`u6k1we!vC+&liIKzGL)suzl?wa2NaSs4&n%N}Y zYczwHse5{khwT2Y7({-lKWC)Hjry|s^Bl@7H@A5VGPD0c5vip9b1Qi0Y$HFUBIG~! zd_n!^9<&V8&{QJ-8G&a>3{RcqL-L=6z3M;bHqcNIkpIl$Osg19zHv3YkA34-RBo#x zyJs-MlJ|9XJg=cVblqw-Dq*{m4?+=%r1qNM#0Z_y%rml1U~Ca|7ifCA>f$<7L3%I`2)$ENy>Bi?*w0{tDaG zdkpR1c40D*O4^DZokzL*v3(}txp+!_ql4BIe$rLs$D_7q>*Z2@s!;dWkyWfBx$T*z z_q@FUJOgXk0_i&&X$_NwZxrfS0bMGq(Wt-2TD=E+sdcXGt7l+Xs^!1C_9O@SHCIm; z{`yJRp0fagVu7_1f64#+L~GA?-m7cR-vxudRU_u3wddEOwWq#vHa<_kXzls$7z}vt z;%ELzIij`a0(!`DYtQdNR9<^-1h?%{v@dZ_v@dZ%Lo8aK4jjk&bTC?F+-QDPZW4XT575O3gn4i=S={a@MZln7% zsRa4qSzl2SISEA1h_+?#}Z#YN<_w%UFtraYJHDPZV1kL|Pe%<^k`# z#Wu+aMz;97BWjEFu!XIQY;i60LsshSc!w*O{zH1EyBk=~8JxC&wAb_!T-IPcH)>hn zuFU=<>hIRa2$yUz*TNR6=SL$w?=2KZa@lI)Zo|i;=l)2~08SIgOvAabK}|SM0P56Rafu# z5RuqdGw=-yW%W$)$!F9UHSoCf+`twRqgJCH9xEI0$ny?#k29TZv`^c;amTJzgIhPQ z#(C-u=~)3tE>YjP^8vN#w{YagUScAfo(7-izVrKBF!h&gT8V6mLBY)!d?xBUABt@H zbSTi*A#syUyKqg4Jge0{?EofJP4{VKR!Ol%u8|ds^ng{u?qMyD$7RO$bh#MScxI(` zXC9J=r1F#6eF&$}eDL_^=}7z60)98^UwVD#0@Smd-6{4$O~A6(i3pEu`mS%QP3fhj z#O)`t=|>`)UhJQgBeLo2aoF@T&(wZ8g_2eQWYhlRu<7)1*mMy3VVjQC!rEk|Qm%UQ z<)5K1XIj{ln)Va~`1#0Q{#Zdaq;wv57M9`JN(03fYBBuBmAW33Mf`GBc9aRif zpTkmq??ibdaUEZMBiPC{iOY!-lsqw+GxGQbBS%65bB!FC4^^Ve=8n&u4GB0U+PJA z6b-nZP1g;1_0X9(3D1T|^Nn_3;0jbCga0Ste`m*P{G}GgNo2lm03>I@M)kOP)V2+M zt$2X7>bmQk%#1~~`KglngO5ag@SPprNjadH zxe@pO@czcNu&!mJn3=&DI4JZ3S8ou*sh@r>>ZeaYCAJ=lne-km^1#lHi$nrHqrSY* zqAwFSU4I`(B|NX21%;wjoV35+1({_&Unmu@wbdYI&bb~(^2Fu!*W>A5(^3D@(s9oI zv++7=cWeLIxPeNw=Gl53SzsBS4b+31@el_2&)WY`|M@gp@9U6w$bW8zO*w{NOC*!X zHz;nfZ)9-ZDw2HT9-LZkjTT^fiK<`=J6@X)DzwZH^7!?Dv>8V6nVn#hI*w)a@!j; zlF)k-{n3i5ByXue81@$OV;)13aO5rB=cu=w2rLUnk>uJal3=OWAW{L>Z+65ju+iJ~t3xcIvQFi=2IBi|zEmy*V%gy~}fwi0`tUFgd zVIQ!pYRSq&$6@6Ik(I62sg+MhU2J7~$-v%_o^a1s2|F=}vz7l6N477MmG?zf{*d1& zIdZG5CL8E)b zf{kVc)U(fYyY|5V!v{8waF-vV?Wn7sN!R*0{?IJh zPa1!wBF|g}27g4O66BdDpQN7o{w{u#mR}cn=Ck2Z9DjbMYV(+AwEEH;b+qcYT?O3a zz2rnsLe^~FOZOyaz`*w;(^UbRXhfTSj>a*1YACj;a?^-58I5SeO7?P!b#(tc`-X2% zWuy_U3&QY-b_`^=S0ZUIp!XzmFPN%N)tl@m46vk)dcouIpE>pL7W)ZzoT)ZF1Zk;- zej=Nm@m#fO(~ z{T}sqr^DuR(M~w&>{TQw%{(cc3CdyBn4{2rD~p)8ktJC(Yl-6V&>dAXJG35+0E~`O z9UCC4zpM6mEI6-N9ka&6wRbN-H16FQCw20V_U_xj13@6qD*W|(w?>kI7pUg#T$Spi z2#|Y*dP~RYZfliJBocW`f8;IwMrLBA2=J7*Y6Ljn7e?wLj~c-LRuO7eOJPh?9Eedr=pACbkpmlolCKfL&VsUOme!6x#;)Qob+S6LSLS@RSMyP34t&dvGQ+5c^*oY9n!j+`e;Kv>m3x44jYC{=kxbPIy?oMhH$AwI=uWibhrS%<#hP@NQb2q z3LlaV>DfTCWUF1HpMsBdSiw>~mvlo{(TOk=>oC($Kg4tncovPX#7=Dj8v**1bQ z;8Ey4tR;^!3Chf1veer^S@0;cpbTNdEuIz3fimk+z6eVHb;@Hs;c~PY=1e5*O~>O2 z3y~)zDv+NVMb8ETkN8^*lSWaBv|xi)r|{RmUP*3kqr`g z?_vw@r6O*`#~g>}^K_S?zk{H5@A@s40`J%~NWV0@>%HF*mVt`y9RBb67}ZSr>AD2^ z!|ztT`+0Ce?%jCz5nc?K7-XD){{}-1IGHo3$C120d$ZLNd1u%4+?xn52p&VJt~H8I z<6B%*U2rALG82`m6tlTJ_@+?-adZaRiQ&Q+el6*oHYk;GHwh^75d{aq^HI;VN9hA4 zgNcW0JFx_tLFpe#N_aIWk)9pTZcyqGI+6B(LThT4hbT9JGUV0#d!Wp|K(SbdSV=+5 zIR3nwN_mtIf-)UZ)DKzDsHX|cz2bD|dhNipin&)1m)-C1iB#i;e~ z*BJFL6h2I%7?nYzmWxq~&_2)fDy9x1&`fU^Cbt};J_rx+^-Mezqh_NR^-?04M18Qo zMIWRB6r+xup)rb{%l4b5GnqRvx8;7y`>S%9#dTNppIPToq-P^a6kBH1pBwBa9FPA{ z&1BR2@NosU>3yJ}(o`aweyCe*+I%)hZ<=L$Wl)0^oNVz3e2i_eJB7lBq~}TtJsbT* z+L%*q*uJAr5MR6i=o0~i`-tS3V%n4OD7_RVJj(hrFb)buBLBfLZXfEA`$>)m{a%Ak zs~iujm*SX5S$~Q_pKA-9?o#$@UN>vd=~|n|v;G8weyA<KZa54VMWmqFie&<70qg9d$}E%ZYMecGUJG3ZAO`jNKKKVi_P z40^vo|B^vpYzv)M3nzO0y<*V&4Eo&${b*b0A2sOX2EE6if6AaQwS|7rpbr^zx@+3g z&-yuoeylC@+YS1lLC+ZU4;gfNDItv{k1x{B8uS5!zS5xIX3$r(g?^hs-(t|a4En7G zy{j$s0|vd{psz6KZ#C#E+d{w9p!XSc7&GN{(*`}$7W#}q?=k4~#U$V7_ZalmZK2;{ z&{rGuC4*ix=sj(r)BVC;yVhk4I^7BH@vNt7u|km%wy!PpHyQMm27S?>UuV$!+d`i< z=v@Z=h(X_B(6_XO{yKxc!l2W=*1qQHTj;*#2iiiPGU$OpKWxxnX3z)QLa!V2V^{@v zE$y8*=zRu#s4eu0L0>ZH^kkwZ&wBbWy|4N4w$O_P{is2oGwA0T^h#Uk;|6`vpdU2o z&oby!ZK01C^dkm+)}Wte(5Kr%A2R3*2K|6RKiQz~Zwvi;gMQec&lq%CV*6e<(-u1I zq&<6}UeYwWdM(>nCf6$;GYzuvx zL8s@Kee{Y!zu%zGwS~ULpwAlgaf7~K&=0kRzR92;Fz7=D{qqKWzAf~AgFa)>2MzjP z8}!3%p}*Lm?>FcJ2L0m(eW5M%K7&4O(6<=$gTEy7UV}bm(EAPg9~tx`ZMD6}pjQlf zpFzLXpf9$Cet|(BH|RYE{jCQ5Xj|y34f>ElUv1E*4f;}B=&KC+ph3?V^r}HW))sok zpbr@Il?HwMmxO+{LEmD~yA1j+gB}#x*}GV2(EAPg3WNSKgTA6I^wSJ_pFs}{`dWkD z)fRe}LGLl>$FLpbjk)Vr8T6HHp`T*VR~vM?s^g=t{3W5UFz6YBe$=3^FzA`K+WrKC zzS5vC8uUkTFP~^bb`Ms!g&r96E`xr=pfCNB&>xGhamZDn6$YK|IPmR$Bu1C_Cwvv_ z?)VO+7t<{dUb++4DtnxMG7Ycm$(^%7bj{b5zCTe49S`XdQ2MnVM|mc&lyX9JM;T*b z@3iAAaB*43jz8wQmAj`s#Upn^Me;Oy-cz2bIgIOeP#UmSC`6R&HR!v*gMZ*ziN8=* zD$%vbgRjzSk*@*+oI921TI52vUWu%Js!ZP1HIDxAJ0C z?>sE$QPv-hqn3EfpnA*WLVw7hFB$Yh2K`QhKGYWaqCr1u(B};Ldkp$`Tj<{~=!*vZ zph3UIpjX;LKVs0281z|#K4s9S+Csn2pf4Eo0|vcf(5Kr%Uohx2?sy*FJ7dsy81(&Z zq2FuJ=M6f2fy9$%{Ywn`Ok3!O4f-L2K5fuf8T12fq2F!L=M4IkLGLo?vu&Zz8}x$) zy<*TGJt?w<#JYoRq2FcDXAL?%L*Uz;BDPQjeXcF^Lk9hTK_4>chYk9nw$MLe&}R(# zph5qrL7#66o$f&Pw7PD;K_4*aw;A-qZK2aMJU;rgLEmD~Z#3u&ZJ{4D=u-y0-=J3v z`jNKKZ#U=_gWhM*UuDo2+d`i;=;H>x$Dm(s(2ur-ew#rbGU%%f`U?&EQd{T;4Emr! z&lvPo2K`uD=(ig50fWBMpg+Z+2REemzM>UJi#hF#LEmD~yA1lHn11__c12t0w;1$( zgTBI`KWNaq+CtxN(EAK}V9>u1qsvO_V^Br2m6X00J+4PrkqImrtuopQV5XDq9z-^6 z#Pc{-k@PHwvtWx=WGu6;A`>!8+dtEy?Yi3f6}GGQu-dD|Dw4KMxb4kXkq@hHbl^uS z>F&WlMQzXR8>1V`FT`_(`BL=$+d=FRE$XV@)iDA}@OtW}na2A7ze-QIAy*}#A_*I4 zjL!cj`UJ~Ndlx6;z`EX(pwR{JHQSG(dY*xk_koA1Yxa(pDd=aV(+}~Gbu1Q*iVH3F zf4Zx+YK{PrNZL+%>s>CyTklBuR44Dby_u}DiEY7@KO%6QUqn% zt9c(NGZCdyEtKk`Xz6&eU2g_YKWdF7d=Du4^?9!OV?^;<`gu@v&B#0tg2Las$w0zd zy^1$gm8*P*Hc=@30z5|}c|yG3WH+dM4O)3lp~pv%Foa2|vp|_%L$*@N3ms3=7WCa$ z{el2vT~CzF+EQ4#NN+nNTf|nbgNNP}N+r0|jiBf(g(+_bMdzzb`4dp+zU5eBe+|k3 z&tBgEg}=v1P^`bHP%KS zD3oH)93TojFQybgnO&PK^#-DNGQR_qE;mb2d2Rz`AhH)>d<2vL@hPtPZcxCIpe%yo z>-pb_;`z^0FvLtp@;K{^@Ea3i>#PRPAxOy93GvE+5b<*eSg~(x2hV&@vRyeEykMHR zSC&B;aP8u{@O~RmR)Q_Y`aMwkJsR?fwZ+{C3?9N|)EJ2SA||qyGmew6h&k zR^V~3jE9wx2f(;p_%d~_vJVnQcHfh)4wq|r_pVO%I=t9x558|2@ZI2Qujiv4y~mYh z?gNFs9UObh4p4OWl6i`tWFnr*WW7c$SP`Mq(d(&{r{@oVGVk?*yFeNAwDC`%^k0-j z|1l^75oIDr zmZ#M%;F$*{_SM~>%z8Dy0hB{t&9{Lv=*fHsC^Jw_te;O24;m8pxO+i4;MMb8P*z7g z#acd3qXXX`r8@ixcvg6&PD4jt?V+C!N>}7#s3O=13VoG0mS-0z`@MR`KpBc!njOZA zxlyv>dFFob=v%PZf*%Kkzq6(i-V4egN^(oXaHLoaLlPnpA-@5hnBu&p2p=2M(TdLf z5IobKgik#awcbEHfs2VjunLq}&w}*5j(N{luK-1#cVL;X1qEF>p^Y0rS%}(B==(rH z-%ZH8ACy@y0vrJ4h=+AMCmnK&IRfwBTQ{pXs00SbR3H6xTRT&$)!EuCkcXM(aA z)lG5P%@E(s4Tb&l!G261ZB{pOn}nm&2nE$^>|u+J18{l zvUL#I3Z;=CptnlKGJhC6y7$Gc_!KDojY4hd*Fd>GiV~QU6lh&QJtfx9x51O~VoN7p z^I3_sLG8+bGVf{rLQqym5)#j5Q0Q5+Si)C=LSZ4sngC_itLKfNEO}V(0j1*k>LF12 zJ>U2WC@s`)H52=wt}MEV{|t&H?T=k?WHvCOAF z6D{y~GN9<5l^YpLxrs`^PpzuvUkIK)Pr~h>9PwH)0t&6};<0HTC^UY>lv_aYz2&`B z%JZm$pgat<$D02XC`(>syC0N($P-7}lkkd=A+Me@KsoBwb3XAzz5yNbp^e5JK##Ol<-RMjC*abfkG*shrb1sS&!#-P!4}8)qvB-!o_?;R zdQeH+u3=DSqIO}d9GOIDoAFBB2%Z&QPkB2iD;@RV%4)CX>p_|E`f?SNg-Bxo(#@dw zI|J_~9#5XTKpFCCz6X?}QA^!w3z2OgQ0s)Wu##B{I7(%SY*!Lu0oJk@hOC`UZa?*_%+-`EEVe?465c@HT2qf#zn zXVX#i4)FANTKyYP0#{1wSpcOgl9}ZBCMXMD+rJ0OToNls`w5g*;6MA=&%v`Ls;4HS zIX|teSf`&03B8&x00sC7pWh71pjY!Xpuot&6OK}hU>}2<33?tpOJ2XIfI_};Ld5en zP!>J(_kp5U2Z%2S{v4EJUOj(Hl&D?AvjB>I9g<7^8z@U&%};nv5b(EXwe9DELMwWX zB%@er=1|u_gylRFq<&Cit-b`Mz#=m}jPLlzy?~Gz{pH}HtJ|?Qt^ws>WG^rVWl)ZJ z65a^Pey?5c1f`Bj;(9&|N`Gfkho1zc$1C-DQ1q)1EYAa=1fJLZ1Qh-@E@?x*mO^7n zjMcFU9v*39R3@4|5hbh_Ci3fhgZ+-8ZGRF<9Y7^6EJiGmczsD4Aa3Y00Y zo>zf#*lTGKlyQ$T1&Y4qiQE2WP%@q^-V4gnlaej{Bq$4>bv_5mj3@IEP!>Cr?fNMw zOHrwiKQ|i8dD=MXxoGAKb<1_{?%C@Rs^`~|@|<`ccZJ1ECCB`I^DtcZAM1R1YFW8R$PFnIL39!vND zD07i5D7Mr9wZ)U?r{Ed#eC)K}08`{G_#Lb#ic4ray~Z`@kmESJ96UXdghU?#CF4Ak zG!{;l+}`%Ihh7BFu}EW7>bF7J63I-I-v?#M)5afzGVf{r&q0Ythg^|%24Ni!>u+jJjeFs`Qcg-Mj7!r9IhVVPpVs6W9)~ZsE5X z2l%!@m<#FiDFMGOYgKnOKU%3*yR}@QUaZ$fs^xk(TCV1R>b~C7gl%8xIJjz)<>k1f z=cd8JurQGw%ZJ0+S{~D^hN5IEm9W0Ak`E@bCGd{mIL#PJ#KUB**{R|DSfON2@^m2u zOF~sbnM$P3ZQpvuW!HpTuh_Y3!?tbVrp+(A`m%8QhFx1W@7Te*hqR5fuj3lFK(kdW z#K|js#fKwh{S+v!z18UxyV&8~N$i-|r{I^e934zCNN`zW;|O9bGdpM zUY3#|9D%**asss=r0u2QEUrWuHg=_QaU?&Lt3+?owtP;H+1$iP(W;)6?2zbUj=^vj z9~)7#4R~oo!txd{5xu5R+Md#6k(IU=4%Je{W2MOu4a{TTq+HV1g&P=oDVluXYU73t z@@p&o;*iiH2E_e46*v4Sl8hBDJh0(j^BOdpF*t&R;pH25gxj|6+=bp0hWJc$ScT)) z5FkS3AmT_qMXqG4=z*oliQ#-T-~%))Hy$F&Oy;{msdx9J+m7ibU0rZDEOd(_$}5}W zL-%&(=nw;Tv78-&uZNQr`jxIzujnKgM=)l9aTL2(5WJSF7BJJrd)v#UTD?*&SGw1r z=aq*M_sXTw!q{XLJ)>+Kj+?_Q@H)6|8k#u@qj)Lg@(kHxy%p0QgragaL@OGjK;V(d zT)jC%Enh8Q?{TzN0o$y(Vz&&a9rd13(Lcr8+j6`D5jowfCh!d?7s43Jt$_;Y6m?M zRxqGxovubqaVJZ=l@xUn7K=MVm@noh@{vx^lZFeWP&$b)mPxJ9qoK0c&>8mA##}9~ zTSW($>*$$~%%ia&KT)pk(-xp^7_^?vIepQ%#nlpBR7XE?nVuqTebN~x%)uVjBtg$R z4TOAQiORWADy*0B1H1lXqzoz6m`Fa$5UvhlD&Wfwt{h)T)%ZmYvMrR- zy{>otS|-tQk`6CQRN{Wp{ac}1eug>RFN6OVtqtqhVS#h8&E4b0LYFZcbBDF@@?Lz_ zc678b6~Z4NMIJvTbYfCm*qtx#)7TjwbMTCgNn@{`EL3;b0vUo!ZXK8Ef--@TRUodk zmBX=Oc^K|Eg1}kBzz|bt9$@-#7;fBkWi*b^WB|TgcugLD3@1RJ-s8q?RD_pvPvWZ2 zK6eanFYhkUJT_a;u1cJ2O{Y#$5uXk*UeTw2!?D_Ewosg`=7Y<2h8xQW5L5LX`CPd= zLWIpaEH@wxlo2rS87OL|OlPRsiNl8TGr5|MnO6~Gqm*DRSF;6*N&JyHOyI6YEZmNx z%~h(Ed9Xc=4u_AByD!lN=pQ-kM1>U=Ccr+Tf2{4qve(JRK7}xWex~k+t+^x}j>B-r)mQA=x_xsvuyga(o30FZ zY~FU|MxG*UzG9P|bhj!%a|&+m&dpnB#f~9P9|qMkZt9pA^W`BNqzm#B=z#7` zr1Xm)$qXCMv!p(J41?Mn?#}OH?^Wd_&gW`@p5~wxhT-1zy(}tKK=DpFv(E)bn1@9!f-W<5rAVYzOptkSin&$Kx}Anx+yj} zl$+0UKlNwqAur%u`0if6Zrw%eFr6BntPN9S$kTG#>5(Q?~y#SR86#=|h~l`*U9LNb1< zk}w8V%f+ycm0@iZ5^-}ed7*_w0P}6b#1caih6J+ZJ}mksc44U4P(u^)^h+F`A~d#u z;$0h7Vly128zaFum6{ueq_v_4m=AqiXC{p{pQ2qQ$Lh9qvpHxPQM7=VOeU{kx)GK~ zNsYPPZW@gp3ECk_no}F^HNee?Kq(K0qmw1-Lr$Br4Uw*yJ_TAutan3O_67`SwaMX{ zQ(lO*XpNTs&IRd{VYpRR&C0cILSL)rHzJM}V0{hczL3cUrO47cAZT%a7RE*S(vZ0A zRg?MZKC};0QOH(^WQ!|sE$2-xRl`JW47(cG9*oN&mbx}3x}^I;s(5;U5gbc)>a8{H zvTMQ~cLP^e)r-jhw(nEO=+n3(2)jFRj}U(JBi{9CU{1Hj)WHoMleTHXVrApR$TqiS zDlQOB$YRjeQI2D^*|lQDpv%Z0xNDp)z;C6Ui3YwK_ZmHoF$Dt;^*O0vpjyUCwwA2H z1s`wkVOOz+5||ZCQVbx?Bfi$l#b6i4R>a79UaE=D()D6yb$1AaAs$?bY##Me+VmD% zhZ{q;4jnDz;_eaqWjS7b2B0j`I+`fxI-oGl9B%6_@ku})`z>lT>NZfnO3zYIHM%pdb;F%p=acH;B)bZ^-8{3?(h;xS zfn}Fn-pC0Z%Xp?6DX~U0EP4*KnMH!{n<*d9Ak2*@EZ-bQ237xC>Ru z$%Tsxu?i6IIQn3!9bZ6@_D8EZ5|b|%!#y@;D|IX>WjP6)8ZWOxOxwpwv>oE&plq#U z6my{my{(4*M3#!LpNaO8PE2DyR)Fg0sM_7H6f~VtSQp^N^44J#eHb?6`7~w=8+OS( zDSSe9%J_h94Q^%pP^S&FKgWfj7py3>ukUhu8GHuj;N@wg^iqDWyTO8GujDG+6GR;} zthwE2)a+((>_A%DYn}+qQ`SUxl56{s0Pc2iIg(rZ8;y(D>xRBDP|$Kh1}sRGo_$i3 z-i`@VG0)e_HYDeDHr8;6O|?QUzuC)Z$)PMY3-x+252ulI6SX}wev>bY6mVjFi?7nR-RYq=yuTjr6BE?Q2ysOe_0Dq56gQ3nl-@fw(T#sBzg-t13W+4qRYvT636(m%K@)C0(O}%vn+#O9{%qTc z3o+5wS9{*>O=@B-4R!IO(NIc42@g3U_Nw%HGtg-Eq|;3vIB*oS z4rQrTu(JVm8g%Cgf2)H+J6{>JD-xJG-YIA@2Iz_t22D&hr7;`{B4BnMghqEef8=et z2q|)#oGn%N(f$c7?3nY`&vCzv2) z)4dlyXLaT*E_al9k|yWn5=|*Wq`G%&hh?piS^e9k7)Wnnme$d5h3yYMlDnJv0Nuge z*5P zKjwmKrcU=xyXnTOZ@S`o@1!ekxZ%c#_sYrMo1!;(r{3TVoHx#U{f$>mKBc_8-@q*D z#-Ph})tv{qR!w;RLf30$u8;b^3Nj=@^32$dQ;?-eyUwAmsh>kW#v{O$zSqs9w~7hSIJX*iEDQ`*R3V4Rzbei z?Rs9G^Z$Cej>uM(e^qqj-BjYLE_%-0PFz;vst`th&%aY5lV?WwHggPZ780fHw4?an zL|5a)Q?9xqas@93d-yXk3v)i#qJKWu#P(Be(tz#L_%My{H*p=m7o6{uX&O$ok+!-9 z0QX8yxLV&SGd0|6ihVHP0N^(41MbS{)A{1^-OL~Fz8Tdl^i9_I6we<4?qJ|I?*rdd z4X0$%4xG^E>WsCMNc^4-}IX% z0itz)?;?u>dcslfO_Q&?5kRdI2v~HcYA?9qr=G!k{?&@yL=gmE4@L61Du$n0S1(|$ zZMDF7`F|S!f7BBnaHrQPxZBR*G7)4xt``XM!as%Yj6v$fA(wM`1h|P@@7o95pfeR* zb675YT&{DueA5%oH~iEyYZcr$kyj&dRa}QlV+#LNy@NG<6aCOW4Y=W4FWCoN{b{P; zv{SjX({}~^ugVI@xD$NcUi|+L|7#o=XU4X87rW?q&O@f#Wm+Akwal4v2Df(Qmn*rn zylYw|JbWb&R!PLDYd4c9rORc;mU}N<)+U`+-x^1|{7wD~nl8Ff&{nss30bc-ST9F! zwLSM4C9alsW8Tp~#~in5A9)k_>N1w+R=&KbaM&jw{Ere>y3b+<^qIF!t81%iJbk*^ z(jMJn+QY_D!0r?4Dly`pQRU*J`QzLT(K!mLFTMOH6a1I?CoG$Cig9$D&(yWctv*LT zoNU^q$BA}P_x4U{-?Xy2jA@_zyT4QEA;!_o0&mu@Fyeh6XCFlTvu->wq z)9x+ReJL+8t9W(u=cbi%HjV^OGD!U{uB8LzTGyVWZ$ju@z4qp!akNiMCgsV~gYfU_ zl^U3TMllXmEi5nLk`&Ilob}X{`g~6&qh;jC;|Dwf{8~~tU;YdiXCd#CeS{&YSNW>i zo7Wz%X%9LFsFpRR^``Y!*m~JIIC=&AEEh$Joa6ldbedy1b$s9Hc!s-OertKlyAe<9 zyI#?Oe6Ze;5AXRElzITbx$NJW4Eoe7SocZ5+LY`~Lo!NvmFg^;?~DO$Vnil~06EY2 zopZb@6?rB1)@cE4OFIaoN5#H#N1x6UvU_(XlYX>F|M(hqE<8n1u|&8dR9%=WZnWGC z0r}ErYif0yjwyclBY0CsYFMR1g2n&>8kBf)`WxF~qIHk1aEt0Esn6w#^rMAl>UZ#X ze%J~O9Bf@M@C?%m53F|HKN&f6{n(A3@!ppAHt!YuPX)fov_38FPx34#!;B5v+DLOE zwPvFH*-PE7OyxaKl_)ho)l5|Woj2H$Oy%9#mwf?irvUnxC_hBlfbp1+nspLz3D5mB zEd9Rdo33wu{$CTO#QM}&wycbt8nTD?KdZ4Ma+aAey}`Qn^g%iMU|OAKtiwBa?8lKK z{jqj;u)Z^z4#k#MhwI;pz7&crs|eM99sOlp`=yspScZMew!e0XIQp>FP#sS2-)iV` z)}Vqksupg|FUVihuQ+D^w8FGrP5Q?xEl8Z}b>>_xCSpv5nHW)P+GDFsYusQnF}6Y| z;$Gf$iSf1kUCtjAtY`Ofsb!|u6)6)A3RR{(f)Z_AO4OVEx*v)@E5`v?yeU^T=c@TYJ=J#%6nI`=pBG zh%zZ<-R4VOGL^N+L8fk*=yG99Y#@;IE(Qi<}^&hZ8<*b4S=(7TsL;u3%^v4Bh!Q zU-&tm_c2&4_rKyky{3Rq^pW0C1&@{e%swAl{A}8OZ}Btm)y2=Y|0L1vW}5D5Ql2|6 z4J7f-RfXD*%2QZ^ zYzikl1F0ZvT{Y0FY?~;X@m(f^fAP=VogpGK?)p892u)h9zbE?llAxnzY1mHqU`5F4 zS`qMUaycu9iEo_Q-=FATI(Mg(oZY`o%w?cvle{x0tu|vzOU${u*IpP_Ino&z_)J7$PC$c!*C~_#;Svpox2*ZpJ-we}=xlN$#svYd0zi>$c%0x;H{w(e~XXs{Eo@UuPPxPO zG2tOsV5;9Rt@Sru4^PikP4b*Nk&t}l5=7;4?iEhjBZ1mxCJuVJk$2(5HD%5iv^eV) zCJ}>#E#5sl5fd>=4Af5NJMKqYxBnAM+lv?C1thf9y<`gZY_-!`1pb-^{|xZnfN$*v zj=vRy@1;t7_A|=f6r2~fY2NYTk!DsJi>5dEn)j5=sP)CSM+W#>r`HguX8j}W`xDGW z2&ewU?NY6)Tj~5A)~46Z7xxRm)f!-c0Eiwq_wl(67G%=myvZp?Xy|q?{t)&D<9TQR~0kqF}rPg}OOf(UGyy2Ld%cq)lw98oZ)^k_|{QEX% z;&!gY;-$v3<4fhmhcyHPQh%+EOU@P6-Z4(`e%yo{YwKx2+pmSVx2Md{$45o=ZNQKt z)p0%R+xo4p?*QZ3#!~C8x&O>CcG>Rh<&GXIwO`S#_ALLWbZp))_HnP+Qn&HcJLwIk zt!Vm!j2Zgy+skq^JxX}3X?m$gf6M7xt#~Qx)yQGa$_be75fbSnre&<@WlkBnm6q)) zAX5!D7LB0Gmp`K`IgCoOol0y0AFEVVbxt^p#2KhQ_}> zR&n^(G7f0jt~wn)e$b;CVTQ6Y*v@ch|55Nv7wi)XWGNPpfuv0!Uv^*+cK-d zlQsogK2iG6`h-+qAHPH@3MIk=-C^rrPPwKeWHEZ*#)pQMPevz8H*x2hU0;_e^k37y zY)^%-u@`L21y!TC4_Qa-F=I(G6Va|v{qE>G(>}Ywin{9FHCr-~!*lTq!=n$dRm~s>KNPR?4&%R4F z@Bz1%{@6^m3s7n*e~R@(>=%O!9c||Z3$NOt{xJKg6~U+6PG3^D1pJJAqx)NE;PSyL z){6@>MYKE5Q=Q;vBXT|rcPWfwW ztbO75Hu`3!WsMPklqQD~=hiy64-!R20LzT{VLbC~M1hz(fuHdNE2hQXJtn z=PT~b#F&%n)->SOtm)q5h-%>=gC@B+2M9*`_(ioX?N)N;g`q@bpp0jnsT2$`6lY}3 z*hB_6NwI<*l5tA?LW<~Sz@s5BQi$;n)y6;@YhqDOt zvQAL*V5GK3zuzG$waw`#{SuL$M%(22`!jGVUEhaaAew|$cO7@iU+1hx zY|HqZ)>-S3{Ubr^WiuIEpm=e=)CnV7@8Z$48y+$3LrFYF&VNyO6;4cEm_9_0Z}i6_ z>gYpd0#O^bJ{B4-ARCC!IC4t;thVSoQv&tZFNul+TOc3T(^dI+v=r9v{cY(_c5ngB z8lR6&a^whDdOZ=xNBAfIMFkC$+)8eoD%O>;!Jl!?@b&}ZXdKEL#8J5b>U^=+_9$=I zo>1zqsP$Dq! z8gceku+8xU5F%|ek)dW6MuSX6(oEdc75!04Ml3mgjU>H*jj_HqV@_G9etl%NgzZCa zYmEML`-s71M*KGr5Kc_@VbvPLC_w5$k-?ZY2C3*f)`?roFN5ng&_dHTZrkNHn+JCK z2&swk<_5)t#e^=Vb-U>6Weg@Hnk3#Dfm)<)Kr7>PShaz`@QcDv}mnGgNEZG*$6M z4ChBxAvQIz=SdChM^)$wM^(wy`7Z_P`QqzqgL6{|R-Nf7RI{#6G- zu>269{jonQmb)Wfd3AxV8~L00ZsY&Sgw%UOv~;#m3nS6Bp+tP(R_;Uf@qt}jqf6zD z*b8|h>5u3_X~RKiaQaVE=KJmY2CA}ajF#iYE+_8GmcLJxH(DyPZ#9nl6b_?h7b@yc zY83#f;!7h+n%cq#c>B$0#oGx4Q%ZxS&aGc(GKjD=G6aAzOdO(tLj^zwj2}5~0+2d} z`U>{4XM-iyyhayw7vsK9ihf4jJ>$n*JT#GlPDs_cfItV!YFcmQbpJw1o3`h?zwyEL zO%&fph$bm1^4?wFMEdjM21uDGaUzKB*A)B&L|GIof*F@%2%1C?hqf|FdQzqZxYi1P zxO%y`{B2?(WF%C*q*>iPhH&b`YG@t+aw$NQ7zy zb^iDjhCjF^M^oN@Qs^9AXeouLCa2Jpc5c*#Ql}_mC)Ly3kzUGts>L;rGD=*gZB{rw zz}1){<)(n{pN06BQW;%pFs0z9^_GyAV`(o6!_wUgp+e>MY~M9dD*>ljln*G*Pt}6* z1$LM&^&-~(~4OD^1&$;2{8&$*N!#H(DMeg1gD#p95Z|9RmuX}WjM$2IQszx7F= zWlCA3QanV}xI&n((tFT#mC&_I1l%|cf3_^TF3@*MS$b6)+LuYcmFH(q`i|7}dG`$5p3^AqrHwoQ#?ov1#-nxI{c${w-dKc^DL0tBwcpy= zU~SU8SKUT5q=*1ou5?BvDAQl$;{AQ-$HGxsKfD2J1!VmU*AG3UQgU5&d^ciFhM19> zm`Ae2oZy#;klrGrxE}Hsx#r#?|13F${*$x6(z!P=fd&N*25K*ky!Cl8N2(#B&S+Lr*p<)oBm;`w_~wR|&y6^f z&aNe1427C_al%q4JH9Bx&oO9@93Vz*2p_Ooy^NMC0A||l3NSHd{+#k;g(owMf+md9 zoVXLy6;4dbISp}(KJlEpPmlm@`e5;%2ho16)m(UYTcdbVu~%kddWG}rbS6``MuLmK zkC8!+#DkA#?{+%B<&HrKiNx}?UrOtyV|S+$p)q}B$?Fk5t|tF|&bS7e?fLboLcP(_ zA{E$`Q~pgU@~i3+tB?j+wz`lfQW)>8QZJeF^3((6+zuLa*YgAgZC`~5Za?}>W|a(@ zqSM73UQEa)Pb7>I<(GlQ8ATz* zm6Ib%<$da2?69)8w#Ry0)m)4AD+OKN0jI(DB4a^4zGdI~|j&FtY7<=uMO#Dh(=y zBsJ>G4Uhbn6CN*{j{t&tHJY4)QAEp|bX|{NcCvMu z){*B^BIdbT$~hl6619Spw7*Od$oQ>C{t7g8=P0uo%Avt_5MTx+%y%V&-^j(e4@}Tn z4q90OV+4-eyal$*5>^d4@&oRTxJ2;4q~ya|`9QcO_rl-3l;ID2`5!66&s6C_2R;V8 zWdDq~s8cv`Eo1meUV3pwxPE$7>GPo6Zs{nXk;Mbz;n5=WJ7J#*ew0i7}1N$#MhmuLqK4)L{T#(mz3Gw}@A4&lhR< z@3`rKo_}&Xdl-a$;8TSCi!PE=iV;$6qWpP4oX0}0ePC-A##6Xm7k;9saBnG`^h~0# z{7c=L*AIvj);RHzl&z=P)AL+H!;cd3i#k+DvTQR~Mf`bxsyov6_ov-TmoKViOgfk$ zWw`z;L7@9n1=v$JLJE0?t-_@*S>%_xUGy#=KgoP-tYcDa=TzgaMx`&F8nl>+yjC@l zhY3G}_R73XvoviV&*${`KBC9-=pN5wdpwWp@jSlA^W{CBC-!)r+T;299?vs-Jb&Bc z`PClJkM?-Jt;cgu`cLff{plXhuN6NFzv1D3q48L&`Fr($Z-{}a%7z>9+u^sLDK3_e zTobJOoV4kb`J)po%upO@D-O5N`C!U2c z7F|?IR+zMuxBi_uA4tx2DxdtZZLpU5V;{R4+^bkJ z5HOytm=eTC#o9|k{AaS)okbZrky2MhPMFii^~$K!1lUqo)DG)debd^Q$%01TuIWUA z;O9eWwvK?^xEt8gpw+lL{h0XYuZKL|t?Bt7Xp{=8{2d>c1^d1uw4`o? zId#nYcgyF^-O>rY`IMfOkfF)qYI$e9#po|!B^L1D%sCoH>g>A_U(gpnl_@jk%_#$p z*@A$rpjh>E(+J?KjUj8R^ACw17L9ZdEiqbb1sG)RtX3u|jXURo0s_AX)PHH*eI*Yv z1Hg-krT*sKUgNGqc;z=1y{1zK9UqlCCkq931M@ZQ122P=|6NlD4$COvN)Y~$+Xd4oT;$8F4e2;h+Q9+? z)%f{+r0qzZ?4M}d-Mq_f+_{$WiN=h&@8ljkJ(SkseNJFJmNoK{9&s-DNLt=h;jdX2 za0Q`$^;tXbnDqn=7OcppZXdv=O zdrFO#D=EZ7@1ZEpJ=_QCyNsVN&@V@p4nr~Nfazk9hqmO%r44vvuZJ{qtgU1u!n4Ak#5ex3mwQ63XW4A1zR zyWBVbG`6`E6}Wk-zvj)5`(?lTH7Py&5@`PrE1Z*U%6W#21+r!4e#YMr>O8-eW?p6< zNgF8j*0MeBLnW#*CoDP7gQfFme;Ba7sQI8}dvvhygEfHBE2)vr_c5~YH_vjzp!IS~ zWhFy`j?uD`Cy^ZMfl}9sZ=SSAQo+w3u4E9hMphZ|!&PIuvU6(>@kwF#TQ_@IW%wIo z(FU{QpE3dKwCG}{wUm-{yN^VXlYy!(;b$!Eu50f|Bjfef#;?sM{mp2I5x*3T&`kXn z{)MgR*03FI3s{p0E+J0%ytWX3Bq|>z9EEcTUJ}!{!2lXlH`HUa9Ig3Z8>ru9{Jexw zVe_ssVrAHRHi9U+YX9Vy?`Obu%8IOcDG7;7z+_A!X^psKsE0 z4{wSFAMKJ1RH6JAy3YSlnu%oYq?aA%V1W++ue33cn!&q<&J}p>QL1(jP zZ3(;o>91KKBpHi*rS(bUZq`3#f~*v8{k!l#ek*E|8q1%8NitfdLWO8^&IT2=Dvitb z74f5FnBvE6*iRYWqo@S~iUMv8*ppq(3-2m9l=@pomZtuOnK?1K3KCl05w)b4vJ-x8 zlmThU81bVZ&YYBt1xwxTSuQ#~j^{kvyr&Jqu}gt2)BdG0~k6`P&p#@xh1k{Pm` z9Haw+;1v+0SLTbAFX5SfC8G?16pJO03R4k1&P^aqRR~cU&*&i#bvV>#pKp`r{dg{* z9>ptAI~Y8GibPh7_b|aLY2mEJH{#pjExsvr704j?G6)RFI>kI<&!51k2z1`tkZbCD zD2<+rE~U`{>$-u}!XFSUV988sElBm}zXK@7gD;=*CA~mNBXvEZ$@c{P>Jnb*y9i|h z*4ESvt~q^6{Q;uY`q{zxkka;?_y9`BvhU!ZVI+oeY#^Kn{@Ju$nMNNmL95MM)&TyQ z@Hu*u@$8t9b!+@q=M;a3Qx>+`TUWHc!pra!Yur9RoXdyszDhLm;oKe{0#;}1E4*)1 z`DGb$`ou)@I{$($(9!KVKffUCsn+sq!wPnv@0+q-#C&1EwAg%dVVH#qWyZ53FPLJD zs3@$%+t+%c<;|w;DZ8Jp*Cq-aPDGz)^<+C!>#WmA2A>z6g>7$xtb%yQpSfTl9ct#a zv97Y&H^a2&VWq@P_n;Bd!Ovm7(0FzNi`6$euO6s6JFYHr8(mysSV|<2MPeo{uCqRH{h;3=k2aJ;cq70mve5TUm+1Lb8cj+iXzt+L= z>#{nS?wGGsEWJ2yPkM|$S}BxM7SO(i{uztDl7+_!&pq^VNozB&pnRM3#4JmkZ{N;j zd}rNOqh^MT*dGOr?Rn`wN+f2r3mg55l|_)brmz&p_=N3hf2OGs4$gps#=JWyRm8?PNv-$!_6Z3yVHpukY!`ih|dMy`buGIuy%&5c5rKi)(YX~m;yJYcUrrgc}!Ze z*Z@42frm+txyz-+d4@^^F6C(YfwBoD;rSIRwl_z6(_A%kntnkubWwhO=6mw-U~C-> zMk`qBx5%P;js>x?2-P6hCuUR)S)9MD&19Nyt8qoHhJDTVO2~qVncNN+pNC!PiojXX zmm`<>Sr`@=d|S=UK8(^1S=`|DFD8f-2c@P_G#hSNP5e-s?1M3vIh^jPQyp*NJ!_Nf zw3g9m`d#s7!CI@9`#1IXe1G#n(3iguiM+uU0hXqykW*SF z_{>9PaU=5l27Sh{;cG5qIJO_sgchI7v=h$&{f(2v_EEsGo4%1HsRx5qdBJVY1aaP3 zXg%wwtVCh_-(!D3ZcSuR=KIui787}?8_9#`@>wy`4n^yciq<3N*V5RRRGIco6-=R^ z_@V4l!o;kFgp;$+pnJzzU!;Z>G-;c22~`nFE*$DM7OlGZCuCbLZJzaXZKP6y&=s;c z|20kdX=2}odTzd6Ny=GbC{0FfLssd)$W&$W-$J74 zsI0zBS|<4&JG`RIsiKsOf=KQ-&`h;nq?&STWO39HE1+K@HT~Sf-YgK1+~U8*E`yO% zo9Hn{mkegpObl6mnT14@?!O;D>pa+K=!D0(Hy@LDw`mdP?HZ_B$ztBj~*9*MmVrWIsA z>IdpYLnr-$byAgUw5mDZGJ6QY`wumYmSZJ6mpnzOapw)(*Do{f_Um^CEhem^xd**m z#?`s2JV)yWBVG>(=AaX-x91cXi@DQz2;3xlnkx7+`Jh0}TV!y~O`LIv5hwm*S4Ig` zDXhUwq$DA8RoX-uv^@RWUuMXAD}ce4&m*L~77gH4No$$WGMAUod61u+V}tvPK+Sjl z`sGGqDYz8Ud$DlzVy&I1(g^4EW8{QM#P zuvzJSe_BbNAT;SUj1bI!gGFR<0Q|9kml=0lf^7?s-C*EpZEvu{1G?DfP}b#7G-Ntb zy}mXdO8EmQFTVylKxAZ);GmA`$u(vATrNg=>4dlTbg2g&%%npyX5pmid$>qCJ~ zr#GbFqvtLcz3%2!a{P*Q?TCCRizdBbPoAc*chY)NU#2~}LUc|$?LWLB3xGDH|0YXy zfc>S0{guFCM>WuFfYL2~dw^9&6N5BvH)|BicBkSh{13n}UK`Jb2ke<5ANJ@Jgl^jv zr>fdd1EaKBhFYq6G|=S?1as;T7?WkhH@bR{R4?8N_GZ&yyIxm78=MXX2&r$WScX2; zsU_UuPjZ8aKgiehyrV7WXk=|LSK1=AOXpTdW$g19D4(P5OzKY*$Z_jwrcCLn4^yfe zt8&GiX%tglIi>c}B+BQUqML?UQBBir@%X?{)PQ=5rG`U@fIkiqrOfp%G03M8=b8(2WXwC+=5!A!Fmj6y+xBUJWGnOLqw=G#`yK)ax&H{Vh1JqN>7lxPx4*hq`;O7@f;$H<^=tUB!2h@HI~!8} z+xC^}_8mz3WDSFp>a$n-4)4~!S~b(Tm;4s%eppgOZ)u+1U%j$d`}`Vy4VPT|q<-DL z>jeJ4ZQtdPnr&ZhJ@niylvahbp}oFiwx>1NZgs?V;<#k}b|7&sd99VRXU9^# z%)~`3Ro}2W6;51sUWxLS>8f!3JHgfpcEPd>FxH_ae*)}*JOgiYfYr&&)6Cw@x4K=C z^#J-;xXxiO#-x=iO80YN=!I!nL$Bglb5dve6D5G2AL~{URj-u(W8c#WSuJa#{p`6i z5klnLKdJ6O#x$Xsn7fr5vwp6`*wIgTcJYO0)Y27QTLhbW9y`77{Zhp1=iG&gFujPq zoG(SqNgde$q10z4?z>|?=$$J)S+!jj8Oe5ZU)>t3)(KXNsK=PH?_yb_^J5;d9CNhh zjVG4uww8KFQVdgmqZRG^Cg<;Z#N9`A^ET8U~s8ykUD9Yw>4aBO}`q^?u~UhQ!G6;d*9g zE>YMUHpoO~%hTWq+7sRj5;eB`k%ti5Ld?X-vIfG&kk!5Wk5JTHrI{&uQYFrvaCE z@o}!?nu1qTas# z`jxkrGQ0D7h!z0N%;33D&s3n?TPFWUm!;|`>3@+#R*wD+P$karSg6o!qN| zYTDzOeO-2q0R8oN0TSj=1*&4PU!|!{7AkS@NE?_)G6&n`>bwQ0I?zHy-?UIzC7qCA z>1{N2$y*IqR_yq=V{>nI1@#IpoVvylQ&+Q&aCo7A>Kn3Ex>rLR+lyB|Jj7~fo9#{9 zQ!QhOy!9;lt>d?wsgP&Cn=Skf$R3a_-kQ`eZIF_FyvgjTv)|^GHFi(0ZZ%^ugEo3 z&%OUeQkI$2DclOz6}Q=p5wb^46y8`DPE55^D~Ud9bxHzf)+=OJNEhwWf{^HmijX(( z$=SYh%R)v+*}n54u^w^W)xL1zM$_52OfY`r9CI8-gmLPjT-kN##5N5a>Wv;t=Xu}` zF#f=;pt=^A|qqfW%BZ-7XAN3!5=z&Raji3faFD|0y;xo)WH*jMt?9`{ev^ z-nqC#Xtg&+(q!ijrDQyHy<>eqx5!@DBKW$hovr=!do+vS&C!BecUyF+#(mQVpjHwEl_J1Lip z3E}b&TWGX&VNA@#y`l_e{k`J#u`3&*Cz*+u_WUvB`Hzr}eU|tmTTvuHntEs#rVM~7 z_IagBi#Vz2oH=gS)N{mASuD7m+_qygYSpEz%u+W0yVq+oR#&^6Tcv}k| z&o~-P0XrsKW$U}qav0C>P4hCAjzU&U!u$u(?0R|dG5cuu4gs%N4#WFHc;N8!7+g<@aovKMiYvU;l+ zSFeZCe_OBR$-{S6Dz_-yimM znnM)*M*IyS2n@YI&zj@Nv9zNsD83Qhx#3XZ|11|rmdyZ8y6U*^gl`$6&PU>s9QV5VI)_E_(=tA>#(pAW znPwWGo^5~8^SZCWqN!2Uie;ZF6d<5Z8hd;igCvC#IWf;W2OM z7wp}HY9Nv$RNrz&3pmBTIzojBgSn4w`Y_h%6Nhy&A4xQFzQ*`yZ{PM6?&uBnh+1pJ zH6Wjc>`Js04n_(xk$CMyH8-L|6g08g36rD|SedS1Ma@q3|9w^}2O8{j#xm6w;&xOE7>m_|?eK;JIAmIkp6xMUS(u{p#cD9Ngrrul)K5E!&{iz;7&NLH$ z*A3g|tUQc{Jtt;S)Mh^lwPeI~+O52D#_+YJT}6V?{>j*U-icrs<*v$ABs)G!k5vM^ z9@~&J3dbyl@d8@}DfVh7rc>gVTM*~`?()=8VC2YL<)=`2p-xqwIuB}*Mv-1$*e|E& zTV9R$vSn%DgVe1{bK`RAKqf8Rh!F?q5qWnqorHH_R#Ptn1jP1SlturKqVr60_|Glk z+|R*e|1!t9)jYLHd)dZ*1T5KhjAF@Ibg3Lm29Vh(ohs#)S8#qr92_8Lu@6Qyhw8W4LW4qGJWe8bd4MxcRq_%6H@nrhn|bG^xU1ZXA<=t zV$SUleoja|jO#AM^T5|AcvfR(0d5h1T>WAXyO)2WXZciA+FvMdbt|v=Vdnd%;)iLi zGvdD!`sHNKC*{WW+#`6HX4EMfw&RJz-O4vvmhmXpsUu4zmNO?EZ1!qe*bA3zH7y*b zMx4R6*~cbY^@wx0TMt8L_v6iVue1`KmM|n`>Ukl3{XwZrYY$WK&UGlzu%GcxA4CQ} zC1e-#ALpf_tFO@2!cn7DMvIuR?ns`zM}DFG0#XuDxS>(PebCmfn-cl&Z>hYg1TVf#1O}>j5q6F zG2(yWyIH^56#E=s1^wH7gYSqOZW4k^kj^K@wnlsrU;OeZ%HfeStBE`R$QyfnHE8Xb zCpjy?EQ1Q-f04|N>H8eB9Y|%lF&h(ExiOm>#QWb!@Z1BEwy{o3u;;1Qa)R-bB5&Hx=RaeAb-K zO-lAdH7#{KQq5G(n2^~bIq@Rx8DFW|v-(JuL7hnX zZsWoH{!&vN0L7Zr71{GMBIS0|Rx(LP3_0-j>d2Xl{!Od5YQ5Sls_A9=C8)!Ea`Dq(4>d+iQQ8HtE!A#K}^?_vw zKH8D9clZBIJmW^^i!Ldt_dDp)(R)qXP{N6eFzF8i(occpDvhKZB)M(CV>Obnwb_|M zR7iP<2CEToE28;T4z>@r$YHcISu5p_?RH0T{p6Eakbrg2+mdq|u6(L_z3qbuDdb3( zdr5yl`U5Cjj`Vk*mh8`FLE&YSx~|gk5Z6-0UI@YWZbW>ym?`HRXvqmQzb%FSIAfaf zIC`&>?YTxhmZj`pO1Ux{G(UHiJx8*PCO}bACziO_uM1$B*P9BfH>DO87%vVQ_dCHyN{fU)SZk0 z-iIndwapp9J2nuLV;@69Moi>C_o@vvWdlgFEy_i}RyNn5GY{FsjinMd+0fa^NNn0Z z^CSjCer<4({%CZNv2k5Hqwtvlw5z(?0M`GKcuH9rQ3pjrca6G|PZbKG`4*7_-}mR4 zA#nP6drX=04eMa+G5wt_T+))zOzpE5B=J}~?aQ5IaOhvP z#Drg_eV1x_;sGV(`lXU|j2@Vtne*SKeigZT$h0oTSrwe-CPP0NO`sb49`ePWa;VPj zZ2Cl3WU7X-K6Q#P`YzayTzuMRLdpW` zeEH%lif_Bgn?2luxW7j1=fY62ZYBHEs*yZL0s5*`-&a2RN7ROU`|dx*8jbWy3Z2a6 zHO?ipDa?zIys-TfSwc+gr4`|j^a%Z$k-of^gP`hHMNTn?OmB>S%1&5Q3`Z3hRASm2 zttAJ~D;e6KpT(PgL8>XpDOJyhd^`>?Xnf8UlniX)`@>aW%F@rzECT$nogWkUo9MNf6M)y0%9) zx3u5#87qGnKga^18+5g&QmqnQcKEQ(Nl>5Iyvd)^LqQaImddkhVfGonHQKYLDJ5ss zEkFGbv|e*IZUTomz-7tcZdyb1�e@Y6Gp)`XYZj$nfG?b}LOf$k%#XKWhYM5e9eT z0Pr@RcO_)7MsPkZ+y7)__AnSkX-d!+qRWYF@3tzie6g;_EIiB9X!@^(XBe7E z|0e%TRTd{hMX606CskaX+P`$6n1pj6kicyom+ZV^b}gDHuXD%(`UA;WB6FQN49fk! z{P8upajqS0v?oktb93EFzqK}C1v@!3hZv$^#S|;L+;6?_od2N`L&!=dgYQubV)zg- zu+n>3C}Cn1I8yHZPhg*HS?OSW)n>#y1)$Z-oONg2nkgOWGJmVzZFNmyb3*HipEa$p zw#w}kzcsd`ZcXcoy7r$nEpL5~^^Ad5N8Xn5$KQKqCF$nzp+tyEShQC|C2}&df5oW2 z%-xUb$E5hPV|$|o4c3_r)_JwOD`UQPRR21rMW=M6%35C|Y2Uhvg($K1GCmxHe!R!N z8qtsE5D2$k=MLH@`tbx!lL`5c`2ZzG>qcJq*~G0B9FhSvf(f zWL6>lGnN&IejKfbkY8|lPU4aLoU_u89gm_P=kt2Xd?r6?8zymHp51`?Z!B|O{g~8y zxqMUfYW=C@Sz7kN`wVj>x=S6!pM1Q_dD0vg!YXi<1l39n*cx`dWlxxPs%RtJ@JWBk z+N&aXNvC#)cVx7q;B~&i&rv4Wpz*;Le^un5AWq*e%gzr%^)3kq>)(m=EBIHw_E%r~ z$=7rF8vU4e6}fkdE-~fZ8zEe4gB_}!AV)Zfjm*lY+j{5XGp`epGiO)HI?kOG2h^)K zieQg2@tN%ePNrG^p_!Q09<5BX6=0;P&r9@~^*h+i$2m`wIEE4-Yh%!I!ZN39`a zKaz=-XK-c2lab{Ll|9af9ncXNcVA0j&c0}=5X>=0&_*8zCtT_leWqRj4_2a}FU9eM zR}#(EdX=wQ;-$?pyf{$MD(lK5AMZ?SW|^6Iv7Ot1MTwoxq2RRd@8ku8_jAm|{aY0n z$IRIJRvj}su0qWYSa<5Lk`*S!$tZ9_N*0Ue?4f<9ngwf*K5N?Zx&%=cADQPT&BUGJ zugv;8B_|#IWw#2(kmHuKOpEJruE)Qm??K_u&?DIiTyoB*h=SgK$m#Q5@d0Bk>LPe{ zR{vHEK;(KE(#|wF*+?3H1YT6hL~(r?=j$GiW6TO+S>(_m)2gFiBz=PgN70AqzohV~ z6lNeR0~DDm5>ZV^{pTKN$)E3$dyREy1_d}gp)17A=knFv=hsoUKMxc@J6dbcVy;C~ z@0X#Xa+dv7BXaAhcV{By{vFHZr}>PQ^P!Qs+(`c&EA$J$yvWE4wWGvnVMQZR%q$Wo=6|a(3y+>QG{&&#HVu-r3^-yO5@i^KtdbvuUvk zcZBJ@Pf365Q+Ko)Ivb($Zg6u32i9g*qt&NdE={jtAS*!Lb)z#Ko5xu0mdL40o8!_G zL)DslXli3`SAKYB+6UFj*|1Jbj8Ofa=m%KFHXYAz`XkDA7ZQ5xCt5RjUZ9R!)&_M1AoSe5^piQnD+3kG# z?EJ_Hb!$Y8S7s^`qxew;j?|D7F-^6S-2w z=kO_8MYMmeg!oI^zwdf-^Ml#(q|kf1LiH8Ru3Lj)D$C)?RIUKM(n%fP=RUy6Oyv{u zZSQvE@b?%Wy-4fPj$xlri@Mk z5_|LKKn}c+>O?khR>c>Y%3ajly*%IY{ihp$&4eH8A1X5~!hSy{#-H6DTC87B{4lBbptNvU_ zQ53H!RvoKY#X8@RH&b~poIok%*Zi{5Y!=bd|M$YzO`iK`50gdg*3DGT98tm&m`~Vo zdyA}uiG=LS26A%w?E_gY_hEEEN-B^>nf2dAW(=8L5&bI5cCu{B;K6q0y|W7xWL*OT zhGX#?ESTgT{}f`*rp$SecvQ0Talu!JphStF|37J1cYQ48hl-oDE8MuA;@QY)5vbVs zp`1NK?dcVn%JccfO7(d}l@XuEcOe3u9U=r}X{kz`tt`fvDrGt{mCwKeTEm=)?7xA? zmP-|Ytj5@H?jEsKrp51naE2kNuY5}{$RZv`OV#~h(o*LCjueYj`2bjxE}1oKlRqj| zB0jMXEnxmnea#!>R7wJroImS1zv9z7{noS7Qn{s#*kyjA6EC|7jG4+m(rV%DJSb%^ z=_f2o+GH+yVfd||zJ1?ItXT968BfyMK4RcvS)m*1_{iJPwqc8uNbW% zs%Co_s|;t>1*}ziDez|Qf>Ym>`Pkfwx?p19fw^_TYZxE6{jv98)>l4}+jhV8vJofP z;hyDhZ_AB+c~v-ZGsowB9j#3Dq89W;^pO`v{A(ZrL$0leexA1lI)~a#De>RP{&b}R z>K28#yv*sXW|)kYIf8@(>FL0k%EyJTzkBC%?~PRP0*&Mp!1-w3g^*- zThOC^FM(HeRG%^}x#=MMWv230s_Cxp#Xx>04E=ML%8a4rsbMWZKh*IDVxNlo!^*X} z{ty{j=nE|Bp)&-}5vI1&?kcACi>TBTrd|W5Xk-)|naY15f~2dUk=H0KUaj61v{(kP z`u7FR%yC1hK!TW_`s!^VpYhtvsb=EHx{rw362ne-oNS+1&D7cSHG9y1QZk+YeU8`) z(tXPaYm$TK?vcSro{M`ZS_a8MGMtrGYO;oOPGkOgis%|Xrbdj(tNHaS8@tPsCqu$dgm?5Ir2t5+HJ z8vQf+w-ugqAkv+xRSV(hb-ze{z&$oH+AK z^5>aQELqEn*A3E4uAAhF__hOD5IFqU&r!H?{=-^6l{ufN9MP~+)vOj7FPX91 zsPc&)!mkba78 zsKt1!(Qx0(@a=BVz{kLV2If`^>VYDaFupm9wUv{pr{MqgJ%8CetO+FWreUiQXIjDK z+#xLx6UWH-TV8|{gI;=138L+fRF`y#$BVl*u&idQ@QTAT#a_m}(A~O8A(ka2t0?rdpOo zaQ|Oqe_1fk`G0s@Bo*R!kf&ir4*i2jY1jepD!(8{p0PaJO3F_<`&@hbgOimcB)^lX z{L^3-&L9n=Rj1B)b$C4zDdcly0=SI&a{A=gKN&2Nkap&d*5g_w?d9r~tB6LfVf@QJ z&O9mb7gax|pHlVB`xR9E;Q6TfeL_DBX_suiGXf&Wnzs{>b*7f;5D)*)dCc?ggO^rx zl|G<_eFq!NNvs}gVnIde&0*{MO*B=0F*jr##IE@!j>5UF4||U;=tE4}T9~UfEZ%@egn_>pPq`=SiP{AITA_f22NxZ^G3A|BKeY z<;Q2u!|LxhG7yX=*d=FxP2+%iTw!g zFGPNI>Oh-X}Cc6>(LSY>c-h4ZES#8IMD6V&m~ z-r1ki&h`yltc=E8W(~*J=1OpfDH z-AY9`+3jcqk5|*yT>e#JpWH?@{G+oUa!Z|6=r2VqNeuhoH%eH-Mmy4{mhsyexS$nk zY53^gN}nc?%3dOKB6y%VcY{lYS3P)r2&L2saB|*wH-9s}U@SkKuXT!CuTIa(E|Aub zz>Fp}t%H!nuydhDV%tIGU<_O7^dWoMFAnjfNMOhi_9;tDyN+8q5+BnwkwWP=r1R6^ z>HDhF+ZT9HmZnD-SbFfdO$+3PEKJivxnX=EyEQNHu)HAPspd)d#L9!fMYnz=WR(u& zx*)_9kM#eAaw7(yO>V>jV22S8H=S}*t$zh?e14oFGiU!-GS5O5zO7m95r{B-t zmY*yBvb|NdmBAzVu`K0YW^g{~k>9OV9NzM)EQg;wO#-Q5C!G$@jx5-Nz4#qDGMpbj ztm8Ivsbc&3?D&B_$Ry{*5d^c^8_X)N-m=7dFSN*B<*Y++P~PtBajyP`Ha37oWS6Kk z6{%W&tWrQ&@`GsM3dGm2KyKvCLb*YF4Q+A*{{t0>uL1EfY{iyVo=*dj3K9&;6$u8j z0_3C{B|r9BDe-XshT zz9cT8D0BMf^%gmD?2(`nKg22uuWNw+*M9L6~^eptSWtF!~4+@GqoLMwgjvjWc6A|83lLKh=aeu7|~oM%?0o z6$9s$ZtsB3bK$Mf86VFLq_fpdUQO}G&g)Hw2)1P^$I~nVgpF=ar*ZYAbV}k@Tq^NX zz@C8p3sn(aEC^WdgslFnm@rys9dQp&oJ@{+OdSZmT>R%e2gRvq-k%iLv-MO_^rkjl z$>>C>WSv|g;+{|q>$N=77#zW#l1$~IQxrwLp@>x=o490M%!^c&aSpi?Q(!kNaE@OF zTQIsvQVo}!N?xdxh1t!(7W%8ECsTP9v}iig_meq(+HN3|5_tmZ7|o5bgI;@9n}4y? zM)b9yr9EJT8obs{5}=t%2kIE1lyOMyT@u;oDVBpXl?F%^g-Mr3*eEQo+pZ3+&GAS7 z9vjjg)jL!9p>C#!QBcxVE+qy~qL^hbXovv{LPP^QR`bw}9c3*N`Zl%g&C#P6!)cCQ zbuuov6R~6}r-GB&#Rb_Elp@%OKf|}wWBg&JaiRI(i)et$E@d`w7E9-jNZR{3b3aGS z&yM2<=s6>^x6vwx8Y!L3YdHf}7ITH&9PIFR>QX)z?f0o|9@a}{;Gy&?8T2T&YTrvj+I0+kP-66NQimz+G^GmcX6lMbbN#8KH8%5;;tz4D|Imm0q5 z+)OtAV>Rq{%D!N63D-xqD4MM6;8Lb?I2_X&vUjP1KIP9Nq(!R*7kPOCJBwy;B zt1-4RA)RgI-LLm(C8GtD_ZpTnk`g@%8p$5Q@$yOk1z?hLl$3+Z^K78~5;01XetsfN z5<%sfB>NYFTcu6HU;6A;+LgMN=H&E`{6BT*cI8nf%D-idB%IA*9t37H*)EL8<5u>7 z`Hw>R?f~jLcBJFqN=*;jlRX27z;MbP;L*@3%TdI?9{Z7+hrNHN(vo{=mgXem7JhFh zt@VWs*jY{ve~oUS2rO0_8GH#R!!&@5@-&WHt$0bXNKWx!Y8-CMEQ%5Th43vGoF~e^ zW=K=afzwZb18M`Wm=e*JW(p8=vahD$d1o#3z~6-&kE-@j7Wn&cjj~-1OZn)mr7%O{ zzifv!lSv`jX`0L5$`7d{YbtKySw>#ib*TRW97+##RwZ=-U$s4kzgK9?PjJa*&z#<% z%kg)#z~$?l>h)37$5}?qvUjU+$WHVtUk?gKYm5 z_-^~Py5)ysJ2R099FByXt#G2hA2YKb>czB7X~^B-xA|3`NJGPxmShe&OGCp)hrh37fSlh&_s0O zztlHDFUeK&nYsNRUfZ)OCOd&5H0Bci|BVExE8Umm8`F(nM~;w5wrom%#%6h&sqDk~ zOni%eq9;A&NL1aPZQa__jo&@_FZ28MXm4mzJ4|opKg)ev@1|X0JH(yX`w5}UN4fr@ z<-KqCv5k57kN+p|q49b6?)WDm)6tD#QS(Hp&sY?{qa8AYzEGmHJx|}6K2w%sqU5j@cZ)-^h&G2n+(1NN{l{AGTJM&#AbPkkOCz`C3H68^XXIOq*+jK zvhXvU82A!V*wq5*Ct(1CIoSf3F{&>_Uo(@-s9$0lexo|Nu(?e{?vmAJ)@g_zB@+$TBv+^`X%sM>ccl>O!HJ zW8I7RmLu1cvy=)nTPyfs>O}b;x2yi*;rNx}vzDG=kz49%a4IG0o{pf@lpU(nn;iR5 zTxyP#x(N9e{3F0_4gC8az~>9_cT@q$Z!{HidVriNAnLdN^8N)0LJW&ubh2&;4D|<0vUd~JH(~5yXD0Qv%WL>m0ulMxU?b^TUPCl?es>U z!J&$2nyTsEMdn(YrpB32$lQvUCOskRb2Us_Nnf$(AS_GD`VId~ZIm@wh$y1K-~SKW z^AOp4EKk3Ddzxqb58E^C2ilYO-zM@1vZ60>)6gLM4YX8DyLVnHr)8ybLQX2j1kNgp zT%MJRfyoVEMU-sH*srE#vlNN0$jWAyH~LgoHkG<9NBu`mHvhP}&=#iu^YL%Pq%|Co zNyJk6i*7OsP0Y7R!13_9{+z!-{@cD${CfEKf~7uJY7q~Sb2{4J;-7%uU(+z%a zg0Io=yNb?-_#*lP`28CG;Uf4Ke+d4HEImc=^L_|^u7-c7=$wele+d3}8vfQI_)~re zezAr>p$L9YDvl!Df$n{xxwD|0_?=3m6IR+CRm2v%lkYANjMNLB1u+T2X-i(R-@BfvQkW(kWsI;_>M z)ryeCF7g^?Y(uYb4O{xRk|uL+kgbtw7h2t#OlAMWWt_{rpAp{%O1mE?Rh1^@W-ISJ zPSu^VI;iV$sS4y~Vswd>q?*+}SJI5V1MZJaSz_zBXP#~>y5K;5#jam;pzgmbN_$bi z@&g%u-9AzI>I^w#|DY0JA|E&JDv!L+ph}$|qka}aHbg8lp4~o|#F){X`WSzdsl4kj zW;0jt(~3D~if#B){cau=iQieVS8u$@}@_BS4OC zI$i=nzqO4j9?VstRuio794uJXD1FL&4e>+|h;Jaol{y_-i{?9L=5oyvPl$m0ZSq(D z{>mGGWGc_TRU+AKEET#8YBK9282b!y@KYHJ&6nQXG47v_{&Klj@RTS#Zowl3 z%PAP^B4GPOgcs}_CSM|F4HK{^Kk8oour`{3?ygAr7; zieUpJY$KHgSAUNkE^L0}^F7lDI3$-3XBqx}?t$cgSK?*`0bSO$vw}nv^M!Rf0*6wEhoo?;ajibv^tiBm+T+Cn}?ex1gxOOG~V1B2Y7u2@_2q zRZ*-WC`z?zwK@U3fPtBT91nx2VAZNcYrWfQTOpuA0+Io|Azl%+fVVTo3o3<(!u&pK z?K6{^==XiT@B7D(=OJ^>*=y~~+H0@9_S$Q&y$uSCBV%$~`mL6`7rAuNT?+3ng+s(t z$I73Nhw5D1fWtAykJ?E=6gdvjGgnuIoEr%48;!|oAw1QyieTFntH^&Ls?;%*ze zjwb@_HF6v0VN=Ibm1j&?p;;|tS%u&kaHbeqhdvWpdO(~-?L`ha~)a53s>-eRL+`hGa&Wx3kG2~xh2g{ z1sTojI5|a3BL{ixba3@4CE?oY_~|LEN@;z#Bz$shWn1I7%2C){JdRpILmuhSo*i;n zrp3f}xGLS^1~>{|r{XQ!O#cG~(cv%^02<5>{&M#PLF-Pp5%?0?A53k%cCaXHq6yTo zG`$SY1T3KolDip;rWdwC-_JUgzB^2Tce7cUP2X?aN3e(+`u?aXMD)jyOC5#l&J zHp5Yca8&VMuN97x#rqnk2s_uXw4GrDOKUZ?Id!a}({{F#VW8Jj^Th%~rO)uVXZ$L$ ztvzgN`lYVlsd%bmYsQ`coz64W{wEP;yz#lw{Vz6e!#_)CUoX?X1_NjVnBBgOZbG2R zH`QTh`+s62i4)3&`kc?$VGLb69Dl(9FbK7PuV;bje@VrDdXFix2;i zA*Z0JqOh?ewSAa|kW&?vKQwL<)mMj!=-7GP`L{GpV)2S7MEry%F~uDp{G%{# zzs3AN$Lt7x?(7AXr($@yG8CUsR~KI*_CC13sgf&pBU0P=1a1p@+N(JJ3;49o7sDU* zEtC4t`sZ9i9Ec2 zRyI=zYqLsy%?TGNh;9IG=2es_y#7P?sQQT>h2G<0dx4wcJ=jJ#^vRoK{z%js0`M_Qp% zoAhf5q4=A26*O)RO=>8T!@3_ai*nJxp{`U1xu5?{x>W%}iNgL$1@lTohrz~8v#9c& zn_dw_+@{;y7Qsj;hJl_JC3h*h#J$&~$p=k~-!JqF&1_c?xCf}d?i7U*YZgUw;8kmV zk$xO$Y9PZ03-l|rU;LD0OjNTMow0v(*9StA&}9hqDHjO*d**z}m>IHWqs+9UD@*}- zT7WsH8JfhM3nTX5Dk4CffCSA%`g6{2aQ9vdQ!TC;!mx@svt)>H_xVAnzqY<;lD*Q2 zModz8AIZe)$>czg=cCoR6|7RB8QO_^h-}QD5fICyW(cy%|Aor*;8ayDf zvwC|Cx~;a{!+Xxm7_+oa5eU{_Wa*-hZ6IFCDCe2p2 z4_Tmg&tvZ(&ly`)zDb<$WW6IX1;pst(N9coarOgQv&_r>azK z=EEsjh&$)6M!sRaY;_auqVek;?P{nSUBuQSjvJ$jb(3>;%6}wJrhI&x+(#C7RblE( zQ2-mNo$2pW^p{CpW}uv&Md^fAa;`1a>ycEq(6%qT1V54KYYwxbJ*cxa`*{AcGKq9v zZ$z&b82DvxU-l{Sykh)E*vn+mMzb7@Yqk2#U7U)WzDcbs6S%1@k zw7L*50&y&t*1NS7$dbh!hz5ruBacTt%6eg;NItDR*ykDS7r@R60bi;UzT1l&l9K_S zY~a1d=FwPMdO0}VTbf?Ixi3#jrGCB{#0*zYc?x%3&8RfH>e2*v9@xn$#5F*h07@Rj zGsI%_KTajq1k{b98m@?bElfv809kJ8^?LuVwy2EI#+Z2aLnY(SU;)5CGo?QWc!qEy zLfsMp5?5z{ZZbgA0g_(y0NpPy2IM+rC6UMMXXVO+acOx_=Uh~3zf(JjVJwb{uP6s! zNMF=C;Xx(1<`VtFoiJB7;bXGTpo4P~cRg-XEwA7-oEG{K(Ey6eUG0U7YvTtK?ZMHl z44opb{|i`&hjU@ z?N?o-V}{!Ux83|Wqi&5`K2N%=deD``lqX`KvN)I0A`-^shyblC28tk zO`aSodIgA&KT{UEN+6_vg!7rH?BMfmEl^JIdDPth!aW^-K?}&1-{+)HlxiSAq{JUt zUcQIm4zh0+FZ^?@&A>jcz1E3$k$Ug@kv54~n$!YDH1i+<4n6gvJ=!jmq!(+hOf_)j zDY{w2(?ipz=b8i{Xm67PdpgZ!9Ro}Lo6#mSO?Q2@3Sr1j>w|(!gj7}rrF5V8$lh2I z*?bt6Qbw1;J;QNBdjpWV_`ifNiHgoS5xLDTGAu9r2f4a$Bt$DRWbMz%CvP3C_Zqtg zOq5AtWD)xc63A-46c*{+9v(^?sxp1U;$dVdEn7@Z(+&Aw#agFXqz#`_B`IFr3-4EOkMs{}Y3V5qo2}@-q!{$l zuQ+*AR$uvM<6>+aCH0jX8}Fon|NTVSbA|bA}t~^Ql3<8gvPBeu*~(+&_THR>4Cs;HprhMMaPm?IlP~lPcWyw`SiU zV0zJBS>7raP<#w~>9sI4w|Y2npu$G+GqmJN^m1{y)4d+JQ zbx-Dy1Gc)&#@#FHfFk?V&??pORc1Y67PVdRxV-(9A(Z)>3pKIU=EBSk;r;>aTih%; zh|8hdpyGyl3K}gOsL|2V>l?*q@guc#Z2gh**XFh(Ye`kfWcxIUyK1V2|3H@g968j3 zFn z(O_oKL~zjs7yROa_TWQIV{E15xkXZ+_&8k%hU^cg96+~>&1>3qffa?hc{sv~J}EVb zU*iirU&xauY`$^p1ywxPxMun>0kH`@{CVBr&9(VIhAP>1*b=fvDKB+!m@X8rUleGs zJ~%~S4TSGL&4mXDO>k%`Z2USD*;6=W2;R&W`NWVh0SnEZ!1G6tskF~p-UsK+;TI5A z;YFDnn@18Q=0iCj+)2m$)See;nx21z6_Z1tkcPJc-iGm}YSHBR-OPaV1^xmnc3>Ag zZ+!&5gg-y=$LLzOOEg~mPQ+8KK6o5-dOft@?-_4Yd=XoW>@6-B1N_m>Ov^Yk#1UTbFmP+d7R4{$3| zE9vp#siYGkuD0!yLbqcX!qEPruHeYa`HIzzV;`tD{oQ-+L?PCM21!726hTw)h7Xb@ zX&;i=-pO~*ln3ofIS+y(qAa5XBDql5v5KXTM$bB25sH5p&klj_8qN&lyDKPLr9-+O z%$lU~9j4i$#zWbiIcAGwzKQHYR`3n?ezLSz+MS3U_P2`nBNc^sTrp}=#-PaMPh!z^ zSB^vdc7_&ElHEx}TIa}Sinf0U#7FN5+BqU#V-^n%P^`J0`R%6G!&V)l3wLN4K0fi-Ih=~Q6xX05FfX=Q8!8(Hh!XBU`t#{_b)-%V}=+N__+ zRnFd1_HRwu=To*0D~f#$Uk$qVE_MLjN$7U~>uyuFy(L>;p7}*5J(^aTsl^cTtac9h z9T{L+F3p_gwB@p7Uw=}G(opA2Mor-`N!(Y=7amKk=+|iQp~!NzmsrtbMf|2+gOe=jUTW?%xp2r zY}S;QS0(e9tQm|e(K4P|0~~VJt*628ABPw_9+L5|Q7E_V1%QN`#wd{T2PTLO)ND~% zOU7=;Xe8C1Y?tu1W3t`QqoZ$TehTJ)Nz`QB+gi&oK;nNHczrkIKVq|X{l^>^%jj}f z!ggnzBYiLy0mF7!yP|}LF_F8{s1r!x)Y%+9kI2j02SNG{H6ynXCbv7uO*>N-jrru% zaS(}{|D#1+pPl&eSk=8;;-Hc*zV~O5Cu3>mi_)bTol#C>k;5-c4ku^l@E|#KJWt|n zA8PgkBvI6ODO)Zg_zBVJh&0`iJnFeuD!2*P%;&?a6JgVAFagaTEq z7t_@9rqeF%Dckh$o%WpjDm$IheIH^@N=mddPWBIAo0nXbACJ<3t<+4)Da=q@tCIz> z{d__o{1t6gl0eH!+Cq{?C_RJw98jrbGk+te!pSV&Q!{4CA-oTd5b2(JC z{b3^bCe@b#*Y*O-2=*M&f=mGs;O|;@hmpDKtFL%VUViV_Kdk2Y34#jUcQBR*v_@3Li{VI=5 zudwBlD2ePT4WBJL9FWYF<*DqY{O5lyjo%h&9R7u5$nEXAjih-tKB+oX_7XFI)^Ss^ z8bUFN9rFQ0BMf!rTq^{o9kSvbW(d>|Bc4a#WUUi@QQIL>!`;vzg#MxvA+l08_aeJ` zgzqeGjqHNft?}x--5t$l<85a4eAs>e!SP=-7K))^Os#f&tJe|zh&A^}jOs4gxbk>9;6E_~o0DENu$6Fe~`T4$*8-KiKiiuat&%)It#VX)#|JPT<{ z+#!OO@O{Du`G;Pb-YO7##Mx3qwUtz*{JVF86d%7C)#!Z)BAOxw`aiMsBvL6B$QH>$ z>67x`EwG}Paq%#U7KLIGcSiJ}vo#Jj&D&qpaA)WkAX$@hMWe5fFVjvXQ^cQ_&tOO@ z(&KG5*F1BCEEa|GV9PXTfuEg7{FZ;qpo$;)3d09IVexf9&TL-R)^& zAk^5yJJ{eg8N4*YY(rEBJ@*)Lk+@; z9E7Ancsv(j6I^aZk2eVOauD7%2ruU%Jg5l64Z`>wgoHu(PcFjcig1QOI4%cau|ddZ z2teI5m4+z7Zw5P~@fw;F`%ECee$Ks&tnpd84cfgG0uS!y7^K}qSN z#Q6sD>MTeq@c}$;MNc)AXzfBEHqPk=;TlEwCQa*y6k#-J1c~&W(77PB<6m_ll$Oh~oasbJIp^+8XlH z5bo6!7WZG73v;-_yafztzspVQscB0|^9~&f{vUH;-aAv;({Avu%1v9YX^#v3vB(

^A~$d+_&V!80`0!P{1BqCxAH z_IFLI7VI-J^&7;<%<6+#3L_4M)aAh3w8@%g3x1z8esO?}1m>G<-t3*QV*mOcfX{)N zOnZt4YWfvf=`Tt8x^#NJrk|0O{=TFO7b^ai4U+${S?OO&y7Zu?w`qExtn@vS{`++L z1Df9PbyxkYU8J9$PM@jiFJ+~dO8PPB^oun8iLCT;N#84-9?*0rEB!P{{~UGLv|rP& z$Vxv;($}Ta^ELg9tn~4c{&+fl3x-_UpOyYQNxvnX-lpk&y3(UdB>g`AX!#FlddF9p z_D8Rhbg6`<&(!pny3%8FCHhHXi351>l`u~Tt$>ap7pJ% z^-l0*Q1>^eMWA}d0W|&!_N8Tgz%9!BlsUmxT?V|wGJ^W&nLNGe3M=y_sfBa=7hlkA z@k8D^UDVT|dr+K-EiUmg7Krl6T~vXVgP6$VIvL(d0xi9|-ueex4(@s@O`kba$g)5S z_Y$S?hHzJK*IPxPg_$^=RuyO|?RpCZS`O%XYcRVsUg_fkdee;eHZjn$Zx`fcftG!` z-mVF>_`BYw1zP%N-kc^L11$r(J~Zox{klGg?@2&|f19G5yYz#sU%U^C^uvK&A0E{Y zebXNzH;zMnXoZBePT>xE%rQN7&UO^=0?`b-elu(0qes$5vM`*v>S@xj;1^i2DNGQ$ zGR)nLrZ1-=(BKd3_`KX`UL+!``7kr{0mnRn==z{hm6>oe5S*72h+8us%FKsFnGZwE zhlesBD$Iw!XFgP!5C6=32$>H{G9MbuhnCETapuG7%!i5Q!-mX<%esHK#(a1^12N5f zcr*PW(gfwqx2>6P+O^umk22r1clFyReB-J#>0OVU(rcvHd9PCy|Sv~ZpBYUwZ!BarcQtcB3CJE>o=4o zEGHMBypRDBn-=mheSV9rzG}xeBdE)Jv)wn>+wMEFLCpkVKRen(#B_p>dk=iv2fC~e zTTyX2cAU{~bL8R7FNC&fdwQL7Lj%Q#KQVVBIipIYn0jYoNhof176}ImZR;i_F)mcs z!YERoj+_;XO%Km@YfrSJ3Dq#?+E0HwT>7E!pCuhph1oh9Kn%+bG#!2`)17# z<}kr3G+z((_&nL;5Zib8g4DGIZsT`r8HM!Kv&1Bdbs1Cf=LJs6Ote~Hdc0L zY^$uCgPVEVranCO*iL@e^A6p{zRPcs)qFkGXqs_eo>Oy)%o0|!nDwaF@rGv>Z_7w1 z_m*GF9zQ*Sm2exbqg|D#c1B;K-BahxZlY2lnoBLIu1-dfz5=$OT^}zbj$C@g<;b)JSkU|@2HLUo1OM> zZ9GJhFDBVO>}P@}!O_P3m9Q4`u}Yx>VAm7(64r-etc$eES()&8xQ|-1vhtzi0s#3o>AL(mNSUMBG|6@(D3A~QY_(1-nh zqJTFP)!KvyM$+)Bl7`=mq~W<#?&!jAd%`sGNQ|lwd~5NT^XlTGhjUVAkVq~$$Fk)!5Cx-fnK5OL9Fm6Ef4l^0?BZrw5L&v9~<7Qe7h1xjRq;zx>r=-Qt zpP?8Klb0*RUx3IGKeA=){ux+0Ow>(I#qrNb{Ih!ww-%4;8v92!k<=_95^g|p7}d{x z4Yy8}IVhhZXGHF(G=kb=A&^QR2qdxg$1<{IS8!~Z)x3vV)jH8Zvh9d#3jQQ9$<-Nk z3FkAa<5Tjr8MTvMb&s4%g=8*lgR~V^^hGe6rnfL@d{u8>9kODmvt3zL^_4xb=lE1N zX%sT(Pf}^_VZ(c*zQuiD3g0Cxg0(mwa^3!gl4ieGGDBXr%|(@V=Tu6&f+a+Qt{^1q zkDSzm)QBY{Ny@(#XLBhB(TVuEaf>H@tmyt!4iR+uYUOb0nN2S%-H)cIE-~bmN%oA; zYaSPe#4!~rhF~%)3S1sz-9415rWpv&;3O*xFMgZ3&e0wF$p0JVquJzY=qo!zvyoNK z)Ju|4e#PH*jOS&4Ph(ac#{MXv8>vQlYi;FQ)~tLof+i)QM7|O7T<_qF%?mV7;Di=q zWvn+=#(HCAY=1LW#xh3E6;>$Yw+s<4BQ{6GXLVhjz1HmrQw_TiUpC>Sp&JPLEmrSG(Ele^*JvwPCTNjku968)>o)ldTy{H;|b= zVdx9~NVD^V0Fe~f-uSz5h1MjHK^X-KIk$9@ZSrjZaYXo#A2TKN;;Wewnv;_pztNgTl{n9pR+>eoL?AmYDBVI8 zXUB9M^6QaWuPzrq8N)gCJ+C!~M8935R6gS8>btkpSCl8w@&=*hp_kmJ`|KTedi%fK z&JSxGAN!p|a1mAI-t~vfk5n8^&p8BEto|_GnXki{*PBk^{8swF*Qd<1W!VS5KJ*TJ z72Z!*t6#Y}@TE&2aoCbgKp0Gpd)2T^gG}#n--Ow!6#vb@Zv#!81ydXNn}6NW+sT#J%N)12 zi@vn<1mq1g&3KCDoF_8%EhU;4Crhj2r|sro>xrDYo=b@mhJNa4bbS$HK0eaC^{sdEan{YNu3Q=Rqo{ytPFi=CHk#1-X0=EaUuf4}kAFf994Pgo zTB(kWUHtNYlz%s*J<(ZHa%PWWv zmU}RmP^k<%Ul8r`|87CaC4Oitol014UMWGc%o##?y3A)3yAMKgc9erZTFn(w54P~1 zRT^CXku+a=NGahSSWeeW;sW6GVo!82R)R*!^3<_j!`+Mi0vz5iNa8if-Bx1d_UC;w zvRLNcjOJAjZ^^9!Xkd0d+SYlL9@tShXkugEK+{cw@_VDH@JY$x+}R|Yr4u<7;+Z}5 zZ1xT}j3WKlF9U6l44#OX|5iAXD3v5^1iHQqJA$pTK+cd~wySIXD*U4MS5DYJuF z-<9!O<^+Fi9x36;entfVwnZd>%+Pp@{a70xjb%{mC+_p#3RSJxJYL8`qba5QJKo7C zVT~{p%=PheN-UYt<1Z@Ndu*klN_DzC&;9E!0YC}sSmbeG@>(!u{%eugh?4`AIPx@} z7)ta|{U&i*5m`3AX+ik^YigI~X5?Ikvcfz^>g;tQq)1MVnBo<&AnBU5X5 zE)2BII3bj8kgF6=c$;}awfjyplj5F$a=dMsgt%~uPX-JBjFXIR^%%6mCUz$^UUrE- z*LSAg*1)>BV;m!%F+s@GnexB!7QPoha%=1`Rk%PeP2-1_2=bH>$xL z+)Yk#QmZQDF7_~{f>gsb2#fZ{7p>(Z&kId@NA?5a{myh2+##aBt@E(R=G|C;3f&uT z>XyIE0ZwK1)Y6sbG|4mkq;B4t`BSH%Nk0!hzlov*!-}yeWaJgzY-A9XaTe&QTKC5r zA>YBIdh{WVq0B(H{8M>-2E4vpIQyq(`hIm>w|aZ?d6&O^S(l=lJ`zP0e)c@np37uy z((OFdX69n0Ywlqv(O-(;E7?gmu`6KQ%o(W6*W^DrD2sh2H1iAD%1_s&&RO_0RGA!G z+a7G{*&dv^s699<)gFxWZVyJew~pbi9w6Fcp}IV3daH`mYSP8Geo80~>xk(k~GO4#p=}oN?fu(ZIl%BO5D6u&|iraR5lfCk~A&(X|!f4?>tgCmd z>=9_rZ@f|cun_G+%JHj~itN;#q+~y3j0A^ZLuAPV%imek5^>#U^e*W>=} zxsEb5x?534TS~xe54O_BZ38FUK?0BjTiSy!@@+MJ-+nmX)`SSI7wPOhrEe%v&|4ZV ze+;==A=lxM>vDQKL#~3x->1nX72_r|W^+s)`*jg$KM2IFkV>Fc5U79M;Ef)EUi_a3 z^n|V~g+2w48R}H;_hZMMS=1@m(=o^RbLHC2VjJwY!zZKa$EQEpu@?qGr~XNTJsiof zvDcy5;O|zhj%X5AHZyz6>`^V_X1rLj11(K78bO!xzlTRC6Z__?5{sD zGm3qa1SAnFg|hOGTJTnueoN>b(k3A$HgPgN*`Y>sT^ z-jrZjwY{z0{*-GPotUJHHihF@o}=QFo+{?L#uN!wbj?06?h9fq;OOL;)DIW)9@d=0 zrKWQA#j`?HTq>thmBwSW|6!8ywWm7^b_@9fOM8OLxps&k-mnrEHTp6Mrawwatkv_V zYH|23<=-Db*dq~JM3VgD@lo?cbsD6!__Oo*$*`CcKT*E2PwW5VFO2TdyFePFpB?21 z=BKOZQ}lv)IB}^iCVHT|=t#IPq4ATX3}Y2|LCXvG4LNana__iUniyNev&;eePJPII>!Ngx z7+NxTa!hTkUsLalkp1cK5R{;&)iF0svRTWNWCvmNQv-)N1`2GR`#XH+>9Ul6^zj&) zIDUZfrB;F(V9(?bf)(3=tgN?p!>AGEDkhO&Ly_UIVZjP()|mh#|085`f(^n;4#wT{ z@HJpG3sZG52s1TBajG)q?>x?Q@FYv%o}FKaez$@Cf^)<><-f&%$9ne_mVM|Yaag~>ifw~vPF#>xq2wT-JAWdm zBE^(9t>{(#d3W?BC^!2`rinc8;BJ^XQaPD3131!IXhj#%H^S-q7zBOAU$=9|C^sc%i;V*f(DW2&)kG1l5SbMBZ-nfwOe-2=o30Uccs^lOg@g%GA zI7lWDDz{nDrzjHkG#fI)qYK9KL3lI)ov*Q?a{)kx*U1^jHuu+(>WrNx_K){2@F0=- zoc&`X>^Yg+#n%X93=Mlu7(vXo`v@1ybvl8{AMx*%9GwH0NRNM%95QDD@%3PG;#5oh zHQeiSS+)HU?VeceTsqGEnxY~vG?86_6}?lW!=#wJVa+@a?qL_4!yM*O+!npb{dQ9g-BEf8@0B`njUXU@m zoQmTxWxhe8HA*lig=ugWyLpa<>WVUQZR?>x=$H=9~)!v>tgA*n-=l9zsu z2AheOB-BMzPd}eJNjI=odtAk6{WY%3$B6Ple(lV5VJg$kNGBrs6NExUsUmJii=^`U zCP#5%%Oue>OlXVk1Oe|+*RUS&7`XZhe@3R4Aw=@!v5V_OJ#pe9U)?n^~_q-jH8Cj1z74i3uz6 zuZ)xm#b;blZI2x;!Yg_;O}1ve$vmjSs}C|l+8#ZZ@7{P9TOk%pmhjPQ_cC!S4n^S0 zhIu~YF}ZUmyFDc|V<|X!?%#gv(U~)``y;S~9qpAV|8$~UGOM#>ID?}w{>6()iWi@H zczzy(C1l^bTC_PLM_9CJBENg{JC5ICejE7h%WsI^KKxekyBEI|{PyM-8jLLBx6E2H zQo<~iRyzgmzt58rd>;_85!zi(d9dvYwjgsD=2ceac4I|XmuXLG6!E~)eQA)WXKdb} z!~g3@aZ_whI&4yTI-W?yc+~}-$i#dqgiN#hp>Ua*7|OW=Nyr_$O&Bk7bAP6)R(Ku? zFQN!1-o#&yz&u0G+7n7c_Ne}$No|=ynBR^`D`ZbCvF7e!B8q(9! zWtp68HRL}^S}klor;I^}9N8cFR^=15a1n*bzhsc2v&Kg}Rs!jf_cAA;C5Vto=zP^A zPmoo9jh~??3PW^gtN53hi~Dp28EJnLQy=;Q6Ph3$n8(#F^o4Lm+9(2W5Ma@4k;GOs zCiEanG`wf403=iB4SV#WE{I1{jRtb?G?cH8;II~glp{p%^N46vCp47CQ?1!k7?YV< zuz35ww8vk04f-f&euPj-r~=@UA)XbSOlo_v7o4!_d2t9qk2q$v0_afTNZ9?c6ilUNbna zncG<7zOUBPrK3uvu=ZZ$ISN}^Y!L*=Vi4iKWGQAjN0l9JjI)(aR`g*8bbahgD|#Of zwN8-zm5WG^GaTE-YymS}!`X4m5 zgN0N%8k3wC=- z`rpR0mT1;?TV5NMR1WPC)7nhTTM9#i-y;HPC?0Q>#X|m?_GpjSe@vzFlGh*x;9IyB zmW6Rs{w;(X(8Y}v{T*Y8n!ol}Dv?$!i#I-{Joj5P#qNwe`v9tZLe2m@;_nK59MH<_ zW_jaYAdp2sc3*K0`-j3GEbz)Rvf})OKri@4?9~f(`O>NvTh!s3WRIQpUFeDO)+lGB zd$o_^g4gKd3}u2iheZk@dxp?8D!}-u5?O?pL>5WrEDiFiQvN@of*5I}S^#&*O|zn( zm&i<{EMF(5itFw5b@sw0FcPs={vN^qz*6}ug;emXg~*3xp~AzZUxo3}_H0kfwTE>(_ZiYc_O1W~x}AJm>`30ADH^i)RIdBa$W7pxPiZ&XqmHraQ7?Hnm9 z-W;5sVdN&jlWSjc?LL|+B*%}bLj+S6$_M(|GzV3# zZEJ!1MFa3$$Ed9ORk0ukL&;JGv!km=S#uU6JIr*EmN&1`%uLa~mNi}r3`N%NM{&RW zDm^{Q^ph;*74Dg52IT=DWO0utls&!2wZVt@!idD1!?4yCXdc_&-3ottbAlC<+sV6l zdVMz8jQuO{6!AL8x`^Q!ZufM4w|U zS&Ogp5xKjR^OwAp6V0^`X~M(mEG&_O%zQG$jn;znLQMi%YilT7f} zvdTSHbRWTR7A^uq?9>Exc}XTMZqxQJ7fcp$m5SB4j`j%{l|9T7v$};?~^x16amoue?t`!`6kn@`_gDp z)`<|%fVf}=Bbq?*BSu##qg-!3@#y;LK4|GzU^i7Yak71<47|zqygT`kRcbqx>gt~P zCYynh4MGWmOYfj|*No>EwY%m5er4%VCTyll5b2C2N=e2<^Uyx?HIM`T2_HNo$Pm~}_10ULJ?3J)kzmn*N#?Of0Yrr#%Ts+Fi z#?BX&&ShD1=zm3`O_I1=TyYj&P2bH^K_pItf9@@6dJ_#}QFAme?tki~cVmnAM15zP z=08ZTBHQ>V|Fi|tn}!-??(I^9L9*{(07S?(!Y;j*E;Ng17RkhUfE28e0hue1iP$23 z}-@LRRLCRqUggBKqM^rSaJPT~6Gwa6H+Kv>X(eqn^$7)Y4aDHARDqg~a3z5d!9@pB=qG`c$xctPwOXvRdm{!+~yWF z*9^86FMPOAcWy3j*qI+{aoH`--Q@?0s2t?tmN+w22Qi{!-KUKdh9- zUw}xF32g;Dg8w&7k*G*g16dJa1j`FlthOSr@=%+g`{kzwz7jGm-W^EPl<0GNO~1U! zGhbt`f`J`a%0R#t_A!5(h+`A~Twg!oZ_mI|KR=W07e3`Dqx96<+n5f^B&kje$jeGl ze(cz0fpLPz~y{VvI4vRA?&x$GfEu(k&cmSY~dU!C{V1H`6UEhHuc{ zQ;`wJos*Y$5hj<3SX;(n%YusIi>zBYmLtTH0#p8HaASg$kJ0s$N2IXAe9RLT$KmpLwf0ox-w!AU?8s!)3kNAluYL4SAFS&`ii_Oz0&s@FM&{t(Bf#uzn zT1t(z)=E&iIdq87kp*m^eNb zu(UQQE6g%;DV-r+2@R3~pQKXN!~Q1RLgW@+V2r+yO-YrZq_4Ks8%&1GpZAeP=J&!P z?v4=cc?0b`GGgo5P*PTgW{$xx^f|Fu1g}Y(eiJcQ8q7bV_X^V_lt1JtuvGrGD@g*?EIN-8n7r+q0A_5r_(djka2}1v0Eq55iAuC<=M*H55&J+!5q|Gs zX|T`1DK&R;>rDf*l!i+`$$348SIQNGBMKT6`}_gT=MM4_QJ`YSQ{`6R`l(v9qq8s4 zL}ZJjJk5*DmdRI`-x#{WYB+f=lAlR(g7FMSDANrg_=jGGh@z%5IYi*id$soStA&5C zRQYsHvj4q$uAo8{=FgEn6-reUU+cs~nQ5x>#~LV_LhB;A;B~@dOpf1)P4V^xsR2$cU5b$-Sh}F9>VvulsIFdwy23FlKg>b_++*x4M|i=F#7Y{9#Y1BU}i=_@zn;p zLZL;R2;d5tSll;@fL={Ap}`Qu;;4Pd{b&lOX5hOiNl zp8NxvJkL_mT=z5 zFjf6@6GQc{vBCoR>mw;P4pjxSVpC~SZR7S`oT!$_*z>>Bj-wm2z|C_ znL;j4qEN{@OeMpZ6ucghaoE@s_)VJyKCSAkG%dd(4e0&`7$djn|5Wm+9Oz37^oR`f z5kPmWXE!HQZ4NZJgQbp{>?awq_I?K8TOUhOXQ7IML@-395#M+5SNLDH0FuKf5&4q5 zjcQ6Sd8>$C59%m5TypY+gAp!^$kAlMD8ni6Kj0-|i^x*`b!DF1N=n)v@aO%{|9`uG zL{I!WeedUP-$5E#%UnV-_DNQ9N8sgV9MiMx59*)Z{!g(~hF|UA=7etdk#szX*J~Gi zH-8)B67%GsCJ2%_Pd8#zZ|qERp6)^UUg!Lwlu4i}7(>H1CwuFiMh>S$drOD`F3wJaB2<5Of8_V0Ec zLXjIQ=-W$6>g>(oL!sW5hqS6U;KlB#0q%u8gd#Y46B(VJNRf{<=PtTEl0x@cM1{p2 zBnsJu{2!SND#;*A%&Nbr+mD=*vb{)sG4tapGu&s**(4fM+`khdvFgb<+Ts)5mkUMk z2`?mP_ffVRxWy%?$JzX#m}Bv4d77`eC&fX>_zNb2t+(g*$qU5m2AKsWgmG8=n&wIm zqWFr-9%mXpq`sp~eQow8s+)0;sn*F^i@cQWPt-5gJ*66|a%3nJ50;9OTcMgE4t%;* z$Ykur=fH&#|E9-`ia4bwYFMyTl;Ed%v=$ROddYt)-wq#1vB|$Go%f|!vDeCmlClP( z?W;UdX-fl@FY0EqHH&LPhyqUsST(^C96!Glj}!3(i;62D(sd03-hE^Q&uqyj_>Jtz z51$^}5gwPkAE`GVdOQd{yzoj@!bo)lu(Xy`4=Thm;GEmw-W}0#)E?eXcm2ec-X$*_ zIp-Oim^lYPFkd`+%sBv-ih2%UBEJHKy;#oyT*GfE@6-4#qucZxKyrZOJ0CjWcOP)AVdLJR7xJ9K;X`inkZs>RZ(7&)hR3wUE}BGyQ7Dr z%E&>F%z8>k4Q(sIS5HUH6Ax%_p50|Ma?5c07m%D$Q`Soc3rn``)L2K&Ryd8CJ!LZ3 zj|_e?YChbvhXaPFN}2LO_+qw}xB;_|H%^zM2{rOp(=!ZL58$_$=~DXHp}XaHym`Sc&pIU5a{3O!agF7_yMgGw&?o^o42cyy+8Ah0+n#U9&YW8X$)w{r*a0=bM z7vzIm&N3A@oPIYRdlj443wf zpN8A;z#i@FBew^S(5_W0WP*nQ)LuaE~Y$MXL; z{{Nz&J^0JK!JOIL(jFXw+IvuYu$-y76HnyB-M!z?CCb@@`qjpR2Z@jQVfdKye0Y0s zSg-cra9?|H#LV{KuL~yIV^3`l2KJ&G&K|VCKn@UZ^t@i}Rr$X5svbSss|o;WC~U9l zxmT!iI%p@~XfGo2H@oo;m{?71tsjfO*<$@eR9uKq_Cael>_3qzdC={yxM{Y_y= z&Jv#LsHDtVqHa!Ek3?@zHkjP@GPw=R%Iy;_S~s~JL~hWRuF{)^4&I=c`y0&r?$dgF z#@=0;HJ<Z@asEBtJWj%oOoLS7#$>>M_=trN9AKl8hdziJqPdV zOPa_2l71uUNd6zieEB^fM^^z-U&f!{G5i^S90xO+gG1<){3&}a+n2smKa9xt1bz;d z+H0)H-V_|!g6~5S_H>b z<9)k~_qJUKhovll&3UC|JjwmK>mKyZN`rGDOJKQk>mNS?BlK*Ju7=gC?Z8;zpA%gY2Xlh7c89eH$7lx<$cM-X)KKqcURQc zkmQM9&~4_=6ddM5jq-HWoyeT$Z+%N5uWq|tXl&S|~K&4NudYJh3fSx+)RI8vvC zm1PKoJ&cB7^eff7j8`m_d05UPF*lTA>@Kp`)H`)~EXV75b`nAY|NkwWb%S4x7nau! z-o{w~v8&FSfo$g)ZPi{EX)7Az99&Y_HpV`9pKHHLUM#kq_}Efalahy%J9mB{}R z`%YFbt88`So$ySI71eTCRV8nfzy7;WbJH9Xiz*jPF?mhxmX}*YHbRbbhC;fN z$OJlEYhcB$lvW=PlhW>{#dY=-6=~Hz`5ep=aEk0PMZ`tU`;pfFn7oT`I*TP;c$?f} z_h>72tGTd?S4}GtJIQwifa(dKe22cn2(+FboivjD8A9pxT<(1UYv}W?^9AEK)88q7 z^Iur*#Qj&y5{hjk=CFIziP)fj5^%Uo;MA;SMOQM^mq9!R4nc>9#v!4(i}?wQ;qJTl zRIGzsQS1zT<9{7WPwi8zd_K7QL$sT{>0_@(>7LWGpZzmq!!YCx#9 zzr=xnBaI0(36`(HJQ$A%Sp*1XBY=4@GQ9-#Lj2;1&fo-P52BVn!AWuxKeC@7?0~(f zmDgocB!9*^6%~yZoA+Sa(C(Ychphc=GD-egyJ7%ck?za20#fupjXQQ_kdx5 zZyy7WN-(yzu!|5d%bk9L;hRlXR5$h;s7FNPPj>-^Dr+WjAyE%>BB%HzzNh@R?J@FF z43CD?PVuvn!gbw^HxRh^QC^_%AMew^TnXO-$&P;s-)!&6-7UT>@#43yCM0tCIgF&^ zdr*aZ^$NON88exBJ2`x*J~qhv3AE&uLPU z^rES>QU#=Y!hiQiOA$SXXpS;HvyD=ji^|J^gz)d&+~xE!W?5TZ!(wx4Kij$I}Ggcxv&!q z?De^@w;9;{Tv-3l0?k{%SAc) z=S#U?QQkEu_vWI^?W+v)dbd(0Dar(ca(OPwuT3e5ZYX7n@=s6*nYrl^`5CeOamn5H zf}e?CX8R(fO8VB!)cX3$o#9@!PEBdY$MeOMl=8oNx6v@}k?Dn781TVu$t(HWo37x+ zi-q3E-FF`%btfut@kv*3Y79{adk`&7cIbV_^2z;b8}h}!?JjWwjxEx3O!c3q{D)9L z`C5_mN25ie1u+p3_C*#}JGeJA`hybK_v`=4`Ld*>r|oC7B|1Z z;a_Sc#VC?*(yi$3KAs>)bj&@;6sjY0Ypn%NOgXLU5Ho9-!(c@_72#Isb|*3pIroed8_tG zoxPJjL0w*>7}zL1RV5}s_wv8megP(AY8*lKq6i$1rX0Y1DG*8R)!0JLOudm#%bGKT zn#=4vr;!J}qHiG$&THFJ*!%VBc;IQfc!Q|okJjfgYWWzD*Qd`dvY4OCP|N(qFwGRIEdNBEq`(3|VDJ=tQD+6$CZ9svr*6%BhNchjlWyzU6Q!-F zm?{5<3#F~cNlwXSAn=vb4oWm=RcCPJCyg6dT+~p5f4|~?!N$%CdNEj8S>OJ+$pE9TE{-0ycN6CooCqQgR+8r{k;ql*J!Yz&<9IPv++mcdjOWgtG>(i~E^Ax1q;P>d3I9wC^ zNiA+L_{ICu@Ra|Dd7c)>eGE5!L-P3~Blx#FlKMeb>RpmL!lb^fsVlNlH%RJXCbdOV zAIM5=mehQcI$g_+WTpNnsbc%5+`}~W(yY`cBvo8sNDXM}sI1hZ@JmfTVp5OL)WKP) zZwan#Qhl1*CoA<3!M(zyex`N)GTudv6C}0Xq^{M}*RoPaN$M|6>aKZ0t7o!O&;O3p zeN1Xxaqq}V{k7nJhh|EPuGZAXtkkn4ReY*Q?WsARo0WQ*q%JY3voy6bEA?qfz1yU& zi%YEz%1WIesW*}e_y74C<^C&e<^G|lO1a#BKG*CSrau$!cBIpDdE|VL8&zzE#s-k#w<=Vm@&@KO+4jD8*cE)c&5PQX46X z%oYKhTd8)zc#8Uv<7Le#3BQ%u!WlZ*L6z;#S%A!b+5f@cf%xU6A$#Gw)S}vW0oFPk zFtdZ5{BppmN2o2X0hiMl- z=P@Uy8pcTuH(-zoadO6kr|DxvI1ptE8p-~qr>Bn^Zae@*m2&Uhituvk`*T8QvlKGv zS^Y6Z%C5fDmiyl7;?*Y;__1&#H&08=i3C?zCZ#?HmdTF-tqIy8i90CFET6QHleLhT zw8D8o^0%iQr?F#-XmpNcb3P}x1pxACRPj)OVsXbDCx3(Mbz`6Ff;o1&YxmUUSoizO zp>1@zY^v7gzex24DNzot2;^jEwwQvP@qJSLiKh8*X@%t8RK51zi= zV|w?fEesl_N6s5l3+hL#p(-su=F%ioOpmX=_#arbKW%HNyY7 z9c0Yrm$m}ASx$=Vq;`p5RVk^gur}+VzLbA83@5#`n#CmXEGH5#BRElD0yg~U`$|@< zvgwAubIL#81C{_Pq4@M7v+x(Mm@+V^Q&zN$3k+;bHpi&HR+eZP<&0V416Jf@Ot3gmUSO%5yVb;(T(Z-Xwrmr_%tDY7pc28p zQaN^=gy9mwe)2~2rheKL0O2X(e;SeQ`D4(|X=H`|Udw%$eFHPUPk}HM-kx3xMQ#Uj z**<(hV@df>qAOtQTlq-ZdYx;jv&Y*q>fQ5+Vxqf91IX10Zim`2hpw%S*UQQ9DWJNq z9VGd+xqrcvLP_!>hlRC_Hg^?iLIVk;8!v3CbrvL|lEi|4lnB2+laA}wdDuh<#pD(q zEIqcx{ZT%1xUM(+lYO+C{U+A9DgT?FNw)3Dq*Nu+*=s3AYDhL><7B>DquDS1G*r3v zyN4Sek%rUL(knxNQ4i;)oD+t0o}MtIN1(|GvtiG4NBje>qv}+@zJE$?T#!e$;OI^x zlnzn0+|FOBtt~i>n%BoZwxTsuEjh%DouR*%VIY#K_=d0&dlF+uyRge6cH0NCs|2IG z^C_eryIuAcN>P=#r@-BQdH2D0&n;%~C1(JVk@t+#wE}9&`p}fMlX;|DSy9SLPNjy1 zxlNFqSztR|*mqs0HC_5s>>9!T4NXJ7Xrn$cpz{FLY0n)b5X6H_*Cb4BVX?U8B`hWs zbN9Rt)Qcjh()O*a>Tu~aDO9QRvP?FwT&vj}_0uZ-OR|#fF%S}62=Cg8Ad|KkFzREX zh0hd>QDAs&m}%M|>OxnaTp&PlnK#*9BiZH%z`bde!S?+NG@XESMmQ2QBLH_8HRHse z;J(+K!JR6&QYXbt;uWTnSFdK$Rd?5ZxWwNrZ|%CDQ{FXLt{0!|=ia-+|8L&sd;iV~ zMZRFNe~Im;2gYKd?JJ^MM+b60JVhhlx&P=dO(|{?fDRRy#W(RRv?_JqlMitmy_jP0 zEG9mgkkI{?;$Z#d;`5UhIKzak&v;@wq+ z?Zm%OUXh`Ms1n>R`V+oXa~QgxRKV#8DG2yEIJPNlX-^Tysb71fBfoJ6s^YCu4>CCa z!sI19YCO+P9X;$-@w12+HT-Q_u)gt|j+I&YJH7!QsX*-c9RcU6ut)XeU3jA-DoqHS zJ=S>WR&kxyVN%PM6CV7}@pm7~Q`$Tos$3O5AheT+bcYlRL_}|O9Ur)Wc&H&91DPT| zn2F$bE|JGuc(fDVFUQK)@h(t9?A0m%mjd^zOL+M<)It;Z$9O9LEL8qZ$lenw|0*=F zJyiK&n2y^P+KC1-)H$3IZQla<$tpNAzFS@%U%FxPn-FICue^$Ptm&ff*mQi@YeM#` zknp&zBJJ;&Iyr|N04ZeRjLXFfEJ$ya&oTwKS<$~jB4)$QLWK&RnH}CmRKIJE{|zC@ zH3EQrh%Hh@c$0gZHDlj$N)f=JBX~&o?m+(bF3f99_~JYX@oCZRJi;hX43sxQ)H=SW z%_BixkCJTS#VgPYQ~uxZ!u@kin4u*TCdQQiNWQrtzvLh)ov)s9s1mH^+e&TJ5~Um} z+!fhX5GJa9ct73IP!7!Sw|jmcv^1@fa%P$zeb+6-WLeQ8+%qAbKG=?X;Lo@#KU|do zKL0}P|3e1L(j`9haQPwb;eSGMPPR2nu=8|mwJ)=A+$5Irj-}puy}UI&lFWc2QYN`} z^`E?(6!TZ>R}o_9j}s}vE<6sz#Eik|W6)(r53}_enK%E zMBSSdC^V563xs2G>q&4s`7^(pe3Wpj-Ut~NnsoeapOAr+`*xk3AQZ;D@1!#w-*mpS zNk!02f=z@fU%Iwm9Roke|2pCeSH5J;dRmCcdBI3)|H{uB5n3DFZIE8s4fO_2q|#Sj zMJV}C3UE!RD>!~IdDh}o7f1w2q<%w+(LZNkt9JJ}%-GMmGNt9#m^5>k5ir20GAECE1W8zUDfN_pnVs*Of(l zkC2YzP$x>Ih}g)Ba?2V+J}^FM?@L?1Or9cx*Z<^n<O=VyifrEI>i#l*B6L4P{C)Wu{9?lQhEP~wV4YHi$xFP8kQt0P z@9Z_>cK-I6aa6T)kj7w;1BKPjS%q>Je5^uW&M4w8_{M|a>AnOQk~L`TFcO?I3R!^0 z`pM&2Md}USj{zfKj0P)m5>%>ljtna|UbVhuC9UUZ%)vA9j47BM!

=YDo*~42Mk7eYG(m=YJD#-2#+VgsC zx$#BE+nVAb!Ipx2X-6F06O?P;*NdPCXxn(XwRoR8`|DbJL+#9ULb&LLS}U|6GsPdOu~Zxg;D^5~Pa*c&{SZ&=C*$a7!co1!8T&r9~w zw0Fc#poyvVOm8CC)AQws1)6sYh*L+7fGH{HA<6d+9vg2aPvI$dx|b)`f^e9%l?w3i zvznONkjb+uZv@jsYxvR;?B}&MR)H>baetku5=yC5DSW*qNOh7|(uo=V7{RKyHJlj1 zvadCKXl9;RrSjU;>bZ|g zo2)1X`IP;wj`vzzIWd1y1?(5ouCEp( zjvQ5L&buh9T63acD7#t_I4VzBHhjX=DrMF1U}e+B>NJb~qA%4^7A-X_8XoMirz(N; zPU-oOr<#m}AFQY&c`8qQh?F_`Lv2kM9Z{yD()0E5k0xO9JbsSx=<##-NyE#DG@m>p z^Mn>I)+yOzY00WcTSN{BfcSJzSD=RK8gN>pGV`~ zFiW^MQVYiVMpiNBa{z5qHAvxIbK{Oh1rK}kvC4lr2LPN ztb<=h(kf+{j(bh{%CC;^1z_!$DBAMi()t3~EhR1G-xQWc`{qifu)qMPr1Fi%J{@N` z`&7Oc9*mmFG$-fn2uI4*#ELSctJsYEBz}KM$ZjZcpFki1d4WRq1hRurn{uaS8_T_; z_}cM)W;}^j5S;}ft}R6uZ`|AQ6$2m|#C?415);r1f0GYP60$jubt!M~ZsU8bhu8B= z4a56{obyWDW26GHO$-Sx<%t)+A&Cj!qx{IfgzsVRDdk^t9ksjL(97}N&UXl~zZRSD z-OQ_Wj~Rok=ZbBI6Pl(m&Jeb?yyMLBoWdojmjU{(X9|TxO*^v$FoT;ohkE2EXG~p-Ps1Z}15vPZ;^?e2FLDlO_)4Zh%m{ zuU!|fTT@o;RQ0W`BnnsC)S`kA>h-#7`$#O3y2>?;ACsk)d$-7Ie7>h1 z9CG~InTS~GO`drQ)fpiAlgJUciH})t^F#LQoHx?bpYMexokrVMN@$T#{DL0T?X;dy zZY8mQ#q=18-?XZ%qc`HXEL8bJcyU@C6NTCBN8zyJR#uH!*|T0|zOQq9muhubA+F<~ zO$Ajds)GY%qNbJZBaCYb`l5DH6}ODNUN^X{Hoq00|AwCYsp^L&60gqdAAVWxJ&gCe z9U`qS^Ymk(Rb3@cZY!@Xk{P1%^=l8#&^$@_g~p7|Y;oWQ>O*>~SAN*+JY%seym%rp1- zv#ikml6+9tH$G1Nr_vTW965j(qH;z0DOKVfBK_d{S$T5uV95DHw$xbVsZe^L?|-?K#!IYg zyy}jrsZ0|_fiE6fDaC2V1tRTWg~#c6lKi9TGPBF>|1FFlb#ji9T}zzVMLj4@GV<~Z zOHgLnmeJf%bKbvBym;trjuW|*E8m$XK|biC_O=5^2RJcIRwe?OrvjUFWMPQHZGlZ|tC+;md+3PnV%Q9iZ~`b=1A@XMbhO0bQP2 zT(4zM{M|pIFsSs=XEl(XId?Q+nv|V};S2KdWz3#F_Unc_n#x*TKi0)hwI@IQm1DX; ze1)&+VtHX1D@b!wr#9X2hBVzYT{KlmO1f_TP1F1rn_#(az0>=!Y~^frxn`^<-0=HD zPzTDFn%JY1(Q4I^lTO7Eb1cW<`@Eg!Rnt>ja{2GJlW%MEP)}OROJBc?qhop6{G5=R zmLRRq4WU-^r-ktCW&X5~{;CiP)D16D+*nD``cm)pyxi!4wfNmvv@vwLcCY` znjD%wB<(LD`wC@$813qLHFOM(UJl0u@yJQ-19Dj+gav;OF=6|yT3%3+uZG~+*k_KM zP1bK5x`v{>qxhRQq3@&;o<%rMpMXIpyauIL9RA%ZGuEAHz+2AQRmcO9oyX`HnBR5- zh4pWTXg2k`JF&8LCoJCRh3e_P>|JL@$#^M@hh7H9(kC zoDIw4pK4X@>;49mgM~N0k~u@QzrA(0m9^1b&AQ{CYB^5a{7Ux!wz^(9{;A{9`qkYw zXBMg~n9nlnC-Gm-{AI_3{SRQLmhLAQ1H#cW^U$d%Bs8aZnk0||aQSG$8+%|LeuL!V zvOwra#c8Mygl8~*8<|Ju-!lFQ<5w9!!+0;_2N>VZ_*%vr7+=ZwGRCVIFJOEc;~9+K zj&b~qf5P}x#?LU`%lHAtw==$$@dn0MGQN!QD#i;KpT>9wW3*%2P{xsu<7(c@JF~<8C zzsUGi#yY;KZ9tqnW{~PG3KJfIrd~O=lvh`dBcXj--!~;Ap%zAvOn7@o2nH zL{h0lN`xal**=ktZ;U54$3;tXT~|k4put<$wHjevm5B~S(wX2u@*3l+On)j83^zAi zWAp|?(O5JyXv89$A~EBt-fTRSi6-JkC>V=fV_XD3>0n>v5-c&QU)6u{PX~Ne#nSMi zis}_%h*wd)a?3Raoo7w=tTHOnut{HIh&+owVLfN#o_CIn?SALTO~9K0@kk_WWD-U+ z9zq(^5hNsuG-d`xCXp}(g7HBkl!*66`?9GZB~s8ECw*;v?!Co)DVl1W9O zWg`d;11T{OS~`@9CNnYv)0tFakRvcEpb)cKN8>0O@nFnINBe+c$aZ6MDw>HP3!^cs z`WND(%+_p)WF*cZTO`SrO~uo2(D~dT6KV7Z}n=vx|5uFsML@^@K@kl6xu;8~hm?E?}Vo;G)G1nr) z;-N?^CUeK=O@Jki+^p)2Mf>^@sE)ipn2yiOK#K#(ScC$kC`nF|#1^$mfyfD$eIq;K z5FUThq5eoX3q=|z{N&w?h(tibL;dzpksywX73Pl&BsRgf>8&DZ^rjL6(vu~A3{@Nv zhJslXO;wPzj^RP6S%%oldE65WZKU!H#i4A(46cwume-!aOeD>jhq$AtwwYASl;Kj8 zKIKc5k%fkAC@7bmWe^ssG;*aN4q1@UJVbI0MlhC1M=}}GGx#F$a54dAqhgCd@r?ur zP>ixhBq>W1qf{g-^96lXFdL&>Lvh}c5mZMh?{e)`RW~+OWEbiG6{@CEO+uBSdO`x^ zdOV7g%BXZ=Ai_;cKFBI&X~_#IPjx20nSNwBC%B_a zD&JUau!YH7-`?tL@lu)=Ea+;xysdq0+kyo`jNpi>fqlUD;lEx7^cdn0APMLO_y9G4 zYJdSK2MEC7=iWIo2`EQC2*6?3O#&tWOCzyBIE9WlW%n139NpdFF`!yeyZ_!)Bog3eP)BWdN2{I)6=GnyQxP<++%OgL zA3`&g3iP81cDUvnI6Ml?Y{>)g7T~5k*M}KDB1lIpKbnu-L$P3VAm7#0FU9BRN^<=7 zP30a=1Z3}*!*AMg{IUTi9t;hm@Il(3PCQQ?(p`;}3Nmnb*?20_dlY?>yaT~4foM7r zz&LUvjA;x4&Gc$_ha1Vq;gdTJ5d%C#Bq#Z^xvS14KtluV%IQl7QH&8?0Rh9&bO-~E zR3uD}=>YmI^u(e+lS!^xyjX?4NKO(|n6$n$NBm{M{FIvauDxF2$((tpmLQGMuI#5V zRHhD>$EX-=U@Tb?UW}fk^rNCmZbiU}QeT(LaI|q|ULT)`rkkmks0-!V^vMdlITl+_ofgqN!Qh_KnX1Y!~`EyM+|LJr9 ztv$Dq0aJm4M-9v7pFA%ORAUU0iNw=b6R>+!i4(dG{MbVWnKA4sB6 zcg8_JWPfG#j_6`hf&)E+0a=0_{fVkPIZ-M(bv!~Sv)PKV*-`HtDM|%5%Mb$@bi}f8 zb~xu5Z0S>@Aoi6bmg&#Nk0OTklc^Zlhix7$ZF1_}KmrrNL_8WYFhU4zlr!6S;$l^o z$%9%&FsH)0jWL^-V0thP&vLCnJEHo*T?La&U|FL#oHhm$;b?D^)-+JDY4nD4gTQIuyYuSuYIHdIU-tFIoh2HpzmGbr@PY#xuY^b0osZkmWPm2@r2RkuS+k)QlG&woduN8znifizTA8B8-)Qf+ z(BZK+n!-AfmOL1vK4s9rNGgf}pTJPda+IY|a&;@Lk6Re&076~1m9ZE|Z;>Psh<*L=~pTT8>5 zaSB}6zgjFtBc;=;LNuE(D=;)Ap)5*HL@Uj5k`$*Wo$VQb#&prKnAlye2jsh&`c~@! z1sJf-*pUsOLQdweB$e)Z+3ElLd0i3q>foPCi^2?QLs0>TuiKO0Me4f`S(^hd6Z_K7-(liEnZA%vJ*C0QE`rXUem zuu0UHN+dF3bwmY@A;N|vQW(~;8EMLv$Ura{PbDHrB(>d^sJ=*lB-8I{5|VsYLJJofas>5p+`Fc~EO=|DMR=G+OOwMEIyU z@86AG1e6UqU(?%cRKDR8-BNEhy?>7^F1k#ESC$d1mS8)COSo_U9_*_1)8CJvL}56Q zN@O<$d$50nqL$56?cYn$g!k{kXqUF6_U}O{kL}+>S#4*xN;-Hq>>n`_p-?snp>2g; zcFbheuzybv)F8{AnMw@2Xhf!dC=b|YC3WxLjbTKv2TdsiP)RbyLNvTZ^vj{oX0baZ zH~r>|R>+sY7{HNa8E`v9;wl(N!Qcu3nGB3J$cE~KN*!6Iq5cpyaUdHta@0RYL~WK- zf|`NM5fj@F-Z1gP#FGbak>O8#{@~V$eG`vQJToz7Ogw>q&rf`1Vr=om69@0m24b9e zXyQqjpFB7;@f=*9HW0=b3}X||!t%z0Lozh*-8=F8!5d(4)5HtL#8=_|0=S+$c-z6d zC!RAZC!U*l(l~evLK-`GBOKusA<1x_kU31^QE(9BX`)C513}&h!%gxptPnVPtds(N z6%sr@@f1RSejzvs8xxO1#;=(^Vf!RfwU1&acf>UDMYumn!XrJ9f#kxUv5BX_2s<$` zf;cG7p@TQ5ggkfflLv3)WQvLVrF2h1Z!(@ID3ue>9{ePU@D!qg5)s}$WkLFet`6P` zhkat=VQG94DtsQkl~DU8o)pf^K#oX>zBVxidAA`f(g(@RIY3$TRRr;bQXxeFy-GDx zHaZl8Oy4*0We)H8iDz|(0a=iRl(K_&8ZwHHOW}~a#0-&SVPWAZHBwU~`Bz9&h?7!F z@lr9kfjCssp=VW0AU|AgMkWr)tfF(Vsyyw3j8vv5U5HHT$|{ap)ed~_?P`7VZx~;~ z*vEK?@nej~8Go1YFB$)i@mq{5?@-~^Fus=Yt&Hztyp8cb#)lZ6d#CchgmF9L9>!V5 zH!&Vze1P#AjQ@r4e=t7jE){My<8H?HG2Y8~KjR-U{uSf57_az*3dhIzUdG!Pk1>9Y zvG^qGgYj<0uP{Eu_`G4ocQNC2jK>&HFs{5?@x^1JHziUzt43B98=N1;rxgFWjL&C` zSxpu*aJ9y#C(ZEA<1)v%n5Ut1)MOzq3CO939+u$*LfD!R(Uw6d(HD=>i3s%RnJgxr z3G}p>>IgCO7w;UY1gvD-1iTK=4~XGf?Dc?h#uov%0ImjL|AST}0zKK-#sb4hE8$E@ zW-VaA9Jcdu2pZu!e@_08TC}&ZuwKv^(lLW$OCZNjG>zp25hG{az!tP5)p%U3Ed(%R z!9`3Up3rtU9z-WJnise0tdj##9ZXkT z_W5*zLap@>W2PSiF?D(+D5r~Zy62qYasY{VY!I_abfdk7e{I0;t!7@{Gc!>@!z&?MHE((;(8A?VQdf)k5yvLc^A4*uACe5uAUizuemyzyXui=C)c?6q$#5n~FUb^xwR?t=;bp z*n{bq%C|lKh^py0D$>4|j^A`P*S5&|TF|#8xAxc7*&e8G@z(kS^1R6uQQ{;Z%^^^? z2Z9;QpG|$h1_#w>=4DfHm2Q)$6zkTSvJqACJ%>X%EO)$>f2&H@`kE0Btyd%0=Y?zf zjuGN9!=oL3okPb6>*)Gt`5Ybju>+i1KKqf7|2N^tq9c!v96OYw=|2_8IU@3If;(D% z;)sOVDA5rWG(^m16`qwf<4i0FKO zmZ)i=wY?NtH>?%P-k1i=%#NicGZt=IEgx#nKygnUZYqL>nsi38shD`L;UidcoJ_&S!YU zW<3NoT_~VhY9{4Ur%f2Fl1B0@rOGV716g?_7)?8lR?!fM_I^nJ^;xXM#51)qxg(N^ zz)FpVxTwt4!IY+C)5I#!3?;I($ME(kgax^e04RDl#8qP^>TJRTk(xk6oys z%siB}idGltdV)SJP7*jdXy~GRf|u@KnEXmwA$T4^3gDjIRJW1A61+U(UqB+YODT5@ zaI6cnbmUc3UNA7DFwUhiPL0LJ$Y4(btKu|+8^A0qf>m}kU9y;2FVLTw5?ix7OK7^_ z0WsCh1H>sCE}@SdpCc}6>uPDa1a$;k^C8;Dq`eoTa$W^`j!kKUuwGY_JQ+C_#DKpy zi%}d7!y)hJvIwfBmG9QPkCF&IQGQz9MU=LQ1nLc;UQBSZDJ(iq)xKe(n8fK$gcP5};EZ<87H$}q@0rW(*8E6O_+U9P6nm6GfC#K*7 z$Vb{q>%j&Yx-;26Aw14^D?VAzC>ESTK(j-$Q`zcN>R5c*z5!!wou8I}=|_rb9!Wxu zq98`YJ`xf~sF1(NYl;J_7zhnLh#}AWRHo;v`XUU&uk4!}Rv9>@sAgSL=j$p%-VC7? zE3EoUngecbK+ftpw%KtTP@uk{#P@e>!oZJSF{5rD7qe*2M?cFKP10pqbadL#DD~T- zKN^-d+_ciHtP%NEwFT_fns(q{osEWb&6X!-uzWaj$n@v1wR}6QIgCae=XThuK=Q0P zlstP&l-6K8i}sPKSgJ$TUsIlZCrhY&H!DbADiKDd%?Zt6YX#)6w!-L$q|lwV$@^>F_=NDa%;OzR>ZW@N4`DBn(ttR)X1%!EKy)&v*nX5 ztaLkkpfWmrSQeHKU;khlOO~+)>wuz+4!rqJmZtLEtRQ9TRrNLtgU!wg#AazFx?Q&P zcJD~J-O@_F-IfE8_@+ua4B_jWdEa=^cU~w{%TBufDDI^+h z(8Wz&so_pT^)+caoRE&9)1p;S9Lwi{BSnIr8V=Z{rEV5IBKFnO7FWTgHJ&5Sx2stt!RMoAa4!|_0CoP@qkhY6L*Xz z$q$ycZTuvVFM;cIgLcaVPA)iYo6Yfu=0ibE4K~Pgqs_SZOmkY&I>#zq&4i#9&@?IS zaJB2gj{&sPoK}-GQUM2vK#q}qaO9_lEc4T|mhS1w7^xFgYq=O!_87F##yzn$&oO!I zEHoIQF&~Bt@*upRC2og>PSs*FHpi@3&i?ci(>~OaUAG=`>!Iw_;|q-HC@8hKf!UY$*-q&bi5MvlV{qv*q{eoX3fL#5jxL=qk2@2r8~xI)|8yQDp1Gb z&s{KTZjdozAA=eX1cCvb?S8wVk8NUcn$7_03$wH>l+$=PQsGOaGoA980KIsm(wH~W z6TI?`Nq#S#UZZ(J0?X-i8ZDLxhA)-rS&LC+ zVpY|onqbRPWS5g#9IgU%|G>a4G}8lRW*p0K73-|bR{Moit=INbwrV=4lPf0nMJwii~4$i;t4N5yd!kYd%!LflqKLRsTe}Ko3%+(^z({q*YG%4bMj-rW*}Wk;e30hG+@Hg}x#! z?e*d`X8mz$0fV%*LB%hP{Q$ZLinRtht&qm6Af}8)B^~2K!$u1RxMvXAjFSmy>(zT2 zxB-(1Eh0Ivl!wiKeR5x}IZ+QM_t?#KP#Rv6Dw0_HL%`0kxR_m<9~#!_tP>ybr3)lg zI<%Z}nd_>Gb=P2DRxUZ>S~lMOunKN2AFXv^kc__GQWff{EHLt^4DulF=+d}@R@f2P zl;6ku0TvK-xt^*&Sp_lm zd_%41>in~Z3Mr&iR%+#{8iYXJ=Mv)vz@ z(x+UC%k@5We=}t`ys}4ShXlweFUOSM-V>P#c=z(>dRGZhrEN-)wX8UgLJ!e!uGrOz ztg7s(w`Z1|d*f)Eyf-Rm1&(@jtnyR2W~u6JZAFF)5psO$a?b2}08E$AkX^cveh?ZqpnDm5{i}tQF@Z$m|Ry?;3+MA zbBv}1w8otlPIv6+vEp>PXjcPoD4}aGIb}Kx|9xn-urSk0b zYiXT1&+#;L2I||}8k<+^hh$*U(dln)vs+LeS^@aI^hS=&!q>FEqq)Ae1%11Dro~RP z`10T-l%zJ3rq**mZb@?s$7P6io1iG@3}af=h*HC?YY~+Yo?PqwN5@=SPH}OWLXS#J zM>OSh!5*;?%R<_GRkw|_722CdbAMK@JIJ)C>^g~{BRJ9*d z4L&AG7ZdGMbz;ZW8e7bM8rf4S{c;IG#yFM!5T7iE?>ai-M$I~W)sZ9rfREu+Uw!0A zH(&^mgk34VRdR0kks}}d@R1{1uTf^Q`|pG|0!NN~4sa>rZ|fA7UMiL>p)F1t;ibgV z>Lni(OR5Pk4fvOem5Y{0TC4=BUP)FTl9X73!CH{WWn!I=FutN=wWoYs)!e368EdQG z+_5?tFvOKFcu}2PvAn7WTSBnv@R^ouB6s4|?RY2M+2YkyYP_*7C*Qk-EncFsHf2S9 zZ{I*)YS~h`%T(V=OOOGd9P|l?sn%&+tBv(|(=O~Vn4HqdWbBCc(5Z0E%0`o!%_e(; zy5-*7P%GM7yiWNnH`BXig%Dagnj0E10_7c<4myj9wL+Cdry~MzTCAm`BiUp_6pE;) zrz8<_y0)NYVOui*FIs3N7OlDJ5S+GV5KilYVem9PT__~&Rxmv6xEA%$N}LvrT^sOn zQ#4j9JHdCsrx}kGo|zIXcGIJCI@aDq3%%FF-U~XKX({Mx2HcKwUI-P>e_kFL)B!py z&43)Xq>X%is8>W&gT54I7OBkORO!s)W5!&4g$T=n7T7mH8g1;R8dbi|T)aJ2Bo_c!2l2qJ<6W1&k!qV2#mo}`mooB1H(+{#8{N5?uOFR7XvXE@&{#|!b$AX?+*70a_m)3s{G zX0_Wi4?u4y&rJkzCm350#LW$@W7A%4!=-TF5L3+%t&7sc*9wVy0LR%sYu3xIjsUGm zyDY5uWAUeHOe#+l@;N^(+(Ndd8^{=oU=~j2Cg^r@FojDuDkSQ6Fe$*Wa?0}ucxICx zd!!D0(6)S_{9{B>Sfxn1^AMMH#Ks&>^CCzj%-e;SoAH4i`+*!8k)=KD$w=d|Fj~}e zoZhkckk5%2_CRT;R9}=xi+{&=GTsFI3NWqjy~6?c`y${Tz_ozm0VJRmFL&SOfE%+O zSxj267MK=20)qiL0aM$O)wEWJfsuK3jID9Cb)bj#_^^E$-$=#mI$IoQlj1yEfs<7V z?Q&27RTmzd<94YrU2KK5yM$6;$y`nQLpXSXeH6aEf)r?^qz2-F^) zT!^Iij_9f!bLG41Ek)JP+THVSXi)j*88bg>nES+|iyh^kAfGo#KNwMmH*{Yi|kvqki@1j`Hz2l9u{*Zj0 zv%qs_a-Emj5G=mibfl-hSkA$-GPWjCrh|qeECJ~&n2ZK!MTe}EsYA?o*Xw3on%2qzNL4JlF+ye>qr;*Vu}}T`-a&Q0J(r`rM%h<09(kl&zO^*O*vHsl ze0Y~~A7?zwxSMe`W5IZ0r{W)BoMc?X*u?_~MWg9y0b!`eQ=sECY~5ne`Sc}9o`zqV;? zS=UtG+$1`iVZBUvJN@l#l3LSTD{*Z{Yo{dS$s$lXJLl){6CBay*=*$s=+g{Cm;Bw&AAd+! zKQZUXAOG!~FO4+aUNJQLkv&U(ymi*?|5UbrV)oXP#KrI?dGb@E0!Br&!Dzk zo*u(a)GGDG89s+=@XL`{4u}o}`yy3ob(aM9F4ja-^n{39YvQA4Y6_~~BE}mMdJ`1y zP4dt5hXpvg@TPsrO-^|!PCYek;LA-L=|eq6G9Af=X?ILLrGfPatk&R!B|i3{*S~Q{ zLVqXcX#TLcuCLpf{93L>^bTlHn}oPXWO3?eBLJTf!rx2aL?`cRG1pJavp^Y~4obkq zkf(y8A_m*AI7iIDKOfEtB}5qod=aN*w-Bz_ocQH{sxyvj^s~aC;!|}JKf83%p%8Jnqw9dPXDDj=JFh~kz+pmBd0vW z3!LF?<@eyVj^-Lp_uO~lSJ&6CGAjL%O-mLUby@7M(le&59qT)mQt_qZn)8hhE?TyT zR*mRq@-Ka#|F2p<@3lO<&wup#^1golYxVP9+n@h!`hS=DQLXy>fB(}OC>Np?AViVy z0pEd-nU;bc27cv4A^-lhN#Hdfgw8>C z1HZCDh%z^11O5lV9MF@%cYFvs2R#fteI;ZDT@HL0&;XjSuO2!FP58_Plq=8%@J2ue zbP~AFE5yx21Mh2u%%I1CZ(j{F=waXwG(n%BtAYCflf(}kX+}9A8u(g(@IaryuK`Ly zPXd3d4SE4R0sNVE$O(D`crTy<^ce7FALIl*1bjQ-YS6>LYp=jLY0%xk8vq&5N#IF8 zbPk&E@(v;H1ziJt0PrB_3Ei?_P(rfF1$<(|VM7(Bevj7eLtn zJp_CkU`{dkfj+WH-tQXu|V@LaYQ`4P4%Xw16i37@!mM81S2bFzCa;Z6TCx z&_3X20Yjk2fm^~T+hh;?ali=ZVc?emyFpI?zZpRt2Ynd$ExvRhOfy9#U@Pcq;5xv)pnbrfNFrZA4+GbH1Ze?HcoSe8^bqhf zfCHe%fmfx3_#yEC?@c3*K#u|cB?|zJ3o&95V9qqe1^i)v0lFLbTY!b2CxAb-8EFAM z0=#z%bPak8IDn_gyNMsT^*ZDWXdm#)fUTe>fa|Xp;(oFR9s%qCP55oV7-;dgLNo)O zB_7~CfCHe%fKU4<CVc+Kkr%`R{MuIJJ?Kf` zlW&LqK^wsTd?(yMi@Q)(KZ&{l+6TOM7xG0=qX1ndJn z4E#C3IOq}J-GBq2$ACZdAnG;f8sHYd&p`WtzXW)lcz~xpgn9wG9C$9^FQ5(JN`Pku zWB^_VCawXMW6|Hfe(x#?}!KZzU|06&?CT+9f%ur5_r{4 zA&sC39|k-Mn()9F^bR@+{M_T{D?yI~-|__V6!b9g4PQoCB^vmNuR#7X@Bkm!hr9!g z=eb4t8RQY@A>cEXz5#ZMV!=NXD%U?h{2Ac5P zapVQ@1IJ&4oS>7yf7%Z@L5r8rro93=L5~9$e@h5)9Q*=53YZIe4EWOTK%by%fLHto zIwTtSKYoI83|jmYsd>Imp@;O;}H z3!n)Xy@7lOT@L(dz+1!*e9!Npw^^Wp=l=n99CS7C?Qf#}0X+v0bg*kOKb&Q1ANjcF0li&0X+RYm-q_t15aD&5)(uNAH38h zeh+#Q_zO4g2DpjLpnbsq3a9}s zYF*+~Koe*KxC`I|-3|OCU>)dj;GY4)peKQ!s&k2cvIqWJy-RE%8u(4XR?vrm*EhJt zFz9aJ5a2=3N#G1%1oRN_&43-Chk^eIup6}SxF8;2#052R#Y=u`ZVw0zCx$3gAxS0X}t&OWX_E0Pa`|-Gc50 zK6{-@jFCNX1z;R>%~dXO8Q>+*{}n$M#!2UxD2Dbjo@P%kp6x%*J)?Sh zcWH9kc=3dLQp%>{>XGTQ)5M=Dz^~*VwWrWEcg8Jq-Q_oyRnP36k(@q0ZK8P6eHi*8 z8J{?c%#<(woV+V!r}DGM%+K7k+x7LI@t+%Bu34pTG%tNq=`^>T5Z}@Qy38%7+TZCj zZ#mt4qU%(V8zaiQJ&#Dv+&up00`YKovkQecRoW=*lr8VzxiSH$Uw;#U?Yy~q z&Nb)y)wEY0>bG4lh5C|0ex}lo zU0%gwwL6sVdkWOAsq&w~((S&T*6CLM3a9Z{ecDuIF*jXy-Pmcno~EL6!*nyMYOr^`+k%6Fx=p1g83RbCve?JSfA70&1s;lEe=8}q`+ ztwXtHm1p_&TI=xLV!Ix5{ZO3teka%cy_)Ui!cOO=Z7SW`Wwq0}a@xcGpFnFp*=3#p+a>v?5(s(hR(Ua~LL zE>QkXHAW$w>OM&8xlmdQ=}pPklP5Q~1!or;%Su8s=jZ!XVN`mvW2mgU4kvMB%g zZ3p`~rI4Sax#i}oUAF~fDj0rlUXdPh$Nq)d({c~Z!9@QaOK5nrj1^SIa`!&Zpyex7Z%ebdQ+sI+IF9w~UW;sdakXG;y5k zGGS>A@shme$PQ)-i}MWR`@jE$1}3g~b`5#kv8zbx6U*bYye=w7u%0zqB-ZW3TGQXV zgaN1qlmo^;gSERVtX~1j4XpVA4&PTKwuWGTI@Y;=1m2Hh-{g}*?ydO99`1(#e*wHj zyznyw7=at@<8)Fu3x(Y4r2S*s2ctbr+P9{CY1-qaeKOi-roCg@U!?s;+Eb=|S=zs) zy;Ry$r#(8_x1~K-+OMWPQ`(oMJz?6nrLzUJCrtalv|mp9v2;#=&J!5mF$}~HGws{c zK0fV7(zyfL2c)wIwC7KI{j^U^d%U!7OMAeyk4<}#vsE}FzwUR9;V)Bq`hC-!=*i4+MA_) zRoaWC^98i8O8Zzo=yWoIJPNzS{h;p!7~jWQF~XrU7+bG*$@2xYw?%t(w0B2)d9+tI zc>`n^f*E|Yhc*{}X|J8mYtTO0cq81Q3)-`zebC8nq!Y5xUL);K(!M0^q0;^;oui<0 z6|~<-`;WB0NPCI2he-R5w8u#M`?POIdv3I+MtiYz&f@Snh$jf%`{Dj~C@XsqH`0?t zx%o26><I)qo~I7_bR&58w-cuL8agI1HGxw@54m z)Bpwm4*?zrd=u~{;KVN!i7G%npc`;2;9i|7~7~o@odjY!u-vk^4 z{2zdL5_JtgJyVfz3y&xkC1M)RR87Zu^O>Sd94BUp<3+icElv<8iaFvWak4lCP0gv| zG;uo4Tb(J+5@!oToFhIU&K2j03UR)eCo08!u>cLgLQy3aiN&}DkJod=GMvNupjd&2 zb5@EAaMt}ooW;5rXXq~#HKJD3iF(l>yrNO8#<{F!ahbRrC*WH}n`p<`tSfMSy+d^3 zR{a{BW?v`PXZ4ffBRDmm z#(SMvG}D`Lj%!d{i#zt$qhfzld`t|98^n#`CULX4McgVrF1Cu>#O>k^obkF#d_sIu z42!$PJ>pa1UU8rJwD^p;Uwl?PfDQ8p#Y5P3eprl%ZDLex7dymGzD`rMWKp$zd4^uv zl+RAa4oM-BBqJJrC3y4&a6>t`kByzHDfj z5xpa9`2TybkjkCa!IP@rHflRPjo8{AFrx$tc!M@uvO98xx zA}iVD=XGqQFAz+JqPUi(>M^mr+p@|R@U&Ow<#7(rVJYihj6POY&`*FmnyK8VFR^8Z zGhB8o6n+{_tggjoto)_zF#4@N+~Y@E6VeyvwcN}yC4+p@gPG;i0jX@#`Vg#+$%pQbvGPcS=W?6k@Y;80l$uU655c7@(;SmrEmm%!9f=jQltl?qJjd zBerfv`Jln9d@|kGgTD37y9l%G$bok0c%xx><;*FVr~$2 zCiK$j2+0vjMU(hOfbvT9hAGqh%fEwlr~O#J__}2`2|ME( zSVw}r{v9U1Z(3$;PdLf;*E7DI@dJ!^Gv3Ge+l*gl{Ab3cFRSnk#!DGDGQOH|it&w% z?`Qld%(Veuweg11g?M#&wMSjN^=NW&CNzV~oGe_%+6d82^Rwj8`}vjF&TR zW8A|y&iGcwI~YI8_$kKUW&BIVe_~wps*2|<#>*LB#`tQ+F~+wtevq-w!`*Ctit$T~ zzt8w}#(!Y^XU0X}Qt{7VJcqHtcoE}Oj2jvI7=M^?FXK4lEsTd4Z)JQhJS2AA8_!7oie@!{&_v?ew=lk_R>EVBS zeejBU`kYOy8T&Xviks4%U zHOepDn6E2~@48l-A7%8Z_l(8&^6i?#;s-Wc^$j~%irGc*--0o_S5BYAd1P+ICv;;G zN@^Qs7He_u&9YSzB7K*UUAs9`@$+{r$(97E!IO zsM&luH&>l4?v_Y!Q(gv%c6SRVGA-(ZZ%FC$Zu#7i51(|Qh)`gp7?G5CA4+>axMQl#W`RMA?STp-8Cl?PgURF1#Gu2*Y+QcEyOTbnBudD( zKA5BrCR6F5>CJIu*OEwV%qBH63Qr0Bt0Ew9Cs0|ih?6!wv&BV zTunE^-Yp?~`2~{{QI+8=lTsnlg<(qbt7enKEMWYY#FOq9NsB)Tu;V7NbLC8|@wBOsCR-JUi^+ zgd=8paSGR`w2jP6+{f~)RbNwV#rIgFN&P)V?C8I(UF_dk6z3POrB8Cm3~dvEKp3-S zEEr;*+5uBE(G#F|sc|=31h8Gur)E&tX$tgUttrlLB5uJQa}mH&MI0^8YoN&gWiC0x zf^rAMS6ym86eS1M1?rTL#tm2$h^wai;usj#U&n^^WqMir`L?788jsvH&s1-XwTx< zOCR(Mu+JMj_*7jeiPCl>Q8b$pHxZS_K8pC1Cl#c}$?x-^F_lq0?BNN&*x^ZYLUw!7 zY0P$Urs0boBuJ*`D@4WUMd+^*6(`GaqB7WfKq<*2rra~T;7db z&;RN7?Z$K7xy$E#-{!AE1Cu?n9CS0jlizEr&Ux4EuOhAg>l1;qeb51pnhiNs;lgPa zoWUw!kK>y-TY~%2hjF$EwEivhEC;!UdTRXj%CjcTICp}694ArQa3-Z)vOec|^Bq3L zDgLrx4(wbKU&;Y_aDqn7oY(^Bb~kZ#;Ot3CzQ)*x(9~;>^aa^oI-)0fB~LZZ$5i8F z4B;M-4CBGGamYCZ5pRz zDE=hmQ13>P|9W9?81yD(3Zc`xl?hM=PRS5IamR6@#(+<<&w#H7e&|)oE~Kgs7$5%z z*CyD}85=|TFr-w?+?icbBoNa#!`Pnq5u1e7n}|>fY7AE4gdyuHjwx?;6>)d)L^meY?hYP3)?9r0Eg7 zwZA91XK2sxo{>Fcd&c)n?3vtyv(kIZ_ZoYv_txz7?d{&1+&i>)c<;#GvAxKc3GDR% z%^j&8Svdk?QkjjBN^Jwn_kVxQ8d!+Lsqs~*N+!?y&Yq%GR{Rg))W6~%nWN^37k{9z zmK1*yD;SD@as|&Tajw76Pw{{FIg{V7_`h^!A#S{T1Z$kco`x57B*So0@&99CcIJQZ zc+Efb5yk)Wqo()e1)9Hmlj83yE*yc9r=wQ$Ph6+?pJnyt`cnKAcwvU+zgh7&(H)Bd zKgIv+gyx^*cl!Hx7GQ>z;-7<){3?7OzpMXBVRq(!2q)PUzfr5+>wb0$e#*uo;eAH) z=d!8zuX{nePjYxaMY~++r}*99)%<#$VS6EF*s1vU{ZRAgvZ?UWKho~W29+L~X%zY? z{slkP{KL%u%2CV5w|=MjyPH+`wMXUuHf{ze{f@ON{tda492QQc@8;>6KUZeue$kAn z+*Nv-W@>lCr{cTpsPbKKmgY}(Dt=6-3jS31;%v=7&io|>xpjFw`y9Q^MQ}a!PBSbePOi)I$5Qz6UNqR4$Q1J?H!g>Vf_wSe{>sK`|k>JO%bn~oL-GQxB2 zvru_a=`?Hz^cnIGK5Q55i>r??!ll@9!8*PuDw>w=$8ll9$>u4RjvmFW=xI)t(rFZ@ z{Jd3>N5$u4aFv>7DWj(pPj!jnfOlQJ*VozH-WKqC>)ZVe;(qsMrq4n(FERIb>J#CJ zaNj?D0hKn(x-k~)OAGgBrM<_p_v1sNsjzTAFdf~6D775)&Y$~p({D#me1Plkx4^tJg;@48OBCF}lJi5r2I_?9%` zGp52lRC1jZ*SA!eZ;NSjeP&OG%hdcz=v{?nyn>g!F44W8(_Rm8ds6g3*+t5co7*JVZ1{c zFCpV<81IzE8Zvgkc$YNRm3TSgPso@WN*Yqt!u?4pTN4aRgnL*Td@w8(?z^R79SqBa z`yOfNhGB(pe@YtqVfc`6-zyEt5`S=uaNj2lTT1*P7(OixLnZz&44;vPttI{*819#b z;Szs3i9#R^_rnE-2c%&HE>YqBoHXo405Ci#4Pzz#mBRgyr1zEhFA(m}OM1M-j}NcA zAC`s#Fd#J}(l7x7QnO7OUV{Ot8I^`f7?un7c4;^S!v}?Xhcp~6@kb%dPHA{+dM`>2 zuD7qjmR}-;4;jl--opKS$^GQuW(U3V?tVdf8}ZC&ptH%Q^|-X&?U_M4<8>))`Sy1v zWIQiQmod8weUn_eeOGvh+e83~zxXM-6-rgdLKlUFaaoze( zuPD9)LpV55#Vx)Q4^0YpgEHK;5DrBiPj4&{%m{ajZ%sQs`BeN_s@iC$xD}F3K~Yh$ zYIUe(ad)+}x2+ENI{l(#2{m6Tz!l3y$=9V(1>}C40-8y@!abLs6A&|-YTFuGyu$qn zm+7Y5f93iS0-7m9RyMD@D6E;b#;3ijv$+kPzgBb@b*7AxI19b=anyz!N6p1?<%m#H zVy3Tv$LEXYgWps7Bk&dnT9+(cSu4ujtBbFKZAnXFvv4;RzXUf?(iH9M7w+cbFT+$S zW-3;Bz-^m)emrFa#b4GH`F+HP-W~J51x^>(n z{moUzfZU^ZZ`2#O2;ovIe!hqzUIPa8SX$R~k_&B7MQopm2Y|iVW?~qa{=ZMks11^^4Lp zMkc7^OVTt>CZz8%X__DtBpH*YNiv}kdR&?g&wvT7?Gw_3_6J6^w_ldVa%n_U_!Vh1 zq!F#*lhRl%jnp7MCCxR;43WMn&3OM1fl;%#Pnx@x8Dc#x%}Hg3V9!YNkTOHGuSqjj zy<}mhhEW!F7w-8Mxp&D1aZY0_(}5!}!u^OWpfDqUl+A8wbJB%0Gms%rrz}G_Rm|Fe zLb*?yXNi+b-H*@u8O(Fq=tzqDiCME}z>rKuHbD#0kTV8Z-Q3aXueA?I%H3m<@e~SI zoN@{RC`G-aP!ar-vuY_sb@~W-`_wFIHs+`^DlmUlnu+tktO4R|jAG0|#aXytnMDoD z96lf-+^^1}-W&q8bp|?{>%>a;{#nH{QE<#QyM;dT>3&HGP8Bq?u@0wqg!>yZs8VIs z5*@(l4fi*tU3p1Iwnv|X=@IUirS05PNNl5|HigfSrGlx!E>vS*0xd8V&~HngN_76Q zUg7?Z6rvhwrUcAn;oRSq>6z)%=I_l~09ieyGx2w(uer5$wKve&(h;byZE2~it-oBj zPd=?ha`^FgZXf=rhLsYn8rD-Y!M^(T=CcR;8c}s95u#MuHFx-GJL{XobTWDU{&v5ZAz7$noJka9X|8SS6lG-S zYP-CxeQldKjtmXndMKqu%pybc5>YNWK+IOeQgMPJmWvZ5%StgvS*#Q%Necvfva$hn z3Q@9Col6wd(E+`PQ^`QR=V?TA)HZr+{r=kZ;&d|BEBXwg>4-yvw-KFQgE*5cT6~nw zvlO|O=(CCDVflGPHzThp>+!liO=XLGAp)R3vJrM*tn5`}QQwXLE~(d~Ye z3Q=!4cpC!kb(eYTJ4J)$u&lgfML}tvMzW~KMSY1|IxwPWB65w_-+?Ivd~$TnXOK@A zlq5%vC-WLagA5bpWKfzAhGbmt_cjVqLp0Rr^{=6FHAKc{+;d-zOgnPKW@@eNxEvfR z)Xw!jFIm7S+yUR3#x-L4DbJw|fT5WTbE&&Na}5frEYH&)x`m2o07s$d9!fMA!^9~p zZA>%WHgkc+v;aeqIE%uV{%|e4pB=!Ln}gxL^hY*RmtFKqksKSn3@3xTN!Za4?3@%j zTy_^92y}Yu#JO#m`fMtN^P`;+GzgCvzk)Znr<8o39cZQ|fUdJd!t^=ZU@C&v2hCYu zL^lsb9rR4Na9?peVr#(l8ahcwmwn(M?Yvv+r3bPgPJ;r9V6+NJl?|GSweWo&xjLfE zi|fNGuI&_8XE23>UZUv3DjIb#4<-slRG?80gw&NF*CjL{(o^JCqVaP*Sc-N0^Jy*L zRYN5G<{ht(@L-DnN5oR;^1EjUmzaMVJDdOqSQgPPsi&0MmIZ-&KUIe2PBG&an)UgZ z^+FN^Ki7lbKLPL1Y$o#Z9bjk%^*3>8q}I+r#{A6_(pUrI7ht3nB9WSn=lWa7{$rG; zMQGWIePKVlTb~V%`Y%#Z@47fv7$egjg~%TdfIffPsF^2u>yUc1kYYL0Gbn zdGMf*{G9}zrRqc<-M@3)B^85ptYrt7^Gu|F{+n#5WMyoE=S5c|)+6jN1Pj-F7b3L9 z_rm&egiw78NwsXu7LHi{IZn=p!6{XJ$Svl-#Fi^m=&p7lJ~#%y=Sy9zAzdU8;L={| zJ8@mjwU(?tMOJZ?KhzG_I?C}^V6);oP}*-fK+a@%z%wG^L&F7}Q2rNx0rvB-zOypd z-v!UW1wWY+?{J`#uy9?u7y-(hXn{wW6G;#%CsvSVs!ve4VakwQPhLnnpCV4Fo#h5= zCk{8QkLB00f7`q96049lKpq6HE!`xYD4!Z7c3 zHf(_5z7tgq%#s>V4@nOwfb;&uJhPzUrwj8eJLyD~3lzh=1#BP>zb))x-i6FV5zj)p zsp{uO+-VDEiJiw)&9W`qz${sc_gXek%7PC5B|0tl*jR3Mu;?J?J%=lQ@0Q()gf1&(!`(1kayA<%0P=kI zx)ONy+#SBxL%#3sM?t$Z5J=)wcOWRAKB2Z@5w#828{m(m)&%gpNG6KwmAL3h<(@Fk z5l`RtJIHh%bZN^T;%ddX)_(8)O%*$^f&40$`iZrtn}qkcp*bH)p*O;99s7 z%=Oh6C?jCin#sm%iYDk7?%pqJClHk+bbNT$D zmycC5nmO)jd=Bgc)4$Y+zw$SI%qx#+%Re(;a5ds}GCWuWo?9Eg14Q6DxA6=h0$0Uq zE^I>M88qLtJ#FF{i$|H?*L<~PZR|L*boTebrbc5h-dEikRo?!AkahK=tYUr zF0``d;nn>jZRt7tX;>HWVt?_uWhii-sTcdxnz8DGk}-GfKa0s>v3)zKwfj>0B-qv6vd@~ zB5%3d2PMBETXV(BqZb-I&ZV#7(sQ8aX{96&-eU=2(SLmhY^G;6;Vyhglw5fa!jZZQ4D%*bNVM---S43#Na}KKkiu&Vph(ySq5|8 zhv0tvQKrr1=CqmkXNsa1sny1uho{X%s%bM(G;Nj`(`LdnZI&3*X2LXWCak8-M5$@B zv@@s8Wa4SFWRcTmqReSC8O&)j8O&)j8ED!pIcVCf2uzz5foZd3!L(UfVA?D#Xxgl7 zXxdDanl=+}$}w#w3z{}dtftLG=1-evlTX{Unat+2nGAZ`EE##) zOtfvD zq*pPNXNiS;R0$oV`3!>WY%!)jk!N2Av-C6XI@c-+p4%<0_R(O%!=Z*Obw z>JTm+wUec;tL1W36_(ZM2BA^d2aPBSPcqbNvN~S@3j)3y>`H>b~FXFJJvQdAfr1_ z<2iZSks@vIcGUZueYC_xxy}@VA zSTLOyWxtbL9&L*SU3Pd=IuvUMx>J}4C1RrNkJ6!JPETuai%-5c)`4ZFYEkxQ=`d|h zG`t4Y4ZAL7|0bg>g$=xiv$&F2_7`b2gQQY&h_WNns%%cQH5kwK;#D}@^n~Z4B1+7x zIZ@MZv9vjUPP7A4^M zvO;_Q2*$GMeo?ke+Dw~+m2~X6nh~s!)}?c>xsVEqvQk^QwN7ZA zsP^(to?|1FB&pr1h)aUtqKEL<<=gsGnWbd`sUVH7e*WP>WefC)= z$roSw8Y^Btl@L|A(*@;=nyosZ;n@PVZ6q%>pt*v80R@$$jO#?fK??ycWnT*g2QvzA zPVQoX#X66MI&+svv*K1WD?~Hhjb>JhW(wdEK7^)cacJ1CUv8D;#ByijbdftxI2ZpKl1)fmNE{{5ph-7+a=@X zH_u$XZsCfWC96(G0KD7_#WbL3Xg+8t)VV{bq0Tf*Hs_JKmkKhPzdQ};wz#^PBk3A}U>F7($h}^q4Rm-@Scf+UI`liB;g3R*w&5GhTjoyp-1Gg@fy`gI z@DvX8A4?9|<*S&zNU|QXjcZpsxjQ8r$zQb)uK?#>Cb_KqwT({h75)}*iRGIaZP5}Z z_bP$Joh*)=XzUzHKp(%$K(5xe`IiIGmFWW4|2zvD&>RzD&HsW!LURpEmv6-G-2bQS z3v!k)paG)BAu5vp)j4>%Dwcx~LkxC=$Fbi;0f+|x^D46c?{`prLB0(?2Rhd!VPOiS zl%7k{(fP|X+En8r5J!c$Gz?VoEFrJUU%KKnMisSA1j^(}nfg{3E!aT{F3U$)*@f69 zE^cVV0ejpn!r8?d0!>&a1McLW3h+jP8y6wQA%dhWmdAp5;^S}47mXlBE~8WVU4-*C z1I!GDiW?AA;ts_!Dj94*OZJkIyE1SX9nk#|?po+;x8hj67AlZJ`_ShM3DIC8s`>q0 zx?@k~FSl_`{lTJ-{rLf4i2E!!9FS}%Re~jKIG@Y+K4NZBqYnH$Qj4S)BUxX9A zz_+Ta#BRp!0yDrhQ|F{S*BL@Nfe&{Bm)pQ5RZX0f^0EzV#;iI7txoyX2zP*qFv6je z+dFbG4uk^7nd#6eQ{ghsu7ZcU zDH8$rd+Mwy70wyyh_YET<~paR!}zR~Tb9Alof@hf< z(ovAHwzAe)p9zH%Jgcs5>hzf?vMwDtb><`}_h(yz{ICQeKH?w-qTH2yoaP!CoS*WJq;Pu)hh) z1bWR1mf27!-_Y31&Al@6TeL7AF(Sl=_^DX9)42o>O>(c6OeCKN&QMA2wPJO+1g4&E zpfjupOL53}d*m(f!T}oo9{vyf>BT<)e2IT{y|;y&(%icvZ{rBNbBq>!ucRF;RlFyg zdw+zUx_W01MRYL z_HrW6rRDq+0CVbPxA={zaJok9FCss|X}Im)@?>4Zq$IDQ)FsQRYN~i6BojAj>dd;D zSrZ+%lMZ)VXc9u$>nKh~>M)prp*%B*O`r*O(NHnH3Iot_@rIxFDC1GCz)HSC?f7DfA+}MjJpuO0CnI%K+Om1oR1yc4Bmc1@0E5(j59kV?9 zUx3@TtI`|Le4OQ&DUs((&|pPshHsOqrg8!XJp|njM>86uhZ$Ret5FTha47<}E^CKl zLC!I^yrwYiM`<4cCS1^O2;iI+)7s9{}$Q_!I=eW4t6o}3N?NP~i_*EJBvI~g4Y z5*Ei9F2mHCl1_&~qXEpNrhbA%Zyw3wy(6PsC)Tl?4p9!mwRWr^jbl9BCZ}U1^%}{+ zT{L*U$WLHC3&N32G)5;n8lyXtC)EYRyw2b5{-g(nIR}sbV_9dB!P@R$Ad57dn!s_Q zT5x?^;N61}jytkE1~1IFO!2)0+~XEj@I%(&N!CgRiS>854}z{(ClP*LCGB=n>NX)>$*1fhT%mC*dRSm%e%k|7m=57XN>I{ru-t3)$OL1n= z^D;=v&1}!%5XnHPT~$=gNY>Ti^b58X%OIICtE{$aCa(WZ#Nl$fR8>IlN{7c~!@9;@ztB6oH<(H&W`D59t(=3o8Xv3h zhk5K=ZaMMD&mZkw3PSESnH%pN4qW$qT)5GIv*sC zxdo21E1wTsQ_vszLjc{K-)5|L{}K^v4{WK8Z*ch633jjUEHb_u;@>IQdr%f4tma23 zXpfG6zdr^w?#pk=h;Hsb?Uw=ZB_!o`+8Y4X#yV6qq zfmHkhAh&8b8bjuAjvEVp6=~tf(b9_pzZZR|UN>@4iN^kF(Htfr^tZrTnsz`53yu{- zL#NR22@@V|3D>6+N>(dm<gOT+w8vCim(EL*vaW=s6E{oL3})n4<{w)c4gy0XYEpC_poi01rTO4lgmg5<73pwVot>g5AuXz+ z%}J;B;yT`o2Ow6^xt3-pX;?uorogVR=;lmh`pA?_FAzhfup7bF{ z8E`7jIZC`HIDn47&R+_m0dPeSqS0SRuW5j|QzosXi{Z%n=lSP^NY4`oYhWs#pLe93 zP5RG(s2|)-2LPt~;@%C@G_-zKx&nWmG><_6fd3tEr*JnAg>3&I(Hv$v#^=K|^o!_9 z`uTk!7p^I2egJO|AWfcwdDYe5As*+zjMdeAGs$sJ@;Ln53UC=ha(96MoT2kjt$U$t zMBMX$H9d4;ggrE5@%oi3PjlRhWuG(z-MAw%0QAEyfJ9e-n1!8Oo`5nZ9$+UYi)@BI z&(7U#_`V5%;k!GH?{xv+>r;IH4q_HIe3=uzICLc&({X0uUhU`iOZD7p(;Y!{MQ@Pl zjg_D=y)h`%8-qftTAQY zl`@aA%wM$309)e{+=P5z+VwT?{E5a61A~#&bE1p6$b&Y?kK1wp$x(xWnv16oqedce z2@_>VJdMQBqo*R}){S0(f8Nez$C1K`luS`Z@e^@5(p-c)9v9)-Ig#VdMY!YLx!#6C z?0;n-z~>2nV8XrKTc8Zi4nhW@gAQ)AH#Bpe@GoI7TtxB40Yq{S$1LUOxfpd~)DYh3HaVfxPh_|l5DYK;p z0$%>15)GG@@~+=>G|?@>eKTpA@oLnWa4!|n4{Dhmw%V2}(LZCQF_%hX=0n7yUM?DN zna7jT`;b3ogOB{>V$>r<5myMeo|sQYVBGE!gFYX*WbdweAqzsy25U&}7NG;O)_v(_ z^;_U16G|`@1WkqjcTYj#CY)rwBH8yp4v)-_cW}(9V(#BHJ>5&N~`Z+GQ<@ zWtU9=m|fNch1{-icG*cGxUG-$8x+0{^tKk#UzCEE5A0?Xo6+0DZEuHm6zN|iaSuwv z6I%XUD}Bq)F$hf09~4#Gg_fG0|3rFz&|y%O^!BI1VH@)@yMHG6TaX{mWp}r-<{27) z+<$q^;63V}1=yCy(WX60z_u;|Ms-v2UkYbi73L(TgorOz;!U`Xy(5DdFkEmV_eqiBU@JCv1Z5w*Elw55duN__l1rv2w{OiLLE!lOnj_KSqtn>t;&ig3;c0gMhvmTTMtbP7bo*(%V{KM_T5^t-V{X1*(f=I6Fb^7F>qYr zWxf-0dYC@B4(7@qEPF@WYTgk)_7+rAB-OklzU(*5S8+amSNz$tv8@?vBBBQ%JoKr= zOFc~l{2g4qodqLsY=UXJW)~b{TTZr7@s^0?2ay+MAun3$SER9En33Q znk{cyvtr?CI39EVTlnVq1$vL1v$LM)+d@o|uSswlVYZ;C!0XlER~?ed;R|7*a(9hr07Fqrv1z$?IQ)PEtd ziHSW({ECSdB;G=zWR8|IUPe7$Wq?}|*?9m5jn4R=72xzh37}{Bam#bg0`t;4fgAM@ z{&dC&81*y~$01R2vyyKM&4lB~=UYXviEb?CoirZvEsw28OwK#pv;{A-lnm4KF2gU! zU!zLkLW}jd-iwv0q?QzGjr_PdIaRQTl%&73weZv9lM|s@sxxc3r&TS}&?~D|?Z1IA zCxbP5#ou|bS=anN+QQ}N*{clJI0Wjm<@h6hU^?)4ueks(?Kov8YQ2wvVaY|BVRrf(om7wEUf~eg!{y9b*UPgdBQ( z-#{B?U{1*4Ci7Up%)p$O!;RJ|f(8su4d%l0;FWqGNW86#7PM==J>h_a-lXnT^8}$v~SD?(OPmuTs ziCSW(#QI{RhEvt#v9=8QZxafz+t%Ulw5&5Xj_BX7&MDcW6m<9u7L6IlwP~zk;tK$Nx{{;M0GOki27pA9`@p{%T*78e`z$cG>dMt{t{rCB2R?R$(+@rkqq|LcG=zn~_LyL<#v$7F!hd8$x~=*0des z%_OvjI|4l{A7S;dL%f;m(9)t>wtS~g+_%gpX*N5B!|g{vPs<(mQpxql0fyNaT;_9l z^VCuFv;{?T`~zngn@`>qYS~1f*u}%8i!F(??n&FalIOI*L1W4o$HkfgKvuLCX z4)KgeZV`1-n}r=xm^orQTQ_8mraShCDd?7FTT%*2(^ zs-TC;j3tjEcM<3=Mq4cQDV?K(@iUyGdd z&vY=&@%L%})bUBX+bvS1l_v`|;h*F8)A6dOtC!1`6j?R$!Q8d45ji> zfhpybG%Gyau5IPg^B>rrH(g5cq)U4`S!{o%;zCd7<XBAEbuTQ~C+8^20#9=FM zOTiRR6x`d%qK>RPzkXHtgm*=xKsnzKX!PSzR--FKqc=+X%|$kMl_=q8h%HL^7PLA3 zRyzxfQf6Feih;7Tg9nl!KmVGikBzbqzJ7m1f zw8nPvc`RL^)jftZf83Ubk4FP#y6qyShwbi3DjZ0?o7b7o*_zVi-rCVLL&2(4e_vvGFF^&iM#VTp3 z2PwPzpBx7VjOi((fcz^Ml_Zs708E3X8>>TullAO zdd)TwJ9_zXYyH1bvR8rI2$sc}1XKP3Obak&eHV7b4;9Y?!hd|IZ}gG$eBT1v>LpCHfjm15|!4wWaR_ad9Sg7TL`ruM9pV)yhYG zWwYf|Ps&y%I!IU@K%w2V&}gySX9@&B_7ASUh(6nu1(X?BE`V(7nFA{9p z6Zn5Dj=n}ehXh=6+qBCvnzqW8J{82pnb=umH;cS7_>|oKADU(>lcv>&n)V|tRG!&1 z>oCZt;oV1MS=y(>Ex}yWxzw&@kH}hf5kwwq!eu$`ZzDu^#mF%p?ql+t>}uxq(Y)h6 z9^rHH_W?UrPWzvbXYk91fCf|4lTz)kkdsMh5ZLAT300gN0#EK|>>?QLuS7PDgZBSf z0NvpzCOKURICxG5hPJv6eR`6@?H~cnJWaVm5oyRmHU%%46oTvIj2VSzsIpU`1&FKA-pT5Lbl6JuflNd5 z@^#A^HY~?i=NVkakt5v&%JxBY9e*(WB<(8dM!9Ku4ZS)RclYoX9q-EF-4ptz`8fC* zyT-gp7Xmi{JPC_6Tnj(SHPzp_W6Ox8_-rIfMxvbho(GAU$)l1_K&v>FT(uY>9o?)b zt=`|cYYUg&?C7@;X(8?p}H*>eXtjoHH=1!WsELw1sF<#df&7gyaPJmk^Vk{FA=!jL) z%tNP$h?g?I1|80qg7ns=d#Wh^1f1c>gfj*_aDJc@&N$l4Wm?f*4=q18T3m@);c>uk z;)&32kT{4$EwNLcNA5UiY0A4uJcq>SgGl7~aphO0jH1hB zVDB54niU>b-kVJSWAaHgMwsjlCc3vm#r~aE%$!=J)!kj|c1n5`rfOsB4q4M0Tg2#W zhqiQ$51q}7&VW+oG3pIas*}7;`)oNz#Hm0T&Q9_ng;Sqr8@S&*Itw0GNTELqBep4G zJviMJ;$-V5r)Lz-Y3{xdqxVwqnNKSGUkZbZR`#62IE5x((G2I!-mo!>45E^^6mH!} z`gTt8By9*g`V>PQ?r3Yk(no=Fm)sC){tvZ|Gr{d@h0~m_3c+twIMw(og=1PteyB3B z@lS>5zfm~(yq$v2%~#u?62CL>?B=~&vSQ16ImsGD(zEJ@;ir97vRmPFCKYC;298mg z8giX1j(NKz@X55fT52zTy1$muolqN_>{55ImzI)AnC0bQ`qwg5JO!&U*In+8-UzDc zBh1u%uatikIhh?MqgalA@N_e9>UYET?w*JlS!TC=Q68_s?@L}AvgvH#A$_=WYT0`q=z-}aq3++~|2O`Ul+tQ=TT0ooQj3CUYSvNKv>Mvq%M>G2&Q#dG&I?+Go8Lb^8N-!$x{!p+INy6g@V zf%a?JD}u%pPPUC1D2VHWj>z#@iNVI8 zl8z=g-@Mhjfwr79@Y-+#FcV&3aPV zCwFUt3i*eTJv_#3xwaMZfEK1g+Myn8cyhnOsgS-Y_z8bkc!om4_Ca$`yQYo+N#-Sc zcdIna8DhHfp+GU`)mX)B6~&x_rW?haB_+DU?Hh~BdL~9eil4#W39KmU3b4uX7ucb2 zyw*d-}49Q&c_1{NAcn8A>% zcgk)E6)m|Zl%Y<++bk_?i%cd3xc`Z?olHVk{M|jGoPEk-WuVUbTC2`IqRuHe4m0QG zzmRZOe?ndqMnY_At-?N5PE^i)`sc4c>jA)+y zS_#wNjd0%)5qD^jZGnhiPO(~kM?`!8B93KP3Hw%s`)(HRM%QDHR`eH4_sH)@{!`}f zrnC62aK31aHjNCirk`e(;pEeyracE#MsHX;Y1)h7-bk76Ja<@Tr*J}7Q$$JR=A!lC zr;ll`fVkg^hy}{#yrA*VPPL8yRvJHOtZn3X(#S`dmqvak92&-HBUup3m2G6ba%TVC z4pc@XEuA#-{q#mU^S1w|)@5{RoA0o=z2zR$UggsqH17(W4jZqmw_Kw73gVjy=}0N@ z6C4|eIoUyIjPP3^yx+VRL_ftgC^Q#>lLmDux1|Nasc z<5q_1r49iM5Jp_$Tet&a@!_VS0+#te9{I#$!;3-)eKoK_Uh{K1#0nHS{@fhI8F;@wX$#9-(ugr*Bk5LwoA5dg|eGVxD{p__s!tr z{pNkJl3?9T9--`cR6N$O*JBbK6%Py{=P7bCS}o_uMImIfBDYxNiHf8uE;mRl@qsFS zuIODr-_;5|^Ik>&PT4j=_fIJ7dK7sp1b-#O3SUt+eUehT?RE-sq(!F$IbZvnf{bg8 z-l=H%in9%xN1tUcC|nL#4r+#u;~6QU+^p!|K$a$p zF4Q`WVU#={s`x)unx)pthkQIUmm_$46l|UCK=`UlXSwA!_xW@W{z9HNn&EGrd}tB zA8WjMox%bX8Bw}KFMCngFW*UP#H?H63LKG zjnolZikAGLDHZPS8b#9@V(F>4FePH@VNW`}l>oMg>!o9uO=wdQ>kV+J@tgi!!W3jl4%Nm983w5{`58! z=s>jIs02c4kPrdxJh>CRKnpI1yxXSQxO{c@(3vwqyitX zeTd!0xE=0f#v8%DYuKVwslV1#j1A{jndaG%zUUqJQvCILdW~E0pT8X@G+$)ET`?qZyeFIlz0(SPxiT?8syz1)#M z@pB=Q5SFXl~B<%mZ;}+$hB!6>C=I!}yz96m5J7TH|krs>SIc z?Bn~~#>>Hvza0_Z4*&Sualy&pijyxg=f6d(As&Bo2Spd13$Faljb$(D25SE1=43A_ z0G_|Ozt3tM2|Ry0lr~-o5Pv%)7cIg+{`xPti>?Efzy6DE2+aTDL$rP>7=5H# z%C;Gd-fR73T0azwK61w2QLWE`j_~S{?IqAIzTktu_(pB;Ia(ZgQnVlpeVgB}jl}k_ zSY{ad=oJD@i}xb;NvNZS)T*#Co^bOZ1u_wx9WMkz z_;H5f@k5|g)aFPCYU6-A(Gaj~>I~R=&gmNh)lHf^ zqYB@!bNYpVlV+7UgF<TsQ)RnT+M-Z)&a zPN~l}R)U^e_5siYJ+~}d#|syR4eqkH2FFX_9M!fJ$60*pM7oJIy5idLwEg`-cv0cK6w{L|G#|v+TwDH0%LYSq+ z3%3#C^agKg2swHF8}0yXK01}5zx+2{zV_vGx`7#dxE2{VPveFAAGj|g@8zY%3-|vj zR1pgeLOT0@7ev$|f_Tn2P$u83yv%sv{uhGC&I{s&`~Q+EV}RJ0-~KlOYDcLmG$hb> z0?N%xj~DKH9_#6t7sLzqqXIcBFFjtk9}{pqkD-^#)8mEv?FH8`U?Q!eh5OS5<%^Q7G7uMRwt#I5Q_;fxxq^WC1eK&r>qNmp2LUc+ zT?+*VBMNYizgS?gPEWD*%cNOxqn8z;m+nR{t3@vbShu^Q;ZY6?J8+fFX$t;4c1&+2gYmQnGP87P4mix8L&lN~-=wPvCDm{M2< z-+$gKh3{x=`-QL!FB=&;olRZ7YHH8R)1Hc(3U0! zsPdz5m7i#p(#M~L`q<2Ge$MH&1J*zh6K*x zv8igx=#ZG7_y(=<^v2;XGsg8ou_(0FuY~IyFvMzY2l;R%0u_eBEhEfS7_( z4pYReBB-$vaRzJnZTK<)W3HSvJPfWBX0f0-eEx#Zf#Jn`T+|JX)O^3zKRal`RAHvN znkgC8)m+J7q)yjQmOK7@0r`1YU<_-xgMNc>LzGl1{W37_Ojq|XCn{}=T?0t;A#_Ln zZ#n*N^Y;SKh3Nv<`@Bya1J=YL@V?-Tt~m{M@BNdoNK7t|nqc?dSKoC36@!totC}3| zn=Jsu1Aqyv>HT{U>*sZu!uzRmS3hm=KP6fO7`n&X+pUew_ z-Ft&YAN%ucuzPQaTh$d22`xZ^-Q%mfEcZbG41(Qz!vynD&<7Ii-b)DAgI!ZGTkVZz z*un@wI&N1v5Au$eY}|G7i#ZoQcNPj4SY_GxFWyX{EtFN)ET_Q- zUc6a?8Cx}KQ$&K8O1Z*lp7J<& zUES#5&~aY8RU#4wr-r}xR*OhOgMFXTh1n=S>z|mH+L@VsWDx#7*g;6FdkKG^4l?2I z(_tq3eLBpBzqi{&u7>8bSTtBaC*pNZ2~jq)VNTWbN<`hAfp4Cb+4#(%eRQym2PrAI zm{r!#tenD6ai@0lz#fuCu*U}x_G&Ye_!{~2228?{KusE>pCjJy9a)f{l5mEN(cisQ zjQ$KrdW`;bq>a&^4o!uE-;{|6V)UmYOpN|?mHFC zc{@EG$&69%7iaf@a5%=p-yU34deSy}KFvQop>i@xhE^fJH2Xv;+sLv_L0KsliTxZ4 zc_hXaJexC<1{3#c`JLOC1QYkBFzv+T$)m||JHcf*TOJm0p^;$XIeod-#B4C}oB^ak z!B8;qoPn~=;|wqqOgv}MuRz$IO*#zIthgSolWl{Ew=3s@6GJfZb`_*?j3?3Lw5y~7 zBC)mlT1vYK%x3{YHjx;elt_%LMS5Uvr_S5%_QHc%nYUA~_+#n$vCLrn$^d8S3uOMo z0+JqC+`CZV-Sc=J$%qEtMQ$JTLSdd=#28uJyI6Q(jt?S>dplfutHp3G_;~{CWaw^< z)_M6VnU_lqQk{aU1!f|Phx|W{*5r8JGcM!Sizn;-LD(5L(0f)gu5&n5wgfai`3L$q z0lJB2yn*e+y)NEe)Cl9ucwN0GKVum-gx~f?d$k~p=gA{-Z# z6gtoJ$~vzJWCejoA;Gx4bA{YEhK_fw$M`UbJoDm{cZ+uovZKSi!i(!8-h)7w3Oe;n zDkB)T_loy6s3r-OS?ohS;&`8U?Rz;+UEAnXFmBKFj|E+Qh|a!v;dS+=0<{2MLFPLd z-avmjP|MJu^kCdxi6GX%>B+p??NtkEqp%CM)8Sy;-U7K`?G_xzErn+rW@w z828ZeHu+TOj=b~>r`{I-aS-pyOS_5b{m6e0(A{}$US#wx5wZ5bmf8r$?Oi9>z3S*> zT(a}-6zn}Hi&2#d#_iqje}NkJh zfv^mD=0!yN+MDM_iU2-f!9k%=FmCVg2rK-6mKO@f?Hv`FhN1^`0EL2ad&fjL*uLzl zj<{Btinr|*3jy5WpuP~YM36BZ=Nvyh>E~jcbI{4)KiL9%G6l>^{ENi+sf$Q#hNap@ zD*geGo?|3-8ZtdNZY=mRq=h3#OHU5`o@Zl-_LNA#k=P9u&0!Kkvw4<=(T{`$$BLoh z6lnN_2|uue$D|WVRx4!Xkys}X2uqF~5!F_9yv1ukRk=QJYq4}pUvZ{jRYK!Jb zFlask0_Gx%q1hV@XD}nbGT&oqI0y`ls7cYk2eb#RRhkc;e?>YXpC9Q#tF!a8hqSbd zHYc6hlj~qldMj4Y&X%T{G_0T}Q((vEW0BY>WR5U{+nyIAgok@Nz`c0}={7J4LLM<5 zDRXxad)m8*E`onQ2nrZ`+T?rRh)utD5xc4nqm6ny#F02sJ(tEc>l@asMu5Pgk@zA4 z4-fpqdV>KzH+C(L75aKO%>$s{qS223bE5h!BIykzb^0{$oiP8#cPW${MH~qV^#}TE z6=ppM&a?b?v)FF`Tu>gxjS2wtn2~O3G_Jn?UKWjPz^U99neeG+gDPX;r+GLbJU83t4`*3M83{qtF)@GLsfk(Oq_upyWnV_ z^}75*!%=ek>u8@N_$cgD9QPRca>IbDNtp0OSatx?EHvP%RJt&iG{b!!01j%9!oz)r zqc6OKL?e8j!wte~)WuSCa5s=&0W@WR0gy5hW8wA>0YHrCJ;#Zjhx8C*M8PWJxDVN9 z;J1LBKW@v)0&H+MP>hF|{CpxVH=x3YDQXfgnGHL|aUWr3BQi(FN1019xJfTR4Ja~f z`BJ>`{CE?Rw}a-GIWUA0rR!+O9QTp^Q_sKAelh zcvu{X@j!gIXMtB9a`WtTXT!w2UqaErao7?On=3O{8Gt^mF#nfSB!SA5&v&> z6{LDrNm`)Fq61+$j{PE>i^P^es*y4fasJSh_SsZ-7VZpzqS#t z%n#$^6?gjRkj=Wo=yLr5auA9OHb-;F_MD8juElIEijUdmrkn4k2`HMLRIs;cyF{ewb-R8d5oKKg7mjR-+Gem2~oX>Dm z=DbM?8FMyiTIyzj4#JJ_EhZ&zjBa%~`4moKWoL;SUnn;BLzhM;cFiF46s80lX~+H8 zJ${gcPyD6fvS^81e7aTYS9@m(vG>kSl%kL6Pcwd5G_$@RCNLS9FLV3UTWWiSmGzc! z`3l=1^P>9-3-lJPzRF}DwBmJ1hyZU$5+eOs64Jv^-+^zlI*BnvR-@yBg> zeHiY!N+*6Q_BgZ#c?q%mnb^UCT8wO&T0avG-!d;9Y4R;o?8yJzC9nOMwo11{Hus-m z(_N=wc153kDW#K~UH<_xyqEGrb9KFp!*t|vX7KJ{!GF7hL6LA_ZjAAj_#6b|W+3q) z602q+@dgq{&qCrkBo3dAs9G#o(E%kMM6RM661=Qj(Fcjkk*FMoguip^mWtz$$i`*b z3Dc3dy~I>oS&0lT7^+AU4}#m`q1e-$0QjVn@u%zp{5kx1L%x+`;D9@Q2qbtC@af=} zcmRn)TuV*-3W;90o0+%?iGC*_!FSP5M53GpEB=Vw706Y*jzq(JB;H5jP9_c_@h2v} zMPlDcNOXnO-PM2w^g)7ALMnzL@iHJ4qmVdmAzD&_#E-{lOKOnG@fX;ZI9afL$XPKD z@I9ce+KTm|&Nc*C_pi4Nz$@Z60GzlAe@Ilm6^M$x$o(0)>SaoP+5~KAKwKklT06Bn zlBQCwFbZ>=iThFZ{y`|e6jkOgg6_5>F=woyEx@|s*10!CGR7#kBQHaShy73<@E<)2mHzL>r@TZ zKhfHA`Z&(ofkxUhA@j5xf9RRU4r?S7P7U9RcdB0r(chR(zhQHVeiK;CjW+M`@xFU? z**Md}3!#nIO&K?VD%@hQPRW82IsTi<#Hl`2OHs1iLaWC^OZL-HEu#&6qesKMS0_;P_y zi!|?dp}czHYbPq6UHCn9?z6J9wJ3|y{nTh!D~AK2)mQ4+Ve>yyQMCC}x1=m-GfIf% zouC7m^t}cfMr~N?I!kW{K1H5n=rj7*&IL~ON6MQ5E>Paz)(k5#)6NQ2H$u1@t9EycdM$CMJg&6q`kzOl;-Yx%^` zXY@^4MTwxImqUZR20E3XWMR)FUIpf`;W$s1$eq+jHZ*uUucyWK3j-2XyRAZ+VIL-^UA^4<< zQ~hCRs5w~f!%Z|+VVmgGzHkT=$e=^R2dPACc$wkq#R{G31EKytr_I`S=u#nF{$%Ha`(0tm7id+K-ZyN`h%T*Od^VQ^sAGf7*!fJkyXuc9vp(hw# zZLmk=P5{IM9)t{{1gOc?PF7aB?1X0`OCx4ESFML;^DbOTF&pv{v+3nTdmtSa{*Y(( zZmG0kjaK|m(*(5PV3BP@skGq@h-^0YNssRRm{VXs;@+2g+>+BJogq813Xf&!V;9Tz zq0-|%=BK0=dz&CN`a8ebOlzDdxg$?ig~W$bA^TJzGw)Ejx`HEnXgwz)Gh4aGK@}W2 z)z2vrXRM?W>Wnqd4l{J<29Um?q?{J!2Bgl+FBHBdtsc&C^apH3`IV-p6Ywd2E|k+` z9uyi5@ghH+pz zeywzT4f3Yr*J;OZ)sA1U9e;4M>G%!O@wbp(I=)#u{v+x5jgmWNrFJ~!!Mj-2Promu zt$`z2t;?29)OM2XWOe~mJ@Zp7Ji`<;<63))7Bm;Oqw{Wcw+W_CX*>*HA6QwAA2J@l zd57y%_g7k4&lO6$1@%=Z{Lw?zXS`sU=&KhgF^%X$DKJgUT9#BwwFySFLWyWZE;M7L za%yi@c)Ag#X(Q8!%v>N#2oHwCU7UL6=KfTAW1q5rDwqbA9Ba+wryieY+=2cY!P~2D zi&#f|74Y)8y%vuT9q_ePIoi8gup3ru@2&?MyalekJ8>T-;X;7SgmImBI?~+D89TXN z?WAQ3Cy1XL$-rrP^+eNG!Cb9wC zAnWZ!sR9{^+buBqp9ft?t&fTDJ5-!Y0=3>g(yH|_8GSixtXj>@*`G5n2ZE2wpnC&( zD&tAvx8w&?G^7vbxD7Gr!`lGw z<~^mPd2S*#O|l6l`7cG3z#K0VHYgTxYCBIdozew!k!3BLC}) zJ1S7jQAnDGzvs~*x(!XOu2wQSkB5Q4^uIHEuEO=$fsu;R=fm&4;_QAc3SFa&J`d#B zJet!XUp4>63fhLkM9xi!KUMW>yiE~z^2Lxq~r5Q4DJ1@04dZAGqVuNGn#&we75fl^xc zcV?yAgwX*l_ScB1*=>o8N5wXV?lzxK!`?(~MwavCiPFjIF~-bOq94m6BRV)!i2NyZyL797@JbU`-1{`q7Vt0|B4GSVYTNuyP!7a!@!KiKhXsoFkBfn=2ZT7y_5AawQTu{vJF24zErP zoGXtPg&Hxr2YxRYI`w|@L6^=1hTt?U@)q>J*AzimkD z{xZwm&i5D88cA6GmhUg0c3M;FRR20u{N0S=X1ktN{SK|(seVWcUNagdW(z_=aNa|h zuCN9(FFMsZQ&N)7H}IgPZB$j5-ck+-9&$E^xG-)txF3RxQ~P*`_Rw^q*GaZv=#o>^ zqB*f2)CTBACC#i3ShKoJ3$PCcj1!r{dqO*hNJR(LFrDffv=oi8+?3+z;<>O>{fL?c zC)5)SQj8mCqM;t!C7587q9a4OwjvPm?!M)*K&O+)&y|^{wOyN z?l==pfLs=M!RHG+V>ScdinZgu=(FStz!uB9Hfb;PIPOdSFMuAg#V!>uo25crfro&> zcY5qp^qtDY!5sq%#)eO0R2NK5%@U&x*z_IogTVARX=;Y!uskvC5qw9kN5KPj$$H<+ej6 zNQbP14o!zlln(il`FZfc+({AA?)V|QAY2V1n?xQ3=I_85FRD7E{a1lO7(A=}hg1M+ zzaLN>8WlL;RWRq+83t^%|F^cZpFb_Ncx)GXJ2Y%ft+kJb5f!0gDeb2fNz;A>_0G0M zVtlbqw9f{K_WL@~r;x7C*e|uM{uL3o2e=IoO|BGuIdk7c@dYXp+;jPHTNu4Qk&8do zKZ5ssisBEwTgtr5)v&OsaXGJl_%%;voAu zvwDln{ZWJ$Z!S6)2hhCZwp-=IY$QMK&d9BmP{g~yJqn`4OGtdk#FI$$Jr9ZdZDKDH z69B1wNtyfyhuVkdU>$1g#puJvzQaHDVdqhn50uSBE6Y_8kz*5Ur5x8XK{+VC$nhv4 zl;eFQYLA(2%=1uk0^V5UqwBP5Rgg7~kYffXh9R6## z0)3te_|s?t`Q$nTFSrFf`0M{ZYXJfLZU3O_44(|Koa&BP`Tk#wcC&o-|0c?f_Reib znEq|fgE}&z-1z;T0rLMW%8g$wW&cm2-1uj_k7{j{8-M$743S9eNc{a@N4aSg-v&)= zT7L4XC5sChmn~dt!qqUeO{D+%42FdniYh$iMAUD zK(>aqiRKOf8_7y&n`j5-BaYCU&^B4~7^%q?$U33I7Ld?3S@T&ShIefvF^Zp~p>47+ za#^h1-Qa#X6781(*#SCau&j2ZyakC|LW6)e!Todd0v#KOgEf9j#Jhj0t$1 zZRXs%N_o3&`qY|3p{p1fWct)8Q)kUcg~v(fP&TWk+6m(1q~n6O#8Odn(g|3&0fBWY zleM9D>-0fm=s{Or>`nI6w+gd5jL zB(V=%es9ntAs?TWuUOcGFUS5>s3H~`go}v%T@X==2x3LVJ{3e(JTnqW>L3gobOdL)uqOu+GY8<9w2 z?FH8fw(=yj)`=FB_urV+Vz>FP0MMD~0=yPpl?}7BuZ44HYA$#!oUllC+H2vxfg<<&4PH^YvCj;Oo5crb4fZnp7B~ZiA%#kCC?J_x_Dc! zg|ke3D~uNGAO)AjGhPe76Vv+|0z)t4;kEF;0lbmm%-6y>B)7&hUJGXnwi#d>uZ2^I zI~1GwS~yGY%D}-RmDj@CL({tzm-bpX3+;>RFwys?`s1JtZ_&iVuZ2?|`{SY4!WV(# z0SmCNg|plT0WkbpI58guePCY;C)b1dsTc0-oC8}J;S%Y%UGB=lm^)r_cq`n#&}k%= zcfwcVXe@5u31@qpc&7%+31{7^rR8G2PQ2|`!YM(_2)V*&o#Hrn zBiv}Z-mQQ@~nRr9<|%G@`q-Q>)wXcqUA*tZXQoH39xp8*LG+m81>15q7R& zUgh+u4Ry)#>dKjL`Rv4)dchfss`Y0O&hyI1oscq)JNM%B{8VIjy4G;2xLPuiu0Oz3 z8@pCU1;Qih4nAlzmanC&oY?J==fEfudkKGgyp2CS`3Hax@XtzN3pu5+yCcuxkbrZD zu4hi{UI95+Uio5l?EVPn$yhviX)X3py>QhpCep<3$Yw5BK&WyoA<_L36q6v}4cz1%PzdITUR`2Ebv_AHoN)7V`g1v;o^Q_C5R9k=gWD z;FmbDKG{^8)AbM3%fRe=kckBSZwfSE#Y6Ov#zju7IQw}NjKp5X-yU>sda`s+mg-5B zW|jnKpld7h20;Y*T8tW8_zvaY!kj?55unJCWR$4HGrvcB_U=4>{KuWabB|1gCP(W&kTm}9Dwbpz@x!H_GPZqYb-6jT{(TMY>9** z{c{BSr(LCVPj)H{0`m-mKn9T*o$^SG-nh}Hx6!>Fh>nO~Qq@piGqt?Bp%%NanNz1! zm8XNTb*ka~>cGpA)&+x@5ftWjf`M>sAZmiK7V%>)5ElU+R;!>1Y;AWLvj~{LeP&_Y zGSq+xWRvK6F&c$X2`?g3tTO^aC2&Rn_0& zhH1E+N*huOh?{|#I-|ktmS+f&Sz|a$9)2qAac z(O>jC+sVV-Ei1A zNvO;&AiVe@SVSq%b#0?lH>?mW;uO%;hv-7VBF+YC0rm^_+FO7c=wA)gGULvtK5*wC zSOgJkup4S4SOifUg9=%Io|P^>+$rM81b5W82mK&^vC5PJ{GW(JEGf*SY5+Xxm>1jLgt zr)vT{5Zw3Hk%BC4%yjm6MX3`Ul+NNl^s(CAYb@lL?<=N3)- zH)uMj!2H%?XzT{VdCSPJ%-^syG<`!OYErZdXb;+`G#@+*kVXJSbVm=`nw`x@AuSr9 z%}J;Bq=V42p7klONtR|SX$b7e6xi{cITBleOs{O1ZbAErk05Q%glL6s*g6#hr>cggd}eErR0mgEelY>fe!)uOdGHj)5*9%TGsSgLfkw`~$+E_XIR#C`J7+LKo-XD0mFJ zIj0wXeP_G5RF>GFq6~!eXF~|I0M~^QKUVN@0AFXoe$zf+`5~~xRUzy{2J1C#G{~ZR z6zDfd1kDI;)%6%aXL{c!^029Q+mvb?$>IX106>3 zG;W0GDl1AYuRb5T6BWdwRKZusiwe4c5I0=UR~1BOnhvDEx1xHgASASz&R2=oeqY=DfMnNf}$N;gZ2 z50H->;`_*wJC0G}+>OzaQ5$Kir$|9mZ#KdWOV_SmnJ&ZSMutU!44116ytBPa>w+7$ zQd++jJ3{wLQ!gaAN>a}8YEzkRj(exz>$FeC;}DrYZp*oSt!3RQmesJ`TGm}s`-8}j zF(Nze-NIz_j|p2pxkSj|f!Aq{m*+~49kVQ!3_`8*V`HtC!@nSHsW{ryiPLZwA3{qTu zk@0EEiK!=ad_n``&H>xMs9a7C?g#bwTqNE^!l_&X^i1HAUx0yk zG45@!@TXdMHw&+hPGmtTGzJuCz%!s(u3Fwtn)%T!U^4zgz#Bj^{?ADKh_s1swVlhV za3=vY&>P<4af)iSiYCAnhJ6eNLy2m65{mQ3{U|!Q4|om&?ndye$|Oi03(W6;nVdu- zIR}3}MQ$9I{OQWf!FjuTO|%yo9SeB39pId>SPEAR6a~SJ%Azy1lobvzP+zW1VK1L& zsKYaxHN)03+nFeQbx04_XjSV0zcB>AJ0(KG+6P5=HU%%9r+V8Ac=-~|98?0_zE7-C z7~2%X_|P^bt_dl;AOycD1Rt$%2v&ZS>Yzqpdpb;N_(q2*kc+D3P^6!*6ig_Ff4Xbd{dEJ0otm!QXy=d2Ks@Z>2eZ`I3v%3>vUwsmN|xF^ z+3ZDKtnSX{Du-KkRb09*%XU9T1tZ1bxJ>9wnai_j30weoNoBJ7ehX3-GpjFivif#( zI+00DMoSRdON#DR{mcvu?(_lHLw!ctbRJBKRXr>8qqMhg?|`5?oIvpNmBDa{PG!;L0^18i``b>j60c$ONi#;9O&#yUF*-?C}o* z*7H)XQRMj)a&^ch|AfR{NR%BwBF7)SO}(zQTKvZtmERpDb}3(HEV@Mzc4-;dmE$CQ7NNmlJ{62RM#w(P=8kpn6)1=6kDm+IYnap6x(zGA>k9#YOfa4oH!cS& zb7qe(BGXrUWS7n`k3a@|`BasE98Q&2H^_;fdu(j1u{I2ppT%xI(KNempSHiVX})vI zKs1O)q3#i}C%|mOl|WSPM_2bBjM`T&X=++{GQ7qwEBP~lC0uU9y?9;FKB!u__wsgKP8J$GTo%S%(p zJ=z4>g;Bcy*3y*jaxG0MPCv=?6uJK1z{B%%8q+fay<8P4<-t(?Q{ODGrHcQirDSz3 zY%mpHi;6jV(R8fqYMzvGjNvQ2H%H-=a_#rjx7#|n#mlsmY~prmhCAXL42$;7pE;LB za=*h*PwH_r%;$uZR1c^C?36NvvlCwo3HA$xQ?MRG{<9(uhNrj94!VXne4WHS%Hvk> z7;kt)n!j|iAQA#1V44)FS3)&y`ktCPhkJiBR{!g@_kUpuLfK%R#Y+0cP(if$T_^%0 z$=kfeDet1)^vAY|z4cp!5|WPznL#Ja52havVUh>KLct`b{X$ElhZC=cIGyl)oCbtB zp?T9gt1bChaMqd9@-}H=f+FsLYHu=#9REq%4}1-8Uy!Ny+vUfcqNQ4dJSJIt6 zgOC5*W3qT?>Q0*}jz*EVm65f3w_M{`Z#Afe&wN6)jF*x-TGjNEpr%r-$?z@<^Oi$1 z>z1rtxT*;k0pu;{6-&(dS)I7FyOn!s;Gz8P7`VhDYn||0i#dA)Z%@Fkc&F%ndourLm@o;Heb{lx$v$ir_hDwic}Yv|Wyx!z*RmuxVHbcF7x)#+$>(06 zwD*g%7MMAK76I>Pw`NP3!w;j`j9L2w3FWw01iu69ie6AM&J5rbo>XmXWa%n6N0%kKjpUgQP*Pc zlZl;7ev`>7gHO@L%BPL-Ve68f+-iFg%^am=sEZR&uN@$jp=LIv;6<|({xs;>_f6X{ z$=F#t^`HVC_p4cZm3F*o78LV3IGM);ugWu)NoZiv^C1yhu?#=U0Mie%4l4CY0n?@t zmg$GW^ygrjII=M{!xV$SGENLs1RGpq5aJJwQ23t!Ut$aFcAeQ}Ax^={VV=gwUq#m`yp6uMJTv-U1}tlp0o&c_L_z0V4!hc?yepFR+GvKYCZicRp9!g|H>$KM`8=d5 zg*kH$pwc?6WK__;vnZ*LXIOVZ(&ke$y`eGamJ?mFgo<-O-B5Df&S1+P%hU*3FicLHc)3Fh$9;E$gtE8%Irg z=TjbB;K2aqg&jH6%RyxyGb)0PMxu}FW$D6UnBWBA@ZV5rx>AF zmioqwhS6lDI}zQx3597c+~wEPXc8Z&FkCP%3$O^cql`JEo-**X9fT@Ita)Q#&3&~L z{Yl2bF?BhKh7h;z&@AAG+J8TYgSO# z0WHPz_3Hv|G*@V;=&y>U!&3$BQz7pA?wOWe96f)>&!oO+gOI*@uyKY1klsfCQG>#wT$8GsdP-n5!`8+C_ z%j4~lGKG6P7Zj~+vr2Enn*UT|c=S$|y0^Bfd(t@D-pNvT`@MF!R_AcIRv<63)CRI# z_a9`T5)RS+;F-{35oND(nIEX(Fu3(*)>|y1>_F8rkt`9_e}^n5j+3Q$^&NKNSf+y2 zC7x539AB@aUB*5*zSd!U9Z)Ro>Z=fz0Y#mnFBMB0wsvKAAv`iNj)GoXTCx@%LbP4{ zR5Qwl22HpiXhO6dC+@Q#Wqt5Yf}7QjFEhB)>O(IZ0LZr!-1-@O-^0yr$F~gJxw>2D zT@X{X*-O zxea-lXx$_y+PKaqvj2TpD~n@*xI^2GLQS&&&Ak%|UJRIvgp*jRWdFnzH3c+KpgYM) zT&ZBrT$d;~bi2paBs14bI{x+SL!1H5inl8dPTDsc9`X$Jz5j=|_W-Y}IR1wBoO8>$ zk}S#gl_hs!%W}76EL<^ImSjsJG)1TJ8&g%cY&W0s_z*pR2uoSHboxss9yG|?oOxL9C^>9`qHO*BAu!|GGvK~ai2TD zzNF1iP#bL~P|QDWc#ASxR|r{SkSBV`Z6Rd4LF)Mw)Ywin$izWPecK?VSg7N6ZYbon z2HEGaeZwG=2zjqT_PVO%69Z=xe8Gbw&>HI0jWyX!?XV9G@+72gVhHY{JefMyx|tz( zp@E+O_*?@Yi^%60I2SVqhUn`JybqIt8UvpK`qGslkJ-pFx>jBbpPSKQXfpk3HmuUC zW^<)=SD;v=be!k?4&`bP{sc!`d0?Hla_~tr8u?*ri^{?UWAUI%I0enTCwL z$8q4p8i(YR?l5qvDVKyiCD#}a>n^S8AcWJq2dr)mAs+D%*gY$`Cxm#-LtqA4@`ypO z`hMmiuq9RUOen-)h%Ip-?W^842Hq(ES#0KKI3`>P+huIgGmjcW;B`R$yIIGZvWRWpiy)-dPc#le|Sb+(`qn(?%@6-k};P(EaW<`9lua12c&&IWLqyzl7WnD_o^LI?16v zFNaF6Goje}O7?_2f6*+YDSm0-Y;rNg3f6?L%J0^NNqEV$kY}1Ea(W*_ja?K%l(ZNR zOL2>)`dTT^Fj8`;7rm2`%_cOZ{Z1fAd7pt_YhY+7B`1WUy*Hqpb*6!vGX%2}v>)mQ zb?6V1bAt_S8(aH3#CI?+h7Hby>xexuoD<;R ze$PV5bzo;&nV+ott(KF4;eVo{WetA#Z{G+V+O{?&pR5P0mN@|OKT+NCQWUcj{3n*S zEO4>D$A4nk5qHONsD*#GD0;-1_~pMlA=>gB0`Why>4+|X_;0^&wLASAo!nH-f|D3 z;D5&9E!X0Q|A`eX`vS@Tj8JZvbl0a{mQl4S=$7w1r~wT z`zl+0OO?alhEf%g-+3y^-}1F8#@~vvm6a+^*Af^*Qm(+N8|%wfmRG3+ecH4_hLF_3 zUQ;Grkfpk;cBRUqr>S;%ZQbfxHHe;y%JS+JWi=|Bp6XdDS18~ZtR4HRA=*)@h6>3% zmDGTFDo+4lJ4{31%BO2pU3G;jpbOd2h8XdnBj{)>TZ${R4P|T9NP5e)dlcPG zjg<`*l}oE@k%yxRsHtZ<$7ttjy2sMpP+4BrP=N;#;fC!f;XQ$#CeK$)-_mMWpx~Y7 z#q=$ysavAT=rV?+mS}ffL)o%QXp#B|+Mrl+P-Xc_RpC(tph|+s%A;9IK>1R&Onz$` zk@zY)S5-DNR@WgVUUb!QhD6+2lCN^;UxjGu8nAmzkIo5ID1>VpDwpEWpKfGhWdpCo zt5fK$h8c`yD73G>3i(!)H7*B*=1P-Y1i-6Ym(OP=e#S~^MtWl=CCNHGCh`FQ&Esn%%r44 zQ_Q5KBI{OG!N|wuC#y_!t)1&zd)w9@-L34Sn7htM^!i!N&ArFX0%Q})K|E;fz6bZA zRKE)}J&P;YLBW98+JPP0E6C65iLs?4f7UJwV@bA8!x%a+A;d!vv<7x}lj;~f zTV0F)DjZsN=sZc>4)1W(66({KAA7EvIFbXzJIVj$dBC>L_5Z~j;1p9RuOjdGcRPgk z<^cbHjQWmiqj3HojQyzwAS3-yV5R{`2hY8Mf7k$|;AYJsviLnD@qae>7eu ztvK4Y&4guV`Boh5s6cYEQmr`Ju7Gp1_F~1+&J^5W<>e@hRP^<9bx>!szgxNX2ImIk z=Afnoa^^@!a&pj5vHGx&5sx+K4SM<<$+|&*qi3slB7))iJpRnN?pD_;^{gkkXu~69E4)dGQf7W52-_1owt<6J5KYtP%61hG= zTY`yx@eo25W(DRUqn1U&Ndd@E+7?OYWo_>2>+a~^1Y<_Mm^=&d;xN#V$Ar8-Yk+yk zXqJRoGXP@(4w8VIv%=;fqq)`*5UQKN&>2N^uyrxOTM14v4;dXI9mOeG=GYh`)ln*% zC!EjFK%-jG)2!{1sAz%3Ox$j;<~F&JX_SP#I1NYpMJhVl+8;T6mB9t(A)|#7Xm^%r zf7)V7w8&yF@>rH{9x^&b^5dy2Z{sIA)w%>6U-tlF9x^&j!tL>azIn*#biusmmw}jv zjFt%34+jUPg}lxT#Wq`z${H-Uc%uu&3;U2>1=k|0mT0wAkJ_50^RGq{q_T{C$mj~m zF*l29C(%0VN(hbi6WE809xQFS05S*mA)^ff9G(@j4;gK=zK_6#URL3B2}V*N=SrcS zl(iT8kkKZ=P0rF*5u>ZDKSI)JSvo~)Bt<1zDFz~=Yc0-57JJczdc^3V(yLcw`354R zhe_(zWO?QoqeoazBQy*|((P01b;`FTc20&nS)^akRFhPnn>`lLZpmp-XTZ|Rc? z4K01r5&qIA6`_|tsW5-(lL`)&KB;iM^ht&JLv$sUKB*{g>5~pkS^A_R{iV+UYl5DI zNGa)t$hFV|_R7kiasX5>UUEAR?0-7@4rcv`Iw0<11;sHJ5& zzrzbq)wN6Of=(}hS5z)(f+0J<81?8K7<#lz<0nEm$2}F_JWf-FF&~E=&kwUIJ!EKJ zV=s>1Eny#ESWd@uSP7QT5w2Mb1?5Ipd=6x;m|Kk2(hYNPoHS~Wi|83TUzY2fu86tC z*f`Euay^4Nv0~C7U{{|Q(V+pe*hIo|RU{Nr#U|Sb7iTh>;V9th%ToC|g$_x&i7>xuAz76AsCFjHJdtKYJe^5SjgA+9_WW1l6w zou_;u&K4omxL$0n_~k{Ts@4Q=`(y!9$3JV=5jfEtPuZ;r6#a+Twko=b-idjT<`3{r z7=^B?6J!ae`vSd#RD8SHhPiVDZnN`5b0RcKN+;4%kw-I;mWo=;rWI-yb^wKo)T~^U z&4|-P^cCI17lNkmHgO#%5>w_LoKUkHHTT2I8faa`ws9K0Y=72O#q{>AtV5ZXx0(oQu$9I? zYuCpGUU?tN?q%9T@Uq9V4r7ORHoffhwD)0p+3#70vD^Cs-f8Umv=`+)UB5MTI4cJV zd>Z>g>u}Pdyme(bTvvv9y7Ze_`uqJHZA@xa3j=-+UR@blb!E6wD#JQ@?1xQdhz@6E z*zQ#ZjvV9qbgq8L%5Zc|K1%dcfFDJWl6T?wf{xeVD8$D3tY_hv^(a0i_u^9y&};@Q zbKWjnDD6MaVu0BM z2=VAgNIZw!4=}`6k@&%=aNY>?YyyP%Od*CQNCBie-jKfztkv^8({~)e&w!?+6OK>m zSO-V>qj0Q(ql=D%;P@^b2f%R$9J9%w^xN>g0G~*5xtC5zWq+zA`4>qG0T4;XJVvpR zBY!bfh)v^t$Y7er5W^vX4fF)+6u_|^*Po2b>T2>9gBuCleje^F;?N^Tc07h@kF_R3 zYBl)@L(3+%LetXb)8tnToK37P1TW|hn$n3O_}L-&g(3Le2F@n-h`_yO=GCRtW;Xdb z6M(|Mt{I8Qs`ziADA?j5rf!t1o6;!rRW{p~*C^9^;4fIA)v;Rs8O&V#S-W0BXx#&U z!5+8_8LxZbFWGM%2k%_n%D!Y{`3cd|1%F9)@4>6P;4f3U;IB*SFi z{zY`rA)w{I{YZ4tZv67!ek^)Gsy>ao+d44yaW+NswGnkVs>=VS%8c1j{x43;T1*CS zit5UG$7m$bytejVoR-NGWZiwZz^0t#=#+6@74O}Q&C0_5PV=l8suoVkqUNWgt8-JK zcE?jm+;}gJCiU7n5*NBu0?YON@>JUYeEOB9G$X?5x77|owM;o$6Pz5aMT)T`QxP|6 zj?ALxS&sn_V~{=gkI%Yn-m4LDmsYgRG+h#o33IAv)78OWNBK2q}<_b7Bv6rKvSf=0xtBgmn z)fv0lS&F>Nq`MHWdi@mD6Pvp{wy{4M#$41s|5Y!-BIe{kj&1CJ&cQsy&GL_J?9cDS z-d?T`&<7Is7r#Qt!bEUvV_OypCj}rwXJh``yz+761;vL-bIGp5WVCZB9--&MEKao&J)gO zXkhxWja^_d6So^|%CU_-N0c*o;3R9pRsnq$2bwNh-`gB}oPQyZKvF;rf&$ z6_#>Jl8W+9Nz$PyrzELJ|CGeb-Sv1~V_kbkd*3z{kwX3?au~WHFN@2|>hbJHBNQX+ z%a&BvR8w6v9ap6v&QaD7Qw(09D(K{y+)YKIi0koWRU=eBSC*AmH7~DhsI9DNuHaic z4GQ)^J?TQ5*dkm`lzpTpK(N7F3*E-O!ObT2zySUx_CS>0#2yIuHnF2-K9IhN9V?CJ zqdOVuj>b31PCJivHt$FLa9*L(LWX+z*y4Djgk8(9?S9ylVE(8C&2?(Jo94#ZF~xUzw|yp}JZ7ZZ<0RBT;*J2)El?eV1?V@*kW z?Dzg=(!ZrLZzg$p;zcQ=nTj0~{{V5OBdM$}DaY$zv2)|!h9pDXbMVb)2HXHgo_uI` zDvxsNd>`s^mNwMo6r&(?B4DrhBWSYZM8K}4TV3bErj7-o4V z0`X!QXR^X40`ZB2r9HqDpZqp}F-p1=42E-ZX{iG5M8GZQhzRWr=R3v3yak#N|vbn4x}0RD8dycmbF935wDU*HKXBFPo9HF)NqJ2NB)UA zor|LwDA7=gFr%d?yt;C9Yv20KvZs9!qqTkxiZQa!dl8d92263mhaAT;E^8;_8aoKm zSQnEP`A4A&rAnCBAoh?4PF`TVz&>57ghulculKY>0k&d1niEMgMn6SylF;unhY>ts zeS=gY%@ct%PXy9DNomG)Llck2f=u~ZPctRse0!kJkjwby=A})wUUD zJ+m=}&0c{?g&MAkP6vL1>7%@y+R)b1wh40v8l5w3NLi(pJQ%C(%$Lf{W+Kbj+Ru_g zmW-M!xoYwVnV_JWRe-GkFa3R?^otwYZ;;AcbRGra_-F098iA%<1XSWza9j;X6CF3g zaWx%3h2woVrq+{?zWI+Ed=DKA@gq9O<4riGJ!}@X!HqL)fbjZ0w?h!8v6W_2u%xmm z>&~Z4sGo~ml}bs@YZQhk2P0(%4AS&}n%vkFcB4R(s8 z&#=UQ3;klL^&S>v<`dYC`z7e=x3nC^2v0%ctcR-+GUJ1M^{lbVe0y_$=K$$yS zr87;S34m`4!514iGx}Ns*Y}~d8B1Q@UCTZ0(&dJdoVjCaIPceK;3a_1IX@H)2%^|s z8efmyJ67|n3@!tS;h(kZKfPzS1`hTgv!j1TZp|?z2s22W9+K z0G~6*z**vQE!wb%2`o3Rv#^J0(H?%)%_8 zv@8yC)>~{@ZSc-CW-8y}K=d&29KEbP-d+!8 zIJr20W0dta$0&QpyaS|Xdxs)8J9e|pZV7dT?@a>yw}@b|xgy#Qo%{D0E6%Q3^m%6) zO*}LnXWB9H+Zt+(#Cg(`OjP3b=i&Gg1iywu&A%1s2Z39HyAQ)1i_7D9X zw*1k{Kr?@YHAAGj{^Zh|40}GH)r0UXII$t?V541?zGBd9_!oxIxF63JkK6F29~zRA z!QnE8{Q)&FA;Olu2ny(*n=__Jyag4kr% zhaK2n183DTFb+^CprP($h&$9}XIhameuqXS3`)vcVbvQkw@7P17Vr8Jaa2m@yh28( zYUJBe>3?fwWO@+(CAtIFfQ%QETE;H-e8UT+BY#$-^&pr@zq=7cshTd+5C?$tv(q){Esg?D7Z0V z4U0B)_9M{rjh$W7yN+(}o4&E9_2{Bw>%eyRU> zTiR(B3t4kYv7;S1{%r(x^dkl;a#krjjmZD)wspjHR`Y6L^qfrab1Jmw+-_kW+1Sz5 z3gsi5ET9b2_ODYmtm8FxP`8Q|Sd%~*H+$8w^Q?>Djk@m;*hCUd_NK*La9wQB&bQHj z)pTvCZ^gCZSj_$&NL9ugtV?n6L`avgTT|#V!gQI2F0;9*rmSIEC2u%ZF2f?-jYaIs z5H4#lK7;yIEK8yrbZ~#`1|45Et{EUc$d(c?mLu_nw)Ar&QkomO`q$xdS$1$!(v7~F ziSnpzf+NcDFIq<5cpS22H#e?rTv@q-TQRuV zIO{fY+_DyL9I5!eH0cH33MkfWR`J>N+Bt}7TiwRhZEZ)Xcqu^<0jcx%6k`Y-wzhP1E>1`m>1dzyd>nQ0JOYXtr`fLd6%1giP72e8;wS zphz-4qKtjV;?Bf+EQVO@;>G4K{DbI6I(d6YDsN&6OI*TZw{E@4%{Zhq5-`X(bg9Rn zlMFHrBLf#V^#a{EXGJSR$V%9$rCa4lr>Z?J>KR#P2P@%jTveC0kN5pX|A>LfPGycE z9i+tonmLvwlAEKK^qGaMsRdykeOOIrj{6e>d#mZpVjVubn$Da^SlVhjb22044UP8Z zqmlnx^^UYPe;>qR&A@_q@XM&^*8G3KKLi@`uo2pp6GO3q_P9O6qDa$_XHl$odI;T6=gh)@9?92Ny6n#i{7o4Y0K#(EEK+G9rG6Z@z#<8!m&Jfp((wn8{I> zmkozCSF=awW_R0$%B|>CJMr*@ePD#O!r}9Z`72v{pjk$kcvrP{^!pUxLhIuNq}I73 z7M7eY=OTc;?CFv;4-b`&w!<`*!g@VF7AW#(?fM)+M@YKIGTrB3bRLO4Y9y+Vs&Nxv z#ANX!GhU3QrrBuPE*h;3wS{BBW;ZnCV0UmLBdR|^PkQS8i1x?+wT@^aBRUg|RX9AB z{c;Lm&0zSeO!!0m@U)z&!_Q#&FA;u>SGQ&|*XOdSCu&)$eO@nv zS78zr(@+X+7 zFVh`P9@VPb*PE77#U$Qp0v@TuVZwC<80#cf(OCy3F^m zni#glgk9!`<%N?G(zKe`v{oamsaLC5ueQTqbSx0Zn2;zD`LotGBV^$jK>d>OO(4-$ zLj)l-(IGyp_g4Rtn;9$ z3vA4*CgS-s|6qaXQPgm;(Tm?smbChJ0p~GrH z{;XZc_!1pOi5>yFF&p`es@25+3t#gj?52c0@P_$oL+;AjM%vd6^Pmjw_nB`a^Xq+P zCz9D4Y0PxTcr#g*oT3x^1GxET?JB~oUgzA+WHsh>ucqG2#&{jP6WQ?|WCAW`F5NQe zd4NtXd>r2yZy>{V!*M4ZlZoDkx6BXt16Bne!J+oS&Z@c;-hC2q{E?2Ka18&W$^UN} z&Zm&`<)>nuDfxdh@T!Po$EAi~H~{>!uDFdv#{%^lD@*68YgIkjTH4&h7^@NW{ob@z`BU>Z#WnO00Y2?<~?WV;&(L zv+8X+m~&ZwLidtRKaJTojafF0IW~>CHH|riCCyzX3)pR41HR}9XpU|AR|ft7s^cL^bn417}MhOb;}= z>yakPadm^PYPU(PH36=~e35_Fu66{~RqZxbwOPmo-6{TBw9M!s=6IZ?kHl{}d?%-tkP7sah!{{n24{S#M98@n7D3+lmq`)qG3oy(j zaL}%U3-tGddX&wb=pKIRAn7~z0DQE}GVx$0N1;CeQo;s*FK4^7$2*=4RBveDe!`~O%>Pz$7E7S+jt(neOS=@z5@pf`y@J8;J4GkLjM8|>7MdW)%**w zwPam>4YnGjhMxQ`vQ%p5Ohe$+JL`(4NW>a?4Tz+9{DRcNuG3K0lihWH_1Nw4*`1fp z?gwMB*cW!0?-_P8;LwqmeoIT24*>tHOILW*2Yb|gq@LPtC_ORdz9pN-PSUY?+yjT? z-MDnxf7dh)GV-!%{0wokZeqV-MzeuGEwF=WziaxD2FAMmc0fBl$H>NJ6vIDw1kGrw zK~6G=0nKP;qoGJ?8Z+XiVl?P*Y%rse2BsSj8|tyZM%^xa_hq%4EwejbL6Di|Z`qJe zG3>J>hmps-O53`-a7d$T@#q^Fn5&!pg3S<^)!Hw02L#5r)P1A5$eA?ue|<-T=W+iZ zwllVylvkNbGpGnlNuy=wP~DAsbK@~r`!|~$POnEe-9cvBZrWbQf4sF3ai=i+|Mdn& zXptT<`xSQTYCUb=BBXcMM+w3vEd)1vU+%U{DhD#kIw1?*XvPq9jxn>~jb_aPR=l#{ zjSiweqT;TzgjS?tr!sMRXC-z{l5V}T5<9nSgUf~!|jIw%v{>h-g%UA zj}V{AT%x_r;&l;nyYLPIx-B+A8O;qVYnsa&s#jK*m(?^k!tN5!_OymUiF?@S=g>ql zS8juC0{8IIg$SWC%dyec*VVHG2mdR3TGzK#i=7$w2tnIGw_|GG+R%2^IGqky%Jo(5Q9W;qQhbkZJ(L97!*5mL%q zlJ0u(PTIRP+>cT229ao5W+QcRk!<_|Yu3Tw&1Ic64hubXAd^CkVIz z(zSa@JaKeA(~ja|wkPWUP1(2`M_&%HBJL{)k=Prda!-=di&j<_4T}0K zD$gr2H41OqQ1TonQz&lJT zkz^(W0L?d#KsT4s=f*ZyQU^gLbPg&f#4a(0(K>YKMCeU`HCz!Gf;Y?B%Dc64gc{_SM<+wrg_~z~Cp?N!@ zpm{s(fO$LZfO$J1fq6R(fO$Isz^L6Y4S_44E^Xe9F5kQzJ!0ODj*xjfdOh=Ybf=iN zBfyxq(@t&Pj&9Gq9o^Xc)#mN!3C!Ek=kK~Mrcax?s*(SsAHl16DNU2Sb3+^DS$MEGiJ15sLSZ6G|Pw&q`j&R%g6Vn$shr}7s_UnJ(KC*>@qKZfw%LVygJ zA^O)$>a)+XPRl@xrlMlzk4~i)23^sP$_2xdJc9wBJ&<66cv zDW-SynP*lVN0bs(un3{8_9Q$Gwd#h?5kG|-@eU%`4KGR5$cOQvZ&V|22{oG3W4>;$ znbRyMidDkcV6R!c{$8`p0V8fEXbS1xrx^1>Sg77b9y50l233?e;{0{>&el?M6l;*Buv02{Q-AyZe z&z78~*O04qJc#HWFqp&=vYurLodM>P*BPn{u!i}qjsPl24Qk4 z_Eo08mnxF%mCUfg+&aSf0Yc5(yu7Wav#nz`&J|kzg&|vto$6U6(#1}n6nl;u%`he0 z>=*0eG>>3i_MwSm4sxG=FsqIgEeqsw7RYyzj9I?`w=WFcDO~VhIXoL{#ZLgf6Zn1K zg5xDP)NE4D{I)I!e=qjNWgd0x14BIp4mF!uw!~2TJD%5m4C>N!@P222b`?U+xde`c zbJb3*_)%16!e56_$liogbfLzmqRj^NprG*1?Q{<{{Vs#L9RJrxK$G=B7Qa?v@YnlUd=r-1%;Gng#pfVZlEqbq z?p9{;A5TCulEt?IFIoIsIMgh585w8j7+)vlyQ9Eu-cEq$(?91LxDw78CW99I%FrSc z4QnKAfpVpBcm!jbKI>S%xidq%*U7t5i|BfnDjruqR$)VC-nr{xZvkC`@=MAhrfGzyk!0tocp6;Hdxl($mQb@#NNrdT)*mW+p{)B$5(2zcZ zA%K6@uG*p4?&JUk3XU72|Av&cuIDPV8CQ0&`?*-sa}D5S9I)W$h&B8pG(`?t@N?9n z1{V^)M2NQoS-yqQmP@qGj#Ez7nNcB`q5cl-A&xjlAohf_)l|KOcNy^{f9$h$vZ_!= znJjFs73CS&VF7H~Bm-meY0aOsC!#OC)WBI6Z_sevY;}F~B9;1hy;mO>-ef{CXN$(1 zqeXZ;h_3Qm1{T3aY^?IUu&?MI;~R-&vDZEUUtFukMQg-j@2Hx9`@E0=w|UWT>#Mxe z-!NfPnvCvQQba7d$aGV>n`X{QH=V6UvkaGt&bDW;_EgI{4ZvkGz@I8*qO_8e41+8g zs4kqVQ&;O(h6kV^wn)nDVvFu$P)-L5k4uF|*2mC?S`WtinV^MmTi00M1MR+B;oeLF zb~qlvDJ1x|brA{JF< z$*~eh&vtR6`0jvDw~L$nc2V?@;ZcH+UOj)xz$!wpQQNh&YXaE9?;DtiX0)0~H~NRA(Z67%d_<%?=u=P1M*}Hm?9j14AH-fX-@x7pU<=PQFiKSX zs_~d)sr`fbS4hfNC6>bP>IgXF)LHpsN-16FtI}(n0=bx%uZxt?&pavL2&6pEFgXE1 zy}Z1{z_y2ArRVF&z8An2b{d%ErS3nuWWqay65lBXeLuF9w0tXZ)Q6(R0PuyyCDlSm zvovTU29)rPNt>s)6R4XL3W zo9l(E5z7Ih{T>lNML0+{)b$HHN7{e5Navz-<;;zQv)Odz)9y3b#hGj#8Z}D8?YFYN z!rutaTj!~1Plib5c_b2scAn6As+J(B{5Z0U{Y)&vATXCEezw$!iR0S z%DNzu_)31w| z)LWzqEjC0?>uQQFDLKM)Nt$4*WtmQWn*{g^{L7)8bDa22o_1I$mS1QgWNowXn+Cz| zvgirp`A}12^(yD}>DmnXIJIz(!Lq2Pe;8tjOp6?wbpe(hTJ$a0>4xa%+8Ak6;l(AMz&p*UP3iAioBS9LG!CcO=AV@Jsca0!|5MjW^R+ zVxnTjD!STu?n6dFz_hg7=V4jx{$)IG?TvK$L6_(Rqzpn_p#?F^bmOzsv7EBWSe~Iq zGsQY41=U5#Ha^^P4nY#heWBE@c z#LOt0Hx9QYg0tb1d?Me3Q)Tk$AbHgGIr~);|H5;OL-OrD<9P=%bGic!r=l+m%mtr; zc{%FRpb1Yq)OeU%%QbnpNq90yj!iHEsp&U_LLmYjLg#Txh#-$;_o9XyP_2EP0Ge=KZ_~|ZB=1iw3K7c6 z5IZKys-LbYO+#DJ4s*B|qIl(uhY42WpCNF2>>JfoJf{^=Cyd7i*8i?Xy3s_3rG$0=g*N)@riyI-zBCrK zV=~q!X~(yb@h<}T^*ZYQ@oi)}t@;c&zICAZsST(^4j@5_>N;6FTd3pC1JZRI>Hp*7 z-c(I?Va+K78J$IgU=jD{;2v?;lIeeYC>(KLXRvgWEYT+cjk)?*6$Zg?hu5i>Lsk_X zZlm5r+_wm8Dz7SQP|;DO2Z8pD9xntgz786Ioa;tUrhNL0H+rhL>owxr2MhINQZHGH zUDoK?!p$hxGp~H*ddgvYht*EKCg1*DVX&GEY7A@#VNShK%HMgrQ1IPWP#ECF1UfwD zP|+)?x1Dy{opQV#aYZKoR3tW2iqt=bj+IEk1jo>^SwbLj$*D^0fqYC9&AD{^pMOGx zamg-R?`8q&djRnQtA&`=8dZpEoXqPM1dX`I;TxqhUQ=H#XE^amRv-QKntYjcxezXu z?+@{f(g`#UOAyMsmOgU;9zV|#A-uDt_%5rFXr@UH%;SF)D^H>82k|#8rpk5WA6ert zWGBwW5E%cv#f()6UQLaEEKGRyApWVf)Tj9@O!E&zgH!jE%L8uwZ`N@LlKCa%$m&<| ze@ZNa+ORVd|J-^RP>7cjB>sg&g4m+=?S5=AJ0wwDJR(uTe!-{72-9R5nv4M#A>t8x z5c<%}?FdMbvLqTUQnvk`h?I5*BAz4BWH&Es!V68g?$D#aAO}|&T4yOY$ttXU`zkk& zwL2oX*~%S8Urcw zLp1jg@u1FV@8J&#*>(7aR6tTSKhV5^9un6E9-8Har}(D{W@|1#Sva*7fozq_DmKdV zQ;hil3~jD!GzWJ)yDC!`#GfB^7N`elHU6@AauZXq{}}(hFiYy#FZE(SS;f<$jlVK#9I$EPRIVvgyW;PSIuAO*TA=rZ zxk`vYe-V!n=mYT>fj$(E5$LbtF#`Qf3zWnSksjW5uZJqfiq<2$aF^txQR|Uq7o?)v zJBj+cpe_QcAM@T7t-ZLF^0B}!PHr)loJ3P3{>dnIaF-^xG_=7=(6Lza#Xl9$Woc<< z+Tx#$x(%szR_jNzqSt+ju&6EagjVziaTHLtubw~^hUimoA}jK~K-NZ|V($!cp8%kb zfyF?BZ+6x4%C!>Y>3rL5>hL4Z@yr(t0b)c*ptuk8?ho)M&8|Je$%0oQ+|UJShc zLvZT#pLqzKUA4Nlg2E(*Qwd#!NeuUd0Zt``-zvgTr9B%82=d?!4F0VBJpegdRpJnK zdMam|N*qcT;?N|C!|nvdFgGJViKTpwQP0RI(DG@os8M7L*Rtii8N+6QH1lnQEAZ4a zGDfmBAmJh1iNXwdEFs5N&&Wt}Y*0Qx^UWjB9nR=;bBuaM#_0P1EJ#t$$QZ+DQM#ch zGRFJ>u!u{{P$YXr<1$r}`CTWUbI#3MVD>5Ve1}=4lAbk!%nO`fB9mRzyH?x|gldNK z0~A?qvcvc-~S2D>iV^1mF z6~z!&%KcQ)uaE7&WTf3Qz;{AP6dZsWNkSh97A)Keuc0wDu;P+lx)WM z>M3MBSlJg~NE{8#0i&Kmr&dp)i|Q%z3-uKKQawd}p`OBDs;BT*tEbSV)l&rKtEbRs z)Ki2+)Klp4)l=y4)l=y4)l=x9dWuj`Jw-d9o}wL4PZ1KRr)U7wQv^Wu6b+$z3SC+~ zg)VOjF`OPzPoX2Eov>m%2e zq@F@=pq>))`RXZzh1FByRTY)1L{DVMc1sVzjrAyafw4xFslp-OwP=7L5y!AQS|Boj3lfQMXUu}3OU@pQgJc3R)(Ot5}0 z2wHcDxI_kI6Oi3O7VtBOuDa;7-p@iVb2OV+FYjGAvak2Vc687|Hz1r43s$lE}jm# z(c)|gDz1A?ehRZ8H(76ey?p7UXCYcl)DR$aJ#^^W2Lbl_(xHc(glTrQ_3r*J(m$|yz!#^{V* z4TNfPNKsG3)0Z4>xtgKNb9zvKk)*(biWewg| zp5>R8DWq_X+hJY5my(hvBB?-KQ3eYN0}4{VAX!s}{4Vrj_3~SAt5D~W*^Bpz^heQ_ z0fON*%=Yef>N)Frbgi`zN0kAW^6L6(Tmta=sJ&o?c@6IQBu|BxtMKs*D(d7ld? zgHq}7PUU?ipsZx7f#E#cW@56FzJcMqs6cX(sRoAgTmk1M*VXnPjoS(v+c)+1;8t@N zuEXVJ3U08UgF&C!*1Nu^y&Lx@RAJswyAgN5bROnO2$P2+#DhGn?A#!RPs+^OdU=I{ zu@g(M|ByFXJWg^8-b&^gzOAnj_j^>{G@DtD%#~RQZ?@#k6jJ0~LmT$adpE1R*#e0t z*EQl{md$TsOxT%Z)riMR#IawJS0^4ju`fLh;&Bq|F@WT)5>F(tjGndPi6$L_m}E0(3l3YR-kA5ydBRD0rZFI!F%aZR?IB_1oW zgE?`ol%1WplQC}>OeAp(lX$*(qKV_Mp3A#PJTYAlE)h>WaTxRHO7WobdxfL&u9cYm z{P;mQKW^~zV>+aZjzdZ!?mRlVgoVjL|G^*qtf~F+-8eDJ@$6&E{)P7W_OS_zXk#1A z#y<9w<1v%V!AS_R1eT`k&+7ol^#NLi*8YMU28GEK``9F$6o3q+ZIN_da&zceQ`pBQ z@!~MhkjI3)KDjsh*bK8~0LBCyBmp-kp*{oK8+gQe{W=Bv*e{HOeQW|lmQ(G)))27T zN-zw7rP#;j=JhE_t*UM~=LzRCG;lBWv6+e64VJ1AZ9Tmv;Xp*#i-K7049tN?=U~_ro-K@<#P zb9Aprh7DpfIct(3gV>j16X!5B?q?ixf91S_tQb#siM`2U^Pda~wOx}DY z?IqJxu-NEM1!)`IsW5G$I~C^H==N3;#zr^g%o`J_z^z@M-m}qNWY%7?EhR6Rra{bk zxZZ(2DHZA2=uU-(Y;>n1d>h@V2yLS~73SOMP6czTbSblFYbspZ=uU;nl#fdn+^jn` z73JCJPKRQ~tc_qJNM9<_x6$q8uGeat&9j(#X4()bDh%@3Un+%OGWE*9$C-OY1K^>T zOb6gXFPRR&VSbL6Z~e8lA5Ty){*v3r`S}|2>#v_aeL+VjuRHSS-jbL4lIZ}6QeHCM zJJyqAFLDoj$<&)!1lN_qvx}^}OCovuV0JNz(}v4LaFy82X~Pxbi6jnXuW_|B30K9< zxb7zyBNj|n=G_vR4K6qq!*@ajKE?b1a1eex5xhWZao$fO6EPGfHgnc>x40FCQeM!_ zyD!52(agvmh;Xwek(4`3c@K#%BXJjlJtFdDY5ATM`EqqKo{6v-Cv`G@C!T^NbvQR5stKz66Y`%-iZ7a`$Z**_v!hQ1fQ2o%RZI2Co&x=*dIyc(2~od z-X8$HCGXYy&^0>g+j63u0eGdFevNJ*JgvG10sL!p1H=jh2 z(Z<^BTDp}s)}}q28FMTT8Ed1VwPE8pN69gh8a1q#Gzb`a$aL65nFA z-vnVU6Z0Aza-?giY@G_6L6>u)k^@zv{0h=2Jp=7k`ISt1B*(iNn7@>MUJWFhh`R`r z-H6Ls#zd)#_Eu{nIE`*`kZQaVc+UoLDFz(#dh&4Y;4HZfKmQin? zW#vymjc4Vv&z5l$?PFe zqnd-B+0r@VW9l05Fhgwx4xNOEJ9~B-iRrqzOBzW-neEPs>PFrNFKfUkcZ(=cb{mYw?-@9yni#%@-*zU#ejAS)7J3!>kdyLY<-}orxutbP)N|ev70RK@+H= zZZ#g8s8lEUo~GK0%B9t{5b)&D9zj!WFnB5-x~5(o?0fbtDVePreD5mQU?@{9zJIQ2 z_1*K-y1?B$s~Hci*OcM#L9O?}E6UcW4QiBs9h3!@e~>#7<>g-orAuE2rOUexI{5@t z#r%VZf^-Vo$2d5O`9bApeb3f<_a*s_rvfPLXr;8Hyk{_SNZ-LnP0&&fx8FSbIA|dF$YN<@?~9f$tiffv&4$BeG7KQv^Xy^}a)nIaf%Y3X^DRiqtG0UYOE=Lz zy9Q*1{_2K(kFvilRDf>0&&!BuEX>4|zJL$F+$(YWyvjKa3Ir3h5ery#gdt`)>>|u4m zLn(zSFS zz)D}tg)$l^TZ(iHi#=d5UBE2GPsIHWT3W=N=25khiXQ;E5`}pUcqXv2d*Gwt7LKgq z#cZv`oRJlOm!osUJ;_6}Zimp11MAUT?$NMoygC3!a+zb(l*F?z3BknsM zB`ds$>P40WK;&h8*BI#lBkl|j!zvzNWMT!DRUVp^UZXkP1!j|nVO7@{b~{>r!~7c_ z4J*E;k!&*P?*lr4HB?dso)5zvaoLYgV6F4|@R#8h=~?HbP>VSsD&`2`3HqK#Q$!j@ zP)rxtZHH75Hy0j`1GJz`z2)ZC?smUFy~;V}{23S-aQN=@(53PYMq77!*{!-crlqp4 z)e{=0?_v<;=HQ}E2#32C{R~`?qs_G*`(tR4$3*6?y5X?NzMri;I7YOU*()g_?kTSPR>bd;cm%e z=j5EsST^TPqx+Ozz`OIV#(3v^gYK<)4`NHz`6k_`oIh^amjU_@Kdxr|5{(@sOyv~_NRN`$kE5xL4!9H6)Z z&kmit-ht4g`OX*)|KxPnoXlG(z-mmBF*^>^)i+>i0i7)zHhW;6TAJXA6rcppNCEl5 zGt)$rR{*um5Ox91gKKB`5>jVCpQKmU)?>cz2^qjKizmVpH9+_$&#F+DoE#0xFj(j~ zk1pI7J;br>A|7MDVR1!*Vvlnniz4TWYW;i7Uv#6o6+q&Qr_5f5bHHHP;rM zr&|ehRPH>C7$or2hpAyloc7E2WT^3h<1s!Idisq^%&BbnG~M|vcX)?Qa$flgv^luX zgUa>lIUFZ)(9Nz>&TB-tc~@j1mtJS*EPZFFpL>JqGRZuiaXEj;n9X!xpBgDy&sF5c z{!UCFyI@U)^JeFd6uuCREegVD33_&13_$oouYWfa2r0VysPo)gpum zDwA^l{3+ehX%H>kCpd30drP9z2F`t*JsjbyqAK@1kTAHE%2*_p^?j%xkvU?49#O6{ z%vxA#cCDOzvs=!QPS2&3Qy?%`O-;+H&|FKMVLKzOTfio1^2LuyIit*a-v{}eM@tZQ zA8xYC{yc^gn!R(zSPy^~uA$_9fi%!<(jogDPX_*>o=o0|qo<(t&Lpd0KS;wRNh_W& z;GHXHvNZ|Q1eN%Lg)~L>21=4_wz!A55%;Q`sTQjd&e3!y3_+#|1czvVv~7hIe^xEs z;-*`iaaF0QW;pNY>N={w8|y4*mUSuPmPL}YuSE@6wGW=-foxsf%9(9Z6*gi`m-#}e zB@+hhnQ*Gxk3{Mxi=o z*82z>aX-R$%HwFK@i`cI{(^Xme}cuFG9jybS9fihQwqHRu@ZrR6;?4QF|);Y3fs(L z2IOkDxB@;eU}IZfe|JUuvbH`mP8{1?#(0-mZ4&$_2B$*pnGAjzqAb3dJgB%_EQ;7h z0>h{hr^ywv0->2fa;ma!5l(lI69svKoXAqb7Y{?TPm?Ch#5?36t7_|?!b;6Gtj5Ek zS&@qtk3tncFpw#d=m} zP&gm*kX!M|tc>?iJo#MgxkBv9c@^7aX`{72f=1jW_zI_kJx*Q#WZ4QFlD2MYlRR2w z9W4QR8GyBS2LnuI`;#U>ef?s7yzupS)+EeewRN*FxZPv$yRTu8%B8EfPaE0{^IBv5 zQ+TNbMwl^h=yDM`cv+yBHw081`;WDC6_v_4T-0Idr@c(iA8{EpUhjjCunr)gp%Th@ zwK9iNPO}cG_1=I{PK(t9su^R^BxFz7*=aQ|#PqASOV|7IuFg*BS^-OkSO&5bZ4M7( zpr2^ddPSIxY1(CcL#efc1eo7o;%Hd3(x_)0_Df)vv_~|@45qfLud=hNf79mrt}W>H zqv_x!&|KWoz5yeD%%H0J*VUq-wryD11(DmjJGQB~K~;Cwv~6l#zYQdq7ms5aovW?m znJcDuUeS!o(TuAYkb%|mht`=$Jhl+)|M_fTMT@Kdjqnfy+0ycfib=a&C~Y zshk_z*U7zMpntR%w9bv@>I$itH(Ig%8F?1I68RK3biChTn+O`#P)^)@rMd9jE#dsy zdI-Tpr^)$^CF>ticXOT)kJf2&o)nMPX>y(tkJf2&o)(YRX>y(skJf2&o)wSQX>xum z9<9^lJSQF;*42NlV9xW_o02*vYJ4NciiGom)w0MF^+jQ!^^BaC#H00$oR`Ihht@N4 zelHlUXXLyh9<68Oyeb~8XXHT74>LHeXXLyt9#jCv>bzmS0|~UGDf*w`Yy{PJAsY5z zK0FE%&RfDxC7$5IeUEso^*NVFzJ9w=N}L5%!C)uwSMLtF5EhzOc%co0EaCmH_Z{u3jj3`nX&|uaffC1jeCYDXg4I zo0IHFvRwBa=%E6QMpFz+ZI=JAWMelT+QrmIy!nP#buT*vr^-GXeSU!fdTNDEwWN7? z5-W3D=&#$zv9KOD{ISG4NJJW$G<_mgFpYQ}rXQH)HapF+Y8=zytg!!uG`SJyV0+wR zrDituuA4Qh1cRQw5NnMU5RO~$rj-GW5zuUcRvOS~Rno~lohI!cjh+WLY0>b#g><8e zICb`N#E{jGU7mWO%X|_!h!@0C=$zFe2qZexewh;KOs(!k;@D$%ZYt|*?1x+OtFDJv zU(~s-HO9MnaNMv$^s}2Q*EFx% z*F3l#an{=7%1p8j(aCCs*g9GNDHo?j(mGV~?0*b|N&Pze8APhv<9dlzCB0_5L8m2& zjXmu~13h3#=kO_N8DfCPFJC4FQ9A+Vtxt@MpE_Bp5M&_JvE5w7o=tBD$ zIFepu*w7LQG^83$Xs0xxND>OX?ML??9a7?TF4nz7QrP1F2fJHB%<%xnk5Uz@>v=uN zFK%pf*&iW7Y_KtY*SXxTDrcX??(Yf-trFSvKuHuW*-C;h4u+hoBrY3=VH?`EVl)?T zM6@uRYqT7==dUBh=2TOCbA4I)a!z!vwf}*rJX|n%nv46+bvAVee2Kr7V0C*Z^0c{( zTdd434*l2LyCHqVeFR^bQoaO7@dkcm0FIkLrVLm1w08DlRm-3^+W(TER)q;V84ewk zIZ~Ww<0B*g-yvS{`8b|LBD4%kJNkP!dotWEGWaOkVFmlU>_fm0whlb@T^@U%3uZuN zy{Ja*u&BDhpYJp9z4lHCe7P6+PA{+|tN2?GFwDku$YmW^jdg+>7Le>)$ZEI!2Vu3x zWA(YuiYW|p3A%a)eApgY$pq|!uVgLF2nSiK1>vxjmQ!JloM>u$w7BMtNA1Y>H+HY^ z-RAM#>GNeC>$L}02Vq9c>-w&a_Vu!ud)B^FSls8ac+F?QQV*4y+*bCA2Kgbkt@OgLWq8>bNGT#&g_({VOZgtW z?~O5xx$&k*;7KTSeoZi?2;*hSdB^^t#B_@n(_@Uuujs{`diohAY`p6Ef&E7b`L-7_ zzAPoAD5%3{ONjeO3{%I*ET`%XE|RAqezuW+&DNw#V?Ffc&w&9FE2?$ z9OjKDrleMvF$-*j!}dR>c{zLGrL{PZ(5t+$&d?eRFg_Sor=d>}1}sGnf*~cKz;06e z(SEJK&=Q~;+Hls~8*CO}p%);LVDtzdb2{|=XB19*8|6AS{3!(Hj+&;j>u!()!R)Y*u3 zi&+?Lpg7AMIeJgxJzaXM#EUsv`}&?P?5&E|P1d${!grAPvQ#{UqqAH(f_Qx@w8q(i zXrOL|Z@i{`-E!`ea4Xs@li0P?I(G=oz4%I>{98DRX|pD@Q{e|*g=-;ZuvzK+MFRdE z-w9ta(DC>vo)`3EX4UR(IjUQoHO`beB$o&9dbq<(bgd)9axy4d=Md-n=&4;U%s5B( z=2yx&)Zt7l7xQv6Q^K0Y;S8%FDgB#sxKjaNVG_yPTibJva5!O_MEuv)e5cvryr_gU zp$^MwaX81BNAQ3;;IulN$1El?RP~*84yPei0uBZV<*au&x2VSy+sg>$Y;ZVDSd*02 zHn4d+Z4RdaEgJ84zi5S=lVQ!W(fJ1On>C(7C})$y@w_|fHv?z0!*O~mAiY{r<+M8- zd{0UKn?A!i(m4_|XOJeGyrZ0p0NyU(aPm4Fj-3}LgJ$L&?Qj&lN=K|yr<_h_5rEfY zmW~5xOzm;>T-MMC^Ack30PhWR3h!n(Tb#>SZRC!jvsG-WsHDDg$rJf)j^5`$h2GGQ z-WZ_c1QY|2R8!NGo#O?Jg$&}WXf9ic`}0ehR#rAbW5Zd7C`6ES#IJ#fxPoqKEL(;h z+mkh$#m*_tod-j(CT>PUbHjNCq$)9v`%>Q&kBuV6DRF}wEHByC*XAuiPc<^v$tm(c z{I^U3mg=MAfdr>%8N}#>^KFqM!)$WY;6<)-oW@~fLKCfpf&!|?=|Vrvkcd=E`uqCu z%2jJO&}RsGMi?!7FB*HMU`xVSn(D%)81`}y`YgfkYw$WvVeV%OzBC0NVtlW+v*3BiI?f=~?K5&ZtC_>?HN3&jB{mv!k8l&Tzq=1Ntmr%?n{k{!;@FK|ox?zZM@e+G)3p%mc@JVI^&zDY-6qM4cpy?~Pz)Pp@_sFD1`Fkn zh0+a!Nv**dNt0=9TZQ;1LYx(Xl2${rDeWE3HNLdUxzmWs?uX{NW_ch_RIHud!e1r;EEu?0_!AmOQi+lGVLs9qp}XBD)-J zPddpZ?R`tz+d44tU9JRLf%Q_gk0T^)EvUOC?rSWdF4wYRn(ddAN81(2)zn(HKGgP9QBA^$++ z9fGc%i5ImfY@rA+sY~#Ol2yZ!O&IQaE4Sj5{RU$gOCUH*5pPklrfU;l@RO=_qr-E= zNj{7fOT(rm>o;%f^$Bkh!jb?;N)0Sc_G8;as^C1`vadp!Nz2Aoc6ymQ_eo_iqfw}^ zfp{9>A};HSIT1pOt>7%G43D%!pR5n+LzqO}@BC8;)haWIO2VO+?myw!kQNwBXj6zG zA8<-R8gUokJE4-HPLB=@P~X$m-P(i0Ha0^B+wB}B!H&UKW^Jc2sO%Nc1%{k)g`?#} zX#krCogWLEyF50Jk`05VghhH+w08F6<~{YBdUPeD7!NsrlklH;;Rmnw#NbL-W{~Ne z%y1nr`MEF&%Zm75DG*adJ%9(K52umVvnV)LQJ7yiCnNTVdm6rSgnS8wVPcA3Kp&bS z2WB+jZH7atrU-{eoCk%&qvXKp>C5CGxysdhItSBnGww&z1d}=v!aue*yjPur=_XnI za&M%e=>%zhHGl>Q3ePD>^!NZGnLlHq*)N-lzjkg}!~D7fUrFu5a7b!H36&i7M^v)? zjq_&-_MR6kV=aPlq$|D)ji6XIIHd}WKOCFWxz5~YDswnxF`b$Gz74g&!mGy!a z;Y5lc+4h3)-cRCuQR3V$o1(p#NmW3``LYCAaHQu_b7Mn5P@9m%ybDhA*LNHx3DB_l z(DeeEx?Xd5Fk#gvs7baUc)$GM1Wj))FprlvBxvDw0qSa_7 zWsGx=CEpHRHgga2>PAPXY&wIoApryEvhZujdhXJN*3i~#aY@p4@{{s;?f+2r9dK1w z@Bg0<7ZjYh(o&Pu%F@a*7Y%XYM($1In$-mX1w=(aaiL^Oo7nhfMMbt84I7$mOieRQ z)5>gVwlpoZrD^5={fzUupAU%s{=8nm8PD^a_j%59=I4ysR6boFp~NJTP=3o~QZ##N zi`9j)(bbTlqXJ>v?%wEVx2n%#e}dSaRKE~#qzlB-hiSNJBGz@AxQQknmT-1`+E8@ezb#8?}Drw7s~Z~%V)PUD2w8bACKqj zqGb&W-0N7>9kNX0~I{6MC>PlxI z?O6@z5MWi?mH>N%1hai*uWvyWjsWI z2J&!3Z>$w@H?=dq5+Lq^M-wYQASkgTMMzj9tZmDuXs;m{C7jq;3USIi3EykVk;}^GPt{Mpxo@2Qk?DRX+P_!C*CEc zNNQ_2OLv2S7(^ENSXNytidYlO09MYn*{{?#uYR-w3;o#T2SL}H3-A>#z|W&>Ew~k2 zaDD#KheG<|$-tNseeskNz3giBBWtl9k*8`dVqqli>?}OWdJIu^pnomchV4&mjDOYu z1EoMdHoC_+HjkM)tE@JTtS2B#pxM#XNVl(LTfKSUBOLkgi;eksc-&{Wits?~YX^ZC z6F~=p9Ieex&qEg#&1okqW1N$A+*p%#G^hO*rA-H7z(Gqr(X~z5btLWl8q%(Xw4+a) zt$8sMJQ$Cq24sw~_JbMo5=x+lHmf zcv2#*ew22ZiYMcuAG`byg!X?4e^9h<(?7p80A1|_i~vmA;65#BALP+^g~~yN;vc&_ zI1b-Pc!(nuc3>de-@zCvWZOTGi&*1=)*xgEE#ow_<@}l2Z8?j19lb!o6T5p--v4Co{$FYPEE z%O;ddy+G%znI4vHGA$IyG*2C)>eJK_na-h(JgPn&T(pDM02;fWB*T>rX(*Gd;xQsq z@f#psGAtAe093SE*-*49*_GIhPIljG7@pFtX~^@2L6WrFM%VG-pyiq>)2W z8?77h5!QYLA@)(xcG$!oM`-`+@CT-vP5=CE@$xiZTM@qj(IQ>~tbW8CS54%8g!X@v zWChslb%a@M!j{WoJ1c(&M_1Ewjjn{^n4_y)9)WhLV@y)w^Wc}pEssZ~eS#`dT4294 zYgmh+I;dc%%$#n_eTAewnNg)xLv`+WgGwl#CKOy7Co`&V98?nDye{JDvPzYh48Nc( z6qNH$in6ag3T-efzyj- zoGNQP2N_DG@?GH+W4}D3Frm1-9+Kvoe6SJKtRHnIf#Vfdk4``M%22#L3E4}jf7ti9d{x6M-W}1 z;?>AJh)&krwQNl7Q9?CPb0-)z3B~S zp; z<5|wftK{c=NPLsVC@)?dT;l4zmU8dK_(>q%@H6;VdGO;gL@Jfbxl{}dXJWEuqAwnx zj=(otS;?VMqxSZ)!^|_rX~+YR-I~JQ2+5RPeyqThjZhQ-vy@Fk9)LXF#NSj-$8O!)n=0>(WTnw_w?vWV+$bZdRA3B)$dD%^A$=rDyPZ zX?`;lGZr$MGt~RxVQXz$WAfF97vUr143wnYcpeVZw6aei_LMMbsInDcr$s;qL5e_@#s0%H3H7{L+ej%tOL@%}q_()+ju- z-Ok;cj5j~wl(`c0Lt$iN2{xEjs(GEY6A0E^Yb%O!UtM!!a2Uj;x_3DP6`D|3 zb(5wT)d@wj7DjdNvg(rH7u8j=>XySVs$0#fYjvhk-Fq(8t#PStZCG`4kXVebvs-nq zDWXH9y7wFP1_i5b66Cs6N71ahdlAm6`v4B8uJcnTQ=LiTWU3<&th%%D@D<#y;iY?$ zzl&k#tN4wMt*x4B6ebkso@H9;T|BP5f&4t_-_?kk+DiCEVc)XC2DUT`+v8H$cP@o} zA6D1~Bo^a~bt`PPB8qDYh5gv502HjS2O-y`Fp6e{y@7C6*kL%(O8w(f*ppxm+nY&- zm1aGx!;L=iPm6}p;$dAP$mpkxi{A(#n7-6AR5*Da`Jx-7sVy;K_Z0$_uam zlwy1$)mJEnwK6t%Ach8hx00U+eg|S`;P)>4Tos8C{n3Xy=oq7tWzgYme3gdtmSFOx z2H?gmLweKX;B)If2Ay9G^tsavXrVajfZoTTFKw+Li7>{u)quRWW{`%4L6(IDuB&1Cj=^uO2L6`mM!!Pwl>`1e2H)&#)$ao!jPaEk@W0gz-q0}kxJT5$ zr7I#S48ENeMM<9wytgyj&A_c^q;`a@`RW-4xKJbksAzpR1Ha7xPXb|#FU^6f(^;C@yOQUGsG23tku;4?njQZ!qFR8?~jF zTQg!q!-!+cJw`%O7;y_Lijwvqc6S~-7;jlMyt%UsUZHr(!MlU;eocPvJa)uT=W#}y z;-3LVG$IE7%QfRSG>kv!#ZOWg{~1;kLGj=}$=b>%oQ=wA*|@aCWJ4&11E$U*IUDoH zFSAINu-asU7-M|PO*Zz_oDD<6*{E=`!Gj$S?3(AmA9LD=s-ZvOpcjf`4*HK7eV20# zdWp{?Kd)bj|7rNys2a|u+?1N!G=A1S6!COFhK6%<$jJ>inljBxHHE$da#5&IJmVl;$4GY>q#uD0qo)tFO?w4bG@;_R#r~v5=SfY6FcZ7dN9!W5RE?cx0lC%crB2*5& zhUD!H34apdp<0Wjwnj{`UcQkh>)~WDCic~_aBT+`;reTKk$0Nq`=3(2UBU!990&08 zf&edkj6z5xX6Bvk&Q>UQiIYfkWCSzh|63yODPMnKiYTOEx&tZM3n}e;rKUwiFXhc% zN*U^uLMWHm2`k+c7A!w}!*8f4oAy-D7RaeGJ9+I1j5%**WOP%twV8JxaLz zJ>2t*(gX9Ajf$@!0CSpF(h`?6D!v*eeQYGjUf}Qt2fhJbwyE62dReX_)0~nz?{-sC zLecg@Qx$KjM_=G)lb@^NP4%cMeht5@VBNwc^;kz!QnyM;@prJ>T%|LQOGm2Wd`7_~ z(+vruDsGnMldEFP3);qu8CmvS^@h%`UKOj7aaH^TIJhbvfdfS`L1j@@ya__8*}o=S zr7Aw=Vp}h4?xx?sWiEGBjF@eqMs`5AWclAw8DBELA5m6dpN3Hp|7PS`Nii>mt?iTu ze{_nN$62I2uAz;sC@MjxhSod*>ddN-)dY7N6_?+3hcN)5xTcdafX-|H^U2TCH;La* zex3k{f7nIFATDErcoBZ7x?NlbaXA}=?1bsc2Jr*v*boRnj4w^gBk-n6C08Pf)WYK! z{SImfrQj;G_YHiYY^308gbgEsqpS0N!lARJlTW5{BMPu(&D=>Qp{gyS(3{`dOCBGY?YZjKT zmhGDiX?zp_9(o-r9%l$^+oS?$+ZWB7Bg4BJap0M5dUdwcwT~{-v=2Ka-WT7S$ME5T z_R(~d=qKbSo7C~7l74DP&x=k;M);u1Y%8;BWa4#*368~|Wr)ssNqI-2mCE_X?TLLw zRKqcy+@65jGtT8f`d9R$^1Z-kKLxaMwCDmKb-1z>qN8t78r;0Qq?3<2-fld(zQ}ie zTe$g?_{DqxijIU_!Z$|nE>RLkqGh{*YgcGiwI@dG3!=*u6ej2VW0$WfgW2#mxC{6+ z%N}H2Aw?4;?wBi-t&BS6j?t~}(T@4zE|4>V^uJXpDv6?V^rMiPl8kUaC{igf@jCc| z+4yrif`UbGY=9%Nl!EWXpGKG4R__1ci1D@1sRgHPB*!+Rw0#emv zV^DH)mu(uU@iSa04;C(W%8Oh=OHU&-(Fh&&vP&pnxCBB6Z>SFL1 zV<(0Pez_Zl#XQvgfvd%F_^Ac`F`9US-QgRHTi7ub|0$YInSPBB8Ak7Atz6IpZ7ged zU$nE6gEcSy0>pElOL(zC$6W*FuMk^Kpc-&I`jLCJ_WcANYXnu`ZYzbNlqj0SY<>U~ zdlBBcr){Nt1;=7?Y=xsvJnAEn1^<9A0lr)d`o)KGlVTHi*QmVRByVT*1d`VS;fq0^ z(g}{%SHKYm$9OnWi7eO;z9-;IOok(P9sYa`Uoabv3t)h`)8N2IWlbjVmnK1#>!JIq zRW3uvm8(+g0nMzUiuYRg)51*$-ha~NHOcwwB0_etN6bQ94N`nyoW@f!dumR`3QSVM zC1`<;sW4h6n4#g1LO_fArGX*wGI;#nC4RKTx|@g^a{(fggJUXUrV8i2)Rlv_t0ae% zgO^=N(72WszC39hHZ4YAsIt+hYom%Lh0Jt`^PyZNC)Fj*e?rD@q;u9}g^RH#GkRJ> z4~&V*Y$dI6aaCzQJscej2Ot)?OyeWEi$9*7OFH#>MbLXL72v231U8R1X_XlE{%qIswF&$MvH#z^5zd= z=)t3$S0iY69D+=l&j`mmT&m{L!Cfxji;1$o+hQVa7uB+oHWkGOywzSVp7{Y7(2T-ql!174W^?`6I!5K z=1;7qTdsMUdr0=|n%syLzzmK%W^jo2?B0u_5Hk>tvw9gb5dU=eso;N;Q)&sO;D6^G zzBzAb0#qdaAJy{>(xB{#?r6Ct$W81hS^^l=>P^vbJGS=#tw@6a|AIKP^+PNS>0vfG zd*Z_wBe7*Y%$C(N3rEi%j*z446N|26>8_0Mq_4(38FP4|7pLeS!LWmV?D83pnyH{r^ni|Jj6a7ri>-lQ1}8W2X0e-l zL!(?7=JMXB8~PZX-o#TysZ2LFlFGDd&JYwb9&NF2X+$YK3+lnV3~?*tiRue!`Dg}k zNdgCqp#T(^_@0B0Yg!q2V|*26(-fJ(Sj|f3GmwpY8}%s1xT6Ks65S8Oje2l&f+Lk; zgYDoehA-F|j`zvY2aZPl;TQ@>S8|MmV-y^@X>edrrAY;%-wt=Fkw~LT$7JZZZth;B zEo{&at9O;dXi)YI4jeHNH33vNv(tP^psey?}r0 z@*$6zE@zXR4}f*_=3}kGu@ZjiMn01B0x;VxEGr_>wvy_-BMRIFXwZT*6!KBg?ukOI zRcO^YapEi*Gsy^#|KbxPLVEb>?8VxSgF1ZfmK%zKoP3>$7NakI!V zw>B+u^aP$Ul52Bpb#85Hh!!HE_nnPVf#%kxHz4Z_03l!HFt_%H5SIi0z!vp5{$6M} zVnLkb_+~vJ!Mg%N+4N-*cy6hkca>$W0MlUpsCz35`5gYF90j@G(MFJrq7aFAa_M>W z%ahqhII|Thr-zf-15Rci;mjUKa+0S9PgR^`FXmtTg)H`6vAbwz?6mp`)5Hr!Hd2!&{;ybCReF{DJm35) zmS*!!2Ad}TNNm4zEbArsrO7|a-|bosfyQ`#`*-Z3G>hBoW1RNOh#8VG36H^qpYgJf zv(V5`ZORD^M(10k0pn$x)(SbFn)1J6lR?4Xa=r(Tm6NHl)JX>(QV-eDOwhrIqNiB( zPT=P(D^Tf*y-#9!@0eE73XRkX$s-&;*i5bDW|XjVGa6|{QC0_J7p0HE<8p;K;~vL%bmXrVmE0Tw zH2AU06Q71{^A?dfzOLgzKpc|I`$5_=ORHoJxD5LYIOGlr$;pJa+OdB%`O%)VXWu=3 z_%Ikhmxn~(kgsrtWuM2=+XvLFMj}~EaLrh}*?WSE=2=fY$vVNdF5PlspdmP=TCgx1uxK8nrU^ESQm`Idm2r%mC?$~ zCDasG2Y#&xPxusmY2Y6tDxX`=%Pm_B#=$}K~7 zEqG)^Kjj)`&K(l5$I+5v}4Gt!GwnX>uC zSW#qFyfZ;|N*$BCGS*67-iR{R_tR3-)(OP}un(Cx9&14J#<*+9nCKp!e;UwSZW;X2 zy8hdMKSlHE`F{=QlMA-GWQNk6i~cOzYDgE-qB74Oj_QrAGPu$#lu0k`+IB;_@(i=b z*~2sFMU@;pikX8uQtgO_bgQUu!J*kh}Y@E_#Yx1e(NaJgF|rr|FT=3B6J_7HmJlol-OG~Ck8vOWS2 zkDu!=quS9!KcM@+R=w?fhKkA`nJ~D08&rHb-$etEI5=T2QT0l(@CO&|eDc>`C))ml zxy-(#;))2%-%Fz!JS#PTKlO1Vl%+9bZbKy2ZL$Uun{58mE^|W*<}Xm@v2L-x;)O_Y zzDCXDD8H|GcZ3yq(UsWC%EJqA`qj~s+UJ^@71-or+jly)g$`ST_roafw=U=49&9vSYMvV>oqpc{4bG9`|)BP5Isjk!{F^S?IyZq|sOw%nC zH>R4V`z`(={u=z!biY%Fn(j_P({#VfU&ZCaXC;3vmyh%B@fY$jprb~04X3*hK5h~z zIXqsc^L+pKjZ!WL0RI2nBnF;QE-DQl1aiM;C4Hm8WLl(88djOzV z^-C-`6su$Gz)qFf6M(LGo;4*KLSlSNP37_*RH7S%AUuR1D;`C&#ZdGnQ3b~JGu>ja zTxa>aYve=j7_I@-e_f@q&pWY}|5^=O?FyTxVV`OkBBHthEZXTwOO*z7v&PDryeS(Va(wEVjJkF(PT+CNwm9>GU{bx zsx*2`yUL_MR;NbAhwr*$DgP$L zQVU|KhVzg=#&?B7uvZDr_Yw>>1ZkUV02|lbvJNQNT@3a=0{ej?nk@2M%JqM%QTKY2 zy51z^ulKR&+-?ZceyIU$8o)mEl4y1}gDo8mu*Ve9*@*I5g1_-c zf~A*48O1$elJXB#ENNbXRSrS665Qw|*lGyU>VI-_GpGRA#Fqu^w+uGoI)Lq{h(4?i zwy#DV@Fum_B;~(TvDAlHml^mL8=GCM1Q&Y=+8Bbgi)sM78(@D|uzMKn%>?#3MKn$1 zxy_(RqaN}mb%jaFze%yY;U(}p1bda>OD{pTAxIlm1K2ox+NpR&H2WQct#v)X-ld4n zMN}0tcv_oS8~4nejOboCPaVhGaissU^Tz#dbuKQP!jHvsHG zMKnj`xy_*V7ExSu+$DgT{{Wwn=}$r8tAm0*vTppzj;d%gy+y8-su6{6W68SI?| zHckru2 zUL~6SnZe#qV7Dlu-PIHPNuz9Vxk@?S$n;;Nh*}AOyHr{!maDwH!wqlRrPaY^nMi9w z+*$a(`MQAJ&tT6;2iU(A(OuOOY^1}G7rY71G&22pTFP6z1a~+D^OWF_m!RAbq)j-v z8KkBGEDaJ5FwkWL^g>0`4SA?y0(~?pRiZGA#K=0v_q<8Qf0rgxP@VTVjk?dv`>x?l z+Yp9m1aC8u@)d`#c9PNYc%COFXhFOkX-3B*-ZP_Pp}1&_86A)3`RG{qDZdly(4cr7 z`S5&d&eW_B=2wt!*%Rx~cE2|=WIj5H(>X5_XX^NEHhr|pvh(YV9ZD0aiaA5_Px5M; zWlyg2AP8;&XPCg@E~rBC6_(lTO{o*SfDq$**U*SH z8@*{AFa)8FJEX#+wm+#fh0(AkF8ZK7#0vEcQ>-%-bmUVhx?7<)B zHgB_1e1*GRBz>&V_Ap5wL$cRJ(%TAs8z#vzB!^ri{jJc!Fv&baa@0jK&dE7T}V@{u8#=OXEAh1!Nm4jYm(7fGTO>Jlbt`i^FLp^K!473voz>263W zTqJ{FPhpa44as5`$(7iJrzBK8%Y>%J`tsNFW;pkba=j!RvbY!HyW}}Tutf>Bc?l96 zg565+yO$ub5=!b@<%A;?yO<6eShj;g0CL90rS9?o|NZdZbG|(fwhxWObDf^#*>HOMs>KFAa-|oCZk7gvHD;o-5t{V7i!IC|A4)wCEn|4H zD$HL$tDW6_l{a2kUy8y9Sn^|+H(p~#D?%|20|MFf@hWfnsDNMg^{wPh9y{TeO&zcC zrVd$6U*)>5`E@>w-Fz(g_>ArwobpQeC(?o3XoXOQVW0h4EN|dwFwO=ZXZ>F{Csw(- zXb2x^Ojh=bv8GHvcKLtnOb&$NQV5eA4B^wqufQ)k7{;fMhh$?s#GiJP_z2?>_$5cf z>n%z%2cwc*#~J;u#aKokw2m!@hY zH?}uUG)+^g?4aXjE6BU+nolxCI?8n`#lTdq=M0hIxEGiZ~OOv+(o3 z*yo8ip<<~Gdx9dkO%wmm@JpL^17~M&D>6E9cbRN9nS^5H=-EHB$!^k^au#Cw+aBc? z+p*PdxW(JAO6iP-%1(`K`hm81hrna;y#P1v7Hh%mRH{IBY(7y@tJkDJTfJ`NpjK}* z9GO*FxCOisG28;Kf&=>lb5t&W_uQu*GQE|M4oiqEuCQI^V^CLV5Sx7)Zccs|Mt6JV z;qo+yWbl4vrUtRqMoyI)75XShA1=eK;wwr>n<{z3bDqd{YYKJ!Jf<0l73ni{bkR4u>TFn)!2pcE{DDx}K806{UC|~gb$Q`Fq)WmKy za;?BTS8_glXFiQGhiQsdpiCL5k!>Z6zT!jpM!i%cxU4=@4{0rdse<-p*qisAWRhrd zR;Y)x5!k05D%=M}Y>nBss%F3T_agRXNr{idY4*Em6v^E$a!+M6*(RS!IWET2D95$G zl+M67VhdIJ~9oAP&6$>1H;Fmw(|83fg;l{Y~!)d%~MPxvfVY_ z`Gm(i(ujQOjA7(DhtGKY^9K0n_{k2&L7UIS<(sNCpMc;#Cmrhqy8a+aorEH+vzaY~ z73;^^ixrrrv2*~et;SM+QmWx(9`PDZ)#whFv|v?f{=YRgPh%*BD}D@Dh(!|awg`ih z>-r<6*!+W(Yo$xl2o0kuu-Qnm0&`pmL?Z7fWzTL7PYTPO6dq8v7Rmyw{ueZ?Q#dTJ z-j!-!38&pWzqwMKak^Avm+SN>Q2di{X)aKV7 zDphQSB|mogq%Foug<=@2My%9sOq(xngXK1Em7%iz!nORa%VR;zl?worc3b zcfo;o7xZlAgnV>XbqwVZ5TsH_B9T`iok*|3PS<3J$bKj~oNjXpEVlg4aUK| zBN`zEY&II1T(a^1;GAjgw;ajD?h}39Do8Qgn))$-twz*MfReHqj*kh`S8ycm#h>6G z_|s)3bod_}xD9cOSY7566@?)z|FDpeAY>u4;HX9tmYPUXt4K_`M|s8XC@lpRd9C ziywFh!k^63>?4fZx8R@I(r_QGYes)O6eIYsXdQ}W&`kU*%_Hg(|JaA?KDiC0OV?vP z3%OQc;?Gk2WD1ptB8!rHsk-3aJdGsv|0R*`A}~pD5tzHPtiZdR?F-^CWuPxI&}nqaf(V zE?@R33g>P_ZA9UuJPJprQdGUgaOA##mtVLO#?%N= zyI?HA)^Hr03#+*R4qSP%J0;ZHCbf12N7TioW&Rk7NvTXy&8`v7VrwRu+B zBN|HuFUPtICHWClI!|b90&v?iq6dGD%;X_F9>P;8FgOjqo8SxH49BN%B$mOESdKrz z#rSj7!1$~xjKR@oL7cz{tkc*TXd^E}Fu|Dxcn41oFM}Ee>!28Nve8#T^gjgfEyT6F z6*{X*5Zr*6OvD5~fny~ciM!!QJb*vJqxiEEL9DY#6|J)jtQSPDcfk73(b#VlsH3-} zei}pBkStIma47&Lm1vZ7-DV_WY^CZ*l*TnO!=f8s3KHZ~`0;!V#Pf z$6s(H-UP>l{8m^oBSMP5XdVcOBLj|9ib^DErW|$lAyJ_Bz&;3z~QR^7}eY_@jZVqB`DySq_2uD73 z1_PXj+UeYp`xxnq@_71hl97f^^1mT@xy%*6UVz=C%(eUV3x`=wdJPwaxcnFKvc!!!-ob73d@0nSE-7x4Tzv82t^3=V= z)0)HAOc`I8l`l7pe-kkeOz}mNaP`G5=7@*2N}T%HOn37U2!TNyyp{{KQIeC*(FXSo zgS^ehchI*91YPJZK;J>ST<|JfE_jH}0A7W=1rK9SJG9=O1_&QUlE;4S8@-GW0d%Uq z>wS$mlHKPwf_qaW&0o8ArSMIWq(Hj7P@cEn6iMr;-T3Clk0R;hguF|=g~Q`C)*=wKEg_(T-l#6O!m|3 z*`G$f3Phyo&mtGX#a2L>qD;y|(cK>*E6bAn-oDG^H;V=J%to2YO=?6#S&*z|aaJWe z<0Ly+Zr119HGl_D*$hxJk;9pwK~pX#N4Unb{^Bz-LwMRgRG2-f0Oy=1ME1Oz)FFYm zA7BbyEk7~xQw^2#my;st>H*FY;ii1ZWi#EMtBWipN|yd|vXsbK>c%=8DEegGid*zK zNc4%v(k*+ifXolOIV}=M3CLS#-JhWrV|5gp%ZS}jA7^`Y6qO6#V~I#Mm)%r$??sV` zP{!9XizsGY6qPPZClMr4-V5mdDUB-c5b1jy>36uK-{F#eCrg(S61P;iJ6V7{bt`T{ zaCa1$gdn(w5p?5kQDsccXedd7Ab0xFgq!cyqq`}zcIDwpKFi+CEX%b;o!=H5__51V zBg}re-3)m(8u&4x%$&juu;a+;?x+N;5q((3pD|3}o~T3we!2j&;~k{4@1pJpgro2$ zbK~}XlpK9MG&%WtvfUq|{zE*jpD!59Pr&~eMQ_ZP-pd!)XNIIH`zdNB+AR}%AHs1A zmn0)szp-L7p+?ToB3Z{#5oo4a}^N(&_(dGX&zzY zx$G$bfjk^3){6*^a`>~)fNmtr-u^p^+LUt_o3BR4qU5Vl#pGn1SGR2Ae`+#bt1KuA zO+Bo`#&Lly zFQCi1q!9m&dH|)m5!6GV_y3}2_K4cdTtgw-kO{{nH^gv2TR}xy@*loZEyq^;7|AE z@I3-Y?$h`a<4Z7js0&_nOz_0D2A(-l5B~r>7a;s0Fr}OY$96bUDK^*@zL=LV>gojt zPVG$&4u|6!gak*!@g6zG!_oF-EQa(uE^_I+)#2}DEXF%@>5J7EjogpHQ!}J!25NNe zA&tr~m z5tg)DqjfYVOjw@iq1xG|i4Z)w^I{Z@EaeL{{&k>Z#rWSDCwn82+&#)ivzmq|Vr0<0 zB4$c}r#D}&a6Y^7J>r4h3WnD|PQ(1KGUL;mEn;~6!*E$iuV}E$uWCl|gAs&PXd33M zS3Avb4ZDb~edZz9Mg4Cqs{nckx6R(3KF&lq^MfmgWN?1`T9ACZ$t1YA8$MNU9RS>cS4qWPQ z%$Ft+10p2X`DX*>Pmxdl1ei2&xEb_3mDmDDD#a$!G=irPQLiHjnnI8xk){xdG<`@) zR#`Mjk|8}6_7v)iM%=RtD~vIc)^bW~U{q)?(yBoCRS=U(fr-z-m$(Xlf@|@o5aGF7 z;qWa$1^tR0TPNr4g#)W0x*8sMRHZ%$%e)XGk!Fmq>zis5xG1i86TeVWygSlL+Ni`@ zn(|dccfc8mY*axNK-k~<2HLDA0(TSkHc^l72lfL9UjmFNJK;D=j?Hikcmug1vfxqp z%HYe5)I0>6!4dH$ly(jr!He)G6TV<~ICjF3+Zzr{5+?^o!qN6EMCHM;8IIgpaA4J0 z%Pw$2@lf+nXCLRA+^E8;i{bUlT8Qk(J z-~w?C1svr$@@Huj@Ufq+La_YvG;*j!a695bPWuE$fs~=cL$|ZA&x`$il|vw>8CeQa zcEcDAT7hj!ORZj+(DG%hw=@=@oPPz1{J)^Voc~jb=EBK;-CH<;uU!1+!vImooWk`& zWB$%n`I|Noft3C@;deKxCST0l;*D_PQ6(0=R~oon`RR6^8=dsgJ0xXj%zngBfy}7~ zTLCu2p;x&<+l3`4x7UOZ70=3m9Vn9Q>pyWo3GZ#t{h_fpG$P~L3i28mo*RKGfh_&c-B?HdwJMS zV#J?o4Yva8U2IcN$5!F6^==wg%U!}oYMG$Hq?XMdX(z!RbTu<-KR-1Ki~Zgan-qJ7 z1d~`AT=0Gb?YTYb_)iOvdhU@}EgSf!4$#}6=k8mp)nWA94e3>M7t_FJ6zx2s zv5~edSO%|uLLl6uOoUOdh63hMb{{Kn#0p#RGeSlcBhEFG_)&sk^6s)VI^(iE^s={X z13g?5lz+owjo!&*uKN9CCgTws=N1bS3E0~4k~NMHenNYp29wzPPcL?_+Y(9a2p9k6 z)AOe(EGsa)c36Aghw)6)V8YWL23);nc(UoK8Nict*wqP~hPTpSfkJ4Gl&15^tyF!M z)mlx}hvrD5-$Nat&n-{GkxH@QIntL1;yDsITyvyxDof@_bTAG-8NIOnxb(JZohTZPdE!5(50#D{AFY5(HubfylTE^V2_du(LvlEc>HcFB8=Z zh${nCW>td3*AWwZ4}ab#A=ZfAV=&#-5>1XnIy-80{0kDsBK&8Nq>P3mbuBeLhz(AL zZvlLP`;})ia?=D1)Xs4YtY7@9@BT=+m9$HHE9r6VMVtkR4LlYdaeNmZ9@3Fh86|v9 z?Z=NG;r6>RWk(7rE#T<54vuf?G zI<6wma|{uBHaAOJffUya^f$?Ydw6AJauX1I%hd!(6NC*hv_6vW8X#N({Ln*o35d3`cZG2A%hV^%Ie-5Rum=+7}lfdXN~3TQ$b`+fwSvMsgU|!6{&9B zdqlc)Z#oez!LF`h(y`M>>G1YR?0}{nfpV9W1n9Ji9sD1$99JpSOWvSTFk-}Rqd1?H zbj2x4-IK(ssv5M=X&32A*vldrBR4B>yM|GUTQod6fqK#&mVcLypMK>C=Tvnmb+71| zV*ipRko154v6Gc*nT|cURI^_ZLZG;$$KA_CoOVRd=08;-t z4JNEFo*rv(Mc8(Agg;IDKw1x2ugIufddanJTkD@{#_TE87AvcX9j6^A?KFrJc1^HY zV<^D{Cx%B}+#tTB@sy>K(>#>YZstzyud4&kp6`c^fW9d{xU&NA8*`k|Aa` zK!3Ti?sr(Nz-A32{j~qjTT=jmb|kth|8h+RH_qx})3;E{mCVS4FaISz0WwX5dDJn~ zQ$to&t04oFmukp8!cR4%Sc3`U$5k*&x8uRM*HxR@A>v@>Ki_T{TOK#0(lK^AC%Jnl)<% zKLIoBA+D{b;VLuZtiZE6!l3KXe>P~jJ6fSJ)Tr1t<%3VKee7ar$-%U9ntHbHHD*6V zT_G{DbRzLN$6TC&Wc{c>Xm2-SPN8L&0jZXXToTq)k#Lggx!Wn=n8spTl(AjHNC){i zcY`&KV4V|j+QLiltl*IrlHNJx5XMt0Vx8rqSlWI?AH8{dQ!gtv4WGB^TQ>X8$9=rC zhbiijYq1}1e#o*C&X6p8ia`(k*yUIFFmQbuQF}2sO?e59b2ehk`ZgTF5AbIRe8KH- z`~gSq*KpwE&4kY9SXLZ3`x9p*UORf6S+DsJgI|hc{zT$WB;G{g8`Z42BtH6SZY`Wc zEPenbGw!$vpkI|%Xiu^zn3k#U=&aLeXgiqHxi-Qa9&xz5jnHqysCb4IJ;fl2)ezRWylsZqUAE_fHJwJIg}Pn zyDcN5OU`iTQ1;Mywt1FH4qt!($ziGF(5i;(@F7MwMV^-b^ zBNUIr8syB(j}7U}jJ*jT{P=A9-iG~PBzc>mDSk0zU&BRd*k{DI?ElQ~D9fIs{rtYN zoU1v|koHSOY_YMCLmrR%r6HY}S&9%j@%$^_mjBXLYz*NG84flyXJX{c%pt~&54E!g zU)&gQ#BY6Uwy7L$_#yH^H|W!TpWm3e17i6^4P_25N$9kV4>w<-8c0K4?0pRnN1+1I z&hp;dY|JRqz8Yf zeb0qus>l-!$(X{Up|UWR4m27L{H@IUk&*uiv$>a^bz!#@UC?y%1qDkw3bc}N;`^v7 zAEu8dG@cX`31g}#sV25k&DzpnWL;E^ zlz9C48rB|mT#t~Rdl2G><4YlI4*``4>{VwG5UKrn#1u49H}HUm;>L)A5e#; zz>)kT>d=jFQ1!~a9}e6xV=B`;SE)Q)r&>M?U6snT&Be9jG+fmx(<+y?Thu*ulJ1&P ztAyVZx}kk+^$WoS4-`p%(uAO#j^Jeg2CH1&=dNlo>r-(6Fs zC9ncR)C8$|#2bFx<>RuzrZE!ozqA=WTYkSb8$J@ zlIrP6-&H%%1>SwVWgXI{Iu7GdyK!u6BlJA4Aw1<*{CNo0oU#XwoS)$M433R^;rIZK z)O~O)gJUi^9)~0TXVeH1lY0z4?5Hfr!AVV{Y(Tfm$$ z365oOjLd)|vnqM;HiUkJ=-{JpoOKWaSHi)4?|X3g5fa=CM-e$bhvQ*#dHx)(w z20a@B{3?W>>`%&8MEngTDQn>vatNhDY`I^-N0~rvJXaM@wQ3S%RWUzf1>C58tBcT< zzpHZ17Y_6cs4?6n8cQL0@1929OGaKGP4z=uf1ZY`!r>}Wg%MZB*i&QQ>ToSpE;?2< zgt^RlXk3tr_l!PtNxktjQr~l=ey?0q!p{homM|3~N|;1PY1t9ruTCTS9wR#Gpo{BN z#q)>ZfTe67V_Ca(^bv=Fy?sV(BHD(OS{ayg9)jZ-2=>8|O0kKJ5sYTy6&-R@s}?w@ z9y+g{3tny$tw0MMbWaU-oM0KqTVCoy;HqM#rueQ{}%63^&S)N>*_r&-VN&gN4z`K`>%L^RPTS{ z{ZqXs#2bZN#v_B4E&gWex5eL!;v&S&cUADw8M$wIm5=lk+g{qzBTb+n{MhApT!8a2 ze1K?`k0!+J4%>WWxiC;rT~|=S85P_Z@^5+Z+DV_17Sg-&_xo4 z1xGy7cZQ_E-?g}n!08D8G9~F;Ef%{oZ5(}g>|&9TB?Ko06SLX@!{31Yw_hRwPn?3O zX_zT4#`lNj$MSDf-p@|Kd%Q~SLy?_bIXxF5CM5HzCoH7E40(Z&bDrnSn2X( zd?O8wf0jad%1e;x5Im#=>%0Voh9K>#uBvcP;?{&xpuMF9&~^aYw#Q+dzbl?P2=zks z*E?T?bd)HAbFN9nU;k1e80sas$02B^1QWajj~ars(KX<#1kQ`j1kUcj`4r)7qhMaH zjNZ8QXF57vOwIuED&2xlU2p7#%M z4pA`IiYQmn`!h9arZ<%@Oe+2oRad!};4g>ZVI_FmOAzy(l!KKvy#|~Kz*%w@aHas~ zV!}CF!9*aG%l&|p%7Yr!PNIx9TA5V*S1XKuUV@$u!DuDO@)8U-1ZmsdIGvPXpTK!; zOW@1|&I|tq&X*L-QiHRT5#rydQ6G9!8SN1Kt1u3D3Gy9+vn~_G)kl)9a=+COq^)q{ zbW*k^R08K_!dVEM&k@e=6-+=x#rPa*|Gyel=uM^Eq~d>Dao+DGc-bNNLJ3xQ2|h3c zX$`wcMz|!Ml&uLCRdGUY1*}Q{L9;=SCvqrT9gG(E`O)CDYR9#nk3I1^i zu2q8Ty#!~jG4^@527M*~XY1C$xd1qq6VAa3W|4?;>oY^6)_7CtVN&szD2(sD1ZfVz z!%7f^Bwab3X9&_RszINnz`2faRsiQ^CxEj=!3-8rZk+$qsPW!ZmYP)jZ!3&Dy#(tW zf-jWdc`v~ah9GT74LB=-bHdrc`66(>N;sD*nBS`7{6M3cfWf5=-&!p-|Gx_3axXy( zhv2L(LYm?wxY!V+<R?&T+5qP}z}XFZ9Q@xYn1@A_Tc7`E)SKQ^2AWj-S1F9I zyaf3U!L>^8ua{tldMvayzQ|=WG!P}~?SzdzY9D*;D;88EZ>xLlhgj=6Z${2+L=k;xYvkoS1 zm4tJTg4t6Y=W&hlfx%Vo@0(Qo#R{Xnmtea?aK94t_Y!<-2-0plInLBl;0&GtjD38- z*z7{l`mG`+#^>b7f3ZeA>rLUHNx}cGLfGIXhujkKfbFv*liFjUClldofjcD#N5{wrE0tn%^Wlr}Wt$JKC0Gucr`*-jUo|x#+v&nat(46Rf0#sxK0DN{oArBxG)Id%;UP z<_iUZY?*Pto13OY|8ql>c^NWITlqpIN`jTqSKMN-H^cHT(a4Y8G0wZWFKFx!PAooE zoGY*>FD=ilrWmsvz$#D3G%7E5aRr3SQ&JwbIA=V)McF1ZOSSiQf6(Y#B${%R_qT>2 zyE#pChSv8v=(CM_=)K*y1p*$SePGOZUUl(buF)SWx)QL=)-cLz^m*>Glg~XK)XpQk z{xW52$t=8g=t&JClj|jt!im$OW@jtM%#mY3uj0WMxBl= zc7v%s-L=K0r1OQ1+Ne|wCTY)}PTB@%6(~*F-c%Oa2;Ws(C`w^lIE55f!xe+&zN(Fv zM^%eW3V~HFwgeB`N$Sl}M>`u`AX0@5*-ZM`CGC^|mKsU=Y>vFXH%;E-z+F8>Sp{R$ zGjQEZFTPnfwuk6XSeGt5$|OHum^7#^U6@o< z57PL8q``INf}}&U`DP!wQ7ANVl3t-Rq%M6R=vg1c-!?@4hSq%tmO!89hK!vwWnyM% zY)&53XW7FTb6kT6*)l~M!j49CpI=o;E+|b3zouBd6lG= z`zSm(NTx`pEWSd*S4!DhuXn-_?-kIrY8qip*{HGiYwZ1q&E3Xw->9O|3CADwLKNvkoGQS4FrEM0?7`bGjAntN#NPdx`L(D6By3t3_{=RHB4aQk^uI zlDhTuNqNraBB{LY$}d{%?@DA@IFVdeBKuFDi04=>^%r-#_}im~!@N$V59e5I-uoVO zpS#cv5;3HLe_hh&pI*A>kS)+9jp!wsB^90qnK@+3W(!`F)eh|!zT%Yqye}fqv}agk zo6cUb(y5t7kSk`w2U;gk8}v}Uf0&Bs!R*1>Mb;FnZ9BZ~INc?Cn#gw7c#q)83#$u0 zp!|0;ukM}-gtStVc|C2U;>eo@lWsni;3_3&(zEiOS6VTp=~{{C?ybm6Sp^X#*zAaN zr9Ye2E9XWfdjAPn$ph-40|XZ+2dZ#jg@(7pNVm5ue65Dlr~gqV1<-GDg-;IC`xCWR zJ+EQhphn`#mNwK7<1C0d3dDD|MAd^P5>U{cVPpP0<^4c;xh0p4XMtNaj&OYI!ts@c zlS==Q@TlVD*y4%9PA-$Z@-nY|$dJ&emF*+eWgl4WumUk^vLyN%;isB#iOZ7jJH6Ng zRr-TKnoI1`u-H3XVt=V3_9WI^>OyO-h$weSj>ISc^$dWM*1IHEuX-LG%yWTNsd9{A zcz)lZ*9_{HSTJeAHAMv&GFiUf_U5kCzi((S^R=n@g9=k8VWUHG!6aOlSZMkB*|ob_ zSbfO9hIWqk%NdYW)R*pP?1w8Rdt1H%b^@ZYD_I3Nbp3H$05mxnS%c^jR^LE-J`=7w z6`_tKk?bJ*BPL&7l^p3Cu}a-9t0+Au4_JoS?Ya||#Z`Iw;o`@FNz)DA*hxd_UQORH zdoI&gRHYxDpEVK0fvj;uaBHG3$zIEJ3#-yOSU?Gh1=FFm{H%ha=>Rj_Zr+2ylvQO? z;j9?Vfl0`3&tjf=4i94dQ?d%Ck4(>-lGT4&s^tsVA2Usk8N?8y$->{l~xKXG^ig? zKWBf>@{&z@19LL_QHs5bV8>&o6lK9;-tp~7p+pB(B?9pPTpeop-t{#dNfZfHDUxwX zcX~l#R%XBSqIAnw>FdvQJv?-Y1zA~D2v_^=V8YHGLQ;78#3`5(6-_C~Dlk>;J>PmJ z?ogE&Mw2-uqsY*$@ij^%lyOz*uE{FMNzY4~GGRl~C3E$v5 zj_~28NRqRs7v^N7=b_GJ6y)U7g{!^~d@X~NCCeimLKs6Ji*7Qtd>eg_h9o$(;2922|YL8`)ABDMGjIV=I#GV*xS&Mt<;iL%by40MBDcAG~T6W<= zgkqQNIfAKpeqEZf33sJ(PaBjpviHzI{X(gOk`nt_%}4JCPZXWHnQq{XNzWLM16P(k zKc;a{7WkPY{q~TaQEv!a!}HU{(;2aefx)ydT8MAYet0n4o?~p7(R4p{{ULA zC!z>-XPr&dz(#WV_P2a~p^iH>^}v)qmT!cR#@0+abWk5a>KsZOG!zgmU#f7JiA`+h zi?B}-Ipfn^k=As~;OUO@kdyHvF?Hi9<8j+G<2yk;BO7lr7P>c7jr|XEYv@}S9hIOc zCu4je-N25TU@OU9Ljs%2$PN|dOhCDg%jZN6eWrEi`C_gwF%A1sd3)Ayxb60q6 zaR#v#go?OjwCsrzyHFR@Jh8a!*Rm(kHNN2$w;6h!duU=hAt<6dmodv$+n7O0$i^MP z=~L0OrH{!2$rM`CKzE`kOwTS#9}~ha#eHI5b_JGScNqmcVv^#5oT9AI1hkRU zaAP?(sgV@3C@&;(WAA77t8Cs!RYekq^@%(>oM&SH(b!np5&1My<+7`X#Bi6nTu0A& zg35o7d4N$>WQbmw<#WRVeBsy7yo`UuY>@0IBUK2P#Jo{>27Y5b$#GX|8TgOq-ojfpCGA67xX&00mx z?9vn$-Q&0UxRS{@!$-dn-`FMJHNi7v_>HI+QL+kQ^xN#Bs96(mCG(^VOaHZ~v`Zqu zOux-8jVgHz2kPjz*``{vCuB{?$e(WMzd0CF(AHA@cV_olXjn;-{%i4$O(YpOX{rCt z>^3tFV(IscL9+_;G0H0%YnlIN&9rCU4Se+5Jags%obZjy)%-+7{{I<^iOD`4CMa#44 z6CT-c|srvJviu1@mX%xV(V1!@VLfhJ9Vsio+k z5op@h*dt6UqNA&`ErWmhJA2#PI$N4EFmH(QyD^L~Blr&gjPPVWKS%mhY88$MPhv&T zBIgeun?6-vcml(6VAU$0ueGDA5sfecx=9Le`c)IC8W~bO4D|`$oNK{7eAXa-{l7yO zP0QEZ)lclnjPr3fH0ZNFi!_0VzQ(qqs?v3(b*l<%ON7q{qOv)z)pg)`6kNByqCyxHDqVnP&~uTH^sHHg z7SeN>@YA!XK?LYoTv%5kA}F+~wys84j4Q3JF03nBD}n@-)YMefh)7OSRaGIPD1^3@ z7Otxk(FCktSH7-l<2o^pfZ~#((#paL5ko*}u889l2*j(v0x@0%7KsE-vP>i@#4?e@ z2o#&FFbJhkXhT(Lu}Gy5hNBkaBGL$`MuR6%ptf*zNnuS*VS|`RV37)^Q+R!CNlkId z>e6)>!%2jwsHT2SR>6%Fom>nFOr2p;-h$oR`#u>j ztrCS4LOCUcm130&SJf1*DG^0(L`iX|YE@ZDQJpBZQ@E%SLQzq6n$?6TS}oS_llHA* zEd@7})YO(%p(l2ArIC~qb*q-V8%yv8RD%fjPVJxZHKyA4XZZ@e+tZmB8s_#UJb&Sx*a%s&3}#- zJpPPBw?Gk#Ztd@E(kc3J@;y$ipsm?uQ!aN6d9jb>n}h(WsrQmvmUZk8Xjyd?ohh66U}3nrXnpJnM@-$ z4-HPCfJhC6+VTAxXWG&)LzK^&h~KmpNKpFsAD^HUK&=KQr5yy8{*8%g{dmy7|KSOt z{!Z2t?Wd6}?nA?T;+0E2a6#18)U>0qy%TaMLyzdQdf+#g{Zn#C;^mj-_SRP7`}HK# z%zrV#bP?h6Da^b-FiQBq{RhJ5+xU&Ri14u-;X~;md^UqHBfvSd@S&g*J`^J1!%qkw zdXn(rCxj0@N%+uH2_Fh6;lnsb_z56F!6>;locQd?WNgtK14nDRkR)Q&ov0giOoO3A zbbwb!!*D*GfYSiR9nzWT^D!~>zK7iu2$4{Tc#$v`pVEoaosx@?Jnn}YjVtQVSbF&h zhhETKu?JmXpaL{opCZLmqqif^c##kak-QI8l;ZFsB#h`SKm%FqMUEq6qLxJZ;je?! zG|)cr>-irzpYCkz!*_dnXv46h{GVdX|IhGYIf?=Q9+Pd{{&~!=?;;G??=WCWZwhk} zD8Prcp&2j*6$7RaF<^dz0n?KhFh9Y7=}8Qjo{9leNHJi>ISiN}&44)xGhhli4443i z0TbXbU;>B%a|&X>DgXwo0${+L1PoXqzSF*BG@Fh@{@QsRx>xI&gI8 zq>fgp-?nAOff)2!?9KeZxn^5$sJFkHObFncXSMYB0XPZ$byxh$^HKMl#5r;aKQNJ2 zH}S<#NqtdCbshG;_Da3WyfZifr^5b{T}>_BeR!F@sH++0Eq4WHV`e?*)g6s(y~6w? z<9&e#K)dFrf>)tb%gtNZ+>B#&B>T7E$B{kGuPjZl>EVbPhDyX7;sR3LJY?GK*#XK0 zJ(+h0>mqUVh=UYqO+&LRHba!u*NK;X=Dt8I3iVg#uI<`^ChiaH=O$J!Q1FKtw*1u# z6+FmroWFXJf`=GR^;a)e@BxN1{MAboe30Qe{vzDC*0QTlcli1M4MdK=a#v9=4%%*D zaFM^ZrL73PxiK&ivC9Z72KW&MmlIe5@S_ao5x5%Q#~55m;2MB8F<3xgEx?-@T;(s( z72m=&75j^Oa)kMDZrfS_xxyS~pc(+A(+C6g02T`KRtB~Jz*|SRF|ZB5Qel3Afo^|I z<1Xw{7}({nX##Ku1N;3o%>eFX;6{JVRseS~Fzm1C?Z(72a2H|#e2Rgih-t@MGjKl& z0C0$b<9-~EnRj#eX@AY7!aU63Q~sJ<^yUZyrvachM;Uk-0D5x|1Fr)>Z|-H_EPzGA z{4@i<0I*n?_c8Fczos3H`3wVp4(<$sV2#KPEu?oUYkCW2?76@L6d`p4%`WcK6Xx@r z?WixZxMgd9n}a^Z==*(<6^*@pt8nRF)3&-UuIB}gIqr=iHwcbj3Lan4fG8DHYa zQ==lCykFwz(>@WkssU$+@?%S}sG>H~DVn_LM`(Ifu>x+!J0BN4OO0}*tS|culyQAU z)w(q-;C;C+0#{J@USN<5Ch$cDt64)Z|3VBQnz9Nr)%XhvVn8AO)A%|exMYQS)1b`b zEb~0Rc!~8{(X|r`9;d#)H<*V6o*`cG2jdVTeU$D`Mmmm1+;o5Tru!eAE+$k_ShJ>t zw1|>5F#K8OIb%Jt#eN;d#PtjFFI-#P<^7G#s=B`!4 zjsH$vyD-=KPf!;B+V-|>!YuVu0hWkXNzF3d{oTv8xBddpj?9;je|5?uW+=;W`*+`s*6o z6k-SSJfFX&rMIPLprsiLrc<#&e@RbIS5H-U6Z7jX&KS_h*4Ew@Oh7lY5b$S8S=-XV zD?^x9bJ}R9Osu;eM#cEad7(<@?&aKZjB_*hamqv|GuCN8qmpeFIl%c+6&R{)?A`|&3gZdCd#|gr4Jj~E3g3!N5 z7Ao$_q3}!G0miPpNISdk4e3Ib; z1*1t%FnA!!WN>M~OQ!1sfs}1o>I!igBwu z`f3{oAWT2U1PU1QqcHa~Cbj}}t4esrE+GvTEjR~|R5rgHATb?X?Lnji;S1HQUq|Qr zq1Efx6_LUrqRlgbMG)@(Rdi16XbN9t$`JmN&SnSqHOBe;>pRJffgNhhuQLvdv-*OP z&2I$Opuw6O8cpbuOSwmx}X=&m`{8aD^8iJ;}6*vW$PY3Tto+Nh*WXb8X&ON{3l`f*rr88dWAFn_^<`?q1~&v6yPd*GTtGgfm-f6J2z)WIf0bw-={hvPvD@ zN1=>KIFm;zF}YSFfj}A|ri8F<;Lj7c^|r!;f&7Pzwo^LQU%467kfX2_XMlw^Z7|2W!|63&}>mN7v%YFXQlN(+^r+)U_;c@B8BTk4!tIsJd3oPo84>xwH%g#Q+UL04h* zziIGLxSQtiy|T}OT~tH_s$qVI0$NuAS}v@pSXEe5F8s+8a!I^dOYv(};3xR+s4O@@ zKNP|VxSOrG6z5?$K5l@DJ;$FqAqI|9QQ%cQeOlC2wbnEe&u3D+R-Hws*jzzu1zIFBHZco;uP8O4e_&C+@49FB92#|DdY zmQ#Rob|H{FI(-Tibw6TKsJOETfF*C#g>n;NeeUb%X=zi#fMLR0WjY=?_|G`>J5-yd z#IC+cY=qBG`x2-O7TP4hIb=QxN= zuv8-(7fK*bob|@B89hhEY;j^jyE>=^3t;R)jyX!iz9G(vMSkOXJ03Sdl)l zG4}(XIz^t_S~{Sl_hSCKHS++4@t?2iUw%FU&M$Q zaEyqQ9$p;fm{C9MJKBgyL1jdw5E&8q2_qss$%x2L7!m17MnrllBO-;A5s`6@5s@Hm zMC2rFM5K^oL?pm5A`;*j5eXn8BBvlDq6)x>r~)t|auOI36#_;?MvxIvVaSL`A!S6Q zkYhw7fQ^V0@E8#Zw2g=q4l^PWLK_iPP#F;^Y#R|N>=+RVaE>=;5#(%v3kXt1L<-qP zL>1OXL^r~<7#7h5jnZ|=(MX@SuaTx(c& z>x}N#tHiZJAvj+*g$5c!*vVu2llme$Bf-MA_T#z)m@w@a+{Z0^_SVWqnp2JeZIZ(? z_D*v8yOiiXoveKqI9X%lwR4-SPs4op#&mA;DX(ih*twb9p?#xvT&UFXx<=fE4&J`e zUe|uhWIKZIW4EJXlT8P{n^sU*ZMb|l@23{o8!oe2B_F2!N5HzD5>{y32;l(nqW680 zovtn1VnLEJ%%$7sb?G+UjhR1}M$W7)-Gq&l@ZUBEc}-PZ;4f61&)J3f!gpa-sIsII zTc;3QyGx6}2Ub_rR2K3{Voo3bpq2EZ+Y-| zS*{O9;UX|S{uG)J7o?--u1?x0iNK8bOHoW}5Zg2u&jT|#Nk-7gGm8;3f_1yQ5j~rs zIU@2s8ylDtzXJtE(YRKi(b0VfM2KV@TDb%W%4edRBxZ_*3s)TXS zOw``27TZcP;;tp1_8KuKP?$n1Ik=8as{*T1@=&k{R<`#xiNNXMa~eBdY?XOOafIYk7Gyz77cRjC@J4eb8!3H zh>yF7l#h3$Jf*i_gurbyabUn&%2QBDc?yw~=O?5*JxR**6H=a@B<1O;q&$U`lxLhH zx50gjX>fTTR9AStf`kn$=3DbGnDl&7#Q-K1Pmn9+2~tv?LbjAwVJ+p| z2v?*R+bLXB38BKIJRwNR^HWKA3SKDX$5T#^lqcA66(Ycv@|;jhc?x@^Jb|v1_dt%6 zC!ANxCs@Xcdq8}Njm^!xo6aK^Ari6aZiAuE$S2STGhTlu9lzskMG}xWK*s_NVRN=4 zG?0rA;t~BOL>sIBL`C)P-hqpX!pm99Tz@$l8io)QY_w-{S?bkX^}-!T3Hd@4p1N|WCpVU&v3 zu_%nIq(mxzkHN3rHAul=ddC#U6Nd3Q9B8NNbB~28KhKR0Z)K~30@A1!dQkv}7sfo) zl!mEkrgJ|JjH$BcbBRhcupqRJTDO$zN<(Ow@epdAkk%!PZN_69>}=V|uXOA%cua`p z(M$v^n&p5+WP|e!ZA-yjRdirhYpYC+pd$J+4t3$AJ$*+noXlz|IAx+KCQSx;p~<)Y z6e-M+`YBIoMQb(`!Hn-{U;%(7$T5|ibhqeZm8tYu&Z)3zl#3}p^yd064b&l5Bj>st z_6?-O?L%V9?{w@I#G>u=ot|l=pH0UbcH7A~MP5QYk?N(@$Bk1+GDFSb8A`EMr>5!uU@n*X&StOZ&oQOF}l2VV;H8 z9zmrq8(VZE{s#+^{)|J{$HEzFXQO?l{2kC4G#zU@HzD8Lmr?w@ z+W}Dr7f~-7bb2u#6?YrlgV*dz|7uq{8J7Oc-Z6Wyh$`Yf9MthSRMc}u2WsZx3Xz!y zq=f?1ha0K5N5?D!shDa;RAxUWxT7aq1Ey_ zN@1E`_PQ!vWH#uG6wOh>jzU9-J)F=(eViKdOJf&^a4v-}S%Ao-=^&UD2+(-WE9SsW z`{pO;I@chvGuOPH7weeK9MeD-j%8MiZi2H|!6=Ss^1Yqd;^e+VcWyRZm|Q(_@Js@BJSI?3XYunP#gBpXtf{)2T(TUqD|ch{{EkwOQS#ULU52d^_O_1a~l3XCPo zfv11tvrGPfBT4!5;1j>cjDNs(+@_ws(6+|T=8l#goKI}g zb6W^$M1SWlhd9+I4w82Fe8lhqV*WMX%gtK|rAd1e--Tpx)>z)eR6wemXOuVbDXi!WymRfd zzrG5>s^xkU6P#hW-oymYv9ue6<4sKM z&9NMBVgeUgZ~<1{#AyJR5vaV030zK~@+KxQk3i*3OyEial{Ybg1q3Q@VggrLt~W8& zRBUN)Vrtu30B|!K4iHcc02|m52I>L8!R%HBwg6ynVoJ6R0DBV?&~0gNVghzq+MAew z{g(D7Cg4U(dlM5dY-w*|0`5W#9C$y)^&CYEdlOU4{V0IFi3vDvDQ{v5KW!;*VhW$K zv^OyUrvachN4cz*0iZYcFz`A6^yXd$&H`8@;7v?-$ zdK1qFN#Ugm6`>tE$(xw69rcYH?M+PR`+eia@Fu31}eI}EG5UAm@=Lk z73t*t66b|CvDBx4tFfr0J_Y=5YPx+2n2QL8(dpJiGM%3JcM4U3v)w4LB~n zPG#)UOEZ3ys>Yx`6d>q0K^TsQ89GG}`u7M!FB6289B1e(LG02?`Q9D}h+TRK0w(~- zF1-ZCF~}~x1ZFVEF1-ZiFsNL52`*4Dn)DP`RIOk%>S>0zC>YIphT(1nqhTi)-mhSG z>80}E(#xbwEQ(3j!0W5z(o3u&5~XcC8T=&@ir_G*9!~{nB+xRqLMIzMc7t3n{W8nw zK|r&VB%fK7azEgN(Z~2^aSHV|!F!BvmM{*@8~YgFEKGS8n{|ti@y%5!TT!sE_!!?@ zokG>(S{Y>)aCD$u1nn9?!F#H>nr14H7oXpnu@&k#=j466A9 z0)Z=Nd}MW9RduMMWJ5`XM2X&2H|#D`aeAvw1Qb*z0t%6dfS)iC(34CA{Dg^so@64Rr!o;xNSO#2=a>ix z(k22B47lW2o#1)1Qb#x z0t&6g**4!LL;#xzDBv*>5Ll!R#?vVrW+EVjHW8?xG7(VNHW5(RF%b~png|GTO#}of z69I*66M+hA6M-Ay+5?L16fUZSP+=wlLKMM7z)xi&px}ijf(ew=|zh zc$B483}XsK%XH13s#+cOb*GO3(2>%nMhjP z-iwbdG{Mtf@6&|QNNN9w$P9SLVw{B0L{)!xmMNxQO}U$CXumTX;6?&lDE4L;wx@kg z@AF^6F~p~ER5Km7C#{%{lgJz~;{_e}kd4Q8Nic0^p zMlaIIt94uyMuTcyB&OZqNj_Vnx%6By^ClhlJrp(Vh$msSH(`#LcG45q;f>1`(|+KI zyV0(f+LJ40{mv8Tj6$wwg4rpvMIVs}VxorGHKm#JO)eUY|1 zZ|kg&Qg`uZ9Lh)GQ{3drCiEg$CA<+W1Ph%3+PR>2i*a z`?QT0)ABsYpSMd{{)P4|vUx=SU^=~PKIsm`+* z8>}Cg>~80D5T6Q9g^CfBr*z6o=%Pg2(54^3y!kJI$=3?%oPNH=NM-bG zF$wjaryGG#O@_lI11{8%G&Ts(; zY;^RhNgduI!TtR7YJl%bjy4gEE0^GNuk8?cmvYkA$O$O|ItG0bpaRz+_woh$zAcl2 z=u}(;zgEZkhVV5`+KO5-B3LHFqk%4^fFdG%TRCC|hJY@k@HH_wXYAJS$&jy^TQonS z7MHWPs8g^OMrC1i$LhD3?Qj6*Gu?&DuV)Qu2< z31>CKnWCckYOe7wBlbbWCjM2&Ccy^ZhZML`+$3mOYen)^I?h7k@HQrXWbCF}7R|v09q55i4DJm=)qL@r zFbb#-M|By8oId>C=|chap%)FD(B0EApc=i3rtCX}!-`O-B0}Y4q@x}{?-S=~AiS&88?|Y`i+W%=`Zb^3YtX;~or4%R{TYXHP*B>o;*Jir z8xh8CT9;oy3*nK&R~i|6sB2H>Fh{+`2|f0Kv;*Xv@>&PS1Vj^H$HG6km) z38wq2Rd0xvp@UKSZk;|Z6X_4qC+#LvP^C`_OP}x&opuf7#$PHLJV7mq8)-1Vv;gCa zmBqlgg{DY9taI=foz}ppF-m-AY+97 z9p!9o%%Y|S~<#^yZW2$>|df<6{%NsrQiSNO8;e*#(cEETGy`^?NM5gmn zS@dzV5bw3MsL7SeaT~3rcK`1O-)^r*d?q=(qX$oM51don3+?^dlppau?%NA`vZU<` z|94ykES2q)%`Sh9Es{^nx%2~{!){!a(nJH0p_f(}h>`wg;@c^s?e6Auy2tik)$T5B zMO5y42hCI_J^8UhkexE=$(w#oc%_ueoAHf6S1HvdJvn?BSijXonVgraYbfPK^i+>Y z&zDO>r0U?~J>T=+MD749uKrYmUYZNIW;?uIt%meHjA;?nkY&(VtPBJqa9x}__${ug zwf)%({7)s_4D}=uu4Uv;D*R6;bs;e!nznXy3;#0=n*;+o!H|!jo(`lw$#8&U8+*uw z(*G=@ETAAP6gTpJk#UiPYuu%A&oM3h0el{4X#(9x$$< z^1sMXBF75S%4`MtzAfslap%ban~V_7)}nt{}t|WIz_kaz}G(f|IYC< zG=jc=J!WKOd*=mlM>tOEVPVG`|54RcjVpC;!X>M)@ZZDHmX2QUy?s(8 zxR(<|N4m$kbo&X@@`mGsggq?sEExPv%M|MOKnHA$(Omt`8ZgBEsx=pRyURoC}7XQg)T2wZh8Z*Hy zSWJHFBFVr>lXoCdv=%-1OodvFwOEdp;r~u@JWc`8PaMVZhs*rm<>m^eRGZO!kC~n? zax?>ag;#T`)5fsU{jVmIyRqMT4E5W+a8n5XTU_@zpT8(&2njEEJIo{jAXmAe^m;-g$H&+uZQ_pr;z2{QhaU=mt%8Q`^_)^T1LmY zeA8=D>#tzwse(oOT>Vx43-RNUcL>4YHt* ze+RPBNF4#3&<#niDcYFu6$r${|D?!?3o%>?-JoqdGW`>vSd_dPSF%-?*e82NCQ+7g zDGsq!shL!2QqMr6FfxCPpein#ic9=Dm7GHv5>p^njodgS5Xm>8Nw%(TpV}CQdQoJ` zgNVw(E;sc_1kz69$EZpBE*`Qc^@z$@ptXE#Klsl$M4!y!obAXtfpXqUMNsZk$~&<} zXQ5V$WEznz8dKsF@-7u(;O7Ul$&N$8y$HbY6E-lbcJpK# zMbz8ly7a?N>A!<-|Kx6+gn)ZdMj}s32@T*Bo`lsjY6Upmo5CZvhRSLpkVkJVjov2# zX3zkBS=UiOhYVHEpvb8-c+&{x(R2Gh{m&5ToI5nGzcNVba^;`6@v)P|TryRpAzQ?F318czcQ8Bhs!>e^^|K<$B58*2@8E1W4 z??Xqvh>oZMXr=*}!xYp)6lBzJ2kUhH{pgUf?Nj8%&mAOqbO(3qv^>FLF3s?D8g+`Y zcc=-)8!ec=X@ugbow7tv?J5e;)b2uH?Eb0aUZb1#WpC@Umpff+f@w(griXf?7C|pf z=Ukes-|Gw_3ym32{h;vZex%l@8BqNgO=Bgy$mBUlgPWrhe#~h>VjKpyWgT7=8+;hZ zL+FTV&;e@DJf^RM)F7i?QP=fU&R>yCQP&MbUAegCiW|I0mtQ~){-~y`F&f-3y1^ib z>JkqVI!d*l(y5j>t-TSgRn5DX5^$Yg(y8`So%iX<9;41*jIOh^cU@N}y?8+Th|19J)a)o5#wnuaVic$P{UY^Sv7(oV zRDOz>OH{%1X;!?G(*k0ii5KS8NPL+_LMP~j#@W+Xv!PHJUm+>G1*v$D?$fpBP%qDH zMa^oE2p&C1XTk<)KCR>b(5TDo#(#$g>J1dn1C=>C0T0?ch~_~nSgr@H2?6|N(f6CY zuds}#U2-3=xU+nbFwgbys3{Lu9j_Cnx{Mc}+cI3vmwJ3P> z;2DP^ycUmfpFkR;CZc&~jkb8iuwr<5Lo{sP&{ zqp0Hse6;cZ73v^si9;Pzhz#s|SX}D(dp-mn>fodoqmD}2fcOrOHEi^-jiL+xZKLTT zP)nF_x`=2e9O#1F`SI*kEWtY|Mx3ZeN-O3@^8t=&!a?t-vGT2 zDr9stb(uiilL&Ym!9Kz1_uw0m!t(v)XPjXVor2RR?|0%2ZsGf@UuE1AYVPH+6u!R^ z3O7oG`L0mKz1=7}&c6xHluph5&2*;$gPl~f{|c(v!n-TVN)fn;hEQ860yh)8amaoY z8;oG9LPV-TB}8m2T3c8nA~KA#$p4-WEI!u**b4l|*QjCPmuUxn467+)!!FYfoFz2g zlyV%113&o~VM4VHwRI(x{C(0mEB9(hQ~%C}7F?ojEr1&+L6x}Oc$=^m5@`ByhwJXD z){QMK+l94=P(DTpYcT-<|IW2t{m8t8APbp!@P)OM;7I>YY?-?7jdp7p!O;}o0UI78 zdxdo=VPk~!G|F231K@lizF~b6zGND9Khm*aQWg%M{j1s=dqpsLBa-r020EK@D8YNq zUHae7mYg?;|l=%48S-tuNVnT;xU$y_zGGP+u56&lOv3zCs0CcD>S2I zA{!AG>cq=sM#>XNBS((zjjKcLo3M1euaz39)DhfTzBj&a50vIKqN0)&rWpUOW<7II zbpl^(zE>p9TCY?xMjXYv-jUXM^dr)uwM(6Jdl)&7TDf0mD5dV<&p7lL^$;CgOkbN>3f%|eEEVZsk#EH zE+J1 zSITVdZxzO@1YmvxOk^uu>St47a^%!CLG`^UW6owoe`uvCq6&1yUj*^31BpjtAw`M; zG43NeqEjJ_oM^s5BO2F{M8XCg^_Y(T7BW7e(!eDfiDcxvQ;;es@6x{A(MAKV-iXGf z`Z&|VV~%+(J#xq+Y~1U*m^Z!EP&p_d=lhC!P=G&rJSq24@9N|~K&@~Pq2^NA#^rFM zv0ceyrfyXE{u_y+F44f>0A#8h#%d9@Sfit`YKk>_p@>406pyFiXE7i46f@!+ zBh(a+rzu`}8BH-h6iTz(PXMNxfd>fycT5t9`8|NBUAj8@R^}{}P9rq{$u_9*G~rP< zdlJ!=m1;Oe%$?pu5%p>~A4SmvI#C~uIi^!Y#p+o46zDBZtcaiD!Nc2|JhS}wqub*Z zTXgTejHV_h>`)#7`r$ieBwhmAr~imVnY6R1x2b!#&=3FK1n=Dyz5*kurx6ldsNX<- z0$vG#bxr;H78=PJD2M(d>Jl%*gZ?AVn@Qp44*sPHuAh|ec|#O}CVk@U$`6#I_VzWm zcV!Rsc6RsR#>!Tx+!=agG2r}H@F6gz(HC%LzJR!~F5sk_-7ma=bNhopyBBc&FC}`< zo&Ne31(yZt(khP*%?FK%M?@sKB(?x3K|V~j{{p` zzXi*Mh@}2Stp$D2zb_uB|NqZB0!F+s(@KbvR=hDjA}$3)H$y~4tpoz(nhc6v9 z6mOjPVu7cCKf#bzR21-j17KjBO5`t1ScU`22ug+p%8C4TqTo1zXe^LOPilZsx&~wh zvr95&rlNB0QfEGZu3fW@e#{R6LbOb5@Xg z=PGXfER>`xHZhO0KQd@wa&vh+=X`X~z{|HIt5RWIup@++=QPh#+#Ra8OVCPBar2{$ z^(izanQk>WKc0jNY7kQ&)xdqr_KVyEsy>GTFrh@D4dWvy;{x4N3=Ab$h-L_CpAd^w zizv}zss@)RQMr`SE_bO1fl*(kiWTD0MO@8t)juItM5^J8iU)tm8>@SIwDMJ*x35Z5 zBec>3Lm+wDiXkg-!OPNUehL?34Xv7rpQ2ejEydmxCbE>!4CbYE;!B=1yF#qih!{1h zLaYf(0V2b$O|Qj??rQWdK}l;%T0~erca{3>g&9yyiBKy;tw5r7o*1k^MK@}hMyh2R zzW(ghHjY*sR-cFHxr|tQImCHlcsaz|%K_`r%N!C=D-n@q4xTkhydp_26{h`Uu)i<$z_X z0k;tsE@x82SX9tB(zMYCRVwzkjzqqN_D`^AmTwT=fB^QRiyB?Xe|;Zc(jw zba0%dGE%PfihXVXZD?vzq_;5&71Y}-zrizFlxvd%!wp1*g}A~&Qj!ma3ovI$g}71= z4~YSEDWt^O78iRNk3^$JV8#{8-5SO}F>p;`2(XjpFoud0En$eLPN+1k;V2>6T*P~D zV3*Urhd!j(Za}f!2!{bO8?(aMZcwq^NUz!xWwYIA#dgPem@AhNW3$~@PYjcNoKu3C$ZaNpi&X)v&oDRE`lCm&)0z+XveP^)KuA{yL^8&qaJnH$}qqPZqqzx+%b=H4vjnr4t&)76--C_|Gy=#We#CBjd@6a2Ge}iI(D; zK`+;gw7F)K&DO?XpFAZl`*bQ%%+tf_P)WREMX@hbu$CDvJ^q{M3e z#H2T)h(hd|@qD7k@&bg2hZ8dhZ0yi&w^^-QM$BI_}{4jdY^eoFPZxy3B z3ahs^&&aXYFEM1|ro8usHtQ`QY>|!Tr^ur@@M6v6JZk+CJ%B7hmb$G6|MYS^HQJZD zOmjIg%@y7@*qzY2S)Mz(G!prCR$^)ws=2IvB3XfAh~S!vA+E9+qE>8a5Q=TySYq?W z)gGn@f?cCn;#x1Opp05$6{1Y>(sFk=RR1cxT~=eNd!xB1^H7(l!jcdNO#{uE&6HRY)`7JH}e~_PgG(+Z~ep_b@ zcw(6CMc7+)=BgyKgNpM-+R9y&L$0hms5y_;BgayHTzHDGWfkKlB!Z50$BMu>4+(NZ z<86{2uhy*I&LntvK%$BP!&L#2@5!EGF>@)lG)T3jLE1k$oc1Y-PfHo@D4(t1jMFQ5 zBJ8>>rLPA^kFXj@%wSZwz=;kQIOD?QMU0w-Sck3i@Wkmnn*YapiU3uOA*>u-J<*=d zBwJTcR=PR~CUt(xHF!qMbF!!=9ooGsDJFW=?{v3aI0JPj10u>@M5++HiDdJ7SOnaa zg0oLIseKwUO`|}0VN_)wykH!NjAo!1Ezby?NuVtWX1P={+e1a9<9oDn=MueETvjM&VW#u193Jyq1Fyf76H1f3s-K+P+|Rv8eN zxrl#|gDD-)?_FsDd!FH%eOHa!n(%fRO zB9zX>rUH6XJl4nzGFC5xdJ4&6s`hGI)N)^uq~ z6=NT4vPv}Dr5wB~pw|M&KqFK~`Od*0bU{Vemnb@SwLh#X&x&<*ztP+PRtCGXM7CI4 z_Q(;48_vDpXuE@FG4aT1>x0@7>TNWMm?esjXk7w2pK7#wnrW+5%axk6!jqnuN}kJy z@}1GUaIvrSG#+ct-X;^H1L(0l5LoDGJku%^Kbw-N>qQj8~T+7^ruQrtBVJWc6#x!qS>~IaHMtgO^v;otimp6bH zxTd_(oItN6%^0FmY=Osp0WTn}$HM~@2k^+mSXa8yQj80qK1KdeTx==>KXAtf2W_Jl zT%t>^P-5Izd+jDW<$HD{S#oFaOh!>PbD`+Q@%hZ1=i&G66+BW8LLID*uYl?7L3ZP)NjR!OEbP7uV#tmA`3ltk$NJOc|g?77Y zNw{ZeSagcK7mudqf0%fQ#9T``4~T6kM=eBEwxyg%JN#(F5fDtTQ66E1Y|)zVxyW%| zoh(KXwug8@y0(!!-lL^*RwcqvV1g%xD^!{zRxE3d>QvX(9m8c*DrlK$&OJK7CD=9@ z!hVjqa83&*+R{ATmUxrYq(EbIWsAKgNQ7w-4Xsg;zpXENh+pewwvmpwCMcOD81168 zw&)VdOb_{MMbWj&IbueWKM2$A3ze!>MrTh-S|bQl3kds2L)WQ=nvyCG*@9@@Aya&W zPB9$84I`aPpJ5C;*SltjOt2zS9w5mV6=d< z35+^dqFT!52dg!gMfqx&aoAzE0KP!p`c>^TaNa{>UI}I1)0lF%OT?_mZl~vsDz9`w zWx!fDnuSz_2}CTse~zc9H4{+k^2J4>9&uKV!(||N3Na{KEoK?x*^mBRfoLz~czY?2 zSLe8NVCwM=@*bF?!}fuxW`MBxy9b>qUQR~VerHXj*(_`VR|dW`kphru9>&EiZIZ30 zPxi#{L{72wb=TU@Ii`AeD+-?G-9k)v6mTwL1{Z;epJ{9QP=Ki!v%@w0IjB3#A!x2w zbD!t#11{mQat?6kyM3lTNv7tsm>L4JJf(7TvfY+PMU9J!j-px4aWlEdTs^X!%{DGE z3sozF&Ox2QUgWMDn-eegt{iX@cNu}3D8Oa^(2iY>Pn%6DnaK-UvJ2ou)Xu3Ik*6yG zX<(b_t|e?Su?Crt!A0mW6}&^0GwOt3G~aNTGnj^l=|d&9l^o5vpb9JI2ql9IQSW7+6$tX3N z&P7>2P*T8a`bQlh)meSww?#p85NgZ73x&g0m!fDSn>?bAyVY!~r!DR{gh`jy(Rdo2 zHW#U=ahtbXd~Xs>(<1OHTas>9&2^N44wZ(5&klQM*y$a1A-Y`J)5F(Iqfe^t)w&57 zVbuhD?u6(R*NnnH0B!8EMG+j$UEw^SR|-}bm9o3B?!Qfzm-8B~fr-V`)v z*NhfZ*Nzrs*M+43bK2{s5MrMTsB`T72EHSNf?aV(GxGjiO-ZT{N3fkMJbaz`w`Ftu z_c(+_<3^okD{9b7-*c!<(T40k(VcRK>Z#14}v)3!~pc=yhQa@B?| z=(=VnLJ4tH9r8KyoVM6LM`#3f=pvfng><3$C~Y)tWgMh6(F0=a_2CDx(XitWMSxx} zZBXzHhPFKDqCNgd#3QCE3Z%t5O-<=^rIC|KLN`Gz<(cnIeq+tH9(U%7St)W#(}d0ck4Tblj`%Z7G^r{$7UNoNJ>=z0obDhKI6`U=9ze- zPU*KE{;S4mj8=O4eGzwaupOH_MbP=x-?z*-`+#tFM;bl*5R2&+hgjShW-4Aw3=dJ9 z&6mB$S)9+c$ar^^_6Ah57Uk^dIM*bjw^}^~+Zn9{rs`qkmZa$!W?%yCLngXQ#9PYA7%NuW{TJ!=I##a%ZUiVZ1cVyZ_BPE%w&-K|K?_YAjqW%|@h181!6f=Lx<4O!;~BQ_!R?1rIIa1PdyC< zA6mhu++_rdyzPP;qjx2dwzFjPnq3;kR@td{Sy&nf`b)#o0I}Rf{5`4bT>&m1wwY}} zFX}W<~_=@7j5^x1I2w)?^d8;WRUboZI1^4^%*9~_hjE5mtP_R z`)C)7l0e%fK!fD+>)A6-^RABRp4Bl!MG%?JL{RU~yvBc*l!y}NsPx`rT*?b$gS}Q2 zQ@q3_6}5kvA4Xm1>KJU(W5&|V-AhK{Mr~&pd3bGCM@>4eQ;tn>k&5D6UlL}7_Q{=Q zY~z$F5;K}rc)V|*uMyjdzko%+cBK}6g1ahRmmANBC%Yq_qJrQC*q~fw=DmU&Q|%Sp z04J(a6z3x)O;6$^4^QCUPFANAQ#OOetwH9@4}Sf}TAT z?!IzYA~=ax=)hn(>JSZ^RYgSDu99vHc?lS^gDF=LG}-Rf4I)y-|2@8;WgGJiw>``^ zMpMaDDidnCB9`ecJ!w{<=xhuN5apV!gss<02(6#%twX;JpzTVCg~+sd2Q_FuB_{Hq zmlh#BZ55YXgLF5P9-19Sv14--N}_Uk1gw{~$D+f(%X`8Jz!BUqM!M5Wv*s?053riB zRpl%br7CM#r`g|_)(~5C25r&Fa+svzKX)WV2W;2~yC#cpL#sQdZEJZhcN<3pjANkZ5%L3;Z@$MLF73QK|cN!Exlc6bgUdk5+wTO1-3 zcicQj(OSv(t{9Asr3ORyCFmKANHqshVND}3^)K;v5;r24f-glh{))|)fj=}1|3=aB z?4FkHu57*_Bop8K%EY&UGTYkwvU_`)T&x?S_-y9@{l|g*8o%KinWs?z39umqea?b|1z6 z!ACa5Tdp~W@H-J@6yB93clF(NI}qn0`hd88*Wd;jon_6q@6qdj_EkBluR%Vu@3dTY z`uvLg94mX|!xi&44rn z?aUc#qHM5UE$?5^wxrZry2)BlYWhK}^fdufbQ8IbLB8*s_K0}icj9bNw8+Zt>IE_2 zJBA<`{PDFgm^HKn)7Rg-m1Z4(1NbBaQwt(o(g9#o1E`CyOvIIjDm#_L#D+vR-BD&Q zIZ>2d0K%$9RUy7z*wWbC8zQ>w+NtTSt2ev5tE0n%MANo)^>ugjx2bFn*`YYPk_}k2 z3>WfX4XbwL(UR`VZ12SVJM#WW?dfp_* z*JpziPF&k}eO=|yX3)ca!^${PdfC8;Ps&r*3<7h?H&|W@=%s7Q`T>5?S0>Ly)yrr5 z`gRhX?0fCm9$A0lOz$SE^3uz4kI2Zf+VcMVf$ZyLr`5MEKeItj%Q|0r*%fP7^lx$s zebG0F@N?JXRLWF=5Tt(M;|IVgW>o*OEccV0Ir ze=kmym&^D;{N&;1qj&}f%k$+&jp0}G8_EyJXUtcD`=uN#|9a-iPhBC?kCi{vpDn*` z43=-&AR`aUfvk`IeC{vh?ksDz{10(hj>8)4&6DE>w=J%a{|*FJW#7?zAG&>HMS1?F zww&cFE~DPcE!L~_?7!{gh@A4KjP1MK`UOVt+||~ri2X#&VF3Sqbv?p&#?({FKw036 z&;EWu9@_V+%(q(mH}%VbdO6wRNLgoP$&Ihdd3|!jVfj^ImKf%$as6_pm36RuWBE3D zw8tv5@(W6~FSck#ZoiiJ!GFnPD%`LlAK=RoS@Q6;dGe>Stf5@qeeGbwF8M?GCWdMR z;c^+9htxM;ORN2~@7&>nhRX8x&E?s9t*5Mq+|KFK^d&y zxLNKTwi-4f_<1W)_6*A;tG=wge2V;@u*M%=SW?(fJ+NWuLzP3>vU|{aSk50lyjboo zE3(nshq8YxyWT|1Jge*;kVixQindKMu1sD%XwFN#)ym#9aByg4k9_62bKs%5>&|by zEx)%xKDzI;HC~?Cnkk?WyVqSgx8tue+RQNkotoS6F_~`8H>{M^>v{&d zw*PeC*8GjvkF3aVKO%45H;AGCA2E1yd4K<=w#@7$sQ=?TPhK7d!J9C_{K; z=P<2+-&*wz71^@a>NB$vhK7b@FiUQ;`i4F!b6>UcmdIUY1=oMy%u0Ny0?jl6t$}M! z-f*NG%UE{53i@reb}cK|X5A_y2hX2>L_V@FPkvj}Z*_Wg0P@L!K_I`*2_7F%tMseEbDPeL49T3q z1CJcc{~e8&+(QHH3!K1jz{&_%(-_-HurF|qvGoC~;aT}KX7p&A{Jt>f8S;UBnBBh# zGuyc5yX_~>AAp=$Cp!nN(((p#X=3H3mL=w_B)JQT_F%xRx8x~t?#L?*=g;@bsVBbn z-P|>oo!nf$ac909XvIJ^JPz{PeeA8w>}=WJDrcWlDe^bw=C^HVkdenI`c;meeC+%) z`Muet`Oj`1di3Oq1)Ho*`-!aM>QO+0+;eP5P8mG%ZvOd4tnA)1GWpzVR%U+xBUVC7 zzDzrJW@Fnc`7PN;5qbPmmxdmc@o!RbZO;PniM=-ik&I^Q6q~QU`N{|7gwcq!(TH!0 zb5`HV=er6wy>aJTEAnNqwP7eTd;1Tq$~9KO>OYm-DEE|YK62z}C1&NFZj$~Vjy;F) zyWPYJhGGXBtm6Rxm!pPa`w;$Hci&E84EtmIHl1(C%wB*3bDtflK-AB=NhvwV$^OdW z-^RQtv(BB*`37Rocb`D)$75eb_;=lX`40iQIo7J*G~|<*ODTWT&FoM169f`sV*_u}{ z|Md@bA8(Ms)6b%Um$(Jba|>S3E%+i@AeYt4vObw+wYFJD+N`5PBRL~OBO|iH%CoYq z5xL;ByxgisAc(Y4d9uGuM%A}tRqKX7(ruB%3vc+horcTZr{w|DI$TaX47_-lICA~4 zoYN;a4a-@5@`_v*NF3}3k z^M+xKXW?}+Fc=uB9BIHT8zVH;fmZ&Nx9=M!q?ErB!#_vBlmmkh_v0IO%DW)^&gBDV z+{$TH4wfM+2*G5&@r#>o{qS4zsq4;NZaws;qa!!4E+wxnJM;RQ%BSS)V{&_*4CaBg z?z|kbuV!0CY3XKpRhI0t2IcH5`AL~&9q!+FX7i<$@}v7&@32ljZzX@jT4YTvUs1k& z#j2$%hX%~KX`tLJ862*#c3Ef2SID-!BUZ(b^|kf#()tk@n`O>Q7%7rv*6=oY>)tmj z)()7{63~^;?ISMmeKE}8ypsTaB8Dql)~+0S>l>$T|K<&=u_UiLx?+{JaJpL0%^S{P1dE0eh5C1`lb*%5Pg;szQ2s`X>J#9VAVyrN!u#Rc5Y8kx}Pz0_e|7%A>jz0AyY0HNw@~u0%`DQ9HS`+= z-Kye#tDuqVXsUj1zKL`<*5$hhzmvPpKBd@fbwA$tPH?1_e+bX+i=j#<$T5Ttx z5m|}zbF!^lA;P*au!%RyN$0H3$lZsF( zLq+bqdgs4gb{_O~Lhfw6$2wXrqYhimN93N?HaYR|z1`amt~hzLLPmmIcOM(6IQZH= z8EcijhRPfATTaS^bJoiIHQOID>yTar*RbWM7H6 z9|Vp8e0X>L4R=`O&>5|S6{JJG6rkOFe)4nq73G(RKVYNN~+>O?z={5QX8Wv^(sN;X4_8^TUP##nEbS6osqm*kCP z%T^28K$4kh$Tet&+zzTTGgGX4)^B>_h5U_j&0!EA7SCZbGg00HGQryY{RZe^78U@& zzQfj$jq*0*%|EWbs(KF;+jgrmKU;Pj!ZHYz|M%D}*4jj1$0pC3Q1On#*=kJ*!ztV4wKiZR1XhFkU(30KIR=UZ0Enn^$ zl<6m4U%oQeqP0P4{mAAsBl#`hxyCtbk2SY+Re$-~25bk;U3X00YC=7I`?`90r)iB} zQ7%8Wul~6&TB+b}M+YpL@IMC20DNSith|EM`;UUFe_0G-KeMvo2zcTRAGzUxd}psU z_%SOP={_-F4VEL>Z#dVj17)1)hmph0GV0g?`Ov=8*CW-h`)S|!$;d&3f8MV)0(VB9 zleg_X{93h@{qgdn%`3Cp)}Cyu1b3Z?74#{ZZrSdC#^R7TThaBWdgXHS5KGk$0iIYbCf$|k2n=oU@n{O?zu<}PXHw+zxY-nA1 zq~9uU!Pt*~y;|<7UkRoCiu{%r&X?vNe2ZETz`;pC{;Jm+PlR$ubYCS(|9Nj-1?@rZ zjPCm|68XCEgC#{N|Erfr5DAg)m%Su1J{e8q{|lYx_UOKb{0~D&{o&Hf7QEFqRCO|Y zWA2e`IdBY;jt@Fy=Lu{UA?LDB(v%xl%b3&P)j7N6p1va=8akQZOIW$HUQT=U=<<~) z$KrluEC{`unz7T>-MM)rG%?dXg+^`t3FN7rK-kStO zKmuZ|OQLkOCUI$NYoe%KD5&NA)dg@VZx_I>v<+_EFsQY)t-tS?nKRG5&%FVx{ruj3 z{{QzXxo74%bLPyMGiT16nP={mGB>ajYrA)4Zs(%f4{?7!;evf}{!ngdXc8rVM}H(~ zawNTz#Ha(qK04>X`_mh0KW7iz76{GATau13)mi(vy>vj*ZLr7Ewl(RH*4uuyYyCD2K`|2AGFW2CXX)_^+Q{* zR6_BNJ$Co2(q%>;rO2vkNin?Q(jn1qrx5Y#nojY?&33S7X4cHoybgMbnAWrgwag1j zQA!_r$->;VlxdM&yJ*m!fCh;_t{W8FL~x4u01>Lsh%{sb#n%M|2xt;|KpbATvr{}I zc7lN}@%p+U=)PY(B4{mla9zLn28tY9m)0!?#Llgk*KQHZ6`v?uXLld!6z8Uim)F_J zrQ%7kQ?XPuDE^9C_lUvV^hsjurdwM>ScHx}uqguzPfY6v9-N*r^~j=uKiw)@3TAt} z=(F5hDc<$yS350zNhyL#^_b>MTT?q9qfz?P#+=6>nC(e9Vl4&K4>rIUzkC*=J~w8xl=kA|1KO4j(#`iz*#!9Z4l44OQw{+BjD$as@NE+Q@RS3k zi^NzvO*E&7$$t3aW5szj2nNCaclbNSqw#jy%RkDfZN9Qs2djqSxpV&SO8*}1j5wxrKUe?lbWh}NF}7N@3(K+X#L4D0;y zox3{s%J@J1+?eIL8-G99a+V_9)vc|(EDeu)pKRbg!hN7QyQ@Xd**#t_tb14paBvVI5=gcBc zjB-@i0V|Z^8-`RkWSoajW zbj7tZ+w0-*r-Sl=(LL$nO~iG+IJ$Tvsew=8ubqJ^vS>(NmxjEwQX~gLa%1Bb zOr)hNim%H+)<((FN2C4XTY$V`A%*I%N)xY+PU#~i{~jbJx7ptp<9C9|M%({h>0_lL z(2ofE&QehcHqZ4Fi*;bJ)*gJYQ+(cgpwoU`q-?@p={It(-S8Wdqjvl75FQ05Ak>BB+)=? z#16Y-{x5dC~P)W|H(O(O-G(NBTG_&u}!Y+t;m?kh8wUO%&O zVRI(!W5S`K9{aV2Ci@3A z6XR;Py2>W}=#uN?xMob?R8AD=9&$|?Fe8scpy#*Lb7Ga4U z>#Yl9=oK_&#y;;R`Y!n({T69_U%_^`-vYGpD(xYOM7i+nx zcIuR+=ne0m=nvjK!r$N8Z@ebw87nSj54`#BO=$~lE`4lDTbn&@gFXJ>=F&q`I(FFO zj&zoGPmw!38)e~f->}EO4)ys!?&E*9!{0h1{SeacokGjK+dFcWNss5-68VfHolB=6 z;5x$l4VfPQ#%9`YJ%dJ0!=Oa`k$f=W$V*C(NvXYY_E`w~0220q4whd8FNHG1a_lBZ z;DR*z!YGxgWi;4D$!_ItwGSfYMF?c<>-KE1Hf{FQeO0A_ys8zoluz44UOVZ?*3$YP zOV9a5l_4%4grl>prgp~EkiBb!xDzDKppDAc?I*7SEqT3AnDK2s~6X$S0BNu>L9vv8sdt%D@4c6g`Hv{%{mXCLR-IwJNz;Z&?krPuRAs^ z!=oOV_#;*zPi^Smd(S&m3yxiQtO7aEuvVjt>*$Y7gH7#d(=tU|b^}7+lf58vIL@Y3 z#lvg-fn7-cB93gsLu)oI+bd4BrV%0Q8Ttb!mA+{CXdRs87 z+TD3rp7hwWZk$!uEndEPlfBSBVn2YU+-s%SwRX3iYVQ)izq#v}xZB$KOB`QF6OB8? zI1H}FG%;>SH0Fq;pmoi-?@5PVv=512-#lbpJl_6^cpQ-|G_|45-b!rluxruz-Kps_ zteHu*)-@AEi%nM1Yt1+f`@RbEA*mxgh&ZiZT#jFHg|I7z#3&r( z>Ux>XyEU8si21bAw#4;>fmF|}C0hVdsPT3Mkmuly+bhP9ZIp|7924s8tqs6G8f#CL zYhv-t21xAeq29WzI{S4ycM0N({(HK&i0vEfowec$Rjfa5t8l>G4(tT@|FZ9)rCY5lCStSBzxn#SCIn(-4P^+8od(yw34$0KEZy~mUN~t8 zL)bU$vhdSu-p)y6gXxEAKiT5$Up&zU^Q%ve;b(L!)Vk1R*jy;mg?H>R7!S9)NIF&* z3AVZbYeV%_>gc4(H?S(NeJJ$|Kj};MSS4Dk^^vqNV~;1sY7>^U(hi9TD{h`Eia4_w zYEj2D@g&T=8*dHSECXfgqa8Mw_v09R5C{(`5aDK3xeV@qSk@|3U% zfc*e*$QsH8*2ql@tMc*?#eQ%z4*u*Er}}Xy4LdU8U2hJpqAdG?()5FsH(#o@LtyZyS%))~1zoIUxx zY>ILftqY_(Yg5eFE8~zdJQ=dConU9&l51T)!J0a8K|a2Te^E<8`>DIEY2(DFu=6_g zLu*QcSOW;(L;<$^eA-VG-#OJzKD0>O8uW|zaCqac;NU()3zpD&@bB@63q0|TJy0zw z4*=)$z&Qe(o-mw0I5^`D^okDyIbt&g{6~QvBJ(Jbxnm5Gv1iyv0%BuJSEt?m-yi2+ zuAMun0tLj&s}KAThX${yvwwc+8te}Ht&2|&+;dmmZ~Izdlb39vb6f2=4nXo6VHMDf zJ0cr@L|o5M+zL@|C)3#k1d3_Z=atq>g^n+!^cv|H(m^V5>QHSi9fJB(BBJ+*>)Oe4 z?C}&F%oBkg`z>jlyQhg(yC%2WPRcH|(+^^s@^UW>8;%Ny2T$wyD>ituS0h&G6C2y? z6cWV@62;chLw0Ywoj&7W_KLR==jaj%K??3X-M-15nT3-K=((;23Msxdp8S_DG|)nw zVRCnmj+e_#oDjATl{VO$uV0#HpP^K|+0KF5Z@01ch|uwzpglI-hoE%2Ps*UinmRU4 z{A4|t>9nhfnWwPN)!UBwe8#e@Jo^bvWRQ&d7;u#&zO*5DaM87kWO1r*+pdRxuCSVd zsOj;)*u5Qu_rtj0t6vghh%w8$G@-OJ-9B&nO0lc$fIV&@txD?b*TjTD#3UrfMdM35 zb6*3F=%^8s{Fq*LmXxOdAb1UKnHhk7Z}zTpTUTEjlFj*xvP+ zaw+xbDvAoexp|}b{^}vxxgNYR%`Ua;tP4(m!w%6_b-H~Q#D#;PHU-MQ9H6ko>tjg3 zUk*qCkJ(9)TrXTUge^WFAV=|!7CpcBW;&{JVfJFZM;m1@uwNaG^J3$&w$0A~j+ZuP^M10qZINBP?MGruQkOk0 zzZnM@a7@yVzl0(ls<6A@EQx=dlUBRjKKL#Sw9IcFBu*^*$MP?>84lRJrJ`uiF6|U| zRrJ71s_V6`JpHb_P%RxO`Sm%QL}FL3eGnSbE4EbZq0B#=)734$*Vyw=asKoxr&(8? zkvj`VHuoHOxSr~ObN9J}oqe#_{qKp>hPIRz&suJWM9G1C`~Az?#rtC^o5T{|%`?cJH!Tp5ca8*>|1?7nV`Xvcx>bb+C|7)NW+S%DgS zcT-qayi_(M7xC#&5C@WtZ3NAyKO{8T(Y`lZhW>2nK;pCyvIUJv5g@Dw?O9)`d;T+U zo|FXJXs~$2Xc^)a=cEv#s3(_kq-dvSBkA%KTZmMYR((A*7;|Fs`U^1 zJRC(DMaNc8?|HV(UUZO}E#hRWuqmuuUNAT|ZkwHJ_g+e89eWmDhO;GKh1ZPEu1m3d zVGVHV277ebc^{=`&76smC6Cis_BrCb!6Thp_Tuy;{@sIrBKH7J{?uZXLPr+8_Pf}M z27d=I3G|4&Hqe2TeI5$Ic<+r1#@X)?mkS2$W6LNw-+@hd8&kr225)WwHr1)|9bvS5xsHAM5M}i{&CQ4X(Ht=T|1SZV(F!YgW?c#W&D7 z}dv@h;ya`FykZa7Sl?Z3`>^KfvaxQff{@Ra zfg{Xn}fc#MwKq6|kn@P;{*SF0eIee2)zN56DJon=M9q^XuY?lF53 z1vf1^Cnl16)L>buLVSDizwdMaulhW!s4IDNZAVJ8da^5JWWJd>0fLS|n zgrXM1-T&!QyggA%|Li_72IuF*BV+bJ!gp6}!sPM6IW)iBRzXhDyXWj&*xvcrRPmYi zLAwvx?>CTBdhd9g`c9i^(zi?Jm7ghxwFXvXoan^Kbny>Q8eXSBq$`IU;}^*ny#=p6 z*}V?{WoGL=I8=Fs{dz-gpuz68t{+!8V<0~_+q!(b>g&Z&zO#q+!tunkiAh8>SZOpr zh_2N;?NG+0bMeAPEg4#Pq(z@TB0@otT!VF9s(h)T!A`s9>476Sw)22kMMuYNL`v55 zi096N6NCo*xk4U?+;&bH9n1{`XCdzo71YR{bI5D^Z3TI4+u%`*?y76czGde1*5%TM z!Xw`&-fbJ2Ms1S*^V0-cdzwnYSJn@brq)3(5kGqRX95T1Xc_7K5WY2 zfKX@d66zZHHphrK#O}ykkFd$UjkrRBauhe()5K&s{~%JdPdvM!AM4VTZAw5B#0>~^ zb=Z4Cc$=dehdK7(ovHyWHt}*JP6em5bz>IZv7x7p-0Por*qiL$0(d5&0?@~i?Kmrc zLT+`sHD`Qhr~Rd?>|cKx`QC%rSp33UfGjxb$v6gjVG>TVTsh&0eF0t$sk5>Xg71Mo zt+_O}_exk|vM*jykJFIi(oJGXj`+stJ;$Ne`_A*-WmXN3UTm4j83sGO>p7Y09*Ce$sc?NO2Mtg6by*SUh2>mc~RY;85X=P3vScI5o zol+~j%^*g@BgV2=bqHL)zl22D9&AaAwjL;$JyVedqbZMrzIM`SBmC)Y3ftgc2 z_m!ohpuacw7|w267f&2mGIiSWhecA4D91$l2G)@ei@Kf%#og=e{+AZavY(GRgZ|$8jwLzQ- zrM1snVlNZFUXR7c%&dkm@A{kYuAkfX9r5${;1C7j)}}qZc{9R*=PYK5)Yo^#bF^5rri zJ1DN`7sYAzl7r&1eo@jdE)5<$bg<#Rb}Z+`;q`PF{Q)jU z&6c)|mO?)X^~?>4_F%~F%uZj`D;^(B$AvFWf(b#VHu270mP zs=2!tL$BYOIu7skTIZh;y1Q1qG|E1Jy@^mQ4lf+Qc}Y?07t`>H*^ChU#_C>i>P|Y9 zY^9IeEB?>T)=V#6cDu&gXDGquiY~szT{2Yb@xC&@Z-(v3y?ZqSM8p zo72Rv+A;7x7>%tCA-)}?N#>>a{w6Vb4~{+7OcmerrifF!9uMukKKBp~HLf`_BUCSf zsHR^WTR&)L_gYgi2$HhX>+DB+_jPyn!NlRMs%1T53kGd7y;*RkbsbKi*m%3bx^kR& z+roR9S+hc+>+|hW>~V@cH`Rz8Bd||+Q_b58^1mP+9nmEY-GtbBXX(S@o|`s_cSiW_ z40t_ja?X{HC2uU5D4_#I5W7;*EA|HEf7Doi-2Nq16j% z5Uh1J*@}b=HLwk5L3=K-kHz+It~_uLtd}+=0%{Q0SYBuE_i8 zfc-|GEtLCRgi+-2wb4D+<>;jiuoBjkB=I?{8&OkNJgS09?v&=_1$i!WXCSQ`!rY1| z%0be_zad0$@TNgTEAf)a4K#gKEU!So74 z8N}8{r~qe%aOCV~F!ZHMLgG)};AU}1Sh?1fgdij7d&p~ zwpE415ca;j1LD{^KMuRsh>b!YAyk9VmU{*>NR-k?Ay|BEF@3pMGnm#A{L3l`s^AFtu;7Rvh{ z(TdiNAa8vH31&na{i&`O12@66*%yW|4Ua|LH^MwpnjEK2Cp7%>VQmBdKFsz=V=R9F|v#une@Y^cEy-)m zYdGjk-;^<=t?3b40m)bAcXV{n6 zolCGe&;yBGK<~45;bd#d&^r4(7$$pCx;-vEfBHg^fF9aDU|l#aqj+_9cBtVQu}{!z z*y7ktJ>pMzdl)Yhi}5M;(#L(YPdb0_Me)H+gW|~mh~|l(Cl1+9EV~i&Us~JZJh2zr zo@njEmwDyA#zjuG^UYN-%F>{u(Vm8J|(wa z+^}arzK45k7v2uSocHj}pysjiy}9CHFC>6I?}2LfIOIEU0fzW+-5$JbhKb~_3hA!( zJ-uz>fks%zuVFbb7q0@KveowO;w`)kYbTYa^64 zEyHai4S31y`u4z;_6k^&Ca^uWrW9sy&mpu4@9x8};jM%m@e5B{>45n0P5r(0gRhCk z8tdw$8Df0TKwZfG**6{_7i49PxJ?Xhv-jHP?b}gnC;eEQF=S7k(pj2aE8g*d&OG=z zGt$HyznDpHTKH)b|J`HQW4gv`x7uH!|90#Urz0$#&|`nqnwB8Gz0S(;ihD#4&e2cJ z&aK_I<5=iEJ5#*3c2FD}XSx1{i6Lc{=I~M`;gviziR(Le&dOFex$vJ?C~?W zY~`OMnY%`yNp1Gv<*@Qecq0Sh>C@n~^kyI2f~W_c#miGySY**GaHZ{kd_jJlJ$1mY z&b6-&1rBD@n}bmBcc;SCLs2&`c~HK?K^-OXF|42W^dH0P<8)|sTXBOqY?7>6@1Dy25vzuX9C>kmoTuG(u|JuYizJtBaJsN$HE_-^9?aXDF*r;@q` z#P&u4tL1c*NN?%X63QiRW=@c+07 zJ++mUtIO+~PAmiGAOnOGE)Wtya;6r+IB)*zQ@@dauR70!cCsC>hH9|j|Q*nTs%7cMmc`GR# zWav_)i=|S$FpLQP1(yExapkEElm$X9EzOcuYJ|S!3tWdEVL{S4!V*I(4zpHV>3!%Q z_bx?@NL1~4?1s+Hy2Ytt)E?}oq|BN1SSVyaPsc5L=Ijk&MynG^)~B)f#hnc)H}#5k z9Hrb zF8hk5*t_aqwX1F^opbCs5PGKbvMsa@{yr%XK2|?we`R>~$u3#_~)+X`Dhiu$oo9pw!Dj__G6D% z%&HNYelg2VUW#*_w~^6+ zOze;bamJg@7m#ChZm?Q}4&aT(o%Dk8So=(hJ~!Dp*lNV;x&}8*97w+(;Lav70XNKa zBCwv1jmsJ_2IslXgHK=4lPQn(UD@f^h>SFxm-bH!QJnXQ4Y+~lz^<<@3yI}JKf;+g zKf*PyuO1M_M#*sd4YTmx~ z)IYwHTZ+ZXSiEV9vn~5@UB%`y5gNq3a=6g4en?z%K;-Tb z$p;>PI=AHZ)`4Epd;pzEG46>yc-!B)402ux30t0}|6VzJAhFdLE=ppa23bedzqyWZ zQ$3}zKESn|4QX4RAO3r5`xhrj+@V@s$%~njH4$NE#hk;{qd(cFwFbX&G|JmH<+e+o z5I3friD0mO+Zk=$+3)Y#khOB^tHC*OL z%#jnqTDoHuZ+v<-{ZZuRi0L^Zt7g^`n<$B^{TU*E2rq=bjDegZ4q^UyWJ3xfI@q+b z(-w6R`|CF0PM-YsCH6M>No#YmiczyQ`AqRo1g>wze$n67r-<9U zoA4Gbjvx&o^K-~tlL9aeZvx`7oguLiBsY0;Py~G7MF?W#BmCIkl1`lY{1u8kiXw=z z{R%~1M3Ks&{I*)WO_+nWEhOa6;d(^G)NaJ4)DW%%qyrva913bLU2ECU_>k1bf47%5 zr?9xJre#{HR(V+JmSWvkqu}9?dq|5*%k$`egks|M;A-3(ye6hi3sXSp3UfnF^Ny2m z^wQX}Jm39KX^68{cG>2zb~v{d>yflyH)^74QkR@==KcHpjMeplPjEN%$6sB`dwxB& z)j@hwv$>|KTz74R%Nq6y0>t3loE!Fb=kOwQ&uCO=EuuBXjnVXU1m-Yn&FL^za5`z@ zGWA&AU8xA+l|FXFu6>UzQmr_x$3M#+S9gL&6dDyJ`h|*x3v6PTBE(=PM5JewC8_6 z|9_CcI5hGjd=NG0NFH;F-3JRnpR3guemzFLo0PB9nF)!V*4%{Dn?@%jX8s_-&Wz7i zfPTJBfBST~8FF&)cxERg-f7KFIP(sXnUH+zh|Gjbwv5b7NZlNlnJ~Tcl(`8jts6%t zOb5l(%;yp=$$UN`IrD{tGiSe?kU0C51Uon0`sQ&SXU1C_kMnpQeiqnt;E+B;%hVU)fqQ8!Dls%20K3hJI{fg=M&BZONn5~o*nPGK-1fwr06Zu zX%t&LI>DYF-;iKa*74-K5UZk$kngR;&t~GMbHtoeuOGk4Bnek-|&IK-&KdQ@j$G|0&6T6q>LhMrRL}%j!#qZa{>7boksGXZh?wuncyR5NsaaOe=llj8fQ@mM< zrRQY=Wtp$kGZejB!|4sjS6KvKbBHgJ8}YSU(-|F32W^?B<;ZyZPZIC&N#Y$nNj%S) zs-5_q1Nq^8o~!x00=d+VM2$yj`fxvYin$3HkgC1>2P8uL_?5!X(D=i(o9X&A-o=ut zrVIHLjV1=N{pqX$+A%8@2y#?x>mXimJ}8i(B9!JkpbSo5DBS-2tX%*{00G%~bD=wE?Ia!rkJY2adU5=ClpGN$n zcI?*WzVh+f;fZcXPP~;L)wmq3&PHx4FHn3wE4gsw7JJ;zP3ZDs+$LIG4rSST-3qL< zbUTtSRCK*^jpWe1oBHD}>W@1|&Q3_ZgZg6&^~YvAGa;*U6xV>?>Ts%<{p#!=QZ?Rr z@z!r*WTSR7&Mr~)=7h^Ha^B976x0B$&OcI zk`p{E5s%Z|n%-&`y)e6yYebqKpTk1p@~KxSewMq+8#}ljrIqnRSppPdF}|ohUAp{j z;pK;u?@GxD`#p2GN!kyR@@6?DPf>hr4W~PdoQf6Mm~!I&+pg)gyXb|? ziG|KM@-9+yx>-+Lf%3#(;&esta5z2mlXbi7pxN=(BH2>XAHqMX@mFdGn%i@td1paF zmj(Uo!dv$ds-zV3bThxr)%E!1D860^=L`12_yyKi&^mGq=EajiBxr7Yt^!bo<{9EQ zd9I=}yx(KZW*bUXksYLRExO!aC=(xU=kdph^+?o^z?zvpG`=O>d5WK`@NohAdSdzQ zr}6Exeji?glHMptkLmB8ujucSwK{yCi2mFJWk0N2qv?wUYW^qwyA~+=$MIj4`Bt`; zyf?Lo*FBu3<&c`C=v*7lr|w_5Zew>nj}+ILr&teLbouwf%O7VwvXP|cvF>(SCyCCF zcdd}HJdhM={LB8zR(!hGi)8LN-avR8HD1KJ4()N~qqRm93&Z?t?zh9b{O?Do2C=@K zsNWVO9Ho}Ei2sgZ_fO4^=kc_Ep=!sA;qn@0{*ClZQ~{Pp-=gEogX`O_@jhvN8+|8N zUzf)Fr1h;VIDUOqtQQ)Oeu9xc++VT%`UMFa1$t?tB~rqyA8FwEbK?smb@F_vfy2!! zWVie9kbf9~>=k`v{jl3*I)1Q9>*v*YM)(;;s$CI&U4(vGHyH&52Q*Hp+_6`ex~YI+ECt_K3>+idDU{KDIxjRzhMyn84Vd@y?H@`H<*$Em8DwY*2oV-w$&W zS`e48tlJ_*?#+y+aY*#~{EA+&i{6RGp;=c=jK%NV_@JimS*qx-Q(`iDb7K12X`H8u zD@HiHvphy(#s5@{Yy^O5+)}$XmZ^G&i>EPO*9q`g?tL0B!zHKK`pEI&vu17(d1;w``Qtz=5YX-Phb6^dT(Nzf}$ zt&kKl{ziD{xVz5D=TW0_CaQzAD8>#Jmo>lrQblqWD5> zml(h6B=MQw{ThE#xZXw0V``K??68RN(dw{NW<2Zr(Q3sn&E@oAJ32@68AKkn%TuH9 za7VQKoXE~7e?xe~tby$AxiK7$8x?0NCJL2+yCvftQZMUNy{lBUioXcEtxA(REQnWu z3WBv-dDfvE(b=f!><*V3{H5djvtoQ0|2lq$7||SuVH4D&P-^6oMY6zh&S+5WaId2{ zp3itbjdw|Sd!av-x<43i;|cKQ>UM9}cx2z{Bl|5ve$A3`l38}V3h0H)kLycZrT8bk zr4Q>#iPY-_W!e^P7jHk_I)2HJ-I&940ASHk_T~AAss>dDwG4@dIevv_p zbog2Ro@P~kIK5zdlB)5>hRYwk&zJo)Kc4+|)(@Y?pLsIv|5il%7t%_BOvAA2|8wD= zv?#u}hw~FdVG6heVrw2whQLOTQpThnwGiJ zUn4%Z2UI6!=0Vaa#$Te} z*RI+>+SQMD#Ig?|?kH&=^5d-*Or)*yR|02aY2c1*14tSSm~E zft24GMemO;K2IzMz0No%h8|$t(Rd*GKK&~M?sZTse&t~T9cde`--&MBWb~h=>)!7) zc9AzLbK)1H;bb7?P8gT>tyAsxx#Vcd)3zX$njgPV0Sb}qCDq@j%P$Qt54~F_^(`~r zul1bqJvXcRBK&mV*Gl|(2A}kr==(H&sf#|ZQ~k2sTvLwpgUW5!1vMcE%|H`jzI z#N7DBj;>Hq<~w=4;@j<)E|&Grk6-L+=Sq#gAiVyt@yPgO?UHxmJn8S``-^t7r7(s-wOR&G%3SnsN5xOJDZ(3wg^VY}{1OeVv~>9D5nZa2s6 z-R(}@sQCH1Yup{5pIf5&aplaR$rT@#@8MfiJ-wF7XFGTN`9wSyF{(+t)6v&XUD|zB z^DD`B<7QRQ7*&n&^Qb7T5r!Mj#OL&jFyHI)p9?R4LOPp&Dp&5;5q-~{ivB_u{o{@= z@%1pGQgab;s75!)b)i~zl81Z>;uJkXcpEJIo=>NAIWzIMZi~HOoIfNZLbAEgi zX(fR)UrIgvqADMu=dcH1<+qsf@Tr%W!~%H=N>Q6H_X~*L$}cH;9pUnfnt#<8`J56R znF&OJRRe~zlNaFe%F7YI)_4D(9o}BduY6vP=550B+^6`M;=(JC^LB20p0>+OH&x?L za^bTd!+1W8m+ZnTbjZoZi}BF+h-J$)K)xOfxUWoq|!jW_&yncYEo z+*IvXqg=*Ul)T*Y*8<%xrti~uH@MnwWop5y1#>1ZIJn$)UCur4gz4D=qgojMET6>t z6<@=(oAHuQ5-(Nbx#I!luKrtjl6YMwiMLzh&2Y&r=&IM#quP5Syo?jz@i^G1@gn?u zjF$@8U321VT=nnQ_z~-sF#nbN)7Pu`yeqstk#?goyg$jF%kitrz3G~lPBicFKC?J2 zhCRfDk*4YIe^Bv7Z@SSZ$}h3*09)jk%!@BqfW+hSeGh%I@+}Xm@)7&!k#bRI^dR>$ zv*N4S9o+MuK z*H5m!zLUh;sPWwM46lz^5Bg3(Z!WZ!#?yX{m+Tr(cf|0g#bV>$kq>YQ%&a zq1s7rA<~D}NyGVzDhg(OS≱D`nl98gtUox23xjgKn2$KQ8RtIY$7m>iwN8-2)6 zp?3E5D>{iM$)EBtXsl~5oTy^^saVt7KA`BWbkRG(x^RqC|4O)gPaI#Uh|-HJiU*pN zE!mOjM3U=C-lgif&t;E}KdvHAk4d5kZ&3&`vZhSAPcHTE8C4IxL{A?cXJP(iA(f_S zmY(zYOnz3Ci|}utCnj!T<)K#PA5ggq@Q>>2)8%AiktgeeUlef7%ZD{yDiy|u@%UWL zT;vhG#P2IUY*&BZ5o^4w?O7i1as_VWy<5?tHRdC31?)+E3ue)ZueeQ z54~qkAC}h%^waEMy3D?@Ux_a%x)I|m%Kj+(b(<75DVf*swOyCL+r?K*efSJ_mYl}3 zw~se z`LX?Y9&etXEBfwuvNc-`IOfBr@lrl!d}TqxVTwPk6j?F&h@UOvfHY1w{z~z&$ki_= zZl~HGvdp`b&arwgdWgsG{$DHl|MfBDh?9Y&_Zz+9QQd3mRVg*GoM!Z%>**U*^_=yw z<;3;$#t_tLtQN-K+x>>Br%$Pc8edWRrsm(}+#{_=V^@hw&ER#!Q=U4$7e7mYvkG3}Zo|6fHJwy~!;@;CnL9~57o3D+aYC2YQ` zmctEPp2=^-5Ii^D+H4-=nE5>QPl}#9?s`Xz`6Hmlv3b45Qg1Lj_QHBn8-Hm}q~v&f zb^Te@6S2;R-!R<#qIx#$P!ExW*d3=qX2^Xb8ehpr75$%t%f&hLkM~DlCMP-bzGq0` zpB9b}Id%%1Xr>Wy)N4_|6QwSt&Sv>19#iGM9Ih8Gy=0pZc3>?D{^5LMu9F-;XS=5N znaPSE&m$+Y3uxNu;Ib=Gd^*Osy~W~jz0K=)r{pgZ{j3}5&K7-tg_%6asquoEeb z53bB8rW+xKtB=aHpd4Q@e2pw6%e7EB;)kBE)O1VqbMUj7?u(HAe)DMDQSk$?^IQU6 z&6gNdAC=p!%Srx_Hyj_0c=iGC4{Q7bl8U^)W4L=VT2>EpO$N4CT84RK-VeS)*SCAN z(#sEZeNx{d<`eZ`IKD~0x6eg8^(C`YH66&k5chH9#4l9$aR5c)9o2aC8ZSbQ)nRg+ z6CW;BGv5*)RNqRzMpV-ojz7xx%|l;k{1IXJl+TyAhUdr9%L`EMi@@*FbjmfIaQ-Pa zPIim%JoA)X%k=zmqI+1nyw*QYaFvRzu~^ezIbYHLtIOXw{`$il^f1eh6YZC!p}wy9 zkhi|9^NYGY=wF)>g+gq|Bkcelpp zbF$#W55&3gC6RPJMT%~>Ls#L+(UlpWr}(%rfyGko0YhBpPAoZN&LFG1M1M36^*#3p6<~vtJXJodm5W7SC!SYR#)SBHGT!6 zzOA}U{t`r}g}#H;o~ri3>heHylc#QOV`G-Q_#3#m&^OdtA6%ozRW>)Tst1Yk)q&bF z`r#4}aOcs@sy^b;)7a9AD}YpT^!GlRj_`U*S@c&eJqDjS;v;H~V1UsHUbs$jR+*DRyPWlhb&`kMMmNrOqKzEBkg{tl_QAjb*{s@}@vdb*rHm(dIJTfGe9< zA80Ov5LZ z)kfUS8eTwF6(Ops>Q<<90J>3D-q@&ql%%E{)vMm}RLnI(C|=W2&3vjVwKP=?n(fN+ z%DM>VYeG$x)R`z6FzwXHs#8??*6Q*q4=(9!D+|=Gtq$i}$s66@sB+seCZL$O^%i6T z9_U?bIZ2q5m~_bL)G|`P^2Rb;_SvS&RyJ0bw`#S+U=5U+n?bp0iZvR2L9n!%v#Dpw z(GUz>rK8~;Bt=RXK@16Cg;1wvs1D77T7-2DjTQXl4kQj_$-JkfyfwgdweBl+8=GrA zx;{A)F$6tz%>me!rmFh#CXW==aH<%VPh(S6!ou;i7dHpX8)J=qJscH&MRUM|fB5AM z*^UTRR2b4elFqQGv;^6%MD$O^obUm@xV$k$CMHmcQBYOgL5&6kZItw&d~I`JbSml_ zVRoecp*PW`o{CTn4YpylQ!&71%d}YcNZ43*k7N>)mKw~ev|X&@EzOM><#gdO%ti}| zzX?{D%vZouZ$^I@Z8opk@NiLyLEVa9VrXfs4#HZ?+p%$Le|azz@WA4i1+}s&J1qyT zQby945Nv!|Re7*nD|B;H6{(^$<#LG08d~ZxSQP}uJ(^LO!B!GBw6ad&L|Eg9F4od8 zWnlTsYc*x)NtF~yReL#1m?W+y4H8z3nH*&0{Bst15QQ-xUf3C&Mx>g9P*ZDljkb;Q zI%(<$RVA@e(b`;IRax#>m@sSyONz2ya~ClqC{jw`=z6IbWJ|&gw&o;KyP%Mjp+?N% zMmc14iV|Dq2#cV}1VR<7;Ut)L8h}MEy#TFZumP+ssGc=j))c8r6@}F|hM*0s#&SM0 zq#0<1*0rm_=crSAwj6>q!YVLDdD^vY(EQ-nM4DU6n#xy`7ZWxgMVdQ}EJtZr+w{1p zSgqNUV_6SkU8J(Ssj@n3BGuWE(sqw!jTAO*>LI{mL?gKMSE^)$jC4J+I7W39+DhhG z4R9`AS%DdQOADVlT0xY3aHNZs^g)z{Yf@M~m|z1iGW-P%~*(gFp6GXeipcT0V9 zn3dCcHBC;#b#t^CcM3_aD>0E`fWRU|dyep(;rUjFS^fHmDT01{tg5*k6E%ECawACU zW{OaT5Dpl+M*W zztbSyl8S7ejTTDxHDdPV;Z#O$i>D&95fc~O`|2X?hS9IK!SM}}<5b^V8EnKbt|DiD zcBsCwN)vNG`B9+!-M^d2pcWk1*v7kVOx1)gv#&;b6a57NYmQF!fmQ)R--Slc23b;uHIO9 zRzx)-X%s`W+)_oE36LjGcBfj7-vA^?{#BH7$Dexy#lkafO<5_(XA;(xFO_DuuB5Jtra~Qrc@E@=?Et{zr4fO z+z$V>AXHu@6`O}({_LeN5Bc>?PKSnRq;y{#i&PY7no`Z=+MY>P3(bIAel()fLlvgxjz*ny>Z>ei;tqx!1dg_g> z^aNKUvOxpK;a0O+E~TUlCM@7QvjC5^GNAG5@E5j*l9DImK&xFTp+Gr012uAgM7kx$ zEn>}cO(RkZ9A15`&B5l%=0-F5z^z3H2jZgP<kam<>l{7d3W(J7LO|LhQw<~|?R}Zj{O~1dlgra} z%HRotHn7ght3J;g`D82m$bK}S2||U(fUuvS(vO=UNht= z+$ARi>hF5FIMgWQpc^z^a_YgVyF>R;SXaq8QRz)<^=jB2o@k25=kdt^4a@k%5g}fE zNj;S47=B@n6gP_5giobiZ152or*p^c%JAb!D)I<7Eq3T|UPonh3(X6Kpw(LC%owp^ zis3Or9jYwOD{}Z*P#yHm%U+F1eKwpjPoSu}l7_#htp+0&Kc50FRDctRct+LEX+{(j z`Sr~eWfbd)fil0jHB--mlb zxW1LbIm~}OlL~KepsAh3ldl)ZH73UiF#XR4wEwsEk0pWe8k^6lcs)J_GxZ~{r)ahY zY1fH9$WnmwmtV-+rn9`BLI!_qvX(Q*$4W+cj(H1vIWdQ`92Kg=qlx2{9$&fy(ET=xJbJgn?3Pb;mZdL&|i@7FR1u@!Cz-?d_6(XmYORuMZ zLFPjtM(}||G%J2)g-_FYJu4Ut=guF4J3n)Gj}hDo2AM_T!{5s(=F;o&Gx&X{EQ2gl zRhCoSGBD_F7VnThq#szGRNj0wsL?pnqHw;Wd3n+B;EJh$8(WRd~V+2yjV7ySs zUQY>wr|B%x$--VvjWdXa3|?rmN*KJF*JSZ2Ji}fzUj@w9C{wD4LFPn_cTO=g zFboVbGqAf1GBdzpaIaH?VMqhfeEFHLF{adF2ALBzhB@Vsj~Yc^*4^-`>9T3P4FB15 z(Q*clnJgcJADFD=41Q>crS>wMV3=LbAhU;=i^0n@mgSk&%kcH4q%T8*MNSrji%r&Y z2J20hkHHNlYdM46Cd-ML?5|H+gpWbn^AODQ?0 zEPbF5Q!0a#be84m_8Y<)h^Aiv}n{-pMSE zqRu6`H;H$KL%JX)Z4H?(oLZ6}et-eQV5NR!dDf0$xKZZ;jX@?(X!@!7>eA4FDOSkf zw{%wQp5TJ_n}P)lh8HY|5(5|HYS3f`!wdSO3hvf5{le5($RJNwFuV+&uV**KJ*Q@y zDYl3~{%HePXa=(*%IfOO*Q**j&(JDn@^hRl2AL*Q+)&WKTl)Jw{VhDLiM^cQ8^XaB zgCjI`%hTdv*w%S*oi=es;mg+1eVoq&v5E;DHWEC*DHKMFrSnulkmzaVj zO#T)pi$SItLv`6zPuHb{ClKvuvN!V$L%NVbK8Fs!lEJ?lQtMXsa^jylQ;C986U?+4 z1;7lDrE4>CaZ|Sub8Z8t<{g%iGUt3_%~B3YJ{xRe#`BSOLK-k zMtZIO1|bG#=&Vs5ab|MGDtB8b9Zj%+X@AkwQOqFMrMi?;Tn(%#gMEgXVg{{KRQ;-~ zo0n)l{Ly?YXFeX$tPw4LFQ=FvgfJLnelQO*xY@9_oWawy=cCAR>METJattnrK;+ar z4kCl^M<8;FMGzy#65ak%ZvTU(A4(YH78Apzru`22sG-%aX|MoCd&H%!>Xfr7zDx@y z{2AwMG(sz7@q9`*5$O3XniS_<>^v*tXPn2f46lYIx!oye*yFsX^)s)hltGrO@N~b~ z&Iy(R=$CTcZf#@HvN%rl1Uz=~1sMx3xYYjWEF%%tBG=<$EsQ$-?Rv}t;)c2&b6a=l z_P8Fqo8fxwZV9XKHq${q2APjA{he)O=yPjo4BzF4n&z7hZ3f@gStC3xn>uMUsKVK-$@bUDAf9D+FRVqA(zpXwRy8L^I3*iOFa>?l9gjh={~ zf>5~Kp2;W~UE%}HGm9{`(PpgCMy;Ym*Q_7$D7HLTN3q8^cWPXW+?L@+F5?`Jo*M`B zb__=^QO`=3>2J)Q3{DH1unMD?jxJabt6=mJExMpTR>9~cT6DqESOrU?Sk2H42{>(J z@P3n3{Hg|jY_bX&eBWdhGx!ga1i2#)djtryx(NsY$2NoaxaYZ$n4>Wa%psyyJU?1yHD5U zlrp_8Z^A|`Fu@Em3o$I|!+;0#vhLjgUq5r zgUKpjdDy1L z0%qb0C+j4tdr;G4X?i`&m=MbiSqmbv zD1{8dgOne#{u*4Qzm*I))f$HA5(1MyYRDHb$faV-AW_pyF|>WxX^^Xpu|AooQ7+cs zqdhHRoA;`-XbI;o9{$Y5wZ}~dy2!=n8iooOWQGtZ){AO~-Uqtjrqc&Egyron5-MPCESP@rok;53L3DOCK^i1nI#q*+<68+rG-Ex8Rm+C#&vUJ2+iHM zvt6wr9B$6dhKZB&3|?hQtzeLAR;G?q_d19Sa?J{n zQw|?dHt{-L|1?8uIg{^pvZ4t^MIr9dgdQ*r@-cXcAymY)?{u=5_LEK)gWok-J_enp zM0IV0uK5~M>ISavb50gl=McKV-8TVA;vt!dyW`3f%PS><(=4CkF&@W=TYn?0xnfF-p`rkD5GN)J!N^XfB(WU;Pzlk!#qYapWjNl^tN zgXJcxkilC_R+JC)g08&I)VQ3%2Ay?^r`;E4*PY$V8I8_^Ect*lnw$q2@&RWw>j$={ zea8m*gmbtdc(PqR;T&!ce8A{-MA_WebvxeC-{ed^tZRKtf0H8oLBk`pNMfm7-04cF znHm?uWpszBl4z!)gd0t0c{HJuY2787qwDoI+yn-TO;$03%_gge!5`_Y5uU*I4ZWQD zxq}$ZS5b5Wi`*)Fl_s#r5GrPHiOKRY$koDGh_0?Uy1FPs&xE*DXw804FQ**xMQ-v6 z(OrYeb+_rLW_*I~ec=g3A4u!c>a*R9tU?BVW3q}F{GHBHW0zB*aXfa58En^C3XxMk za}eFkG9TYIl@>5~*klzk$TbuBf?iGq4f!Glxn_mPDTj|DHy>ZtmHkM63(u%`dpYrQ z!-;RYt}D~j>0>ZkXVHk{8v7hH1|K$PZR;5RmV>rmgUl-!`6z0=cvvHe@!SK244!YY ziW$7fWEC=avCdNc6rGUW)OjZelOi*bGryTMnZu04xMwkAk?q>MQhJF!K+7X7v@NR?V zV~{J1WzP3&^bbw3LI$T#Ubn^J`g4w|eY2H!GSg$%x}vy>P(^*4i9#Na<85KZa~ z7Hr`N4NfvyQPzXG-Db!aFnGjd6*I^zV!$xS{3)q&>O-e2gN8q80XgNcRy>>_Z#A_1 z48Cr%N*H8*$jjDGnHgfu-^;1LJ7pPUW)vc)9M+;VBUuY{o)K&zgRLg3n8A?ADrB%t zXQ@8s)MpK1F@twTAi71we9SQg3mCl7WEC;Um816<3@0CL?z%LM?-*Kz4F1Ao6*2g0 zlU2yzVV$L#$*H#uViALXh(L5V^QeA0=}e>A43?U#A_iBQtU?CMb(Z3TQ>zSO5ra2I zAabh1K^%^?iwsHugG)_TF@wwxdVoP@hFB};Td?Ih{1nGAad#y z{aSX6a3r(#l%Z9?;Oi!Q44gM5o{rY)h4Tm!FrQb$Y6ucQXR^v zwFa?>!J8uxIknY6bQ=$5ZMs1zV6ety6*I{EphFpCW>i0M>L#ZwgUpOVAGFgQTzOA#A)HwAwgIL7iKOzu0b;?<6>Z4p1W^IR|RlwluCaai1 z=7)xXe#*=!VQ}h0r!0faj6&p;!&;Qo5;fP;4EKc$R-3FM2J1~$A%hJ%OG%AWYYk!% zgEvPYa%!uC7^Q3a(R71Sz+jEZDrS)RAzjl?nHePvPTk~`WssRsh@5g*i;`NGrtzeq zRmk9ob65>lFnG7lQX=Bi%ySK*yXAj9TjgA3Xcbf4__^N~Faea2^cD|#(V~cL3Ca^(&#}wUe{qRNojpi|U>12=mC}XJL=)Y&^ zEEHt$8z$=p1|QW~v1ujirz!fIMhU}RIuH8=8ZuwG8sgzY#Tafk#iA_8)%uY`nF|@p zOEpxfzvHl_81zi;H3%BmuD@T@-y}T^CYrZtOBkG>vy>1xb+LoU;H43WnxOf5Swjc( zH#M8#*L5DuD}#U5S@K8+Cq8uWG-SR~b>;I7Uj+<~(Ql7Z0}6UMm8f$upBo|?h^FO_ zMav(9mfub5>L|VnnO2Ws)yLptItxR}+slb(96Y{ih_Cm7F=OyYPSJI}oZ!X+k3py1 zQDdEXWp1z-Vep%VdWW}{69)`qeg=Q$;H~TB#G4KtgYP(aExnv@Sc?+lF^$hR4UL6> zws~>nb2{GkkidCSYR=91nyJ2k!6!}iH*V1gLdO4A#4~_~?dzawEI45(DmlNZi%-vp2OmH%HcsX&Vleyi?iL;!{N4%Uk+sW+n za^hSk^NU_i@GU9Cr2oVrAx zMuTBsaKFw{qnT4zJBPg(Wabp&iMjJLcfU5=l`zQs5G{WU?n+{D=kJZ?t|S(B(Z}7R zWmn4Fv5G<8z8Fj2z8Fj29*L!Ihhyp6p;-F1KbF4jiKTD5W9i$DSo*d-mcBg_OW*op z>Dwd2>Kh9Pm;59%%tH`|Y?2v1TT`HeHw-81yb(AW;Em%Hk5vqa?G`6^tRnMG4<~r6 zBJ;3^6FgRtdC0>F9;?XQ@8JZGRb=k*aDvAwGIx78!DH3(v`=T4hbrR#!>4m@GK0X!;N2#xm_e2=WL?KF%NKI3W0)n0DnIb@V0y=#8}~7oqzCu^ zCGK6|wW!KH{&!zMR8kVnyON;d9To4Xlv!$;Gw(%TbZ;Qd75;pY4xOO&koekw6rODm; zRi1psn3x@^QZ|77mP$0l=^|0KIYmEX52d*YHBaY>E1q()p)bo;@zJNd5o1E`)^^ zi$GZFx~>dsxwd0Ui@P~p;W!jzI1&X}k>Z@LiWK9ktJk&D1kP`#z#K#p;uSl0au^k4 zcpw#Id?>Y;WE@I`UU)DSWOxV^WOxve7)xfwCpzEJx*pZ-u>400-r8#Xm<;A|-6MCc zKnnND+v*X?BIx&oIsH)GaTbt?4aBX~GP^VMD0-o*Lv*FOOMgbet(@Oc$$CEEj4(qF zU#H8#OurrbE7hU#j%6)lwmG)?M8QhWC^_AATj{Ba36w9VTIlv#T1Rd24hm25)D(rZ zL$tzP2*s(9MhF#lK_Z4N5UsF&p~B*Y3M&^XEL*5>Bq?wktELyYpHU525?^6mHbNNwWYQE2Im3o0JIdYiAZRm~L&>OZP9Qxuw2$L_!b+DY% zRbd$~Y-bI1zCNehd|?AG*7LuFoYhIkj@55p7G#eKAJeUzobOP`(NpN%t&Q}(ZH2up z^bXT?gafA_!_F0C*nvlMp8Q0&Lu;4TX4JOHI<&6wx`hu1Ew4NDdAs`Z6D~SWheMXT zVK!qf4<(tWbXF)}smcAF2rOQr$9(>%zwiM1W4INLb)E+!cDx_4{?2+ZV$#h1&WbVX z@8o!3>?9W;!&n$2{J@Tz9w1{Z(*nq$RG4xwO|*ll2Y9McE#RF-^#B<~2>|p*VGlvwc$706C%13)&znDe!9Z zJqbu(B&Ss!2)-Ya=*Jm$OxPKVm8dYSnAfX1Dkkx&j*98Is)N3@Y~oE~E`Hrp@x+@H z_Es8DG4WP)R7|{8`l!^81gH8>`7>eM;0E11z`EI>OUxP>yg1irMY}}D^LpLNZ3dHS zp&jAT2aU5Ms|2fWm{oKIceEz^Axk;|vOHFNUNBR&nHU4F+D7UE=h#sy9XfzLOC`=x zPB)wbjtvLSv3__QBB$Yc%9M*7;8dd;XDYnKQ!LV?ErwyvGHxV1#CkayILxTV0SYNg z48xi#F23T_dr5sO%QFG`)SGeYy`(-`8!VG2PQ5qIvl-_ZT^*6<=WMd1KxTq0@Fca7 zWza)X%mL9NDOL-i?ofk&ctcw3``Huc8J$wZ*I=`QJY{j3(?zC?d_jh}79`n{M?r>} z6l6GA3o^`x-vQa(W=;~?Rorc@!<>+4OFO85))r*g$%3p{h?jPRnG~88>*UgCon(HH zXnqL<_OrGXwmnxPXFo$)^qkCdH8A5)aaohAg(ZkuI0QWGyGgHi<>nf=m3`H_0o+EZ zeCerYNV|DO;2r}Mkq+^Sz(WTphS}Y$Sv_dkB?R5cd?mQYSH+z9raJh(If_06eJD~% zA5-c{vx+_-MCDhe5;=ZWcX^d`xl%8gRpc0zznV(q_%+?-Rnq@f>MgU19Ha7fYhdJf zxbC9Y6{o%lsxrlU0bXrX6L_ssZr+5WjIYzoFa`3%2XX=dmVH&cr>{Piny)(W{r27M z7VvnbTwX|5dBrf*IqLQabDsh~U{<|A9OmxR49UBX&MaS2w_WNhKZwDbng0Yh!KfzA z`%0GJD@-i``W&JQs2^(%tE|LiD|N81cLdzus0Q#*qY|J`v_YaXy;js@-Sw!c)PbMX zZ&S;B0Df61H-<>dyy9T)e`M}c;8e3}0&(QVa4=sFny)tS3+Af_NOHNac7{ZRiqrM& z>h>7*mCpz8spdZc^5Yk>&g1;YB}?$ny(Q4+5S<}Ls`mcgir!rADc~%ln!sy~N`OAm zCW-#QYlTf-uDdoH;r7Tm3dr~NWj+9}Q7tzgkiKTN(R~K)N0>?qywa#iKpeXHfaKjr z9{}P0ZRV>Dyi_TAMKpjG^s3G)u&E+)&zPc}(%W4Q8_nJ#<2(vu7q=rC6dGs2> zY}L#^Uj|?8xp80$&p%%V(}bd&a1ckUlL_W*Tn4^SIk_jeMIpW_ZWFLd%qlrkp?8$v z=vJ>4rnFFZy=*FV;D&E!sx^UcQ_9UNq%BOb4m`-HCh(8}wn*>sifd0TB{i(v1RTup zC9A0o+`z&$fK-wDYG+6XdPN{9J4GZ?k)tonV}-`=Hebn>3it68jwX02bd>0>Gfbrp zoMBW0c!5!M;Dt)LaYMSwD~1v0=&pyn3h!8%%uz0Tq^5l_xChv& zuS+{cq(3TKG5X|jtmTmcch@}f6IUm~!A4%NqK5ECO|Q^Ic*Td84B2!HY9><)y#d9uF);dM{0t|8D(Nq$ugfsPdwg=05ad-a5F^Qi&u zvcXG$v`&02=s=)#U9}4q^&vcF%@xggn(P;S(hEAsk8k+rp~1|7A`U~puMT}dBAlUQ zZVmo=SrOrzHgOVQsWS_rXDZKVt}p1e;*>-4K5Wg~FZv)Y)LADt@#k@&o6g$dgNEYZ zD;w$PyEy&iyzxMXTL(R+EdK* zJ#DTwnA4x})J+PR*%C2KUMO<^jW-OtPU;-Ul}EMAB93Y5D)bQOwS3S+k(416knR_z z)I#WFoS@f|g?WetR zKmkh$&aYZM=Xa3cSR391SnBosj*6V;cU0s&zoR1O`O&I)fllqu>Q-_FmU3QHmGhz~ zY{g?!W);rzBM$t!#q0sTp_KgeVPA&8fXV^^UOYe%>EFE~@SXvR;p8Tj?aVL*9%EDkNIrRXX@u`?>idZe$~F( ztm?pPl*;pr|J(?_bMQBB2z*Arw=L%j;B!hjUr2xRiom}QP(-TfSGFrIQOSc}1&|{i zh?ScF;bg*ag%!{S{><`f07=;m8q%v?5lG5T5s6ePCJ%Z1*7BGL{JFVr0*RcvpO_)N z<`scNc8W+ok7y>Gp+0WVZD(zt4EzPN~EK3vc2dXEgbn`_|#fioDTEkTRgSy?c zHuE+2#nuDI%zSmQuedJO;eK7WUGlDcR5MBstCD=VZB;Ep!nES001Q#7y3s<1!&aIC z#H`|YquS%O+RD5`rHTw=mFTn7SS7l!WRh?>B{cw<;Q0X%FJF4eQX8Wl^56M=uVO5# znl?psuF$On1pd~jCh!HNTnM?e@{M0T|ud(?UA)Rhc>l)cM2k9Q~ls4t$((duLx( zjQgsC<68C0cgbW;1rkyoVT@N#2kTZS0un^1)3kxpbt|tV-<%;_X5EcGto^-q_wP1% zO}ye#K34dOI-nY%tV;?OYI^rrn#o>jHQvG}p;a7y65*Gcqe(bA-W)}B4Aowqty{^E zp`w98U9AqNr=kw5R+^*qFABY*G^~U0_o%A;5u&j+SE#5U!!aqyFt36PV{D?neTkDu z)@L>;bR~0RFh?X?p4a4>b787E7rL*S*CcwhCY+xvey^CeR{PpJI;E#-cbabHPB1Jd zR*9w=eIj~S?cA~1-_<3}E6C9K_Bsnul7%r;xlt$8eBE}|E}bx#j-PnZ6go*GF#;8H z6P0sSb(nn9X6WcqLwVJ}M@187Rl_u0z0A|COuAuF{}*aeFX~q62l~Gj-2i@2UzG2z zoiC>?q`IhV;6zm(G(Xjw)?nFN@cK zn;6vqZmN{?=;w+=h=ZeIg9O}|~^F3*rg+uOAb;66sxf%_`uY>{}o zx}uS!cC4kA0%zLyi(0@z> zTh0ma7JJcu67VZZb=5BG%MiY2dJ}<5%6bTon_dF^g;Mzv&sY2o_TP~Lo@`VC>!>6=4H(766K>q6T9{DuB zp?iZBUE2v5-F-v%uu)@%joNAWPmeog#CF3*?YRF=${)YeHaldP{nEal)7n^P(>rZe zwU|QPHec+3+|g5v2&KqbJf1JnX?Zh^JWsdz*nyukZto1tF(IGVuBvfRkaIyIyh{tn zJyOAgC5~#CWrcBg928_Y4h-j;wzx%ee2k|4H7j9U2BrkLBMu7?YF$zlwJ_0&+w0{T z`%k*{<;i<4<%GtWKB7t``vt&1g2ba|F-eL180WwmhRjNEdVG{K3 zn_7=tQULF_5@)RLKw!$q#p#G>JqVj4InbK*HGApT7Lnazo$#;P#IFMv+P4fEK>m8B zTs6xR3#3J==+34{HGA(qx(p)d-z;bf{I&({#nGQV1>}!cy0aV-5v%@A>aR5vIm^)u zB+k(MvC-%xL&jajGfuqSWvTVVR?#!fmTI4`TRAB#3nxVl*NlSP#sK~Is-li!MH`3I zF3E4U5Ql0+xuBMdaikrMoi1#c$?Mv&clvDOo38Kc&X;v7AJPC{Q)G<9@b?U$)jA{UnGO7+dS}8XZ!-^8!d!aW3K4w%C_@q+u zdy!K!gr}5r0g!gFFGw_jUp}uPaho4MuPH|zRo5U3ROcZ}c}9O{_NGchEV(*xQ>8j<=Zy-J2%X7l zh^MX1Q*_TodPkW`9q9igYXkTh)sn+N+Q1(=z0YhLK>pyVQ+!Yr9yi50@JB{PhvfOX z>pD}3vhUSh{6$(>X-MjRvx+V;Q2Bg<_HmU*aQA#?w;<60sL&i=Q_7s))lbDhR@T1;in8!5T^>I_F13za}1NgX7 zZbY9@=~+{(1Ak>y)Kz@_U~rY?x@)zm)PZCCtMNk}-@Cv15*^+Tay3*MEff~}6ygBfz zO65NX8veIX_bv8jz(3>%qj(b#i%Bbu2Xs`fzKP&1d@!iMe?ad&j|T;#}Vc$ zxk2Ggp288|$f$U1HcHDs!rD*=9<(W)=>Z<1lsrI{YnDS*I@>D(&l#Y2u1a6^iogW} z6u+j@y@kR0x85PBK^Bp1b$5^r-(!? z^2i?eBeP9`zN}_g))`vP^;T9As{BfKtvtF&?c0hbncMQ#UwB~jr|F`magM?=G9Hp7~2r#tJ z?}6dne03F0oAruhB}O=TyeI14NDmG5gviwL24RDiXf@C4R+bEWuF#4qR*`WU?kGDV z>p)&<&X0uneGv@bZH6iEbfX%;Gn8^i71F1?BJlbFib$kVvDA|XS|9Mv{wWY*(oCVJepzqk5(UT^OfNK0#Aij{4rVn+^SrX0PFr+8^D%Pb>N9cHGroY zRR@00sKyftN7`%sjcpYk=&AQ8Jl3c>aEeil!K!)63QmDIbQ1t6HD4(Z_fB!J2#;HY zHt_paV-rZNZV-_+wV+KP9dL?B2YE#xi91Cka<2G5_m`UJim;!MiYb&tqE6#qY`uMH+sso2?;YL^{ z*D!_KdTNxyU5%;(cQ-0pcL>K$ON5Qq8jq#2U;m4@@}zcl5yEcJvuH@6I;YqxQ_ z>m*aD1A9Cb#+stLF7YZrzWE?+0*=?W-Q7$>I>g?AkJ^I!E6jZg|cJ#47g{|3#4NG@nJ5R|0(1s3x#m3zX-H7i4i-(NH|AE>@VU6u3$$d5$&$ zT(hpuSlSUi;=>tQ6<1Ib)WL-|5Ov^=`j)Z`B5)^raXEjKhP1P>=P$o3L)yjIOXMj4 z(r(6Hy85yVX%AyBllwa){ye3dGDsg&T}dk((+=IWnW-dOD%{#rK)x>`ADZC%0Ivn~ z;Ucl}1Xz?%av8eoppXKens8L8jc{0xJ1m3Iof+7$Dgkgheh>I6mA{7Ft(I)O)7 zgeH(T`sJhoq)4}HAkFl)KoWO~NLPAAU^(IV)bg|r&oUdP#>)zS@2PO2eNuPvO_=;T z2~5uU<9jga<$7T9s`{7=Uz=(<@)1@1q0b!Mxxi|!1G~0y8OtFFTwf_SmykB|ioneW zD2A1f(!Gb9VI6qX8VwWOJINaYCl4@0I>jr7N$}SwZ}2L>J-4OuCh!2IT;)jr=@mow z&#BunrqYP5qP6aBwL&!?Yp@R%nGt-H0y!3dmmAdt&Qi+Ng7j&x2>i?dMWlsZQIT!l zt>|J?Y2f}-o-%a>SRJc!{>7q?DxOy26xt@VlUp6k&QT>}ImFQ8*V%_zOsnmg|bvRBY7Vt8qT+&Ea zctzk<0~C>N^oqdG4Nye-idO{QHb4>SZm$TuXMiHoBVG~s*Z@VO7rY{HzHc~(yq!@9H5J}>&$IAtbthNzTz`;Y}m%|A}gR5$Ux=3+8Gkx7LnJOfYjy` zkw~TDeWy5&iR5vC<qlJst!EQs0Jzh z&QpYA{Ny?TxT6ha0`y5mhu@y+lW&O0nsJ&^=UBKV8C<1Q@fsor!fl>>Jwsqli{?Kw zgvY$*>I{Luq$-htR40F8t7l6shw{YX&CzYy-?g>7Sb*!7S>FLDZRM5D$`E!`QnCQz zEMHpj!4_ZW$e-2jKX*!T##(D~72g>R-BrxuSS4B~QCZK|0whm48&U$>aoXU9&6_&# zHvOK6yw3}~U8#K5*E1ykjzPtXzqt3`VM>8m<-X$OBQ|VT8ODzjV#A4{q5L_-Z}-sv zw&!UBuD3=c!2hsDOs3?M^vfx7uM0fQs02ufqD2_C^EAwV_;A3#88s3352YmYMSW*z zpmTjdyt4hEX54F;C;UC4FBsKWtne}27Dp?>FFd(AdqIVlbSn!E@O7{ER)(;FPYpOi zsiK5~R5;AYio^QLTJ$%p9}VCOM)guMTdcfFbfm;8(bFtc7!z3-fZp*$VzOO>6(iYE zs~%Kbu>F=+_<&U!<#=DDl0K{yfBH?%);MJQw5mL7juZa8rOz>8!oAG~Ji5C3fjan! zIf@$nWTcW3_77&25^DpC6(x#~&RSoz!s82_HLdWW zt_(5FW*e(SU($?KqBR2*zIR*^h#u}fcrSO>U3-~IG_?JCSl*^vId1^}Qz>@_pgy*- zVOnJvFZZ!wyUH+L?qkD=RfZFz^D|HGU+pSi?FwIQY{TsoCFGz0l1X0U z#0p>0VTyAc4C+f`*#<+ZkPknARe*D|E_H7R+vCagtQFhTdWE%iF^L8F?$#pWx2 z_a5mnWAhI~kd_#mPdTJ_+qFd#c(hS<;4w;7pUKFXUqg{ADc~iRa|?K-Qu4CvFfg~@ zx&JgndXFX20+thr=Q@de*rK+9-!rNQNDK0yZEMJTEocw095g;C=BejzTU~o+Zz!gc zs+UX7R2_OCGZOfK?vh&vlEjlxKnAB`D&M9K$Vp!JUe%Ee)6zD!66?Utm6D&hTCKKz zW`^D*Ag*}UP>};^GIX+10?Q4JM-fBXFHZr0Wy5$RFk~XjBRZh()jH1UL>n^I_X>D{ zQ4QeFm2$@i(u-aZ`1=8hNc`G{3@-4k0g8Ss93s1qT7(q%Bcqx?@^MEO(o0?uNIp&x ziBu|{c+OBCL=qJsVg6-bPg!0KAU{+j=ifM~=p1pKI{2J9O1`LYp{MRrxY$!+mup>) z*-5t&9=Kn(+a)9RZiOp7HJGD)%~1+G+^i-8ap*dSy1}Gx=grnyUal#Wxn5P|b&;#i}p76vB$-9ppAM@CTXEw4p z0moVPlW;@_MLAUmQ*>K(VmeOuouFHBLl>U$R2Y1f?%F_qD@6_#Ab$d0RtMmRRLgy> z7wIF$=GV$dryE;!t-QJJeV=Y6?)w$;yEAf-0{tJRkDl)G2W@vUM-AY) zsiZ(6=f2X4JW}$&y;BTb_bc&vi%_poD?xB=R3~4`8tOMU?R0CMP6pY^<=CiPE z)v)T#qfkeVt*~USv(C5pb>LM>RnLz(y7v)p2>ivrXqZ+R##hZZtJ?)WVpt8kN>@Rl z%5t@S!+Qa4YA3FIy+QI1PwT*`swlraIW0ptYk)P<`O3;P0bVyiG0blZ-Fu7~Hh^`b z>J5b_8Px<%HYx#r#HeWeS85w}Rh4|og9##MH6TIcE!kn<)6IL6swuJR06IX`sY)g# zkPoV)Sz%lF!0KTORtLUpR13&;f}6TX!|dGN0&*cyJ;!fV&qT`00Y7h1n_;f}80L>m zrSUU`FM2Ap8llm)D>Ovsdt=5N*@2PJbHmd&fTXO(l(YyFObMi5y|HfUAWKG zU<8*-9U#Hw19>2k|G&tiP96+~bP-t2qi+3RF#b2=a=rHBuQmt`y11XUy8+~<5#`DN z=zATlJ={}pVJ%kYsn3s_@8pvTmw75YbY|%0o^_eMpB=@nYiH?6b;=rd~4+9BpB z0diq3>mxnc(`x}qPP9nI_asV+47eYuIAyboyR?dTsYHQdmB`Ca)%w@wCAuk&RidLiR4LwF3d&{+34y{GH{|0utFRMM%TUeG5orr-o%1i%L;g;8 z4$XI-G`AahwfQP&>fcn$LmheRfJdes=!dC?9oQx6fcsU#Z0@j9A0+>{3xCv%|Eya% zX9H_?phU|ByPh?b);b?G6vrH{SUh9*P2960$Qc1hm-B<6p2hB?^ThU=wa>nR)sc3r zHGuqdrkr7cKJ{p=4O7oAd&!+dbB=(xs=C_0Nb~%ZbvgNh!Y_L&oE$gmuFrcFpf9-R z^I9nJD^7&N)xrC{BcONGOL2eoTEOAf%wEbp%%}wDGl)((gqv)>qkgmNd{c>rJ64Ij z+@jVGn3qU}T~C`z^bj{ziM)JR>%Z9g5P6AJA}kH+S!_Pu6R2R>m`1NdX3>cF2U<+4Xw zZi)@yi$>LfFDd10kzV(TifqFh3J2)pE-46jv{4P7+SQFpfK!Z$hJLI*bJ$C_RqMvp zYJRFv(yXdwmW~j3!e~J3JP`7f(0r^7!@{71jYY5y3cGhN& z1@qJW!i@qSuUGcMZ2?X_Hv-)7+%RyQsZ>#$ z9VQBH(_Vb1)MM~b=4`(dlDZg%;pV9JD`u4f zpSP>29^gw#<*P`VA#skC^%J;_onTVnDYni>S7LDzZIZxY9v>tqx7xKi?smK44Td({9$39-diKD5_(z?)sytq`;qU$nZ@D{!A&iBp?mf-#L~S41t>( zl>)aiDth5#gt~pmB1TKsD7F58c}an<7}W#(i&8F6q}8UF0zYBDx*W}(kE!O@aj*`>ioDPIrm6X#aaF@52^bmISRq~J^Zd6L6*4K!l1thSW3rPOwXj{NV zYU>n{PSJeDBajlDqR-x;xQ2FEgABL)Nq8M*QkT;(kP$BQ5Ex-0msJh-(rCCvb4e{6 zZy^`gDhB+(iUA*2G2mk>27FY-fNw#k=~hup*sPWw6Q9s+esTogYsX6ixI`)W@sGX? zfkw(X=WE(i#$G7WxYK4vgQ0!54Q+#=ou<@A@-mfsa<^A33MradHQ6ImpELUN7=w1e|_@sg18)?-v-=&bE3q6Fo?#z<| zQ(K{kaJF}NwL&Iu)s6GPI^c)-IRHGvs3wqh$asvU9~{~_2j(yrZVH%nT(~xv<65`` z%wa9uQD6>h;U<7NtmTkg)Q7-vE#$&J1P*K=7xW=8Q27zvhd{R_&RFn?zM(+h(3xYy zIru*98na0z9I({AaTVPgSJAzx72TUs(Y_mYb49Tj#j?`TEy7F9KGVO8@MR5foL z&3m6UF9DXCH!f`6u%LP6L$O|3Mb1z>x5R zIY(6-Yq>vgsVp7}T6GJx3qQ1O)PWxu>9q3Ga6LmhQCYcq0!~$`v-Yv!;L8UXTQ~(z zXf%Fg;CK+ zE!ABsO{EUJaI^AAAziDij1+L5QZnJU0Uu?*mzvMgaHQg>X;suTi=(DQEk}q)Dvr>u ziqNiz&?W-4NL?eq<*4yU{ZqTRku@m+e#oc>zW(m1owQy1>9*pcW4ZeNpjs8@aD-{* zszuAlw9pF&09lu`nv5oJYuzWSA#fX|+>(PWTjtcMW@z6Z{isnX@EoPq?28YDBnco6 z+Zjs=8lG zb?@f(NkV;pg(rGSm288R|B_}3#5xa`W=P&wYEBg3Yhw%724bE2YFGGbhrXy{jQOgE zD${h=MP3E?lv355!jSJH%5VX{T{3KENVpTlFo~sV@LxU&;3)mz#U+8Xv$ArSt=(6O zuPw~ic@JNlA>q@F5R#7&jS%ks?z80!m?H+yi+8)*UIlo8r_cQ()OJJ}zRz zc9mhg>h^1-*%q-5DZf*Gd3vSFNWY}l?cjHkkfH4@scP$Ys5R_J`Se#r8z1D6<;0)L>Cs~zb{ zQ>+754Nwf%<2!WkcXiuYJ9h+_=tFAL^FQW@NCrb{=jJq_mzO+%Ur=sXe)Bdu*AC;8 z-6r~3uADM}TPWo!L^|0k0#6^Hxb_HXRfIGn0^cBzr2|-w5YLymhIUniwneC04Q*gK zLOikJ2otL!Otc6eum}@@r3CPn4!FlQm2}zG>z7PE(B=EulK_MWx*M zBE8}jfo~2_49AxU*O*}n{H;+9AYt;LX@*3EiZ{q{|AhH!1N}?oO&|_)_w5Sz%`p3# ze&W2ly;M*K?qna+&s^Anu(KzZ)ey#da%l}=7f&v!A?)T!`QS)}J#?Et!2$2(xpCmV zJvSD-kLN~#_x0QsVE&GI{@k$x;dxceAG|1Bq1!@lux8D*W~IQNs+}8GB)rL?ymnu0 zd|~AVF*H0>gCAi@BtRUjU%Q|-e$2VG9Y((kit&@Wmedd!KWY3lFvBO@R4}6_+!Qc_ zCtMrM;0c$289d>R0yB8RO#m}^lAt^-)^0L-`DpYZ(A=UFgrBR03?+~@mbwx4@(F#X z;*HY#7NHJb_@u22i~nzJ~QISJQ(_y zJyYOyCBrmBy2~P@z;cB6O!KCuhFf=mfrMKwFp%->w2_E}cG&lgG`T+AcGhN$z~h}I z4vgRR^Q+OJl_vvS^2%$)y(TJjJb!`=_GS~qWcSpB-fM}C%fLq|w}E`xcd`5>=xs)K zWXCC2uhqZy} zw~R0{zMVD_ktM$A#2Z|GL$1CY0hs^Si3M6U=eM~LSG z5jHWyHV~hAgtkREz$*feF=`@^;BveI%X!4ttG8%twpL&HTp@v0i38(RFE7K6!(d;q7La0?USRs*Ba&IWw#SSFSN4hQBn! z6j(NlBd$_|x7llQb>Oy2Ro95&hGv)o%Z72pQEG6g8PG{c3Qt8PfJzi5UjuxuDdT&M<5nqeLI+!`Zd_(L;H zfn~$NBR*<|ZD83jKCG6j!5d~+2fj^ThOC})82-ZyQ()OJP8GwynPD4PHjGmpq515g zTREu#4_#xb8180Vgw&9Dx5SA*}E zVIBCOQq`$qc#j#Tz_MYS>S8r`&J63om1~TM;V;cF1(prth^y3KTYE3L4m{YXCh*ja z+@*jk8)>Sta%2I|G^z<4v2ocpyrg(ogZ;>YCJ(5ON6c3eTCJzMHqvcZ?cBZ$;fOWZ zX%tG8%z=qnHCqbXo|>eP(&ZgL>bu&s65zLtYElecsQ8M;qpJNIvr7J?uuFSa@iqYt z-)ky$VAH53koQ%kVBmaxa$P-@pH?65RjrD@LxO|Frcwt!sBchJ`^NAYGfaWJ&M9v# z1FtFhN;9PEm6hjUK!S>GIA4gkp;@(oya*r%_-M%u8=q zq+1Wub&6rek7{qOvZzfw`#Pg%ue5QLSv5k(e^SR?mixF2yq&vOCXCY#BmG$;@qVC8#L%!}Zf>ioA8sWyfk!Bn&oA&%UhNWvU-r~sDZOsJjlQr& zO*`AmX?5TqjcUE7uv1@RlEVc!&Zy|P!}kiyFa@qO-#tKLxS>Vz?xXLu;J)8{wSm_e zbrSFfrQ89B^i@-A1MfHLB;X51O#+gibB9DziPHcGE*U;be3n>g}T(NVsO zYEL(-hIv$QnC@!oHh&5LZY!4`<j?^W)UihZGPGV8T*ug_Qb6;BOj^$Al+fmpk7 zN4m!=0!Qdea!zru2)r~YLjc658!IH-iXyNaA-*uA^3Pam6M^{5BTUSY9`lO8a)kJT z{%AG0#S9zx!m#4`exGWSj2xU4^mB7m2R^IR+w(J&`?ARRF|wG-XFFj_iTOTzJFyP@ zWN9qo4-R6(w8}8PE}g1wFYyt>q~_?ZC%g*qZ$>pw&=)bkYA<9q?^bxfQT4|aK4(;O zuy7BW?-clkQ7z#6)sg)0?-LhiNF?JXF4Aolv<3XSnO`Pvj3JS@Ge`1eq(I7X(UE*{ zt+2Q)HQvsaN_|&_@Aec4PxaKf3TJt0w!+VN>az;(@)W5)>?!hm)>C1g%XQaZybACu zn>*#aIq^iqaC6m?iwj_%Q7z!*C0}WVlzBzqtwyE5avt%#UQZ1Oo-fE#lsny=HGpR- zC0`ipuslBL^}_xv)LoC6N*#FG7EW32Jbio>i>cF>cN$CwBe=NRwwk%d3Kk>f8aI16|4rMt8uG#ncnhe_V1L<`dmDIPX)t3TEQErlfICM)kl6N0nhR5#PxF4-XPvpo&u6W@tt6Vo4p=+(X5I??gkA`z;cCn%D({`x~lqC=xu>7`H>Ei$CXf_ zC!xa5yjM&3ux|6Do>sif%1eM(X^&+ttf)PuLbo1$=|iCy2K^7s{=2%ByuPpS zr=AL}P6$%%&gcEmXO!KHWC|9EeC5Y2$hJ!}bmrtcNm)^xACw@}+EU3YClNya?^;B$ zrO_k+t*sbMtQbxC<8N}-!jQ}yOFtMr$I=giI5w>Rm33|UGt8F(O(*2P)^vhWM$upb zkoP*zLA?YAGT*^5R7gQ}&=xHZ)G{JIe;sEQ4 z)AD=`yVSzhfo~t>LdbO@a7(4!ltCKj6@iBsRR_LnfNd@Kk362SJW}As=Boi5X;cre z>^{EXi`}1fNY z2_$i+h&06%Qy_`wSDl(DiObUjAT?CX_*7FOYxfBR5{b*rxSUy$NSsd~kjdU@BauDY z$duqBB2k6&fkYur7m2c*uIsk{_bjdKXS$UGmqd@TMz+WXUlkvM;E1Nki4vaipP)lmYkHs7ZGH@Zf1#X2B=uu`MBLB!5uHo_FDVlwcMg8aocH4V zgXX-~`*7$7s_m_ksj7XMStZwNDswHR1n9F&L*M7A1G?E+yF|bK;Wg2@#)8#>J8Llc z&4aN-`F@G>P8=f4Tk5K-cHspXLbnjD15B3#loXOFA1 zit8oNbe3xxyNz}cWXS^_qLf=i!vruKW`-&7K%*MKvak3= z^qMBIyBg++g7-CNNtnU}-PJUeI&ij8CjoC#%9Vq3k5?Sb{b{C>0%sZ32IA1I)kwFQ zVhZ#T+k-`Hn^hY~6*4|RV&oCq8IpHjAIv=tqupISw7;B}A&oP(>hU;xPxbDAyYJ{Cxn?6B zsI0^d`;V^^%vTDWXH*k-b1APhL-OvUTM67>V!qlytlg|fy2BJ(z?Vuv+ZoahR#OW| zxy~b!&#n~~f2ew4H33`SpYyHKVpeG*%a@|9KXt0UT->H>q}#QH{8+=v;$utn!3Ivz!b2ahm3G zr*89pfbX?D6W~6UR0~MHGXH@-iE$N4#FLmLZYU)IzQwrl8Tk8_SkM17W#SN(Q&dsTmGN_?q&x_0B0U0srLsvfzU zgLmpyC?NUBXBM+N5y(jNfG2Ajg&qQlh+f!``*(ND&vYy6DsTfEg&yF>O6BV|5r5;= z3|cRe4uzyrkphiiAd2tDBmC3mO!9`povdLA(D$%G564*#8^B|XO3qh!t*3x=T-JfG z&qZcb@)2JobAUcq{)8VD9ck(J0^hGxm;9J>hVT)uM@^(Cmn4^I*S}gC5wHz|{K+v* za-=2OB!7~wc-8+m+LhO=JClL0E7eu&>&Osp*U8gWyR0KaV6MogpFsLq=rMoDr{Yu6 zu*hLD?dEpp|5NJMwEPWfGy6N|cF&w8|G?c{u@COo75m_5-+J-~1Pg~Wkxa|M!sBVV zHhQzY+#Xq(?pFAqrv|e+#8grs*7*u4t4-u9#qDHPy6Znf(e{^!* zY;Tw4&bpPQ4|s}Ejj0OzJavV_$@@456|ZVc(Ool5r4Bsd5I;`w3yc`{nPCbn8^))T zE7jl@GfaRF7}dIJKNoz7Zsp46{sSHLgl?q`z@Hk`0zPk4;>`TNg!z$$OMrhis`Yb? zyw(2BQZm5jE8aKoHKSUodUT@Po_{IMS#Va66--3<$Hg zg-d{`Q7t0h>@&dU?%p?WU!z*U!;FeDAj~NiE&+brs1}i*^BLgtSnnIyFscQdWK@&^ zVdh%61o$nZT14LV09xL{=ULu2aE4JW;AKWd84%`S3zq<2Fseo5UY`Lzuk*fvbB$^N zZ!s#$fG~fxa0zg;@m4UAZ}u7B^A7JD_${Mazz2+qG9b)O7A^t4&!`rWpYs{u^9k=8 z_*0`=z~_yMG9b)}7A^r!Gpa@8jqR{*;qw*m8~B=0E#R9*MHvw0atoILzhG30$cOt3 z@HzZo#wr1hG^z#M&ZsB@!rX4*65tPwY7zNTp8-C1_r8Jq8r1?GW>k~`VSZ)d65wBr zYE4oHXL(1!8Ai2$ml>73p>QWXt5rM*Ak0uZ=On=GjcQTCvEDbZVN?r9zH+i6GN;Fi z3~fjB3$+PKe@&La(z765w2;TEJV3N`SPdBB?|pf54)}j5dfRt7E-xCqSSuVR&w9u0GVHCbvanFUhk6N>`|(j6!teM}EbxC= zH=Dq(DTFN&~;!5~u@DSE~BR!SF~kOo3&?`0{?N8ldeyCqu%PPsD1$f5)nI zqT7vX)5qP=Arnb|%eE;1J(O$g}*nd4!q_F(*oXL zR2_JWQN2#x|4RldC*UXrK5gNeKr(TQDH6#@fk2Xx;}b|Sq6PGMMQ4X=H6N03GY*M- z+-I#wo2TfJ%q-v;=$wNI_AH%u}|F)_<#G= z;kD*CA^X32>IxlQN|5!)yKsmM@0j4^imAxFJIB(ghh9Pzc?!3CH0wj9p|w8w;p(2X z>Q%h*ySJwDKHcVvFSw~({=M=G^n2xP<$5djg|*Drrv1SVjXH4a_tK;u;Ao}XvWoO) zuQ-_dhs}Ko+|sOCKpeWm3dy@~4d(t&=DrPlr@5aD#9{8fogsPmlSB8tSM9@&)qOPNCOCUh(bJ7Je{MvLoI!INm}tH=BbJEM@wqpA1Wu0 z`u~w35VGo;Yn2)teWWW(PBg%qk9L%s+eo)5D~iB72PlT^Awtt4q`*Z-5wr#To>Fec zBN1FKpMV6H6$?ln6&G0>YH%XERUC=n@`ZJI`5B4eoHdZiz-c3qg!7CYRo)SD=ttsVd;Lj>2tIFyOfl;VhRXE)C zvWXpC!rZ94R+>t5SrMwpjb40N5h}@d)P7ZqE-KLacRQ@cWniB{BOHW9s{Ulj4E(fm zO;8FlMDM09`oda4ul^mDJ27cTGm5&*6R({y}#QLlmcm( zB)7T~fsP5exC4QfAhag&kX|ogz{BfF1wXRea`toX*YzY$#eER(Ot4bsUjf z#Tj^|I(k#L`LY4t+&uNfo_fMUmaFz(%&HFTKh7z;OP0Y5w^1$W9Pmt|TEMeQzS0bd z2o)8Q#G9H|QK8}?>MZ{rEO@wa`($A9$!$~J-`1^MF#>y(Dt?$HPAyu;$oebhst&x* zs1*2JrCb-0o-oBa@V7>#z~2q9MH>1+Hx_ch19woWdZ=cr8?x-KO_wV(BocMkT1X_C zU$5mqUV==v&Ib|+J0D1vu=+6Bvd!}dYan7c;XWT!A?1f9$Q%swukOhIrLX@9x&5rscC zst)|HUi66;@S{f6f!{PLdfY$;hgk+G@F5E~2}maSoJun!l9953BqL9jfFvVYK%dv7 za4!8)J3}&V4M8HG?%HLtRv?iNcaz8@<$NHKm-B%{YEBo4M4fJ!>pwNuw{$D>2>3~D z>yX;{`Ja$OT%@g)tBCm>2;WgMzs&^S>$xf5`#jeM-|x8u{GjKK0@EsqF#*g>lVle4 zAv~prJx8=tH2NS|TD1ElNb7pQ?*UdkfvLyBlf?DN7#b5*oXTC%n_t>Q1dg z?%Kl4gbEX=xVO7U9o?tfO=>e=>EKh2@ng=<|56tF9#$RqAxg0;tcJNlRdO_hDvOnQ z){fdba8JE~b89+MTUj|D0FTz|lj_Bv2*0)nDR3wA)c_L49rQ>im|_b2j8P5XuBANE z42kS29?<=Tl+2e7pzqQ#x{I*VLSV1%%Ku_Jm{cSfkUU&PNNdRIR`q+A&kFdkQH{qG z{@$nr_=-^t;NOf&fL+?HioPVe>k3n;1Ftix0sM?oZupVzFvU9X6{8x!R|nW4)$~&$ znPb4MjA{V)GO7;zH=`QBPa9PS-fC0>_%)@fr*N-kNfX@l3(|E~L;llyNc4egN#r|B zJHPTodd1k>2NM0j2Qp1@c_7gj_Y;6fw8rTo(H*CYM1!0z5v@ z?hIj9PY%ft_VVP=3}L({*UJzN^5n1#;V@6GpCKIK$qh1uqdd7`hH!!>-o#h<9~R8Ik?8kJtG@J6Hbw#2V@vG0^HXPZ?Mh{HVfG(%e8 z6@iZ{Oy)RtfOCMm2#r%Fm-=N=K+V#TOqSDAzPs z4Iuq5e)boEE>#TSQgtzUq6;iT2ppv!(8%+VIU^C?>B%LX2s?OkaVNrPPcG_2*wK>< zI}vvF`sJ<7rP>hio!8;$kf%J%rM)7wwCqIdmA9Q9e<7GG$7@neqsgKn#ij=IKQ zt}$~RaO-4eFQc}g8{zBvK5VYITJe^eNTG;8cDW*Wgrz4Q5y(APB>y+GbA?BQ3;)gK zlPiL^Jgbx=!p%zNir^Q|FDW9tqtqENT`NK({JEqEE*%UDx}9_XFMZv;)Yn6_pP%-9 zo!9+k9odDt&2y%&!}R%j&K+>7bN*i4=G@BD9QRM%7H^^4aIPc&UAIF1HLI%Q`HM7N zJE%obDcihPQ~1z_9F>O!e^fc?RDbu+Rp>dzD}papu27@^=1K1HZ#sdP5;@0I_@&O7 zoV!V<1v4V&9zW9sWbg}4C&2KteKI#qbNCy&&GpU?dX;ld%l{j8pg6R`7RZSqY(SwG zc0lyP`U}0V0Rd^{Ky(F&)g949Nf!a)(eaM{W!U6@#us%G$4 zbd6`UI&1r7V1`LTF6v^SX6YJJkO)KUY|{i1ywF4Nne3N=OH1XVu5eQa~JfY{NEcZ-zF$I=p{<5l>zszPn%c&SM^I1)Wil=!G)10+bv^c5yIo-pY zW_1;^26;2tQn%m z3URuh&RnL^k&2HKnGl@9^F%M#VdW6YIi~2%rL!RTHsxf70y(KmL{>2J%DsU;p zS+8<6@acNlDc*qpsgxW7v%9I2;mvKAp5aF0@4A)bfE(+HRonp&F)9HvK|~A4Vwd{| zGih?QU;)h4w$>B%dvsgm`y~~Ap zo2jJ)mlo57`H-uzSd}m9StNdEi$seNzQYE+6)zI4H4Qq8 zg`^8)pz}Q9;cQh6XFPT-#%`F6U5iEH8@5QafGiSu%)@oT@I$OmqWwVst3%8xkh=#n z#Ki*4ARnUxnky!XPqjf#fQ)Qmi%>PpjBTN~E{i~+xGu|pQ>-|_Fl89^LJ@&uJ+BYU z!CojLlqUh0kuMYxIFfUZV2j6xBCWhGYxGl2?41Xht; z5zJgE6cLy#xgxkUaprd;FoAMKFbhuM5rH#Dt_Wr^DHIWyb-7|N=W0y4^7Sv6>tJy< zryF61(xWTzp32Fj12TOITLk7$o(Py(Q79rXEpkOLgIy>hFxt5yxX*6f6JTjF%;`p8 z0_3(}Mym*dz;NY?U`ER+R@|#IbTq$E47>jsJ^y~z-$4L>Y*dT0OH?ap}I&PCoa^jj2Dn6jTIk+;NT2%lmK~NAXa2D*I$MMSx_r{lcaal`j#el zpHC9#lWY;r`;HoL=S0_%2Xrgd0!trTEa^hvGaDJH{uu~-W+UY4=?HvgBjl>-2z+KE zdhcsfF9J}&7(;PU~g9QdF= zEiLJ)I4ubo{KpExBNX{*)CpBjneMWuOt1295+Q6gwjED z*IEs5-`tL<*5v?bBc42tAQy&ChBbalxsb|Hq7qc zRE525ZAgHngJgDhSfm6F>&vO2v?6X;7YUb=^B=*D@yYdfhndJCUlF0dJB&d2|E(>N zG<<|wIl^F;tJG4yOvHr4uHu(#zNFfB>oy+(@L$YR50JDfE*5SGJW0hk@>We!`Y(G@ z)&#y~R08yg>zkW3`|qO~?sDBqI3P92WfzbPq@Anmfj-^~(i|%|M*SYA+o82-waeu1 ziXfk=yu=04f#Q#s)`I_b)!QW=5lhg!h9G=Zcgj5E(b*yPV5P}(k4N>%R$=;c6_%ID zAZCrAJP#DhIo&+k;li~b3CnYxg1qRX&LK~B3X*HOQs6n=TzK!N*V={Vd=)rl79{6N z?vo0V8zi376eJJYc*<6goItsIa%50%E6VQgrfi;G7Mct~sqFr$ zvgMH0M@FR-1)JR5)frh4tiA@E_GMpJg5c z2YeJlJp(>(2sT7VLO_H5d<$deLHjEz)COC>nUVJ#23PA20Q^i}vv(J}2|<(T zr%+XmvwI?H7rmhH+GSe#4YsBxl=(heQxo8sN)^Krx?&FBXs%koc}jKF&hN+&nCo)l zA*AnYbO((0^VZS(7rfqJiF#K}67^QmQAGlzouB)|ymKy$c9~8M)<-#DFmfxsCyrdfi{uoc^lj#HToF zdCDTR7HBDyRIIu$X)Qkg)>AXxocpP63%!4;&|xcS#fx+MYOqNbG<{s5&!cx`6f!!c z(I1+T9|&~+eb#;XnMcKmZl#aFSB;tsq{iGEgG7up>aWmmiOu*#hba(lJH5oP&_j~&R&P> z0iI}70_06Oxl!X8dY3&f?*VRPR08C+I57mCV_H2Q&<9VbZxRIUlJ}YTjlgl0D~5ICTv$fVQN^G2 z23r<(Ad{eo5f*lyKE~i>x%?Nlz}MO%j^=+TyxmiSdAib6>akUQFe{$4szft~~$PL|o|3$7Nd@d925Bo*1M>MER zkR@Gw5P*|{3@z_c3o?-gVE2F~AyjDfeZ70(rcGSW@8%f{_f!SRyKsH#tRQ(Sjz|T$ zwiq&cVFaN<|3Zb{D~7!y|2ZQ=?~>J=k)i*B3?md|nE!9IM{nvjpCn-VCg&cazRS*Q z(Ya@)zS#5ueN-&x0Ny^}*{)FB)3@whqXti~D5B!z5&D)=`nyB#1sVD;$S^`dhMgeB z^;(B0&FMy1VsCA=fz(;(g}HRp+GOHiy=((1zAz;@Ub!krgkx=Xw}G^&&>O6XQgZXF z8a2P0^h&wR?dpLQtRP`C0e?e6FVLu}va z);m;xlx~OArq}i!lOg(Ux9G(WR8x-PuoF}CvDta{_^b}x?-Hk6{cUCpKWBz1uv-l! z9B^pKSDGR1NG?8g0;E@EVnwI!Y6Bs>97068zfrnevlrC z7W3nT$n@E1BhhEHk!iNmMxxnhBhzuGjYP-MMyBnWw>F=)qm4}Ooi-A^M;n;|aGgS8 z0MJHe6r67)#sqCQ4g9~?=%~@c$mDWAZND$`30((dmC!@x1(p71?*B>bM_PEOvQE z4sEKnjn!@b>305y1wy^B`*QkuGh@muvw6~FNZ#4+JQR8ednqY*aKMwxdI%hHa_(ZJ z$g}XbU66EsXH5Z9bYG!}z;TuCi?x zJ-5(pSMAbS8xE$#TwcF+N%sw%8_4Zx#yq@EODpXf%nOHsJS5&q&p8Z&P&A(-Lnykk z^T(Y_p~B@xC_3V&?Bwlr%08xB(TZpB6e-&y*|vAn&wdokMmSr;YU36 zZH0b~YBD_CcBXBHZ3qt(xpJlrhg%z3K$h2`GA-9%Jthk$U+KD=Hld3Ay0xtZWI0Ba zc5=}HPXoE~fJgqe^|}S*@&i@m2W<>mK*j)727>NOZ9rO#Dt-1>G|{d3);i6$wdqy| za;(ea6IxH7g^F9;8y?xB6}C($y7gDn2PQJDD_q8X>ka4UG1@QRr2nJ&`Ty2rjC&Hzg}A1F@%n{hNiIXewAXw|!;vCd zah}ojOPHs-N(kquW5a3cSY|2-J2uSOvEdYUEVG!*9UCU^*tO4{fARW-wB?#3%vq=~ zVWGlog$h#@YHfKIR|a953o`6-L558($S~i63^OjsFz12{vo6SW$a|JuWR2Iehgi<) ztjK#-XGM%zorA^rmrv8wx^CxWrk9-ZNvm`M4wK?^c!r%J6QEzY?Fp2hMbQ~g&MD+M z#g^$7kZXwi(IuF3qF9ClCsdf|&YB=u$zb$%R?L_F&Wicc-$`x+EzHBP1sMkB%FHj@ zJ>i6w+x~D`2o)wLRG6AjVPZmsX$i$ha!wLzZF%OcCehclc{vBBkrkJQ#VF~;jUV!6 zn7!Ozug=2!bK9_hoC_<+xv&Ic5l9voX0tz4H^TF;XvJsWXl06hxA4ssmdrZfiFyUW zWf4~vTsgoabLAy2fMkqnm^OTzdo=gs+$WPeiOOk^90@E`7*nV?+~lw3`V2PY|TrJZx&jqCzD0s4v9%eZjuom+zcALiZ#zK*JD z8=tfY1r#EJ)EgY2V&zg#+9XW`HKi9?EO4485D+;@lhY=UCdZtl7eonyPyt^eFKE$X zf`C>5i3nO>L8GG9D^XFZc!`1niWn8Oc;o-9+3VRed-j~B305X=_Z*up(BiKmh{d&+8I^d^e%3HgzHMvV#Nzi93i)`ludQ$s ziw7zc^6}&VyVPi6k%0;M7?($F+BLEGVojcqk0*>DYRlkF*t~0Ek?{;g8O|f4oe35h z;gD~t0NV{GhM5(y7g!lOX)n-K`eiTBH#%Z3lyhcc&|Hxx5OuE(x9iHWGSM;kZJkM< zmuMb@Ad}-gagdpCiA@iPU#2;*&E^6?=E85|ARB&;%?5D(Mo$jXYzVDS?KgJyeZK+v zegpLV2I%_@(Dxgl?>9i-Z-7a^uhQtz0n=TR32V?tG*_7j&!@xF4*M^<0E;wTuB*^2 z`v*i>q$mGJU4^dE51YoxDA)`1i018uz3vgT`A-eMOdc$^YVKm6H|c?}C5;P4yBrz> zW0}1(W!sou)Tu=gWBDY-UVy%e_iT6?IhT9B&e0LEl1#%-X&k;1iwDaOS*&W9sR&$uD$msrh3+3ShI#gO>!N(E!NN-@0QmGtz@YI}!LY$)7h zUAXTm!ybY>S$4Gn@xIA9TD(kY$j6g=BR&>as~;gBPj*M(Uxs-y?|m`LJULlGSZ1*| z&UgBCM(8}H5(1Y0dVNe`aDzFyX~48C9^c z$N&o)%ZxMFSY*hBjpd(d#}-=6 zW;(;Vu$sjt3*}gh%z4{gRJ2xmk$9QbxM}UdsGjiOCZ|L;ujPRl#`67&;dSC~YVqBg z@gmCd#}xzHXSDca1hI{-)$SpZX`znN+>}_+S8GKvp8ot!jI%sv01gOdJ~P&Kp$OSP zY}8SLGCXI-$7Pa%qD(Sa#FGId&Y&?;aT~-g(6CU3=S=OmOfqhiNyd(NGJcFxlg1Ca zmv?BKh@G$3Fod%h3#(;M37@^jYJXZ2ByNUSlt+y$G9qzyMq^l`6u(9+%C$xoA4y>+ z7Uf|hi?LYSN|cKogMlws+c2DrLI|?@tWOBCA~Y3(NgLPbd~$B@5Fkz4v=UbO@EYgKkx#!e4N1p?Oi{!C; z)d}+KoxO_r;ap^J8CU0GaujkdCdVV^VzMVW7Za5ZexXCkZo2@bxk@&ElmNYG&~o z3wa*U%-Pmlj>WfGsQFJ?cX|R3KA}246X|C0ehW3TxYI(O2Q+h;HJ4-YRtq%`Y26=; zV!&E$jdZg(Y@ucr=`Y$U*$OoC8EY=b;=>kdX7uR^V(=R^^CxRA$KtaVYG!et4;jNL z9?;B_)?ALo1Kvxi=7T?Aif1Z?2aM}O)?ALoM=aFLBK=MAfM#B4&E;5pgN2$IeR={9 zj@DYui)zPWjfI+7Y_O2m3N&-3HJ4+tXrX4-{n{u7jB912o5jN|)XXCNO^E@`yvv%) zv3QGxnrZpL$OG1Dr8SphakYh-Sv=oDUJPjFUTZGL;*TuUOv?vvwW&d!7eu;Qe4B-u zS-jXno(DAZgf*9AasU6a=4koM$OG!!66t2~S_?I^_(2PK9?;AythpSECtIkQmamOG z*r7Tfh;*~~EekcX_#+E>9?;Ag)?ALoUJEtT@`I5F)cLDOH;YeNsF}rQEaZ7WGnZO( zITk-+q2_~c)bT(mdLwlP(G3WT`&p=&#X~IQc|bGwSaUfRe`uj*)}5ZfgRJU2InvGI zVhc61$Q!1V-bgc#TXQ)UXX$nZ%zZ=aesDC}u~tV|b2%1YZJ}ls>2Hb$H1l$6F2~|Y z7HYmqJ)kFWirM|qsD)X)(?ZQGGH+8npqbOHxg3k!+JQONoy!tHmuN+=wiV8?c%6ls zS>*k7iU+)r|D^7p>=PXDubIOdTUb0&q5XrIyKh(%-otUt%%v!vjGDxa{?ZKZ z(6E=~OPxnQ@3&PrFH&Jj^z2Ey1=Qjz^2}4}dnz>}STM|Tq^U8fN!XGOWOW1RD@t)6 z#^S(-4KrSX`JxsNRe3-Rg;~ z@Au)!rz3D^22bvZz%4U)a&H6<&fv*sBXD;GPd*oclNCJqd;~sG!IS$VaH4`IUx>h6 z6+B@W;rw_7Po5qz)emdLlb75~u(-2=C$CX(-(ch1eUI5$!E;73)KD&#_t;pru*mR1 zZX_+1Thn4Wlorb^X|WufkrK<@X|bG4i{%q(v7AVYt8x8D zjNnG4n0#2g$3jh?y2WrktQ1dgj@EH*t{v}kEH+uFDe2V@)bh`)2RRlQSVVa=Ey}IQ zD2L<4tc(paN8nJwz3Ri~tuHwiW6d$@HODV>FnUHQhVh#<4pBV3k)4e=paGVxST-Oh z7s1$goJs`aT=Gt}C>XtX)Oyj#;$s$iD~pG!gCa?1Z?lcp$l^yW^i~$1j7c7@ZOgV6 zZESBgwqR^shEcF&GbiJLhcnN40SUomL_&}u;g1D};J?&L)H3HEtnM=aNM06MGdz4^ z#h4#}SY#bS15;H(D*AjIl{FCAk7>)@V_PuC;*TwK9-IED2x5^n7iFwx);8*SZ2Eg5 zC|S?FX{-O!YO*fOPSM9QYk)3#&x{YLpY%5b_r_xel|2UA*}=oQ0nb=5KJjZb#N3Eq zW0ElYE%bELyV_K6w8Jmc_&dAf3#C!9je+Ng4v=Wo#LFe-R9 zU~{IKMaIZ5CZl7}WLylIjEF&#u`p;d3I;7#fBJ;6HR%wbq&I+)t^i8<0VwGNpmH8C z=194bw7Dji8vj{YJJ+xZp@L*3LNHm45KLAi1d~+>!DMAZuv~TM4W3x_d~ik(Bpo82 z^oe-VE#gVfh$o#RUe3Q*xTm#%V*L<=9W#=Z3&CW~LNHma5KPu71d|mC!E&{^e#Bgn zfsN%aDux+|MLLZK;7ON7k{(a!C@2^mUS*eAZ)K6=lCUMKAQ)>igpgx0`9+AELdnYi~3w6FmKfG?4uDQiyu?SFzSgV zRM%w%b1dqU%m8Boi!_5eTMb$mRl36}YGm;n3Z;9{tXI#rf;kr7VxiR+Yw>am7CTkZ%%F71Fi$pE?Vc)Dm^(1o=V7r`rCt~e=yyk69K2?jC=DKFuNIZ- zHNwWr>s3j_)*ol%LI=a( zhTt`o^4*xvJ@+R6yI>}i@foY5k;O+U43_c&+u?fYD9e&#vC%^3jA`)!3*}ghbf2S! zJu)Zqh{e|_l%A5*KyJJo$zoj4|1K+Euq92f#asMmRkBej`aX;2D`Z^dSt(*<@j8c* zXZq9;y||G@-S*X?L!~V7U0Idp%Bo@Cl~rl3tQz)R;SDNw5a$EWh z%`DO~vVujLHCe&4$Rg)d8Vs(`63t*VU~#>*xSEPs1#qz#>Gnd(8R9v$fyDufk?!-T z=!@3ec`Sa{LOB*AbKY~3WL0D($GYsaF04w{Mc8aOv~V!i{c;?pG-X-yW4-i?h=oPm zL5GJt6w>1UO0mHiu>4ZRUKEr9es}c6!O_20_^^Gf78YNrP(tEZg-?qlSX`AZ@fL-9 zB8grtzBhtcyk4P%S>s;xceO_1n^8muJRu4ZLFTwaQKz#6AbHc6h8TO6{)VwkKdv-%b4-;AKn>t0Eo z6iZ}@Wlqu(Gl}VeIfBJU)p$6^@q}SYnYVtf{A8UGRC`V*dGJU&=@D6CiI`+z7iKof zXOX7jNeK_t#PU0-g}s(pkyfW9Pl_e7#1cMf={SwvX|~C;!z{Cru)?P!O!AaPKQ*7C z1&kLg@=nam@jT-i4U8<_r?Q5TXFrTIviLWLk!Q2*oYTnS0)>o5p1nR|WO1v*sOmlP z2J6Zy7Fiv!u*%+a>XUm}im=G)7)G9rM;cjVbqpiVSR-g;k<~GbJgc#lTg76$a{h{( zwOnRhX<;#5xfWYFeYpjdYhjVq5m#DLq_?wqvBos&|zbJ8kzPDB~ui$>GEPiOCnM;u zT0F>_%N?r4qa$dp7HcCY8Lu1E8Q$iE9ZZ$KKxz0mn8A66g2Kr1C2>Zc?2Iw8{GB)> zPYzb^L?g?rOlX=X$HW*}W)(w5p0E+Z$|P!>R$*ph#?@3HEJASn-TIP4J7wm+LTR7MSx9Mj*W7Tn!!XoQ! z757FQ``yyh8a91Jile#>FBPHW);z4{(&fv*BsPTsq6 z;6Yt>C^vPdR4=JGt$LL@z`oWFw2f6-th3N67Mm3^HRjoeB1Y@67RYj`WyxKk#Yl=t zY=xI7OS{rE$0zjKZl&lzEdEO&<0a4bn`!i;U0CFzIz8=PssbHW&>PHNrk8kwCJ%2C z$8pM%w_3dFCbgthcTmM|v}zhzyjdYr3!dE?F|xSbLM<%*%aNU>cRPnGH5z%w$3rQV zyhqi1%UWn;kx~Z*Z?{9)+XH_jqwSZd?R|r{W2`EblDe5v~BPO-*Pz?#shiEBAuKnG`ue-KQg$Sl}FT}v=pMu%d`MbSmZ4c zCSw-2D3{3ro^b-&!>oOTRlkbGD=pN-A{C1IRl_`s)N?Xa$sjmVOY^L*oG;~dtr6wE z(@Hh6IANjHEdEjv$$%QXOTrOIKIUeTI3Q1uj8>u%Tl41VV*_m&!alhW3|Ao6bvjZ zen&4=1ZPnZBLs*=Rsn)6M&`WT#~rGZ3S&~(*$59nZ2bcwNaZYP&`aDD!0^E0->uYH zEIy}@X=kfM3%;&Z)b*^@)y!gCmw*4|>uRAc3eE`Lw=(Gh_Z*@d{~U|EtqWc@UaFTK zwk$ao|7M}pEdJX<-pYWAu2L2mkXgRLik-vajS9^SHdhRf>d9wgvMhf!l4bE5aoJ=T zc&@W2QlgQ?7wEP0CiDgQ96yK)`t9Wlwxn6~Z!vwrbJ7I;hfx&#f0e#d9UD~2DfR(9 zAJGOpK-aAbTT)K`YUR+6(g(L#3Aey*Qla|yQ(Dd*_Z6AL8RfsajDP>8Iju)V>0G6} zOvZ@My1=7-m5gh9{lYfgZxwJ%!AGO zeo8BqzDj9Q{+UXHJgaoy7n}1%hZy>Tml&E;+NShUrRHk%_iUB_zS8F_zft9`Q+k8a zo0LYDOleZ_-AezV^rh;5lK)Zld&QyV%AnGpC{6NDyuu)lD}7q&b4ru^xmOzGY^7~V zi%OIHw=4cRrDIATE5pA-*V$iF`W>ZzRGQR(miC*U=*x~+ha`D+%M&C>JHpBKK!=s#HLiPIbP}Ol&(^mSK6U8DSx<*LoZi)gwh`$W;mN(YUqN) z4ZT3=ok~Be^mj^=`oE|1E?>oXQqQ^8|A_YE6`C(+DlI6zP3c`qllu47@n*eJZrxR@ z-uEQ*B;{AA-04bJDJ>{X@>Bnldj0Q8X)nqD67_>`pB|~_<@o6@`_Bzi_}{1cE>ijq zrCXII{dq#iho_W2qx4tWPb#(F9a?6+aH{e(DQ#2wEu~3&N&d^G;J-k}$G0h+qy6z? zI$lgDt<>?ksI;VXQ0bV`eY8IwqI7}M)0HOuoltv^D}7q&{$<9iU#XrM+Q0WzdTg2g z{x{`+PAU11D#L%HuCs1cdb`puDgCq3zbpN>(iyt`dV$hclv$5GsQvs$N`I~Nk4jI| z{@5$UflxB2XsZzR1X=|DB=9jvqG^zAiZZUB? zGEsr2UT%O%rGHZTSEbJ?J+#dFYmw?(skBXLQE8I=T>);I?4#r1!Af7E^tDQp@*mOh z<{_mID}799lK&r2O21HspL}=e_3tQsQ0e!TChh-3@uYp)c|fm!Luom^N%?;$ z|Digb@p;B;^qh}CR+Jg+Q;?YB+wTa1UMk>GnQa?^#M;sPtf^M<`AD!}k?W((6l=o>qpxq&VB%Q+kKeFO=cu=jQsfecq$=eM*!1cWArauaqCi`em8+n z?N^k3P3iZQCiyu}pQ7{gX-eO#^aiD0Rr(#J-&a~r-=Edqzm)D@hX3O_zu&2JROx+6 zzoPU9N|W}^(sjY*O0QIUz0w~meM0F|N`I*PEk9QJ#H*5;&H1BcqAE;cWj6CH|QF+RZs66Ew%E(i$r1F%TPa z8DFzXBhO8Va+R9*v_n0VJFAR5Bk8DNjN~cK9#q8W$evuFba-WTBCH4 zQgb!>d#&QvDcz=YMCq+c?@$^fj>i@Mt(fCEB<4RYoPFgbOgNnaf>2*rKRED4U zul4$$lxCXJ_0MTG_=!sEmA+AFQtGjD4Dz_rr_ML$J#B_gC|$qCoWG#M(3dHF|5|hY zh|+DH=6wGyL$~RT_FZLexWAk?d=D%ArP61V&S*8)pH)hK0`iM(3fs7^kk(Y zN`I~N4@zIM(eU*u{qrVse(q*NuTzRQ^gqe}53TQ=C37X)Z|L8YvOZh1K1umbZI=n9+4BrXpVB1%J&J!;>HjFb^R0%H zd0C_RS*dx+JY`;P)^Fr9tsr0UkjKmj}Cgs19$lGLIwyNAEO8-kK^(OUg)I1r`{{3#H z?DysJn0Au-G8Y?UuF|a18l_48wruJoNsuTYwl-|w9UIY8+_O24EubBVcr z)S#hRr4338mm2&v?=m!Vg`q=AN0joHI{91J{6$Xw;4gn~*GNZyPn)JcgX&kHeof`y zr_@jS$6t_-JTaxDUdpk4l-t|-Rcd@0=bsL$MfLx9^`Ad3PCN9ooE`q&Zqk4LK=Ink z%oYAjD)sRvSd;BiPT#_J8$FXs=^ypdKk7~T6KFjTRhrD3BtL&Xuy~cZlKhRt?rRNx zk<#FO=A1uJ$sd>Cua)r!%920pz+e12_$DLIpKdf~(chg{n=u261B<@v)m{Mn?WJmvB#Pq}fGr=0!K zql5y=U8nMu+7H?k^L+?K=MQ7j%+8yPVXQ^q=2a{?41t zm8X;*`Vn(}kJ2ZVW^OU~r<6`81+2f949DUqV#m7d{LR-Tb9(vFP_*} z{dl3$LzMD^Uwj`VDgS`-eP8L1l=6$flKkID@beqL%JKh2`FAVjH&o2l`n^&q-`h*t zdz)VGS9+z=A*I(VW&D%!Q?*l)|F#N)d|GKv+o@G)l7CG3_~~f!T~LPqHdSzk(z}#? zM(McHT}qRrTJ4>rbdk~(N>?d8M`==?Uoh0B*ZCbhcj`Io^OZ944=MhL(w`}POevqA z@^cAE`-f^=UZM0TrLR?5rLzQsZ1rF=>>#KFqf~un_<%WLWb<8zYndr{?gUQ`|HYP(`z+4n z*cbmzV84#iB=$)5Wa}vrnZni~aB*}BJ@w#eokGu<;K@zFQvgrH6g+PSPj(6(c{V6NQ}Avw`j(^2h^j z@!mc7-seGpXI9*Fco1~E3^+SPllI_{=NglE39gLtyd>m#P@kr|OvfwFi$WgpS%Dba z>lHdQ2EJT*Dnp(x;>>4jQl3LXo`><*Kl0!iv+eG-C%HM_y%@mEidGnMtHyC- z6|U>Jv3cG4uAX%#V*FTBSl88KMv#rLl|_S!TPA>)3xehg^U$wA=)jHOkrjc-Rpz05 zH>e2AtdLFVgg;Sg7+WctnTHa;a3o3N(L9vwGkN$*l-z@PC@pF7a1Kh6ZP78WFLKC? zQAbA?V63X$LayAoBjsgo8*w zl((27%^w9K=@23E+4o8Zk&&;#L4E}!=OFtbT7wQEtJ)CIM2Nxce)yz?AMNnQ*(JZAzKad_4M$zXVl^lT6*hvz*&#vPuU zMGBoTlG*`82J*=Iw}8lJr6Qi60cmwKOUAWgpo@4a&?mselCc^^A{ka z4$my~fa1&JdX54zcHW8+8`NYVBS&VwW9&oZFTtat-#)H!3jza9f~;_&Cexe1PFJ(j~2bTioc zHV1pl%XzQ~h*+6f(Ey$ydtC~g2OCfhGod1f`h-)OT(*a-$7B^|)?+_7ACe}xmcy*a zWb`-dv3H4E-jRVGS%sPP*s*U)TOZ1LOj>!W^_Z-}Ff5>6gPt#9Sk_~*3aboxs?b(W zQwU2S>oHk{VF-dAeyNXKi4IunRGOt2Bhfl z^Z=3BA@b)^;i-x1`7n^I!}BSTs*UrE1F3X)9tASAFwV0-=89}x9C;0pqJyjkGJz(J z{8=kJ^>L~H1~TX%pA;zv*$HIK(ent9?GExZknuOhHNO;DHR$lX7RU(tP!!chAfpa) zDUb$7>Uz=B5SMxY$dH3P4kU1-{tl#dQC#W>bkL$jIQp6FMT{x}%r{>MTc3Y8`bm$J z%t*^{j(!ce9*)@PG0B5>qpw6mn9*;O$Hmd_dKfaJpL|EaDUK?Rej}(`*rpZh#iV!0 z=vTx|jT!x(UKRv3;=Xgp-RME+31;+rL)p>qFQ;sFxR_aP*Tm>(MpP7T5U*e#*LS}Sb9P}Ly&8(4QlK)M4cr@l*-V z1&Wl}i)#i?a9UhXJCNm$o((_-&y4$XJ&+*>xf{rcgM1%ItK;*pflTD$dgL1)G7itn zfn-<3d0r2svN4XV0wVAHM>XvLGV1Vb6dnh;21ssoT+eMl#vMI7fQ&gj4*?lsRHNdF-Rc@>ax2U#FIjvo26_GEKhPXS19RvdW;kc=ZW1f;UX@JRiG;AS9$ilB?& z*a@W7k$MD3!?|(IyMg2!b6tM=3c)kuK$j6bN02z0reh(z;@Kj*n$vMbuAfr~w&MD!T z01qlYiF*(CyI%g&bBa9SGIPo+O_PP~X8v$a*@jTapgXf-6eC)9j3Zi6XRyQ#BUbU( zvUAG$_j69EML++rXHVvoH=}1Ftzj!yc1}593+I$IRgN=yB6G?R${4DkCyT$HsX%r( zWiQ3dDHBpX?~plVBU%Uv3O&og?N1r9qW%dy1siwRGQ8p=L^yn z&+r}~tw&LcxoT_yt@sUOaRVJYrkAS-bK>B-CG&E%UeSQ~oa}IMjWmiXn0!XZPaMqW zm0&RWEIfX?%KGQ}{VH_*GYbyAG@;4d{e1{IZ*o%<=w9UE@*|jsL(t=P4d&rJP_KEoxu@M<-CT}r z8EiB8Q*Lc@19*yam{C%v?LfvTB|z{^AoA&~C|7?b$Qsog^86V{rNgr?T4uC8p1nr^ z8FF~4fCOvfJj;M&Ey4^pwU7+|`948_0XcR&pA64IPI4_R8qDz4W3;9f%Mo7;g|UMf zz7tAJhIhoSnj$m2!)CaQA_!07kPP3359y1AnH9%l$L%`_4wK=(Mar2BFPUK>!6g~~ z@y|2ETcHj>;*boV1U6NMkJ=0$LEZgBGW;HRYBIb6XFi*Z#^<8HN{we$tn?XxOD~w% zi(atH_JXa@gIlK9!CoNmCzxK)+1p?29$1&?2(8GdR?Voib{CZ!z%y>MPLTHi8Ce(4 z%v*p=I@$XfAfugeo*x5g?TRCR2O`lzg~R?61P7o!0;UL)z3w_fR5E+-*hBWRr;ITg6RQJuX>q zycJV`$?){g_)CWG|4nB2Wp0;LjgsLRWWrP#o`WGXh7YA?reyfN7+_3>Ux_oHO)~tW znEgzKXMG0vBpF_b@P=b%#c^J}1(18#Vus_qyib#!;qpxlCd2zX`wDFxrToUOo{rv) zCC&6>QK4~WRH`>YP%Bvnf1>rXe1F`CgPbRUSs&-=7AXgLCy-GGxdBL~Coc6#AgvB^ zzeqXAgTm7rmwFV)go8W-BwLL0%)}FziMPd(!+{hpV4N}R#M%pC3y&)B4E9rsJ5L2E+2G8~UjtpG- z`-|qVzh90p`E1hPe{1{uTRndTklC}i7yZ5NSoZh1u!Y59?BM!vE;^{`?>cMd@%}|@ zjd(ROX5uQ7W99n$jo=BcR-Vwtr-5W0MiTkq#NX|hvi5>@e4-k1vJJNF_kjnSQ^=t={aS-`F#;k*U z4~TrqMb;8fhvOL_Lk=Q)eq#)G&o2e$e@FC1KHlHJw;3fmjD@ec(wtN zy+QHC_;VMK+_iCA^6fD>hv!E?CLEqW0hv56uIB~VjUK-)uICsaIfthf$jE=kd76R9 zr-CDYI)N0gkMq0(NTtIw1f=1HIL}=`Cb63u>G`tgad>_XWZdETBajh?=RoX9j5<6= z02z09P60CL@H7Jn-XHg807$FDvjs@j;gN5@$v8any*I56&kuo2o*S>%6F}tiVNpgs z2V~sgIph_{D2FEtM0TX3_$&r8>F{&{k$vol=j}i;ABfxf0FYLP=MzA34$n7%G&npz z12X9F`~gU%!!zTRXbXquB|s+6iTiUb5czCaRQEa{69|6PPgjW4jfMw9BaTiWofya? zo((|c9kK|y49I9(+}8Vn41OqX>oy=mPQTazWMo^MN4^m#g8<+!9B&0-5d9{dUoF zYnsTOzpNR9E3M6xT9O(iwa$a2O zVjx8axfaOSopGs;i=I!$k*|v$2YCv}go7M_HA3ZGajBz#$a9dWEvkWJM&mrE04aVd zj;sWdwKeVR>d5yN3q1iAIZ-t7;E^Z1Q6BaIndKl?0jWDbZv7@f9G*`Dk>|{jo-rU< z2YDFCB&rbcJPBm3!?RBYncyHt0?9Z?4UnC#IUQUtH0s?xaN<6r@@i>EReuKzArpqi%b0i$WF)SKZ(@0 z;yn8vg?4w4V}Qt>mH1okGa3!x8GkE%24k=q$l!P5n$HKa+iBCciPVE}o~wY2I6OBA z@=%=TZXlzMt*-(ZdpOSXQy{Io;>a^Vg0{Ga`yGw;`f;4+6@u8vOD*OB8F6^d01`MJ zwh7Nq<9ap%8FFl01tk0PIL}9bOti-RxmToq5$BO_M9WOXkv{+leicXdI|e>K8b^)= z(&A)7HISTxECVv?NSzO4%;D(=vco~H1~TOM{9zzD2l*6`5l8AlAfpcQ6p-x>a?l)T zc91F{4UXm|Kz2Gj%|J$ic<){ZWUIsT4j_XLaxIWe4zdkM(Xn+Gkc@+T8OWHE8$Sdx z;UG@{8F7$*00|sD2fZ5g+P5M$9=-}l22Zl05wadg*3q*P$e5FLc_8Bs(g$S1LEa6d z^3b^E>wq-u6CZy*3S^UG>vKT1fF~L=9|6+o@H`Eqa&BDnzQ@96r&qoVNTq|E0A%8I zaj8>)Ogcy&NPsQVC>j@w9*f9$SlHCnpRow|gZF|b>mVNn(qIwp1DN|b8OJ(r!`|}? zM3#rY4{$4@@N!-bDfjdSakel1;|Vx;+=Kf7Td@Ny2C!e}*b#2->E-t0K0rV8ys9Fu ziM#0XQGuDEo`yFC!Dr$uVOjP8e%;G`fY-gTBKZ9alT5PjckwaY2l#`y?j0HM?0P|k zz6X2LK^4L4Js#Ny7=@QF!j(Pk`;EPX`v8+K^^^dReSr797VR49x$;OEzmkXS1Dtvw z_x+AQH2p*N0c4Nb#OFAl0Z8~B?D5K0sT4Z;#|yY!d)_ZbwGt zG^6<2tx1DBz%#ywxv~wPkL&7(RF%o_838lXXqKpc1D6kS6f-j?kRzxtc$~}O2{Ti8 zOlGF==<}V1gPEBUfA?T!K7hzeYR{~|O>d~t<&&&C^pi96>EwH0((Nh29qu-xQD6>w zE=chjBOmk(96Cd@?r*LUJ(H}Pm?G;Wqh_yQMlA-nZ%#6*a40kCgj8FSQR91&QNdzn zR1tb4QqjSkr3-CFt!r;z-^LHPS;ikCTQbZ9-`$`%uYP`2U2S07J(PSLQmvEd4<*OsIoedCR?+6z76?c?MF(^25}RW^ZT+SGw!YY?#WtM? z+g;i;l4pr+I*Dcyx6BHkR}E#G3Qw3VDSCuc+G6Sduq|rQ7Lp(CA#L${bUo7+?{hEe znZ&sP|4p1TKz)M}=k;%9oYQJ%K1uOD+u!{h6LZoQ**&xcBU(vIaYxuGX+mSc*f>)1`(+%fk;;}eOZvLKqk;#BII@; z4eK=PY=4h(L%z@92obdhb3-&6pY0`EU~X9J6`R2A9_;U(w!ddw2Ar|K%Oh?XG1BH8 zu83?cC_g>fafJI<(Tkk@c3+!tF8EN zay6UkkK}4`C3E%oR6Q~`eca~i%RGMtkX&uuL#_&staf(WabpJ%iDq;#pMPQVxxc%F ze0JA5$S-8e*aBUL`_&E=J_w#k<$+loKL=9W<4m-vBj1MgA9!UfpBd!yKrX_{$|5KP ze}SG>JU)}VfM|_m{E^(a1w3w=J)c}1Jb>evTH{$K;l@r1UPoNHqk@`!YF7+Xsg*~q8y zAQeO+gZ~H-;yf3B6ZvE6b#4Q$L_Xsrc4)m8iF8>W*qU?hx#zZm$Jm+`(_o78glEyB zMRHb-N3KbKpZQ((_j@tqVX{vg(%-vZ$Nqj@MdEUJD*gRy_<2s;yrAyqpojQu(%i;h5#jQG*P{{F1(@9nakSlAT% z{6E(T#jwXo-6MIHo=^Xh&lHFAPMV%De-_INfaP<;@GKJBW%DQGS#fS=YMw>X%ggD( zr7(YXJjDF@JiK;eC_Ius|3*hO>y~o_@(#(3F`FA1T=xSYbHVT#%#DJlLjW1)$M(?f zY|}&0HO(EXe2vD&d}pD%Sm@(hU$Bl2XxbE`sP9T>`^DfH^hVk!6Of{bV|tn3jv}Ix zBkhPCX;Vf3{r;Ad?MN%5vEMo}0+fEl7W^!XxwC`VlNLO?iY@q2fxJUna036Q>fQUC z$rk)Rboil_7M$Ee3yNWxsdG!&bC&~gW5iZoWLvpdDhzb=p4eCD?v1_8eH2=7NLw(i z=ZdW?c!C<8%>@XS0lAg^H0bXvD`0tgeIH4bHE@Yk$Xt?9`^{dS3aS&)@8t%WbeOh_Wq5bb@*idIuc*2X6CPkS2_Tj?d4co&Bbk%sd;Onm4ou(oBV!ncIuZ99qUPd;)sXGxI8&nOM@| zCGC#H?N%GIW%La?KKt&5{#^>5L3G#haT>L51($>0fqxo;A&{{hnJ@O%fzh{N-H zAPsM#6m!-1Be^R5@7T}>{&_yRYCWu2PH{__tMVW~X6%_2C)jH&Fju$PT*Wdh@g}_R zN*;b2{SmkO(6a-h-$H?%L-Md1FuDeKMp7d!dAQ{S=HYg?K~j7)iI-J ztK$bxBv*g8nz`DUnya#w7~G3IES}0d%s>ySA3HcgZj0yPdW@2>JY>6P8YB}WJ~0Ja z^xGW@69;#M#+Y>}dPGFp>+=0=djTAQwk$EPV7YtAGR?p7O?J&r(vk|FofUaVJ0;Xh3R$RX$W&w_K4&- z1xTxdtO7FXAZvl-7ICZ-smp*&I>?8BWKW6nd=ki*gM0x^>n{tEQFH6r zE6+E<=S8J5ie?vZ6g@k2=^#CK!e*U}>b@!&MH^1!C|Z6k`s%aTyT!6U0?3U2Z9C&P zCA>AKlD(C^Zi zX#V)_2Femx9=l_25V0;Jm3#cBGpgTals~R;US5LCl&doG~uYReuCC>g%}Z z>ynJR;v{C2bS?joY^j7O%)wTAw#YcYw1t_l8JvD-rIj1@qLo`uV=Mc%*t-YA78HNx zdk+7{+Cslmcg))IOa=cbTcTOwQ`|#*nBgzC8ICW1F7)*GZH_Wr^!y9WXnaoJePRrw zdihJO|5Uv=LT=iNe9rAfJ_koKpN~Ye((`%L=JPrUhj&OmH|#||f5GPSH=rXupGWr4 zUSc>Lwf2{!WcXL(|vi+w)-n%R!os|lic}A@0?jN z2Y=nwmvGA5wD1_V`!PsXnb+Mz=B9VrcAw{WK(Nc2<4P=5%+A{!x8kZUyieJS+&K4K z=En7~<(rf7IVhq|AZhn0Vov(|q|J>{AZ|b87+$iuv9YaGDmeFpd4)2|%CA!LMk;7M zmAS!8FjC^-bEty*ZrFb;6ZF~WU?-z7A(eLyj{Mtfwn!$p2eaiGn=P}!;6_X&BwNmX zEwe@X)jU@b&LmszcmqcXY|Ez{k}bEN%xsZQJ^P1b%lKYo%hPXRwlt<@i>!Mycn8z$ zbj|e*0g;T7&(TknQ6q2WibygF&czO9)JG6Dv+mtc>M8bh_4KcGmIWta+{oaIQ_AhZ z+WZN5B!3X*L@)S{<&VA(Ic9Uit&>!bxpAw_jqEZHjmHQ(RB}V^FW?evW${-4_mGuv1Kz$y)xh&G{`#pXxgnp2Ho4*Z zD;gy?T8q#T>cNsO<&e=Px01Qx`@=TPvQ7Qyq!opR@3%sOBuOPNXJ> z9CMKB2Ds-SwQoc-DWdD=x@lS8#I;_Wmi7BQ>y@5$8ID}* zPkGiiP0RWY&-yISy8Kd>cWY0&4g!t+_QeS zXMOv$tdDrscX`%#de*ml)<>sheVb=}+_OIBS^uzSeaEz{Z}qJ2^sMjjtY7b0ADfo- z>pkmZp7l}B`WDan&S_a6@~rRhtZ(+er)6F4w%nW_^{kJ0);D?9cTLOs7SFnT zcEs_gdaGx>$Fn{$E$f$i)<-<+L!Nc{W`Ffi=l3V3Wqr`IzSXn7#j}3CXMJ*7)-U#~ z4|&!HJ?lBo`tE62-{e`};#uG1SzqQ^5AbuFaz}-`68+h(O6Y;0Ao}Zd{=H1UXMNDK zUi7TL-m^YyTGor6^-Z4jPS5&0&wAywtap3Xi=OpX&$|4AlAH6hr)6Ds0-fGn)9G1n z@vI-}SkXduzaC)Q zi}&x-vfkoZU+!72^Q=GZS#Ow@^(N1HgJ(VKS%1v4zITu)-#^<2R!R7)3UzYvp(0eKHIbY8P9s_w5%`jtYb_2tcAY`=+9qiJjod?jmPZQ&6oEfLhBXb zn{STOx~Eqi`K(AyEIwNIukNAl+)?~rtXK7N?m47=a>~@briFLw<#`rPFgGeNz$Ol_ zUViKBVRi8oHQSxiR{BGvI>%ZNsa+oJ8foNzu!qPq>mohOx|l5;u?PPbvu-XTIaSt0 zJ~QiLK5O0AKuNhC$JY5@tXFjl+pBy=)pW9z%kwOpWNz#s>ukNASJq{znHg0hE8(y$ zh*ZnM*gL)zw=Xusgre!_jS(onzaIH^x*5w!Vlt+*}0ZryiH%lbZ^^&Ot|?Vk0| zc-AMTWj*k$k9yWeJnMIO)}NS`^?ydI6kTg=_pERAtl#QcpPZKU-JbOk&-##O{R+?e z?rB+n#pEWJ(PkGkmyXoBizR9zGhG)HU zTGr)Pa~)eXgP!%GXT939K6_f$AM>nl@~n4y)-#^<%(Sdec-D)a^;XaN0iN}_)3W|k z&w8h4y~VTsPc)W0(q^Y+eV1pw)w7=StUuvdubYop7rIP^kXduZ+q64Ps_S|K1Ewl$NA-+^*Yb`sAoMlE$cfy>kXdutY`iGp7oY#S(o2DcI#f} zS)c1!zrwTLIxXvCp7pF}J>yyL@vL`F%ldtu^|_w)*`D=A&w6oM)^~W;GoJNI&-y8z z^-a^VevfB;wr72oXML_`eQ;XVM?LG6p7p@9KHIatWm?wn@T|}BtncRD4)+sk|BcU+ z!2x;JrgxD;)3UzZvmSWXCq3&=d)Bv3%lfUJb@}xTt(O`7s-N(zKjc{-nU?ht&-$ci zeZsT;WzYKdX<3&~b2~MydBU^4%d>umXMJ>9*0*}rCp_!po^|<^E;s9TOw0Q9p7mXx z^_`yecX`&wre%G|vp()wAM>pDdDeGM%lb8*^_`ye9iH{`JnQ4rvcAQ$KIT~;^{g-R ztnZqZ^~*i$J3Q;#J?ry5>l4$mKImB=^{kJ0)-#^;0bft)BHQp7qB(>%p6+bN^oStPgqC2R-ZG_N>pEmi2DW z`WDanCeQi~&wAywtap0W2R-XW&-!-H`s`_0@9?Z|@~n4y)<5W3&rHjDt7pCFS#R~M zU*%b!J1y(ydDc5U>n)!3i#_YvX<2XathajBbDs5LWL=*I7Sa97Jq@%^LaiSABs8+6 ztJ4P70_*7H;k`eW#`8R$zl;8G)Y`-Icdza>vG{1+-?@jnbJhL7Sg-0?e1=&5DQC@W zK7A|Cv#^@`*cB)w4t|PF?&wXsw{Ko2U#@r}zALBDW52fPwBzxKIoN_r0U8^}SwKuQ zGWfhz2swZLS0i>od!HD$9;QS?u3un%MlCAvct~#Z62~U+JW$DRXOg_~k1N45ieTc_ z33|}=G$wJ*_k*X!_5#u4+mg?k4PiKzh^BqAbzWbouU(ZMC_M7*!R_+x!J-cvk70WR z!7Z>AtTTF~g-`<^V-sx`KKC4X9tAR_**p zuw58^C)jU*Y`50)_%_K4;r-n3*+d2&tShSl z0pYW)8NvF(`t`jV3W51VhG>@KIPl0J`DT!MK`w~vX$g5+W9`)egukpYL)yJtzDIg4 z1fzDp2s|TB46g>V8;InGv9%ot@0$#AFA(ls800%Z2H_s21C@FVNXE&i3Vif;Omo#p z9R_4bpYOoK@W+GKcF5a4k)9L4!#ACb)Ej{e+P1(a^b0*35ND^o&JfK`eAFz4G`XygWwKRv=L(91kh}l7*?oA|P9BRKXma0R+{GwRIi}+F*^BEuJ^B8z`I5GSIka0)z1Q31$s;Sq$ zS>%tCV@CqnX(P72tsDIk{nW{XI`Hr?dd>vGdtqdqeA&?H_;w>$m+OY7U2Hiq>=h{o z83dBi^^cKyFOVVVh_ZJWh#V1eCy?tMBQ%6qNg&RKL=OAA6s{^aWs$} zP7F^3l5u*$A|Ne}<}-jmam>SZk+SW+y1P&)F5MLH3Am~0M)1sbq^?$C$9qZeGEO&Ue197wW3qYQ6GT}!+b~xGc zMqwwtfPhLC3@21F3@^ zxo&v=4rHgJdA}O8yR))73<&onjMT9}!QO~^!JcCwGG5lhEGm=C+9{|sxjz4z+DO%0A6nq}Yq?12C03zd9q~}o} z8EZ?V{w7jRJ|9*KpKVli0TN6sjn^v+o@)*uQtDdQ)7Fh1XR}T;p9G#tCmM}F12Sf~@MP9-+z^f1fHXKG(kFmSu8s5D3nT~4QEq$X2a zEB{QStaZ`+Cy{cpr2^ml%1^SJY&i%B_u>pP2gs-s)g?g2oIG3&Bm?Ueuwta%1%#gy zpAqyGOxGQB>V7SFCI%RJ@o-oW$LG%gks}&KzX7Ddsp;cDp0Iil=l)(S-xy6%YwSt)#Kq{TN={z7qj`a(HxbfKxgge_Nquv8#mz4_F z&lrCiVBPe=yeyt|&IPD--wvq}E46l``2rsE+2oA!d=or@)25FD8FYO9H;~y*d(C=1 zdWsXVBZ0J9J;+1p?m?>)u@k{FYW)#EPXaRH=s69Dd%xTQWVe%tYk;&kdIo^ZvU34K$bi0)dFO$!_y9= z(zX}W2PGhbppmW1fs8wMtTzJL<@DvdflN65d>e?&U(sm%OCVXt`kw@`vv8Qt?Lc5X znp0-uTh=;(V0vQRfy~+v_pk~`&e6OA$Zp5_dBWq=v>V9fcGiRX;4&a{9iHof6dmL? z(PMoUsry9=G^*(jf$(=LObb2*L{>5pPX)dYENk0+?Z!U*{tnh-PL3T2p52br;Xt;+ zR@6FkfXs4u-YA-#@n$-7AWm-d0_k-0T%uA@u6_W>7DwuKhi7qHPkW(zMKAZ~ zjjj8@)9U#1T_8IhJwFFhbXxE!AcOktrbf@RKxRAbelWf_Yr@XUc?>sQ7;k1dnqLQ= zQ3qKJWT&;2H$UqdWE`Hez~kPrb^@t%W}*Qg;#m}*_W_Y3LOu>;ixbt)0$J{4=EFd? zS|nfS>+9(af(FN*KZ_oltN1Ni)Eaenvjx8dTxsJR{va}V>Owsk?K>|6Pu3aL=K|rg zq!|H1h_7wMxaw%G0Z*OvP%JM8(rWee_u{t?3w=RDD8+tyHh2OjV(WoyvU=7Q2l`83 z8Fy^GTcj)x%E665+_v~UkbgRJ!PiA9JTgI-{MV_gRjeiG0~ zy%PwZGtLM$;0vJT%k%0SpRWSXCTqQ~t*cak)-4XtHt-a!^|gHkVF`9RJa>Ud<^tpM zmvA<(qp)URUB0cat!G`K#M7>xwY@C2ty$Ao*ub;yuATzRYy0GrsHy>J#iDFrDXMDm zz1R8ny!-%}{>aXpd3}Yo#s0o|dF`BQ3hVG4v*x!)yo*@!m@TdqXRK(#CUCK@7ZZ4Y ze_MNJp~Dx#FQRsBzz-YAuc8hV%|5rMIl%;G49*@`$L5}J$5LF+%bod}Hf)-EY~fvE z8rqh^D^D(bURjak^ZI4G*v?yRy!ScPacsTF7xm_G(^2Z}38oY@KNZ$iEav++7g1C5 zJ8Fv-v8DFV_ra=qOY0k?J4ymC5rPF1OuftUHSIjo*w+T02FNK zYWEs-Bee8xEajyoC9y)0@Wzb-A=1%RO6Un;?9?k;e$8h5c2=p>)!UQr>Ik~K)_@@| z*HOs#46I*+;WCEGFUO|AZGG~{CB|sn&bM`R;M?L$DOXCx0@7Y3(2wZ1r-MAWr^&Ys z^!I{M`b_@9LSIjzJKxcVZeo2Drm&eP)!9};$`{+#bai+2Z#Hr2?p>GP5XiR)qrh{vTok}>Sr`DM*# zEN)tH<{9}sIJ4O*W2@ALPSsH(n-7NwHtaBI8P4fJ9B#*pTT+xC`J-7{~M4QhLLTi1F_Js4fqw)t5! zf4=nqzpsa}w6G`MI(jP}Se^N{ZX}I-$#%~=&+7#-PbBi4VD^}*ZGMJ75K$)M=T}$L zz8SAD$`;zzd+9zOZLR4Zrc_xr+uY88kZ)_3`O|Z?1v%%V~zLGRWS3ic1`E_+cQV>0_JsMvNo3I2)s9BI* zz=~mE-rJWCzhEOaUSP7eIsf`*evv8@mJ)ln$5_jMKfd;5aE zwvFLw9%HlNPdK-*4xP^RcVS&!jR#?@NpfZ9n^8fhlXh7w#cd~+Afbbt6JwQE@tD&| zL-jVpr4O6r(b~lACB*8pj+m+ap7^V3O?{$)0xi%{*d+7thPLj3WWp}2pKseWCKFX8 z5{!2i-;r1_O5wBXaQ%TAt}kMS!t5WZOg2J&jqTW`Cr%|F_he14OsY0lVs0d^BqLi_ z<@r%-M=lA4EL7&_v$%i6YX{*1CT1t8t=^9MVHNf$8}kvN5>}giTt~#KX6=x{ zXicdiW)Usdj}cYBeo138%<@v0$rGYi;aT8LObKyeI2-aNc4ITtw+ors5 zT{YHl^1GS&@RuUwu07##ea*t;y$Bko3qf%PYN`nrA-=uw{OCU$tW zi|j*?ONGtmL;?)MW`4p{G7e98lFhKdjwmr+<-&R_J+(UW*l}$~Nq>GdN+Z22?bss|x#m}*UUgagJfp{>vfAJ#rKo_- zjyoYYMCjmlnUpF?kDZIDV9Z9UD-zP^PD~QnL_r4x32~TyxRui@p05~~Lzb@Ia1mop z`U>*?Tse`2HC7~C&cq_Djo?|Svjagm+K?^YH=_GpPdZwpql&0=TX(^DV9NOtwgz!? zi%5hDl|$W<&MT{`*frc<;XYo#Qc&95({6{QeEXV&@r4VqE_8WpM#lQ1n*j?K;(o8A zHy_Ha8R)*y8c1rdn{V@1rh&fRJq(d}g059^RVo-R|M~`su@TyYx3|C8jUBf2ZT-0O zMg@J;g`CO6tyq1w$~I)D>W%G^*!?MWi7a*-#WHB>cgdZ37I(IePce;{#LTtz16YN} zGSr-7l10pPYrsGl5~WwfrIP2mD;wH0LbCbR)o#}KJ{;#qD|N)&2u~d^LS#)}Z(B!u z8}6V(Z6T(wJVb!xQS7>mOC2GWSQrc_2a9uq&7?Pd*%xzo5G_Ahka zzHZsw=m^>|vGo`7F(lkdlpZK|i{T;?GhDIDY*iQed<8G7xouxpzpyHh{vHks{+%YS zYdaRZu)k;OX^gMcjv4xf6XQ7c!BEyrKt;@XL$?>|r3U>nBlrxHWCZR^-#r6bv#lKhQ6>~Ed-enVV?x_i;-ov6f)?-0W zn+3buSP~CWzfIVxOzsl!N_%f{vmI&j;kN^KVkPPe7*wVU-Pu~+)v+YMtb3r;xoV(* z8yU%p-V)|$lj_lFINnF6$-Rx}iYT`?q_RH&Al#maSbV>tYvFr^5(XI(W9}H7E22{D zN=oG!X@4)NzNQYDBVj1(r;|YSwYBrHKm~uY#!0qpy=|zpMoh5J#};B#X)zmu@$+q#>u@;UQaGN;E zEL(~(W(|!dMA`6E;jSh{Y)=ubT99gKk1?%U;F@vzcd{m!;o~lqZ-FXo7sNUJ{*hE& zg+VPIq;h@ElfzbQOm2#tuF6)s>^dOE2d9LEY<;rQ-gaz#ZMGhRcg&5HZd#kITWE)7 zvp0qbKR_vb5Z|+IUVY7ingx~xqc?7IFlx(enaA(l%fo<3B`8cJuVD()!wk*hJ=lJ4MDXsI9WB<(qv0_TQ;+Z%3mA^Rw!v#Ff%!?uvJI zy&67l(p3tFd=8GrF^)HQve~sEG3eCP)P;jusKvc!Nk*@FenPf3i}X)&nK3d{hoAAo zGlSSH=knInV8@xBmJLo+>w(x_jFpqCWp^LrD*P?Y zaB7)y#9dfb71)PT;q#-;{r-7{AB3|yl6_G>wvX0e0bMfC>O%h+1M64x z;N6H*2G(M8D6w%+Ut6=V+Dhm83gNbK#}fQ1nxMHnbS`cys#`g%JC+WQqnAj5S~+Hg^Yy}~dgT#_^D zx^C%dALx^(o!A+~P=Ilvx76PhjuK@Cgqk{xE{r4SsRLMe^E}tNxr9x(?j_M4DV+-+ zA-E}4TZNm#PAnmkqXuO(dEJ>OaWAmqjI$Q4T(Km7_KGu>ElIR_?Sci>LHLw49MBV2 zYih7RC+1VlBwWQPXGfJiO>PSo#upb3CnLYdjlcSudgQ6}8*HG%H@jj?IA1#-&L`qD z)mmUdY?yK8g{1DRscbkNX>d3kCRl6g7uMO{?#-GKT&W8Bi#%yZ3hGmqd0nNxwt09! zLJpzP<*@#;A6UW@nb;HkdFXci^Xh}er%Q*+=gf0@JzEk!lFqMKvdB6lwsm9)pVAi5 z&j*T2x*)u`8v`vwN|^l=U5Xb3jFJ`du8o@jH48C;C!lI95Gjm|m;3HWex*Du=GC}r zed<}V7vT-X^x6`<6VTNid1g5p!RMl^Fmrlxj*7g4+%v4YRHHM*{$nraLb?7v>eiN97+Upv3X3u`r=Vo}|fFdtsNn@+QAf8oRh>9Afh1 zV7gxPr^OU=>(B9kEA;8j2?S-N|(nx`F^7@lmHSqN`si@R5 z_O@E`VGTbbn#cQWeT8*Kq5}pyWTQFM7+@jjp3_;ggPYHXn>%@YN}{)Kvl$<=0bZP0 zjkm4fD?(i?bS&G!xTgtq{=hr)KTIENpV4nsH(PbBbI#A|`Z<};dBoW3-lTfMY- z$(i}ar7O=|Y~B%Ddd3pGC-yu9Qkc8eW4(blzVP&2UO6+_w0h}svkR@yEF^;Filjik zVAk5k^-jFC1lQqvP*^{ZFNV82QZhd!oL|>7fTyY2W=Vax5t4}D1&GZiB^f%kC)e9c z0WX_(fAWZSZMAVo7~~lOIq0Yn4C4yO<=1BjNs)Zh%GGuoxL7I-bo8DWw$h0*Y2hcE z^B9liJLn24Bxa`|WY$~nN|0ZM?a$m&ZU4mSDVxub_d^*}%qz;bthaBGzTDkGYWJK8qOd30iu!hzs-DQ|!28s_AcMw6-NT(Nf<^D^R? zZ!4UKZEkrXH88(T9-W5S6rF}+)I3aFcy@PcGgg~RmY%iZjHacH%N8wOiav2l^XgNw z`DH6s0+MDg-*qI{!?7{)6tTyXh}d#lu7`sk6vC*eTz7skFqpk4I4sdu+9Oz84BIw-!(t07(bA%|c-a-x&gpHX z3j@F_@i1d)_!tc*k&BB;*2QS#!e(!2pjRH+;&nGafsj36MlD{7YN0iYrLg~(OydS; zcXUT=9&vIxXUCO`Y)gO);dIu-V?SuYwASPd_=sx6E6<8qY=?Dy4p)f zAYFs@%ETvI%$Q5%P0!x7;sy4QkT&wN0}{B@qn~EO2jat>_tWK3l=#!TCck!|N7~et zmHVJRJU$Ia`nC&XQ9rPz6gF#~3oE&n$9Mb4_ldAoO@)@gN`GN7h84ND! z&ASVd1Txm1En$Jib>{0tBB%E}M3~g+?Z(Sg?Rb94dC%xVzUjznJXj&CBCHFXK`wlG zJmS|o@A6Sq# zmsjF3<4QBDEDEBnCwXD9#5WeDJtPEJu!#qo7MTZO$=7DM+D#c1%2b0xo~Cr5$%x?g zqsIoOQSJNwOueEFsHxk^LfZx}+s&m${Q?SYCsd-TtNlVVKS$A+su7GX{hEWw3)2Cp zhIQc}Y=pv_!R6s=NjCh+9T-#-9UO1UMLnBJ!+|InXQLT)NgYJPI{LE<@}|&Nen`Nl zKjgC;($b5=C$3B74Q#nx?uxHF=~uK87m4tLUT9)$)XBb_-U+BW4jU!2z{Z0-Y}d+t zL^yb)e-gwv5>?Nc#>AreP*!ZVAHaASpX=o-dVonE6Mp?rv^hb9&P1rq(`}4gm?nZf zOxY_IH92D)bjjCU?5XeOgK#{};eBnH-mx)*EzY+M;MPRs)S>YErOX*(ht(vzc#{qt z!e<&IoG+v?!WB$>;MGrLx?}qPSID*PHVp((e^LK|!b6KHB9S52|aXy zs6v!nw#Xtw^1A2eQ|Y1zUC;pi?tnx(FJ+c!`z;^O!&m64!4;pwVg~%Ck&(b z@auBocHylDH}&`*H%b}4og2+S_fX*;5kvtU<=}?cz)Q`l@@h5-KS*n2S2-QDHSr=U zHfn%7JW`wUX&9XsG=oMOyq4j;AUt;nD=)>gYT$#=EAR*4&o~?bRkWU%yUfrXuCc?4 zyHi}SML{}otgmG?ljCi}a$uNbjt%(of!c+t)6;DgR_9E^ z-@`3yiEVe068jxwFLvG$B464!X=SYFonLnNM5aZG*?~hc=c0Muga;t;>A_COHIM-9 zPV4VXpf%wP33_J?^>K{Bq=S)pf4u%Yg1Ev($6J_#4?j`vb|uDBYFBL`WrsOFQEfUL zCdgh*v%a~pfq?V9M11jlBdD%=UF<<3EJRake42b= 5: print("Page must be between 0 and 15.") exit() else: - page = 0 + page = 1 port = sys.argv[1] +pp16 = 0 # Search for connected ESL Blaster if required if (port == "0"): - blaster_port = tx.search_esl_blaster() - if (blaster_port == "0"): + blaster_info = tx.search_esl_blaster() + if blaster_info[0] == False: exit() + if blaster_info[2] == 1: + pp16 = 1 # ESL Blaster FW V2 is PP16 compatible # Open image file image = imread(sys.argv[2]) @@ -79,6 +83,9 @@ PLID = pr.get_plid(sys.argv[3]) color_mode = int(sys.argv[5]) if arg_count >= 6 else 0 pos_x = int(sys.argv[6]) if arg_count >= 7 else 0 pos_y = int(sys.argv[7]) if arg_count >= 8 else 0 +if arg_count >= 9: + if int(sys.argv[8]): + pp16 = 0 # First pass for black and white pixels = image_convert(image, 0) @@ -137,7 +144,7 @@ print("Data size: %i (%i frames)" % (data_size, frame_count)) frames = [] # Wake-up ping frame -frames.append(pr.make_ping_frame(PLID, 400)) +frames.append(pr.make_ping_frame(PLID, pp16, 400)) print("Generating frames...") @@ -155,7 +162,7 @@ pr.append_word(frame, 0x0000) # Keycode frame.append(0x88) # 0x80 = update, 0x08 = set base page pr.append_word(frame, 0x0000) # Enabled pages (bitmap) frame.extend([0x00, 0x00, 0x00, 0x00]) -pr.terminate_frame(frame, 1) +pr.terminate_frame(frame, pp16, 1) frames.append(frame) # Data frames @@ -171,11 +178,11 @@ for fr in range(0, frame_count): v += data[i + bi] frame.append(v) i += 8 - pr.terminate_frame(frame, 1) + pr.terminate_frame(frame, pp16, 1) frames.append(frame) # Refresh frame -frames.append(pr.make_refresh_frame(PLID)) +frames.append(pr.make_refresh_frame(PLID, pp16)) # DEBUG f = open("frames.txt", "w") @@ -184,11 +191,11 @@ for fr in frames: f.write(format(b, '02X') + " ") f.write("\n") -input("Place ESL in front of transmitter and press any key.") +input("Place ESL in front of transmitter and press enter.") # Send data to IR transmitter if (port == "0"): - tx.transmit_esl_blaster(frames, blaster_port) + tx.transmit_esl_blaster(frames, pp16, blaster_info[0]) else: tx.transmit_serial(frames, port) print("Done. Please allow a few seconds for the ESL to refresh.") diff --git a/tools_python/pr.py b/tools_python/pr.py index 6be92dd..229edc3 100644 --- a/tools_python/pr.py +++ b/tools_python/pr.py @@ -17,8 +17,10 @@ def crc16(data): return result -def terminate_frame(frame, repeats): +def terminate_frame(frame, pp16, repeats): crc = crc16(frame) + if pp16: + frame[0:0] = [0x00, 0x00, 0x00, 0x40] # Prepend special PP16 header frame.append(crc & 255) frame.append((crc // 256) & 255) frame.append(repeats & 255) # This is used by the transmitter, it's not part of the transmitted data @@ -47,7 +49,7 @@ def get_plid(barcode): PLID[3] = (id_value >> 16) & 0xFF return PLID -def make_ping_frame(PLID, repeats): +def make_ping_frame(PLID, pp16, repeats): frame = make_raw_frame(0x85, PLID, 0x17) # 0x97 ? frame.append(0x01) frame.append(0x00) @@ -55,12 +57,12 @@ def make_ping_frame(PLID, repeats): frame.append(0x00) for b in range(0, 22): frame.append(0x01) - terminate_frame(frame, repeats) + terminate_frame(frame, pp16, repeats) return frame -def make_refresh_frame(PLID): +def make_refresh_frame(PLID, pp16): frame = make_mcu_frame(PLID, 0x01) for b in range(0, 22): frame.append(0x00) - terminate_frame(frame, 1) + terminate_frame(frame, pp16, 1) return frame diff --git a/tools_python/rawcmd.py b/tools_python/rawcmd.py index 5aa9a49..95c6043 100644 --- a/tools_python/rawcmd.py +++ b/tools_python/rawcmd.py @@ -2,6 +2,8 @@ # 2018 furrtek - furrtek.org # See LICENSE +# 85 06 C9 00 00 00 00: Blink green LED DM + import pr import tx import sys @@ -12,7 +14,7 @@ def usage(): print(" port: serial port name (0 for ESL Blaster)") print(" barcode: 17-character barcode data, or 0") print(" type: DM for graphic ESL, SEG for segment") - print(" hex: frame data as hex string without CRC") + print(" hex: frame data as hex string without first byte and CRC") print(" count: number of times the frame is transmitted") exit() @@ -40,12 +42,11 @@ pr.terminate_frame(frame, int(sys.argv[5])) frames.append(frame) # DEBUG -#f = open("out.txt", "w") -#for fr in frames: -# for b in fr: -# f.write(format(b, '02X') + " ") -# f.write("\n") -#exit() +f = open("frames.txt", "w") +for fr in frames: + for b in fr: + f.write(format(b, '02X') + " ") + f.write("\n") # Send data to IR transmitter if (port == "0"):

l?WXrpr-n2W5bu&ad2(a>|Q&=%)* z;uk79PjJI>wKt^bQO=*B>4;pNqxq7fWNw;csOSP`JZxWPlL_^R(S_2hSL6ncp`wc< zck^?t8>Z;7&hy}gW2knv^QXK;NUs~i$><76+?c7&n5h%TP|@Q=1K()5O52_KsOSmC z1_$;G6k7|&2_N^bwiBiSJh=FON<+1LojGIk(tXsByws;X0)Gaz%0 zDzB-kfK#3Zcp*F^9a*l0oSqI%IUqVM6EU}GX5G9w73$P<1f~KD)G6sO;|oGoTwvE&$NU)&B$BV^R}~Z_@T@@RbF34 zu8>G1*EsWXua;Kf(_Iew%B7*F#Kbd{dt2n^5ajvya10tf-jK znRy|?#@tUgMT! z-7CDi$;;`O<`uSH9O0V8K|mr}`vs5*akCVi!!X>yaMGwFK9VPQFWEuhbVb}O#RhT4 zlCT%$V?#&-#x?8Z@;sjJQn8_gB~&EDsba%;5}w6uG$GKNt1n0O(m96<(ixn#&=poz z1!3lB#}9eD|RHlUG2Yve*#1gTg4? z-|oe=ty%>q)T@pUnxS&zF>ePb2ehzS$75`L1Eh6j$Jo*aNNdW*TT>90+MW}mYx4op z^mAg&`T%JkIWcw#1EhK6##nd*q`BqBSbJ5P4(Uq@_ui;ifaJCOd!r&>mKXO$nUevs zx-el`T-+CBrU%H{!h~gMalgQe^h(8jFiNQ~Ggp6|rXO@H?q8$cB~(Go@NP6^hIgZ4 z2Fdz+S~bb;d(l*O-;1WQ`?n~wYgKq(s{ls~()-zb+jN__c`FX$-Sb7Z$2Y@iB`y#p z)F5uH1m#6%YR(~c`(zSw$B(n~SoA{&Q+MYOs{UPUUk<*K(V=(}Og(|}UWeU0t@B9g{56y;#);i%R;lXYHUp!Xfz^l>%X3~y&bzlGD)~7J zBH&HI?5}_w)@UNk`r8>Qo{MB9X#h)o8nF3i}WxK}16m)_i*E1A2sM#^yr^W*H~g|36y?3^oaLI!_^ z3?9su=Ul~xH)aH)tbxu|Y#YZj%J%16MQI-*I^uEiUQJuM+lxl9;W<~cBD&j)N6HxJ zTun*t_T*rxCfCs9r;c>gD5)mbQjoX(fz2#|>ljIlGB#cd)o?;!Y&@FX%8f?jKIGbXh&eyXarUu(9Xa@1TICOqz-}P4E)?n@OT7XM?ej`%*cHk z)_nm|rB140e=y(=0RF26vp|Ra-N0pq0xek}g!j9nOw9Tv=nF&e3qtTQDfo~l4O}+^ zyd6qvfX%VgfI^dfQ`)qNly(o*g+*tdO~`ED%2`NT?llS2U@MIuXXnSgZFw(b_fn8V ziL%FY7OevPiHx$-)6p9lWxwYvVz>7vL`Sge(@~W7Nd1n9#jG4C@Dc0_oyDX@dF#rs zSXYJ#y7Ze^`h82##-vs?lkt2+b!AwhE5prF8J04#4>)OXQ5;9cz5TW_aO7yXvrIDe z94o^KHTX?_3h*ssP_*wN@Fxb|Kp-|2MgJlKC6D7Lc|U%J0W_A3r5;pnLhP{HQT-Pf zkqTCF_eA&O*e3ZL;5U+-z)}u`zd{VYK*+GrFeJ(FaFl+ZO2{yl03r5DNj#3ks}1oM z68|D9l52n-OMnos5n>#%_l8zC8S*{AI_rMR{G9^uJ)lXhM&S1hEJa}0VF(e!2#lqG(sL1e2r<#*S9faDDOlD0RBQ4kNeK{5BIXH)Vf_s$o5tUugJ~Mm z4LFWn|2X6W9NT`wW?WKJ!>%{DzQ7%3arY319x<~02~2zNCN)y4VP6?qHnCbwOJ5Je zy8KLQ$R^erg3mT^HnGz~@cTpXOG5B>44h5uF@f7=X6sUVGaDBDxlWkM@701tWi@1w z!7ypIc&MqnVAf4(l)Y3JwlCW#GkV}JS)r3g$S5%L23_#irVAc2-=ue5H&L4Bswf2W0#XzM0P|r1 z{4E&DgShQQG5i-twijOVvZj22e}3JAqEi;34)W_h9-T4_|NOeYj83Tmo?rK| z=#)F~&#(JLbZYuJn!m@Hmi|%}MYnYkwct=Jy#5D|%FK@Pe{ov2%@}w^R9Du&jzI?h z`_nRc^~l=wcyL{L)sI5de|&uQf8gNk8((vB;CHGV!xj}jT9b^((OP5(mSi{`j+!I0 z=ta&G0K~|$58teb_))%TIA&`)v=Lem`@J*CL)U4KhGK6xJINByJQ|9Oj)r3U z96rA1k}!2N6nj^wA{H7P4aMFUMARaJqakzwOfVMDJQ|99B8aSba5NPAT$1zwu}4F( zF9eiLt+XC0_O*a=TY|=*MEW zdNX0W9EOYVHjleeJ+ZmFbi)eee$tax)Un`g9)v~A$$=c(xc?l7d5E7I9NV~G+=acp zL;%nS67H8zfwL%{I<|2ghlIr`kfC%Pl1_++k8Rwj5SN94hCC+Z_3;kJHg2x)%UJZ zJhpLrJ2c`pgH1cOaSsyC9T_<8gDAJ3b1*D@mBBH2laV4}+7mZzLm%6?gB>i!)D!XG z*v1_$_INICk8RvTozo$4uLan*d5~{k01S?8+>s*jy`T*2+dNo|`|~RLk^c{!co~bvGVQq9zlKU!f>-&<@_OrMk@z5ZjEF~#Zxczpw0X^*N<+Ub2ijQ z?M@xsxJOD$>kX|_2RCkm0Qmw*v&sV9j;GF(qU<*BFvy*o6P`=~XpVa~E{P z&DIX{l~Z7f!7|Op!IZIXIub=(k5^SRHdR#4EuS&Fsk*XZPGwC~1%2!{C@1yKozNz> zDAzU0KGG_e+F+hjHwTYEc7&Tv?2d?F6T2fyZ(?_Z+fD4KnGa-cV#i9edZDN8=J&&I zcXrx6SZ90O#2?NpR0e0LmyeZYH45(n^0o!MX>7r$gh$o*gqwZ2MQmOc6Y8nUZ&B8Z zV7Ka0!^-*2)J_?R=MWI3yk<+;TY08w6EW!in0cAFwC_l0$D?3 zoXHKJ2xJW-l; z9wX4l0sc(JW6+E;@GBYPSk`v|#~I!oNdId?-cwh1sBq4`(>H zum{5<8BUlpuy~SHr@JH^A4~i7&c%*#d|V5HMTHGyn8?amTzDIWPG$KkJo7{ z9z>>iLn(Ori9v1kJYmWDmX)%neJPW59sxyv+2_5KS?>>_c(9ie2QV$?GNv`)YX*0a z7WSi3MN%b<7wCPIfs+?pT6E8oDxuN5yklKT_r`ILr8%86{k03~GlYI%F|zCY+BuU{ zqRp>U+Wb1D&9l^I&{{l+M<)TMe4Xc+lR<$Wuoo!h;HIXT^XAN$TU9rwsYzW12$O*J zG-K=m1PPN0)kh6J58*>hA7w4ItaV-M3d|YkY{s-9<&-+|qB!kewp3;|Ls`boVU85C z7;3y&)z}C|PeTF0POBfdqZTGPtKR|Tslc3vTQf)@&oJXsW;_z1io-`Rmr6Ucp z5IYKdAlN*+UD{;ehXB4Q1Yc|5H1stFuJ1u<_f@>Mvw(ZqrKg4@bH~(3KI{quPeSsz zM?%SfAWClr_1GX`HGj_FvY{tG&Q5OM3?B^CNzi@xXat5&L0}RBcOo#p5`khoLqC2Y z0?i0aI1T|k1m9a98;xZP8*z7;h}%YU>|KH_m*F{}dI03ZzXCpc8q%A%AJ|ujV=83; zNh+HdpaORwa42aeG0jO#FC(pSubOnGBA=;hVlE_DjpT9rBBLJED*f1Gx(ZyMAboIZ zUk84XD(z)Nvaon4Mw4zpWu9-~EUe)gZf~7TzSH0qYBhLCQ4QM(efJu~ZDI|Ym!1Cb zCxH5j+58OxJIk=iwikhkMc9sei+F+umjh42wFn$a)OZrzi&$y*d&)#0b-W{`W9g9w zP92|0!N)B(aF)1S2QxQO)#R^@f-AJG8_Gb>$ z?sT*)=GXZPTUIrqqxHiW&R;kX-AFt~FJ~X+Et~;IJ{-Vw6uYETIfU6*@iZ)tF)wi5 zX`$@x$*CNpoOd`zx!Wg9m7eXdQ~__vW}Dp@>I&a02K+uGP-d=%wBgFt-~;mgS8nr<>EaJ4z!5JzHG`O5-aK+<}0axDDuE05=^zC;P|}>m|Uai_a<@ z{~Yld=w)#Ew9pwPTHUa@^!G+QU!1WH{H$E!JI=#KyDH7QPp8g?e@O_9dvR>>xCK{Q zWJoqc!p%Ygp9gC4aR$svr-g#{QBy)J+?TaD(3TE1O0fEWY{9%`>DQ~$HiKl<%7fYz zwjMjM*BCgfmVt4ALNRvpIVI`lvoozo8^1%N5(XvZ)H+*?nj6L9F!9c>kVd6+&b2Z^ zjmF}3ru4saWMsM?@#(q))`0y0%wm`Oh>?ZTk&n~p`~t$H->sR6QYyXDP%tmAn7nMj zX~*vjTzbb(O~ho(_Kve9Cmk=La0IEEj(W*&*37CC@yBo0tRqr4NV0c3RRaLz*S+}& z4#~KCV*aupa;nb;f?r%vslEjN{Koo5t9PJE^BXIQR{s|N{Kf`F)vwXFN7RbZm^=Ls z?nSR@AH9AhJvg*CZERb;Y|X~@|6*HO-Crif@&Fd}{G50gvg>E9TC;jZk^F2}ZQhcN z6N}J>bu>jmL}*(&QvEpO{KwnUUXysn7+1hQQ#thZAP$}F>29lOZ66w#>v zR|4meM3cSc&*NI{=_gavu>=#*=vLq5AUEE!gMwcC?%Q190 zP4jBX8)jAFBFNmzSy-g|v55Oa@a5*?CvSs_Z@Mnqh)h&0S>HOBZ(@kPA^8AwcH4@T zDezu`BgzZdqi;S9-MTb2E@+%vSt}9~StYkq;>HDdw}HwUvx6FT-B^q311nY5SVrBh zNNQ8v@}pZ@k5^fx1Vsd-vJPV;)^+3THF#4));Pv|Ft@GVu)bAgjb}W&>&C`b*)+|X zz<4h4tFXWjARgzMNN5-3g_O#g)E7E+p_`VImaIaNWPeB<%^TYNTo$`TIwXbxG-m)yB+*qb>2r!$Q+tPHtZxGI zpts3vSJOE|G=F$CoimiMjMa3`Feb_y8f{G{!2T!e9cgFcK&0Y~!h$&eSE%UD#Lp2g zz!UPgE2x}FQgy;y+J&5QrVHQvfNwhaR5!5^mp$Hk?`$Bu>!qQ$o;K<(%RU`8q+CUM z=XpO4k)9{!?2$4Z%8l7o&N)oe8-Ts%{3odEIT94Lzs2OcThBf8QGG5|FIc+@Z60Fj8V?Fg_K30gD5>3IqI*#Z_lPG+?83!&F1h881E{R+ z`P&iX$JzM>SPLcJ1DNl1sIYypM~zGs-G_MIEWDudU^8Cy(*#mz29u8x-U?bo)y%9&tUfC17#wmDvO}o(LEiiKAP5`V zXk%Mo9rdX<{Nn?C-VgMtqdt)%0x9ffjbD#>63Gwd*zuGh=p!0~=!)A( zbP`Z^gQ%ztfmZ|Sg?q|`E};Iw8G9{HS4IvVC?($Q4UGC<4y1A#%A^do4t5j5EdT5JTZHG-DH z+HapR0lTdqLoRv(x?veP+N8M~)pNIoJ0-98WoN&KQr>~N(kf2eA0VAWOa zc2>1sjkc=Y!K!v8qJ5Vvm6x61<$oj|Iv1N2%iI1x-rhXE%HsMTpXWX|$-N;Y0d643 z79m7L)W{}_OF|ML5VG6^2yRJ$08vOVAp$B(-S>hk0xGrEt+wv1TC1q2sIB5ww<@^f zQnfCvYx%w3XJ(%JJXvf%zdycty|_Gc=FFKhXU?42&dl%{Z;Vl$dpL0A8z6&QHQ-(j zmbU_F@Cx*9*?TGtxP2L%734*8{l zKQFK<-rI5TW&@*cf0V#I_-Ml$n^7|UfkvVk9cv;-n21iz=+H9_MxbdNa=6idULj!` z%)nv;(_uE$QxKaJX~FMks@)hF-SG&5j5J@`-@$dahCCXn{NX95#^o*8q|sVD=r$(i z>}FhIF$C9Xj0>)S;1Uk?;2=(Na!3C^U(w)x-2ac|jP0i6(~Z(hnTV;R@v?K<@W3Sf z=7zlvsdT@{;kH@CgIx$S6zQ zt(;R)iYL>*XWmg+JBegF%qnV@SR$7=j0;Cj!*6O`S!s0*F2tyb&r_L^<3l?D>@js| zQ}anGa)N|Zk10A>C&36(ZV=jugpv9XL8*1|nzFj0cxg>(QDIqKb&1~F(;f!-k>duv zj3&~fW;O06h#WsC2PssKA}qA6Xlb2-jsKd~h6RnK%?le>A!~^aA-V}e`-Y`heURHc zB6Wk>&`2Xa;Ow^m=fle|-)k%56g^Tu=xI>Q>`}s9&LUhd23W(OQGn(2DB?v5&7@!= z=1W8_O3G7`kp&VQ(KR<*k5Q3@!qKQ6)%1OmC9g=MfDY-V+-gK*r7+v0nC^e2&5K%8 zWYwV6U?1-SgKxvi>OsxmG14R6h(53_!Q!a`PwP>!vKc$6HF{Mda@rtPTc!}GZd}%| zd`U|y#Cf`av%y`HE#jI%l`K1|i(-#f{!HCO77e-vY=t9lB1N<-L={;pwU;!#v>XS0 z%Zo~|WgAZ3^&XNXw>Lwh7pml4)L^KfhXc?zLU%iU-RZL`if5OVsN}yfRazw4Zyb7z zm6bSe zofGZD5ka!71>pS!6^&5{34o@XMPMY8*=Hs%DWMO7ifRce*GDconAy5zl>yjJz`_xU z>8R@}dhxGW)cGwfc9!_L;XE~f!6N-Vkl(YbOX9^PQ%lPs!$Aa; zRkECe_2*oE58-#bq=;+Sx%|fBuh1UOz-$}JW5`=|EnsL$S;Z7p$S=?-!Oa9y^mj$P za9W8fN<@?t*HuiJ0sE(lEk*)VLJ&z=oT&s9O;yw6|FUY>@9F%6URT380x3;)r7@;N zKy$J$gW);IrXmhaW+8sS4`});+GH+gfM1aa-#g;km7Kj?!*xo#8&WHSZ{N z`mD9!Cs~$z)64m-l4ZG92iS9w;Uw#ulu`5$@!^}4Q7on_*|@7@lst~|g_Es&QpQw< zlac-`BuJGJqIb-sGW`PQY^(6Ziv^zD zgX0F?n4W%#^A2(w(Zl9|=lE3mFNIcqkHm{j=^LCEfH$^>-ds-K===e}2|Z+`FMYGa zexg7}>ZP&tYXvr4^=e&NC&MMNL>V*g2lu_>bKy-#cSC;B2*Ix4Yc6{85*1Rez6vmL zx+bG)7m{VMgnX!}FMlAQ9TYIO%^=kLjOt04_=|jNL=ye>$G&UEY;qRq_Yu~HGv*K@ zvtO9-xg?R@FP-1D1za*nZe6J|=25sKK$@0493iu56P%gnlC&(5E2r#PM5*MK)~3Zx ze09fOZdlHoMkMPMeR)f(f;~#U%03jCI88AGTzb{@A0c5fx!>Qx*LJ{&q6X~14?_bn zH&#(Kh}eU>TWjVp%T2;8VMt=FS%ThLvy1`5ksiRw;rIS^aDc}FckDA_t-k>)e|n+z z4zgkg-&cSK{yAH@4LcN~btL{VOxK2CEB-DbPdFBY!s-Cd zQR-Sw!D4yC^5wiX|HXQPGFK8aqmMyg1Z&87ku}r|;s;)8ur9|O<|Um0T$18yU0QFoI~fkl#1lO`SVVMQ_xt0ZsY69vKxt7ye^tOWC_+JuOA*PHm8JrVy7 zQ*Da)ZHl-Rr4kXZGI$#(;&)F+HX`CH5icTsfI>TrCS%f*I>+tA{A3`gO}Gl+i42dw z9$$C|bw4ejN#7e>2toe#g05hX?HJP`CF*>)NgEK;Xc3d8FJju65R<6D+a{f-0zb~+ z;sO=s16!KZ6HuDmt4)~~Al@(3+!2PvN*zH#=N@KYJdsXew@p{MZ3cFog~8qHbOWQI zQAbEeCx?=pB!{Vb63oCkOzJ1m6R zW9>tD3Og-?*=x~*3x%H|$fq>GA8IADEs|{AjqBHGVHArnK0tgidz=&S5APov)tkK6 zuqW~v{d56Y#Gp_Y3yW*HB?iW`pDZe1qiPL|#pf-)gs%boX#=M&-m2lc*=l{XnTkF} z`fKG^lixI{DB0ZdXEY1XB(f{H$H2l^h)phe$REo6*n|e4SZwU4;}^%OanKsMgf>ne zj`O_W0jGIkxAjrpgM0l&=MiW!+Oh;#++bPMW}1={Go7vmu@0w-&$jMSm2;-!oDJYK z>EO?lI#JrmNxDJS%qAz_VTBJJ^m%i=NeD$VQFxZ@x|O6;h1t7~3H= z8bO0e9}wfuTb{`$|FuB!l4d{ocvGfK=+WdXLyl^I;TPKuo}lKKMUV2FTSc+g8#Jyo z^UvA3D2tW>^1W3g)_0*c3b#pU3qrbG{LX6^xnCL@`ABJWI#)ecAoPlTurdRyO~59< zY+%Bsc_Gxtii+6{5OaBed&#QQxgVX`no7S#34`X`2Z|E)koA*P(th`KwCDIfKz z5f?|YS!mR#jYzwrpNr<$X@VNH&xbO>qNoJQST*_X7j+KOCL3SU0aj4%ttPNcCycI~ zkQ|vXc&!?$Mm=SsXbP^>(SE~kSyZE5Fo>4}@pg^qt{jo9M!oBc*l8p3lU45Ymo*C^ z6jtjO%EB~u6yA5`Hs|tibf5ee$;r(hIl@tW`>0W`nv`VfAf38PrgDEYh*LF^uV9mp zHu9!4^qkCe^GjRW&{3}x6G&I2q&~yom(vlUP5>#ymL;K(7I6< z`Eq$&Ga+-E$#0~p~7zs*I_dYw)X!Y@w`@H2Ag6dqBPi-vK?x0t7!9MH?_25%YY@ie33@wqf z3^!^G8)nKy-lQ*2RfAY!U90rPRnDCvnGJ^UD$h8s#mHSGbElN^Nt9Dd=FSlJIgV^i zNajwF%yoch$=od|vf9|ZvAHc7oQ#k(W73VfHyZ|L$YXXdhtglu#h(12VT5&=`>6?h z44ygMfrnG>!3Hw|I-O-%W@4!qqb@W7N^7P@_csa4gGlUbE3t!L_oYGxI)#>TAVosP zvU*X*1*itR{f(^xz1T4O1}W+ncWAB6;eJFG*GB#fcwdf%``(iTl`30aB=13#wv?>G zB~GtPs=X#vIC2ZZvr5gGFu=7>X)2y-&>&Q_7J-X&6wv z`S>r*$N-+7IMRnGGefMHD5vsZjcFR%tR`HCi!O>s&bXQ2RDS@5qwaf#xmldV)M0^c zJ~j@V8Wu3>?lF<&iA~$ghn@1^rfud!PDOSM>r(iaew#W7M|r|()p#sm{lE1{H=gLY zDPjKq!5cmEb*-&SeuL`6-xEh+e$rw4HazS##QYE2x8Z|BXmp*nZ(VH1=nGWBM-d_5 zx=zyWO76OHgLFQ}0{`=NZ_txnNOK55LKiFrp>X6eP!C7wIPrhp6b?uBFj>c~;iTsP zO^)boRh5)|4}xx`Y_h7P{vqg1IPxK3vx}w|##Pcl;sZg41`QL02!35O0NK|~T1Wo$ z9&gf_@?EJT&Z!dY1BpFl9#&bCE);6Uxt_A}oa@O)C~TbT-AawV;Zh+mmjucTY$IWA zrE$u?>K?)1du_llz)b|Y+~-h9*KHzUC)u1y(A(qw?d@`SM7|2{HI5pm&oH!Dz|14zksFppL#b9Gb>j&V}f^++0y zoQmHhex{UF7Req?$_Qr#!<8C+nsbdH^4u^C5q^{SiD+*4;IW8bGh{ZvQ!a6Y3A?wH zvel_(G|MC#<|*&WElfwCr$NA3SVAnlxcp#GUrE@Bh^!N|>NNZOq-%Bn%=k^ETADuS<1$%)cDL+Xj$So;! zkC$6=$j4EN1cak#=v5CV)sNG|;G}js2$2#F^@I)Wu>lFmQkrC=SxOImDlBz41Cf#; z*`(J^n~g23%t)V;Kp+E085#~#kr-82heoSN7PUJpabr}ZFGI-^8jGC)CX1*{D&A@M z?8Vi;6y*xlNOmqjP-Y#Pb_GIkWsu)r;Wvq&Zjo%FMUIgGbVdh{e^k(J#BaCfG|;>e z-8)5J@K7gPU@8BOQmmQ$NlP{ig;XY0Y@iL3jfnvCsjH|q8+Y8hDpZ%J{B7U`z>5Bp zwfV|GT|--_Gp|Y@99_zo*CY^$&dNgIbqSyee6$tpNr1`A+1d_Mz{3hUcD<8e`v(0BE{d z1V;KZ`^*gEo{>7}K>)J@?is0rnJsG9mqqH}n*a+(7}E#Eo>e_f<@dPMVH-$~y5MNeg5!;rHZFPT;ie}S~2bTLkxiRzi!j#zu7sb?CyKnaSA zSkImehgIfdfSv=y{bU~m7n+a*&&edckd{)+o{_?)nx&%A=`)q{S<=ftfj zE0G>GqnO<-L|X(1`_PQ3`;Zow%3(;JL^6Xt_Y{)ur9ziuCNl`W1;#yvpV~czUvy8A z|KXm(|LLA0|HD0n|Io(nK@s;9etGUG40!G-40!G-4A4DA zFzBA5Kj5CCKj5AsC~!~F0Jx_JfbJ<8LiZGYY4;R<*&#%K2E;vuA3paK2CaJvzXR?m z1Q_=e{i)qk_-)-&_-!3hhBM#|#PS$QxTi3r-Bb8w{6(hdZ{wblh)DRN6kCi0sDz+^ zdkO(`Pm%w%dkQ~0yQd6cN}qcQ!=8Hz1J*r75RH2ZzkTj03?|%Dd?C+0g)qN+O3L)& zk~!ih(tCrWyWr|dRJ_2bQH3g}_oWUmV2FN)aa-@p^q4Fr4^&NS$APlmmpd|qh!r=U zQrZk}jow!XPAqy9I^f<{IO{BcCH1YW^A)zOzh(#ctiR)++sM?9*e!V`uV%21Am?K>3yv;4%v8&c8T$}a7?^z zIL5VBrMS-u60IwQ>)5T%IP8dO)_-eQhX7>^fP<&KZ*w?Wf{SaH#Sakc{X6Hw?)mG8 zdI7SOZyzN7G_C;ay+!pv9zUl4FR)Ndh*7Gy-XWw->Qq{$~1>T zxkEFSC(|#6#kV&$f>thZI5jqs^MQfJF)DExo$;$7a@Mz{*ryz1u9PaKDVkGSRH7Uo zsHmcRYAN2F@PW{L_zZ>X19>_Fo0%YIAF+c0O#r7cu{h-cin0pZIKH(SFo=OWp(O7yB$p>o?`Ei!!GHJC`=0ef34mNF6GnCJsl(ZlVJ( z_H|8xkM1QZF-To1FFw1nCQ+q91SYlyJM75?rwE%DHnj56%#+)3{8NQRDs@f<7NRT{ z@sg_9=$-4PmC)oD*37Q%99L8ZSIIi~OV-Se`;^ZntwvHC>FJz563^hkI#(yO%tkWP z;*x5(z*f@#Fu5aBr0k1N=@`%STK{L`o;GSlq$3JR1W}?LQAj1xK2keIlR_f8N2lm{ z<+!JBDju0CQE8nbk+!;|Oy%1MAy!?16vZWFa6UcEt1VMWevRAc+}uS?$rF)upe`pRIZ0*Jj}IO|6NrIIV%->Iy90!oVoFBr}Wg;<#Mn0LW& zR+2z6V!;cBvmye{jLk1^Uxw2Pi<%ap%&(v6ZtLR&fsBxS|@z zYE;&!5Je8*meTE>CtI=(6;wzs-iWpHwk0ZSj6hOi^Q-YN%Mvex@dA#-aPYUaL1j$} zJ%x@jGg`>}j>MI&98_8FVldX&%0Z7`HAZBWg!(}dbg`xhIa91M2{_U3(9E(bBoK<` zLaVdl5^$rl_d{Tg1j5mY49t^2QuIPHaJ&SPqkKIet3d)O(cug%lt3i990JW+A`E2O zGAxxcWa~1tNEvc47#YL`1S)Z-;;785_RxHm;U$bEvsTHsiqTuRVd)C&R;-{qVb*Cv ziayFqNQ!l7N#SrO^dTsgGeZZU3|cH_3%f=v7f8T~o=HhuEOi%(-prggNK81ofJMAa z0!h)Ol-`vRNY;9AwFFY4<&@EN5`gmC%28RrmYh9#+~k+Xt)4s%M(U)YC`mXnfuEeh z;>tnq!5{ssY3Q5#!C8jAA6wQhbjZ6Oo3OCHY@^QHkNw;*jN~$~69SRorm4`66#!&< z0PR8>`iTn$IkCX~*hCzW02$1XL(~beCFV}O1@l2P$suxqA862%1-&xX)&1B^Q`;%V zBTWH)GC4(bhsazi`VO8+Ev|9&JxP! zX`4GsaFT~er!_xV*i9Ay&dr(%Q2Fr za`3nm22Hpho4A=c>^%m$nDwyxIP`58zw2>7_Veg(VzLK{`>|Oh6-(TYO_@bvyrT>E zV-Eq_FwTMdv1!?}qy5pEa4$9k{iA1tIxfT>4(uE&9aJ@JBv`8vq!H5cb(8i?JTAm0 zfdgaSh1d(Rzd0(V3sEbD$d7fr5SuIN1vZ<+97N$lZ1(QOG5>|wEKY6AcOmv>EaDue zhThIT_i6V{{5Oo>`Ju%QGdFT+GICk4v;li>yqLmRX%y&0ha5x*l~X&=pq?BOsMYoakZ!<6-? zgi@ooGT9TtUz+CcIpHr;7vqI6n{iAR;}r>H$LQ-ZA7fpW^@fx{>Ee)kgrJm*lP9`;O6x#%CmP z1Ym2m<1xC<@DA#pNZ=i#>zqa(qw5T}$LMSo>Yh3=JjoiH@^3H~j{Jn*;T)3WQH*)- zh44f1c$IHb`o=I>1u0{Y0QHaG;iX<$Nrr=5kfi^zw$QB8fub*K3zhR*>C4)5fFon} z<-W_>c+pzlp&X-l7p?WpBMuV!9y0BFfQ$iD;M(%O2c7}MOcrK0K4g#CQR%uA*n=+O zKqUjNM*WJ3qx1;0P4z2b(Zd<`Xkfpo4D)Cp$%G?EVz3*IaFlU?sA6c9vj~(1&90tO zT31w7Q8cq|Rz-P5O+|TWQ4owXcQ^oyg$PIWkuwWk%cu-p;Pe{~ji>U3E|h)~{j&^k zE|Ojs;}ke`;g%Nk&>DWRz_X=Qgf4MP(6f$+S&DR=4gFH+U{tXJ{&hIH2+#)SGqkd? zrqP8q%AjO|83}BbkwAftG^59B1vXs`4lrEjGkBq2Im7a7L9LCdOIT({OU8?-sK&z# z<;B=^5+rTBMR*>HG2L7x4R=UwmOG0}t9c$A=cjQKLI;%U*;8hf*3>X{W{0TKa=a#h z2hMA-_|hRutX$&uMvyD$5M#Po!*sD)uST4PDU}$AexqJO(R1MmR9rC^k4==QwO#=4 zk(*P>>jqhb+2x7OQ+d$ZN>$|rM(5{`QE@Lg2X`U-g*)N;|5Nc9gXPhOysl4z?p%qcNuIH-{LRS-UZJ?l+etvNOzCQ}iMI zYR?BGCj$pT`^}>?c@UI)$l(at?6a_`Z2?{Bq4zQu%nW6PUPDBTcM^yChMoaO3TA$J z!vekq66zjaOF-?Afa9i*;*^5r(qznZ26A^tAgUe{mQGOzxKj|dBzgi( z*(3=pkB&jzhh|D(RdgjMRL8mvK*K9g=+r|^?r8{|7oAVE(_KnrLrg9g#?X<*3pKFL zy$(2=Vsfg-gP!R=1n9QdNpje;Zec4#(pslQqe7QTjyFRYRy5!;p8%2yT`#eBm`PN} z*t;e6KBPrvEvu=0Sk=UP>+W;NaeJ(-ef}~WL9iBAg`RO=M#Ro28&2p&3G70(;=)!B zsct#=Q=#4N2f%zaX721ZXVODXIQ3x8oekJhhU~@iW2sPu285Z(UaAWoQbEnoVN!*L zhesmm7e?zPn>yZ^qe6#N*tV(kd7LPt zak8Zdu)qTI_=T9M_%9s!C0bfIGRk5#5Q{$mawdxFH4qq1Ww+pE_!f#(@jSNHJdVin zE@kf=j;yuO)NNn%Gl;b~*H|1XxW?hAQq%DxK4K9gkfsk&f+j;|9*%r$F{$vvs?970 zfbdIw*D+!M!;wR53{^Z4BLgdtoNlA3^g5cuUBoQ5F;sOOL$jm#H^hHoaj5tjN5o{J ze*@@nYN(V7G@pGD*3u467svIg^e zeH-A*vo3==yT9P~s;s+FHunsEug_?h&xh5(0n7(3*FBTa^9!C%e05XWj__OEFBw(uNZti3o4!S>@=OldVDN26J5Z$;qQ(Ax@!* z*h#rza>(zeq_VPj(W(2it|M3l-@>H(jIJTf<=Y@$;k^m#(e7VJFale#ynTg@kbcnp zD{00uaLA`q)U%B0o3RMDS+ut{29rI`{nOGM0xZHPA$FLk&r$$K@a2C0!y;*KtYmhhe z+;_=*4jNk$5R>v@*>Nxc>2s`oHvQ?u{UK3+ysKK<@PhH z7w%+yTz*AQLlk@p4k`Kr`R>Kpy2mk|eS}7ujWf9^DDA zy>kaU4}%ttp=ADqGVt4!L)JTG{CK@1(t8j}yRZF+HgB^~zrmKTY zcfPcx<)rrIm}j|%Ih&ccOp@Hu4n1Vm{&?ih!zuwmz5883`=WWazm6ApD- ztu;lxOm_ZCGAoee2uB7cdLv7@N17T*sjFLvTQTKyz|_{3W!2J*QK@dB^ADsAN4~=E z$Y;<_Q^up``3(8y-HpkdGAT>j=C-UHKNfxga!Ujf7CU*s#K;!EBiUvOn2@vGykdlG z!s^Bq?aPasrZuiG{lqD4h0J%F(g zGZ0=gNJ`V4+lA7-q(nxZB_)!S^m%>LJ8|PDVmEn6s?_;jNU6gOsbTogq)0`xN2c-~ z?o1R#w2T>=#h7h1EtTTVbZS5<9682PKEtC-Qh9YS3Yy&;Nxlo7(fxAzWwTh+QifGA zGCj+=T}a<+N$;?vJJdl1hKEQVZ(KaH5koBHmOCFw%Fmgy9|YcS0`eBgNpYp5iJ!x% zp26Di$_%1lr*$!GUO#qS2!X|0M;zp6t9A}v%Xk!9u??xs# zknK;J0R8pz_+!&o;#m_vfw|7_g}^IqxLJpXiVcy zYitH+DG@Nf!NAdwXu$AkVFlJpa4l)8c#fHv@|G1P%`NSVmsGZ_gxOE(2%ZAZ#g$D9 z(eo#psOjzV%h6C97uK|Z<;LYpSF02gRoYzExVT}#YM@|TJd|a0f90G;sTk`#s}9Oh zhoczafoge+b3O`>B?SDAYy#rV_{b~9N8Ta)p>B6bT(qQVDXuJ0?yZtGNV&RczMLCI z^l!U}*3zgeEf&SR%}G9jnWy1bG9QT#o$oK%CK3&+4+n0Z)0}_o7IpvPJc?xEyyO1W zk@=6fySdLwK>IYg&q+Z0G`YJZpnaO$=Ov(hn%oy8pnaO$7bT#5n%tKppnaO$mnDGB zy2@@DbN}YNC#7SdhL!XMi|(sV{gIZ{*Mx-jGjd;-fc7(T-;g^zw4agtcZtz{M(&#u z(0)elTN2QIMlSsPFoM&5M(!R7KmnMm`?m8jIMAF1{6GC-1lFZs4QnvKjYQlJoPUth z1G7QkLm{W4eAUCW72WIB2V z)$)Dq;vU^Q5P?sfP0U;k`!EZ0O7~r7BJkinaj(f(=jw@q^~dGRk-oty&Hdha*(<{j{xXC@ zC5V83zNkdPSJzAHhC|;FBSL0}JrTo?TNHZiXe*IoeUy}^CeRNhrozfC32~4ejumO! z0SlGzXf)L@HN^Vw8>?Q9hjuaakzhYVtF(;&C0Igf0TPkJlAH&QX2l^`( zu`jH|34cuSW(Z3IV#X$7RkRwf!?Yu2W{5^}h#JarxU)h(piGglTNN5wpwywW+vXp3 zSUx&EeIV8uA|PzHD7V^x1`B8mK{W<6NageCQ+Kuw4}#^vNm?{~JCUwdVYebQ6FH={ zW0j{;@OnH43E~B@0G>Nn7y(DehTb4YTBxOMC>$+z^Wwr4)$RBec~!LXs2m5~#~D_@ zuuYLbE5gPHhVKdN;|=y;!}tk0JlJEL-4}hX%gyE8+>U694SFlG?gCqs@ccVRv3= zXrU?AF}hd{U|SdKf2HEqOIiDf%>HX44C?2HUO=Y0JuZ-3Rm?Wqg}N*;6rWSg#)YU; zjJz;6YFUcXxS8WxX5H7b&tzGP&!%7 z3qniV@Kiu+3%X2PkQBh5(!TU0^uvAu^_GLaNUU!qW5-}l<4IHd)2{QWwY(I)BmR9n3l2_eW=n8#> z46(q*{3Gr)q3K1mSu}swN@^A5n;0&fMA4F+80cbS$lWG+g|HdMtK8jRNiZy481D6& z51jMYnPPEjc4b{Qt6c@Yx zn?u{deK_(2eq~7cIzI9i@<%%06qCr*VNGj8a~o#0OnO`B2TAG_o1_QgLnoy~^0Gqs zk)Ho+u$OlkwkJ^t&BN5C?QKge5BCTUUKHb-INKUugoOUuNPto%@^z;NKWUP9A9(q?&eq>XoObetG ziO~jm$>X@0$)^4$v_H_pkpu86C9DXh{<&6yI)}tfOZ_R(N>H?)(OJi3tF}S`Zm{~3 z+?F_B&t8n{f`g|Pd9}diVt7)3!wmwxxCNI7OA&O*;qEE zw7QO2Vf(pk|AXsh(h5&4$9{yK&WVgV+4iAWR}79o)^?2DuA@y8_v;}WI-)4c@64rUbdy+mA4yztOTLGAr*)whLI}O7m0Mi$R55(pS*F(D?u^QLRC*6xEhjL;1fo=FOI_KY>08>GC>s! zAI**MElNPTZmT$f-T|dkv&Y%=1PaTqN7EgRH%_i6&?t#+&|*F`ui@jAdm=Gw#8_v6PqJpddVvUkvrCW|As@6Tm{S7R2gcCE4k?r_O zxyQO3iDhD3ZbnL&)3_XAWyi$6xyQT32<603ysp}wdxFaW(+I|Qr}=K3%W+XYaeM~L zt#>)bnLuzS9dH|5j$;ZK=~I1ozRO|AbO9$i3FR(uIku?85ZekuxeHwm6KZ49+B!FH zx6$P=pkBv&<`=DyV=~NH7P-Gb{1P2cCX~C_Wq-ar<~0L%iOYU^6(DVzQ{^_f?0nb9 ze#U0FC%PvB=RD&0i+7THCBPd5>@VI@mwo4^SfZJ^%Ut$?+jPddbjodZj|A{$jMA|I zjiEiZo(tpE@WYq;4)ESEhwzb9ccr_9Y9nV1-Bog@ii+tom)wzG?do+7DD=X1SYv=r z6;LveL`_Xoc25&9CNjvcxUR4U=jW%)t|_U8$A&u%SqLK?BmRPja73bKSM%`}cbz6v z;I4Q7PzAaFC?2xn^^0@UMN!5?K%gsUm-D^}o@tA^!> zK2M?#@kh(ri;g{CV)Om6ys8U}Vpz*T>I)=(w29Yc@>9Q1;>QN!edI5a=<$K*0R4*v zVS+(0GVy0{i6Bf0BKUInrNkc*j1Oe7K`@R|nbf5xP^+>HnklMM$x9KSBpcm5R!I_| zPk@UX0ueE|PSjXCQ0NtUJvzJ0ogBwtY&wnwV_*h-umLS849g_SluLz7rhY>1Rqj8L zQ6$s7-3?V+okK@~M@h8WX)VNj-aBgos zt(e->xD*}VHM)?oU~|QKiNKQuZY;}nLO+rKRf@scCg4fl1Q0heH z5%(@3bDt&iB*`#oAT7!}tD(6aC-3Rs)T)(?Y&`0IDe1qp>3hw!Y;dM4Bgl@FOn03i z@|Y0u^NRd%Qy_+lx&u$3?&yG8$*N#qMP?p%*CF?C6+((4Mlcd1m=^LaVQswNuBL!o)nfH?&7!w`w#qaDY-l}tAxJgn^b%p91 zP7vqmPB~h8cgU9A@EA#VmAXxE8k;3C-^wz?b9ub`v z9a0)?{N%Npk^9L)z+C=}S%_1^?kDv80@Imea0M~!dDR?Celp}o^mFB z{J&VV?L8=5U9?AfuxOL;(!`@eK{6Z&Dx|72WJogXqmoE}tT#2}Q4#BIsGL_d3v0-N zi0xIOJx=m`P4XPaH>{o4de9Y+dA=b@CY@-%)ZyRm2ZZvd6y_69nz&%;Nm2j}n+RVo zMAO%6JU1qs$|ya_CMDi4uZr^O%}M6*@_3Xt+)je7R?7viQoJ8Pm-*=8F(k#yQc2A5 z@Fk?XRM*Yn$64K2>Z_aPMBNa933Od}8nS?^biO&XvpYqKw1M=bes-s@e#Tvlv?h{V zzAb3FYTilFT35FOT@4i-4G80QzoVlwu&0py5M(E^eE~q9#&O)3#y2No<96t8;!J`j z4DLz4QZzw2=ZzKOD;Kmag$KRUM^hVgJg7+n@6)px-2iJUOQH-unL&?+VMBnK$93|x zOfJkk?qlY0A2W~lw9Gu&li18)XHW8@ontQnOsZs`I=qGgN=cVuMozGlQ_`iFSpy`J z7Jg#l{v(4vQJk5bh@>6&CANg^w@4?Fo{&x?oeYU`Fc0Rbb$#*y6kbh|b2qc*O%Vvt z>3-Z(RMeUz!pBvxRn1PipEzi6{N@poarDeJ-;<2;N>fIv(M zr{OFCzQ?i#dC`9xrVqGIAJ2DV2ZDCuw9q}s$XQ*dCEdiE5&>lQIdLh@DS@lgLc$*g zG<4UYQVP-1!~{V#-|=Jb5Pgwu6u zERQ|4v|)|C4!(6z&jWgi7JLj8Em{rG?dgDCY)`u79N0^Y8rsuHNy1DH>P4e7K8e+K za4*u(?%Lnm3|)2jx$Fc^)4Fzjy_Nt030*raU35((rS(d5=`_(LF;1taGo@~Hr;A#R z;~7Zj^mHDA95InML5V;gi*dC9O5g& zp}GjI*flaGFp!{cuw(I*lP{E{gk+cn&}GrK36>PEv)L>1oX2$03g_FRJ?1OgV^Xwn z+`cx5IfY2qhc}Mcyq0k0mp>J)2e?1QLIe!10jTc@b$Q$zw*vdXd)ame}kU1a?@Q z2Xx0YWC4^@I;ID7$HcQ2h@>6Ujp{+&9UcBhMx5@9T8RJnqpjlUa(|AtifhDLYOA=$ z5v#bESFk#39QrwH$*&RK$Gu2>T_fYj@fV8ekjqlXe?z;wPBPH8a=o}UiJDA7uH@pV zONq48IeOBPli=8Ex<_wxf>%==y0RWUNuM0buWMVqY(Dpmmtv*OoZWy#rOkfiO6Xp z-X&!uZLJjP5+E>vrp1uZ>YfL^<)2Wax%dHMKYX zQ`0Oft$MT3KgMxn%v5h^4e@CG3bZt9PJ~7}bp@VRl!1>0eDeJmowaBRj z$CwCuEa;=POB$ArKKOFYla1Ht&e!eLeH$ff%IVQqN~z-l;n8ZQbOZjJzZJ z(0h2g#nv7Q7`9u45SMKliF=zGj)a!c9kJ4ffaO@N0*%;dVKmcsOx4s zM5ycWq>fa@%zL{b-@_Bh*MOGXi62z$pZQ;vnue}+8AbrsHuz6VI-kpEe3zkv1|@&a z*4o9`BatDF#&F`(MgKmJvXY&u=~Bfeu2z+zK(LIfV9RBj+OIh`%RFF@$>Llui;s{+ zp=6;k&Vlf>CfzL4n+F+|Y;=6&6bM)58@KxAIKP#7$c(~laCKV`cHlL@lZq6Ex;T01 zB*|EI`5OhoOPa^gtR=S48Uuxvsbf-4P90I`W7&}>_2j`tr&dkl*u9GaZ_nURX1yVg z5t;lsTX%xIF0jT}2}ZS4w`XXn>f-9yJG|mPnvs~&J(eN!hEkoiUq>I8!$EsYu5-Oy z3z}@M8skUM)na};letb`X~p_vCi9sgdq8`>YGeM+eNhi%+2#45QSwzVS@ zJ#5ne-ER!)B}Z6`$wI;33xuVFid_e2$#M9BsxIMwRetjNX}+PF{7yt`@*1FunYgkO z$xi?+`4efyMeWT9v(tp_L?K&m(vR?DwdzDGD~+)S<=3)0QAVKsS6P+R@o|K;aa$^* z(kbT|lG*}SX|q-fbxaI*S!Z51=D$MHIa#>c(21+zCt0pE#)afUTI0#W)ees<9sd)< zysXkt9KYIf*`~R?uS+hAoO!Up&;TE^U1;|z;c|N?F7NTU)EF(uRdcyYxV)KRY0f(S zZI7!{HCKDP zbrHhj`?76++3WgxJ0|){vvts$1wz zO_TSj$K;^i6x;CAEt7+LC&V_SH!akZ-v*gXv;^Dr>1p4MGD5w>AXj=-IIbDIiH_eW zBc27!OBSAPmJ!cPnXccGLId+E;>x&|#zav!QZq%!%zDjGO#wJKFe?AXM9n+`FU0ck zdGMD=iIxy`>&=^Yn6PkGEylk4w)>LUeD#*rm6cvOl3T2dHAd|k$W+SplGywQ7?xI{ z;|Jo}d);<*crC)Ztbfa3S@$3;WhLRLyQ@lhsKz&&X(gQDaU4pr5rl`JA`#-eT%R6x>b5F;hzMf?j4r@y#fC57$R$B ztkjCdkwQFg3Q>dys6#8jo~&AO*k*cr?O_%e<7CJHBy+c}o4p}jC}->Ut+sA7M(uiA zrVJT?oc#-1CLRAg!n#bod;^f)z5z%d8Gxjo;iw86y@d~}a$-F=5_LEJc3mZJxO1|4 za7yBCylveKSugD?>!owfL^Wd}qo1&PDncTp)HVvKvQk%a)oZ2*pDq`L4zJv)k|8I^ z0fKVIKtK=~1QTAlT_vlk+&#L){ZH-+9V$N$dQUm7Q>v=kAW!WQ88zWYKF1)pb%{JK zh-qt1Z=pb^++nVRU1d*u^{t~k4;|CdB>U zl6cR+DWWr0>Ef685})~B65rf0@twZJ+y6`AB^?r%zvWB(bLAb;A)%goQlDh*IY1>* z`>TD!5`EzjuSB%{nR1?!?o7R->*R3}0(5xmScqSbWHrVoP*~k_JSW{*?pd}w+a=xE zIS6Yj_Ph)UzeHHKq!)T6#D^O zitbUL=pOTlZbw3N>yTO0-QXA9hlZnF6x|cO3V|V_n+>`?(J@*?w+e6(-R<~*=<44s zz<;<2BhYi&EV>dMnGn$p#=}?m_6;xnllc*xdDcqrmT_e< z!!qgL-HWF7MufG%-WGu!a=sPVJ3fKE>l4^}34!fIW>I&!UtqsC9I3(J=7V0Xzz~70 z0bQTK7%c+Z2Dk|96@0)-je4&@%0hwt8i^Cb4V#S!t={U}loL$?SUjvt)XKVqtU{4F z5oAmyQ7Y5go7?PJDa`IW-7w^QDwF%=hF)U*XFbLzy7_91F&9`J{4~me-%^HU;P+{i z1Ha!OEKQLK(H|M{lwayAT1R7KaHMS8Y}t$g`1#gDdTVm9-TIL*y{!||!&h0RHO5;W z(;o@b{Vp_25;5xLTP7dvo=J-%On#AIlBO{r+z#`O5A>o*Cl+^lENYBOu%z4e2g2g{ zmc>_v#Z1fMm))~yafHPQg9A2+R74;8t0ZO}VA)(?heaQ{>-r4SyTZJBUu$JTDb8MP z<*P9s^_YKGnE$~te+3Zn`f|DErF^KNqzyu#2evrE{Q4mCq$11@Q%TIaE9Qfp(H>zu zzZ2s}ooX4^7-O*yrKP?{7+;34Xm2?X@jA6-Jl;Ly7DpK06=a-Lgz+INiCK5Wc!$2= zP2s%06X)N0oNJ65JD2nL^$Y3YHcK37O=OynPlSjg`?DM$S7<)YKpBL`?|I%`=JEy8H~Kj>XMM|YkO7_H0$#T0Y$CO<3Dt*Q>-5_j8h-v|j;b4P z*a@|(yM7^)^+Yxp6T7Jj*LGkL?l-2mC_88QRWF%zyLBSq;W$8*EC|TL$2>s7n3?B0 z`KoU7-U2BsGURI=C5S1F+ zry6W!LGu$g{MM~lLZ1q{U=EFLLe=G%4AAuC&)NEivy_?-uN=H@44n4?e;7iYAs!I9 zQN|9w9IH-Cn$VByYvkxdFg(g<>D`U%*Hz%{9p&Uj`Hr%?al<-kIu9ZldIvoD$iJ#% zOs=J8isW?BM9?B)Y!7Hj=TOp%3^MAVLF3DobJb-AeqI+uoG>cYO$~)r{7HkxQR71z z)xUOQd6EXOcBp1hRsF-HdchD!mm1IixIox{alKL>SxPEiVZh8_2+HYocY3KekU_1@ zAbzZm*m#>t#ZUDSTWZ17LcKy6Af`NG=lY19X;Z248-2unj;nl22%ZR=$6=+DlV{oZ z3ygeZW9|+^bBL!fXPslM(kp^d2=&lr{uSBwJC$KQ@{y;fKSfwin_tW1Li4p(*lF|Y zvMs0=-`~jO;{JHqBK*5-5$ffdHzf~Is>_ja)cwLN>@MJP%}0j2X;M+J?rayAxe zxMY)VwkeRO}8l}%o4N`FHsiA_jXNvtYw1HIFH_|`P; z-t02@WO@}`be^qXjZu9iDpWSPZcXDP{(OY>Cf99g#rrF@7hzq&ze{5U$FH&#{QERn zgOd%g+taSEw;N!0q)BDV*7}`k+z*~1d%<@JN9Q5ER5%&Ihg4|cAvcFvR9(M|Du;X-O=JTgX8 zG}{N#6es>e%f3|UKj-4KvhzDP#g1sw6dwQ|(iGps2kP+}LyJxEOc3d$|0d%OP4QV@ zvL|&izv;K^N-BR-46Rkrf)VJJRMlsO#v78p3Q;QF|1(`QR`HjXt}35sz~u60Ih^WM zv9wSMPg-bimBbqKT4?tZpnMU1fyr$w+N1<)81H(LeB7X@fxSccp>{&|LF z0;I!ZwpfK2Eedf3!g~39j87rPib7~lm~o;I&j3#pfec{IVd^9PiBBX)Ac|s<5s%pi zwTQantXSgT`2<|8lVK!K-v9FgDW?^1x0KdfN_zRBkv=SD25?zMj-i4Hnfy6h-HWW$ zE|X2k+^tq>m&umn@d)c)=?d9a)DpQ;wi{{>7D-Kn&`_j_6IPGyT7agD8jw^I}Q7w@FfUe4gT7U$hmW}S4c&iXx} zq6!k*EvDQvdwuamft2@gU2JH}K^NO{&ybcbAMz)*0|LK*y=n@Qa<#0i6 zghz?~it;R>I9@cUFI&{S$m~kM58dXdg&iZO9*3CPMfll>=%%+#+Bruckp88Xh6D=y zf#dvvGyH+8d;#P?c|7a)K-ake-0Gu62fFNVwZFze?)CNf7VnZ#E<4`wvMO+}%g52Q zjvgWhpm-$YP`NQeyhKTkq_w+&&nvX^6C=)nk?n@5p`Ok@wgGA*{r`b-nq?;nZ&-?u zCFz)VnPkh^F&`8e^h?t*$9@GmHI%>lssKN@7JwM}k!wJ8b|v7417j|MQ;$Qab_sr# z15~>LAHT=P)b#{kgr9#SbmEoxh`OtcD~9B4DSsh(yI0%15569G$A_AH7owW(L=^QD z8hTQlfwus@OT*#zkXIy3s`wHUeJY~&nq+NCHMJS|Ie^DEn*c4;K`0Pt`+FSArI@>& z)<~Unt1ssnI+Z`?7kot5{}-Y+TB7sb@eu_ZK7x?J$6ppmu`UIl_iB=y0ylkY;M7_* zxfk_sSHwx*X!UQGRQR~mz7oNi_&C|U*%jfp*2NbR$C{XsMD$Q*@{xm(?8b<5jz{lC zAH5rehNh>#HNBgKp0-1`h_kD9pT1RmS0~}#WVyD{(P7bWX28t!ZUy^OIk;yI2%2|t zoOgx57hh>nM8YBwn8m?Y!8nN5&$|(hUn`+D^Z86IQt)k){9hy7Yyg}@|55;WrkQhV zcw%V6n{L3cScbaqOS5^zXY^+H4 zqX?Hp#FIlLufw&7mp+&LqI&%;;Qp_5p>nXy<@^xYa;a&3e?=Nq!v?(Q8;wynm7%wt^j?cBBfSZL zUjqEuqws<2c-8D2d{p6MF41a>5jq#4sg?MsJq|yQAym5r9~rkIn^pM0rn1Qm=}Ubj zi2Jg*%a;YmwOsfLS;ro0{N|voO=b!!;*BS^pQ{IBFSC8gcBuU zz#0bFc-FE}{*^CP2m2XFah^>97H=@xN7cAiv*^Iz2W7p(Xpd+`WVqG}OvnC}sD;Fo zE`VHOkwJgBX;17kKGY=%uiOLIr}+6MhB*(qvXfHo@@N08HO}!HeDn_2slw1w(EE>x zVJ}n_h)FSJWXwr6MtB(MEB*C4CNRGYFi~%d6`$@S_@E^yOjzS^3$l92BdFr{`%-*n zQ;>zK=S@uXDvF>syz*5#jLqYy{UZ}aVy3UvM`XPt5ICCEw7A(j0}MlZk30{rzSWfk z^D2MN)_zxG=pmz=dqNx@m%vQu`HW6+1H&?((P3QFEjITLLa%}$jD>XQ_Xz1;<&Pnb zB`cp{cXwZidAJ*IUN^I85yp^h3zTzzXnwX*-!Zjx3lD_YElj!1*xx}&5Os5`nJP3~ z-;45QZ%Q=(S{Fi5P3ugw3=FrLz$3to5Be^llPx---!j+?M3eWLS`?em4zh=u#4mzU z)f5xhYO>b`VhwACL!J1^zMNkBFF9>bCawGnY%q^H zEz3r?EL*I$Tkd|E`-S$|wWZNofFAk>PYu2hpWRic3ath@h5DUU10AkIm=*t}(EAV} zUGZOuhi}uzCIePURp0M*Exd(1SUfE|F4xqGiJiwKfO%yGYnbSJoGa2mz<;$Ez`oKS zinLi&&S~C^F_LK3X3?yPjW~L~Ii!!SH?LTP(u58G{v>$nTYbAm^o=vgYlR38?3yne z?A2c~&LMGTX1p>IlfG_!GSc(_dFWs2#TQ?Jxj7M9XvwJb8i-A2umLbj&em+5X z=5m+;T#_Jw>38Z1)1gZdl9A2^q>Z}DtS;104X!jr$;?49F6}j8E5;q!5X)ysGdm3* zz3;+sgR!;45IP>A+I)Q6#*ZoZ_%}bw@G;J~8ONFUgdYnaC+&!GUm-`a`q!S0amH<2I08{YzDwB*hZ~!We4T-BYwV_i+sCcVS zEVVk;Z|DLvmv`W(>N=BnsU(ylHho}VG=4BKylYuj)~GMCvbMiUT90q9$Dzrwr_|)$ zT;=>lY{M6Z(y>z8Y#B4JwO!6%^!Wg2N1+^R)hV_jtgXqj`n&+_%yU9(FJj7%_(@BD zH&}xdw4uY?#0@U$93Y|t#nMSP0MlaUO8t- zZj~mZl^*AZU1t|L&Pd@R$B=t4Z_%Z;$5zisp&?p}h{Cl4P}(z6_y*(`M3k!>&PaI% z?2r|h+#=rC>5*Sq6R$DK z{|E_)iT_t7SCuw1Ec4BOWpXzE9m3k=|2vbbOIO`zP5!sCZ|B?(iOKx-yUgqBVH#2O z-%H+`5HoW@3m$_>Jmcm3AVfKJRnv>Vki z_U;LD^~4UkJ5(An<@n~Gv-QdA;qIXCqu9Y$#{L10k85qg)AGw(8y7XRJ~rZCn&?5Op<_*Asi7FI4m{FmWSh!AWQ3#o_EGV{Azdo!@pT&C z-+$WDi$WKh%> z%~%&i&$BJ9e2_^+=^%wqGP)OMor?NJRT9-oJQK91)c0~%M!q5NK$6wI4{x=$PGg(~ z{m}Eq@6$PNOn!vQ#Cv#tOy^u~Bf{Fc{**3T(Q^9xKk3|Zfvd~Hx(4r}Kjo+lUPz0^ zytV?(8?G|A(yVSFU)pt?3|@JL+2h)Z1$tjsRMszP<+hNjYB5piH|Z828+2lXt}roF*_k@ludgG;S@efQCHS;YU-K})a^K_+mBvHJ3@uffEzo*~UQ9LV6`WMkM+jV-h z&G>J8Wbf8s-KBS>`L&65CUsr@zArUL58Z0F1UWAWqGbU!FN;@2RoP4`2oG~K}F?HhFNAi8#m2_3JkriT2>fk-G$6psMOFifW3i2 zHEl3RGN$>X2^@mfdxK`o*S$9F^x>*TyB?=6#F&|~$HchM`m;GM0+?`o6p_!4f z9|phWDfB<+{Uo}jr?U~RNa5{{9O{aEnFNPo%@{i#?V&|75e!ZKok&VMghbuck;V{L z4KYY3XoSQNf?7O}v&Fgz1_k5#)BI$xT&JoQo5-vEG13Cqe=Reyzw=^M)ddFjh!1w3 zfxT>Cpxm_6z-EE{sxM5yK@m~0bT?)1i37x3_pS=1>7r)oXmYl+uYqAy*pzR+i%>7| zBTRr5HA@oscWmRwnrIrSGj+7zNLlfUGUZq~)-SU;Q0t6R$zgnbqskjHcv^0d{uQyc zeAoT91!|0D)UDnReM1IIHzB-ieU4I>-VW`<9N^9L1Ce+Sz;zo8H54$0SZICJoo*Sb zyWPgNsR=q(FDAiP-QrZ;mZ8NqFNme6ZL5@tLZkYss{}(Jweu|1`9ld zR}I1;L47R$FXVRX-YD9ta}b z=^?)6si82ZkR0qv$O8e%)TegHa`PqKQkP?(3#ofbS;;!f?18W zSyi2Gc!`0mPYsUt5H=ZvaY2Mx7NP#n-7vcz%zkf}eP5XUg3Jyv9Ieyz{AzHxiP{#- z>R6jq)q{qYM}i1#9>S{z;hiADMHZp{&2E_84rXtr;adJ%mDoa6}N{TZ>RXD5fV6;QwRqy~C@jvcK_t zZsXo0K1H(16psL`=t$BrE=BaUUT zcV*O38Fj>hBDUXWt-bcS=Y%%z`~Kng_df4^o_p_FYp=ET+HLK9b~`ZEdQcntIUBqD zMHqX7Sag=w=d1>gO3=;js6u0;d4!J>TQ<8HM%oN3gkhVTA=NOH%-D;u?J)LEF?Jgp zyOWH4T`Zb_Ab0x0UrA7*4l>o?I1^QPwM5mhyX=sDI?FoTvW-TzWSlTKO5{uvh_L~T zU9>^x?7!LA6JLU{zl%j%caLy@bo~~j96GNuI>X0{u|qV2vs7}#mKko@yNql}>F&lp zV**v3!edVmgESg@eZj{5LdG5<7G1D=glQ6Vr#r%Tjn42|Ddm5-8NRR?HVDIZH^VQ6 zq2%g4SAzwqFqRDck_}z+4;Xr^STh-E=u!omBxr#S!Y~pe>yWqm5vIOACebwQF8iJY zUE-DCy30eokzZf_ThlM#qIun$fZ5=(EL)j+gTDXbx~n zZ(SS>if5l&BQ+kK7*8-+MW2uHJYaY>$9Sw+D*ASeF6SZ1oIcYrQ*l+H}U^0|X0O+|afSSk$5b_YwQiVlsjoNZWk zI#_0_XiALbHp9}61HdMC=cs5}jO8W6a<+pdT}2}?mTwG8hl3?cMayC=eIJ)ZU*TYx zs-i71mMMm%)4`IB`V?b1*08K|upEV5c)~*Mr9<=VwY|(AXPVxBMCxuWp(po3-iu6o z3I8q(uecdHZHB}oU1Z<686LD5h6zL8Cph^gip@5|cww02W_ZnJNEe3rZibyUL!mIV zxfuqfm}FK6!xe6Zu{OhUVR*>RFvn*2lQ6vFW{BDhR|vz;ZiZHy;TB;SveA_ff3g`K z7KRyah8t~$=Y`<}H^Wml!+XMTiksmzo8c>A=yWrDVl!9+b!l#LGwie(`U%5FZiYd2 zjXFdayqjFf9BVVo5QdR%hD^f{X%Pmh$%}-E7ZPNNz}3?<8nI}Hh{3h3)KVdDtoM4z zp>(}VDV9mFBiN-h-*jK$Cq?Xeqw!1=6n!%m-?rUCBfmM~OGYk<=3;qy!yG@+1>ki<3)<-oW+{)tgyECQ)aZHIp$$Npf`Qo$D2OR z0R6QNYohl|YV%TRr zn8+JAzDJ;A{$DmHcDcG}E+1)Z7x5#!ItkX=-<~lk&>RC^Hz}CQr;o1$u2V3NPalta z1LGlH+Rf!7jPC>2DauQTr6}KVoH6V;&KTk2jD6mO4u17PK?04{CIi=JUJKdEytXAc zwo#NY`d}KMwdNYC0)1@)CwWEjwCHfj-6e3;rk^TZv;)LOpTN zVfE|5QAGC(K0^TAG5Bu)3y6(R$o75JzYLs*N#+b!p zHv7iG$g>WykF=PxD{)CVPRNd?J+P7QM7S7p)&V3QaeCXRYsK_8t=-as)cheayN=R4 zdySyeH1KeTNad4+XzF`_*7RySP7E4NDl$>Xl<;dbdG86o+r$u=A!2j@>On2$ZCj6B zG$%OpePyD-XhAMuaOKEFMqSBeA|=M^cQ?!`ZEb15xl_EuNm)Pgww3k5mq&$$kG1yp zXHmWR4BwBQjA7V`fbvZHdN6{1^jr+C?Z6k)>$mh8zgCm?wyEPk@mBOZf$MdzU7pw} z(O-C5yKbewa`aEVL-kr&zcH5Zt~?w(3L8S+VzWl`yBJBEW?uQ5u1l*?-UlA2OMv!i z{M$iq5_%cxfd{H+Y}E|@ONCBFa}3j6$3IMbTqU0PGLEQuOk==fGrLHdOTcw2a&HCry^sA=@fi{6fDv#fwpy4U<7>BLJ6bPU7^GFYUJ5c%ei5-U^7jd2;a+s z#r$}<(A)MU^jHgXO*(V0bO`Pza~%6i=?sj$C&GOx;uaodY!S7C?6J@@FBu1;Id-Ay>uqgY_f?paW8TW;fxLA>0U+FNhlov8!n;LpR5-;RgdXHr)KnsLtAlIZQ(;k z>9}eogko4KG-?pnYr3;W7(2PG|7?mayi%kdaA-P1Xw(E=G@4Z8E=L4Dq#dQ~+RfpL zA#s9qM&V~fEJ;LQYxo199Uh}aessi|uIV&*8h%i$qMx|GSQ|~Ok()(~(y+$XmivlB z+dl12HJaq|-`KGtcP+K}Z4cW;ZKu*7Yi+|nOfA(M6FxDu)ap%}FKdD8&6Zw%gF_yA z79Z=f@@X@Rzc(F9cphB(iitq)BgfOBgVfw}57rrS5IP=8g5F<}=&a%l=lft-K$I+E@4{M7Z-u=@q9G>h z%3#qB&<^=bq>3#_wF1lP4uC#|^k&#QM5di&t`0U)Y{!899LW)}crLJhpF?f|fO#(n z|3WZQO8FET9Uf6Lzmp(083*$Y9v!PL+>7wzu1O_V{@9t;jP-~nRV2>RmSQ-%{AC!n z2|?8`rRYTf50Xvq0m%9sKgHkUXW%yE;cozN8)8J)_3|4<)i6=TN{#{}D_IO+H2$;a|2AW{|HNk?k@o}Fk~rXBarcr*HAhfL<9MvFr(qbKo% zLv(dOTjG!PP5fV9LFv-$rM5Ai=LH8X{Zue@6f1_$;hL9XHjh5_I6Rtm8XYIQ> zwYt!;91+{uc8PHO%pBPGM%OLsV9#=Nad${~PZ&cFgTZnY*(Ee8nM|g;TC_<7SErPT z(t$?0jfoZWaYjl-4iYjcJJXP3F3%`axpN)zCCzdxoXP21Cjp=^{eo_ zZ(vS^Pem={TR8L`B#ZbClIc9HbR1s_qTBcJ!Rt%VzWJK86Zmctx@#xOs??MN`$O*p zt#^^FcY;IjB!}L~4!u(xdZ*fYr-|N6hCpwY)_bq5H_M@SwnJ~WL+>1i-nq8k9IZD) z9f#bJ96Q#omxsQM%G3)%&wPzO^Z)>_qhZt>0wCl~HI;8WD%l-x3TNnBR6C+%5qlTb zD$3$JB^oTd^T%2dEb0sTF_0|p8d#i+kh2j|d^mu20Ax)Ckd=X-;(Yx43KILgdql0c zb!ANnUIL@$lh0En&r2v3ygt_5tYa^v(s@}zlMh1fo*10-77|kndh&Nj3=xZ00ILR8 zd03tOby@6+qUP_$l6rpC>?KV<(Dg zdCI_iLGW4I*l<`v|0#yr`Ig%vA(RZA1abo7U|{YY5=8AY)+|k3={gcQ3Uy?oNL*;r zxAt|acBKf~0Yi)G0Ic4D)T{*X9)PUV0o3KASZ*Um3h(m+7)c@+Wi<<$=hm@LSzo?zg9XXGY-o-DIOc|#W($kLqTSTufGrNo5l&*fp z(1qVcd{_5>fomG!d}Qb@eq;KX!1FMFeRuaO#!~ECR_C?U;cWgr{1$cZnystz`=GD3N5;v6%O3~Z4m3wV3UJr%L`Q!wQD93B-uCmMVxp$E{p{P=yAljmV z08)Q}`#2bYcg+hY7atAaeo%_%0Qil9N;zoD$;I^mX8(!}BP&H~1$0rlaEYMo!Z%64 z85}^Q9^G)y?sIGR1qj1(A1P?`=N zS-+jQ)l&X17QvYKBpB1jq6t0gZrhkX4rBT{jOok9OiCXD?!Fcs($H^B?#s4tJfwt_ z>MOp-(;Jqfn6);ybhn?63S@l)rV0Ax%kA{;zBi07#`(U z*}um#&ejTqPb+W2ZWwfv@A1)1{i=H%PIC_LGw1Z?ibj3I_y?Y|AvC?E0assq$P&|0 zTXmS=Tury~5eRJtN$^}QvW=o#W{x&EZy4llKHjgrFMweJ-393Vnl2Zdfy)KA(;2`S zxLfd>g-E`d(jPfzJ?|sLdhi3ej1UAmRX^#>!5ql&z(Igt@X_<@q=Sk6f{!wgE-%!t zw|~J$B|MpLZhXl{CnxlKssF+B={TKVk2%{V4Y+sB_tY^+w@ryIAFr&JeXpdM@y07Y zKB<^ZQEFI^PhR!W^9W}WrOJAZ&19V3p8dM-K3GIK{f6%fKwJwbQItsiqUb3XP%W#_ z={@&DlimteG_49{s&7&w9!i2vY6T}%C#O;;hmJ1m1E|nyxKn6T-DHobIx_XX-89bXd>wT{aRiD3X@X^%+oFuZF(xLdW znJL%wMUt{~l76t0l*LJ!%y~Fl=O>TlG_3P8TjwWUmaeQh+Q`Nj%yE%Iia@{XY|0hn zF*fo%!(_pQeyS4Mf{WOK$-EZT!Q5;OMM);; zJN@jt_2_O2XJ~>G(Oyvyc6kcE@-Ncs@I~PyG7m>-J^&c~p1*<^K)gxPHEA z4!;8aQ$M|9eu?tv)4bZ1edb>UUxov;%knf~o1cusf^I74oYJB6z+_CELfsSLiq#3FDmNRxv07QMyjV5d(0`gsBE!}`& zvQ=ZB1c8;-m*F~7y5&O?gCQhA-v;oVe`S=+Z*R_nCq`4jK+up{=5o{D!4=^G$jo6c zrSYHQfpazgfr~h=2XJlz8XunsoU7)KTzQgu!w~4hk>aS1dMDE_=nKBt)UJN=lTV57 z?~$X)yZn09sB>9?jCt88kC)+0TJwr*J-xyI7kTKM$R7Tl9-LT+C+cWDK# zQ~cRK06Qrwp`FV~`le_b4sZJ_xxm&p(Pdq_5P$VwhEiP*?zzbK-~0t|PzeKowbtV< zhN!NbD$oYOsu)>&DJwwL|E?sPyQ~$KdYGC&(4*(RS3?p{-32qbLKk*F0k5N&kj6+m zJvv++==c;voDgLYe1$zzw z{S*il4Fd2GfCUsz-o>GfKz+Rit_+W8|qQTivX-6U@3rLG7eU^OxJp8-Rhf9 z^jM5{=+cVS#S-`h22cGEqZz2lWq~x9id-W+XF`VNLYSVYlH7SkBB8qs^_>?BX=JHapz$}F zjuqoS1t)ubi0%oIqo3;K!RIr|IfJYIr?+nb=CgnfnnwUWBpqma3CL z(_F_HDV6)NkoEJ`-mSNG@a`F(J=Ef-(Nq2ne^aL1Acy#xF5g*3eBR& z2!4e40wjKfARvn#A+qT4A-7$0(L<6R(ovmvS8}L*7G=3I>Ub6*&cMTfodkkz@R`WRk%!WuRA}@;8%TY5Ag-XO3@?Lhd z)CpV^*Y*Oxp`>lAPv!0sW+_d*sv$ezj7F|h8$0l-7z zvf}vwf`=lg7Qnp#YEA-xS!a{#v0@Lohq!H=YHO;Bydh*t-y9~REw=l3FTAAE(_0|21pxwf$fI5|)1uqgU)Rb=4 znuxqX$Yk7SCW5^im)OO)NPez1j?(P=w{{9x?5C>`RCt2~=I8+SBQDEnpWs5;uS8A< z2zd*}+_wK9ddSEXMwb|=cf*(*R1r^}Hi+D1hvwzWSnm&OI;UR@MfyJwGN*r^s=08s zbWMLkM5`tFgHZw5(eBYSmhb2)pW%?N)bdWJYSP8RD`v!MhJUr9_mxJ7bd6H6Gmc{aJXU325?z$Hr)z!U z9CV?#OT**L*>Gemb9`+b=&+*iioCDw3UA;Vhe0Z`U{&VjvKoV1(8kwMwotWD57PvmI~P$G27i3>D+ujYPk+^n~4qtZDM zF`km-pW2W7RxwM3KNH{ZwwBPtfbd1qz=r;(O9>w*?ucfm7Fwy?rg=Ounh|%|zA0MB zqNvv7a{R6m*z70)NzsG(I;W^PFW2(q&OR10seNF7YFF%50MYFtk665cmmMj@_CJTG z2!8D>TfMU8vUsKGsv>VX8u&3Tu{~7cskYdU4zcC?6H~U>vVvH)T%g4$Tdo!|Wy^~$ zZF{hNgTu{8ZVxDmsr|%Oo0}?RQcHsi-j5(Xw<|kNFm(z&_k7Hjt(d6wsYB3nrw4|7 zgP!|x(EA^T4*NU+^9VQvz)Av|0o+AEC4jF1EFi&}zXHP@dg2Abw}{e=rZXn6BTAg) za2F?GUE?&7ryM#NzE>5}obb~^O`$B97+CZ@vLGG_I^=Mq^EWW0j{)#4fNKf(6u|T& z0K5a>9RLeRux0=x=$WZ_1c0is7?X@;%9dqKvjMD;fpX1}KyaO_$*S!V`C~dcU2`Km zbc)W6ZO(A=ICOt9Qfazu_@;2K@DBP`w+a0?L61dd#nkBuP#IT<01X+Yh>%s2PCyARh8#Ro4$CJdT znv5#%EL)RjT(-DMl8a;W_^rq<*;Rhb#z?WxMR)V4dT45~KWkjb8rsKC3o3|BH;Ed$BS9p>=X`;kqS zoTuhP&qy8eJh`5l&uxKC)O_d}DJ=zUgqB;*1F(QXW6wyNK;ma40vyjsmy0g_j6?_H z@F_b6^N(tVPPdOJ_*m};KBJh55!QX22ev$bhIO)VsYAhWZXjz1I9>)l1sn^ASo1zN zzvR1h?aBR81n3qZq&ws_A*i<4Q#4hxAwD)DPil8On}8_p57bf=WJCcOQFZ~IPe)~H zQ|~uiF9q%)t~(L799-pH8L}QiNb!^Sxt)}#!nDPhca#!Mp`^SSIP3>#SOWSMuoNu< zFk?Kq9)uPz1J(vC^0dgjh}86f0Qos?f!*8g^Iq!Hw~|g6sdE2Os7;jRC12ZS9*Y+K zjK`=~W#rUI5fAHj?T?6fuPnC2>V`PB?xt&c!KAW2*Rpd;^6X>@(1(aA1g!!bGnhYP}n7@8mHbkydt zupjxbS1oVFw2Ve(;qgrJhMH297VhGRTvjxSyvlvdA-H=RatWmxAr$sPA;@||<6df=Q`ZHnXyLfLnp z*6PfAmr6(8n@&VZu);A++O;1oXFCj&u1E$;FF3TMB2T;2ga6W&!=zlPmpnnV(1W!% zF4?Pcm+rIFT~Q=C4AmB*)4pMX&b)iHW{liaZ0s+Eb}+mkPk8y4iU1NQDTJPe?O@=;tx)a)c~0A>7c`I6_)Y2tDyt zzvu|5j*~$SJ*GuQ2tx7PVr0nwM7GF?<8Rkteolw*Ty1cwPBA6P`gy-e>X0O{UqBBM z87=apcc7Lhz2Q5AK3`~hyd*34!;wASw)^O9J;~m-NBONiIC_PLYiuLLSo9eYezhHr zP%EJ9-{G+JuKnA(L3$X9MJnw&=>us#;90SZ{L()i^R|IscB{;;Qe6?7^fhWPmpSP7 zuE$0qEiMt>EFlzOsvW{3FLsFklyJ)a)%%G!)$x4D!g@)c5@ETKSsw;r9)&q z&UJ!s$=41BHKL;%$_$ew?NlYWI-M?}Yxf|E2+TyyIFj=x48#(k3U3mbH${e@+d|&0 zQ^ePr&5S(4PDV5&%oQ;Ff{1=$i>k=4LZhM@`J20?zyzE*c2$!^Gro!ZB9l%3oMEY> zSda%_;pj}A9V@glS9avMTF8doT1cD7QVY3A%To)vS;%DL%Ux{L-Hyw~*(NJuE#w}@ z;5qJhcPjUwAt)MDBwj{l6!k1E=`&`3FZmDaHLoHc`=h#B^f)Rz57ZMUV~lo1A9kN$6CEq6!%k`QXzmPP5{6KvL8 zU5QCxFq3KLH1%wKCFBc)9H~R})QJwSKGY!@X%~d7J=dt&M=tN~gKuzXc&dwrJv7f$ zyLnEN881rMhgy&h@^R`;bj*eg^X#|qIvw>|r!x0H`y9f!T1BHsW0w_ezoJEN-rjVK zN-V+hHmzkdelYIir9Dji=ID%bqSy;wqzmD7r9al%BfZ#$cO!yc!r-*%ZUEh;V$Av& zfa2%ya}luOR{^{Opyqu5IC)c-c$iYjkjx}WAI_m%%c9e!Vem^~ET2X4StOf9atkx( z>&O?~$lk&}#1e)rxra(%@7r`B`(SF)YNEXZQeIZ#+yps^H$hrI!xp`jW)kmtoW%Pb zC-HvANxau_67O}KUXRx@R@9d_HsJkA*bgwJ`%{R4c2zB@uEa(+>^q3^_OYqF%aL|T zDQjAHQjfhx%9`GNz?HN)2jG$2<9(o30X(XEF9It7&geb>;N+A+c!W5bb?7Z<#LHze z8f8*20GSq~-Il)K>i*6Y>OFL>ZJzBqg?B=MPGP%F;kSJeg$~rIJ=KxgQ*~J!rIdMN=nq(-D!WE>##HO2Jg?UjkYwE);BMqje4K*J@olfVA~QP zfRD8{vp2@9ycb4uoQc|?&&+(kwd>c>Z_h~W~O5XwDN8F|KZ#6FFzU^L-<05uX~y^ zG5XBRcD5S}wI|Qv7xrlUQ}F8>^uOu(Jkmio=+l0mZ<)KtF|y5r5{EZQM6}c9!_7-2 z2WW$mwXNqjezYXoS$=RT1{H^GfVmf_>4r1rF#P=Zh71&7qR`;mG|q%dZq$6FQ2UYN#O$c^8jg@Y$qdRj)j z`6^){tG?Qg{tq1b{W!IaRmku?B0nw2DWVZ07O30WJ$Ub^nKSmcok6I!ibtb{fM=Vn z9#E$8LhZK>Tb65mI*0U_!j(hYW44T@(QxFDV|7}oYyGnpHuutVUW}7)dJMc%jHNs} zZBb0_rLJ;#d>nh64yO$Ap)z%Orgs@-pK*?4muM*(iw-tYc$Kn{NmR0NUah4#NoyS1I)%>pFAFg)bsLSk+=9ii6zwZDcbiIx>6~5Y)jA}n)>F&+ zN00gOC1_RC@$(dFdki=pl%e^cgaN!uKqi1WVE{(}*i66(0BI2b0{}b>U;!yDt_F5g z0oqV2fXRhuL#G0u=2dek0NgQS8q)@`g);K0xZO&{@O5cS9!FWexgV+B8q?>F+)j$$ zca+YS5?IaeIa86}MFB0?r)ULOO;M4drLh{AFZ9)P@fp`&6`n2Omq?g?Jf(ToVm^v( zugUQ0h}lNrYFU+{f@;uhCJIE|CUi3CDThgyI86H3=C@6XY?5%w{t*X&;?$2yi&>HzSJ1BkKT!iz0mVK2zt?f@N)`kbJ0ft@`?bw0bu=n0M7xK zu>inr0ICSM7C>?_S_G-7*##`*O_ge2cmRe*S4kyqq-gr}=+gr|Z8hj`L8$0>0I3TB zgaNz@V16cm1;kt23MlVbw60SDyiULc0HTY~%q|B&&8+OJS&(bpN$G zA_>5jSHWH0m7%ydS$UiX?77QC_zM&UYK5mY4%9LldS4|WKN+>XdVET@uR_>T2p2T~ zSOZ{w8G!Px?8Scq^*#g_UkyMV533&lzruJq3zJEPZgaF&$?uUxiFY8UW<|BCjZ_rf zdra$z65jy&o_>n9AmBq-QuH){aVMaJNv!5QV3Y{7#v+G%YJe`gRq5Wr)B<*DX~sE+ zD@5uXErFf^Erz>9Q&XswKCvHty^Ov{hm;dZ?bwf$vZd~j3?r$-68CL;iY@hyNYSyX zxh!SQL*s%}EHM4-(0b~Av<|nm_LX9x623`GNeNRiqJ&BHBw-?h-`kJsuVo@#pp;iN<433z-!)<7jLND7Kiq$BO)B%oD}w7C5qGSKz&{8+wrC)#Gg#o8t?;bl_`x+vJJ3 zs!qep8(Z+8Gv9kYT*vg~{M@^MZuC*p>q=|rkU_Ec3JR*Lu6JS-7OhyuCvFyczw{c8 zF0?j0UmxqmtbtPF>2OuFytWpk|15+`Yj|HvHIL|n?EttNc{^Q=teVFQ`i(}@1pQW{ z`GS6@(Wsz1G+Hm{4;o!9=#LsbU(lTz{fnSKY4lb>cWLw?L4VfhWUG_%Rgb(JiPgYdD| zo_7e&$M6B74PJU64n^@mj6#2y`Kt&+!D;MXV0ooWmXJmqoOr}L8fAs!r6=W;x7O7; zC>wF$#{MyA(R9hWg(u88Ks4s))zSkuHn z$H~Pf1L#qPZtH9SKN4^$fGHIKt^?4#1i+mD-X!2r0LhgA{th6WfDZt45b!O4%>be! z%F{SE@qG2ye%vlS%drg5Amq0+E#$3wR`XHU5nK*efJ@smX0j+A&r;}dBRp=Y=J_(F zD0)$?reRtZuj%WrW8ify_7ON85q?)#Qg#c)?o10uA6}}{Iw~~79*wDv8N+M9;fL$B z&~^I|YKaLYhrES?sqik5ePbW8i(;~z`sl<4M@n~UN&R$6GpR^u$qM110fo*23ekx~ zH$YD7tqQGVBUOcuyq*zwpHMO;$KFSsC?1FwbygJ$ZJThR(4q){zL578V|_HVMC(8t zr|VGN<%hfv7@qL$V#*C}hNo?Y=Y-)IH^Zxjp`@-w$KsA$)s?{7Gm~KLXjmJp#)}9? zh&^$jy1BzgNzh?B$k_Rji6uOvQOAC=iA^H^Z-nq2#>1*x3m?#|(s>Q())0 zWM`fjbI~R@nJE z*_j196KY`RDlz6*t;$jK;Y%fGl{=Q{CYJCWV#ZoG!+e|J@51nyo1xk;l-#lxJCo5V zuO0+Di(u!4Waph?j0aRM_Z*`n{Hz3x&_O0QPO=&5#f%I$!<9C}dBRZPX1LWblz3Ym z_0x_S^%HiE8VozjVQ1n}*!fQ}=2m0p`9?{2mjpfUj^z=XVazfe%a?A3EjGg(Vd#!1 z9p(P1VJP{RGe7N^Rb40Se39&IhMgCaoqa2HToJ7*DWYX2>)QC9C#gXD95eI}mo>1v{@IJGY84-|lYbPZHDz z0*>4$GqHrnh#3>z3@dDgIl@rnX1LHWlw7$NJGa8lenVmBR^`mk z!zJhucP#5nEa5sa<2^US7MtN*VffX}u+uP<10y`^`Vds0WGZ}}O!z;y@ ze;Yf~jFRxh5)=;sN4Z~RGmL50WpTKh;WnFLjxfw~GdyM(N_s8V8aRjSnBhNRXZK;S z^9$H{J=uA?7;~{!74q8L;b$c1UUw}2FtLQclI(iT&G4zs5GQu-a5H>o7)s{t#m=p; z^M0~(7wjC_2s=L%W2S@3se0Ea3GbAkMLNioyUI4@{*{<k9N27FbVQPz)|i8nOMR%i=89g3=?dIr-dQY z&5&joN*;99&zPMHN?>Pkf7m#B8EniHL(bA_LSCCQe1Zhs?2aMN#1I}MS+&{Cu-Imp zBMjTz49g8e$=W^Vr7E0NjtO6RTIz(s)`7m^kYegh{e|d>i~v%!yAN|rh(RhlZu3AH2KZ1G0i*= z6gPJ!Ki1)nAQAH)ZK)TuSnL(KG{c0=Qz`QBMyfqX0#rK}Esf2r`Cwb~JdvVx$AK(G z`|NTzOMa2EecCwNXhPynEYsDHcFZ?x3p}!GE%x5r4q^JU(?tDT2GhW=qIU=jW=8LI zs=?k26@FU+Uv`FY?jaMxA4urG>`*LK$P+ZBW$>uoGR8~?aK@B8tCN7$T!&OdOSwwQ zCDv{pa>Boh*fJK`?R~rb zmrL-=V%=&K!JR^*v<44ymYrViaanD@gg3lV#0Ikn?;UzoNL1yH(VAkB>nc}mo{hn%W0(N1BynXMM zrW<}o#8+!^UIq+PxktPXUvRU8I(>o30u`xtaDL#_Ba6|7ldJI7ITCesn#|VF(p{un z5Xzq6qn$N_8eeQyjCE`@`4jn7W*@ z+H@_YWOntQuCj_Vn&h=P`t5rw^!qq4=h{-yw4}5Q*UcQmH|wT~-c6WEr;oKZV}jY; zq&eP2H={3GKPH~8v2JVze!&p1>hMQfFcr%awP}1KaLRJ*cH$jQGx_FUy~8P;ZwH=R z-5hOguCA}d@8YtuN^CmIh^LwJGuto``#k3DtxUcE_B6Hqg!6?-+3|E?(y=E(8()w#CthEWwEbkh*@v$6iPksB z6*_a{X@OwqDlorFw<+bsKi;mF=jJYHXss`gE~&0X_9<%~+Z;GawoFluVars$ZX|_6 z%dmoRqAsrFiO^FO|Lj=w;Dw-XfJ{*xfX3ATN(nd_z-$2D5^xlNO{V}z0Z`hG?w&N% ztOSNzolYq}6TsM0v7otzDH~31x)s3olXPq~R|CO8GO?ufEwSPOE?QiFb2x^0_kzcB znn$(nlF&;f^iqV@yux}PJ-KEF0~=4Si9?2Z*F1f4@c{s)LNGjal_U-VR2O-96fd&R z(HTG!qICSy+x8mm?!oSLto86l@+}ZvEW%kL%yVT{8as^sq5&tfgo~>C>6+8&%1sK{ zvy3+J%EqUX3q@GlhNDVfNlJ;(^_Z&cjmJ!;Fuf~=InHNb=c)%&)%n8FV~kF>p5`Ub z9`cqPYZ6Zb4oWt%MTJiikyNJ$XPEPlEH0Ad9702{Jy#?!bLR5L1+!AEc&_}Vsj90#IZ<>ETs z3jZ4ZNz{(jvM34_nX+2fC5kFb(gw6vTA`)oA zk$(w&@X_dR9rW*oPD}p_O$^}w#X(;d;}0*FR&|Ha*rEDxWy?@<#5fCLjso$WE&c@L zL@Ek81$8XER%D+OS@z_5<5}bZ2_rlH>98Zg(U^YGbbs4=Z1KclCr5)gYP`FC=pmuW zR<0k7j{1Sw4i%Ypa;zm3XnAT0Q6W=lU9x|*IbGFuIMm)6Q~QWR?N?pY?x8ksb*Pm} z7kR;<*@sa8+8GSa{n4R$_onB{gU@ArOHEI->SGLfjp;cB*%?_)4Rr-AO&BsMZ<_Vu zB<9x^2Y4u1r6Bfkl)mR>k^xlH^b^S8Lc<3v4D1tXH?IsXi29#8Z&UkWSa8M zvQiNo@}`Ocn=cc`1;A5XR*_AYuzF`(=P={ceKE>N647Q`FEM*cS9Zj2)CzY-MN4UQ zEo_-zZcX&&T2C`y zQdd6P7H~pi(@Nx8V?|R7nzuL48ZecNN$e^l$~j{s1ty}fbrQ=2Z5f1wTPvDY&M&QP zt;k%lKzSq9%gm#kJn6L!%@u5Gft5UsqTP9)F3`M27 mSz1{EtL9r_4&H7D=T}rL zjfF3;)^PaevG9iGmcpv0iqi5JSF!abb8R(T>GPt9CYoQ`L^~n8w^&P$BqQFE@aYns zUR7ONuDrKe>kw>+1=Wjdxh~#jJp*!{@an>fW@o_a+pSMn-xd?!?CSCiiZQJP^>}e> zO9g7og) zoPYCP$(&~k=XB0uaAsAMQZkhHS?{~x&~!v#(>Hs620hOdNq*JJ=IXN2TC};crs_tz zaMk;qcW^N!sokXIz-ynpv*fy<6KueAjRn!xA1H3-zPWYxAdSD{(7!m1a% z7qRLUjudhRaEsBo@S^u==4lk3GvO(;cuF!9J@yjN@>42X~fIg~pR5S`Thh zUT6`=Y~e`!JqNdXPL;z+9(CM;>iVLBnZ?R#z5-OJx<|LcwpD%Ukxff)73me(x%1O< zvNNI!vU9UC)PO}_K*mp}ZdMxe7MGSS#epkjofGOkjTELX)C&EdgYCpwMUc+OoS&Ur zm>J1ROV5lV_UP=qg2HHeUT$F|FDEB60`GMl&bi@PQl2LEB1U@BGnF^2x!d>6J-cY8 z@)l~=#=W!VWY2_2DbcL#9GIxQ3$%oJut`k8e${PA8K3U*sg-zwr#sH0cEW!Q#ZRY% zwQiiB)(fW3zKZ)so+OQW7`Hq@ysjRF^GnrW@GN5-efaY* z%0`YPUlQUcZ70$jNBM=L(b|SGT$o-<94E4=N_#uB@0^U&SjiNkh*aqWkMD12rgZYo~?9oEm&HovVug3VP#cI>EbB9 z6!w}m{z%HEpalAY6BeQ#F-u!hbxTFG4nA@PZY;+pHHt{NwCEdq->~lE>iw2vkrv1N zL@gc8GokNEXd>;1yb-Z-*(D${+-0t>qvtds%fAa<##U|on{H7o@|F>SeX+Npxdp!u zZDzrBB1jDaRbxdL{X0TB*E$Rv<(OO355m$YEUUJmCDPY(`$^c4SE2YP=?QDqw*Cmf zw|~~E%kf9w{-oT1{W_+w z=<7-FtiBaA`t}>+KdBB^GB=bd`Agbpt^OWd^zAp!zq(^E7GCh}_d?+0x{A88#+6F` zPQjRhwwB7@z$quev63eFOM2WQmNJ~Ql)r(KSM`Qn^zEO0Qgb6lc`Zwn`5&~(TGftN z={ul&)ik7xz5^;&&qDn4?N{Po^;eWEeFs#pZa_BB*Awrdi0I7$@;9*fq~_+b(t0S@ ze}hi9R^I|v`g-2BR(qgC- z*Yl>;ZiTMtHer17Vr=SMwFrzOg_)`wK{E>qBPz(W?1KEX!t~iHL|A4d zk{3~N%#xRvqv8pIE!kuQyhz%tOqCuB$jpf5&76~&UZ^q*M~sw7BvNH~ zvWSqLrDpLzJ-4da1kTTl6lCWiB__J;IFdx%+LGUU5-tXY)`8NlW_`V=f2;^u1%rp1G zhV3;ay>KjPO_l2TZ{eu{PtTtnNMb^J8Yiq3A*=1^dJhvaVy9Jdv^Q#@eegB{ctYhX zw8%H42ou~nf2_41LW5+@R1z3?x<~b$CTuMrKp(%eQ}v5VHcOTzQTE`%85x(@!JKyk zb>Qa`*q?IlP#8Rb0F@MtR^$CQcCigP20^~yVEhhTfF6{-{`G_O08oa3{RXyyN?&X6 zz)Jkl*MH}rXlp%>6V1QXU)=!1eCp++|L~5evaGDGw7MSsP`>2oqmuC*c;xxt=!d*G z{8C=MWC{8GV(Qa8|HC?_eRMuoq2&F6E}c(b5IvW@jNfki=zM~9=R^GHd={Z%c7x}T z&WAwV`4B{%5C5a{p?~Up_#d4Q{Zr>d|GM)bNOwL=vpXNcr1N1G?tBQcJ0C*q&W8}Y z^C5&fALgLWM+4}5G=R>BSu3G^jftf=%Z`u<33_5fbZs2#a+-gz3(QAk+D1SUR6rK&+?9FdQ*bCXrm74-u&I z;eXxv5V(8i6Cz1R=R>&N`4D0{A7+%!hhRtNLujn?abR}mLo`?CL%m3pkD$e0inGI|b1r!N>T4SNBx&r{+FMayAp8z}sZcfudz97|Pmy$BAB)LO8 zMv<+gAGzv!#Em$HW1ΜHwjGjA{fScLM4Df(X&;V|vg|RAUM{k!X~Bk+LRj7bZN5 z@W)!44)(-^Q?*gJq7KH=;U`RbVeE=$(D4=`z_g0YeD)%vmqMnu>JyDpe;>`s#^gs- zSqUW|gP7qYb|+$A>51geUx*h+g6vb{gVoZyyfWZ#!V(_bAUq)BqpahB#mXwF4%I95DaG0nfJ5_*f@%7cV-@WdV9RdygP+AKKMTHgcvu@5R>bTV&L2bk+pwloR@zh!uX$rByaIYc zLsC}q{gfzgvRLiaQzhzMtPQ@+$zoG~51{=w#Z$~lg zbx`i_(iwOm;koQ-{08>X8FaHd1LDVMJQsyZ?NmAg0(ED=4H}&R|D!XYf9eeQADsdH zQ)fW`x-%e1cLq$eI|IU`Ghi0(3<$D2148W1fDpSgAcQ&t=Ah0%1LzDifX;wf&>3g~ zIs+z9XP_z684#p91A^?%fDrBs2yk=;gqqHPU{_~A1nCSks5=9KO=m!`-5C%P>kJ5s zbq0j#&VV4(8E9BKgIGY!^Jf^27%7uTuFil6)EV%^r^{~UIrl&eVRAgjBP1MJ8o{G!t0uTYppt?2bI#YKfaVI zo1@LGjkE}lf=ZEsdKYzwK3D$FFR0i`gS}|sUUHC5D4JQEo|#{W*<<70uJBwQ8iaLK zf98s^ipCaP2b11Vjune5LI-1Py>)=Hbak;&_PaXF>UEi-X# zZCO=e1IM$8L)JS(Xd@wqJ;`AkbeP?gMDQsN+}I`1mVKIoH~Uol%!OEm^PV>ajVgWt ztwVXwe;=mDXK3Vt;Rx8*YGk}UH1UnShXjjq@^WYKsK_@iM!+RbzDVnUx}G@pl6 zo?YY+5=c~elB``&#E2$*Y`s7P)~qR?SR~v%==l!sj7Iy+X=p=($GYkF7WCe9?L1#!pRCiJn>h%O!T@neBg=MEtX>E31?z+fNFDDnYY) z=J=O_vlp@7k8kh($o_5`f5zZFRWEW%uNyoHmsLD(9tNQEGcnf6Oq(zsiTBh5CgPSV zb}guU3mTg6_`8%Fyz&>|LAMoqPKj2_G>^Zqv{Do5*ys8Dk&5PursWmoXfXBK4f->i zni`t&8q3&UH?Uwph)b5B?^T{gb|LW3#92^L%Pm8BmN9RFtrP98iAg>DwEZtnq?=hf zk!dmE7Ut}03!|O3GO53Dk;_>wNu$wurOiu~r;TYt{8_Z3ZrUcC-ipAD$hl;Hab2B* zx-vld-5F;Rjpl!1fU+DbjR{?I*Rv`>x!1=~qcBUA5SY&~JfjyoCKNEp(07h_upgC*-3+e#Qb(cO$~j{^pmdk_GM=w-7`1`%5{<*GhZt|vI1GE3 z@pg^Fv_}~4zy>8sD0xS&!MJk-74jzbiiugZEd`~^(V5=N6%;tiM^n}@rDqP^uErW3 zG8zVAPYAZxQLpTICP3YELcW7A1O#6+Qj|+8Un`_Xq@@GY4*Gr$c18W@Eus#s|3xl94IHYhf3IO z$m6*tL{H=i`MZa7hAwACB=2(!mh!Pp1N-+1;6CmTeTYCk{&^s@8nABG7%@aD%D53f z7d-wgS(F(AALX7kh3DdOw&Rk6k_GZE&1OYegY#$@6~5z7tgPO)>ITBBQIY zA3MGO+y#B{xrGIVX@x}vSd=9{J0NHcJri1!mb65%I||egGP){oauKQ_?*AXMN(R{R&~X4(wZWwh{HqW_01r+KMltb5 zBl2iv^AhXjj^wKJ(xUe@9 z&Zk(aq>5T~H0JfJnLXrCvGQA;K2U;~GO@eyCB1&pAe#4&SRR_@dJ~iZY3C_{M zRto6EgM$n)Ex<;5mao8Hif4Hv{-%=X-$gWPMAeWtg><4OVMn!W@Ki&-kf4h>C>-c@ z&e`qlC#hlEh2DloGu4aAmGVv;$8gH*!LtgY_6SF+yfuniOvqdE@Juck;*nvr;W&ug zM=T94E&2391$sKLMh`>0F*`?4TN~-9mZn4xC(FPm(*e7)pzhW+)>hQl_j=(T zRl1nATkBtcDqe02qkSrhxr0A=!(6n!qOA`7Ii5nFE=OH5xU#xY z^Oi(PskbUs{(*x&Ch_=K5AFyY#DT$hTP(Z29Q&~SgPEQfqo-q2>`Zv^X5}BkVM*}? zSoF?Ya%@FYLl*X6EB^t5$k^ogbSxR*XbE<&qO&Q3z=0evQU&&$0RPZIl-@msD*t#+ zo9tz?2K4}A0`?NDtdF8f%M50Ora7!zkO$o#!?TPPc@22?`xqpXx^HIie1JU~_4c+x z;_gBF?u*_=<{;l^gMhVvqnY+7DCBERX6nNt)d)a0se*5#mY}O0})^A!zN>h@b_K=(7sIM+BS&pzcrDZMFtL z-)r#GuTf+V5?NY2zV)CiMnSXe9TSoa%v4XnWF-zEG z(|QAz>Ha6~M>j4im`>Rj%*L-jFd4tc;@gcjk0U=(9jd8r#?1ka(v)J?bkxmwO;2&q z%ZNWg)0K-3{_dKdD0KA~xEG&l`QwWYM~|9NY#YUA}#md<>)}yT|;q5x9744@cZBG8X|ry6sN+m(q@wXw`<6;P|O=`^z!Hsf?W&6 zMEHNZhG@;%u~1BCY@yhJ*$c%)b1oEji&mI*CNX<(&~wYCb~Z%-JjtRAGve-6$c z=);RW$lM6wrQ;BK147SZY`kF40!wUauEjW`Cxv>}B=@2LNiQ-1^9sFx5kJ;PW(3=*9Zab_8~A`_B6$kLOyvZ_j82A~64fOThJ8&od z=<6>Wv_y{fnScLEyl@E-`_zY7fB49PhIC6B$EDB%@tL~7Fx2DEm6a%R1Y)5SbM#iI zYdF@$??w83Dm3d4Plg@@R#ntu60aF)NtU$qm9+G(LR$Vuce38#f7i{%#tdB^sk`jV z3ZcGwF584(|2}qR1?-(!#E%YlE=tr7Unm_efqG{aL9|Vm|FJWR{%L0x|6^ws{nO4Y z`qw+N2+}*Vm}c+HB20E>F$?d^BFNsEMTosKix7Kf79q4Vi#cd#mIkmhO9R-M#VpvF zr3u)X#RS@!r75&Ciy*x-iy(Vv79qSdivUN5OQ_kIMX;;GC4zLg8q_WuMV?BS-kC*^*_owb*_jm!h;75lFdQ*bCXrk_vxq=Dv-n@{%p!32omqUs z!m%?;pQezVS%jFKSYG{fyZ-D%<*8Uk_JRL{Fqj!S#2BnRSQQaX7{Q+D!voC&HU7bj7>#jfE zZ8bJmw3auFX{x}sV0f)mN!D|cu20BoMWZ<0Tozqk8pTXMCK;2SL}I*nP+HuI3kk7F z*o3?Ty3hDHL-Y*29b^w3DaH(?cf{|+wAaT*-)_g4k@IqV%v(GV<>A}o@iCv?tcyQB zK1>IWeO=}?5vhHy8DYC0q4sq>*X$2^c%Omqyvq==hqo5^&Oef1J+0}xpq(r-)0&=q z&E7$?e1YIPV$2cR8lnN?M(?}wCgzC8yab*{U5BQ9&O_6l*z~7=9Oay+Ap2NMS1SJ{ zqao|j>H@n+ozHg6KDT2IM(1VD!vrN>Z(op|4nL5U7nzsFD~&0E7Lo;OONEHN8B+u3nx9(#va5 z_wodrUY=mPmnS6F%M%vs*XDo-OCfr*~|9{T1Q@o%GbBFyqxE(k0KYL z`qKVeddQeTs1MtGTI*?f9`^xJ2Z;rCG|(ufKvJGnv31Mcq`9HCJlZIp+qzAw$94vNo=91@zd^?KttxHCYxC|PZ-bMUcG~nERk*sRA=( zDn%`#kF~Y|EAd0>nkx}V;FR+`>VN}Ly^d{WlG(H=F zJ8YKH<`vpS%mt~hg}Tq$2$qq$4Db6989QpRvL2wp!6;ON2dNs2!ol4QVFamz9!0*a zmnfn{!N*#gh^dx?UqetG(tPkg0enlqR{+}1_o&e)B8o>vs$(J~x?5jj^UJ|kfW8e3 zhY<158-USm(}&#wAoBu`I_v=e_W?*wJS&Z(YDB8?Ac>qpn$^%$p|1k{@M=NYm?2E6 zC|80h>hS9&=sXSrEmb9dBsAJ}ajVuD@~)8FSINISf}btRD;my%abTf2CKM|E!Y~Ve#V8d_abT4bvuX_(>{eHln-aou--lKqvX%1wpOp7h zEFW>PpczvuR@TQ{UB^ZnE2<|W;( zub`e`q~lGMXOwYu1r=B^#(iN#{~ftMnp*i1(X)k$Z>zPVhf?GFAnoIa(a#wC96~{d zO$RjmLXSFhE&wjgMF1vVgwkvTkkJPmP7$tBbr6MF|ZKa4CEl$DLCel6^OQe$l zj2W@V6d>;;4U;51aWYgrZq*`YR=1F}P}^E<)OC`&(mkrf3#vFn?v~JeQueguV{+s&cV1i=t;4>gjZ9c0KhYXvId zAp{>b9)V*J_n}7up!_^EgMsr;Is7S+nFVIMthqh^OF|ZL$U?f(d(1Bm3)womvBFX0 zNiDmK+~R?lDW-;oTE4y$8gN~sRQ^DaI?4la+7gX`JSAA}*6kxhSSCg7jhp!enME0S z7?#7WCsSr_2Hig}P8h4v!&l%sL(Hv%I-aPLXQ0=mZ>Vs}67FMi&}wU%bKh2csx^5w==8O2n(W0NeXX0PyKj)2JPK6$S~sfu5W7#^GzSBL zKlWm@6)h`TWS^H>ioP?tgfL|V*26+v79pi!c6t5Um+ap1$JDMBX(akNRFk{SqfDxvz66rs}z&BPgia|47PMW{X{Md;Cl>QhpL zrV^@8NfA0T7&|3JF=YhhloZ)E8wj?~cLWH@2Z9IhHH;Jk!N&QE87Tq6r=*Cj3J9N) zBBU`Wr=$p35tLI>gtQ0cloTOn2j!F$Ass;2*JUmt2mxcgzzaT3RwpQd`gOt z^+A0~ir@`FeM*YpjX^mjMaX6#NKGf}+5!ZrxsH*yfFL#3GqM%PM1@mQB=b2CJ|#uS z_Mn`SB4lR*4RodUla-=wS{_(UK1%=D^gukn9oL#p(IP zBH?b16G;}kFDwJE*nw0V4T> zSc-QZRU*NF5bdK%)Q;gKyB<{{-UM4GDt{BZiylGRd>T8dMAC^&a~@S9;l8#o8cQn+ z_cwlOd4S}SG-@AJBHEDP?njk+B1@BlINIYnsze3R+1(@>ZSceZl|?6BJHLmcO2r83 z)k#N{{*8thj2%@X6m`Hps$@sTN0q3=J1J^p>Ky^X))R*8xRbGsgdu%*F}8&;ShAk6 zt%UJWC6e3T9T*=~A`G4YC?8cKG?7t0szhiqqkL3}&=f}XQ6<7tH4c*= zObN-o2{?czptjXE!LfaqAlg=IaOh|g9ICAawbOe~P-|c9E7;afHmL1;eed=6U3)lZ z-2sE5KZJC8y!*jf zmQAxwH{B1;a*+q{26jIqyyr_S(E)bP~zi+WFLPE&skroU z3MtIpbdh{u=$ojBo$O+D(x|iSIM+rdZ5ekp;uM;55!c2r*R?_QVdMQToQiW`bylto zdX%mWdLq|`_zTwt{Uz6i_zTwt{Uz51{gti_dXlaUk>|QLD5YE*qKa^B(39)hpoHt% zpoHt%pai)#L=AFn$OpJKJuSuw5+%2*25hWIO88}!)UwK1Gp8mA5zH zlneF3w(MN7Gg!=o%^sTy&_?MX!*$D7RS6TjK1EyhHFWaSC+U0fOh5L~ z`-j3(L&rz^8ah3;z=kwtIh+Zx?bF@x%y zX4#vCl6p7n&3JbPc(UxRH1uzfGxi|0-bSc>`yM2#DOpXWU%1z?#%)mN{O4hY_&iKZ z<8iNY;doe3XIK;Vsao~NpRSCze?^R01j8`b};vM*KDtxqo&_(%pe zXw*xsahItq0%o$x7QN53CKjo(e?{52HAcm?X2luSxSdAXF0*W=HSW_!*{yn9f@h{R z>3*Zk#llQufyFBu)yhO-*|Q0UkE=#>NTDD5Xj>X!CnGi12UedsR4b8fS5}`~WX=65 zD&~F8v2yX%DfpZ&qy2LqrK?KFq9#HY?0JQt$w!ep@fkJ7&uHeqREf8dD92EM6klPw zdWjevlfO+O^*t0<%VKh_Olep7qWX;|W%cp!F*Kv$C<>SHf_FXoeJ&BeA5%@Az%%{W zM}z2mjEp2DmyGmfJx95J0=$yozC#3e+ZT&LXXt!uYKh8PF0(`c?6?+{NquZqbv0eyuF4`h-x~LvQN3MdYr1?@l|7*I zt#Q9Ksz0N9kz_p1{)~i>M*fLe267u?l>JF}C&_KxY@;k4Z4Htex6&vpP-U7A%2XNg z0h9|;4u_C_yAElg;Ek~+SMQEiHOOTtSc-hSnyZ$42uafeaaH%psx$V;s=bmrrfIGk+S|LjTAyYYwq*%PLJ z8h_}YJ<<9aP6R$HwH&I*Kh|)ISGn-P8@g$6lfv;1h+O))X1A~<{Ga>+5%*!!6tA&5 z2j2n6K4Cp^ZX=_-Pg+l$+sApStXJjCxjoOrC;1{ zEF1bZIh6H*){Q{bd&$d-dD_FJ2$_I7_nm1mzXc53B2uq&$B%yELs2>A-D}mrvpzI&@Rlvv- z@ZNq@=u;~HT9KcUu%-pKyw=L^;aR@xMm>w#siK2*)w?%0Y=^(s@?9^oa{yhPp5hIo zj?>(+j)Zpq+JRt%K2K}os~PnkVU^DT2K@t7w0sA|>iObV*Ye-~7twSsd=iP|m`Eam z!$QgX0>QjhJFE9Yle9;MQL66|RQU)d8AES5q@a#v=hA9fDe@K7u``g*Q}8_-v>iv4 zQUM{ob~1>D(JyRJM{re(LDV(mTkM~q!Vq+cScz?-a0LqG z;Kx2%jom%%c@!PP7MR|y1kM;)EH3R%`w>c?M`^|*sx%X^0}<57imHrqbb?I0PVw{- z*)sb@udb0zAA_jE*L^%hA#B2(hhQ0;&~H==J06%I2`Y1G)thD(2~7PdEf|{ zwUn|}b>Y>R8&qds>j!Jr~t`{)dGG;I5_UAyFI#IpAjU%m(k5lJL2JGQT-sr~4f$dPwRS@v~Ae`oGTC=XGf zzkRXj?pg9;-_rqW+Gu(lLnJuz>#C4w89Er%&sACPQ2oR7vHQ{VDC>VWrhfW-m0T%C zz*+&|;gTh8C1k#F9QXxiiNwSQ9Bbri)k5HCpGw5xDC5My`MCzWlOuds4u?7^1lzH*-OIA)p1iciUv*A8b6vhZ22|Ks5{Bl+_vP#-gxR!=iN|Pyb1g#gT>0LP{h5Qz9>k@;2{Nc~6VH6y!DG!jxx3YA~fR z%(EhuiqzJo=x)pZZIMnx8rN(3pA)GJQEK_07pW|ycGYYaKz&E#)?B5RUtGRyLx&b$v;nu0V2f%0JaU(9?5 zcq+0I2whYtkj!NIgia^wJ6;T&`(MhWMbUTS#Fo5?mVQpvp`YVEHF!$>q|oDY$V|{wbowN&W>6tp2H4*8xmllIv_(w}1DR`d#ZqP^y2LDCJ3R zC!!Fjxe0z=$!)`)9`an6$O zoWMu^j{j&@Irh|~a!Kp=Ddd%J-cjEOC(6$1MrE?K{GD0EJx)@2-JX7BU80OBw1~hP z|1k-w$}7P&9_kx8L%99@;@L7Q#ze`$6bD)xJ=&A%+0gl5cZZT{sV&y_LSgd-<~i^&#e-w4}glJG10 zmt@o1gAh0LTAP1GHhJE;lyfUZKU%WtH`e^CM0Tntr`?hgQIcVl7|vvWsVL3yN==ur zKO{;=dh}s7Ez71IB-bsBX<04`$4L>tT6BX;%?5TL``2W5V(xxU*aTV^4S$8qykd7K z#%GR!$~BF3xM_9st`&8SO_BB6qp+^|7mFenqb22Q*WjvxWy{yWk^*P)<#@q+;qc{f zHl)%E3zpo^mWoEcq!smzE%?q1oJ!m23ugZ1A|E>$y;kU7AyO%zC2zQuA}>|begEP7 zs|4J7k^@vI8GbXsK@1Uo53Pd4se>uH+LOa}&U#GNCJ%aAGB!0krvvHq2JG~TqV3@? zU_;FKBiWKi%m%vB8$jE-aO9n!SoFLCSIw?nt}T0Z9#NJ(A4Y81YaaEQ+1R|Cmc7)ThSX3pbtt`Sws>)d|`+%k3 zuhfZ+Ul-_*oq`AZ6T`FdXZnNabQ~U<=phdecjEz$pBTg}*)JB`UP`mwq$gm3$c}{4p9%l(w-+zg77^MLy*<;rAzCHJgZcE%17T zpZ^J!Cw~!>avirTt0Rgszymr)#oj`ITSp|)|H(zd8;F${4O`!q2QiUXFcFD>ZG?a+ zf`Y1vg6zx11bwRgCYs>(&!erJAf@9cI91gZ3v5lL70y#x$Ef)(xuAFx2g^5(vc%F} z_C>X{mGnSM+m45U=O@j*b_1Quj;X#ExKrCY1T-#|vyo;anV^Z5b1E&?gQ~%s1WdD> z2R+Bn<5bK%;%RL8K5}`s5^~>E6+i7lkdX@HRUgVFJjm zkkoZE^^^W3O*?X!HhE z3q~;UV;{X0&`R)*Qw1?*MAh0vV?L-Bdw?I3MCDfFT$JDE;u0f)2sH``s`8Tpj=KK&aNFt?7L8N`i67nbWAw{I~@PHqe3F&ol zdP$Nlh2B-SrEzoPeta};HwAAzOR{F|or}f1Uvy{x4RHAAIusK%Uxn`Eyq}|aOHuSZ zk;;Ff19A3sc)(9S zec9Q3^(Ku@$puZ3MtW~m{Rvz~8GE+ky;J=+P;UJdH0!grd;;3jKh9{m8%kUO-d(P5 zAdA2@M43i9Whu(zo(*WF+mWr}j~C%(apltM^86#=(88I?qm$ z!{Z~oZk|KPC%=F7wp`&JkGTxQ&sU@SSq7+lyC`GCtz}HZ5grZN^ zt0+Z!lu?S}d-jM@6n_z=NPj6xQT#=eBK@T(MfxkF6zNGuDT+KdN|913N>Nl1QHu2B zMk!LljZ&n98>L7Iic%CcC`wU2AWBg_AWBhGL6oA*K$N1$peRL|Ls5$KB%>7R$&FH^ zgosk42O~<6k~&I}o@1gEDMLjm%10TcNY6S-k)GWsMM`*4ij?xA6e%U66zNGvDavOR zrRWuSA&JX$4KHgsWyM4(QU*mSioY^SkskX;DGs8RMwB9@-6%y$=qN=|QAH`zvk|38 zNiRy#NV!pplxIdM4zAsb%XU9S%wul?5e~sIL8OM@#b)u4ifu*QvSST}l?*dDBCE_{(k^dXYr^;Sd=_7C&=hJbd zi~6&}8CwxQ*a#on{nXRlD9+frf9o!M76!3^BJT&3hwV}%{z!=(DpA#q3k>&&>MAE= zj|2}h5Y?YXjSPZUXAC}pjD~uhyoQoZEt{biA199g64IH(uT5IE)4us|7Wu1RL|N7{ zJj{O-w+*hP4fIN+T9Lw!pMMea5n^LlRWlBxdvKFt)c!Ftht%xG{Guf6hR{gSpHhRN zs?LGjyBAa1x>5WlOg{mqWtwPofExW9Mi@SVTHZ)4ai>A%Bj|RrZbu-tX1#!{X^#QK zUObfJVPu7>uoqkBsGTZtJrdi{|7aVRBIc^_yU~cJi^826HCr4~iFUO3tZacp2~~wF zf8-~Ps$=d|iKD1G8WEACn&%=01n<|<-A`3g`~vCE(;^>JwZDwLpMLD4-+;O^R#3(B zL=|m-erzQX$@4V-9!jpHVApuSCIpt@7k>8P(Dv3d8Fy4q-c6w?ry zpQTLPUbz)_Hi!)NRk*DGM@_C5sQ50<@IVJb6@hJs2dz=t?pZ9R{4z>^9aD;rjmSk9 z)u8J940UYGmwGq|7~WO+L{jwb3Gx%!EwGpfFDuN;P|ZqQY49I)!Esw$0E zuSTOTR)5ax;!fQ~vC#!8jroF6Nr3ZaYz1(|Nwnop1Bc_J-UPok?#QR0JA0{3xLx~s zInX)4NeGO?r9!qVak8xi|TF}Qbn+W7aq$dah zS!NT3fFvf6PJxA6CWdr6rcA8gg~eTA6K#AG^(TTvg&JV56ji2w!?7j_s*>sNAw3y# zqi)}>{rHLp=nGeI*{eidyc(@M)l-x#tF=cp{*#;*$=%nWsM9JQ!0%6BEoqsElfuMw zqf(B_nnW>wmNi*NYCw=o9!SP0&W1{kj?Cg`Rq;D$Jy#YdvWaRLtWm}Hd0^1jbO;P0 zM-zZyogM%OV@BWyEk17opEt=GwL(=Q+0?B%B7(!69|UU!>&U^MFzd(-Sff5?^!QRt zkC-=ZXz7vz5_!HOiy@1ySt8b7%zJ}1Dr!{91Vsq?+GNld_0(|8>uG_mWcEarUQm?? z^xd+O;FSSDAMLc{B7l5M`u!f-2xZsPOdKK-mTwdhawE;M5VH1E66j1kZjJgM0#*CDprjK}}y{l{lO(puV4=62f4*fckYx3mi@t zP^W)OL!Bp}E<;*Eo##UR$ln9?9GEg2b|L!GvTI0cB(hD4>qo?@M0GR~d;=n`ROmoE zWZ8OEHjPeU=P|=ecA(8zYXrm!HZ3WLcH1y(d3?cNK|NIg=VI~g`aKgw6)kl|718H> z z%ZArhZEK29ZOivxl!fc?VglHysHp*6r}`@=fG_mO{*BXQ2hCM`Xk`CYG&08v>@rj- za2ugeg(?MZ7xG%$X5u1|5=3ZGLXJ&6By3o^YVqY(LazNL+J9gayU#md^T5BoM1aM9 zDKPM}S;(Z^m@fqe-lS|?m*Aey13&*XR<2o1-+=WlckNEh z%tr)@e@WfuCMz*(1FDKosP5SY&!liXC1z6vAAMIt@R4BdPgA7T<FF@G*c5!0WoR)H=a3jgF;;fE zAo0Q6&Ugh-4B68(bH)tI&ip!h7*Ydyn?+<}rB?014HI_u*HMRc96OM@9-~)+b>Qd1KFN4sXyjVx?Zb$QmiFKr_(LUnreJ9Lr~s;18Skr1k#Xz*P45Eck;I92X_DRy zlco`rYmYCciCHD$H_h;?G(${q&PEKpA0yEO=MV?JibN{S{W9v)>DZLHMYZ0Hsu&Vk z=~7{XyAw=b+fo%Xr0=gZ&0dvC3k%&y&&TQZmXE)$ zxuL9ch?GBIe~8(TK6ppq-RQ$la0RLqqAYuYM$~MDDEsIkh?|5qC{FeSy1n#a&^L!S ze;4#>kul;VWl#hPGUyia+mVroJ3hBW@i~!6>B#vla*}FbADm2`v5sf2OT-I3bXD1u zjVRvulw&2QKCl>|Sk_ZusMTQG6bOeTtJoS8Rt2PGBGaCcf|Feoj}5r0DtopyI7wxXKz8ydm6(J?v#5h%EEgzYLmE6@RieSHA+)Y{p=#<>KnpYlsw6L1 zcG?V8@fk5E5}rrVL@sd}JwAx_&`T^b-VqsciPLC_i=L(>w(JaA-6l$4sYT*pNZWe%_gx=-);F=SaPYa%WwNZ(_AwZR&ln$;nE1gw|C(w1XsuUrdlaV6% zXR355#`%m}Y7PB^kq_UTctzzQOg&9XJnusUDFkx*ZW-#V{`j7?GxmY@>0d$y%WT=& zw6$TsrT+L2q??xs`ikvL@c|%9{tg7w@vbw%2IX(xY&&Z=`k{Xb>oab{ANrSY!O4t0 zO!zNL_g(<;J!4yoL6bh~xhwynyF^oDTU~uYbJHIA#T*i<3bR1C_<3|6gi^deHSgOf z8_1vf8uI)5Q+GasY|o$iKUC=h<#WF;BK!^hR5AR={tQ9@$I_-M7b%u+xU&dU6ptDE zXdad@0ZLX9y;^YXGY(v;NW6pTeU%dUEF!jE*@{vP$Ciz`MNzgn$_W+ zZG3=rH%`rs`W^t#l=Y>>035~$@f*78evrf8u~B;;{$-)((3iV&vn_+L0v~zj{`h;g z?_+*D$S5K#fzC?1G0x{2>_>f2xoyjI>R6-;(C^Spi|T;-=mBc& zBvBD6da^rMX10;Y@&*JY5E!5eRB)#=On`>2htu#h_y~8t$&?(adH^nHzN35s8zt$4 zCn_I31^5_=k}*b!z*Md%!8FGLJQ`5cABSp#39~w5Jdi*b6v&>CZ!a1q7Qs&w%@s{> zb(YK`=qDjSixx@XY;rmhML@)qd@Hscd|PwGY^UV|V5&cPnC$J6WH7~am76?y7!g8o z&OJ-SoQ#jZ;i?th<8ylC)m)<0wamW!0r{< zv>-(U1_7qQ2pSn!jfH*%$D(9Fkp^ch>{~SEVgr7$fJU62u2W2di0Mg@f`Dj@y z+{FW0BX!%O!K+=?s#jlWAL`zVnGO*sVZaFP=(Xc&(CDp*Jpfb2v zXHeprm<&vLt(SozToEvWUy(i3ju!%&?|rd+;E&~lfaJUcQ)F<10|WsiYTkfFgJg&x zdV$(x%^M^Fl>C4Q067mPd<+)Fa1;;0sERp=`%+C#8fsFar0q11d?6e>R3gqiU$PBW zCKnx%kZ@U23kku2*;?r2XrVLA8|M}~mR*KRioJuVcZ4QcqKT0PS&z~M5Efonnm+E9 zjE5K3&*w;@M=nWb-`D-}y!bK?Vg<00{Y@7*h}dE ziYlFHkfH>Y9Bfk05KTRhd`b%wgAR=)inLf_O7|FEZ`&CjH9-1#w19>5Fbfrll!F}A z+)zPq$*<;6s7k82P(enRlGIR^pekueI$BH8G5v&9t`=61a8f%MM>(WVjn`y1!K0{& z2GLE@(qpm|FH;O6oT{4;>1YioUe~$ALkY3Kbb|#zkq~Dt`yiQbBvH9Q(c9e6ypNZVZh{@=&4I za?vpAs>ov)yyD{}v}9eVvZUMuLoJG}16?Yn29|MgOpTAggRcG|+0JkBWWZoCfwct9 ze5URpm`v&(7%$1>r)14fDY5*dc@Qc9=^2A#*=vX?b5mXX3N26Ws6#zkf-v>?CkFrN zvCEiY5^1JE*;xi9lV}ynvS3T8*t&E9t_0Iy-G-Ym#f%9@i%Z5Jj*$i#qunSYiBhO1 z>J-smfh7gS*da(k8C;TnsUVxNn$yQ=PKR33zb7U7Cs0$OD5>g9)OjAi}9EuUV}mPSp7w)G#{eDpi!&_0~-Fw8cZxF#OwJklKPWG zLM%yeB$fGq@RFz&O)YbhcbH062vj909*GY!xFANiiJ|Es9-*Yl$GescBV`yTf)AuR z<7hyHVH^$!*bD?)!^ac=*STg`GjX$nM02x#J zQ`oeaEYvYcZXh#&x$VLf;GLG^1w<@;B*apeum_UROq7&+kz)=BFUBr5$VIWS&%!dO zX#vIoj~PLBQavBYC@=}Lg-RT^c|s$WVmedmj|1+yv zBOjD(8(@#sDl?3RdTxpYv8NJA67&eJkUGL-tuHG@nFQukkC%j=>`BiUioQf?yC55J z*r$H;48j$vSiV$j3nbK3MQ@Z!&Wnwb`h{UmZj?qBA_FEulXH}zP#}Q%i&2qd031L; zCJ~`{%v6xUa(|109M3g|f=n6=$!@JCyS4{kJV9|20Z~zEGgqh#13X07! zIzn=osO;MRhl}B1X&j;L|B$FO1sM8GgQa(d_1qM>0%F(kFxFH1<+g~UtOf*v9tjuX zfzABhsa>`Q>x%Z^AG~Ji^{&tKQ!W#bLLHXXJdeRNk36IftWYNm|6pEB zltX*n0#5)J8gjYFtFLfF6kExdaL2nOG|Gl~i74 zj;l?&Y8K0lk%5gBS`e=^+elcI*w%glCAUgEDPAf85ISf`A1lZ;;GV(CrTAT~H-$9@ zk}>*PEyC&K^9eZz^hT4r+=NHZK|!?6#15jtWkYIph1@l-1Z^m4l0>_KEJzjlOcyq= zMXf5`G~y%WGon`AOsaA<$y~`dFSuk)iD`D&ez0dSyru=@c|Ople8b;T2+=sDR$#kCnd&|VxB0)E?F~NW=_^( zH${rwL56S@qEPx#Fu@^4iJ)@No+zcTAtX^<+Y^=WP1m|~hADP4W5uraqEH(!YIdxg z&Czmpn3l7!B9dGaa#y-}N5;xisN-6$Nz&3fxR8g?z;&sXhg$I#w+4=71GnMOw>p;A$8 z;)();5yjHZ&@yr+xJSvRS>9w~Mw#tRf=1Ei2of_$&XFA`i3VxxX@OcAcyd|dT%KL9 z%x)6>Kt>Bx&|DyK7HEkhe6wU*l#;^G=7S1(VvQDhz{d@{NR6Z5E%s1O;4jvAra_m) zi}$5cEH2Yxak<`6RwQ9ZAz`>u%PL4;(uqrqE(E4a3DfY*N+~7X)@8=tQ?3ih6|0fg z{{$H?kc|ZuEcgk%Jzg&R!xw2VGeu4`H&ghUkq=7>SZ1?zyVXpCNSXPxv43?y_2O7pEH%oBN-zz+&)C>rr;renZ z9!2dDq$lcl6jN#@X{nj4#o7SkQ!I%mKHWj2@Kl2+@i|ac zEWsv9Nr_e16{54hDj6$0J=%frBw8ekF)5i-`ctA-W8)P#vgm3q0K3OqbYti}&tOZ$ zt_-M02x+QeA-5>!zFNwc-y z?nnwPRzRr7N_@IjgLNMMg%tHxfRaLurQS$zq6;lJ`-#O0gACCw?7>3aRQ8{j+B21w zi+%|~SE**;CMiv?_WF?-T6nt3surNqehlQticf&P*^{@#s2?s*^|9Zl#G>GBVGMww z!4#DVT2ykWV19s$8$%A@;#NyV!bcmCmB1V<1t#2T@M*g;GF3@cKtpZF#jU%*tOt;; z?jb%yE0>vCxy+KvB}q~lyC|gaKp{O^c_gPc4JUAM5vR7dfL=HcM3y9P?IgoIVZZa1 zmO>Hw>6znH7DR1~bkUXqKtg;S?=C~H?xBxt!b)0AHbkHHm#H3Nz2Tm)GL%v+S`^Wm zYAL8YJ}Qtvkf!V6-#4Ey@o~R{UGg=bUB(!1Awc-Wil@#s!cKOioeSbL1nVcpfOJLzMIW3?$ zEkSacXM+4?nrhVUKBZ@9jgsfT5V57mVk|6r+e=ZcPMC_+|Dos3q1JkwG z$k1E{&kPZIR;(V9?P(f0vHa)xWMXv_3b{2jmytk>t8y5pK+URj4s=;nvz*}DT#uzB zLxSy;j^ZgaCI^qFgjPx>NU=20q$$~rw!{g(p6pSMbWOV(I#d{Kh*yjRA(^3Jn^OdB2ov}ja= zc;NxouW}4EjGY1+xrG6abfZKJC^biLtk4{#8B*(xv3nE+MT$+yJJ})pN{cgud5~Dq zJIM&Wn~&5chEZ}+ya+3U{AmlLWfbI}E6HE$i~WVD_9~Io1SN|dOeteXs_+3Kl$c;i z%@f*<HE_lF(a9RKU)m&k>BtDrhSrF%J&3Uw~DZY(y zD8(t3@h&AbD=Z(OZV?fJTun+AyI_bFmphXJWU)fJYPrNnVgm6SoF*`u9KCa*54?Eo zM3Rp_h2V6qA;7yP=J;}SLY!&k6r50Mnh!$Wlt@_VcTi}(F?hKuMN)cPV&6akH|aM} zTy6UAlPQvC0#bNfd`naqCt;Hmy9Yw1kf_jVv0yUeJPK#^#WzIF%0o3P>vzxGW>S)< zeH8r@5Zb~A98nT3YEP17o05#&)9!Zay^SUY113k%1L8If!6jH?l-AQn8zlmeFU5 zAVtXf2ic)HTXL=vknwWE70wVEhRy?(IPN$CRago~D8VEG;fmG+#L2i-9wvz8OZrz- zG7OeJjU^IyhUB1Rtc%)(lO)h;nIbR@!yXN`*60#R<*lYR%C;wWnsxnQqB`phjZ4tM z6=Ko==1M8|;i0CZScTp(Odqvp$ul-yHPel1iAf5gyMa^4zxHYanY}Yu2DOyDsM3hEA`K*M)D0sR7}1z^h?d z2fYNXyk*^J&&A8E=J}6S`(<;e2(2OI!t>N#c=dJj|w zQ@eUZzhG)lvH06C4Lrvq*o&JsN(8HU?~=Gv1%hLkE!hK|@R?#HfzLq(2Lagz7Kilj zQ7u?pXuDQJ(#C?kjOcYq>v+AD9`?A#Ne?ga)Mrdi(3MYX5`LpZOgo@833}%(W}oNg zK5qp2%Y{vnN0?+y+9~vQa~wb(eqpoU)2*6k}L!+ z)@M+$1t)p02J1}_{)~74FAf!s9UBB7NO!x40^FY+)b>H=Yo)r;b~wUFg5T(+QAjD0Q888@Eu*}6eK4;3 z7Pso!h#R7=$D)zi0>?>89xo3fmKW%lbZ$C zdU~Q1q#t5dF_ElQ-$6>@6Jr|N0X73~zt;SrMU>Zu5I59ATw1^FKV55Kc-2O12j0$} zr8Svst&+jmG9W+E`jXW}69QJ=qzfbsx{zx$Qm)-7b1i6V8LigN-C8^bkC&JOuZF~Y ztlx(2DBK6AIxtERuZ$^mW0q+o zNN|k;0h>1r5ZBUcIBFMAFXG5k=U9Wj$4L&u%dUDLx!$;fLw64|tVi17Dh_=lSDO#K ziPCU6#XLZfpfg#9z?aAgbHD5 zMd-dKoyD8#%DoQ)hoM!^O{$*y0uGleFY@}Ttb<Kf<;JB>nm#nl;+tfUP{SOYrsCtC=spX%Ps)yL+-e8X{Y}&(ulz(a?!2} zurDQb$csu+47Ontp=)d0qvUvlk4&e9$986Li$?-P0Q3eMIx^i9MA>krd88>gCPqI4 zMy7x8rtfYT{kH*A=gZOOh1l#Yzd0sV&n=1P+oqC-!AI z8EqvQ;>`|li0YaE*%;Cg~pks!bRKWMG_Lc2xSZx?uov1DowdR^HURu+*mB zh2#ixZOtoO45=n&J6c-b#z-yDBp590MJ{al=#t>0*Bofg&BfM%I(jFKRlPMoi`Y2Y zCKF@H!90kelzf|pB#{?TxFX~tTddd4^l`?nl-zgdeQL#TF*bsj_uD}T=Jo`Kye1;G zIl>qti3sKx(!j8@O7#RwE(>U}u{Wx%2AioY_uii#SZB!mdz+Q(AHFQ3@I$MY(gnES1mgTpy^bZ$b&AC!#1l=D8@A~ za`!8U7cqao%0@!|L!#N`#1MsPULYv186pZZNC|#*wlxD`FA5L~jOSo}}tnq@@2=j>h(1S^$9*(}uV;u>0 zQ^1&lXS6{O>OE>A8Y3($?gR@ub798dIwZ6I0YwL8lGcQZTEkOHl-BW7Dc#YiSe+`z z-)7>Ow-GS*f#=+5TE1MO^@ZskMkVnXuM5fZLVo=I7E7Mk`Det`K*r2i0;V^bXT@fj z`q+m`OjiU70@Q{qwY3fC$<@Y1=4^5fz?$W`TVsPnJRA}snWtE+ zlsd(dGLdeOlDCCwVuMHb1AsHJ^}l&1BAn0Rx(RvxTlMc zDPLW@^=EOyoFTBdM24D6qJa%lThT98%8c@^= z$)2JmyLWAdn4y%R`q~W0C)o3(f|=Ui>-OHg9S*R9=987FuqJ*6rGck4zQpZra~8_flC2fA`IsTZNveH_`9xSp{`_ zw(g2V4JtGy|rNZvo>&mU*~md{_Q# zRo65j0d%$0?b#ENkC*~dD3Zx7n{g|7(>9sFXCK9t=0L*chB}$o&{)5ZV&F`x~m&X!^Uv=m2-6i;n@zzP3^&`ADC$l27=;3dYmV+jiA$k@B+ZADN+h?Lr z^Gz?ZI}h;oZ?k{1Bgfc-2b}SCXg^^yRP9};f{O7Z;V z{rPNPWaeGSI1^|^#_|2FEUAJ;BP==p@duB6{czV~sAjXByqy*I z)nEN6OX_@-&$^@zqkccoj*=t$`&d@rE4A#X-O0KSwz4-4be0c49j=_k5_!ISa{S-{ zsIFLc`tasJT%kyMd;RX}f=F|{r1jY@9RumnrY(6h^JfrEeq{Q`7jrh(?V)djSeEPp zs|5&fPdz>cif7OveVj(n9?_&pG)TKdgJ+CiwXG(KM))xws%r2>D>u6;8mS`+#}9gz z#G*#2mjf0NA4l@)_AHc@6m_8zdc}8rHxserr%u&JZjnlQNDxSf6!TIvy>VZsbMMkEKudq`GBI~-kx>ye=YbqtZK%dppJB5r*y>VtX%P$6R0cQj+t_8O zy^3mI%JbR%b~is!#n1Ef;C*aJ50A376>NISPC z7ue%AKi9^tsNfxJQUz6uRPb7sTG7TTDtJ2k^1+Jp?2z4a{H`M{Y;fo4yn?!yUwq(Q zmeSpeZ@Gg50<8f)o|l8{yADJ^_CL4t#WQi@n|3Rn?-%($v-59e?^rwyjeO`hiKq4Q z$JvlGY;UB4|EZVPIa4yv4$9ZtY@kUy1UrJPIqtH zi8hwf`cxA?4oqbCG`)DCdDWp^m0!7$FRXl*CAqjQ4e+t-_ZB}Ty7>G-UO^9^Wp~)^ zEYTTfN1bumy%+ez3(=d}HiGgh_%SgqZw=IbK|U1)o?$gS!uEIaC>HM-{y>xs7TvJk zgTQrOH|jAqn4c5%opEUa_U!}b&}$eoQ6oQngLA3vPNfxO`xP6+_Rs-jvqulo?_LLp z{l)=)>NKE>unecfW^W&GmfGysfS=uU5WnuAU*jQWpJyBRneaaL5(aQ)rLq&(^HabK z>t@$dsWTePhi`O23cUgDyNFm6+xkU!dP6LJ1R3f{8X+285eQgZG5HZiUc59@A`d-@ zuYN(4;gRH4Zgw#}SZum|A&)PqY-|p*Y+l5+w6f7f*tJd+UUL`Q!;4BTlvGY%SimxA zEyk9$y~r1_2ru3Aho3m**=$H3+nc`(8{eLdhu;is4D;gJyZHH%%3BJ9_n%nveX+Q$ z;y1%L1VKe7LTm)qf3Gve{u;ZI*RbSL+6D7#_@P_)I1ohIbL*(yGps&x;$~-lmeIu` zmfXYE@^igxwlmLW-#7?jn90xZP#zYrkL~CA__Bv>9})WAC79<$mhdC2%HOuL(Pkm` zntr>Rr&+0u=i_Z}-i8*t)&zjJ_3e$;HSQ$+3O}yK6ua@6`=QX6Mix_TqKK<6+j(hd z_190V{uFB{x{+m8u*MoT*qLu*6?s-(sJ1ZJHk;36L$CsSOWBZaCqMl#U-?*=v=}=8 zLBLXa_(BM#_bG!VLR{wt_>7Vbq5BT~in4wgXctv!bF`ZtZ+`n|+3WQ9E5uphPk>|( z3xw$RXG0L%`TS{qD<8}6=3`&HSJXHc;1iBDF68gF-E=r%$yYFBpONAi0w&KA$ zmLvg_0JI4J+E_g&fo0dxFE)jXD))u?1lGjQIFqti^c4MG0D3-opn|<%L*}16$cvoC z>FoA{LhgNykE7Yx{Ek3ppsQ(n^ZV}}X1mXY3d`D9dh4x#@wF7*ir&B61o4IBnG~7I z4>35iZb-2H7`*vHDkMFuEh#g|D&F|buCFkkaO-GynIPoM@ zd&e4aajyJ-La;(v>nBxX6ia~QDwcTuTP3cc4~oaC-POA_-{CupQsTP2h5=l5#B(eQ z3w?63;=&&=yQ{F{s$gNk*@(Om8eeLeH3m^hJP%3_hSz-lS!AsvG>ap2`?jucYEV(m^ouCi;LVK^M)gCw= zYwTp>c)K$x$C;PO){^c!7V0T$p{H5Sbo-Xe7XM{&IIjS@VOJ$JzYipR z;%3p2+<6MPfU{78B4tUp08 z=Cg)UmKqVii)zc)hc@oy&5f_}mw9$uQ$b#+5~AhN#xQSVpSk`N`!nlfw_YD%??Ykz z)b;I1w<2AHzq~Yj)+x*&X=6W)0}&e@!K1@!`c9u^|9u^1eXFmN{rS2G{yLZ0c*@69 zPx#f!>K*r=<=+Mqe4>)I^so$~CWozr$ezvf51(W^@*yCxo@*VrQldl}%{T>3$Z@7* zvF}*UOuJ?N;es|=B$m|I^?L8S7oKK`=T08N@?aOM=)dX&JtoyJ(UPP<-2=a?`y{2j*B!pPI6+}(Z)jm`^!+7>6;u*r zj9pXL6};&&zUN3ei}tbPqLC#E z?PQHTpy|pJ>@p`0tcJ5j1#4*Mudzk^99zQEoV?6K!TH5(P&=P_@HJ4#xen)&ESOQk zPF^~@<_t@$VcD&06VKh%HuatDYFJISsBRW$fBIvi-Bad1g61de3H>&W58oJK*TR(fB-tC5 zsC6l@L(a_MEWNuNGIp-b(reVipc=t_XBICEv3;dW_M!L^n+>X9kw~*CvY~yHb!R4ji%p8KtJ~j;9*O_2fK5M>(NuZ1PMj*=vd-Xd5&Mnh zOtWu3y?P(9BslWeX8zAk@gQd`Fh86T!9V%2F)t1`LNOH>jnwTX>j{?C(~AYIE3*%t zV+q`#d=sO3XN||XGT)#Z!g+h|VtTOHJ+{50q1c&$i6Q&h6~!|950-rjlH{C4wzDrD z?0)Q*y!`#9mKp#0MSf#5-?*Ld!glwtwC=8(_^gUxcq4!5=6T1F&DawMd8c^zp~Z8r zdi`N%Qw~e&3D$-;un6pWMQnd5B>d7A)?5MByLw;a5k8Au&d+qQg7y$Uv>|wckA;59 zd)Hlk*&J+g`EQHfUOylX#f&{{^W2T)dkF;SW?f&nmG+CBQx}7~-fApsd#h~0!kte* zfTgoRJ*=sS4Ju_19H?3S%&*xiHjIEgjU7ICicBYOO`lQ6iwoJ;4;Hntm#p?Oeidwz zWSNBKFu&)1_V9sIWiX+%AEB}M44&~^2md77-@}d^sOXADf5Yo9MA;ueGvjbTEQ;{c z>~ja5SrE`xgbi_K*lceP`!uxbWM_%Z{$$bq^2vkPRh*LH&e|dD=a#e9W)B@CV*Zik ztg+cH2y18jAeM>^$eEZ9af?oJkl9*1@2U$>9N516O>A;a3BT$v=5<3j9A?pqP#gVx z0%ot!t@~zuzIbXV)N!P_4FcpGROq`%>NHhAD6yuRyTez(_V88wV~ItqCBHbdk5xkg zVoR@?w1Dyf^66!4=Q$wA*<<5?bH|;BqvtQ+=lrp4l_Wm* z^P=3HGuR#9!#FB{P6v(0KN|^zo5Q}thJ4Xs;v}XDKyD9fS=~g z%EbT>W4K>C18_jCA_0LByP>|R zprL-(E+Z2)x7SA+c16jpfFD!ND0wB0&YoAFxf*j#Wkl+DQMU|yJw%fC>v z=&DtP(Mq?|=X|Yre)_tiV4E1Ck9{3|{#f<-hqEVdWVvTvUU5|$r-P!ytN$?fF#C6> zuPwyxxuKQ4YxRUeP*3rz2){mszlp7(Ap4ZvekK?W9b(^d&LHpCtTps<-onpc#YT3A zPDBgX%XVw1@=7==aIpB)FQ@(*9vD6u2k=f2e2zP6lMHPLZD+?Cc_|MT zFW)(b(~8_B48Ff%-SRnH7{ow7O2}uOP-_33m4-v?zUy0IR(yk<1FAak9D>0fwQq-e z$Y!T}eVxVO@=)EzP{9HIO_<|P*u3b~vU$ZcseqVT;CR=~LD(;FJle34wX}2WA&C`V z<{7N9on`Wh(z?(XnEH8I=j`Q+!)u$bY`eO=t$;PO!Yehsy>kw>nx#5>XIsI~Sp7Ma zOyi~ZgFM2)!rDrfTFUmeI@2u!wOfNYsFt!_`5iMtB~;l7@ch8(M;DY8>|;Ytv2f2d z?Dr0@`N`(R4Xdx2y6Z121$zTh&raR-X*LoEKAyc|bz^h=&VO%)8U5xC9Co{4V`&BI z|HEp%Jrs>r*5(z=#rU6XIR*6h@rn?wMN5%Ll;XLgrJXq754<8=Rsai51lB8TEG#h} z2Y^W1=h)0Myl5^ou;QCvbMiAzNRvoS;JV&haCpA<6l*vG`mN#n<`r+}M_5wpg$s|d z$DmIA*s9nFEu!@>&vfQx)v-a?eM(sijrl@z>j@gPH?b9|?=}-OJ&CQ+Yn-W>tJhZ^ zLgqJ`Tao#)sPMIB$)ztQ_EnzlXk#;44?T7`_(#GQtW@~p3-sW(IOvTNxqB!L2cpQW z2=MSp_9RyHSS`azahlB@K8V%*FUu*g@Bf#&-V2A|Y+23rwDOWr*tsmDys~<(Gbxkp zL#1nhaDE!WS+yv9Ucb{maaii+VSPHnap;a}5v`{u;<{fA{&kf&%QQY;vEh z5!^5{SbJp{z62^hBZ^0NU-(wAsh}iya%0;Qy@j(XdF72n)~OZfAk41qZewFwyZ#!y z@E9*>It}OLS)Lb+KE~6lgE*3(-cb8Wu)5$F3LpRc{HjOT&~wyX?MYc2uX%(GkIxtupYda>k4F|hQ@^l4)WZy{76$&C^)C_X3hy5*K%1}Ctnqf zvI(7RQajJ$(~76RdUeC&FvgrZi2Thv2>mkqm<@ zZYPOc(axqsSYUhi#-FMbeh<_df|p`EAJ3C1z`#fkdKE2;CE}MOvc`}+JA`$hc&liyH5+Z zuzRuj^$8y?oi>NS*2OE;_OiJ%q%1U|rb{vGx zm91)a#-(E_Uph!q;58f>>A8sf3O~2n%d1x{Y&-w`XYcyKEi1s1JB}4D;d7rWr54ExF-MnA}c^tquu-cZgQSH2J0}J!g6NRB2uU}DK7Cp2e7}^O#+OY%O&eR+p zdgl8_I{2-j!rHt~@Fky=faWd4OgqpafALE8SEx;2w)^14hM}v+nUHywbsp$sPutFH zdktG!#DeYOcTtcnDPsR(_1y^%S{g!JI@$l&-RzDVARhjWDzmc(`r10!7wz_2$o`jH zT1bCVN?D}nJe=&MUC!i;E7{O9{AX+~ESQfLhIgK4R|9`fJJ>JI1FdI)k8j*S2kD<$ zMREm;F^HKJj1H9BJM36+^@7Qw|*&si0iXFCFoeAmeO-$wU@Wc#) zeo#-rE3hRV=BuVedzm^S%l;r!9XHTY zz3ZGqz1we~Jr@P59|^)_)zkG#Eqwee?HnJ5qh0BamRHNJ;kCWch~3C5rgpy2tqq6Il#FYs%a*+@|Fq}==&Ogd z)ZEXHg<$38+q&4bHMML+=kbQ^hYNd;mBFvoicPSi?C{xxu=4E(+L3ny#KbkK@*-rx9NIts1;+DI42s$HAFC-o6 z`9KY_pWhEB!G<<=+rd(t35w|NE?)c0)3%gu!_${*8vlx4Ed} zE*^g72S4Bih2b4+8??AKGIYcJA1b>f#O4-t6u|rsZ6K2jjw=BM+X;wUVc{-iE3`EaBv*P*hUI{%6M&K_a8R_I*8xRC=?)?=z)?Q1_5ndiFV7t1( z6Hhr4GM<5-tLxqjO4F;MEPCU zIVk9jFLwS-c!Jmoiq3(1;OOvp(S(TgGV{8vl>lhG0n( z)`ys*`p4RG%)RTQZ$BS+1mE1$RNYA7VZaa_wXHjf>A_-mWY}wfS%*BT_v67g4Zi{i zqPuYa81@33H^&-hEauSgW>pu2YfCEm*&y53%0~9Qx?tfuwT_LaJA&1axpp7F zmQO8N5)G{i<2cZFLpM9(Ks|luh6;9%!_yEd1uNInPw^Z`w`0wm7X1ChQY1dvTpB7P z_5M?k>fg0mah_QihVyynEuXyQ5JmsAewt^Y-kr_7HH2!v7p;yomx@MjB(-m2$=!$8 ziG!zZMy=mP>D>6aq*grtGAa)O_aybPI}UW7UCRqT8#=aaVL|Px-r90VSNJ+U<6t}K zyP<}C#epV<^U1~@w0tt!O+%d*L*3Ub3<=-k?F-m*PAgx`rzYgxFIO)iBO>NpP{=Cf85uUO6M+CRgFmA?G?%~7_Y zB3Kd(=LKiNi2|cw6ykeIz6b>1>sVDE9VFltgvJ(O!)w|u@FTt9CwRu`!st#c0OL5G z_!#+w*ljH3RKsyR!D=FkiUJq-OsRu)2drq#;shRk`}>cQWlnQiPXs|L=38hFUg zzY@G~_C;@EN8CWgzAYL9k2#?5l zNWtScUd?0ar}&%H3ERQX@$t@-baq)MTLv@7+o*E)L7}s=nHA)N2ME~UrZ|&rc2#E^ zyXSh|zBEE9>n7SVK9@q||0~tzu9QePcoR0M_vSB}b-uQ3 zO>e=5nOy~}xf?s3Fm$jzJvc04pDXAUZos{4@F~dZ8T(<|?z+0IH`s*X;Bu;9-N_<(?9Z@JeUcR+Bf`GK$Us1w(EaSq>wDS|rq}}j+Syyz!!8cF@ereE z%(K^bBO&=Z(975C1v=-ywiEaJN@p;7s=hvM0y>QGEu$?y6EEE#xJ%DxPMZpbW7?tX< z&4(Ljv^`2(`pT}-M}e5f)8R>>;LEeS=rI1}^ho$n$6KuN9D6d-!&@#{1gp>9;s!+j zbakyowZr>}Hs4QZ#q+23QIkIQXwY`Ufg~2D-;8KJ{{FvNJO{G`!Y-fCCTW{NG5z_tN*dHD1>)07T-f>o% z^PBeX*=i~Vu4&voeHw?%7~P@&mX8zZfL3?R5*$l4@H`WP#2-$u$O7Esjsnq=|js43k<?#Mr$c zvc@X-u<(gO5$r)Qd2gX81(}~OAQG!UVx`r$yG?w_cccwVzEd{iuXH5az-QC=5g7Pc z2mt$IpTIeckO(C-!xspyGh!Krq@(>=KM99{7=kbRjy2Mpb;gMJPUx0?c$mN2CWr#HOH{ z1@)abv6B}rH@-?{^{@o3mX&LE3U*>W# zwxV}eBK(ula<5e&Mn>&pr2l1oZxveM6S@8WDW><~fQgvg`2mIA-Y^b)I3KEH;%6bA z+hATSqmaNUGYBn1C5G1!n`ses6MfXiMP}lbf5ZgpJnN zqgx7(O>TY8N;uJ0*fCiyc5IS`6TW4QeHWti(P<>mUu-RCoRM-2&mW#fGoQO!GndQ3 z|5*uq&WW~VljVMiZ^`Ge?`@%_$8$(?*7QlhA1RVfyr$%rgc^H=&qV|TDPi^MxbdYJ zuqi{VKww=aE~dq90WFnJ%SqS7lKsl_Xz9Zfb{Jcu-?gx#E_rt1p|ZkYcG*gK0D@Lb zeAbu~cNA8?EuBbgzoQIsRUgLuFD)n( zXKfbC`o*Pi3`+W-ZdG4Psg%)>)fE6D%W-+a zWvM;qw<9FU%r^MY-b${8qc{zUSln=j$GycrRo`d)PiE6c?X&aZKjuYpR{_nWOxhA` z5=Il-3dOdK?Y-7i9RB#5kzCnvtXFK=*t2hoH5R}A@HC4ek>7{s_wfd3&Ry78Z?!fo zsKV%M`9oV~5)LchYO7pU*)eTq`mvdT@3iI2fZu%$e({NA2s>Qd-zHW!iD}sT{BV7h zIc03s`x#l;Z@!PY29-819A_m~-rLn7&h0s6CXNvcEj1f!#s(&A3TWCm3$c-w+p}kw zQ^!<_1_VE$o52**KjDj3M>ah5PHWc9v#L78>$h#T7T^rrE;QvnbBa}Ibzm>mKJnYz z+E0ml%)LLyN`A7a!S+=sS52}==odAaVoZ~HUBdTdEK0QWi(lT>kAq;=kHwP+>Y%A> zs;oPR%;&61bbd!t$_#Vnm`d}yaiYPJTY$_NXJH9cK|UN7jdIf&#|nzJV;_=OVwi{aonOOveNWWk#e?1$y5uxECL{JvfwJEw87i*E3w|$zx&X#t=1uH^3fUA(fbHFop_?}E%awu+rL>)@4ok8Im}`O3^x5h*TVXi zWmZTIY=~r!rpW&D)-iDgc1<67fxfCS?MG0&;4gPaFyACl)Swj(` zL}$UZuLC1SHx=%CpbJhKX5`kYedZaoRymPu@Vo!24R#$&`$U_&V1CK7!6vFAoV-=@ zLXTndfJhhKvBx0XZFTYJSY14@)kU&0R9&WAD3x!g!_2Yz4O^+n9;=7Oa@xOzw9DAz z$+p@AC9Sl!=y(pZ;`Z+f3l6%68q|Sx{Ngh2_PBy<=7BQxkq#To`yd7%2;8SZ2(jKb zN1k2$PxUzP%vrvi`LhmAY|Z&WV&bz)YeY%`o=;6&kZpw~`m@t#9-N5f?QHRe*qbe$ z6MHEzCJ?PLFB%X%CfT&(A~WSdtmm`E@L|QQ6N6> zWzsClw00Gy94%di`SNC3H_ZNiws^(Zn{B=O`KRnZI9lJc@TP2R)}FXce`CQ%rV>6c zwyoXVmUI8UrPHma#3S)NTf29zOcYH=KKwm)#b6s$djIZ{s_Y!=j@?_Vqc~w$hwV>2 z_2PJQyVY`IYU7No0JdR#Nj62fisr@RNL4HfpZa7-PDbiN<_+U4|Ls}Wf^H^Gn4g1h zqF+=}{5o-;IW<9i4vUb9e>W$`iFLH&baEVFfGxj>me#~~aH#*-La_~pus=kgW=B)s zAw&z7(tPkAv4{&i^(U*hT$COG%$ERj0x+E}nBO@t3E15G_h6>j0)_uL*hy#}Cp6p7 zAT-tt>qJm&YG`k>I{y8W{L8YkCYGRpc)j+>Ti8E$U6u8-E7oD5w7|UV?BKmSs(#ho z2%EfgD{WzF!OA%CYlOLoM%)n@_#MVW_`+GB^6m6)|iY!E9EFw?5^^`uwm6) z>^`gWuUPBMs72T=Ah45q3bA4avEq(V{Z?0tl``XK#>(Fy&e1O7a9%w@Jm0d}nwgG8 zee_)W8j7yHKbHKL2iDL;ozvv*o*XNun{-C)Sm7FL%T3F&t#g!!*ISto`#lzx;Sfcg z(`1cK2_Qb35|BKoFcWdi_{SSSOq*3s#5{u~pRN{+=QEb4XIoEcBz(!4W$#5&QeCy-NyHe!MDcSJv*g#Y$Wm(IXN%#Vco6 z1*bCn*dj&~bCdQ&X*^C@hjz8jXHrJ^mzoN|u+yspQ*aDx5xjaVGi#M!3IxAuwi<&bHL(oSn8bnvcu z{^x=D(9JTI@?0GC?SY$#jOVbNN@;Q0Gw1AB)_aE~V*-iOtKIy!KN`5vtq!N7if6t+$!r0>M( z17bVYDYJjPrFo&1xARA0>zH;cA*UW|`Peat-RaWb5D%AF?QoXFKhICDTwxu>DSfHA zSf?XOOzUm=7ZLX(R#&0O?XwDT2&<$MUQ$(;IqmEnJ5Vj{t@!2nn{i^K%Q^}P=@MH@ z4p8Rr&TsD!->d0-I4@`Vw5jH_bFyY(_u_#gk5o(Y_Qu?Qw5=N!yXQlk^WIvRH){nh zc35&G$NKYCE#l9kDdhQPF$vAnpC_StvzQ`I-~0UDLkDSd-x}%Ki3!Oc%)~mwXzX4{ zt691K#;u|Sdz({mqAoKZyG+noK{^E9L19_(T2a58#HTz(6i705QfeOkA*Rvd?tK|D z^k+#25*uHTEl4Ltkf3&3vmUB?`3rEK6bGA0S$uT14Mt3yKZO8AHMxuI>hpL^0PI zotTkmy^bvhICY7+&B7bjT9?8GUc2`Fz(MP%Shlx*r8u`wUai=D$W1qNt0yfda zS)DC7mALS(CrQB1%zUrXyy#qDHUDW{fL%GK(+`plWoEV;A9w9Xe7^qpwi zdJr24@$X*z6In;F38oUW6xy%uvvBLi0nm2@{Oc4uHqzdVLk5LleD}pP#aJH_mGgV8 zQ_Cqh--`8U3q!((SKWVqrYp+K3~sy<98%voc$V19S46~LUU-NL-B3`{;x297Wa%JJhE5fOZHnUz2|Es5?Y3s3cS7t$_R z47UAoR^}=EHZsQQfh#peC2=_hc^%07%u+O&Quv&dQ-_o1q?})$oZOAlr(u3K3Evh- z1+iibS&7qNen{LYlOAKB^Z$<@Nd-@fk-P;J;ZIBx>8~cy7b6-~Y#AGnk^QgzeOF@m zFZoxc2`9**Aed$IAASCUI?D`8lcbtf!V}g+3U1=yELI68bt+|9t(L0~;s@W?=nqMYPtGm> zKl&)GuG7E)AA`gQ`Kuf^^60U(l?K4{z1U4q33V^Hz7PiqD(RoqEzZDJGV$mcbTIIq zlFb-AK02Sqw>wM7Df;02y$f2}o=6m5Xz8=Mk^Sd2405We&J55n=pu!%uLtTB^md=TxmxO>Te1ukUCtRzDVk2LrC6LivVQU&ID zNpgSx8Y}tU=X+0J2g@$8mUdBFh?L-<+)L-e2|@$@SR!`@?mQo-z%#K@H4AyaE1^bq zo=;xeuS&>k+X;_iRC`r(#_cn2GOv<06dw5@@j-L{RBDs-uXmi@Z}sjnFHD&A;C<%x z)TFgm(pn6op|$DFYq5*`Da;nELs*o%_oo6qBT;!DPq<_?U) z&u#2%CinVht=49%YY{w?&?4Z+UgQ`vXIxf!iaBR&TbuQjYph>hPZS-+{;~(&N6Lhw zJ_$P_FByYP9n;30ur9_qi7L8tXi_KSY26iBUDIHRWsqG|(-HP7HjAa1;#;E*oXVI@ z2(Wn(vHOkBJYI+M5qrDD?X?wK;R+#Mlqq+n^@*B-#%zqe6-dlcw{J`_uNbpTJP03T zOO93ZnzS*`;_eSDVpm`T5nR^ph3j#UiiGbcYsty~P6Cl2+jCKZdEJyuu%bL2Y9ts^i7@Rrz{)d){MLk_vr?8FLylg`6(!{AN9uZ?YMKK1__b`uq zL{xR|7WZthdS079%X)^w3{3|_D*65Gav#x$XH2>64%`$a&Y6O%2`{>(=DE@Id^{MwFo-drS6KBC0jH`&f7Pz3)hnOiFiK)0VYWT8BjTk$iD& zC)Q=nTe1Cpt(CrIcYapZg85llS=k-?tV6#Nd#la0v=D_UIChm!d3|~o=67e|oGqBJ z6W6FsZNoAV&ck7XZS4}1n?#`LoujxVP2?q8OOJ{xd&H6+aYfV7V@KCK*n;W2IKF}Q zW$(hlqK|R6)$JRa<|2&Tk5k_l`QEXlEu*Q>k3*elA<@zlvf46I)^>>}N72sN%f`Tj zpi^>4fFZx^9;peRjBv+LV3~Fg9;_!knw(o-U|fkC~VtM)jE&ofEpJQoMFLZfZ)L5vs)I zg(KKHC@KqZc~eu{j1c_B@-8~Vj19VGO2R?$!`tXChcgg(ZZmHf`x2%wjZYz1gVV#C zZvl7zdj!ni)>}H~=ZL?L=n;Qgf8-cUB*G9teiVcALDJ7I@xVx{iJBlDGtH1sHpiqH zg?R)0Nu@uz;vF0nc@#L0wN!{FvG)qGi+!zqm}t|sE;>-WV`RJaJyDLefLG~SpUz(K z6<_kcdlKPYiZd(BDdT!GaGy#A<`iFSqUq1Cai0|qV$Zbtt(CZ_r%fE*P=IBbHT%Rr zaMW?j8K~o3>=9zFFjivyDeG#q6Lcg(I_l+2=Qza4KlCA_SA_B4`2siMWXng zZwd}IKN&iBQ`Rx;?^}0*uCbsK<~`!nhCVB!%S?n4jLAr;vL5d`)X~-r6Ndvv%R9wZ zC~ZA$vL8=ZH*KFQAbw-wh+_JzQ0S%{T(@>%P%VzPX5e1eXUeCJB6dd(TUn}k#QDI$hpJZ=0PG3KYF^#$oC&|P% zT!8dmi&;yntY_2W!JlaMLekiK8{*lMLzRdIq&Hg={&SakX?&G=$%IoBLFpCNq&KaD zV8J(=toE$lwzg2{v4vM>|D@M?FW4N)`YysKawpfQPV*}C(neSbx^3cq%o|Ztdn~Gg zNbZ&9%Fb z$g@k3zm1gx$>rqAicwZGdNSde8T< zwbmLt0~;~V+)PHVvQJDXz|Lk2eM?1Y!JXE)_vgN`WMN6`##_a@id!)8J^*`X9m3g^ z`{YTGv#h;`tg*Q2rkY|TxQ`$+Woe2vVZn{d^H)w^A=dS!cAHn8d+-Nznq_VQj@Ufv z>#Waet-i^+pu4*~^xbMRY1}~^h}=uuT-PV=!M~Fuu^4zz{L{2HcQ9s0NNt+f zX}vzr8i(3?m);B4%1VB2-*>Fz*dL5A(9zJ0-i22z{Ig|NA~ z*-C*riNYRnBL#>Kny^jJ+|~y{Iux>KD1G&ee(?DT>R~f!jQF+a!-)&gizU2M8L1J0 zIT^fqysi~Iozhjab)(pI8*M%Qd8zcMzHy%RsAe}J^PN%}-1eMDF4f^ua;Y9YZ}Z}+ zPzILxt|H%`Zs9tVv296qWA>V(&hUNVn8{XX4GuVE(kbCF1$!{JZ4&LbL9|Yq$w*{& z&HU+y;yTg7#q|>@YpjVWRzgb7^aZ$t zVXALWuX#y=Kd-hUBedrG;t;Ox!O@aaw{(g>;2#5~8WBf~Q&d(MHA?>(QEx$R@p#on}0Rd+6r!8hUMM^VzZB2sM8B}cC^fdmF+V+;p*;zoLtg$yI6r(WHKEA ztjH9f!^SFnL{X-=C^<{4%@pI4=ZNA=oC?g!&LW73Q>Ke@IL*nTG*iSSi_w|OL`8)- zH*@7oEHY5xtOZX^PoeKSa1a17gN`n&6EklKs5+5cgdm__0*H2~Pj#t$Pn9<d+89cUP}Uz4AyZE+Q(UG4GMvfX%=?Zdu|HA2@(M?}TV~ zI_O)iBU$3_xO(a55Pk7i1+-&BXIHb>RRimY%bhaQuqz&w)mnGa&6rcHF@-5OD28+B zja4^QhMvJ;tWGf*#?0zCifLs5SXwULGzyMVlmtpfe}A%wf+H_9V_z`(;5@YH;&$}W zUW~O*<2tN&M92C9TzE$}_u&6)5)k_t&i~@;Bh6G=q!u88;&S3^FIX34?fc1$=I@18 zT5Xf5?ilh-d@*m*&j#6Msi`Vc>9)~E^GHYqNW0OI?WJcJA11_)=$5+i(HV^72;0Ox6?X^>jj^yw8p$G z&gr)=tb4GdE`&Vn=Z2fKwma7h$*CwRTtVRS7 z5mjuH65p*kBCaCK^30g_Ua_Z!lI3zZil+lBKN*9|=kBSY)xt62H)HUFc(#UqcyA2m z7DV@=PW&}*_hA`+7M5&HVwnLUT*2(Kxu(VC9)SEV@Qo;}y_zF^=PhXbQwJ%t>?3HE9@@K+N zqW@Fqih$U?zs@=(w}-|_7QT!k|Klt)DoacCmE=S4z}d(E=C~O`EC_7UEJ*O>yqox~ zoSRqvxpLQyQ%O{>A&Ye{{mEY$D#zguDZf*&Z^mjL^TDoo(*zej1}{wGuLE%8|CwlL zQT$hgDol*PQhQe%(sjj6!KPvy-ICK`NFkSUvy?J_SkC80;#kDJv~*EK@RW zi~$v<@zG~n$^VG*mR1!v))u!8t-BsJ)2@=+Q^5e}YrHSvY`MJ?i~?Jh;qPatkVaWe zO>tvovt~Uip2QW8@g^$a^U%#RxUhYvtl6btI zd3=^Hd;j)@d4-jgl_^&0nC7$Zx0WN!d0rEO>4hHiiW94EYz@gTeTdV?i(*V`Au2z)A;)t8oW=-f4t15rKqaBrlGtsICMu4&y%=4 z6YwUZnI^fV*;Z}V2e=IwTOXQmc!M?$(TwTyP30nV1gCcQ(jolO)_7W0s4v>^VjON!YQu_I4t6Bql`q(+c>yNtC7r2q&tB#Y6qUdh8RSyD-~d)L z`d+vNYX?)Tqz`Zz=U?eoO>6d#5CuITrgSc^!U7;7=?AJXnHr5@h2x7Vb%T^0XdQM1;j)+X23@gcg|G;l)ae}Mo(#ERs5sjxR#%AZ@5hC7x- zyxWRo*M04zR}QNy)wBrta`3q;l@bPGH@=0~p}Ozu_l3l)DRj*q-Da~dBjq~bPsVAB zf~g@|C3Vy>7{P6A#{wv$pAk znA5j=i=0n%#w^Fe%jY@^MO9xYxVrwTN?hNXd}m5vURTPiSm=^K*hUtA;1u40VD;f$ z3CXjqB6BjxT8@oKd+|Dz9zplm?wgs9ZS|d)?|0HqFKq1m3nZ*yU+sM&zHeU@iJUx3 zaJ7~Et~m;wT_!vJZM5`%-txd{zz%Hf?GMwogl#HE-+9f(>K#r$-g(IC4kdNmi+CDB zcA?v0Dh{-iE~mQ{8*vCMWolyfp_ayAP9-+YVZYsh6(!RUVieVVuQe}2sADvaY-4BK zA>8}2r3h!Sa6w}-T?`XItB+9EI^Ny7E#Eg$&n3xXg;Z zi(hO1;dU)G=OBRXYo2`P6;I(^4CAqsWZijAb4SLX_iapHo%m+c9Ff;UOToFgs0({r zduRt-&`Qn$h;?E53aj-k>|Dr{qt5zdBynEc*!+8ul_{oY;`LjzmRf{KTwCB5IsG_J z{yG#nQyjw}_2|Ya^d>nv&9kuM8C->$3C+hsRx*;wxCnAHF1N~QS!(TsGrT@CJr6aT z7mgSIjb*QGSZ)5>hAHAs-)5Y_#|FlJWZsWVyyC7O_k%v@!>v{QViQnq_GO|7=)f^5 zBIIME;M%2a*fIVK6nPv)5TpMEioA*|mx@3ppGJ@X0c>eL&qX`YE~+7F7e3PfJJXgGky z%UiqiX?qDa!8R9I2eDfpA=hN_ZxDjG{t~)WKE7Wx6kwOPOGJ(GJAag+<&JX zOG{^{JXH5(+&W|>SQkFDTLkEWA-t6&#+r$NbF|z}WXbi{rMP2Q?mUuvYTv|#KfQS4 z$TS~z>YkwWRocRR%1YdZ1vCuQQUWu(>-3RdkHQc}UB)wQ`eMMFp&R{ymKYE>#V-V-EfT! zUJru`tw-!#9W8V4>3I5{U0To2#?XP825m!0I+eX62@5iXPn@tSKco?&Qk>OUFw06P zyeIM9?Z35C(r{MFVZ8XW8(5{`q&OI6suT&ZLk7kI+5H2(F7H!BGX51C-J&mwlSX>5 zd8XUPa~s{D%ZGQ(E6Mtv+^u`%V&8$vr70`a?cJ4fmvYAm>t1Yfd&6p8wOrI3`R`xh z<%(GM>JqJZ`yt(tx%o*rhbMxxcBS5lbxc;K4LMa7sA*PG7j*!|g279^ni00NPiZRpcX30XB#(DVr8BG&D zy`Y5MEAlB8SFm(}_Y+i?6*Uw$7T1EJ>V^=~hw|ko-Y>s&wsEz} zHR5$XHYdnWT3nLZJ1WjfjWrwOmxen}f3H57!#=Uf92GY`^~JcP)R*EePklLV zQtB&l<7dAf7eD)rI4dhwA?EszC-`N?g}Oe_yAstK{Cm89Q?d8=f%rq^CZX;8hT}So zH#IK44Gl|5*1so>^UGiMI=^oOp?0;6NQ(=Y3rB(U7vsjG8S!X_HJ?Z)J`?_v zy8M++`7KnwO`vEo3cZLzFU46k46k2~eD7#g0DQcM__#yNj+=D%h}m(MZzn!(BR+0D zEj7-+#Y&A!Z##W{+r}y&In2R7u!w!E$i0r z34KvgV;C$CX67h#)QiNv+w9cMDvLm=9aR3XE`K3plRm@c+x)oh7_o5Vu-mZ$xFx-p z_^BF$MppWO-fbjbTS-2*klwY8Op9A>J~IkB_96uJCCJ>%p!*eS%7VyDg~rIkH{n07 z@ptL`!S$MY-@I#Jtu~BnHQr5^`X$D4jTdy=df_)$IEtZv&&D^=b5fV<(D|TeJGFNk zwRbDEcMIu9TZ|-S6I9?uwDBc0{AJ*L1uF15nGNG&jj#POzr=Kv{Ok00neN(w^n~bH zJredqm*1?*4?<6%WmI%>NF%8p!WX#QFEL%9@lm{r@;B*xS_`2M>e)ed;cl`E+o|2# zsNGx1E^HyY&}OB@HHa!`q8}`n4i+SV1($;blfZ)Uun6(62-+H`exZ80uk=g&cgnw# zA9la2Hd9AA9i!|B^(U1}y6Tga<96-W<*q~D(q~xh+T#-!4b`x@(!3aHz)AEOiGKVs zi~?=XqU%Y6c~=xY$pk9WZ^E-W$xmpEVy7R5X{R>%%#*`V?=(d>*LQfDs&Bl*pJCRw z--qq-!>Ca8Bg^y2>r{Pfsgd{$BG0SMWzprC$}#<`ulLiVkvl?ueFA&9X#~#e4}*Ti zFtXp&Kl^X;%ZmKEf6&k2+(_;DWS zEEt9M%=Sx)Z<2ov1Kv!C{W1D|kN$m@^ZR=D?CkMseZEkpW+-WdFws#?a8K@tK{^Kwe{0>OJgU7bll(z!^2##M0 z+3&zb^%M3-v43f?g#-Et)E&Jx z_XPsNCkp;$qqu_9*dk66zo>kCzMqO2?eecK&+}2YpGcHeN=z@$ex1m@Tuwc+QI7C* zYdqg{nlx4aCOZ^hlHaEV3=qd`MYYufK^YOUG z1Jffv%*VN!j|_Kmm~cjcU*Z`GU;HrPCTTbfS@Og5rD^)49Rz=qG#owChx?i4$9{0t zTJa*WP;h%z4^cnkZP0L+DYUkn<&Gi(GGga>_|&c8&-K7B(QvlhYq$arT%E+58XM5x zxw>2);7E=p75Zg~-EKP&=D&x>N4if>KO?5ws%8n8{RXk&4qt}WXXeM@GkN%H_IsxqAmL7qH8v$J+MHU!>^z`hexu+QkrqTf_E@?cqsX zK5M}8&35^@v2(e&oX1nY_*bj?Uv|ciZBgP%?)f9QCNA|!tT2tU-u*X17iWbH5_+mRV-=0r4( zhfAApo67u>!WZ0h4yd;jbb#K*o9zx}*?QdyEUy8N?2mGV*Qe)o((VE8Jv5)+L2aSeF$tW(A8H)p>^)%fPdn*SLk8@1bdR;B9Abn`DY*f+rbSet&AVaQbGad;fva{N0)cSZ={}YkH+8C!1Yop`#p2GN!kyR z{AND+YZYC0cjPdpo)%^;q#d7! zd9&_*+qS32zNG8f6jJq6yX^#YvP}9n>9OhmTfZSAG>^Dgx8r29YR8#)rjN8YXh*t+ zOF&+<^)r%t|L5?h#g9LR@woi!*qOokZSM4PmhtV;_}01c!9IlRk(y5|aP-KxP>t#K zeBx@9C;F0F{Swo0`PXS50-4mp*|FwA*;0}pf{$P4myoNqqtEttsBve0T)PSR#Ny8T zVWOl2^lW>4OVjl#Y=e&P0XYq+p^UD&w2-e$!Dmw(OuX56Lf`RxcX@$XUW{+SuE+;1m$DEzM~^a_83-B5l?xM!jYFhBO+qwoyG53cX9hWl6R z>uw)jeS0+Azgpj>j=}3I13RQ#Xt)NC9!H-K&yU+A&`X<4F~w#5NCGcPi(MQplNU(| z9B5o2yZz-0@aH~7C)q3d@VHc@;|FW?_(XP);8$z-FuyKLKFwQf0R;sl*HrGLF6Z@+ z96MZyVq|^OwW5wBa-=gNX&OJjQttkyjU6!3ICo46n>viR%7c; z^nSpSCOk~jyfd8TzSLOKL&CTJ%L-qf2j5V7XwR!AM58w?wn^ik^i_rbR>dZp-l6gD zAw5qLSC4RLXMT*tjQ^P^*;xD`y`^?_cd2>@il;H$o+03v@B1~J-@~WD`Tidckt8#S zM%nVbOVO7Bdg&wO**zYF)F{C92Q>U~3GKi~^Mmv>P}Vp<)+~^|m3%S`#+S6)FEMou z1K%Rm3W*^#){T93EbH50jc=9*pFIyN1ri$8^mxPN;ve?Q601DrT=SZ_vU(a{(Z5`- zL6@r;xLmHg9Jl+pF1OuNE(#xA(^qsH#aA%*lT1Kt=4zCe`u>PtVhS7A;V%lW<{Bbi9#fJ-G=y?^r&Cfw^mha>xCl^sx*ni{8$yJptKe% z<5rZD`mgcqck>PO5AM&3u`c>`{0=dqIS#>gP>({XG8SM@1|=kxL=khxup-w z$r35o^X>6ywTAnd0#k5<$cd8F=N#r~tHR@vzsD~zUGM3)p~nk_`3(oN8ZESJlmRQr z#im|`Kh}ePd$f4Z3ye(0)6&@V>3EM08*?~Fl5P7D?N6wB?oiowKiKwAu6~h040rgM z|C63n%q3 zvd52%?3(h=D{RXv4C+TJ-|&=QmR#d$$Kd*Hev?~d zYwes^lZK{nRZf%s5!G}2X;n|Q#|{oHkJ^7(8fH<{1a{;+X^#ni(z6Qx6xkYwU)3)C zC%Dx^zzx(dG+rKqu<+|r*LvzHm2#31d$atWW3Tg(K2ka3JAPT>Mfq3L2mKzp{YoDn zbg`Bi4|SB7^6;1NAJ+IsdHQjCG<^(lM@fCm!PaYyT|P^^*&6Th@A~EQlk%^oJ3_t! zwBlmcDYViOA#UV)N|$mV`S+Z{_j?bWL-RrV_2);C1Nh;j4}^cyUWMN~?}*};m~!!6 zN464BKAJuf-oqqR`h}oDB`Q9jgDZF2BrO9`@;0DQ~H<1zOG-KIwVCgbeeG0beQM=i2bsYW$lte4z(F&kGA= zxiq^R$p_JOT$fwpE*D)s*0}^CEjHgaMp6=(?!fo`5|h^t%$N1gi_Q16vt7f_ch^tj zzJ$-P;mO`fdNq8H8ys;B)0zs%U6vWFbc zm4!}KEOM=KD>m5~(qAV0@jp=bz3t{WIrE9zy;{S6)1!9-&ASvmw@1?B$&s5w&_=E& z{@)Z`T^>6>_;?~-3e#$0?{xIFQqudnC*$*kul<<9*XrhH#Q3Xp`!$?yzTF=8 zzC3F8VGT!P34LTg!>{1@4%uabJFejdo}aQis7@9#9SuM86I#PNe$ChIV*Hyl+$ss} z(19Z{1eq19Ca9@A;ox$|b-AVPa^Z3|-xe+CKhx#^55FuiP`eo}Fig1B8qPcaF81_a z`!M154-@XBhMVDTKl-o9Q*YAGReOhmYZwBK^FT`0<>>&n>WR2hWmBRlrp6SE( z(4H5W+d&pNCUawpRYJmX`NO~R%jZv9zWcva`9l(mQ@_iesy%Vw`}p+Oa<<1T#|?d| zyw`43dHSh)m~e-O31^%bUcE`fgj+pKxb|Vf?H?xG$zj4xdUts34Ga@*(=g%oXgKdU z!}FtyAve$@xU>GM{u9rKh%8v8K!Q*O_X4 zfa*DUQqk+Rli_hK)vtFel;_#aZ_+w>1E?`BDaT%=Px(4N_n9hpuj zxt_q^R6P%R?9mYQgzeUnND}Ls{YF4BY1T$9`E8-O)rJN!K8DTiM0P{Rc3Vol-OtvqZX;FV z-{R@lq2*u4TjC?+AJYX#K9hvPzjvgp#%{+@`02h6>?gq??`Q`B&f#Ii9_LP4svf$k zh(64(A>`9uG4z;y+kW{+DZF9&6=8pr{kl`KnuN?}({)^zzsEyYRC)LUca|K+Gh)>a zah4C+W*+An&QNsySx=x?PomgWF-9o7k}@0%neBSyfqeydM)KP*R^k2r2+2m9k3;nr z@6QxD(fxSVx1@6w{`m^M!Vi5jXDfwcIyPxIzHf*7b0|9I#~r7ANUKG96gpyO%Qzsl zbIx$^9mucwG0II+~PsqHU+!FH?ASyYZm^ zLvr3aKX$dAzi!a>m*>0w%T>8;o^qxt5Xlz}-~S2in!}f0L>RWwr#bw${nx7$U0?7i z!dMSo<5js-HyW_`1PZ0oV$Ch~51ICOzIw94=Z(8=k1~D)l^)y2S#WKDHulnfV5EK8 z{VWM&{n|f8)e|<)A7p${J?q*;Lsh`eJ5Gblkn2XIUx7r0|Hp2=IGgNoUIS)wqBHI% zO;zw`x#1ySZ2~)pNh41BWWW=puAt6l{`;q?a$j}Jg-0&gCb%|;je&nS&oe+^AL8&tN(i|eE4?d>M(0n^>EMA7||LFndFsw&XSj_gXCY*Kl)1A%;n z@BK4ADcy&OyST1wYZQ5(z}Iuw{(`?$)$I>Lh2aKsgA$kZ&CRF z?X*vdpWA^efwa^+6-;2a$M*Z;^^32Dia$=$a6JE&?S;Ma#&MH|3FjYXy@6rEtsW*^ z!w_%@V0W~A3FKc_EyR8YUH+S@Td3dZ9v45llkW`+IJbqVd+VrN(k9iP6LdLTJ(oxK zlMGbfd4M~Ha{N}V>zr~8RF3GO-`h3bCHi;JPB(_YpPJ4sgE~mTz#UVN$f4!0hwB zSL^!XH>>{myRJ{lGwh`^Ua21j;tTn4t&6~yHiaiq<3YbJ#=VM}xN=RZRGNnKYq)9+ z7uHYZu6~*m>+UssJSRG+zC9X`c5?>o2kO`Hi@{qBuc*X2dEDw-S?=if_$}%eZ7!w1 zPx+H{{_mpD+wKcIFzUiqC>-vaKTeP zzdpvDA5CwmpC;vEKC1B)YdmiLL;R#&C%8QtuE?hVhq`A5_u&2ap!dk=`ttBi_~Y+T z{Qj%Q9~*prW^aVCr)NX0Cnlr5@u)QZE>+)`b$cM6*f$u5n=#BRd|{LDQh5z1Zd!sD z(<=WG$=SO6o-eBMEC++=W#E(+6~U?i0feMPb)}!rFLm1cm%lI|*Ol z9@Wl=BsPgpwiCu79tO%vhu@`>(lT?ole*kbJ>@DjFlyy{Ddkw60Jvy!Px<3<=>osQ zf#dO^D z4fiQJu6N)I0GJlLBpmM^4cFm?liHOUo2}_(Is!WtUS2ozwr`z=AE-a`P|vTILf-WY z6rR)d4sM^!her)??=BB4WG4vkq%SG@Hfg*O{Tnbt-o7Ky8vLX3-Mai^dSC)w!@R!` zM~$)9c)0hva(#iXDth~36v4x<4{k47?MIb<>UwQQ zxc?cxdzkP8(VLBW?_37IQscSCrwAT!ya4$l&F2RgF;eAz8^V|Lh-$|Voc2e(SM7-b z?E66UQvP%V*H3EvIxIV=|58Q4_-`tDq>;fR;i3F^ozL?lWPhfg+)znyU9hRV)|gXO zUb;3nRBIF!sh1f9%bP;Ma=b}ZzSF?StzKWgup*PD2RZ(L`SLvM*JD%Yi=hpascypc z_O-gk+@|8vwT#rMW=?%=EudwKqmd$uX&_ZOgCIsBn)nT|v zEJ{O-)lKVUPZgEc*RQQEH)^U&Lcx-v(wgGxTKoXa6~(1ac0F=hn;5FBytx`bmQ{pM zpuD(IHY60}pOxfj6h*}~O(aXiR0gPTD6iu*^r9T%8d)b{DJw4tRmys5(9EI=bc0h) z0Z2+T^&}t!ErHAGi$V>Q;u57b^-v4-x}~C;dXNK9)a(G3l$NDAO_RM-)Krhw;nfU^ zjN%f!?AIw*RwpYUMi6u;=mAG%%$qX2N2)%#KDZj7 z@$2R(Nd4Xj0z+A7R}~r<1XeuT9cTB2)JgiOwz#IIzEqY%y_KXmMJ2_JMtGac>RX&9 zY4%a+XuNPWE-HcLtqo{xd09~q8e+6o;FT9L#rVRw6^21lNu6EP0zoY=Ds3z^ni`Ai zf>0;2h#DCDj3Sl#N1~42%v@9_wbf=wsIIZRLNncfY_e!pgz8F(ha@0HH;1Yl*9MJ} zoZ{91%vX66DR~mtE5#R961J$Q4lncId@8B?h8gsA6=bZcS4dz%OR%)Dx&fm_QE{-ey4uy(8jU0Y z^i@>5p^cL4^18~VDx)OL#*jy2h^z9*LarY*WlsHE(#3k0Op=9=e6+=v;i)mOOS%s^ zH(U>3ml}(UY81s~EpuziX)L7`PHva7u|v|Mx{jF=*%^?g>QdZmZfa;mbfG75t4lGml&&?xERTdyuZb!uZze}i zX^#QZgz=ZOFGOBPeVuKk2#JCvzoDX@yiHYCb-nVlB+{z-riPkOWl>#yQ*}jksl>q) zDvwYjk?$fSNiVM}lb(ZJ(*P#G)vgdm1T<+NonVY%Z6h8FjZ&q9%wY zs05%ws8d^uDl`j&oU3z4b1_o@#{n#fHdSC{Pw6Ges5mKkQ1<{%H7 zVf|Aw$F1PXD<@%ruU1wr&6DG`k?=Lofzc_cu7TN+V=j6VU22rTsDY~kjL3=rHd}U! zb&o_ymiG0--6u?;r0rrEZ>X<<&q7KCvjK;_j9dySM?s_7_GMhS*}Q7Q!$lUomL)25R+(+erQam88>-=;s1yh{ zG@&wstt4zHoMo96W{tzTSj&)I29}>@_Og_$n%Y&?QjD2~%9DczF{{EJ9AxGEemAW| zE)4F%G<#CYX|q&Q5ay_cF;kLJ(uk=|X|ZErT)veIb=)R z23u1SE?p4F(ohX1uC{Q<>J%on%wZNmqX~veFy(jLU~hxN$b$`FX+iZY*|Mf^St?mv zesc%|JL{qx&urA3XoS?YDCKj+sU<_IAZb_$hA5*&+XhXqoQ)~RG)zLm&7B68TIy<> z)|--AO`gna?dE~SpoZDVq)@8}`YCx?5tRou0E5Ay{^pBE9?&5Gt$}meH z^GyCp5GGeS7NsRLODzjw)`}mgClDbB>Y zIbn**Z7U8Ik!z-`Bx6+V;V0;boEws^7*aNk^yaC3tAsoWe@}jCzGK3UMa1YH@O~r`gNCJ!{xwDHFEKHkQG-u(01#{IbBV)n5g^P1i z<&0x)fzu$}l9CMeh!)6+bJ*z1>V#=Rb+b{DS_9_^F|G1k9p9lhjbh3z1CG`8rA;+Z zW5hzsT4sl;Ysxf2c(8I5mz>f{ZzI-fPqX~6@fyYhvCL}fqoOLjM$={pcQ|PTI@>do zrCb{nT!J4`6Et)aB-diauF;E)ifDP zXe0>GXrN75NvLM6qw|p+OY9#Ay8)!O602UoOdcT%Ign)6wcF5xO&^dvmh#s zBrOJOxups-BapE`s5fF`_#sF^dhk2Kxnrd;)D$B^y0sZrLyxXjn@HE#6)dk+gBZdE zH0x==x`iQih#JOn1!7?VwKhua)|kTF5OOE9$uZ!!HKIpdLKPOW3Uh)fj#l3S|8-HQ zxJ(K*t6~V#(qtu{yhe~Wj-p(xnOYL3=N_*rqQrmk9ltJ>{Q_?z*r|Xo#FIe1xbyi*_f(6RB zvCYs@XZtN0PyrQ(5DnDh0QHjgmh?==RytR(fYEB|BQ)8eC~cz^l1MMb-5sMHIp@isqL$1?D;nszI#Rl4&rSu^&5fn5C-Pz8s@f^ml_xw$-C8S zjo|>Z*Datm2``uIRpbVZ$jF0cV;!|Tx2d?c!Dv{Jhvi?2+<4b58yptoS2t3qhv~0o zRJ01*?C>QBO9?NqzTTi^HajFuP^AV3sKc1#@GDr?!raZ#bMFc}$BA8iri=YikR8=| z8z1Pt1#=sbTMm{IAUCiS2SM3V(pU_F>DN2SBfCp~f z@41zR70LGmP2hPhLcNH*Fj3l@t=qIue~&W6_&u{FqAn)!h$h+no3|=29vp!77FTDY z!wS}VYWEpSB1`cOdAlT+3hC0+`<(uo&hr_$UQE%1gu9fBL+Cll96<+pF#*aZMkhAw zdLOsz&+~$`Yc{elM5Cuq!~9);3&Z-jiyutA*C|T%3Hqn2^tUX>57P!Nmo&~V$(*ad zp{bnwf}OR5lXvN?5ymOs;x2yrjRWXyawPgijDD3}Dvy(lh|n*JFf#mxgex!3zH76^da|7~IyUqn5Cu6_o2IQwp zbuIuoIdiWYke^oQTxzvWekBZ$pI&qTIXPyZ8zVnmu5*Erlbgc;BSb4g92T)SoNbFk z9w%7f1Ad&U7TKJH*p0g*Xbm4xzpMJ@9NRbs*bJU&^DDqf zHitmZ$;%z6NVAy72C&mMfO%inNj8MQ<>d_XeyWyX(lkzUU&k0hI6~)kafkoH1OipG zK2OwqTB^TcG&xyiXXPpJ2!Zn$YRY%$%Jvb(5c|d8~A~39xC9ZtAZ~_RPcLkBY0rP+=&NtRvTn_ zH3nH@^uW%R1zFy48(H2F8d*FRZ?}!i5>_`9m#b#E1B(owsSQLz8R)kjys7Pi-c$$FnGV6f$d46oqIs)(Or?I^`VHOmgNZq{tL#U9v;?$OCdoh%k}mhmVQ zd{tBMZM$y*oE)i%f`vM~fget{DJ|gS0yo^<`r-4o+ZLro1>P3PDp)1BZBd#j;keCh zPD3Nx9$+@GzyKS|3=0ghA~{sx?W1QkXAU|X;^Z+qtB{j_)LAqnJg9l`w9T^sClA?K zg^?Xz=%t;Id5NbyFZGn?C7%g9SJx(V=XtTFMjEaL+)ND&qfRnDeKhU&Zr1ja+riegZ zWW|Nvim8vh4fGj>UgXiba=GT;tqyCw+~22vddCJ?^o(xYi*_S%p+xwHOa00&RTNn& zqNf@9Pj;yQCr4}TN6($q-1BO;>nG+lE41q;CYrTa^|x0SqKdDV76<{;P-C+qz)9{B z)cre6F_X2yf##%(Qigt8LoubOZh;O=Irb((U?PbuWFna&2nSQb)gsGV9m$KgzGyNu zM)!TiR>dHi)mrg8^sj-RwMdAe}g5Q{JYM=DwMB_A5M3ifk^BT zWInCEvKO7{Zn#t%#$Nr?D>g`k=v#U+I6;4dMlY6l{nL3iNCcLf^iT5!21(OD726;I zo&=4sr@Rq$H)?nL0Xv=+U};)qhdm=oaSP-fp?E;#myw zB)62>U1+zP@kfbVaeZaFKGH8vH|jhr9kuA>HFlM`T-6#U%S-cM$iHkO&*x;1omI%m z>uu!uT%XgJ2tWNgjUdHF6yW5wHln;pL=hpF-)RK=jy@OyPI74|l~;zMm?dlZ$LzMVw^9sTqs9 z_=#(X(tDBU3mE;GHaqh;$%qJjL6=RVPW(la$k3!{oPN$mwuE~j-d;9c^1e={+bvqc zNp1s#k&`z&P(zX6GgdMMOgknc4{h|8>(`_&w`p3zG|jSWTM5(oY}Z-Jity832auC5h5_n_h%ZL#GZt}@aViDpr#*HJ zi#X}7Vc?PaLc3rAC%GoHl#^VIQhR>lwg8Zm?n)!=17Ejtv96Tt1E=RXgfRXuxxjSN z{z}j(E)H4ZOZ{f+pOD24AGZTpjC_{^#mOJqS-G6#_Mo8t(f*3WZA-yc4Wy*NE};{V z1?|pt7mVyPF33>W?{Ptd4Q3#x$#yStIn|2;k;PD^abpDX!@AHUZPC#4ob15V!WW0RiGL~eDmeyx*2-@yr2n3JdJtkduw@tBZtVOJy_5thoQD;=f3 zPd6IlV>MAEb38=9VJHa#miIbCPP7!5`<$l>SDY4%`9i=;4OIrYCh zvO&ttz5KS87Yx0xufIrBa+S@jCCoRjM#6c;=n0L4kx>PlKI&9(U_Ec8<1rmmAx?64 zqJjhK+cg3E^*15pwA1zo$2nei0pp@#oOb#km-`^YZe}hcKkTZI(-ZA}$z?9=wfT>$ zD8oNFy1gs(H$;AiPJYSBdS#?4^|t;7)L(VdAvEA+1E4HTj6+m}`AhdyM_k};{>_+Bm9+&CwSmS0|3!ZibEeLbwv-(HVnA-Jot<@ju@2~=#dA-et zm7JWXvj~S>yH4DuaqZCGBaBh;z6hxM^sisj-(a5?(Q@6;NA-6!)9Qs8VRUrg5>c5K zia0z}ZBd5_M)WmJ5)`8S7B8m1>K|jZAc6r#Bm>6iUoW-AHG%<`>7P;uMdVd*aFX@* zuZ~c&X(}m(JJU7y>zYgPoPf$r*OmVovVY zS;{%!r&n#jJWjqH2I%dZ3-zyz7R=&gk&SB!qd#P41vvTdc2>l~>0MC^ke!r z3%fH~jPn+r7a@PgHN-#c3Kny6<0#dP=#G)lzsBirG>Mbz?W~BA(OZgCf{QJ;i{)~1 zwayYoaAOxglsj-m5oUMTn?Be8HJ1d`) zZqf>E(zsHT^;WfCXRzOgPU7U*wzbaVH!6lb@B!$ zYlTj-OMvJvCvUc)7ITt=f>E{x{YJOur2dBO;ba0+V&rlwxCy9krT(?lh6-@}uPJX1bqBE6oJz^JJ#K|6=MNH+i8(Ab%8CjQ&tbmh@fSAf@H?l~kGBSn+Q#t7_ z7|GP9bnQR1sR(eA3r1n8q5bxt?Y}SPNCz(%x;^gHH z6es7~S-G5iO=l@O_~{Q0ASao}3Xq?e&1ftqnd1u3YuqB4UcgMh)^7X~PBKpkS3wjG z7chsJfpA$k$qa-~!AWKypg7441QaKkfq>%VWSbuaoMa9Fij&L%;Nm1R15jR0)Oi$< zW*y9mE?YSlE%C?@?Xmr*&f`W<9*3EjzGyT2ZjJVbHu?Z3kJ(wd?{U)ZkAP1nol|zX zoa8QoUa)N6>J;SU{dSfud3iQZ1GPHY>|}BBb~`JVCGqce7W;}eYco6zBqn%UNb?77 z?Vq@*MxLG2loHrTo#r-D9;dmnayWVi!wMnvE+WX64tGwZgWri#hqGot4YU zqdJQ;d2ts%>Gw*&Gt1@Vjh5<71;|f+oeMxtwuAxl(*_5SlV1)4v}HvnxEVz@&5Jnc zE*R+qaKSvg;QwLo&Ew>#s{a3;C1F68uTc+PnIsBmWYIu? z1PDx2_C3L3#07}TCZfg-0}2K~3Ec%MC0r1spzIuQ~!}uEDST(r743nn9d7h$++>esH z=vTk>D*+O*grhtA^R&&QHM{)S1OBMbcprt=dn!yfw+!=@Yfq9Thg>ZjbCURrCX?%c zziAQcKqAWx+`0V-52{{nyNY(fVpr;yDb=)|MJMA&HTrLD<|V)zEQv#jM?EDgWF6I} zkL{Hmtf$ACr(WP`M)d%{q*O;`Mt>9GTc+0=_c{7*>QdFd)vP80t%OPvJBnrqRqSn! z5+D`G7nGOiUc$=Z1>dJz%O{2d|B_lUU}D9XaeGfF#_Tq86rI$D>7w7o4lEh)%2ixc zS=PX7lyV0pq%r!CgD8f1;-0_KCzrawA6mpJuuC1~?$ajHYUaKQB%)IsEa)dKLIa4Q ze8L>|{$@QTW;|qR)-yB;Mda%U{GesfyUohZ;zzobFG_*0DkaNucK>Iz#aCGOd+GDf zJ!R1qtfMZ7B7^^|YQJn&36Rc~EWtxGt~56_!LaL5|X0$Ln^r%1LWo-q|&LRM+s)Cw0m5 zAK@6Bsfrhy&*Uo#XBkxmlAj!1LPv8{d&p{TkKEx0-n=^01mJB-xru@FW&M+davlL* zXjBG#&8X;XLlQr+)KefmAF|vVK=Q~FZ8VWcMebDq@$VG9Z-ZY=Y>{Ee78z!bJFYYG%YvCYT4(uz1Qwz`5_RHEozL_#_XX}YUwy!j zD3uQ_82@rgjGNdORwP>CWD<($&s@*b2+L;B=(#+aa$SF<^%EV5ie@SuTo6^w&h=DD zT)jRca#dN=rLeAU<-h}c*{CXTsZ#F1gVdo4BGPxfBJk$} z6p?=86@mX4posK_R|Jk*+m-He3`c^-Y-n9bf&Vb74x|;iue6Cogpxb3vHJ$@Z!q^Y zAP#f)4Re2l)l>scDiq&nBKbUO?_XvQd0>?XjZe*__Fc<10ls2X4M+iU>F9+Ig0Mltys-h_<&JW;KN2`z{iZL0v8&U z{aWGUo>F9+d5Z4zDnP=PT>mdt?N#l&`wX~|-8QavE8NRdz+;puA7Xxcz*7zR5g7cY zeS1CuI8?vfl&AWRZmz1rhW3r;1mNhRUbhP4i{x|_E-aD={CGmH+wRow1b7o+*(qWh z?M=7!C;?uhl$;OdoJp5xNsH9}+U7X5ILSK$`i4jMcy?B89*vcy0we`lpFD{1u=l;5 zHkqc2AtnDnOBagjKV;*ZP|R+g0#aYeCDv?>55}h=aTr;G(m*7dV?|&Kf`*lvJY;V-*-Rz;JWnEMQV7QeQ@jfeSc*i+(_M5cCzGJ=>XM{lOFIOrOGE= zqI-|=hQOa2RRumaz!%bQy&`ZWJ!!k3NUPhGNfo&D07ax7ydsbnl$V!rqo(jZ(m+x+*8GdwE;_qaK(ORYQJXpnJlV75b15Kx47K#IlJ# zw9L}i0DVKZGOoadM%BV#3-%k=q88~^tbiAM!tIi4JmAGjxy~Zp;uV3n8{6p;UooXLMe zqy_22W7;a~thxOMR~608y0>jvSw*+`EPzz>zmP>ZMqQfCFv}_do^MnY$XI2SlPf!n zlAnRmz`ZsNqBGDVdhC8iw`Er!3)K8E?*{k>qpH9~O1bk5(lcH$%={O+Yq6qFzmwXEfg2RzuQ8Zc4HWq|ZuuNY>4`*u@Ffm<6@-B#fax?QDmq8ucrS4Ldk zIkmDy6Z#-;0VD;vWdl6QYYmpo2By*gjx#C+QdVAU{NaN6*B`bAyAM7xp$7_E&KS(oC6p>~eY>L41lyZtlv%MnlxdDnu|MH5!bw25W zIFCsCDl4~`ffENPB2D#*!0!%FMEa>$1im*w5ozclRyA-drCg3kyHtNgnO+fi z&j3ZF`@ACX$pMN;&v-@PI|CF=O01Yph5PB&6@%2{6@h0AP((V%D^`O4n4GKHP@|;;N&2>2cK!sy^7tITT2xdG{Mu_hc*bP#}xYDI)b-0fz!9*C`_TVTyjbG()qx z*s@E23yrD+{gCvr=2%j4;04}gt1AKe#@1=n;x{H9r+3DDZ3LwLb!0sZ4V4=<$40cmuSotn1Zf3Tc&`={d-8=r8$xnE~*QlK(`GlGsr+`L0x}+bpA! z<4^P(lN%zdgrmXPc3zBP?Vz(^iXG(>PFKhJ<-xh>4Nrw_oTV|Yvsf8$uXJ2XTY3h( zN-1}uN4h;TMc^|^ImN+(&b6Q^aJB`l0|}G+N}EVmTF^SM7&N|{My21epbg-a7W7ac zVcaPYi3lZ6dCyk2kLtE{s6cquVy4e2Jk(+)hbcVIQv{r=RLdK}T2^|xuELFsN`R*+ z)iOmm!|MURWK;^I%+kZ%Jwc&zIHk<5TLCo+_@+?_kSKCc1fFX-B*3p36`cx)=`Jd5 zuZ)WhVMA1BWpk4NY2Wshsl(*+?0Ry(9Qp1F9>3R7#PXzXx4T)o+vq6DLF&E7qBMZh zlv<%Ob)(BWci((a+s~P80>pMTpW#$_=r}&DFIC%hs;s~ac!5z>;4G!wqC~pFD+0eh zKoRL?Q_O&O8C3<|XH*9KgHcuBD@J9&b!ya54UZSdT)fFgRNzG2=W0T_LRnG7Hr%p9 zzTyR9?G7|Z$CdX(IKjqBBSGsia{F$io!mr)Th)%E{^qJ>_bchTApF zECXJwlt|uo)X<^ALvdg@)?^JVi+KeUwZRn_+ zR*Sr2$wPm+cks#TO};ZxWSavNu|rx6JW_YHS58|Q%%F=J5a+p?xm7Srx3}q5rXcVx zrOHPF!)whj1r`lUPHa)cMp?x8j@be={F6n@fV??U&iz21Z*bWo?QP%6SApY=N`d<; zRbKfoH9pT($cX{>`=n(g0^FZ!Dk<^X5J} z`(LZOcp@b~%!7FnMFty4P?<Eff!7!n&syE} z4^zp2Z+R*VKdI9(7wA^PuRFw1yXsab;2uiJU*wsue^mbc9j5r6Z82&lI!z7%kCD$&$QlCq_Z{Ukc$&b6gG`)$$`+7=zF#+j( ze)t753Uas&J1-Q2aEOM?Ey0Y01OzfDVo3w2UZ}A7LWK<%Dr_?ERXWHwB2>9UcYV)P zdVu#RC9`yKXjX~s8lhduy;Q7ly-H=JO6QDx3d=8%<68rv`Y?Ihz0T3k@&T;ve#oMrc>$QMy z7*zwlV^jj{>T-is@&yMOOgF0(_=r(;Aep#Hhs1li=~RbM#OvASHXhE%4kwBx8I z;H17EcJQ2`A&ha7?lA3rIcGlNNbt< z1V}PY5vkiN0!h&+BKd@)PfjGUJ}5T5tgumM8h6t;WOY-O65I>&uq_WH<|5`Fw}et43CWFO{ZQ@wEz`nRGqYqfh1(ld#W|kjJPAC; zw4$+_sk^>rDjD#0qpHBWlyYN-w8@8Dt`ZSA%BT#uxl+#7SLYCaDZ}1tS*hXv70V+! zgLSLV{e3v#@kZ5vCmNLjrz+)=Lh|oXi*6}l%br% zEnYTJ;ZdFnyE#*LUFlVTzcs1`d_pPL1f&)9izivS4=P;bDd3n@T4(||Uu zZ=QNdiMGk*Ja9v8LT(8ru&5E6Vsf=`Z1)bT$#p2_3`-*V*fBaVlWSzGzGGHpsgoYL zm0VnZL&xoI8^7o{^MdYrUAJX(y{>uqDxwemsC>>+j#L=Z^Hin1a>|&nhp|p~6a6c_ zYap)`Z2d_ggl~Gi(EUGj7b9HqktNZIaEz^r40w)FRp5C_xfP0ZhgS?Un5Mh>O(ntV zW>1AysN7;IQFj;Ut|v_;1HNih75KVRE^nlDR&{|(+VZR#{M~#dSgmSS(d0sfH;tA! z9+k#=fMSP|AK|ffM*UX zuAI;}hEJMd3jB;3%IO7oT)|h`L?S}Tc?kC;BOj-M$C&#*AP)02(AO(gHW8oGCiVFbs9H7(V|*U{1MsGJ->kTy%F&pcaM8SojS zYQSfea%&gq7f@JGue8LP4OvX}{Qf2HyjNyIr`4S0j8oiYP_mseY;kX%cjreCZ| z9cwcJ8E~XgHQ;EYGT;_Uxp4}cf%`5qOo1bessiyTm%YHE`}jU)xB583d}Y8nM%92f zD&sg&y%(gd#<7KHnMoBI^Fn_1O?ICT9&^6u-Q`!VWc2lG{} zD)d%KXf;VyzGhY#@HwNZz!!|lfG;ZL+JN+yDOQ2+4p1~{T^gHpD%{kl=;%SVmz(<( z_*bK9KvI+i10+A!RiwAQEzt679RZPiYPG={d5-yN0G~Ii4kVxaDqHuGOrBb!iS!?D z3nUq*h~!g?X2x)B=)Tt240xhZHQ>ocWx!LEa$}5ip()mY7Y|SjTSOlFm|+S$!Kf;b z;4*r^qWk!8H%ond&wORTKN(d8{@JJuxL7GyCen+hSOvZ`Krt+HsqWo$J)7FV9;2$j zNk(PBPbuZ{KsweGtH2WmC?ZYwii4##+Eh~D;YQVfhB$+(5w25?_w*``nQ$+Hq zMeB#It!BO&z&@jTf#f6W2S_q`#D=Bz1#b%^8K;QkQ;R+_klH%ts|R?5QFS2s$k(92 zVro5>+VS2NNHTe9JxwH^TC}uhs*mrOuMGH{QB~jzMrFVkmC7S#O{BL>u?l>5fFjZg z>odorV>PMWX}(h6^G4NyU%rZ`o(Sqm8NpKW9`1JVq(kHKfx_u?jq6fFjblUNM?$x@)Ydq`=P@RRfYwKG$?F z$+%`9o$hUcB;yp3d}>kGW~q-m%vT2N+?Z+52fRcn*CM2kZeogI<^SHuF*};CY$t{L z8Px|o(5NhQL*7gI!vd~cDj|H zp~epijMEwPIh#ot@X}40@ztvp{@GJ6DE!`V({jN7dw}lxvTo(;)Uyo)J6!eMO=$hQo@b(C^VK-$790=FEXs19xOn4-sZo0koK zUO73u0{@{@>yZwGx4oVs+jML2{VcB(xU&9wG%p}+BJq}YIiH&o1+lM2nXg8PuSV!= zrzo!sU)Ncx3Gh2g$&zYoBHZis?pOG*r+~llrZbud6e|Zkpszbx>*Pu{@?ivcvw5H1 z)#5GT;#X*{=M~Yi1h)KR1?foY{u3ram~@QJFTY17R&s zKGKG;wkH>~A*|!c`E3a6d2(JG!Umq4+lH`_C+D;wY~sn;Z3vrsa#kC{a8I7shA>5+ zqiR(Ywx6Dj*X1V*4fq$Ms=%iUPp+m-q%rz5nj9E_3zc%K8EGf~uosZzoZ|au*C4w; zTXuCI`Q*MDCE3->vTHQs?CNFN#gDtkz3U-6rkKpP*=6%>cG-NJTQ=Vom(90DW%F%e z*?fDXY`!fhn{V^W=G(lo`8Ky~zRf9{Z*z6o`EjLZG)VqN!f-H4P#&@w4&F#T7Vx8cmiBg7k5h!fwd){^;l5v7WGW9V?ffOkk!`m=ZkdcP_2i=-+x6F%9z`M z@TAR|{C+A;?$n?1&@NE~o}rzSKXErx;jcVJCy&!J zk7)fue+fu)g}Nl@Z2sr+l=`J^g*r~B8oy!?Dr~dl6}D5Tu$e-ItrRNNmeELYKUlwZ zv;wQADWvwH^5fMLPP0#oh1D5|nbl|QvAd*hO-aY@yq~GG8~B(S(4(cj*=8-=~VEu>P_u5 zf%A`3U>1>tc*)M4ETa|~E~FM2FQqz@jHT4l3l~$143|KQ^yxZ8VjME%vMyBlzSi}S zZoBfA7QDB?PNSMIkLn)z)C#0W;I3Ol%--rIz#BLysl*k@nCd z)m{4P2Y2NBzDm~f0cV7%x_q53iJa!sg~AOnK(k>;hvhLkambx*bAXJHPQ&7!Y)X}umz$O)-P08yij4~LWN}u6;28Y z^nd2F54f`xSOxk5`{Dxo;sX2P0;_R>eH3_~T_^SZQXyk5e?Od>e`p_-`hXmAWSPZn z=!@IX7q%fB`qn}SlW&n9z;aeciDi6XJ8r1+^>y9m2R85mJ^xF{v)bv{LHg^<7TK%9 zDY})D^Q{V5JuSVvwUNHJ^{}@sy^rc~goV>0!_KwHumcb3Jo$}ohgQz0OqIV3(x!Fo zq+9rK(DJ%NpSMISDms3KLzcT?He)U~C7GvmRw!Vh$urv#ICzO3^ZE1s!UO2na6KIB zJP$_f5I^d1e@7jGQno*Y06KDaHLxgmxe%YXton|TXF?) zv!0y%Y@ZM|Ku#$1f;PyJ6nMV*o&cmTlGD;Q1mBMd^y3&?6L!YpNYpYdnb%9(N+$8r zwvy?&w2i*iZQ@N}F5c#;c;Zb6dn*knnRrXvN+#Y?y;bT*f>Zrh{FyLraFuTEYTc~T zC1#BbUYu)mM4O@Gd8uyYV+NCIo~`ici^lUJs|2g>npNV9a%g`|_EVO00_5;m@_oTH z)n;N0ylPuh4{(khuF{?Z*yB{<9OZPwIpElE;2axPLQX5|DN`Q*&)+Z)ni-_PDS&*+pQz6P5e z2?X}DwjQ=US0iUXL+bRL%yTs`<4|&0ldFX# zh*~%V-0ZtXuXp9cHE;v_sdp8)ky81gCu<^Y?G=F^9-xS{hgSsdIY2SY?pn?2e#%Iem@$nna$i(Z$U`o^isB<}@yzEL&cg-W@36OJ;zjyA&- z$cqo;1OhDjDtS&{eJnIz8SoSK+wD5=5T#sRNauRRFx6S=_Azsx0uMB+J|GTr_h}Q! zyN}K+-%z(5>MLKw;I++v0vu;l4d?v@OYqsImH>SY(FN46HHW2EVzPlc*wH%z?qXCG zxTjGG&?j0Y(P>^QYO?Nn$W$`m*YwxaG9Q4~E9J%zX^~eP%>A#-eF~gxRy81w+!zk# z>wfdq0A6LjdVwUD`)V|ih){C6zD3<0puY0?06xi)C3?7-F!gu?xQb&aKDQAY5>nrN-ixHv>{N3kV`5E{a$l%1%aRL zi{_#V!k4_}!V1D!o_wT&Kt*}<3c`7+nSZ|wKHqcQU<%K_Uk1~JRypAyj#MY(%vpC6 ze5!KtnczBw_$v9BfK_5v$*~H(qXb7cc&#v{dAjRwrjh|av^rC*23$ocH?NS^GsO(J zn^8639s_KV_V$YJpIS<4Sh)!}nBntQQvx=ZKrF%{uNS(ntm&8|bt`8} z;5XKCyJW0@%hq<3%O0s_KMd{#w(H~4P7&$v%9e~ic^qVUq`+-7kNm{djdDz{2(Nl_RvW_Wo;ns<~n zZ|CTXv{2^*xrx7z3*EF=J~n757GGfDb-?6rNLE&QPu_4FP8AfH3v$x~ zh;3_R2D3vcAF21(iOVBCeoAWDL~CH|@=#1ACQR8x$+>%Ue*CB~p?<8GiBgt2F?lJA z4DckrcrIw8#%o#`_%P3kRn~?Ij1NMeQYd zFKREzdr^By-iz8x@?I2utxEf8uPi8FA;CFiN6$HJBsj)~HvtxUJ*TZC=Q(X9InQY; z$$3t6RGh9;`)j(DoPmX$=a=O?KMGrN+mu;_vwX#Y-?W&$z;~3AS0DB_5g1T8Kma-M zGSA)C`GDmeFndEsjEHCfA9=hLLeSFM(CBS`+ zs@ zN`RXiRl88(6-FgM?>idZd8+-SS!KXg`6af@!mNq3qp~s$fO`y3L^{$d0;dg73`dt# zp0-p{;7aDJ3M3ylx=7oZVhSW588_fWuLUHvlF^OxYLM5;=BN%N6F0g@-hDK>yqMxW zD?0%WG557&6`pKV0`$J4(VeN<=bKdqyg;cu&-l-c@ScM=ydm%j`}ub-@F}I7FQhlT zBJiyNibxgx$#%&lDtYi$09o-stlR_$CliKCtbhja_m)=`NXl-|kY4qQKvH&!NTgCS zdC220mPZfpadTe-5;=F@(?ojBD*}n^6p?%$(M&i-eO#{F_R0=T@Kwrn$*&wvscbZI zTodM+V9(x7-Vg9VuxDHo=AmHE-pw$*Ja#xQePj>UOQlwAb7ZTgQ%?_Ud3iab2Lp{ibd^_>Vl2y=Hc55P)~y5t{>7*o@HwSi4oFM9q9WV;K+&H}g>p>g z8bvpoN&>vws45Ug^2P>vVJ{gxZ;A=fCly6ps@lW#(~Hy$+|#Hk@Gzy^TXB(kjXhCb zwTskeY(7RvpEakMMz+mvx{F}0EF^--Q5Hxf$r(tP74nJEmBfEbbBYG}w$B6jd;QQU z-wFW#sFWLHr0;gRoJG-+SI|_q3(Z#z_-m!)UBTm;2n6b^oFPMqL?EjI!bfHvTLMJB zU&G`R9J77(cS<=2KG?YJo7XGGec9r;Q2p{-GC8IK2`RTQc2ZBf>sBZN5=5w@wSgz< zRvt;dwux}2bvOF5_66oR5B?a>|y?ZRpWIMIm$-*b0RUCc- z;TM{t2{<~$97S~u)m|R2Tgi~2qJcu4uMViEqz=CyZ&nr7me+iwvD_sydGtH4j{gYun~ljXF9lquU$IistIz~8fW=K-YKRkh^8|BsphUgaVQ zh)+4>&+m^S*dad-5`A{uQsZxDc_hGtjj90;Gb#c40-_`20@Z%btTN#4_F#1t_^MK! zm6PW7H<8{n_Kewb$5Ew~>|yZ?xQ0H}YUo2>z%4+Hcx1tDK zeuTBu%~raV(;dDr6e`T?qpH2gtfC99M0fF18TsOPOp{+TJgz%iWau2rns@$Xh1iwM z#L&uJx?y;MI&dt~r4}Ir62U3He`*QO++S_J5}@zS#L&@j9k1~=BQl`>yM0yQ6#aFL zTb4*8?djSoa0jC@;EqZ;TO^*YE@>pG9b~Dcz-jjTqB?Mmg8Q_Iw4vou2Oc~?5$Pna z2t0FuBGN3c2&9I*viR|n7c|#pmU9BU&K~ri0K8GDj>?(+O@yDAUJvk*q8`Gdrk4Q! zpj3W{=O=!<``<_bk1#3$^5+}nkuwIGuF6#d-Q3#RF@YharJ@zKQmC+LC08I%=zv$O zW6@cCtg0NYDtUR}PbnvBdPy58lW(p_f@GI-;qc~MxK=)3(8d2FLI0=~w|-3+R?s5D z5?W+f!&kI9*H~}sK>q6Thx2KCdFM(?IyMn7vh(uJuHmD)hL2wPw+DZE*d|@WH{WHn z@`sGxXhajUKicne>Z|E&+RSEEohj65^TihA=AL3iC`HcV@qCF+%WG@o*}Bcg4*Uz_ zwr_%26Y_oS(h7@$oLeNqN3?+4BNg0V;HZXK)-n#)L5mE>f#H1D4sOvLAEl|^Y$bFz z!IU7Mh{FPe`XH%_T9|0b$Lqx!`xV`GRQe}35q7Y{%|w!T$5Ua&l(S*shy>os%#y7Y z?p{#Cdz;Ot1jtAgj#9+|3X`CJcW6CwNddgqN}Rf^4S^{m7pKFb<3ZRQ$${3asM$-u z){E>G=!AdOCVmE-XTLJ20{QEia@8z%ERg1_qC1-+RqVO@=rV|)Z&=V2_&p2ShogUZ z3dkR?bZ0pvBIcjs!e;+jLy@zrW*~8f=C_STCQW4AmE7aR+g+AgZ)_Fa)2yrZ$-0%3 z!lE$G3a%Li`4|KAzpIKmiWO}fQkju|*g_nt5#@qfF2<2IH}*tf!%W`Pj&0_%jX!k# zRCoSOxAG+o@HM5@uS|Wea(U<2jar+jPs)As?k&f(Rn}QE3Q5Pex2cl>_c5vp9B)(x z++Qg-6T^xU-FvDx1U_t34fqSCL|MgnX5WKwv?yN zY;V4+(hy571Fof1d*!6zVG^M;IU3?=L-Q1U<|4iErjh~upJc59zp7fY45SVGq0=9l zZ57BLJavlqtHPtEm;rxfRJ0^d)?F8wN|b${?&2@f%8`bo?lr6E5(Aa*no1OVq3(L# zR5F9ZT<2xVbtvRFFLI~>uI9DEff}Z}Mwm(lJi@3duvaPRF_oS)#SHi-qoS_j>t}xzTwS*-%=`n9ccL9Jl(gzn*kqG%0)$b$k;q8(lg#1_`FhO zQTdU?diIci2IP;4%CODVz4v-8;8R9b`QgH9Yr5LRFf5XATbor1ywRu{kg)Em2Rf0(UV-H6Vq! z_9GqR6@e7u6p_B^6@fP^tsM}fbjOfNi>BuOzz_0Sp&y8IbjPNx0Mo{l+)Fr7 zUIunqCyE!S!N|c4axZe{L5%3#vq4&6cXraQGNH_qwZOuQgu5Z?$8}W z^BwieI+6daeBL0TnLXn*6CVMF7WzFfJe#ks!fCTYD_MyVP9E=x`d8JZp`H+#THYXR z&?8#S)4G*I20oW)MI}d(ZVflyR%8a`k>-3Q#LtUhxR)8Gz|R_01s&iE+rPj1Xqc}A_tQNUTJgtZ z`E#psNdnCLuQq^nqcY%OMpc1F8kGTmVpR1pg=^Yl{nd>Xj`h^u3J)?W15PrkI#@No zw1QJ04&4MmO3haa#Jy7-EW)D}p#l7<)mQ^ks~be5wJc~2NC%uE(r#W6Na9WriJVKm z(EXz(`d3Rh0nW07dx2LPm5}YamP9X*{A4);$)xP#Ch_=Lq0BKLKNWOWd!y#E&t=6*KtH2G7%7B|HCX1n!z$D42u}h1 zC`L81>o~K@fX6G9&xrUa85^c$hVeH}Q`GIHJ|b}TawE>sz5LilMhy7K2QvJwMNEM> zkYg*b=qt{Cq5AlX`O1Jp)^j5)ldDVN#-19ka4VxS;5J4@#~s4)Qx>_K2E<`LJZTfj z`%1(4_D@auJxe_y&vh+>=-RDYcO7mj8L-z=VXR5IYlc?=^2-Nl6L2Se+TG1Gq&@5z z_^2(oKik}=Kz>3YcTRvfbe%%-?(2hPk58E$K&*0K@m~bFNb{L*c_qMCjj91VwLrO_ zIK3IC6%ECc>SBqxN`Xt2lKW`Gz!mH2)P-%)Ek2x~RdNM2P92TXb zYnw{4zQPSX1?2Z4@}&vBclBC8A8uk8jz2njuk|h(&IfeYZw6O+LU;XbaFthd*MA0A znW>rIU=?J*{q6bpI`BZHIx90|9Fcei-1Qr2x;F=&HozRI-`MSE+MV$6@lvxPz);{u6sXbh8b}Dat#yRJHZqlv@=|MDaXklLIg5~-9tvJ&UfLmtyDk6s{=bN4-#$KSjnkjPFE z$>-6l{j$x=idHaR3Gl;4Wx$h+s*=*Po+2FMCx?3A<~EcG&?glwzirhgKk|`d#?eZB z!NS$Z;9R9zPm-|^Zt~=tO$6q&X#S^(@UYih)Rn&Up*(STZFFV* zmbP|F3vlTo>pK9Y4ZPBEO@z&rlq`Ta%MY#iV2dww^1qBcZ(M8d`zBZNv%k|NZo!|rFmF*`r<37tg;ZMq3WmI*6!iRO+TCE6w@Z_@Q zb1FQqTRGqW-}HL#H4#?wsR4&6)hb~(6+UWY$+Es)i~g?lqY8Y^s6I+&ifI^#~(&2=>tmf*Sq8+7!KL~PF0>X z#|eL-(C3&i;a0H$kFM^1rVf5%j-p2YB2q~S`=VK;#9GN>MMV# z2>c3C1`>#~_DX+rgvS>;%R9n{x-!Hxn{BKT{mw2{iH;el@YB(fK=g2%!F#!d?%K{& zqM@Cs%kn1O%6S9$9i`kEfcn_RhH05$e7KJd8)b&^;XXF(DKqSe&ddB(?GL_2;M2>k zF*Z!g4C5MO!$z55Tw`q5Q)U>~$gmu#K*kYxlu~XSk&g9>*oIpi$e{&@wL6m|d0)|T z#wQNsb}ta?+*hNC3o;7@vEd+H zeSgD2hBh>uqQq?7%A5dl=__~gfm`Usq}-d7r_GUeF!n@Yk#;n;?Cv0Oud%o(aBI6_ zod7KQidRzXtAQ_nsoMuE`id9VjhfG0mRA+{fKfHz5KFZRT*attRfQWGRRfMRD*6yM zPs7~r!vP;QDgmxzj%q++$hl4RZ9^$o%atgfeqZ#yf!OM`Qy__4;!1`&qjL0*nG+%?Pb>%HQ@e6WxxZJa!0_y za^{5=a<~J|u$=3_bCi+e2ZOCNbE8ujas=&vUa_a->uU--O!T?1iUYH<*3w&>Yq8|%~$nNtN zAqD=*s2Y%b-0DJl-YWvh$0;I_O35A1sp^ABq5>q$f7#bBEw3t&cg@K8H%=-#M_i;1 zzHW|^s};`k)LjY}cq;62rNc3!bt~b4J9oNWGGcoveA!cjIr4wGJq3QutR@0+=sJhw z-ACse^2DcHQ32OA_kF;xDwVr$G?C_dMc_RH6p6u88EB|x84^qKW#okZ{H z)?E}Jtzf=VAUA{Z=la2`TBq|Xig20{09*{|bg=F_RJY=WEF!)m4 zwUWN>LKX{~!Y zw6iH@!2OJ>0*jY|@dKcI7q+n)mOVTY>d4v(OXfQ3WQ(5x&sC~?e$3Ln4|+r3AO4Gm zX_;Ys)qJhGo$Dip)v&8@6%?v0R_k}X7vNfU;>wRVNdD$&2Ar&l^76nbO@!kHSRHE-6&`L>4LH%L1o#=FqVa!O+pv|Y2_g?V zc7Z=@-fL7%iDe6DS5>DfnUp}jsFG%dZQ%>62P{|y{F_mAAlC_Q>LPX7xxEhLLZW<* z-=Lm}l$Qg3+M?FNTzQ}2uS})-dxd}XRA@C!v)jV5%z%d}Ri5R@z)(Knb~Q2GUU#~8 zDa4PCahcTbqXPeJR4?!yrCcIN8|XP-u4sXqDCHE9Rv7AvF8S6w&Lbs{w=Iu8Adz$T zX%lH9%cBoSWT%Ma^N23or)e;P%cTyG;PQn$kjVcVd1U0lU`Q8%#XK_W2ZQn785jPb z{J(4vs&sK@Yj+jM+wJ7a0O)%i9eemp!G*P0ouod$WWJM&6)y5rxOC3bT^D&3;0s1Y z%k*q5=?*I`0s4$;w04L&N`PFL%khz(Z0ogvBqv%V<9iY%MFxBxDLG}ci%)4Kt0`8A zntz05O2_5qRoK>8CGv8Gdb!K$j#Sw73sZ>##VV1P->UVW%}ey5I97>Pcc{{Ob}1}- zm>#9Jx1&`C{ENMisRsPJQtn8Hv_cn0x*BkpQce-+yIygyJa(}>QsA?eM;%CHcPK*Y zGWT^Lk)0xv&m$Tg`ay8H`2u{@QtJicFn8Z*B5h)M^a6?K6vN_ARL^Hv1U|!==5*b4 zxo%gj9C2CajIP$p$u^Xq@4}PWYLyxCd)$HoJBDaC*UVGCtW*9O>Ai#%L|&+88!fTa zizTgq+~;WSn^#V)y!mk3$}_(R(ICLmhd;fJdes=!dC?9oRDJfP1lA z^Rli&AEXCy7yhmp|3kNO&IVR&p+tuZc0Fk-^$)yiD2_Q?a`24Z*Kp4fLCy$3x|}bD ztQotH&J&wz);{|xR{Ppos{(oZp`2lXKK1BW8>XIL_L4h^<{SZWRd%(1n&$Zx>vD3H z!s|U1PL3;d*Oguc=nL+>QVS)1$%$}fb?^!A2p$K45P6AJA}zUeKC8R{(0AI~TJ!OBc7 z&~kWCxMU9S-RFn(Hb7YxPpF$`tUKFB)r30B%XBlnYS>b@WidmY<@rn0&#AhVB?shP z?($O8g%t!o2)0+IjREuab>W7C578@o;noAEo*M?Pdaesx_gn?cmlfh~I=JEWrht1q zHyM1Ca#9=c9Hm;d*)maZllJ2Kg&u>)o3Dw-DD3xC=;^G$lT0EU(I~lWh#l4Nd6xN3 zfTS*lVYpeU{gPRwz^CnMsu%dYQu$FNZ6a}wmD4Y9BRj#Qz)#z8KDrW%lW33x4)chO zCK5j7lL&Atjo5mi9D$h5`u%I~DGS?E61Jx#?7aT6u<>J<2Wb;$TYqa9@^W<eCBPZ^a0pEW87c?VQwYM>2OvX!VOBwX%o2R>IFT7tvvZi1z~GXE~p@Eqoka~ z$AY)@TsOGeb7R0ecy2g&C(o@1-q~}*z`J;^3;dlm3Z*#c|BYLfhOLsD1aYHM8nvQE z6fGcu-CRKOZxpQq=c}z#MEbPmD;|NA;1qrK4#hPz!Wv|_<*$0{Fq68RhJlQ5OAmn& z7IIP9a4(F8TQnc3gySvbf=bDNk1ZMS?veo?Q!?PgO9p&BI!(7)#e~hO>zeqoZu65P z_y@LLs=!B-lJ__CHxX#0oO5p0o-+1Ak;d&dGpY>jUN*EB*Q&0y zf|IbI^VGu}?YAtj8Qcp?U3;pLqAyBIR|E$ z3pWYOaa_0tm~|~&0%lnYHy+Hg7H%AvWi3l`em?^1TF80*2rO(N=k_BoQ2C1PN1)ph zXAJl--%y}$=(I869NbU4#%z)a2P|~2yQF*FCEc4`(!EI~-D{L|FDdEX_^^9~>Li`k2TvwwkLZc)?g9y|jbydK{sPPXscr)+=*3ASs#QIjn z*F;a9rtoZ|qLEstyIwYx40!6=#gRg~P+1u%;B2L2!fyl~Z?C+}XK6T6an!UdYTAsW zrbI19h({`p&?t-0D2dP@0<}n8!@$L;@ksqgySS<~DFJ@Us4BkR^3-T;*Uq{vx#(D| zzCWo}t#dfS6mwOlWn|jY3kLvM4{7%oiH!pnkdqW@&BrjmmSDY7n=a{by zc#Baf@K&YD`?XN_u4~^UWV)L;=25vv3U{*14}n ziLXZJiz-H$uPjvIkA9!#Re--#s=QMe@_R%XF5veHhK(i??nE(6Vxb!R(k^A~tN48OBH5nHuRli?C^H;9RkY=`0Kj6z z_{RS{O>w@ZngJInRbC^8JXbGARAA9Ct}!-jlo`e~F4lbh?o$PBs9#-{r;6bQ_MCGH zEE>kCKBtk;?yQ_3e+C)}+x#i!bYv1;j11RsTU*!+c*Jt^#qe-5Oo2tiINwoffVRsQ z3ERQ)out;sTG$MDwNmB%#qcUKOo2tiIN#W?QDzuVg`+eQ+OAL}f(};b9JT(j<(mN? zF)9WAOet48(l1Og11=q)7#@#r)xAH`ZF}W}VPK*UshpVqJw8M-7*aVQrwP5d-~s%c za$Wg{x6;3$PIhbPce!%P0IsK$s}Si3uL%6?0L8GvI6_($A#Di*TSt=m8cZ#0T7EI#RgR!3}$&G<}(H&#edMPf_Rh9orC|R>l0ri^3(kZRrixtjnxfDe$*y z=f)KYZ?cr%-&X@)Sh+zA4foXG`&beQ5C3C!RL*8nqk!X;n^Pq^`522Z$gU%rq5KoQ+VDY)Zqu;bh7mUA7Q>dlu-pPFe(8Kx8$l}5hW{rscNrp4?bkT zyOqjkMtqwGL;tX63cRRbm^P8_vIr@#7$H8>ysN3<)?HvA;g$;wWPCeqBqE_5_I*`N zu3xw9m8rw=p)6BRn1-$4d@vz{>7Z8f2fTVmZ!@Ob4` zl5hJ?mp|sa(a5&u!OCSN`$FFfRObcV$|VZ$Y<-}ld_G`!pgney0(%RFX%p!zuLvwg zi08vEH6`4-5k|r-BaDo1r;S7;w8J($t+5W#B=h-z$1fH*Fn*UaA8@&o)g9e?K!uLy z^8xJ5qWSQyCcBm;*4+fJr(AJ9Y^>afl6_$#W~t71bu04$$Wuk-^8v$k{nJ9gEtSd* z(k+HA@X{Gs6scuTtfyVt9)grof_MoazEK zc*+bj;LFR6h~Xd2Fa;J3M{0aww7A!FQ1r`nCR52WFh7DlRaPU+&HNzfY(J;QpF-{Ho z%rFBUuT=SPV0eTXrof_MTqA~unqdQ2G>mJUq6Qb6VFtWbsq$1YywD6&V9_v66~lAP zumLO@#;MLxgYTPR2E1RX@>DUr#|%?o(J)SRff_tzh8ghXjAJaSccDd5URnyjp>Ea0(5)qulRE82#a6c1>yUs=%PKK1dS`AR~o6?E6C zy6vc((BDMZXE}Bng;FJRU}9Fay26I1CMcwIdB%_W&NrM|%8QpuOjl<2V8ajSO9d}sn-A(Wc%H^K{ zPSyJg^l4bhzR>pq)!ETM^fp=H*E}_t)!)=wh7|Z2v+4ulFmGGhL|W(-L-)T^xA=7T z2#|2wSvf<#aYVu`cMgyV0sn4P{WXQ{`Vf;W7htzh(YnL;63Z|JzHGjGfy8h_i{#x$ zziYw$O!L(MUS!naz{{0#3l8a9rq}@9Yt-Su=Zu;FBtPd4iKfVn1)wj0C!uVVUe&(5 zXzpt`@>bC*-%_MHM3?$agvLf>T8XXBpDQFx=L z2DAFIsiZ)x-MAy&;}wC!^dUK?I9LQ8nv@{`;?s>45^hBiSd0)~7*hFHEwvsXKJy4Y zO{9mtBCr@CzM$V<4X!i8D!wo*xxe49+9V^3lY$;MM;Y)*rB=_+Q0~VfJB^ZqseHE+ zwv?Fr+0%&`@Z!Q)#9ti5hH05$d|f(O-Olh4!=z^EuE)Fz@C~DChw6iv-?9fXYj-QW z*Qo4Kg-;n(8!X)Y<~s$xV^kgZ33Vhd{(bE9CKAcGiHmfT1+4>bGxIa$i7_M+cjidG zj1)*YE;^Dgt{xV*zQ)_aQpvVbxR<9$c(SKXPhU==9TwDPAjj98`Sn!oLk(yo+c!NfJoK=CxDkVP{YqLBq_IhD|=IO47O(g>!y`EE+PaeSQl#)N2@Sl^KNZ&BFtdR@; z$0ID&2qP`w`e6!5Jnvdmy6XJi%rf9A>r;9a$lv=epDhd2$8Wr^FdTp29fxu_1}@+C zikb}C@`7}^;zYtWzv9eB#?QE+_X%IpAqv0hsjCz|>ZvgQhVJ^bsU%q4;Hl7xswtx6 zB(zwqSKff8XTZ_=9J*Zn0>>z|f;<2)v}^1}O^B`hjz((-#5R6M(%J#Bt=}=ewF6>1 zzhhi$2Sm5-=*piAXzhVnvN6d=hf3;O%j!#kq$nSffjD%BY$WeKx(tuqH*h~v)0M{) z7Pldc^5n7#!seb_T0x-YV!ot;K)Z9F6$FwOQhutdzG$p)7P&a$jYcPRO-&!199!W|wPm^5+ib(KG##giuX| zFMG=8=Mc_!DmVvkYR;>~JJ(Y{QfU1q7~xv4M_x3mWXWBw!3kKb5Ks9pKtoq$zY4u6 z@Fj00AbDH~6?zgX?99itgrjtuC-pnUi>$l^c&_$X=E9Q7FIDK&WtiKJP)r|Mieb=i zYxY0Vt>pDng}?PwXmx0iYG*$0hd!a~+9cCrk;qqGZb7yknxQi%-wDc!;+&uaq24c* zymAsDQAc$kb`d|8>O@D&% z{I4~gpp?;SFagN>1J6OcarBUG;)~i#8jKY=XoIy%49lCgxAx!@x^1uQ)Vx|Tb1q-& z3zU1%^mdFcqpBM52;IspXVm|qW+iu_m+G#~HgN+gpFDwkZVJ^0+(#*Q@r87mR}5zb z?zc4eDR4KlssnN8&bdh5eRN94{o3Zf0i0k|6^NtUeSB}=E;aa}Zu4mae%hSXfU9Ww z9hH;%n+WSzP0^>&?bXFT<|;W_wa+oD1bC5opY~YT)5@XhVh6LEK(BBq=RjOgwNRm_ z(duZNiKk&uw8@ONBd`$pSn44QjyLd$)waGmzU@?z)Uf!!5k*C$-INtY;2#GlIwSvYoJvY6zZ>qOAs8< z6gg31b(J~lCDmPQ3iSfXSH20J+2#{;=zLA@65Zx&0Q?8#BqFIFXPQ-Vsitz7rIY}DmTBnwBy~VH+bc8l=O11Z zoeL~j2HZk}$vY3m5ap)@&O334Fz>0Wj>@Uin+Tn1DCFcO-fr{c^k(Spc6IZHW!4LP z+ak}e*hUTWM8P|nvm{JmobIZbN(Ma7sKbHRDCNpQy2mRH=Kg3?Nr7h> z)d1qq9jlRUGQ||=BQ^$$*f6UGkSb(+fW*inHkwG@eKweT9LNuYfmr9hdP;otgubR~ zia3zdOsMijRk^~dsfH>Gbk{#kB?B%~$_>|GhA*073dBKM_5H^HD4)kwox_UwS~OWCX#m_eU!lc4D;0hV(n%<(ygXg2R>g2 z+Grw;u$t;X%5@%*e0KG)_&wD#6}!t3B#L&IBS<95X2ty4 z%>4og-*lp|i#BYcZ7A#t3oq;n8<1&C#w0&pgRj{1QE((DJmOG>J9!PB_S(IEn?x|ksT*={b zoO=0!&Cm?^o>6_kv7=p`Zp9)UudLkV2Yz9IBGOm9V%V=gYp`c@n>PpiswI*FS5{B? zjUDiC<%U+KR!**L)I=Vs{0hPjpIR9ajn(Puf40S`0*6}0HL9IpR5h+EI@jPEt32V* zEa$?09Id(BuG_pH;2&6?32+BXstzPyng2kaM0ZIN@gydR%L_?>uQP6^Cith8SnvPW zkh8RqA6h{f@cUc1Cdmg$-~&pz`H1x77*hoP&8Q5x)|RFfHvbI`{vnH)0%sUiC)}mx zyAHhGs1!&hCChX>)jrm&`fgX~t)dS_?V1Uh$>IjC?UMxFX;hWGcd&4E;J!vxfd?Cv z0I5>Gc%eG-mFj>#^=jPmXr0W}mOr4|&dN$d)@~xbYO^81Ek2!MID*WX->Bh=@<3PD z*il_$M>iKK^?bZ5^g>eeEqn(2xlt+bcS^OMxkh-_>xG$@T;L4XIeClC%?x<#hh27V zsw17OtoQ=ny=_qu>F3IdBJjxpiec?>Drs3NX){hGElVYBlFB2NN(wBd5??BRR=e@i zRxU|7Rj;|VgSYEeC?NUBcNXWhBao5k0guo$T6zd1B6?v%?%l>Qzt^oCSAi?pDD(nX zQz}1h6Y&|ZX3%<(v?(N&k`!nJ1JU|@Ji>o$&Lrl(he_Ipb7M(mDl{4F#2+S4v_7g}y zTYAhN@+tY2G%T`9rrl+o`Tr^PW-WiE%Cwp7mvv4%Oa6hoyJR2SpG)?^(Y_Vr4+yp# z(nK;X1`F5IVr}%=+qpe*WV&17{hk`kY7bLMfmr89NIBX>zEa$7((SxDMWoG@ExAa3 zM^nAsg7)FwTSX`63sw6Dvr5R|K~IGRQq8warH0inJOzA5DfxIm224REH{1`>8b77m z{OAO}+Uk!^&TDV)vfM(qa_9qo+NkPeh5ep7Tj9hVoP&}_H74nEs+WxXug{;C)8b&)wMte?+%(WpnRXM?I!nX#?=LM%95&8z|^QZk+1a`;By=A8@QuUb>K&hiZUR~r!8Cp{E|_1B0uFbz~@2U zH?V3{9XP?LC!Cqw2sjjfyfL%mWrK0X}C`oydJY z1AJcOeFHBust&x)s3-%%{L8{6z_oX>f{A>s&j6pddf&i1jj99hGb+k}FrzJ80^HB2 zI+3698Q}9V?;H4Aqw2t?jfyfL%wZNT0ZuWhPUO{WS=aITlJ^aK&8Rx?U8AB52=he? zmjJIas!rsO`3&&6^6rdP0$kImI&c%Cq6`Rgi-k*oKR2pQ^#rR?(AO6@)`z#h&G$!k1*X_ZMJi1iUP*;@90TRCR4+}JgU-Kfrr+52*@VmT>Z z5cZZnCZ0mZuW2>p7qvl zGw|#6OJPU-74=uHj2-XAaZf8t5h4pBxti(U#%PPxZn7|r3-q!`tAa(+w?3p9Q z1D#^M*tlZ)c)v9jByHa(Q%kyfM=Te-4x@H~bhX^n+Ie{t5`W}TcoVM=!gob^NzkY= zs=~+c`Y>~!Ixp;5LT6 z;l4H|+^>s$X+J@uUnjf7K@DOr+TTfuo#&tiu~$22v=#S%6~X&;GE^`2Ip?lPtRk_C zsagsK9TclzFh9jA7)Xiraiw;Liy4oCu@$G5;<4|ws-<{ThiWS*YeOx?Wo@XX(5$Rl z3N-t@-Rl_Z3ocYp1%?R0LRjq$|!E)vwb>{2EuIIFhVr9@yE494& zVmb34IP=Y7H+AO6ij_fQzPY59H$OHs{}Ro<=FAtw%1uRXdbRkq>C$}bO8hz=YZJe& z$0mwb3ZUC6URej$EPf-eTM)mA$3}`*pP^ePei-HOuEe5QYA6i=yJo4OoS2@JONx4f z=WbHloelu)K~|PBp3W(|16=s{kTm%el8giL+=IW!uAqU!S zVWSay)gczLwXN2TL?I~lj)Y*C9(ibT9_qy|8Y!nmvA-i^D_$)*$MH$5oMXijt2iHaAd9q-qCQ?e*h24-W^8iOYNpnzxfw6z z=H&;quWxQ^gpTG_a}MRD(ESAZnC^TP_GVHJC&f0r6+8M}-{H{E@90ax-x=T=xFsW>CFYB@DqWt58E31K6Ec zLn$-e$g8280qn}Fp`-y^kXJ)l1K62YLumszKd*-J2CyTqhVlk*c3utT4Pbj-4do5s zvI;enIjm-4m9I!H%-H+Plmf*Y?6NPtjQ89RXLauChN5^p*(nZckRipEu>-$PLtl}a zWkdWr&QeR-QcKv8UP^!Lv>L>=A8v*1k)@pChLl3)#QwlRMX@KxY}J?4l81~QDu}Nb zSJXrDE76$w9<2CP9kxSByy7vs^}OCpiW8&Q7DCYvv!p{ytz(M%dS|LZ?EMa^7yAGq zn?<$$-~=1QzTu#Hv2P}H)f(`9I~JJmVuumR9;(?iqbRF#Q*km=OM%+6mRbtboY%~c zm#D31tqrvlu(hF<3z#-s+eK^Q2>T$9VZmJy^a9-vyMP)D|4Uo{O?Jb+hS^46 z!&IZMVV<-58ru4AMlOu6mLqtOFGaD9ger4W4=bs0j~nsKFIw>G9A~Xw>}4^<`jT1; zyr9^)hxC(G#UZm94{v1q_L#@?M>ixTw-^Pnam925-86gQ5pME|eS{B^@Gi+?WdG=( z2C>KU&<828lO5C`_D%<-9ych0yR6?UJs-b*RR!yZhk`1%F3R9?V;c>29OE2RI zZyUAlU_Wrz7Dfgr3?Sp)?p_+YpLEUK%%yp~%dykuGt9q~rE8B;#=eOXT?%`nT2Zes z8$yw8A}_mH+aPv0Z{X~ju2wTq><3~G;rS$c@t23!orij{TRK~fV&%q8dbN&pg7sqO zI;c_Xwy`+sOKK^)j0bcdDEpn}+?4r&zpZwD2`Rx(=|c`5MHc}}E3>?ICr6g!uY9e%ZLb%G6I zmpZ6X?1u?mwQ_uy2sI{leFrs){f>hg#7=Thqu4nPY7l#!gBr!&OenjAM>9$#!Jc2# zy2SOt{Pdn$%7f05YTxRl&B;@(r4BVV)KWfVLv1C+#-Wz-Vt)cqEv3fFs-^5$S+$fP zE31}rWM$P-#uS^MGL{Sbi?LK^f6LBhRNmFRB+;1GeNL-h>^CrEyCkzRU^ia1WX^Up z?9f8`msG|+@Nh~bwVs4S7%TDBTv^tO)gWeMDm0X=1sSj%R7>WvJ2;U3C6&>^At{km z2c@k_LkGpy`3{Ozuk+Q|!w-OE7@V)sty`UotiIF`6L>cwv8Y&D9laZrocxcT%A z#G^Djgo@^&hIj>-aa*Gv?&AH4^;+DCeUGH2WFUcJz19lmrH-C2IMUk3Zv%+EjF1_O zQ6;s0=LN;Smk?BI=uyt158ZNddL9)ka+lV~{w*;~rap;bp{)WtFvewmL`nRy4%?w5 z{sf2ZSQ3At!*(i(pX{)mOX8tBU+p{G8I*09562HJacxE;=3GHR}#O_Vf&TDFLK!aCGiguLp6(ij8J8+ zEniaONe@<()Ogl|l_fQv^I%m;jlX(urIH$NcyK^Tjdwh_a!HM)9voOw<6j;eR8r#; z4-PK51`7^7TD4Tk#voGkTHN)Y#C2l_fPc^PcyK^T zjh#HWa!HNdJvgwW#@-$rR8nJq4-PJ=G17ypl+-xVgWoEtF~);=w>n%$up+l>>W!%y zE(iy>g`q+0cbe_A&OT#GaSx|hFLtzpju9KTm0qZ2tIjDli+#jFjba}oWa4TrsU;5? zJ98~NQcsF4{wT7?c}VO;2i2cJ_A&?Yw#2V@Y1{R3bF$NF5-Woy^!k!o3%sD%Cka_W z@6K}f^6LFgu^{&M4r&xDTNzuO+}+`{3Su8{P?K00GW%#4(*6`z=c6|eh&4G=jbfGm z=x2Y`P?j==u!kl#8)Y412*uX$4H`Tj=@_EMrXE~ep~f%|c2}senFkkDsIi3yyDHS! z%7Y6k)Y!&@ofT?q=fU|EYHaVpjtVut?ZMdGlJr)U3jplhGI8@ivLSyF0!b`X_IU`Mo|2E zC&gk^<0^tiQ2g67VuEU{9m|Y(Wi4{8#y?|%;$xFxL6tS`|0=KB$MU)d^Et=ob$->a zII>-&CT8VzAfK-rY}ezg@dHQ=_WpQ_eL)(13T56Y7QB`e;3uW5e!O-%!*!Dyf`lA7 zfFX<`In}D#Bn- z{=hoa;71q>VAYd-Fjux&{&rF$HzUZE!K{@38)hJyT44&XF@y<-05e^zH z_C^Pd)hJA4;-M&3s}MXs84L@g!qUV%dABkg6v&0kmVvl1X;I3m;On`@YqTnIJD0?3 znBa0zr3UI;t}zj)#!7CtX%Z{vk(?SnlATN9V@u_t%CN8$N^DuYvPz8wTq{k?3h(Ev zBe=aXwSHnVR3#~*NG>CkD^shsLQxT$Y>wdyeg-L?b&1tRZN#)`DsYHB$JpO@eW)#k z8@f@|a<6iSs@PcNznE3|FS^RtatdWtzE)E}=`wFonQJYDlr~jg(=DoLt*($t7jR2P z0l%10z#KPU02_1t-G(%)dX<89w*!qRiT@cfya6b7zT1@W!|iHl&48R%hzY)&bxc!6 zGTu&9L1+s%fu7A_)f6(AO7yDOE-3y+VyIBD+SK7uE12Rk*2K^8v1)9!UKug*6L{=| zHL<@Ygefq)O8wOE8r_}~?P&am6v2sIof|96iQU6N1+gj+NQu>AXY7kt(HOB{0W@M8 zaHHOjG>Z2cHeMiwZgGkY_Z?C|=W$0<4FVDy-|7!!i5*6Yj*8Vv3r(>)Jek-!d2-b1 z3o)@eGa9jvPPL(JcbcUTtK|u+l@!oV$>z>*QkL<5ziF+h$W0L9uW=KjAXbMkBPL!& zhiyr$=7$jzzrU-$f>_ldG{ve6ji&gQT}h5s_4!#gT5P-^#jBXij>)Q1Eg1*mRZJNh zs}WOORk(T?trAj^KvQhIUc{>+ASO0m9O8d4RpUAO)9IF7opl4vbP0{lDj}7VHZEum znQ4tpAqAvDJK7c6=(%LI&qB)AljXi?Rec;=!IqKt%T-b3q9w{CTYQ@Zg-1BQLGjT<8vP_7=DQPB-#)3HyvWF0>->}4RN#pYmg7+fEvL9 z`QzLm7sP60BV9GJhFN1939iT@5DBixGGGNWHW-zRMm-W#Lv!8qPrN33B&bHb2*hjT zBSAGZlZ{33n$?k@j-&T+)FV*itueNsAK-}7eV7iM#)bGvJd!}Mvr3I8V^3_ve@YCy zpje$kBV9G(PawqWq!|gSp{>G1BmQ!hNF=C+>cR+$*FiNBR6|ErBPf1Nf1K&8TAPgx zNR6O)9cm+sYUp@t1jXxIYdgcj(dJ?V#n0d|BN9|Y%Zd>cuL6n$)zB(p1jVaXB0)7& zEJjd#tZ+K3)KCE#LGfB}B8zHh=P-iewU|VLYN+arU{G^86a>lgO3(6-k2 zQM~8J6ROksII)Wq<0V#48Z+Jqk%1GPp@LXFFMyUJ`I$e4i`9afVOv3ZL&duo-2FaC zu|CM6+$6X9KWzsv3IF2H=ZR)zEu30DGpYq4#V6E}p7}ZbbohPgNsUkBckS(E9`Ex!8yO zwzRl1V_O0kytG2-5ej}9wJz%^(?a)@=@zcG2ykJg8n+X~r$fam%t%fR&6~)L8nH>V zu-^d9G*z&=g@=m=Tzs!`YDJ(L@45MQv{;>v@vqfBP&uz^vwTTN-c5z0#cBnKjH+>$ z>-5oLbzcLyWtD2E^O3R|>b&WXcpV@kK{Ygtkx4aTDSIH5vbVWl>k$kzJBH|4O6>V- z#}KW)I_*W0=||O256@hYWKc`F(D8uWhrj-+B9{w&3lH534 zy8jtdf-t;?T--xB%|2@4%S0+T>1F(K%{7$1o74<}_>Y~X7O@H|g`nRBnnbayr>+=*46aO@JR2$0S`_ds9PBhVQpb13Z|PC6jh zmOBgou87*l5rVpxo-YP6VDl*&5W7oe0#KF6OwSN(b+qdDf03JK4~d z8G+g>b)OW0x?5n#FL=u2N$w zJ~fWsdsjmdMUu)$uP^P{RciRshNE<815|0x=KBh>g`3 zl{(XfQ3RKu4!Q$?}!303B1 z$)MX73N~e$EFLkNQIEsLCj`j;f4$=}1kB40E%y%+1a+m!4&zIbxUMGJWyKXR9--FAR!NhB(;j;p1kEzc9450PFq&UZjjpe#MD>?01 z$w_Z<>dQ0ELvaDSqAo?N?%&xLAAj+gnYQNsOd833!A9P#q!}Na+mX)3IH&bblJ#+n zem~_hwWTRPN`{#T%Kkwv`}mnh@&!`lQS65f8Y@Lfl^B=&Q4HCGU;Edx^F zd{n3^B4fOZzLi}30_LjD;}tHg0F_QTh$KT7ryXq(eFO(JCN}P;2Q5!u#`zeV}7Vs2qWz=6#$}`eZIr5 zq-W-byN|=Qh&{?d1+n_19B$O~4877lFK-dMnu7{r^|3f8ik;%5TE52zUG?sPSBuyd z2NlHX@fd9B8T+a{`=CQ&s~uD*mzj;-yIsX}W{T>d;>D(^IDG`EO;cHaoY}X}LDceN z(HMHPf*KBe_!$+YIP?YupmZFK%7nJ8j8ar+3PL3pMj||nMR*vH@GvUjVQ9k34U6K7 zsyYlV0>j86FbpdK!ZokpehX7=qly|Iji7wL6sVs zS4J@Ghrz;b7)-tRCvUK^u!~g@L_WffP3L0_eOS)?!j|}p-6M{so5meacOngG zt%h=1deUP0qPO$(xe$Zt(*XJ)fWbmrde*K_rDU93F5$!WSKUMR)ERCcz9Fs8Gi2OA zuEjUc^zk+%TdY2Rkl}j_we;3oRu^vJ0;jh%R>_@`TlH(a*57gSl0ZG_U(LKHGOx;C zKiy_T@5_YO!+govV|0oFSzM_%0%RltL(PTMP$Woz^d4dmfI_WDc=w{4Hkj_L(lZ#{ zQ$?UY3pb0#B2b@-lcxym&j&^?^Z+Qd4=A*rG3*)fcMJ)wBdU%eq5TL9Jw#v_|KFIS zuSiXih*#dQ_sHv>ZeL67Ju~^irtk4lG4=p``asWi0qLH;=ss)Is3%zJM8@V3+D2E} zt3vA$7}}4(&_e`Ml`oH8 z?i$1nJwHBdYHdsuUjr7q&4qEnurTD|YUiO|?9)H8!svk5rG)Iauhq(*#Xgh}RO@LkDE7;QpjzY4&P6X+6sw$B*J>$k_yma9pT<&M zUsCHAF4aY`@l>Zv_!y>G`L(}zqn1)^e~?}+rC2{ssJ8NKrPWfNC9SrSZKc&xvL&sy zGH#{SQpP2%w$jeHnS7;P(rPRBR$49PUeao70Bokz(f~+WZHjEh04XQ0G7EshjspsN2Po_UARnRS(s8yZ&PF%?TGDa0q~mN+ zoX@#9Thej1%;c2$)J>h1bm%SV&|B`{%y`Gmkd~GUY%h)_#RHW4$Uf?!w`W_a)wpCq z$^!oHZXA<6N%6yqf2i<3tT^5Lu%fOVNE!RXiqR!+$Z|v3x2;LdyW8d;76|3S>|^`+ zs-%*6(bY+lhGf%rYaxv~_=}cXjpey6X=Uz5=dMytNVPmDcV^YR ziov)&EvXJKVb@}p%30Agz(eBox#wsQ04e#J8Gw|Pt$u7x0t%NKK+1?O*|D3jWFIGm zRJw}C_7^7}%Jo!~!cZ+5Mr+Y9V2g$^TQm&YqG99~4THC6fAQl+E({(}7&)LYY(Qbm zfWm+Qh0y{ELj_bW&NbW$Srn@h!HvW0iZJ*H48xDWumceob|C`8PDEhXjR*`o5`pEq zqPSPar*NX_5ytK=gz>uzVISOuupjP1*cW#p?2o$;_Q_o+*RLPAA*$DezlIY&*(Ri@Qk~-N|i* zP2?ef43DjX~XnOO_OrHw_9qOMv^_;Lk(n4@X$SE{TkJz;i+;vZBv+raH8Pk ztTgQ7(ohtu<#hnca?rBPOJVWF&fQ9rMAiP(rL8Dd%dte2P8~XgD}g$B2v_?am+PWf z9X}+h_QP%riefbe64gK``{g|C&;M01rgM_2g>;|3;rT^#3CEBy?ByS6G*cjzjx%+B3FEYl%4cF2NQzjC`LP`-*%J0A8F#o6kX>7rPjAt&@dexn<9z+hny z3>J1lzT^lCjH=mh)s5l)3#s((n_8LDwu`c@6BepY>`^>H=vbtag-#B_)z--iCd4XY ziH2bdPsg6B{dDYO6}tk(HmDfo7*OaFP}<$t{)WMBNufuJhE6RS`n722+M@k=$E2KH z5ju~+(02ret|Kt?9Dys~_}nbV{+y{y!`!(Q8II4b$Z(wA7&N@G+c5Qa`8QZ{`G3B3 zQUsrJ(woVt5OmTunE2J)0lOg97vgA*i_YFgQ~Zy;rdZ7(oWjK_u|`v!oa^onM~nSA zAtNSUr*c>elW)YrK@TT9Ca}U+Fn|<;H=dfKdW5d$(zdvDKX~uC*0Dv^dV(mPn~MD` zA*fd6c~%|o-HX+eZEH~p(<*CGg{wqZRJV3|Olr|EF=2nOO{g==iHYQtmp5J6HHlq=#S_V? zq5Pq@N?xz4yC$*9XQZlhZsMOzh*gFox&9LD9ylq@>WI6b&L~KCL7^%xcR{f!5O<+m zFum>eig^cOw=JT_b>&1==ve&bS1RTMSO*cP;R1V)hh(ovvZQ zTJ#mxstVzoOnCXx{KXUyE7#?wiri{`Kvk?F`9Dn+g{C-M8HZVL7Zj1)y9+BkBjoc7 zrr&HH;#*m}c+ML}V8lY_29sYc4F(gh*_rX!SW)aok48=W9>i9{T*c>X)bzm>zG-j@ z#CQqI@DAqTkyt*&Kj*L!CGr1s*bc7q>vD-SZ|jLy60&?M-#hwzOI)F57xW%tv78AS{Ks64!*n;@H$tbetkVbN9-0kJWHZqP#PK{+A z{G_DD@JnN!)!36DJd2$Ympgo}RcawMDG>kfc`<{z%WUJSD`Vh;Y^=__BgjumYHZ-a zt4eD45gKFd_`hLVO(+^zCDLHxl}Su}vC5+n6R$)JW#%C!c8P-uVl@D$UNiCx1 zv&OF^#XX83yVT<@89ITp$V8bnxLM<&tZx4^TT@1NEcqER zO#Fky@NwcN$)3lGH>%=qA_lR0$S(1a#%KJ^)a|=iAaOUsd>u82RYv0C%0`JuB3jpf>PqFnBj4E(s-4@+SdB2e8|e`ghBGN~G3a#ebuKB(+ySH@cD+li zFb?5Lz!NSv#Up-UueOk4oW&mJprY8x4l0BZ$jx@nT|w-D4l34MZuRO(5tMA6?rn=b z+d)OKmpCXDf!rMB+!e&0;-KP(?7JdC1UJ*>J>It12OU%tyVyag2;}A*=dK|3ItLXy z*!O3B4%Dmp-nQ71gNkAmFUBey1-ZG$xhsf$!9hi3Uy&dOf2W%dox6hA&m2?~TlGup zI3ohNS>oIk#18(6w2G_$+_FcIA_C?0Ip?k*_7w*e#VX#62;^o%=dK`jF9#KseMN!@ zhOt+}eecBX?4Y99ItQgjL2iz4?h0bt98^@_=lC2buhrhR*mWFK6sveMav(Q9cJ2yd zuXRvSo}cv*s8@$McLlMH4l0TrACojZ9x!bc#Rv%PJxa~xC@`wIu9B9NO6oV$Y9Jsnh(=Q%!tMYQ>- zw=MQ52NlIW@1Rr!a`S!Xt{`@bgNpL}tdBr8-|)7@E^$y%?8gpDMIbk4J9h=Kzj9D< z^((j@kYYB4R+EOhP)V*lcxqWZ2#5J4?%?&)od-QPh)vASW( zn2mDtj&oNKJCKhv;O+_beRaRusaG32cLlLqIH)LA@n%FIH|slh1+jZLsCW@0P$URS z)qR5>VX?P4s3=x-n-PKB9PZo|#Ol!w+^O$6mH?W?j$Z6KTo60gK}E5;zs`t2H}b#c z^OLIF;4dpnY7KRV&t|ck5E_)Ld~wVDqXN~LSw~U4GinRh|CJlvq2XCpTB}8IKIpp8 z;!Rjiku7nLfSS{WQtqYoM`~5%b}WhamKs7!Ml1}VmJfg)A;o=|*cn$_VSEVYVX{N1 z4`>Ur!yVKh_A&=GE+qT9hfcfBn*A3kY?TXYjti<@?469nobRjDxXXhb6>2Q>;Oq)D z?)G4Ng&OyIa9LiB-*~Vuug3izd^fMggC6Y7tMQNrU(BnaG$Qz(yc!>L+U`d^Qe((9 z0^1hn)!2&QfZWWj2W+-DueLH7Styswg)W!PVwFDVb!O#qepW6!vT`{)E0^sR8M$1R zmCL@YT)vx?%igS9zUXqPqKtZ^hRPE2Sgg_<$*G|<(4flU&XV zVoxVjk(*U5J~j@ED%4OJSL9~aidPi_+giMe7+8&XQ25gly)C;6|_huN^ zxvkxLR}kCepr$aYKhyJHT?7TON-VP6m6hezFw4<;F|fv^Su1d4;BLlnzl)_HHZ~kx zso{8?i_yoVSjMkm9(+DhE4v191`})^#cBYxxfo1?r>(?b+Dp!&M}sMfH(eABV&8Jm zXt6^XpwU#Y*So=M5PO4zMvGk%(_DvRtFboLG~OC)gK2b?MuUaJ9OeUW&U~FpNCbu% zi9n@9|5$JYen~HWWX7z{@Ra}*uUPdAZ$7DGst-V7)rZJIf1NNL{icJe9vIylIdTi# z2o}V?U}q#j(!&+24w|1EaB zgBr#1eT|&`M2%WEctNo@60(A9I3jbCoMJ&N-^t8jO%N+L=(Dpxri*luGt?mV2}0Qs z6nXV1r&thsjDs4_Bzvxd3SxawskKXn)Jt?l>_i%>%uSnBQsaltddieKtS2yd&Lg&! zTC3(}@V6t+%xzT?Du-*it8J9p%82Rm$u#1{rpLu}`BaK+?5sJlAI9Z7D0e3*?mooc zO9;=oIv4L7H3U89rNur^XmvRJVQ#Bx^V^tTf4xuow_tiH__4FmAoi8K#WFs?whk|C z>O=}+8yqyMo9v?wDv0&AN6~SLZ0;ix`yE2rB`FJ%#)l)t#ud}QWtCQJ&Qfen9sX;n z*+7c9FLn$e8>(8f6N^@3L(gT$4Y(tiZhSbPPQAw!C?NC-m7V&sWtklft zr=yb8*{&KI#cBb-`gUqrhZCrW6L@oB|EN(CCIcBqLebPtRCuT_q3G? zU0zYFR!Xa=)?s-o2@h0pWInkMNzEuxdJriFHFpee@q}&YueIr#uqPk*gO z*Muob_`5;ZT$};3r3<$~>^KKC2EzEpfqh-$L>k1N!GO?jvFAIeLF@&DY+BX&sTUOc ztb@u1!DoWVa=q9yomP`rd4`l&xivx5m(-GH2#WPVH1(f}=4&YPBNs$btUO~K5i7SQ zh-Mdr_o!2tb9_EIxj_wzJ=u9|lv#BFQewUBR7!QG_?kX&oD}PAx5&`L&RvVxXB<=z z>)mM*mhFl;`>QXDT?qAIUyPWuL1y&|%dAD3aS(oqmtOZGVlg43mw6kJ>>yG+63>ZW zo7lH<({lQ?@iTM7-Y2|Pm9rvtLqdVZmV^)W8e;3SHI5-X*=tN8`x6g|oku8eYs2$@ z8<~kGeMXd|_1P!X&5dLqbx=X<^MqE*O{VL~lMPB@jq6Q=vQ+et z(r~PY#40mkEK1XSukrxd#SYTe;c{~xQ*x_IO`}+43mf?Kl1x3}Or<83^fq^$ZB%Ek zF0Z9JP>-{YC!tKnO|e8`Idpv_qpIG3@m1t@OHHp(Cc~3NVwDqmQYEQ8ut$h}lg^`4 zks3-<#!2Tj%1g8&w^J(UPzE1j2qTh6tPn#HO<`4|`Sx0WG8yTSnOJ>?Ry1o>6 zWimWTBv$aDr)`F>tT)}V$~fh zs8)}+C|2FEf@-NpuqamDv4U#t>^fI3Hr~1Nr}TqdD9vKyoojZTM(Wwj};ihm9zS*XU*)^$up3t)w{W{fg|Z9um9I zLG>?_{ilNp8ksG9_y>_a+C%Em1P`4=_H+-aKOG*TBS$oHS)(+EQl`t|uXET4H%bcG z$cfk8ph>mLYI!NVnIXPPYHTefzXeY`1`~e?v5XBsB6Uura17ZWc*tdd%$;<$h!kTe zc8P?(xJ>e5hBYZoslb~gt#h}}J*tJc2dPjK%s zq_16Qg$cBArZZo-lkDRjdX;RShyG1=HRrA{laKhnUGYASj3c6Tm1`x=Fw$e4g_ls?~S zHHhU0?y+MR#qyKSe8jAlwmcll#J=Io6~(?u$j%2ta z_-89<fTHUd8SS5Uc`dOI5wf{bOHY~*m)P~W%vnLTwj~NdvHK(h z)jHSpjzrW1jWX)kiJPt*Ftkv7Me4%(43Wp=8P;fXJw%|BMZ%0 zS!gb$v(TKCh2~N^3(Z+sNZ-x$vh4lQsNn-b|8|q4QS6rvO1(KD0}{>Hgj9zslfhgO zy9psXsU#>`LuLdi6vgg9=zpwON3*&ifJd?CE!U%@v@1YStQ6NYC&bP6)W6h%#<0|V zm{zWH=qzI`lc(b;lC|P?@Y>bROoP~m9n>WDw}fmi)q2_sihVXAsMhwbIGV%`CzL%p z+5#(_Vm%EzvXtC*PNY$+Y-gk^5$pZ5TmzHwV>=EfTUlR_m8uFbrHGXFHL? z`DDG8ir6V1K#}7}vjXqswPmE3Kw`fnWTRATg=*xn+nG}#nfW99xv$z z&AfRNytbvtSZ5{G-Ox%_ciX9cg)`G2_8LOA7iwMS1;s9KP_x)C6S@O=x3dnZwWyZf z9?IzCLYjHXd1w$Tt<`d8xTWljTzVyw?;-R(Aa@4d_8L}F`#|Cub$%bcsxuG~E34H> z@0)exbw&1}Bvv7(m4dO&J(TubPDJ@Yor+bE{iR0t<&sAQm-F%p1Ij8P>5L+SNW|Vn z$PTz#i@cz8L%OyTsTZrKUbw9iD}%;-eMv2EUOQiCJ*W6ka$==zY&B=tN=-n0i0&E} z>S(by6T&~QH7m8XYTuN@jKY(MVl!D6ug?Jt$o(icJ-1;=ZTTK(@y+rjA&N#CVK&r} zlX$^+6R&$(jH%eUu5(joxz9E!3dn`#*C6m~(tPenu}Z-}Gk!RSY?zVv)MK$Bv~!!Y zR}>q!*9?=86*Ib8)nDLPoJ~ z;;9!KQyUoSN$o19)-3i~cPtqrc46#T(p*yOD=#Q^A{TMH#Hpnd0KRS|_TGe`S|1UG zpxDRRcWY6tSKO95Myz^k1^e&sDD_v0$nLtK+GwWd7T47y)qAO7u?e+qpjPb6EA}3j z@1j^`sWNwI=PWg5x=a+r%3&lIx|Fe-U7$q;DwBAQc?PX&6fiZ#%6i7z{P#2Fzml5O zTl^u;Uz6B+LY2Acvr1~r^Ky#oV-JPBQQGCjc-))fN0OR%Yt%J$!pMcSWU#Po4A!5| z=oz_UeZa@6u;m+v1+fYvQdL9oKu)Y`JCajFF+xtPN;{HM!w*zy;pyY7Xj#d24oisG z@2)K9NU_H_s6p(r4mwh7HJ1*%8mjf&D$ZP(M+LF33!+}EJfp_MHaU;=V!w7!QLNmW zAnHqMeaO&YPV85)XzNRA%^j?0i(+pgWG$-YyOrAL)GZ|x=Q^?K3l@-S@nc;ln#Ibv z5i6IpEnLz@iH)hHmZvIuSs-Rx2$t6mT$wdKOIGQ?@BMu{HHSMH z#qUVXJQx2qG4%Zq`jYRg<)D}TzHlKlh^<)FCcsXKFg=L@_feI!9vO_ISlt=nm@0NQrEC?dr75wTXVV)y^Yvmca8Q$28MF(eTHbtW z^Vx(phC5q@v{vc?QYWQ#e}z7a?RAD4#r}^o8RyQX$ zRJC?=aiqpo9yPv5q1Y##`9^uvjSl)O_6thc4yolmrtXB&9-HM+590APMX~a1%r}?R z^5$D)PIOB$yOLr<5c{-)j+7x~2*-S}>H-wSdUvUtfkm__gE6g~%X&ehKiEUmb40gn zdg~iQFZMr9>qxO*6SCv%jF3s&s+X{kv-Ju{M_izs5w0OBumYNNznL8vl!TE5i9#=S9J@sD|3 zu}{Qx!!)SPqdQ8XK`hULWxmjuR@A4}b8*G=c%>Davpl9ZwzT4?EXDN3R!zt=g>1JaF17u{y@*KW7; z1Jbweu|YE0Ur2fh>BhHOy%qI;4*k#h zKgRPS{jYyZw*N4G$!$dWZAgzHJ%#a{K^p4cM7dv+-bs2l>HVZ{kS?H|+eq&seWZ+i z>Ag+;e~}Jhel>n!oXTey?{n09iS$*{9m>>?>}Xs_gZxkwEjAl_ARh>eq3gLY5&pNC!=X_DQQUbS%XDfkMtIP z1=pVer243|K770n*CXxer<7TrwEgMLmktK-U>FG7J1~x`Xzx1G+esIaK1SM0TFqxS z`;eYTde=Z}SkKWyw|YQ$HJ|z1K)Qf5lwU&pU!<}?@=C+2D1O(COw$+Dbf!}L;bbomvj@-OG!_q-}W;8AEVrsfn1(X zn?iqci2sK4G1Be%?BlznCw$9l-bOlbwa}7n|88|l|3vx{>EB4-BmI!{6Vkyd)WGcT zi2s4~&!jJrzDD{E=~B{9NSBf3)(8x<`QO?ZOna-6u3N@_k@NRB(i2EKNW-Xx9a0xT zZ;<}wFxy^2T6ef@A51!%^hwgUNIxKrjK%)!OS?^^{mCnimA+^FK0(?;`WMn=q+y(= z9bxqv3YNw~iCEd)DX_B=`+Ewh@(}7@Nxj=he?&j$m+`j)?X{Ag6!=kIXEJ~1kSfp0 z>)PMX?oanY7GJx`(hlwuJ!STbCG60@NcAjeV4grg*5UfR3F$D>y+{M`+_hYfZX>;u z^j^|Xehk;8@uX8oe^O?>I-Be7C8QmsSCQtp&aPT!y_H-i<*y^XTlztO^H#CI6{J^^ z-c1^a=RRG{B43bJu5Q~alU9>%L>lUU%=P0l(gB?3`>tsvR~lkzfpi?{*`%Spqp1HU z(r>CilX`PWFC)E*H1yX;d>QHIq-!(&Q2tHEeF$&d+DTv5ja;D6yMYDXA^m{#YtleG zSJ==ZN0E*rZ6gikZz290(r(hX%E&L`ljq-)K27>B($K!%^nID@vA#}T#d@tHEs_3) z^efieK<yvIw`qElfvT1EgcU;HP6G?9) zy_fVKq@n#ka^KZgaF?+CAJSiO9v{MbIf8UN>Gh<#UkdFH;68masqXi7qTLGvJE6Wl z3v)R2^)Z<7W%hsBU&8DEA(g+-{t(8o0qG{B<>VEw=FesQ#6OkxPAB~l>3q^Ko_D!E zEG7Mz^bO9FYRa--pKW$m$aJea~tV2 z(st5r(kjl!HA#0QJ)AU*x0n9jA^m`KP?`1W4ce*T{2oBMWtsW@DdoQ=mHeh<pId~NPkQE5$S(Ozap*R`D-Q84a%Iyp5;7$p7d?fe~})_`QJ(!=Ia&8y+*n!B{k$y&+(;M_b2bS`!jy}>4N&ijy8R^h6 z=db_Jp57L$;<~mv=@8OwNCWq|Uvd3-j`Ri6w@5?zn~3Xkj(4&BP#Jm2-OlSzlRiuO zC(_XW%fv(f^7AOKKS5f~Zm9n`<%e>8()UufVq0HjIi$?`wGr`9e)}@=dY`0~fs7+P zJ`9ZQKGJ2RpOX$MGk#YRzn1hyQhm(xOSY@n?}4PNlCDm=F)7_SqTij^gVzrvJ+zGc zG~ybUKeDZTtB>uk%joMvj-NB1mE3>yiwrI>GWsomxs-d7^i9%GzK{9%gmgW|u~C_L zc4ZuUlkQ9UebUhW>GZ2l0qQN*HMq~!kgm*qDAd1``gfBqB2~Xa`O9eUO447EE+h@* zbKF;7Cha55bHA%4y`41FKbZ1|k{(W~&n|}YdJcR&q&2yT$%p7#^)1n zkiJ9u57K{*oIX2N&iGz&fZ7#_a*6| zGV(WZzrKyMi}V4~M@aun8u~ku`~1127m&^)eTnp4(xs$-;q#N1NZ;Kkv~1gNmeKE| zUJvPt+B?6-+MPps`lhyBJIvBf(x*u+>i_Pwx#jCf4rPoXSUh38C66o#jb>f`#*4WXa(rcxDj(Rm^^rg2S^`+NIed*Pe(U;yd z>PxSe`qFDHqc6Sds4u;mU2T7)*Iq_ndVf*>rAI2g&NBMa8?Y1oQLj^!dfjF8rMD~f zrPoV+>GhV;m)MQPU#;-U!6;BX=^rlkZ$(8Z9b)7Y^ z9qG=b`;ywL{_h;(b4jlx?IgX9^j6Yb@Op>%d!!rgYXzo|2I9F@4z$Q>q&1|QlWs-& z9nw($io-2(73uY)3rR!yQ0_OBdxf-@^vyE*hc;M?50mzg9?}?kvh8-_=aJ4O{cRa} z;cxT$hom)4+4eUtTKwCjyOZus8fv{Y$|CQOE*)drlgC-wOM3FLw!PBvmaa#7`3biD z3h9*-ZF|rpORsFR^mbC)@_&Cf*77fq{*Clw(u!7l{WDUhd&>>rp3J4_A?f;}-gF=X|(;^g_~$Nv|Qjmh>jlTS!BDlaI5=*`$|{zDgR( zU&A;TklsT2B3GLOK zX_2i-Ye{z|4dss^K8AEA=^3PFk)BT)>aTp3MFx|uM*3UQnpyVxrtOy2lGc%qKilG4 z{n*l)^DXTl?IeBl0*h}l+tSBL-zHt{LW_rg5B)FWX=hwH#?@bZcQ8)H*TA^KctX3< zQ~#v5qW!C8ewF7}+v$<!8rF>$wA|b5SKCFlJ?dgh&mlc&j%}Y#svj=c^HPiJpOxSKXSO|- zH2eqM=Uis5uYQ%KTant9|GPNwE4?SE{~>AN3afJw>G!X+?OCMy2kpIO%gO$rOKdx| zU-*T^CzFQy(%YH(HJ4in{fkl3yQGZ1^u|$N{gIuUskgX{zVzl%zk~jJNaa^{!uX~4 zIQ12`?EIa6t9}`3+P3umL;dQXTf9K3xMe4_BE4__#9mR{vNMc+>&p0-UMuzGw}bu_ zx9o)erS~)HORtCe@;j!Cf9d^R@l&sQzV#%%Gt1~p?=$L4uRwk2{i2M%^tS)0^(Va! z>Mx?+^JVm!H5%J}#p#y}8t{=KRxql-`=0hhhGu_Zao%S9WTtr}-S}OK+L< z>A#wFE5EW6>Pv4su4h_5dT2*^R~|!s>1kb*U#%Pctv^$Obu(NiwQfCFCVva4zl8Mg zxi&(r!=b$}e*JsJXI*2jEF~TKE8AX3x`edmT8rO7+Dkg@I*T`vo|MyI?+#YjW zHgb9&LI0?c{&^&?X}K*cEZvDzpTp4mfL)dLdiZa2=pUj9?dkVFx@m8lDl4%)=>epN zlh%_SLmJx4(Z9YouqxYYlIjQi^!biZ|53{QiS&6={ev!{{1bt^{^gc(@}E$C8L570 zd|mcuLsESXFZ6c`uTLkvfV6{j9;xyl>i0KJq5SoEi`+$8;5fCChVtE%dxlhU`aRuH z{(1tplHN{w4`~nSi=-jhiGKDV-Iw$b(t6TSq@lik5N8~(>)%qijcxVkkuv(v5r2hL zKdkc>+j{?WSs8tOA8!NZb5qR&(h;P)lZNqMM_iv9xQ*?*Nj0w)m(hQV_&-SXezSfz zQ}byc>oxSR`Bly9nqQ;K$e&C6V$w@V!ym4^sf_**2Cz5jU8IY`z}SAA^cm8(N#7-X zpLDk}BeMW9UH!%V><)sT#hfJWmfa9M1;oz zsp&`S0?5?%BV*PfvlaPx?gi4>PsUz@Om#n&&CcH2kDbjR)3Y3zlgCY(Jas(&CG13m z`$4O%AMeeOY3)a5GGsdXkumFFdp|P2fQh33=e?X>ZIWohsu<@}lV#Zv}?*Jc% z8}sfp{P=Ox$FXJlRGBwbl6(z6cG@%{QT^mMSJTnqr+Pzh0y`7&cd)x|nBi?+#(1gB zkHp_K&85W4d}hk5Hs=3u6_wz(AXC$ijD8f^R8?jEfh}^m+okTP{=t}UMKb!dmb)A= zBTTS(t%3h5^X4RHM?V7jXHUwQkIh!*Yw5@!NwOSV;re9{6H5K4rs#Vi( zTdV$>IMu2d0b8rO;;CwNA|SYfuMPc0a;nvlXqz-uMm0YuAvb)guV)MtWQHZKt6|2X zV>x3n{KVs?8d;x1W&S3hHuGkMOrB9Djz6g_(qazFol<@a@3lyU-}TIINc1_xST=V0 z=I0|BTet5(rrO19#=#Gxk(kmpJz5iLz(-@@MzGtB;L%W76W9GqBUl3{(#pRIvX&PB zmmb0G6W2{cnKz?sGk+9{SZ7cxu2DW0O*_gp_CoBhM)@RQ=y2vJ8}Tnq#-jWfnYrlH zP@fJXfY&N;aviAkWzGlb*ZR2F0oeMA)}@q?S+&es6loLc4y3}2TV?*HR6jHe%v}cpg^U^RK&GxAnHL~a(~ry-km>42W;L8iSQ znNg7G!{FKq&z^&)K&G=FJLVhXt^LT{44K+~WS)Uc$8uyQjGsQXZQS&UW?S=j3g-7U zdK1VOKnlyTV+M6?%#HT7<95v4>PsNI0O`Q$o?L%y{g}CYKc-MaR3ZBFzg~ap*3js@ zld4v&KTF{pMT2-IDhx-p{wxGyW=v(i34fEP0wZkJpIwgB`m;M$ke3adc$xL*YZQrH zfAn-KArh@WPi?04=X*vp^)l;EC(!=ZA2Sc_`eUAmq+e$JF+T!q*PqK##Az|J{#*q+ zcKumDy>-H@S$}GNraYHle`?{uu0OS~W4!v8)}I3rf?I#4r5=6d%y%QYSy5Sgld*Ud zWD3|Oe1(q#(w;zO05SKUDD-Id=5pr%F{cNQ%mHF5!Xv)~a(n{01xRZGc>qXT0(k;R z=lbz@o(HlnY6Jsz;sBPAf+81Cfkwxfd}@^zRdc#Ii)rDr!vCwQe# z7d3%I?2J8xIm~~8SduTz?j}?e3K;P$P70u<*=?Rznn)`1Sj=;qr{v7+o-$RlyAFN+ zB{Y&RGrP~hu4iYrevLjUV@?-qkI?LXs3v*Uw#@AA0o&i~Hg`#Oc2{T4N;A99M=*AF zccYaGIXd^=i#oHjdtzDuahTa%Sb^EyiX_|F{VwVclP&hr>^2@^vwQ5x<4;Z;FQRWo zeVY}P8BH#CKSsJuGLetPKspnM`NmDJLv-%VMTi;Y6A|loV)3C8c)M)gn~3I4hIdtF zJ2ayimnFkzP3AWfZPnE#{FsKS4mWMAIwOP9iM`xiq*j2udG`m?FL;^Cy!}d5=AP*H zp@D=w_x=Mz^DSJd%-@<3wLSMfSFg(a2v*ZCQ<JCC#+Nzrg>9jkur_b?qxqbt7TNR$Vn5q5H9ys%{>xxT;Ikn-%^5YUaBy(K?n6Hxl{`GF_61 zkOA=Amq5&K?bq%|JCRHcklq9`0!YnHahZL9v?q{5fOIF2(Lg$Pj%!UdGQ%*Q@MHeR z+G7wWqnfwd*hW=FPt?YHR*5xo}i9zZm&NAc)88TN}IUhEdJ80*?9> z-JfE^3tpz?|8bpaeh5mfA&{^&|8t!EY|ZPNvq>?t8b6LR8^jRL(->i-FnF1ouSLwu ztNG~JDOA^t?4;+rF=^(-gF`egPKQPO7re~8H~@C+ycio?wM{cGx>jIbG!NFim<>lm z6Sg!jevd0|UW_%5CX$omGQ`qxi+%D|?yPkqWV&~WSLPzq1FfRDV`rQ&eCM5Z8PSdi zqBS#$CXknnon7O0-UiZ_K+Nw9_HNDEi0o9MmtDKXwblgEQ5Q!x1=6>l5X}o4 zvl;gzQ6eT5|4Ppblt%DM?*#}fc&VQ2Hd8%!q6g{MZYJg^&nBKa2$)%vd>ss#`EGtC z_XLX%p9ymcI_POgLHZx znmM>D&ZKs4+89RA$>3$?;I*)0=U{rjHR5It_O8Gj>_xzKZyE_l#;bp64!(g%?HoL1 z#-yn~n3kM@_zVEXwB`U-Zz?lbGxIaDk zUaFsYu71*WXjDx7Jn^LJ=Lz%-$I#$q>gRY=7T56Ls%@J3>6xke8J3ZuT+Y-_C$21S z4L7w>MD^L)mMQcTI&f7sTJ`*BmI2J5ad zJQd^KeSjVJtno53?T{%PNErj-uI)O|CQj_ky*;9@S<0;DG)a|#giT~04^E|9|EaXVK6X-~-94y5|~ahXSf)FzPEfwU&HJ_OR4 zkTJhfR+o_3+#pB9E$;@TCLv>lc z1c>?0u+Pu)21&@g0i-7(^NF$36!&GG{?`@b$S@%0bm1-U45TZ8j093>j%$qr(vgsv z4y1EbT;?Z0+7dFIK>89g_W~&-WS#`ladh0yn?Pz4GXDlrb4*-j9kZw;WVQv;n~>QP zNDt0qzNbe3DYV4x90#N;A@f6nBxEiI(vgt48b}?!S?A~Soj}?WGLHf2NywPrGA<-! zJ~qghxSeWjwzUbF&4BbIWcC44osek&QozZ<$1}!gAw_;JPXn@S=Xf^G2U3INn03zN zD3|*=kmo?X)~|u&j*DBq56HU-J5K{?A0L-_9Z25^apXfF)w|2Pc51t-1I_O>3{%1{ z$8eh7sj-~|uk=p6bszyd`os&mXis{7&|>dowNrQEit&PzC%6uG-7q@A_HNH!1Q`L zr@}x``GT)wx#aJ{u{*raIs&~v=YdVfaDTL2avwK<674OX`2@J)eWR(E@jGm?(|j2 z)J>0TeFmf>;cHb4W=BG%7D#JCW`83yBW|Y^NKYcdX+U~^7?&}hndnN$TyKz>aha!p z6i}IdwOInBBY~`i`}_8Uovnd%oEFzA0_jX3Z9sCT$7L=8(weYy6_Ak$qzg#jS#hlw zfz%{q{sE+WR$ON2P-G*4><^@OulNWa38b?*P|6XJ!#$Q_Xn&ocJ(_oC8gD`7qb`t z!Ph{@><7-jwEER)4bPu!T&7-T^&7uko}Y^O;GkU2e4aM>GOORHjkNmhRd)4Tcac`V zwd#@2h2 z#$ab|S^&6N{o3Z?dL*-L%8voeJy9JV?Lb-+GCu=Smq2a+ z(se;x>p>tj37H-s-Lu(?C?50P`-=y}Bm4+R?ObJbAf$ZqZLhHBt_{l<#qDeXS_j5seiexM%z(H21rXB7 z-;vPT5=c)%W_KXfKZ|R9A4ppQnP8BFozsDsXENT`b`+&41kY|B(CXf$+^dykM>%sdk<94qsE& zSH+P@KspjyXBy<{xXgt>YD#hBN+4|st=oYV5;Bh%nFR8(k#SmXPdUd}M%MDb#tLiJ zasT>X?B5GB{}4~F>0at( z_LOUIGlH!LG9$5UC59rBHz(>pK)~)P?WsN)A+x7+uE3r$e^c!#3vfms8QIq#?J1jL zD%m|{+G&%IOYbW0qoTSxZDp3*Q@(;s&%qq8$iW)xW0jCrgzN~UGa+*jkhW`RIg)8H zNJ3@`kltTe8Jmg=fS6}!eg*giklO3xGPeV1b%X2BeM;S4twh^G|+rwcE7mjQ5pv%q|w&CY_(ba}&mbYF>snVkiBSWJtV zS#TJFv9sW?v;gdwSwgz0<&KDmuA7CZWc_OGQI7j854qu@B}KVgB4Y7 z7Q7Cb+zs(MG{2|alR#F*2o*4tzIrzS(tBfEYd;_z3*yLeK-`%>3Vs@p_M0W63bzrO z5uAX+!tF!sm9B84FL-^Edxu9|^(NPEV^Y=IyPWFPI$xt~j3$>WnW~dal(Rd5^dykSfYjcq$}~cMF!5r) z63CW7dK1WQM&{RXt;2v+-yTOs18GelCmESL;xg?(%;`Ovm1Um5`~osvcS%b#&SuP1 z-2(%0j)-!iKbmoMFpCm^jIMb4O=eu}VC@%w@CL|f#%+x#Owm;4v4G^ZP05+rRQG{q z)1Od$II0FOGn*!SN3%)4ZJiV{vuWx5s@} zI+12JEgquTlo?Jmn`&2JHuVhGZ0dn8QyTuI{o)Q>v8SfCDJPv2OeKil2(@ljOV+p> ziw{Dkb)l^&n8WL7qm@8j2U2sls?NwP1=0s<4#igM3n1?%kb&lK^F4dr%4`6n^`5w$ zt%1CYCD&ZHGJ622UKE!(5J=%Sam2hs_hLe;2{N@0#AU_-X~%;re@}EWklu&m$d8QW z-^P(kfpq;Yj{FkH;)E}A_tN(JxXf>ioyX(Iqd*oVv|a$xu{bXCHy{g~jOMZ(FJvP> z61xnx?bz$To6G4s)Y{&{b@?Z%=gW)TYW2%X)-QTFEigC!B+z9`S5exJ*UOYeD7O<`QD0pwe!6$ z)pz6A?4JAWuK9j0PBLjRGv8lz^L=zGUIUojvvmdLdnfw7I^-+!Tf^7J30s=)<~y-= zzH`?ci}$@_XT*<@+3F{4jg_146);^ZnaInAKw1;XE zav;49Icn16V&i_zxmJvhUpKlS)Akf&j^cR=NP7bLo3WEXJ_K?qvf=GiY=S)nTauaY zb|qN@NFjmL0BKDi-v!c%GjTgB)gXsw$7R+9(w>mn9!OV0W*;Ec&&KT>1EkO%w=)???oV-y*$zl&Lgru~wF#M{f%GI~rUR)? z$Xoy<_m{Y@TY&VQ74O$WKxz{*uL0>!$ovaPYeHttVaR+!W(y!437Nft6cRG^K)Mq$ z6M@twWX=H6myo#vNOeNyRvzxA10?rCJmzbFwC3aU^iCi(FIkxii05*D1oCcTF24?> zFM%utQhi>$?_UGydO7ZEwauY*c3fstAU&_dWp)Q*-v6qEU-Lii?}7Bb8kZSs?6k*a zrUI#ZEiUsjAl(U>8-Ucj9+&9?(wRUW0@BwTmw5(A_ut~k+Xi_fj^ww%T6bmPUL5(8v6INg+dz5} z^K==IzNK-kHMfMF_v1({ke&om1XBG$TxJ@Ox&(3&kggxc^K%uD!aw6$w*cwHfz|i) zZXg}!NNeJxi!d#c?w8x z0(lY0$d!4|h~DB;7)B=H>q{W-y3Cs#PMSPvdfOLq%hg+>o)cO%K-v??9zfbw;wRW6 zUn7BR-LBCw&@n)22ghZm7&{5%5+HSRs8!|;`X*y1FH1dO^5a07UB8U?mx1K) z56bzheq@k@%z$lBz4*uGyvznbsuRA31L<2kE^{D||F5@i0gvRU&h7QuVF3e*ae{a` z16h1GV2javM2wMEyK4#dG3>*;7;tMeGt!KAG&7zVtt5v80XD3G7{TSS5S%E4$2xI9 zNr3DP4p9gp3JEs~IIy2Xh;FV!lw2n$H%`0|0{1^vb*j7iw6yEK{^-wZO`kqh|EW`_ zPMvynFFY$uc|9m&cZSPe2W7B5%yTCwbqD{@5thWQU;ft z2lyzgrhyF?P0AIy|EZ|VCm)^L|`)B&;Tr>|b+sE?&-=T&lE}94Ue3Rz^?#0V6 zUM6^G9w4>-;_F0<&*ymndMARsXdd88H}X8d+kT4rw&+Fk00URUV(?)5wrij%c~RfK z@IKZL+*8a&J8)L|c^+W#Sz_mvc`wap!Kdc|a;;jGY%DYhfPAlpMa>(Fx=f0zkY4~E z+C~Z$LFOI!f53Pd?s7P>Qf|S*>$(+OX3wzboGI0xg74}07hG(abi|W#iJOIB%N*mD z8vxsk*fP&!s)tMx`=jhL{=t@c;c0A{m=IF7&K&wLS>3kRZZ}qUH!R9+Da55_n_tdW zcUz1^`t0p%-+Y;weR|9VF?VEj*^5{mS=51B*`kJlCE>`Tj>9swMZp!uTx3zpmtaw) zLu^rXZ?7u#Xm z)7cJpfZ0T!M|Aw>EYf0=Q0_ZR`=`rERR5YpFL_242hddbg9e*~D+~*?+b%<+a@6 zbDh?=@GX>r>Y{6s>!J_bWFPKDb@7kr$8=p_VJ_w(Jug{3r@$erjN1E0##qmB9ufOe z!Sfc|-ldHZG}Q&|Ueg|1_8_e1AAnEmd8S+`NxO$S`s}9zB;TtmofH zE+oBsk)H1uWIfAr5jW|X*1?{N-`lsP@c(!{e=Ns(E`mp1q{Hkb=#bvBr*)VwY4nL%g8>8zBjD<%1hC63=f|o!Ey$~hCDGm=Dn#s)<>xr z%n`g}`0&x4Cq{>Nfl93*8Wk`zwVfADah?7x?p)tXd{n0&9ppNN!ecI~(+yjvX>gDh z+>6@IQ^vVYF-(r=khrN%=eMX+;-ScDEX)0%#NxKoW9z+8snCm>L-p=Ai+Jtss|AZ4yC~9%jqrZl;l|g&!Vj_Y8}DFR=Wb8rHk>7;F>@n{7PnHv*bRUi{tPe*2YrKbGqU9XaCbV z{-ORW5(Ai(Vp|Fo&$H%&EXfXk9h(F72=O#>M5h?J$PRC}c8F~xF&B*xziVTp-vN(g zBU{bl-^Fb8gVt7YcqAqt>bq%|KpW)PzU|pD(r9~Ly99e)w)T7u`5@!a#XhQP?b)vu zXQpa}(7AN>KW!KtQ;B2!hKZvt#s83UwEuBsVX;&k^=7WG-y=kRWdBlq`NQltHt*l( z!FRF#{fheqpk&|0=;S2=t0P(_!`w1{)6?yma);-QSqgr5738yIbCz}bYv6I4>f>qe zZMIIyV%>||`!3twsV%z~xA%f=?>oWZj(2n{v4779o~V*WW*8_(!!ta%6_4>7OYHqN z&1cUoV@^J}30)d%&ydx8+}Hu8KuJ>gN2S3|4E!Gk6}pVfx1gDZ$`xY3Ps1~m*@_2P zJ8!u~$*i$ROYYS{JVQf6MBR*so>3co#J0iDpt-(;$j(J=@NU}%_@~=x8f59isek_&G*6fZba?r;xO~WGe%kuXZqDBMOKo{@i?&S66xYqZ zn&Y}fP$K<~nK4_o?LALRRL<90xP2`@K|V8O+ZRdbUfMQ>Z=seKw2N3CRqtE#jNU>u za1ov%YQdZF5Hi`%uini*{Bx);SBJzy_Ve7m?89F}Byo{#tm2=xjTD|EtH?#Ras33_ z28<-;qI$1yQSa=-|F^Bvsba%9f2}i}g%{Oz3jZucQB3!M$JUpkd>E9r7Ds59j%t;V zd&*Lzwa~c$vi0D4Jl@!%$9W_Z;SXAGyfXkXzt|g7tOUiO#Su@$8}oS(>qQ44vmCXN zCA zC;12KNuC!$(YIt#i(6O}agir!Kg^zF0Tj0tu+{y*S{;VV{zSbq9mEc}Z4@y|Y@0Ur zBgOR$i)VRkJg+HKgK)i(>+x7rdMp29EUI8F3dN3GY*F`Hi;{B%l!UD1Kk>0IZ7qKS zip-0wqw#;wPhUWPtEs@tIKb=flO)-owdb}zQfRco0$!Ql32l!7dC?gMO@zuKn1 z$mixomiZ}bnUAsB946|m`rpC5)u3!D;3n&xzlinH`y3W}cr`g4i$(Fz!`8y-Y;sVi zEEM%<+cBMk0-?Ufne6-}Uq`3ZFXrn~N4Q73fb?$b=2mdCZ3VNf+14iW33wGMNgCG* z9*_NG*}`MysHuQdr_VXdb$X5viR@fdryqYMdmGo5nUU&i$<|j2WT|JW3-2U*n<6K5 z{*s=@w$L-{@aL=!@m(vwl&cmh#c)Xa4z$xYrNhl*(T{;=>F2^e;d7wSd-tf`v>v_; z$~-#Ufbt+w9G-81viJthhdqEsry3kWncP{m$5Vr2jJ0i1SU9)tv$l1o9BtAKx9&%` zXx+S@r0o}Vxwmh7lE{Y$WG!E{*0Svbo#GX?4`Pi?(%76TG;{>K3-JI!d78)uY_H*FYhg2rjlvisE%7 zgXshux(qD_D&~JjQO15jTT5K)CZ?b0^t=@6E3mqs289Ma0i_d^Rg;g_%t26gI6OH} zvTtO|q@3Rb%7&$|t!jD5R_PnV*Ak<>9*?bB3Ds8uZ5HYW+veD zMD*rl6b(FM_`kf!R&SkR?^lYoRkFk7OR&QW)(%t1$L&Db4u1B}P2Mq~ACzSJ4$P`Bm)N&g}p4*v=3 z@JbXMgvdoU|Ij7qFnb9)d~uC+2xZ1xq{Gw)bxp>N{#b|KvpTF}sGbj-q003>XjSVl z6{{a&`XlmM%2v^vt5jbHrR_~&&-VAAj5(C=f#SV6%=4@+w0DQ{Qc%_$%5G5VZwaS5 z49b#2sezKclX;{iyb`)`J2h@imtqO^ryD;njoZG%?a{0BxKMwORjI`OkG<%K^`f(Q z=B`%~Gg;K36}G5NfYHDL8Tn z0!!FDovw@(xn)bN4PP$#1Vd^c30WsYy%Gr2~U ztTXji-I{d2@XJU=?_Q(3=&l$x!QTVVqD@t=Q;ceAM`>*+)Id2IBCM zkNTBgXCL)#cvyLnk6OG0AC(M%u#NMtVcS@O1ON_QY#X;)+t73GW(iIi2iNI_s%0vBCtgef0xh^*Y^3n7r&!M?BNFRd(sSE~v=m!Kxo@;OoXIttMQ60- z8V3|dCacY zjBRo4;Bl>v5>YL`?BBSS4`Y_6L*zv*?jBpqJuy1dE$+V0af_pO1j&n9T*_KP8Vs^w zQj2@t3|qosU`aUg*i+VH?~*{EkhKhMVJ(!1Jof2Z!mSd7(8aBC4vtDkR;QZPdZS!z zO$6>5{HNi2H`rRFxOR-Md8p+=&5?3FVfJHIIoGUhxMiZ^u{X|I+n{+JS!HA!@4Uda zu@{v^ZP>lYHokz!TzlhRavz#I>hbUR1GbHaV|mCnvX@{RpG1hNz414Yk5o3<#`~;o zNO=jIY=hoUOC^r;B*a6uk$ElKhO|}o3Eun2OHf{-2JI;u8^w7YW!iwav;Upw)=*eV zr768>_zj2BlZFHirH{UWVJKz{vLg}tX@O2}EpxDXb_w*`1bSN{^g9K5N}#6%`j|j( zPlP@%(Ax!iyFkBLpr;a{zd@k43G_CBzF(m4N`yWu(02&*9Rhu~Ku;$^ZwYjoE_JPr zfXU0-er-IP&zpP@s<_LN5vQb%9P_ z#C6eW=HF0^x5*|#F9`HCfxaftpDxf(Btjn(=;sCcd4YbpKp#tl{yKraD$wa{m(jEC z3;Mo?4$e@F=1YmtPYCoCfsRQ>#xm#|0==FH{ir}+7U;_Yo#q4Fvd<<$&kFQ&0{xso z|E55nPlQfyPBx`5{ri$YUlQmK3iQ*7&_@LNS%HqFV^_jHdgr;3*;w5|BJ@21eNmt< z3iK}s^fQUj2L(F4!P}He*G116flfQY+_EnwLcc+vF9`Gnf&NK>el`($MxdV-=%)qx zM+N#)BJ>`CJ}=Pc1^R~s`ng2tX@Nc~&}Rkuf^cVK<^XiZHdq?7w9R0o)YLC0=+#Ex+l=v1$w(c-zm^jiO|1~ z88g6<{g}9}O`x|4^q&;yyAq*a5a>Gu`VN79r9e+7LVr}ClPVl-^guB#rSCFiGTTMJfEh}M()S;jmNXO-(+(y=e?*{f2=ons{)j*yNrb*G(ANd}xs6m`jS9j66hZi=%*8*uLyM7 z59@fgp0fh|9)Z4)2>pu!eNmt<3iLalAoOK{enz055$N=Nch}FKNmTX+1p0zNUl8aG zfxegs{hUBQEznO3^pZe7n+W~W0)1Yf&kOWh1^QAV^d*5lE6`^J`cZ*?E)n|u0=+KK z>jHhZKwnOTepaBD1bRuJ_XzZrMCczC=wkwXOrXE`2|`~K=qCjF34#8T0(~`6**`4M zvjROU&@UJ0=M$ly5$GcVeMF!?ip6@@*R3T&f3H9v6zGEj{o4Y4JrVkXK+g#Dj6i?r z2||CTKu-(wv_Su|K;KAI_R|7=mq6bo&>s-!7ZRc0DbP~_Jtfe8`w2py7wGK*y3KS>V#oi)&XAZlfXQ8XSR9XByzlGbXY!8U7#_3l>vhmG7Skcm z=KH?>@_W3u=T_8#+$%$SdtQ$nt#Eh9=V#?+8_;QQ&#lY6x91Qjl8yHE%)@07!e-~T zXy4aebG)}_6q(3;Xx|QfMH-U~$R~ccA?@2K*?l`B-~=Ib@t&?vSo@jCouuvRp{rEQ zO%W-u!--aDx_T0nz*fzCLQ2^N$rH-J{N#FHL^Y8`#PXOkNAs8`LFVy1dakMKYCKn- zU%fwpv=CfoKB^~>nP;d%GMl#Zz!qiaeN8{Ya`j|TMY>!u_H5?aGI(?mp8f@%8{8&s zS(MARN?SX2zm}~Fp5^QRFz3va-a(d!DLsQ+3a0eU2fGN2=D)m!=Gp3keAwzjSjOto zKSHb91tYtd)de!M)rDj>WgkPO=v|bu#c}QY2+P$o!u1vR_90_+BV5ay^YkyWZERt6 zwp@?P>MEkI+!6R6En&|N(O2FR^p(b1GHfl63%w-J$w4VgU<>adx8_j#W(E3SBJ_el zzkp4%4pz?v_*{q5cdI}jNrXNo&^H7+o$zqc4+`{bB6RAzot%5u1^T)`zd@j%NQ8bu zpsxw^HGzJuKp#tlepH~J7wG2&dYeEmB|^^%bb9ZBQx`pS`p}{DJqpieD5k~L6QS=H z=qmz!MWBCMpwA{k9}(!w0)1JaKPb@W6QS=B=;s9bIf1?`&`&2q9~9{H1{J54dzJ+H zS%JQg2>k|uPG3lH(a#F>Ul!m*Nep;ZP7U)L>`ng2ty9D~YK%W=rg93dy5&BMnJ}b~?1^TrD zeI*fkN}$&TdR?GjCD2zBp+8TcmjrrApwkztU8_5v2)$jPj|ucKf&MQ7eJv6C)dKy5 zKtCbS9}?*6iO|~wdRCxk1^Sl-`bHx3D+T(9Kpzq4pBLyC5~1%9=z{`%P@sQApnGt~ zV52=S=56YiGJ?Kbpl1YnMxdV-=sOajdjdTz(9;5aR-m^fLjQg+4`9ZXy9D|!fll8+ zaNB!(BJ>LaJtfdn0)3A_PbETsRG_yD^mc*XBhYsxLf;VRZ34Ybpg%{TrxT$+BG7jT z^c@2IDFQu{2z_0kdjg#rvJ+?aZD5AVwYtGX=no5Y`kJSM)pLPomUup)Z%v?&Btl;k z=os}&^nE?I-p>p4 zcM9}UBJ@>(zADgH1^TQ&uO~wPbAi4h&{qWdxImvxguWusmj(K=KtC+d=M$lSQJ|j_ z=;s9b4FdgiB6NDcjbmfIO9FjKpkFJ{7ZRaAAkfbW^s@r}DuI3`5&AiSz9`Ta1v^K1^T%} z=w}7`yg;89==TfsF0=*>AO9K54 zfqp&_`Wb;fCeX(O`fUPzEfM;A1^NkrenOzXPN1(RLSGQ*S%IDv==63t+ufvA0%sl@FmjZEg^b(`vIG)F``cL_*Qf#sMAIQw>upyaE+2625*?ArI zM_8_&HeN&Ae2ulYjaMEw=jpGvv3_X3ihJ>{kN4WL=jSHr6OcrPBB=bDlN<$}?Mro0rCMPt31as%-=lvjbWWGVUu zQ+TVSIv1HT=*Ph`2&_QD3MljM4r}90pqvE*;b^Qg#A8PNn(`@7c%?>D{tOhJ715M+ zPzLYjoSUr%z5-Qi3_9{$08dKoKV%8FWh%B}%MM;2ZeD7>zBnKxCOnyQ^DdisPuqu&G`x)9cyvfm6!dLf+8wBi{I zS<9P2Yw^q`4%W+ zPR@^lGU7=1Lr{2DU*~frDnjpVPMNYl3zRY2Qb>*$QDu3l5Y{U|fysv`uLXtJf;yeT z?YvW8cY`u$B~+GB(BD)DQvDiuD1s&Fpl5tkz(?OPhP%M(R=`t#S6E};0)@|I>vH`Q zQEUw&x%U_-?f4sDJsB-v!^!6wP)bhOUkVBmhElx(lrg8h(;HGxJE>j|%Bqv|G$?ch zrI-ihtd$TgE?=Jm#ahd$Vq?74EUK@0B6Da1pZ+>EK0V>pEf3}Re&kbkZ2mq__{|Jj z8=oZ}t9eSb3JUMRGa3VB)wa|6bgM~xryZ>S1kZv~t{1!v+CY!5C8QKD1BK@$bk0XW z@f-_pfYN3uQ@IK}87$nvdJ}kfrUI5gpF=xv)El(6L0Ipjd~CV!LT2^K1C$E+1pUsRf->*$JOs+R(>MJCr9ylel=QoxtUC36`Oi}R%mc69s!dnCcBfod zf#+%`pBI9{J4m(0UQYS^QrN=BKv{MqoFN{^1H6lPoEG;HP!?^Sl4PF+Wz3cf8biMW z{Wx0vL-1ssRDT7^4#&p+4wNP27ii-#Ph*I`iBAalSo4ocR^`F2qF%XB)Qc~DLu*Py+>2NYfv(mcNj3a<}p$^*n> zQ&pNp`rwK;YrW{{STq$li=wC)EJ}IE{`CCv{tz{w$@4J+?$Owpnz_=SJ|%J8iH8O4_mKX;9p<-vvt6wm8b?UgB}ACO} zVh#EEKL$@gQ5If7-{4sIL*Pj}SdUREr=&k|BedaI)ODcn{Fv6^5GeDGW!?(PhSTCs zf^yc{Gf8#|lr;VZmiacy$7+>$-Ve%{Q}+8nLFq#!JqJqGYJ;AxfU?WM`Wh(wZUj^B zpsYBy@voqeg(IP{@c#nEZMn~U1$=^2(wBg;45BY^B)kfgbB=`9fZ~o*ZUAKjL@f`#j7e{m_4J!q zQbwMez{6|(TEZMC3l__#5q-7hEhu@o6gBXaoZ7h?lnt9oc|Q+Yb@X!vJZp{}-UkY* zJ>;X#fkI+c*!(qV+9xd_vYoSU~St3N-)El#i7MnR(v>h2O)eOS)qS zb>Z;*Bq(dn*lH*7IPJ6-l(eJyQBdg8GNVr^R}1*cxFd5OJas4P{&`SJPR{p$a-HKL zKLpANt3yPLWg4+k>n5$~Qv4=()~q&2j<0}{b}0Wu6bI`uP_71Vpyy}oM!T?Bl+SZP zp*VqXG*&k#?YIljhe26&QXL0n$w9A!l5*<(9#GCWwR|5aD^{y!z~L?L3)ktV!Sg&D zYcgn#1!Spe$Jl;peOQsk)c8 zSd_kP7=HDxaFmh)WyF?(c)CGJ0VvS(5GYy4683{qN2<%fPycWt3Y2qB`)Yx*X5}Fs z`rf!}t7kwt@7VLlK;iWQo%82Fc?3TLtgnEw=y;@m2BqZW^LU>_Z2leIf zWI$PWa()#kgSH<;?Wiz!*3sc>!L#9{s(|varQqY9>YIrt9RKqR;8}L+>mE>6FAwYa zW1!F#j1bR(l5w>9bx>ApKB_lIxU4Y)*^Nu`sfrqjT%6jEe{oK|qf zK3KS;jc0;FJ5|sSOsZ=@X?MI<29y(5u!K~KL!gW~Jb6%3uL`%y+d;`#EQ~Z^Q}92I z#@+xPs3)YccZ0Iak$I8w`LQti5-5XC?R*K8(~g9H1%gU1X5zj7>E$ql17Ir|h?Y=Yr)yQf~&7 zWk=?FK*>7weugNH%=9JLWh*o6hg_yN;$Zzgc+NUle+J4Lge7^k%>N6N6Hd+>pty6M zKLF*t)4q0$KprRO=Yn$1TDa;xbJ70mI`FJH-fuT3tB%dT8kCeR7wP9#P!=7m+dyfv zG6O45vwU>zz&~BCH-hJc&8KPNu`x$K?*|VB$3e^e6s2*MhR(pl3ii=h((gpq#gw zC-lRVkAt2EW$;O13%?zd9acY->P?_{j!$?GC`(SH_X$u|9M854%6UiThd^0(DBl5P z&5_W1CCX*{kOo18(u{ttMXD0+o~$T{{qP?sj#j(Dv+mgHD?sra z9Ucc|!;$bdP|iBqxC4}{ojQFtC@BZ)UQh;|RG$Q8-J$#eC`)e-d&qBqvI`=iI!w8~ zLp)Bq_%ZlYic&O>UoFlkD|6&|E_hDcTAnb2ndLx-^ev*k9xv@!%Zrd|$+3h^P}-e( zzY!EN%Rs^tL_ygD$^Hc1C&L};~SNou~>wB4m>9;4^h4d%9vx%Ujya5)gcT4qjlJ`qxm)Pq;1(LpML{o z!RAw|QyO?J2mP{xz_K0y6S?(zvEj9;oT;SLzn3s~nsu=L8&aLK@=&fX2c>S&$*E)0_c z%!+@~qKKiIY<*vUv#eY_m8+BsS-?$UnXxgVzXEolw7^; zx8~|aZz@*>ZvppFM&I~kg#Vj88ZS^*!~>mJg^Y2QW*O{`F1dW@{XRlHxQ&6F#Je6CUOe7`l7D_61N zb%fY42#qrP)m*E5s)&wHJ=YrnF2)3AOs$r3O+TM+)nH{23H$=;n-*ND1U^k3kLR$z zK(J|3s#OZb*?hg_^ILudpVDJ4KUJtm)oUdyBw8dFX)%1bBbJ(rq0*$F%%O|{$nkRZ zKtz)jt+W{!)RroqtWKj>$`>)4S*vbZNb~VPuLG5}^ThDbkoh%AzqCu(!UqKHJK{H7 zFB0|@%01|cyW8Ww_aQX%X%a?q3ndxE&D6NikRK*DNX|+{t&gw9RXg=5++^RPv*;|AQm0GRK&bEd9`u)y;^mmJUQJ!%cu#1 z)5Xy&usWD-6k2nXC-7n2i!unxm~K z-PDx=jelkU;~(lWQ<2m=nIfP%b1je(SZljbJXOw9N9Q^b%}q-ZUZLECzN`2KI_ga` zs}VnC;+H493Jg>KuEIb`?@bSnV2EZf#O>3$Lf16bYz$c&CM_?Z?hP$hC^U*qzSCWr z&ZJVzVFQ!?J&i94)>@E+0r2@rguv)_3;{voB#ErxjcNM+zGDZ6kB%NX==&X+f$q*O z^BkU9+hmlZD{VNM^Q7>YGMl6NXa+oQ4ZJ!>sb8%0)FRdxKbqpZHWg>s%qo3IRM4q-att!XQqdpp80zX$8@bywRrBl6>->TsU*6Suo zdXp@kNH(h>R35}sE>v``dSeOuFUkpaFi8f3n4_WVf+-!nJ$+r8M1yp??N;DscM7GZ zwLo7D>is-+Q{rEDm*2{b8#v|L)DB=RbPds%x^0$fGk$Y=Vxm0j!yX_-5kHOVL;zks zS**;l?+os>^R)M*vD>H1jgw974bk4~HEJHg2Q#fx?DnRc<7M)Rp#~UjtTS+gwHeYy z{v-uYDv4U8FfCS7L_^kO5=S>|e|!#R(`-^lSuUVqk0U2#0QkY(N{Cv=wuU%zu0e(! zVl>%vBbQIm(25oiN@ckPC+CWpZ$CE;8_^c*pDZ@2#fo2OAew?fXvv95^{Y%!F;lLd z8!uPNtvOx%N^R0V<&mktVi7Uc8fA(xiBC9KAw;~g&+(LT#fe6oG6SRhBz4M#%0 z5r{?V(@r&gM72}_5r>jacWSI=4iQ=Tjv_I`>k7WE0hW|1C8XY_V9lfjtMb+%jbVfj z*94P50|sa`i_Wgza2CW}Zq~L;(cQ->rmLY^iWIlA$7W2UE>l?Th(h8Sqfq`Sl0&*D zV-%*=M*Sk~g%$Gm8m(%VvCWwm|flC7mf_CH_ar3v(8*2ZH>6UK`q8%R6Jbm_O^@9fj%2^+gj03&Q0V=GEQJWYwqfg*c(L?hNw5z(oOMWy z$djmMGo3oQnd7tJDsh?;9*b_3A|I-^Yslu375T_}{zl7({CL3t=oKiABc%i10%3VyZLDo>R2 zdJJyTX%F4PoJMm3L6%$8{!EXxO(n$Ud{)@z^!OBJs5a&7?-wA5xr{W}zJlef%@b#O z5W`h5g77J}!;mf7sq_!@_Q$%6h`;4*RDdBf$yj6Ja!|)fqaJi*p)lG$C36j)!W_zG zR?3z|HN;9$&3{C+JOIxgpG2vnqAN@!a>FSr3N?6xW3<|$@gYtl>5xm7w$nx|VJ?$c zFF|lpLsV+hB}6dc*G@+3bfDXMln^g$KDN{D9|*#aKm>m#hwY|~CL2dslISyHrHSs? zsIq?mp{J3YHt$UonznY>jLc)IN30>je)WS$xiaaVemXnk@|d*7GPOx@23+kJ3Aq)B z25!To*pw`>^Dvee!iW`xR2q!L$dI)bj6)z5EAykd2mM6I3dgKi${4`Y0*1P2VCn($ z+?yon@3l!(I1|#asRV(Nv5r7_8)gf)jbOYhQX@!j&Q%el7-#0^$0I!b{RrP&9&0$E zX5&^=e?Nw0nD0^P#-}SMEkHE)OqVq?^45*o7M?6^J&c>B(UOYN8q=7;=hA3pmTIkf z1xs0aDh~zJx(QQVlH>E;f(@iGYsLm+atO^n+cky=i=Cdf48}ssG=NTH0P4sT$`O5y zel|6YU^!$+`W}5DbY@2Ingq{9#v4u*z1LnL%t4b><-88Xl_)wdLk{z!mI@&;)U6|h zqKr2%$DPO2paxMiv%gnmuLxvEq37g23W^q)gDuu;7-P_5%}vgvg%K%EFsj)x6)Ms+ zlq#oc1~eB@p-G4WCbf!KCh|iRwH!nZg$8vh)pnBk-|11a zRIOJI2=Uz1W4(;^JzY)>K4Ipflx(=sf@8W0zl|ken4s?iL8)+>rt%_*BO(o?(fl=# zT4q*1^(Gxx_JQ<3zh;C$QMWqKiGZEw&h+@6??~0CtI#?GKaoRfexk=rYB0V+wIMV-{^t-XsZ8zF8~*MF;czBwwq~*~agy7Y&vWFvDAN4>7ufVS`%HVHgz%*eXHDZa2uV12%b>pcHBtQ2q36ggn&iL6+F{(zfc3Y#E>{< zPT08XX6Q*w;aSsi%4eWA1Ir;bY$~T?Km&b!U5F#WA1!f|Ej?f>Dy|YE>|L1Y3kq%G zV48iiEhqx)JOM zSwjGB6-SwA<}bu-RAUTcQ}uLW@DY=2D~)z`$0BX1)6Q-e#%bTtlAwnVi?n$SbYfH= z=9KLtnsq0fT3AV&wKh(L&QMAi)IZ9TFp^nf9eK z{nj<>DJ*pO9)6kSq>h2!?%r<80`HA63%oY5-X48mJ&R+X2e6`n1-c=xep9h! zZ=y2w_L*iLKchL&*N?egcDNU@`0l<=%er~BcVn8IGrUx9)QzP{?TtvUoLcu?;l^&B zs#PHqrI>jON~FkIF!ncC$||3VR8((oMmaUb?hY-Y+Ux0xr0q+?{G(jjN2=_waEqz^ zP%r25_V!|8m?hm*IYEgp(M|NDKv5txzAz9wZ#|IaCqX_aUqy^bS*ZfeqzV(Z}a)Myo3 z7k6V3lLm7Upx*u-n>yPls@dJbo?I(O)GXyWoU5DM_F-)&p66!TZ4xjd)qz}f8ao48 z(|A3~5xpMFLLO0DBp?^|tVAAV_4W!wg(6iP6z48FF{P(e!XY_p-NY@`{B(mBB{6|V zYxVVPt=T%Nyu>CBp*I8X!Xo1DP16Xx`952kYhrG!vL~2&X5rL`H=@)|3<^sKA);P` z(-`A*d!EQxVD#Y4L;FYf_{T>N?%NZsweId7Pc4QjhaP#_+ly&5f{%rXhzc)9R&C-< zYIxdYBYF09_lJWEryFF=Z#h3V&^rJ-rFNtCKL!zF6sQZrvp|>F$h$*s#_1QLd8c(@ zl|M3hvpbBi_73!CY-<<2CMlPSg7!iS;xIwp+*EEhavfO5U=I2lJXYnWX}cyiLWLII z^*)CIZ}P4s?-x)ciCP% zPGe5FslBtu6=j$PlJq!Q`tHai^gwSP-h39}>W8<8kotNfYg(9Y7TsiT9~^GbjVad_ zYO5Cud;5AK>mmbvJ<+8SkkHgz;re>|R6AFuuUra1`8rMZ*bi%o^zH>J@73!D17qc83itZ|pKJKa5?a4M(1Oeliq_s_udj)s5LC zs}GAroU++sY)+EkJsUNDvQitzhOq)#G5u#uAZaU%* z>!s<##e5ChmqFOe8)sukS=zItV+h`GOvR>BhxQ*wS6KM{KiC^xX%r_-3aw?ekDul% zO9=FFF5?(>D;~hzUfl7HdGtxxT8PstnhB0Ck28Xpno`1eh$!8AE~gqqAQ!#s3mf^c z6OK2OVe88gY${aS5&e3x+@0z38`D)amcU@FhGj66YX&=lsERtU0)b@^VGDK?mT0B1ja!$W#&z zS}Q_0Naq!&utiQy1ktZq^~;an32l%tW}-4qqcH5|F!J$I1KY_Ph~1sT45wZ@RylPVt$*I*ryoc7KZAs8~q?zK{R z{%G@Htx7gWn+r#)!#WIA3>LJA9+~#hQ}BQZ^hOSAaC$c+dOwZ$*4sY-qiwS!BHxMWb)uZA!Yz~bW|JR){O<(#lFH)LXTTHf5Mr3DQwcBh;3Okuf#NJwwwG|fO~cDPl!xr|dZxyrFB z_3$2|&SO>W01LLG+E=bX`34_4ISQ-01wAw=g%m=&o;W_>y+I*c(@^AmaHd1wL=>sk z8aU;VIaKu&VH~Xixk$f|Or5@At?|h%AEj{)`+x!Gczi!_7XhoPViQ=Drm^WnZEQ9A z&`B_9uz$onTQp5sA&b(t%DL_x;{7t zCJhxT7X-|dMkeL#3IUQh% z8c;{-ESt6sN7ec@X5?%zkAOLYCKm3RFiJD1s8Q@fYX%61XoqcWf`r1PAZ&^@nb5Jc zu*F&JHLK=b65e6Gz;b|A97*WfxIZynWi!AGk2(Pr&7TIp4J>V|K09|CjpU}sn@Y_- zN7M8SJI!14&QvxFt(85%Y!!#mLC}N(_ff8>;j=78ms@)>PVR=6I;nmifN4l-7-VHD zTiJpPRL$x0bp{%{Gbi;iUoKObItf*N;yz5wJH&z>cq`TEt`Q!5KSnOo^?hhot2~Js(G0+mT)pqzK>3*!p@7Gb)kQdC-(iYsNUOBfoH)AwIQq2zOHRI?; zFdi5>&RD13q-fmJ7)Rilc86+Fr1S;wy3@#Qrs9ivbIy0>2 zV|PJp4YBexBk}QhUQP@%RC9Tzo?%=^%lVT!+U3-iSDqWyrhaid(4w3790rBfUW9R2 zb==kJL~5F5MD6RdwH=)sMfu=`vDGwiznrP+QKHqVb4FofJ4dAi8AHHyiw#jHTb(P` zFleFlHY$Ci-XWm>ju_nm6y()hX0_AM{VXH3Bw@ zNqL%sH{*OG1$*rRkl!YNu%~~ zXh{c@L1Uj{-e#rqrBGbGlttg73J#$z^~M(TFNiO^O(Q>P-CDu=ET=UZ1Ehyfh{1-A zI=z@Vx~RGI+hez~YageODZW-~Gpbk3;wU5qoS5FlLdosZn3o_=N2)>I>ZR=Z4z+@T zCVRxAA%6^0(X$rTAoyK1rm5%a+}bJIVPzpIdLau@k-OWZ97Sk!^J*J?qk0d#=h)nt zw^X}Pghn}1oXXWpI2WgF5$EiwHzos7Lsd*g;B;`zxFTloLowyZvE9`7>26-PZpxT? zB3%M_=JLcG{!ji{k8fBhL48MGh!76qEId8nX%LE8m5SC@O~9NisctsY+_g^g4$*QDz>#(J2u{W#xHfY& z^}LEgSP7fXJd)VfB6Q3Q;U?&GuGZ!Y@du&IVahlsmU z%}IGb+MP~dXx?fHKrJfklfhfTP!cnIw62jnn&`Hou?i(r>kQDS8az5-i=X9j$Tyw$D4O6(L!0ko=$lQuT>Th`7vb1s ze!xnInaUYDLaSdC9;~k=N8%9Jkr(lFIud5F?FFMPp2Ta1vgr~DqRhxsdq59O* z0r2bYi zLNb_3FcX0pi15H2p`Kn&(kn*cm7#Kz_xX|_#^%B!O@O#Pg@?1zI5Lfie%f_4i+L0z z2GjzC20*M?iD;k_}K2GdC* zqc7QD#muYJJ|}c=Yh0{rmOwEcLlO=b_CHciv_W*a25eMjq9WF^rfpZj;(I z1u=FaOb&CAS7cf$n7?ut-a*oXf2z}bK2I)2GNxBG&|G^ZH%XI$I&UD+8{G^L z35i!V>br1E7wvgqQLr7J0nq%|K%zD<;*B0Bo2`>rm_SDH(V7lKxkoIG;=MK${Zlt^ zBs?)6XP>MC?Y7h?B4}oIGRd8DC6hBnoZNC@BQh|6oSRNk>Ss~a8x(UKLf=J=Jvzuy zZY=5v(JpmioC&_oB6tnNua`AKP;h|RM15!8JgaXIIjI*BaoDHcT&v3-8aCH`XF`Y- zug2Q+_9>HktATv{oUImOvoSUqft`A{F!8BYSN2Raa02mk;8 literal 0 HcmV?d00001 diff --git a/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util.exe b/hardware/esl_blaster/FW02/dfu-util-0.9-win64/dfu-util.exe new file mode 100644 index 0000000000000000000000000000000000000000..fff0d39420fac66f0ef8a60ba75969350922b400 GIT binary patch literal 290852 zcmeFad3+RA*7)5WXb4NJs6^rtZ8VGt0ww|u0itQ>U`3ln0*Z=C$O0K5!K9l-9SnB2 zQkIR3<2X7xqvJT6&OFZeIBYVSgeBk_gA3w@sAIK(8N?A0m;Qavt?JIA&hz~Kdf(6c zdHVx(w{y-t_uO;OJ$I?fv@6%S`nX)KzWh%lT&|6T@+(o#|NLm8__#ARALn{KiK8U%p%Mbq!M}9@id!nNqSr) ze`u6@T5EpfXn5z0RPN%+6~c?;aGyzhWr zbE4ZdUIhI;ztO?!6+z0z|CoocC~c=5-GB34Gv|-4st8t)X$h@${1@IL{O|TFam{ZY z-QWODpx`0?OSp#r-G0E8j9zNPsW$GTQ0i>$21K;PRZuc|g$=hy>N~`Lf!oRdZa)RL zps`W1<_(mmTOQx~H3@&UPQ4=QOyH!=FZKk5Ui0WFvt~=~B6)a$lWu-T5?#L%S4s2e z;9^y;f};-<+`cXtiP>^#Y^Wrz`j$Rc?bzQNuAuqcv3A}=9>SRpoYfmHbMm=`MJlsj zH8At}U&H@@eh1u`LX|nFfS{d5oJTlY8q@VFaY1kFIF<2d0nen91@6}GfE)Ki1($g; z!A#&zA>7y-u4MALKa>hxu6GCVSPC3t$<@&tj(W%2{9X4K%A0_Dg7BU1fGZM)s8af? z1Z6mZa2@d7e$tL^$^Sq4|6&Pj)z0vvw4=2%Y$KwF59H~l$FtStD(q-;q0BCl{Ya(~ z1G*=kZ|zp{cr&C{kDqpBa0N)erpUf(xtXyAx;9io2 z&6_d^^w@0BjMqQaAJfg^JY?rLwNhFW-Gb1ob+hkqF$21pa}(0j&86vu2LtBtm(tv> z&g1o>9a>~8aGPXO@g-i-4eOAu{dJ5UZ4T|%&2e+VDLiQQ3m`b5L-`V*=jne!`N9g#@Q@ZpY(3=N2Xp|k&4bP?{BF_Hw zaqy%g{@i))jWV}s(NB09o~Le-(&4WhaJfoji*w!6Di4;meAp*o#I5Ek@}eK;#&$a8 zF#xo+SD~zhZ|dgYcdf~k>anG6-T1`1N8*P6ZCW|x-7;$l60~rsoJref2icuB)!O_G;fe-_={YK7mz6Y4l)QKhX&-`Vs*2A7kvcKJiu( z4t?Y0MAl0Qmn(k0RU)xY238&etK{4E??WLDUw|I-@rZW8uj}!fqZ=P~mye{W)2oMzn^u7y zEI`YDe!FP-7vCUQl;~V6z)#7clM`77oXi1$%>*IQPGl&E@aDZb{^Js2G0#27yYp?~ z)UL0Kg>qGynNx*`61%~@3d(_)KHs--4^%cQ`CPQXDLmaw7FHs4yKqFZur`(~`~WPw zFoVKP@PPghL!M%K!UqblBPWp_%nm&BzCJA zpl|d@aD;C9bMub zpI>GiwSEn0$(%WVlMF=5AiasX0evF|)?9@Js9=En2ar2=+VmCs<9!>&eSvx5TQ{Dw zemNh^iSu&vH2)458h_O_TWuNpF85uQvbo^{I)m4ENw0ji)OfMXc;0VBavzeKLzq{D ze*vRLH+Gb28xB~H3dvZ;bh3OK-2fGKSkuoXuhPaTE!-v6ethTH!VaI&!l?HfpZMKh zT30};wCF4C&SsDTh-*A#`U~aC-PT|z__Yl$XzMQ@s+%*$ml~FC1arN|Fys9YweDg$u5m1Ho~Z@)cCqgE8V88FQ->78IJ;NS5tXu?0UDQ=S#O}Ytk5V z(<)!}yZ<%K{faZ6>&9W-c*FXw0$DLaTkp@+CwYR4CJhW$nSoq?bXV}LMAi?!gaaG$ zMg_U@HKewbToFvh@9#-U&6|>1`87SIR!Mr(#S~k$#25?_;<)-Z<(6Q5Wd-Js`HMwk z$3ji7e0^GFv-PWyE?3b_xszzmi`t!R5F}D9WU#m4s|XEiVV>PUQv_8hDtG8-wh~